Expand description
Signal-settling / steady-state detection nodes.
SRD-86 §“Causal ordering, the freshness register, and
settling”. An optimizer objective declared over a run-produced
metric (e.g. score := 0 - metric("errors","rate")) is a
volatile wire: its per-cycle value chases the live metric
window, and at phase completion the trailing window is empty so
a naïve post-execution read returns the empty-window value
rather than the level the phase actually produced.
is_stable conditions that volatile wire into a stable
register the phase executor can read after completion. It is a
stateful node — its cross-cycle state (a bounded ring of the
most recent samples) lives in a Mutex<SettleState> setup
field, exactly as fft_analyze carries its window buffer.
Because the state is an internal register and not a global,
every output is a deterministic function of the input history
— the node is fully verifiable in polydat function space by
feeding a sample sequence and asserting the (stable_value, stable) output sequence (see this module’s tests).
Cross-cycle wire reference is not expressible in polydat (a
wire cannot read its own prior value), so the register is held
internally and re-published each cycle as the stable_value
output rather than threaded back in as an input wire.
Structs§
- IsStable
- Condition a per-cycle objective signal into a settled register and a steady-state signal.