pic32mx2xx/pic32mx2xxfxxxd/int/
ipc5set.rs1#[doc = "Register `IPC5SET` reader"]
2pub struct R(crate::R<IPC5SET_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<IPC5SET_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<IPC5SET_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<IPC5SET_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `IPC5SET` writer"]
17pub struct W(crate::W<IPC5SET_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<IPC5SET_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<IPC5SET_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<IPC5SET_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `T5IS` reader - "]
38pub type T5IS_R = crate::FieldReader;
39#[doc = "Field `T5IS` writer - "]
40pub type T5IS_W<'a, const O: u8> = crate::FieldWriter<'a, IPC5SET_SPEC, 2, O>;
41#[doc = "Field `T5IP` reader - "]
42pub type T5IP_R = crate::FieldReader;
43#[doc = "Field `T5IP` writer - "]
44pub type T5IP_W<'a, const O: u8> = crate::FieldWriter<'a, IPC5SET_SPEC, 3, O>;
45#[doc = "Field `IC5IS` reader - "]
46pub type IC5IS_R = crate::FieldReader;
47#[doc = "Field `IC5IS` writer - "]
48pub type IC5IS_W<'a, const O: u8> = crate::FieldWriter<'a, IPC5SET_SPEC, 2, O>;
49#[doc = "Field `IC5IP` reader - "]
50pub type IC5IP_R = crate::FieldReader;
51#[doc = "Field `IC5IP` writer - "]
52pub type IC5IP_W<'a, const O: u8> = crate::FieldWriter<'a, IPC5SET_SPEC, 3, O>;
53#[doc = "Field `OC5IS` reader - "]
54pub type OC5IS_R = crate::FieldReader;
55#[doc = "Field `OC5IS` writer - "]
56pub type OC5IS_W<'a, const O: u8> = crate::FieldWriter<'a, IPC5SET_SPEC, 2, O>;
57#[doc = "Field `OC5IP` reader - "]
58pub type OC5IP_R = crate::FieldReader;
59#[doc = "Field `OC5IP` writer - "]
60pub type OC5IP_W<'a, const O: u8> = crate::FieldWriter<'a, IPC5SET_SPEC, 3, O>;
61#[doc = "Field `AD1IS` reader - "]
62pub type AD1IS_R = crate::FieldReader;
63#[doc = "Field `AD1IS` writer - "]
64pub type AD1IS_W<'a, const O: u8> = crate::FieldWriter<'a, IPC5SET_SPEC, 2, O>;
65#[doc = "Field `AD1IP` reader - "]
66pub type AD1IP_R = crate::FieldReader;
67#[doc = "Field `AD1IP` writer - "]
68pub type AD1IP_W<'a, const O: u8> = crate::FieldWriter<'a, IPC5SET_SPEC, 3, O>;
69impl R {
70 #[doc = "Bits 0:1"]
71 #[inline(always)]
72 pub fn t5is(&self) -> T5IS_R {
73 T5IS_R::new((self.bits & 3) as u8)
74 }
75 #[doc = "Bits 2:4"]
76 #[inline(always)]
77 pub fn t5ip(&self) -> T5IP_R {
78 T5IP_R::new(((self.bits >> 2) & 7) as u8)
79 }
80 #[doc = "Bits 8:9"]
81 #[inline(always)]
82 pub fn ic5is(&self) -> IC5IS_R {
83 IC5IS_R::new(((self.bits >> 8) & 3) as u8)
84 }
85 #[doc = "Bits 10:12"]
86 #[inline(always)]
87 pub fn ic5ip(&self) -> IC5IP_R {
88 IC5IP_R::new(((self.bits >> 10) & 7) as u8)
89 }
90 #[doc = "Bits 16:17"]
91 #[inline(always)]
92 pub fn oc5is(&self) -> OC5IS_R {
93 OC5IS_R::new(((self.bits >> 16) & 3) as u8)
94 }
95 #[doc = "Bits 18:20"]
96 #[inline(always)]
97 pub fn oc5ip(&self) -> OC5IP_R {
98 OC5IP_R::new(((self.bits >> 18) & 7) as u8)
99 }
100 #[doc = "Bits 24:25"]
101 #[inline(always)]
102 pub fn ad1is(&self) -> AD1IS_R {
103 AD1IS_R::new(((self.bits >> 24) & 3) as u8)
104 }
105 #[doc = "Bits 26:28"]
106 #[inline(always)]
107 pub fn ad1ip(&self) -> AD1IP_R {
108 AD1IP_R::new(((self.bits >> 26) & 7) as u8)
109 }
110}
111impl W {
112 #[doc = "Bits 0:1"]
113 #[inline(always)]
114 #[must_use]
115 pub fn t5is(&mut self) -> T5IS_W<0> {
116 T5IS_W::new(self)
117 }
118 #[doc = "Bits 2:4"]
119 #[inline(always)]
120 #[must_use]
121 pub fn t5ip(&mut self) -> T5IP_W<2> {
122 T5IP_W::new(self)
123 }
124 #[doc = "Bits 8:9"]
125 #[inline(always)]
126 #[must_use]
127 pub fn ic5is(&mut self) -> IC5IS_W<8> {
128 IC5IS_W::new(self)
129 }
130 #[doc = "Bits 10:12"]
131 #[inline(always)]
132 #[must_use]
133 pub fn ic5ip(&mut self) -> IC5IP_W<10> {
134 IC5IP_W::new(self)
135 }
136 #[doc = "Bits 16:17"]
137 #[inline(always)]
138 #[must_use]
139 pub fn oc5is(&mut self) -> OC5IS_W<16> {
140 OC5IS_W::new(self)
141 }
142 #[doc = "Bits 18:20"]
143 #[inline(always)]
144 #[must_use]
145 pub fn oc5ip(&mut self) -> OC5IP_W<18> {
146 OC5IP_W::new(self)
147 }
148 #[doc = "Bits 24:25"]
149 #[inline(always)]
150 #[must_use]
151 pub fn ad1is(&mut self) -> AD1IS_W<24> {
152 AD1IS_W::new(self)
153 }
154 #[doc = "Bits 26:28"]
155 #[inline(always)]
156 #[must_use]
157 pub fn ad1ip(&mut self) -> AD1IP_W<26> {
158 AD1IP_W::new(self)
159 }
160 #[doc = "Writes raw bits to the register."]
161 #[inline(always)]
162 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
163 self.0.bits(bits);
164 self
165 }
166}
167#[doc = "IPC5SET register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ipc5set](index.html) module"]
168pub struct IPC5SET_SPEC;
169impl crate::RegisterSpec for IPC5SET_SPEC {
170 type Ux = u32;
171}
172#[doc = "`read()` method returns [ipc5set::R](R) reader structure"]
173impl crate::Readable for IPC5SET_SPEC {
174 type Reader = R;
175}
176#[doc = "`write(|w| ..)` method takes [ipc5set::W](W) writer structure"]
177impl crate::Writable for IPC5SET_SPEC {
178 type Writer = W;
179 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
180 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
181}
182#[doc = "`reset()` method sets IPC5SET to value 0"]
183impl crate::Resettable for IPC5SET_SPEC {
184 const RESET_VALUE: Self::Ux = 0;
185}