1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
//! General Purpose Input / Output
use core::marker::PhantomData;
/// Extension trait to split a GPIO peripheral in independent pins and registers
pub trait GpioExt {
/// The to split the GPIO into
type Parts;
/// Splits the GPIO block into independent pins and registers
fn split(self) -> Self::Parts;
}
/// Input mode (type state)
pub struct Input<MODE> {
_mode: PhantomData<MODE>,
}
/// Analog input (type state)
pub struct Analog;
/// Floating input (type state)
pub struct Floating;
/// Pulled down input (type state)
pub struct PullDown;
/// Pulled up input (type state)
pub struct PullUp;
/// Output mode (type state)
pub struct Output<MODE> {
_mode: PhantomData<MODE>,
}
/// Push pull output (type state)
pub struct PushPull;
/// Open drain output (type state)
pub struct OpenDrain;
macro_rules! port {
($PORTX:ident, $portx:ident, [
$($PXi:ident: ($pxi:ident, $i:expr, $MODE:ty $(, $has_ansel:expr)?),)+
]) => {
/// GPIO
pub mod $portx {
use core::marker::PhantomData;
use core::convert::Infallible;
use embedded_hal_0_2::digital::v2 as eh02;
use embedded_hal::digital as eh;
use crate::pac::$PORTX;
#[allow(unused_imports)]
use super::Analog;
use super::{
Floating, GpioExt, Input, OpenDrain, Output,
PullDown, PullUp, PushPull,
};
/// GPIO parts
pub struct Parts {
$(
/// Pin
pub $pxi: $PXi<$MODE>,
)+
}
impl GpioExt for $PORTX {
type Parts = Parts;
fn split(self) -> Parts {
Parts {
$(
$pxi: $PXi { _mode: PhantomData },
)+
}
}
}
$(
/// Pin
pub struct $PXi<MODE> {
_mode: PhantomData<MODE>,
}
impl<MODE> $PXi<MODE> {
/// Configures the pin to operate as a floating input pin
pub fn into_floating_input(
self,
) -> $PXi<Input<Floating>> {
unsafe {
$(
_ = $has_ansel; // dummy statement to satisfy macro processor
(*$PORTX::ptr()).anselclr.write(|w| w.bits(1 << $i));
)?
(*$PORTX::ptr()).trisset.write(|w| w.bits(1 << $i));
(*$PORTX::ptr()).cnpuclr.write(|w| w.bits(1 << $i));
(*$PORTX::ptr()).cnpdclr.write(|w| w.bits(1 << $i));
}
$PXi { _mode: PhantomData }
}
/// Configures the pin to operate as a pulled down input pin
pub fn into_pull_down_input(
self,
) -> $PXi<Input<PullDown>> {
unsafe {
$(
_ = $has_ansel; // dummy statement to satisfy macro processor
(*$PORTX::ptr()).anselclr.write(|w| w.bits(1 << $i));
)?
(*$PORTX::ptr()).trisset.write(|w| w.bits(1 << $i));
(*$PORTX::ptr()).cnpuclr.write(|w| w.bits(1 << $i));
(*$PORTX::ptr()).cnpdset.write(|w| w.bits(1 << $i));
}
$PXi { _mode: PhantomData }
}
/// Configures the pin to operate as a pulled up input pin
pub fn into_pull_up_input(
self,
) -> $PXi<Input<PullUp>> {
unsafe {
$(
_ = $has_ansel; // dummy statement to satisfy macro processor
(*$PORTX::ptr()).anselclr.write(|w| w.bits(1 << $i));
)?
(*$PORTX::ptr()).trisset.write(|w| w.bits(1 << $i));
(*$PORTX::ptr()).cnpuset.write(|w| w.bits(1 << $i));
(*$PORTX::ptr()).cnpdclr.write(|w| w.bits(1 << $i));
}
$PXi { _mode: PhantomData }
}
/// Configures the pin to operate as an open drain output pin
pub fn into_open_drain_output(
self,
) -> $PXi<Output<OpenDrain>> {
unsafe {
$(
_ = $has_ansel; // dummy statement to satisfy macro processor
(*$PORTX::ptr()).anselclr.write(|w| w.bits(1 << $i));
)?
(*$PORTX::ptr()).trisclr.write(|w| w.bits(1 << $i));
(*$PORTX::ptr()).odcset.write(|w| w.bits(1 << $i));
(*$PORTX::ptr()).cnpuclr.write(|w| w.bits(1 << $i));
(*$PORTX::ptr()).cnpdclr.write(|w| w.bits(1 << $i));
}
$PXi { _mode: PhantomData }
}
/// Configures the pin to operate as an push pull output pin
pub fn into_push_pull_output(
self,
) -> $PXi<Output<PushPull>> {
unsafe {
$(
_ = $has_ansel; // dummy statement to satisfy macro processor
(*$PORTX::ptr()).anselclr.write(|w| w.bits(1 << $i));
)?
(*$PORTX::ptr()).trisclr.write(|w| w.bits(1 << $i));
(*$PORTX::ptr()).odcclr.write(|w| w.bits(1 << $i));
(*$PORTX::ptr()).cnpuclr.write(|w| w.bits(1 << $i));
(*$PORTX::ptr()).cnpdclr.write(|w| w.bits(1 << $i));
}
$PXi { _mode: PhantomData }
}
$(
/// Configures the pin to operate as an analog input pin
pub fn into_analog_input(
self,
) -> $PXi<Input<Analog>> {
_ = $has_ansel; // dummy statement to satisfy macro processor
unsafe {
(*$PORTX::ptr()).anselset.write(|w| w.bits(1 << $i));
(*$PORTX::ptr()).trisset.write(|w| w.bits(1 << $i));
(*$PORTX::ptr()).cnpuclr.write(|w| w.bits(1 << $i));
(*$PORTX::ptr()).cnpdclr.write(|w| w.bits(1 << $i));
}
$PXi { _mode: PhantomData }
}
)?
}
impl $PXi<Output<OpenDrain>> {
/// Enables / disables the internal pull up
pub fn internal_pull_up(&mut self, on: bool) {
unsafe {
if on {
(*$PORTX::ptr()).cnpuset.write(|w| w.bits(1 << $i));
} else {
(*$PORTX::ptr()).cnpuclr.write(|w| w.bits(1 << $i));
}
}
}
}
impl<MODE> eh02::OutputPin for $PXi<Output<MODE>> {
type Error = ();
fn set_high(&mut self) -> Result<(), Self::Error> {
// NOTE(unsafe) atomic write to a stateless register
unsafe { (*$PORTX::ptr()).latset.write(|w| w.bits(1 << $i)) }
Ok(())
}
fn set_low(&mut self) -> Result<(), Self::Error>{
// NOTE(unsafe) atomic write to a stateless register
unsafe { (*$PORTX::ptr()).latclr.write(|w| w.bits(1 << $i)) }
Ok(())
}
}
impl<MODE> eh02::StatefulOutputPin for $PXi<Output<MODE>> {
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(unsafe { (*$PORTX::ptr()).lat.read().bits() & (1 << $i) != 0 })
}
fn is_set_low(&self) -> Result<bool, Self::Error> {
Ok(unsafe { (*$PORTX::ptr()).lat.read().bits() & (1 << $i) == 0 })
}
}
impl<MODE> eh02::ToggleableOutputPin for $PXi<Output<MODE>> {
type Error = ();
fn toggle(&mut self) -> Result<(), Self::Error> {
unsafe { (*$PORTX::ptr()).latinv.write(|w| w.bits(1 << $i)) };
Ok(())
}
}
impl<MODE> eh02::InputPin for $PXi<Input<MODE>> {
type Error = ();
fn is_high(&self) -> Result<bool, Self::Error> {
Ok(unsafe { (*$PORTX::ptr()).port.read().bits() & (1 << $i) != 0 })
}
fn is_low(&self) -> Result<bool, Self::Error> {
Ok(unsafe { (*$PORTX::ptr()).port.read().bits() & (1 << $i) == 0 })
}
}
impl eh02::InputPin for $PXi<Output<OpenDrain>> {
type Error = ();
fn is_high(&self) -> Result<bool, Self::Error> {
Ok(unsafe { (*$PORTX::ptr()).port.read().bits() & (1 << $i) != 0 })
}
fn is_low(&self) -> Result<bool, Self::Error> {
Ok(unsafe { (*$PORTX::ptr()).port.read().bits() & (1 << $i) == 0 })
}
}
impl<MODE> eh::ErrorType for $PXi<MODE> {
type Error = Infallible;
}
impl<MODE> eh::InputPin for $PXi<Input<MODE>> {
fn is_high(&mut self) -> Result<bool, Self::Error> {
Ok(unsafe { (*$PORTX::ptr()).port.read().bits() & (1 << $i) != 0 })
}
fn is_low(&mut self) -> Result<bool, Self::Error> {
Ok(unsafe { (*$PORTX::ptr()).port.read().bits() & (1 << $i) == 0 })
}
}
impl eh::InputPin for $PXi<Output<OpenDrain>> {
fn is_high(&mut self) -> Result<bool, Self::Error> {
Ok(unsafe { (*$PORTX::ptr()).port.read().bits() & (1 << $i) != 0 })
}
fn is_low(&mut self) -> Result<bool, Self::Error> {
Ok(unsafe { (*$PORTX::ptr()).port.read().bits() & (1 << $i) == 0 })
}
}
impl<MODE> eh::OutputPin for $PXi<Output<MODE>> {
fn set_low(&mut self) -> Result<(), Self::Error> {
unsafe { (*$PORTX::ptr()).latclr.write(|w| w.bits(1 << $i)) }
Ok(())
}
fn set_high(&mut self) -> Result<(), Self::Error> {
unsafe { (*$PORTX::ptr()).latset.write(|w| w.bits(1 << $i)) }
Ok(())
}
}
impl<MODE> eh::StatefulOutputPin for $PXi<Output<MODE>> {
fn is_set_high(&mut self) -> Result<bool, Self::Error> {
Ok(unsafe { (*$PORTX::ptr()).lat.read().bits() & (1 << $i) != 0 })
}
fn is_set_low(&mut self) -> Result<bool, Self::Error> {
Ok(unsafe { (*$PORTX::ptr()).lat.read().bits() & (1 << $i) == 0 })
}
fn toggle(&mut self) -> Result<(), Self::Error> {
unsafe { (*$PORTX::ptr()).latinv.write(|w| w.bits(1 << $i)) };
Ok(())
}
}
)+
}
}
}
include!("gpio_tables.rs");