philbin 1.0.1

A pure Rust AEGIS library with SIMD and runtime CPU detection
Documentation 
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Returns true if the current CPU supports the necessary instruction sets
for this crate to provide hardware-accelerated AEGIS. If false, a slower
pure-software AEGIS implementation will be used instead.

Don't lose sleep over the slower fallback path. Effectively _all_ desktop and
mobile CPUs manufactured since ~2014 support AES hardware acceleration. (See
separate section below.)

Further, on every CPU where a pure-software AEGIS would be used, AES[^1] would
use an _even slower_ fallback path.

[^1]: AES is used to encrypt _the vast majority_ of all HTTPS sessions.

# Which CPUs support hardware accelerated AEGIS?

Philbin uses _runtime_ CPU feature detection to decide whether to use one
of the hardware accelerated codepaths or the software-only fallback path.

(The AEGIS cipher internally uses AES rounds to benefit from dedicated AES CPU
instructions.)

Currently, Philbin provides hardware accelerated codepaths for:

- [x86-64] CPUs with at least [SSE2] and [AES-NI] instructions.
  - This covers **effectively every x86-64 CPU sold since ~2014**, including
    low-power ones like Intel's N100.
  - x86-64 CPUs that support [AVX] will still use 128-bit SIMD, but will take
    advantage of [VEX]-encoded instructions for better performance.
  - x86-64 CPUs that support [VAES] will use an even faster 256-bit SIMD
    codepath. _Various CPUs support VAES without supporting the rest of
    AVX-512!_
  - x86-64 CPUs that support [AVX-512] and VAES will use the fastest
    512-bit SIMD codepath.
- 64-bit [ARM] ([AArch64]) CPUs with the "[Armv8.0 Cryptographic
  Extension][arm-crypto]".
  - Since Android mandates hardware encryption for device
    storage and iOS always ships it, effectively all mobile chips have
    hardware AES support. This includes _all_ Apple A-series and M-series
    chips ("[Apple silicon][apple]"); Qualcomm Snapdragon's from ~2014 onwards;
    Samsung Exynos's from ~2014 onwards; etc.
  - Raspberry Pi 5 (which uses Broadcom's BCM2712) _does_ implement the
    crypto extension, but versions <=4 _do not_.
  - ARM mandates [NEON] support (which Philbin needs) for [AArch64], so only
    the crypto extension may be missing.

[x86-64]: https://en.wikipedia.org/wiki/X86-64
[arm]: https://en.wikipedia.org/wiki/ARM_architecture_family
[arm-crypto]: https://developer.arm.com/documentation/ddi0487/mb/-Part-C-The-AArch64-Instruction-Set/-Chapter-C3-A64-Instruction-Set-Overview/-C3-8-Data-processing---SIMD-and-floating-point/-C3-8-30-The-Cryptographic-Extension-in-AArch64-state
[aarch64]: https://en.wikipedia.org/wiki/AArch64
[sse2]: https://en.wikipedia.org/wiki/SSE2
[avx]: https://en.wikipedia.org/wiki/Advanced_Vector_Extensions
[vex]: https://en.wikipedia.org/wiki/VEX_prefix
[aes-ni]: https://en.wikipedia.org/wiki/AES_instruction_set#x86_architecture_processors
[vaes]: https://en.wikipedia.org/wiki/AVX-512#VAES
[avx-512]: https://en.wikipedia.org/wiki/AVX-512
[apple]: https://en.wikipedia.org/wiki/Apple_silicon
[neon]: https://en.wikipedia.org/wiki/ARM_architecture_family#Advanced_SIMD_(Neon)