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# PCF8563
Real-time clock/calendar
Rev. 11 - 26 October 2015
Product data sheet
## 1. General description
The PCF8563 is a CMOS ${ }^{1}$ Real-Time Clock (RTC) and calendar optimized for low power consumption. A programmable clock output, interrupt output, and voltage-low detector are also provided. All addresses and data are transferred serially via a two-line bidirectional $I^{2} \mathrm{C}$-bus. Maximum bus speed is $400 \mathrm{kbit} / \mathrm{s}$. The register address is incremented automatically after each written or read data byte.
## 2. Features and benefits
- Provides year, month, day, weekday, hours, minutes, and seconds based on a 32.768 kHz quartz crystal
- Century flag
- Clock operating voltage: 1.0 V to 5.5 V at room temperature
- Low backup current; typical $0.25 \mu \mathrm{~A}$ at $\mathrm{V}_{\mathrm{DD}}=3.0 \mathrm{~V}$ and $\mathrm{T}_{\mathrm{amb}}=25^{\circ} \mathrm{C}$
- 400 kHz two-wire $I^{2} \mathrm{C}$-bus interface (at $\mathrm{V}_{\mathrm{DD}}=1.8 \mathrm{~V}$ to 5.5 V )
- Programmable clock output for peripheral devices ( 32.768 kHz, 1.024 kHz, 32 Hz , and 1 Hz )
- Alarm and timer functions
- Integrated oscillator capacitor
- Internal Power-On Reset (POR)
- I²C-bus slave address: read A3h and write A2h
- Open-drain interrupt pin
## 3. Applications
- Mobile telephones
- Portable instruments
- Electronic metering
- Battery powered products
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 18.
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# 4. Ordering information
Table 1. Ordering information
| Type number | Package | | |
| :--: | :--: | :--: | :--: |
| | Name | Description | Version |
| PCF8563BS/4 | HVSON10 | plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body $3 \times 3 \times 0.85 \mathrm{~mm}$ | SOT650-1 |
| PCF8563T/5 | SO8 | plastic small outline package; 8 leads; body width 3.9 mm | SOT96-1 |
| PCF8563T/F4[1] | SO8 | plastic small outline package; 8 leads; body width 3.9 mm | SOT96-1 |
| PCF8563TS/4[2] | TSSOP8 | plastic thin shrink small outline package; 8 leads; body width 3 mm | SOT505-1 |
| PCF8563TS/5 | TSSOP8 | plastic thin shrink small outline package; 8 leads; body width 3 mm | SOT505-1 |
[1] Not recommended for new designs. Replacement part is PCF8563T/5.
[2] Not recommended for new designs. Replacement part is PCF8563TS/5.
## 5. Marking
Table 2. Marking codes
| Type number | Marking code |
| :-- | :-- |
| PCF8563BS/4 | 8563 S |
| PCF8563T/5 | PCF8563 |
| PCF8563T/F4 | 8563 T |
| PCF8563TS/4 | 8563 |
| PCF8563TS/5 | P8563 |
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# 6. Block diagram
(1) $\mathrm{C}_{\text {OSCO }}$; values see Table 30.
Fig 1. Block diagram of PCF8563
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# 7. Pinning information
### 7.1 Pinning
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# 7.2 Pin description
Table 3. Pin description
| Symbol | Pin | | Description |
| :-- | :-- | :-- | :-- |
| | SO8, TSSOP8 | HVSON10 | |
| OSCI | 1 | 1 | oscillator input |
| OSCO | 2 | 2 | oscillator output |
| INT | 3 | 4 | interrupt output (open-drain; active LOW) |
| $\mathrm{V}_{\mathrm{SS}}$ | 4 | $5[1]$ | ground |
| SDA | 5 | 6 | serial data input and output |
| SCL | 6 | 7 | serial clock input |
| CLKOUT | 7 | 8 | clock output, open-drain |
| $\mathrm{V}_{\mathrm{DD}}$ | 8 | 9 | supply voltage |
| n.c. | - | 3,10 | not connected; do not connect and do not <br> use as feed through |
[1] The die paddle (exposed pad) is connected to $\mathrm{V}_{\mathrm{SS}}$ through high ohmic (non-conductive) silicon attach and should be electrically isolated. It is good engineering practice to solder the exposed pad to an electrically isolated PCB copper pad for better heat transfer but it is not required as the RTC doesn't consume much power. In no case should traces be run under the package exposed pad.
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# 8. Functional description
The PCF8563 contains sixteen 8-bit registers with an auto-incrementing register address, an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which provides the source clock for the Real-Time Clock (RTC) and calender, a programmable clock output, a timer, an alarm, a voltage-low detector, and a $400 \mathrm{kHz} \mathrm{I}^{2} \mathrm{C}$-bus interface.
All 16 registers are designed as addressable 8-bit parallel registers although not all bits are implemented. The first two registers (memory address 00 h and 01 h ) are used as control and/or status registers. The memory addresses 02 h through 08 h are used as counters for the clock function (seconds up to years counters). Address locations 09h through 0 Ch contain alarm registers which define the conditions for an alarm. Address 0 Dh controls the CLKOUT output frequency. 0Eh and 0Fh are the Timer_control and Timer registers, respectively.
The Seconds, Minutes, Hours, Days, Months, Years as well as the Minute_alarm, Hour_alarm, and Day_alarm registers are all coded in Binary Coded Decimal (BCD) format.
When one of the RTC registers is written or read, the contents of all time counters are frozen. Therefore, faulty writing or reading of the clock and calendar during a carry condition is prevented.
### 8.1 CLKOUT output
A programmable square wave is available at the CLKOUT pin. Operation is controlled by the register CLKOUT_control at address 0Dh. Frequencies of 32.768 kHz (default), $1.024 \mathrm{kHz}, 32 \mathrm{~Hz}$, and 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain output and enabled at power-on. If disabled it becomes high-impedance.
### 8.2 Register organization
Table 4. Formatted registers overview
Bit positions labelled as $x$ are not relevant. Bit positions labelled with $N$ should always be written with logic 0; if read they could be either logic 0 or logic 1. After reset, all registers are set according to Table 27.
| Address | Register name | Bit | | | | | | | |
| :--: | :--: | :--: | :--: | :--: | :--: | :--: | :--: | :--: | :--: |
| | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Control and status registers | | | | | | | | | |
| 00h | Control_status_1 | TEST1 | N | STOP | N | TESTC | N | N | N |
| 01h | Control_status_2 | N | N | N | TI_TP | AF | TF | AIE | TIE |
| Time and date registers | | | | | | | | | |
| 02h | VL_seconds | VL | SECONDS (0 to 59) | | | | | | |
| 03h | Minutes | $x$ | MINUTES (0 to 59) | | | | | | |
| 04h | Hours | $x$ | $x$ | HOURS (0 to 23) | | | | | |
| 05h | Days | $x$ | $x$ | DAYS (1 to 31) | | | | | |
| 06h | Weekdays | $x$ | $x$ | $x$ | $x$ | $x$ | WEEKDAYS (0 to 6) | | |
| 07h | Century_months | C | $x$ | $x$ | MONTHS (1 to 12) | | | | |
| 08h | Years | YEARS (0 to 99) | | | | | | | |
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Table 4. Formatted registers overview ...continued
Bit positions labelled as $x$ are not relevant. Bit positions labelled with $N$ should always be written with logic 0 ; if read they could be either logic 0 or logic 1. After reset, all registers are set according to Table 27.
| Address | Register name | Bit | | | | | | | |
| :--: | :--: | :--: | :--: | :--: | :--: | :--: | :--: | :--: | :--: |
| | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Alarm registers | | | | | | | | | |
| 09h | Minute_alarm | | AE_M | MINUTE_ALARM (0 to 59) | | | | | |
| 0Ah | Hour_alarm | | AE_H | $x$ | HOUR_ALARM (0 to 23) | | | | |
| 0Bh | Day_alarm | | AE_D | $x$ | DAY_ALARM (1 to 31) | | | | |
| 0Ch | Weekday_alarm | | AE_W | $x$ | $x$ | $x$ | $x$ | WEEKDAY_ALARM (0 to 6) | |
| CLKOUT control register | | | | | | | | | |
| 0 Dh | CLKOUT_control | | FE | $x$ | $x$ | $x$ | $x$ | $x$ | FD[1:0] |
| Timer registers | | | | | | | | | |
| 0Eh | Timer_control | | TE | $x$ | $x$ | $x$ | $x$ | $x$ | TD[1:0] |
| 0Fh | Timer | | TIMER[7:0] | | | | | | |
# 8.3 Control registers
### 8.3.1 Register Control_status_1
Table 5. Control_status_1 - control and status register 1 (address 00h) bit description
| Bit | Symbol | Value | Description | Reference |
| :--: | :--: | :--: | :--: | :--: |
| 7 | TEST1 | 000 | normal mode <br> must be set to logic 0 during normal operations | Section 8.9 |
| | | 1 | EXT_CLK test mode | |
| 6 | N | 000 | unused | |
| 5 | STOP | 000 | RTC source clock runs | Section 8.10 |
| | | 1 | all RTC divider chain flip-flops are asynchronously set to logic 0 ; the RTC clock is stopped (CLKOUT at 32.768 kHz is still available) | |
| 4 | N | 000 | unused | |
| 3 | TESTC | 0 | Power-On Reset (POR) override facility is disabled; set to logic 0 for normal operation | Section 8.11.1 |
| | | 100 | Power-On Reset (POR) override may be enabled | |
| 2 to 0 | N | 00000 | unused | |
[1] Default value.
[2] Bits labeled as N should always be written with logic 0 .
### 8.3.2 Register Control_status_2
Table 6. Control_status_2 - control and status register 2 (address 01h) bit description
| Bit | Symbol | Value | Description | Reference |
| :--: | :--: | :--: | :--: | :--: |
| 7 to 5 | N | 00000 | unused | |
| 4 | TI_TP | 000 | $\overline{\text { INT }}$ is active when TF is active (subject to the status of TIE) | Section 8.3.2.1 <br> and <br> Section 8.8 |
| | | 1 | $\overline{\text { INT }}$ pulses active according to Table 7 (subject to the status of TIE); <br> Remark: note that if AF and AIE are active then $\overline{\text { INT }}$ will be permanently active | |
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Table 6. Control_status_2 - control and status register 2 (address 01 h ) bit description ...continued
| Bit | Symbol | Value | Description | Reference |
| :--: | :--: | :--: | :--: | :--: |
| 3 | AF | $0 \square$ | read: alarm flag inactive | Section 8.3.2.1 |
| | | | write: alarm flag is cleared | |
| | | 1 | read: alarm flag active | |
| | | | write: alarm flag remains unchanged | |
| 2 | TF | $0 \square$ | read: timer flag inactive | |
| | | | write: timer flag is cleared | |
| | | 1 | read: timer flag active | |
| | | | write: timer flag remains unchanged | |
| 1 | AIE | $0 \square$ | alarm interrupt disabled | |
| | | 1 | alarm interrupt enabled | |
| 0 | TIE | $0 \square$ | timer interrupt disabled | |
| | | 1 | timer interrupt enabled | |
[1] Bits labeled as N should always be written with logic 0 .
[2] Default value.
# 8.3.2.1 Interrupt output
Bits TF and AF: When an alarm occurs, AF is set to logic 1. Similarly, at the end of a timer countdown, TF is set to logic 1. These bits maintain their value until overwritten using the interface. If both timer and alarm interrupts are required in the application, the source of the interrupt can be determined by reading these bits. To prevent one flag being overwritten while clearing another, a logic AND is performed during a write access.
When bits TIE and AIE are disabled, pin $\overline{\mathrm{INT}}$ will remain high-impedance.
Fig 5. Interrupt scheme
Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when TF or AF is asserted, respectively. The interrupt is the logical OR of these two conditions when both AIE and TIE are set.
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Countdown timer interrupts: The pulse generator for the countdown timer interrupt uses an internal clock and is dependent on the selected source clock for the countdown timer and on the countdown value $n$. As a consequence, the width of the interrupt pulse varies (see Table 7).
Table 7. $\overline{\text { INT }}$ operation (bit TI_TP $=1$ )[1]
| Source clock $(\mathrm{Hz})$ | $\overline{\text { INT }}$ period (s) | |
| :-- | :-- | :-- |
| | $\mathbf{n}=\mathbf{1}^{[2]}$ | $\mathbf{n} \boldsymbol{> 1}^{[2]}$ |
| 4096 | $1 / 8192$ | $1 / 4096$ |
| 64 | $1 / 128$ | $1 / 64$ |
| 1 | $1 / 64$ | $1 / 64$ |
| $1 / 60$ | $1 / 64$ | $1 / 64$ |
[1] TF and $\overline{\text { INT }}$ become active simultaneously.
[2] $\mathrm{n}=$ loaded countdown value. Timer stops when $\mathrm{n}=0$.
# 8.4 Time and date registers
The majority of the registers are coded in the BCD format to simplify application use.
### 8.4.1 Register VL_seconds
Table 8. VL_seconds - seconds and clock integrity status register (address 02h) bit description
| Bit | Symbol | Value | Place value | Description |
| :-- | :-- | :-- | :-- | :-- |
| 7 | VL | 0 | - | clock integrity is guaranteed |
| | | $1[1]$ | - | integrity of the clock information is not guaranteed |
| 6 to 4 | SECONDS | 0 to 5 | ten's place | actual seconds coded in BCD format, see Table 9 |
| 3 to 0 | | 0 to 9 | unit place | |
[1] Start-up value.
Table 9. Seconds coded in BCD format
| Seconds value <br> (decimal) | Upper-digit (ten's place) | | | Digit (unit place) | | | |
| :-- | :-- | :-- | :-- | :-- | :-- | :-- | :-- |
| | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| 00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 01 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| 02 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| $\vdots$ | $\vdots$ | $\vdots$ | $\vdots$ | $\vdots$ | $\vdots$ | $\vdots$ | $\vdots$ |
| 09 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| 10 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| $\vdots$ | $\vdots$ | $\vdots$ | $\vdots$ | $\vdots$ | $\vdots$ | $\vdots$ | $\vdots$ |
| 58 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| 59 | 1 | 0 | 1 | 1 | 0 | 0 | 1 |
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# 8.4.1.1 Voltage-low detector and clock monitor
The PCF8563 has an on-chip voltage-low detector (see Figure 6). When $\mathrm{V}_{\mathrm{DD}}$ drops below $\mathrm{V}_{\text {low }}$, bit VL in the VL_seconds register is set to indicate that the integrity of the clock information is no longer guaranteed. The VL flag can only be cleared by using the interface.
Fig 6. Voltage-low detection
The VL flag is intended to detect the situation when $\mathrm{V}_{\mathrm{DD}}$ is decreasing slowly, for example under battery operation. Should the oscillator stop or $\mathrm{V}_{\mathrm{DD}}$ reach $\mathrm{V}_{\text {low }}$ before power is re-asserted, then the VL flag is set. This will indicate that the time may be corrupted.
### 8.4.2 Register Minutes
Table 10. Minutes - minutes register (address 03h) bit description
| Bit | Symbol | Value | Place value | Description |
| :-- | :-- | :-- | :-- | :-- |
| 7 | - | - | - | unused |
| 6 to 4 | MINUTES | 0 to 5 | ten's place | actual minutes coded in BCD format |
| 3 to 0 | | 0 to 9 | unit place | |
### 8.4.3 Register Hours
Table 11. Hours - hours register (address 04h) bit description
| Bit | Symbol | Value | Place value | Description |
| :-- | :-- | :-- | :-- | :-- |
| 7 to 6 | - | - | - | unused |
| 5 to 4 | HOURS | 0 to 2 | ten's place | actual hours coded in BCD format |
| 3 to 0 | | 0 to 9 | unit place | |
### 8.4.4 Register Days
Table 12. Days - days register (address 05h) bit description
| Bit | Symbol | Value | Place value | Description |
| :-- | :-- | :-- | :-- | :-- |
| 7 to 6 | - | - | - | unused |
| 5 to 4 | DAYS $[$ ] | 0 to 3 | ten's place | actual day coded in BCD format |
| 3 to 0 | | 0 to 9 | unit place | |
[1] The PCF8563 compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4 , including the year 00 .
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# 8.4.5 Register Weekdays
Table 13. Weekdays - weekdays register (address 06h) bit description
| Bit | Symbol | Value | Description |
| :-- | :-- | :-- | :-- |
| 7 to 3 | - | - | unused |
| 2 to 0 | WEEKDAYS | 0 to 6 | actual weekday values, see Table 14 |
Table 14. Weekday assignments
| Day $!1]$ | Bit | | |
| :-- | :-- | :-- | :-- |
| | 2 | 1 | 0 |
| Sunday | 0 | 0 | 0 |
| Monday | 0 | 0 | 1 |
| Tuesday | 0 | 1 | 0 |
| Wednesday | 0 | 1 | 1 |
| Thursday | 1 | 0 | 0 |
| Friday | 1 | 0 | 1 |
| Saturday | 1 | 1 | 0 |
[1] Definition may be re-assigned by the user.
### 8.4.6 Register Century_months
Table 15. Century_months - century flag and months register (address 07h) bit description
| Bit | Symbol | Value | Place value | Description |
| :-- | :-- | :-- | :-- | :-- |
| 7 | C! | 0 | - | indicates the century is $x$ |
| | | 1 | - | indicates the century is $x+1$ |
| 6 to 5 | - | - | - | unused |
| 4 | MONTHS | 0 to 1 | ten's place | actual month coded in BCD format, see Table 16 |
| 3 to 0 | | 0 to 9 | unit place | |
[1] This bit may be re-assigned by the user.
[2] This bit is toggled when the register Years overflows from 99 to 00.
Table 16. Month assignments in BCD format
| Month | Upper-digit <br> (ten's place) | Digit (unit place) | | | |
| :-- | :-- | :-- | :-- | :-- | :-- |
| | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| January | 0 | 0 | 0 | 0 | 1 |
| February | 0 | 0 | 0 | 1 | 0 |
| March | 0 | 0 | 0 | 1 | 1 |
| April | 0 | 0 | 1 | 0 | 0 |
| May | 0 | 0 | 1 | 0 | 1 |
| June | 0 | 0 | 1 | 1 | 0 |
| July | 0 | 0 | 1 | 1 | 1 |
| August | 0 | 1 | 0 | 0 | 0 |
| September | 0 | 1 | 0 | 0 | 1 |
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Table 16. Month assignments ...continuedin BCD format
| Month | Upper-digit <br> (ten's place) | Digit (unit place) | | | |
| :-- | :-- | :-- | :-- | :-- | :-- |
| | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| October | 1 | 0 | 0 | 0 | 0 |
| November | 1 | 0 | 0 | 0 | 1 |
| December | 1 | 0 | 0 | 1 | 0 |
# 8.4.7 Register Years
Table 17. Years - years register (08h) bit description
| Bit | Symbol | Value | Place value | Description |
| :-- | :-- | :-- | :-- | :-- |
| 7 to 4 | YEARS | 0 to 9 | ten's place | actual year coded in BCD format[1] |
| 3 to 0 | | 0 to 9 | unit place | |
[1] When the register Years overflows from 99 to 00, the century bit C in the register Century_months is toggled.
### 8.5 Setting and reading the time
Figure 7 shows the data flow and data dependencies starting from the 1 Hz clock tick.
Fig 7. Data flow for the time function
During read/write operations, the time counting circuits (memory locations 02h through 08 h ) are blocked.
This prevents
- Faulty reading of the clock and calendar during a carry condition
- Incrementing the time registers, during the read cycle
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After this read/write access is completed, the time circuit is released again and any pending request to increment the time counters that occurred during the read access is serviced. A maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see Figure 8).
Fig 8. Access time for read/write operations
As a consequence of this method, it is very important to make a read or write access in one go, that is, setting or reading seconds through to years should be made in one single access. Failing to comply with this method could result in the time becoming corrupted.
As an example, if the time (seconds through to hours) is set in one access and then in a second access the date is set, it is possible that the time may increment between the two accesses. A similar problem exists when reading. A roll over may occur between reads thus giving the minutes from one moment and the hours from the next.
Recommended method for reading the time:
1. Send a START condition and the slave address for write (A2h).
2. Set the address pointer to 2 (VL_seconds) by sending 02h.
3. Send a RESTART condition or STOP followed by START.
4. Send the slave address for read (A3h).
5. Read VL_seconds.
6. Read Minutes.
7. Read Hours.
8. Read Days.
9. Read Weekdays.
10. Read Century_months.
11. Read Years.
12. Send a STOP condition.
# 8.6 Alarm registers
### 8.6.1 Register Minute_alarm
Table 18. Minute_alarm - minute alarm register (address 09h) bit description
| Bit | Symbol | Value | Place value | Description |
| :-- | :-- | :-- | :-- | :-- |
| 7 | AE_M | 0 | - | minute alarm is enabled |
| | | 100 | - | minute alarm is disabled |
| 6 to 4 | MINUTE_ALARM | 0 to 5 | ten's place | minute alarm information coded in BCD <br> format |
| 3 to 0 | | 0 to 9 | unit place | |
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[1] Default value.
# 8.6.2 Register Hour_alarm
Table 19. Hour_alarm - hour alarm register (address 0Ah) bit description
| Bit | Symbol | Value | Place value | Description |
| :-- | :-- | :-- | :-- | :-- |
| 7 | AE_H | 0 | - | hour alarm is enabled |
| | | $1 \square$ | - | hour alarm is disabled |
| 6 | - | - | - | unused |
| 5 to 4 | HOUR_ALARM | 0 to 2 | ten's place | hour alarm information coded in BCD <br> format |
| 3 to 0 | | 0 to 9 | unit place | |
[1] Default value.
### 8.6.3 Register Day_alarm
Table 20. Day_alarm - day alarm register (address 0Bh) bit description
| Bit | Symbol | Value | Place value | Description |
| :-- | :-- | :-- | :-- | :-- |
| 7 | AE_D | 0 | - | day alarm is enabled |
| | | $1 \square$ | - | day alarm is disabled |
| 6 | - | - | - | unused |
| 5 to 4 | DAY_ALARM | 0 to 3 | ten's place | day alarm information coded in BCD <br> format |
| 3 to 0 | | 0 to 9 | unit place | |
[1] Default value.
### 8.6.4 Register Weekday_alarm
Table 21. Weekday_alarm - weekday alarm register (address 0Ch) bit description
| Bit | Symbol | Value | Description |
| :-- | :-- | :-- | :-- |
| 7 | AE_W | 0 | weekday alarm is enabled |
| | | $1 \square$ | weekday alarm is disabled |
| 6 to 3 | - | - | unused |
| 2 to 0 | WEEKDAY_ALARM | 0 to 6 | weekday alarm information |
[1] Default value.
### 8.6.5 Alarm flag
By clearing the alarm enable bit (AE_x) of one or more of the alarm registers, the corresponding alarm condition(s) are active. When an alarm occurs, AF is set to logic 1. The asserted AF can be used to generate an interrupt ( $\overline{I N T}$ ). The AF is cleared using the interface.
The registers at addresses 09 h through 0 Ch contain alarm information. When one or more of these registers is loaded with minute, hour, day or weekday, and its corresponding AE_x is logic 0 , then that information is compared with the current minute, hour, day, and weekday. When all enabled comparisons first match, the alarm flag (AF in register Control_2) is set to logic 1.
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The generation of interrupts from the alarm function is controlled via bit AIE. If bit AIE is enabled, the $\overline{\mathrm{INT}}$ pin follows the condition of bit AF. AF will remain set until cleared by the interface. Once AF has been cleared, it will only be set again when the time increments to match the alarm condition once more. Alarm registers which have their $\mathrm{AE} \_x$ bit at logic 1 are ignored.
(1) Only when all enabled alarm settings are matching.
It's only on increment to a matched case that the alarm flag is set, see Section 8.6.5.
Fig 9. Alarm function block diagram
# 8.7 Register CLKOUT_control and clock output
Frequencies of 32.768 kHz (default), 1.024 kHz , 32 Hz , and 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator.
Table 22. CLKOUT_control - CLKOUT control register (address 0Dh) bit description
| Bit | Symbol | Value | Description |
| :-- | :-- | :-- | :-- |
| 7 | FE | 0 | the CLKOUT output is inhibited and CLKOUT output is <br> set high-impedance |
| | | $1 \boxplus$ | the CLKOUT output is activated |
| 6 to 2 | - | - | unused |
| 1 to 0 | FD $[1: 0]$ | | frequency output at pin CLKOUT |
| | | $00 \boxplus$ | 32.768 kHz |
| | | 01 | 1.024 kHz |
| | | 10 | 32 Hz |
| | | 11 | 1 Hz |
[1] Default value.
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# 8.8 Timer function
The 8 -bit countdown timer at address 0 Fh is controlled by the Timer_control register at address 0Eh. The Timer_control register determines one of 4 source clock frequencies for the timer ( $4096 \mathrm{~Hz}, 64 \mathrm{~Hz}, 1 \mathrm{~Hz}$, or $1 / 60 \mathrm{~Hz}$ ), and enables or disables the timer. The timer counts down from a software-loaded 8 -bit binary value. At the end of every countdown, the timer sets the timer flag TF. The TF may only be cleared by using the interface. The asserted TF can be used to generate an interrupt on pin $\overline{\mathrm{INT}}$. The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the state of TF. Bit TI_TP is used to control this mode selection. When reading the timer, the current countdown value is returned.
### 8.8.1 Register Timer_control
Table 23. Timer_control - timer control register (address 0Eh) bit description
| Bit | Symbol | Value | Description |
| :-- | :-- | :-- | :-- |
| 7 | TE | $0[1]$ | timer is disabled |
| | | 1 | timer is enabled |
| 6 to 2 | - | - | unused |
| 1 to 0 | TD[1:0] | | timer source clock frequency select[2] |
| | | 00 | 4.096 kHz |
| | | 01 | 64 Hz |
| | | 10 | 1 Hz |
| | | $11[2]$ | $1 / 60 \mathrm{~Hz}$ |
[1] Default value.
[2] These bits determine the source clock for the countdown timer; when not in use, TD[1:0] should be set to $1 / 60 \mathrm{~Hz}$ for power saving.
### 8.8.2 Register Timer
Table 24. Timer - timer value register (address 0Fh) bit description
| Bit | Symbol | Value | Description |
| :-- | :-- | :-- | :-- |
| 7 to 0 | TIMER[7:0] | 00h to FFh | countdown period in seconds: |
| | | | |
| | | | CountdownPeriod $=\frac{n}{\text { SourceClockFrequency }}$ |
| | | | where $n$ is the countdown value |
Table 25. Timer register bits value range
| Bit | | | | | | | |
| :-- | :-- | :-- | :-- | :-- | :-- | :-- | :-- |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 128 | 64 | 32 | 16 | 8 | 4 | 2 | 1 |
The register Timer is an 8-bit binary countdown timer. It is enabled and disabled via the Timer_control register bit TE. The source clock for the timer is also selected by the Timer_control register. Other timer properties such as interrupt generation are controlled via the register Control_status_2.
For accurate read back of the count down value, it is recommended to read the register twice and check for consistent results, since it is not possible to freeze the countdown timer counter during read back.
# Page 17
# 8.9 EXT_CLK test mode
A test mode is available which allows for on-board testing. In such a mode it is possible to set up test conditions and control the operation of the RTC.
The test mode is entered by setting bit TEST1 in register Control_status_1. Then pin CLKOUT becomes an input. The test mode replaces the internal 64 Hz signal with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT will then generate an increment of one second.
The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a maximum period of 1000 ns . The internal 64 Hz clock, now sourced from CLKOUT, is divided down to 1 Hz by a $2^{6}$ divide chain called a prescaler. The prescaler can be set into a known state by using bit STOP. When bit STOP is set, the prescaler is reset to 0 (STOP must be cleared before the prescaler can operate again).
From a STOP condition, the first 1 second increment will take place after 32 positive edges on CLKOUT. Thereafter, every 64 positive edges will cause a one-second increment.
Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no assumption as to the state of the prescaler can be made.
### 8.9.1 Operation example:
1. Set EXT_CLK test mode (Control_status_1, bit TEST1 = 1).
2. Set STOP (Control_status_1, bit STOP = 1).
3. Clear STOP (Control_status_1, bit STOP = 0).
4. Set time registers to desired value.
5. Apply 32 clock pulses to CLKOUT.
6. Read time registers to see the first change.
7. Apply 64 clock pulses to CLKOUT.
8. Read time registers to see the second change.
Repeat steps 7 and 8 for additional increments.
# Page 18
# 8.10 STOP bit function
The function of the STOP bit is to allow for accurate starting of the time circuits. The STOP bit function will cause the upper part of the prescaler $\left(F_{2}\right.$ to $\left.F_{14}\right)$ to be held in reset and thus no 1 Hz ticks will be generated (see Figure 10). The time circuits can then be set and will not increment until the STOP bit is released (see Figure 11 and Table 26).
Fig 10. STOP bit functional diagram
The STOP bit function will not affect the output of 32.768 kHz on CLKOUT, but will stop the generation of $1.024 \mathrm{kHz}, 32 \mathrm{~Hz}$, and 1 Hz .
The lower two stages of the prescaler $\left(F_{0}\right.$ and $\left.F_{1}\right)$ are not reset; and because the $\mathrm{I}^{2} \mathrm{C}$-bus is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be between zero and one 8.192 kHz cycle (see Figure 11).
Fig 11. STOP bit release timing
# Page 19
Table 26. First increment of time circuits after STOP bit release
| Bit | Prescaler bits | | 1 Hz tick | Time | Comment |
| :--: | :--: | :--: | :--: | :--: | :--: |
| STOP | $F_{0} F_{1}-F_{2}$ to $F_{14}$ | | | hh:mm:ss | |
| Clock is running normally | | | | | |
| 0 | 01-0 0001 11010100 | | | 12:45:12 | prescaler counting normally |
| STOP bit is activated by user. $F_{0} F_{1}$ are not reset and values cannot be predicted externally | | | | | |
| 1 | xx-0 0000000000000 | | | 12:45:12 | prescaler is reset; time circuits are frozen |
| New time is set by user | | | | | |
| 1 | xx-0 0000000000000 | | | 08:00:00 | prescaler is reset; time circuits are frozen |
| STOP bit is released by user | | | | | |
| 0 | xx-0 0000000000000 | | | 08:00:00 | prescaler is now running |
| | xx-1 0000000000000 | | | 08:00:00 | - |
| | xx-0 1000000000000 | | | 08:00:00 | - |
| | xx-1 1000000000000 | | | 08:00:00 | - |
| | : | | | : | : |
| | 11-1 1111111111110 | | | 08:00:00 | - |
| | 00-0 0000000000001 | | | 08:00:01 | 0 to 1 transition of $F_{14}$ increments the time circuits |
| | 10-0 0000000000001 | | | 08:00:01 | - |
| | : | | | : | : |
| | 11-1 1111111111111 | | | 08:00:01 | - |
| | 00-0 0000000000000 | | | 08:00:01 | - |
| | 10-0 0000000000000 | | | 08:00:01 | - |
| | : | | | : | : |
| | 11-1 1111111111110 | | | 08:00:01 | - |
| | 00-0 0000000000001 | | | 08:00:02 | 0 to 1 transition of $F_{14}$ increments the time circuits |
| | | | 013aaa076 | | |
[1] $F_{0}$ is clocked at 32.768 kHz .
The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP bit is released. The uncertainty is caused by the prescaler bits $F_{0}$ and $F_{1}$ not being reset (see Table 26) and the unknown state of the 32 kHz clock.
# 8.11 Reset
The PCF8563 includes an internal reset circuit which is active whenever the oscillator is stopped. In the reset state the $\mathrm{I}^{2} \mathrm{C}$-bus logic is initialized including the address pointer and all registers are set according to Table 27. I²C-bus communication is not possible during reset.
# Page 20
Table 27. Register reset value[1]
| Address | Register name | Bit | | | | | | | |
| :--: | :--: | :--: | :--: | :--: | :--: | :--: | :--: | :--: | :--: |
| | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 00h | Control_status_1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 01h | Control_status_2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 02h | VL_seconds | 1 | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ |
| 03h | Minutes | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ |
| 04h | Hours | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ |
| 05h | Days | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ |
| 06h | Weekdays | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ |
| 07h | Century_months | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ |
| 08h | Years | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ |
| 09h | Minute_alarm | 1 | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ |
| 0Ah | Hour_alarm | 1 | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ |
| 0Bh | Day_alarm | 1 | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ |
| 0Ch | Weekday_alarm | 1 | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ |
| 0Dh | CLKOUT_control | 1 | $x$ | $x$ | $x$ | $x$ | $x$ | 0 | 0 |
| 0Eh | Timer_control | 0 | $x$ | $x$ | $x$ | $x$ | $x$ | 1 | 1 |
| 0Fh | Timer | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ | $x$ |
[1] Registers marked $x$ are undefined at power-up and unchanged by subsequent resets.
# 8.11.1 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up on-board test of the device. The setting of this mode requires that the $\mathrm{I}^{2} \mathrm{C}$-bus pins, SDA and SCL, are toggled in a specific order as shown in Figure 12. All timings are required minimums.
Once the override mode has been entered, the device immediately stops, being reset, and normal operation may commence i.e. entry into the EXT_CLK test mode via $\mathrm{I}^{2} \mathrm{C}$-bus access. The override mode may be cleared by writing logic 0 to TESTC. TESTC must be set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic 0 during normal operation has no effect except to prevent entry into the POR override mode.
Fig 12. POR override sequence
# Page 21
# 9. Characteristics of the $\mathrm{I}^{2} \mathrm{C}$-bus
The $\mathrm{I}^{2} \mathrm{C}$-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.
### 9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 13).
Fig 13. Bit transfer
### 9.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition - P (see Figure 14).
## 9.3 System configuration
A device generating a message is a transmitter; a device receiving a message is a receiver. The device that controls the message is the master; and the devices which are controlled by the master are the slaves (see Figure 15).
# Page 22
Fig 15. System configuration
# 9.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle.
- A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte.
- Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
- The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration).
- A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
Acknowledgement on the $\mathrm{I}^{2} \mathrm{C}$-bus is illustrated in Figure 16.
Fig 16. Acknowledgement on the $\mathrm{I}^{2} \mathrm{C}$-bus
# Page 23
# 9.5 ${ }^{12} \mathrm{C}$-bus protocol
### 9.5.1 Addressing
Before any data is transmitted on the $\mathrm{I}^{2} \mathrm{C}$-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure.
The PCF8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line.
Two slave addresses are reserved for the PCF8563:
Read: A3h (10100011)
Write: A2h (10100010)
The PCF8563 slave address is illustrated in Figure 17.
Fig 17. Slave address
### 9.5.2 Clock and calendar READ or WRITE cycles
The $\mathrm{I}^{2} \mathrm{C}$-bus configuration for the different PCF8563 READ and WRITE cycles is shown in Figure 18, Figure 19 and Figure 20. The register address is a 4-bit value that defines which register is to be accessed next. The upper four bits of the register address are not used.
Fig 18. Master transmits to slave receiver (WRITE mode)
# Page 24
(1) At this moment master transmitter becomes master receiver and PCF8563 slave receiver becomes slave transmitter.
Fig 19. Master reads after setting register address (write register address; READ data)
Fig 20. Master reads slave immediately after first byte (READ mode)
# Page 25
# 9.6 Interface watchdog timer
During read/write operations, the time counting circuits are frozen. To prevent a situation where the accessing device becomes locked and does not clear the interface, the PCF8563 has a built in watchdog timer. Should the interface be active for more than 1 s from the time a valid slave address is transmitted, then the PCF8563 will automatically clear the interface and allow the time counting circuits to continue counting. The watchdog will trigger between 1 s and 2 s after receiving a valid slave address. Each time the watchdog period is exceeded, 1 s will be lost from the time counters.
The watchdog is implemented to prevent the excessive loss of time due to interface access failure e.g. if main power is removed from a battery backed-up system during an interface access.
# Page 26
# 10. Internal circuitry
Fig 22. Device diode protection diagram
# Page 27
# 11. Limiting values
Table 28. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
| Symbol | Parameter | Conditions | Min | Max | Unit |
| :--: | :--: | :--: | :--: | :--: | :--: |
| $\mathrm{V}_{\mathrm{DD}}$ | supply voltage | | $-0.5$ | $+6.5$ | V |
| $I_{D D}$ | supply current | | $-50$ | $+50$ | mA |
| $V_{I}$ | input voltage | on pins SCL, SDA, and OSCI | $-0.5$ | $+6.5$ | V |
| $V_{O}$ | output voltage | on pins CLKOUT and $\overline{I N T}$ | $-0.5$ | $+6.5$ | V |
| $I_{I}$ | input current | at any input | $-10$ | $+10$ | mA |
| $I_{O}$ | output current | at any output | $-10$ | $+10$ | mA |
| $P_{\text {tot }}$ | total power dissipation | | - | 300 | mW |
| $V_{\text {ESD }}$ | electrostatic discharge voltage | HBM | | | |
| | | HVSON10 (PCF8563BS/4) | ㅁ | $\pm 3500$ | V |
| | | SO8 (PCF8563T/F4) | ㅁ | | |
| | | TSSOP8 (PCF8563TS/4) | ㅁ | | |
| | | SO8 (PCF8563T/5) | ㅁ | $\pm 2000$ | V |
| | | TSSOP8 (PCF8563TS/5) | ㅁ | | |
| | | CDM | | | |
| | | HVSON10 (PCF8563BS/4) | 园 | $\pm 2000$ | V |
| | | SO8 (PCF8563T/F4) | 园 | $\pm 1000$ | V |
| | | SO8 (PCF8563T/5) | 园 | $\pm 1500$ | V |
| | | TSSOP8 (PCF8563TS/4) | 园 | $\pm 1500$ | V |
| | | TSSOP8 (PCF8563TS/5) | 园 | $\pm 1750$ | V |
| $I_{I u}$ | latch-up current | | 园 | 200 | mA |
| $T_{\text {stg }}$ | storage temperature | | $-65$ | $+150$ | ${ }^{\circ} \mathrm{C}$ |
| $T_{\text {amb }}$ | ambient temperature | operating device | $-40$ | $+85$ | ${ }^{\circ} \mathrm{C}$ |
[1] Pass level; Human Body Model (HBM), according to Ref. 5 "JESD22-A114".
[2] Pass level; Charged-Device Model (CDM), according to Ref. 6 "JESD22-C101".
[3] Pass level; latch-up testing according to Ref. 7 "JESD78" at maximum ambient temperature ( $\mathrm{T}_{\text {amb(max) }}$ ).
[4] According to the NXP store and transport requirements (see Ref. 9 "UM10569") the devices should be stored at a temperature of $+8^{\circ} \mathrm{C}$ to $+45^{\circ} \mathrm{C}$ and a humidity of $25 \%$ to $75 \%$. For long term storage products deviant conditions are described in that document.
# Page 28
# 12. Static characteristics
Table 29. Static characteristics
$V_{D D}=1.8 \mathrm{~V}$ to $5.5 \mathrm{~V} ; V_{S S}=0 \mathrm{~V} ; T_{\text {amb }}=-40^{\circ} \mathrm{C}$ to $+85^{\circ} \mathrm{C} ; f_{\text {bac }}=32.768 \mathrm{kHz}$; quartz $R_{s}=40 \mathrm{k} \Omega ; C_{L}=8 \mathrm{pF}$; unless otherwise specified.
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
| :--: | :--: | :--: | :--: | :--: | :--: | :--: |
| Supplies | | | | | | |
| $V_{D D}$ | supply voltage | interface inactive; $\mathrm{f}_{\mathrm{SCL}}=0 \mathrm{~Hz} ;$ $\mathrm{T}_{\text {amb }}=25^{\circ} \mathrm{C}$ | 1.0 | - | 5.5 | V |
| | | interface active; $\mathrm{f}_{\mathrm{SCL}}=400 \mathrm{kHz}$ | 1.8 | - | 5.5 | V |
| | | clock data integrity; $\mathrm{T}_{\text {amb }}=25^{\circ} \mathrm{C}$ | $\mathrm{V}_{\text {low }}$ | - | 5.5 | V |
| $I_{D D}$ | supply current | interface active | | | | |
| | | $\mathrm{f}_{\mathrm{SCL}}=400 \mathrm{kHz}$ | - | - | 800 | $\mu \mathrm{A}$ |
| | | $\mathrm{f}_{\mathrm{SCL}}=100 \mathrm{kHz}$ | - | - | 200 | $\mu \mathrm{A}$ |
| | | interface inactive ( $\mathrm{f}_{\mathrm{SCL}}=0 \mathrm{~Hz}$ ); CLKOUT disabled; $\mathrm{T}_{\text {amb }}=25^{\circ} \mathrm{C}$ | 囚 | | | |
| | | $\mathrm{V}_{\mathrm{DD}}=5.0 \mathrm{~V}$ | - | 275 | 550 | nA |
| | | $\mathrm{V}_{\mathrm{DD}}=3.0 \mathrm{~V}$ | - | 250 | 500 | nA |
| | | $\mathrm{V}_{\mathrm{DD}}=2.0 \mathrm{~V}$ | - | 225 | 450 | nA |
| | | interface inactive ( $\mathrm{f}_{\mathrm{SCL}}=0 \mathrm{~Hz}$ ); CLKOUT disabled; $\mathrm{T}_{\text {amb }}=-40^{\circ} \mathrm{C}$ to $+85^{\circ} \mathrm{C}$ | 囚 | | | |
| | | $\mathrm{V}_{\mathrm{DD}}=5.0 \mathrm{~V}$ | - | 500 | 750 | nA |
| | | $\mathrm{V}_{\mathrm{DD}}=3.0 \mathrm{~V}$ | - | 400 | 650 | nA |
| | | $\mathrm{V}_{\mathrm{DD}}=2.0 \mathrm{~V}$ | - | 400 | 600 | nA |
| | | interface inactive ( $\mathrm{f}_{\mathrm{SCL}}=0 \mathrm{~Hz}$ ); CLKOUT enabled at $32 \mathrm{kHz} ; \mathrm{T}_{\text {amb }}=25^{\circ} \mathrm{C}$ | 囚 | | | |
| | | $\mathrm{V}_{\mathrm{DD}}=5.0 \mathrm{~V}$ | - | 825 | 1600 | nA |
| | | $\mathrm{V}_{\mathrm{DD}}=3.0 \mathrm{~V}$ | - | 550 | 1000 | nA |
| | | $\mathrm{V}_{\mathrm{DD}}=2.0 \mathrm{~V}$ | - | 425 | 800 | nA |
| | | interface inactive ( $\mathrm{f}_{\mathrm{SCL}}=0 \mathrm{~Hz}$ ); CLKOUT enabled at $32 \mathrm{kHz} ; \mathrm{T}_{\text {amb }}=-40^{\circ} \mathrm{C}$ to $+85^{\circ} \mathrm{C}$ | 囚 | | | |
| | | $\mathrm{V}_{\mathrm{DD}}=5.0 \mathrm{~V}$ | - | 950 | 1700 | nA |
| | | $\mathrm{V}_{\mathrm{DD}}=3.0 \mathrm{~V}$ | - | 650 | 1100 | nA |
| | | $\mathrm{V}_{\mathrm{DD}}=2.0 \mathrm{~V}$ | - | 500 | 900 | nA |
| Inputs | | | | | | |
| $V_{I L}$ | LOW-level input voltage | | $-0.5$ | - | $+0.3 \mathrm{~V}_{\mathrm{DD}}$ | V |
| $V_{I H}$ | HIGH-level input voltage | | $0.7 \mathrm{~V}_{\mathrm{DD}}$ | - | 5.5 | V |
| $I_{L I}$ | input leakage current | $\mathrm{V}_{\mathrm{I}}=\mathrm{V}_{\mathrm{DD}}$ or $\mathrm{V}_{\mathrm{SS}}$ | $-1$ | 0 | $+1$ | $\mu \mathrm{A}$ |
| $C_{I}$ | input capacitance | | - | - | 7 | pF |
# Page 29
Table 29. Static characteristics ...continued
$V_{D D}=1.8 \mathrm{~V}$ to $5.5 \mathrm{~V} ; V_{S S}=0 \mathrm{~V} ; T_{\text {amb }}=-40^{\circ} \mathrm{C}$ to $+85^{\circ} \mathrm{C} ; f_{\text {osc }}=32.768 \mathrm{kHz}$; quartz $R_{s}=40 \mathrm{~k} \Omega ; C_{L}=8 \mathrm{pF}$; unless otherwise specified.
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
| :--: | :--: | :--: | :--: | :--: | :--: | :--: |
| Outputs | | | | | | |
| $\mathrm{I}_{\mathrm{CL}}$ | LOW-level output current | output sink current; $\mathrm{V}_{\mathrm{CL}}=0.4 \mathrm{~V} ; \mathrm{V}_{\mathrm{DD}}=5 \mathrm{~V}$ | | | | |
| | | on pin SDA | 3 | - | - | mA |
| | | on pin INT | 1 | - | - | mA |
| | | on pin CLKOUT | 1 | - | - | mA |
| $\mathrm{I}_{\mathrm{LO}}$ | output leakage current | $\mathrm{V}_{\mathrm{O}}=\mathrm{V}_{\mathrm{DD}}$ or $\mathrm{V}_{\mathrm{SS}}$ | $-1$ | 0 | $+1$ | $\mu \mathrm{~A}$ |
| Voltage detector | | | | | | |
| $\mathrm{V}_{\text {low }}$ | low voltage | $\mathrm{T}_{\text {amb }}=25^{\circ} \mathrm{C}$; sets bit VL; see Figure 6 | - | 0.9 | 1.0 | V |
[1] For reliable oscillator start-up at power on use $\mathrm{V}_{\mathrm{DD}}$ greater than 1.3 V . If powered up at 1.0 V the oscillator will start but it might be a bit slow, especially if at high temperature. Normally the power supply is not 1.0 V at start up and only comes at the end of battery discharge. $\mathrm{V}_{\mathrm{DD}}$ min of 1.0 V is specified so that the customer can calculate how large a battery or capacitor they need for their application. $\mathrm{V}_{\mathrm{DD}} \mathrm{min}$ of 1.3 V or greater is needed to ensure speedy oscillator start-up time.
[2] Timer source clock $=1 / 50 \mathrm{~Hz}$, level of pins SCL and SDA is $\mathrm{V}_{\mathrm{DD}}$ or $\mathrm{V}_{\mathrm{SS}}$.
[3] Tested on sample basis.
$\mathrm{T}_{\text {amb }}=25^{\circ} \mathrm{C}$; Timer $=1$ minute.
Fig 23. Supply current $I_{D D}$ as a function of supply voltage $\mathrm{V}_{\mathrm{DD}}$; CLKOUT disabled
$\mathrm{T}_{\text {amb }}=25^{\circ} \mathrm{C}$; Timer $=1$ minute.
Fig 24. Supply current $I_{D D}$ as a function of supply voltage $\mathrm{V}_{\mathrm{DD}} ;$ CLKOUT $=32 \mathrm{kHz}$
# Page 30
$V_{D D}=3 \mathrm{~V}$; Timer $=1$ minute.
Fig 25. Supply current $I_{D D}$ as a function of temperature T; CLKOUT $=32 \mathrm{kHz}$
$T_{\text {amb }}=25^{\circ} \mathrm{C}$; normalized to $V_{D D}=3 \mathrm{~V}$.
Fig 26. Frequency deviation as a function of supply voltage $\mathrm{V}_{\mathrm{DD}}$
# 13. Dynamic characteristics
Table 30. Dynamic characteristics
$V_{D D}=1.8 \mathrm{~V}$ to $5.5 \mathrm{~V} ; V_{S S}=0 \mathrm{~V} ; T_{\text {amb }}=-40^{\circ} \mathrm{C}$ to $+85^{\circ} \mathrm{C} ; f_{o s c}=32.768 \mathrm{kHz}$; quartz $R_{s}=40 \mathrm{k} \Omega ; C_{L}=8 \mathrm{pF}$; unless otherwise specified.
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
| :--: | :--: | :--: | :--: | :--: | :--: | :--: |
| Oscillator | | | | | | |
| $\mathrm{C}_{\text {OSCO }}$ | capacitance on pin OSCO | | 15 | 25 | 35 | pF |
| $\Delta f_{\text {osc }} / f_{\text {osc }}$ | relative oscillator frequency variation | $\Delta \mathrm{V}_{\mathrm{DD}}=200 \mathrm{mV}$; <br> $\mathrm{T}_{\text {amb }}=25^{\circ} \mathrm{C}$ | - | 0.2 | - | ppm |
| Quartz crystal parameters ( $\mathrm{f}=32.768 \mathrm{kHz}$ ) | | | | | | |
| $R_{s}$ | series resistance | | - | - | 100 | $\mathrm{k} \Omega$ |
| $C_{L}$ | load capacitance | parallel | 11 | - | 12.5 | pF |
| $\mathrm{C}_{\text {trim }}$ | trimmer capacitance | external; on pin OSCI | 5 | - | 25 | pF |
| CLKOUT output | | | | | | |
| $\delta_{\text {CLKOUT }}$ | duty cycle on pin CLKOUT | | 2 | - | 50 | - $\%$ |
| $\mathrm{f}^{2} \mathrm{C}$-bus timing characteristics (see Figure 27) ${ }^{[3][4]}$ | | | | | | |
| $t_{\text {SCL }}$ | SCL clock frequency | | 55 | - | 400 | kHz |
| $t_{\text {HD;STA }}$ | hold time (repeated) START condition | | 0.6 | - | - | $\mu \mathrm{s}$ |
| $t_{\text {SU;STA }}$ | set-up time for a repeated START condition | | 0.6 | - | - | $\mu \mathrm{s}$ |
| $t_{\text {LOW }}$ | LOW period of the SCL clock | | 1.3 | - | - | $\mu \mathrm{s}$ |
| $t_{\text {HIGH }}$ | HIGH period of the SCL clock | | 0.6 | - | - | $\mu \mathrm{s}$ |
| $t_{f}$ | rise time of both SDA and SCL signals | | | | | |
| | | standard-mode | - | - | 1 | $\mu \mathrm{s}$ |
| | | fast-mode | - | - | 0.3 | $\mu \mathrm{s}$ |
# Page 31
Table 30. Dynamic characteristics ...continued
$V_{D D}=1.8 \mathrm{~V}$ to $5.5 \mathrm{~V} ; V_{S S}=0 \mathrm{~V} ; T_{\text {amb }}=-40^{\circ} \mathrm{C}$ to $+85^{\circ} \mathrm{C} ; f_{\text {osc }}=32.768 \mathrm{kHz}$; quartz $R_{s}=40 \mathrm{~k} \Omega ; C_{L}=8 \mathrm{pF}$; unless otherwise specified.
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
| :-- | :-- | :-- | :-- | :-- | :-- | :-- |
| $\mathrm{t}_{\mathrm{f}}$ | fall time of both SDA and SCL signals | | - | - | 0.3 | $\mu \mathrm{s}$ |
| $\mathrm{t}_{\text {BUF }}$ | bus free time between a STOP and START <br> condition | | 1.3 | - | - | $\mu \mathrm{s}$ |
| $\mathrm{C}_{\mathrm{b}}$ | capacitive load for each bus line | | - | - | 400 | pF |
| $\mathrm{t}_{\text {SU;DAT }}$ | data set-up time | | 100 | - | - | ns |
| $\mathrm{t}_{\text {HD;DAT }}$ | data hold time | | 0 | - | - | ns |
| $\mathrm{t}_{\text {SU;STO }}$ | set-up time for STOP condition | | 0.6 | - | - | $\mu \mathrm{s}$ |
| $\mathrm{t}_{\text {W(spike) }}$ | spike pulse width | on bus | - | - | 50 | ns |
[1] $\mathrm{C}_{\mathrm{L}}$ is a calculation of $\mathrm{C}_{\text {trim }}$ and $\mathrm{C}_{\text {OSCO }}$ in series: $C_{L}=\frac{\left(C_{\text {trim }} \cdot C_{\text {OSCO }}\right)}{\left(C_{\text {trim }}+C_{\text {OSCO }}\right)}$.
[2] Unspecified for $\mathrm{f}_{\text {CLKOUT }}=32.768 \mathrm{kHz}$.
[3] All timing values are valid within the operating supply voltage at ambient temperature and referenced to $\mathrm{V}_{\mathrm{IL}}$ and $\mathrm{V}_{\mathrm{IH}}$ with an input voltage swing of $\mathrm{V}_{\mathrm{SS}}$ to $\mathrm{V}_{\mathrm{DD}}$.
[4] A detailed description of the $\mathrm{I}^{2} \mathrm{C}$-bus specification is given in Ref. 11 "UM10204".
[5] $\mathrm{I}^{2} \mathrm{C}$-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.
Fig 27. $\mathrm{I}^{2} \mathrm{C}$-bus timing waveforms
# Page 32
# 14. Application information
Fig 28. Application diagram
### 14.1 Quartz frequency adjustment
### 14.1.1 Method 1: fixed OSCI capacitor
By evaluating the average capacitance necessary for the application layout, a fixed capacitor can be used. The frequency is best measured via the 32.768 kHz signal available after power-on at pin CLKOUT. The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average $\pm 5 \mathrm{ppm}$ ). Average deviations of $\pm 5$ minutes per year can be easily achieved.
### 14.1.2 Method 2: OSCI trimmer
Using the 32.768 kHz signal available after power-on at pin CLKOUT, fast setting of a trimmer is possible.
### 14.1.3 Method 3: OSCO output
Direct measurement of OSCO out (accounting for test probe capacitance).
# Page 33
# 15. Package outline
HVSON10: plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body $3 \times 3 \times 0.85 \mathrm{~mm}$
SOT650-1
Fig 29. Package outline SOT650-1 (HVSON10) of PCF8563BS
# Page 34
SO8: plastic small outline package; 8 leads; body width 3.9 mm
Fig 30. Package outline SOT96-1 (SO8) of PCF8563T
# Page 35
Fig 31. Package outline SOT505-1 (TSSOP8) of PCF8563TS
# Page 36
# 16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards.
## 17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
### 17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
### 17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
- Through-hole components
- Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than $\sim 0.6 \mathrm{~mm}$ cannot be wave soldered, due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
- Board specifications, including the board finish, solder masks and vias
- Package footprints, including solder thieves and orientation
- The moisture sensitivity level of the packages
- Package placement
- Inspection and repair
- Lead-free soldering versus SnPb soldering
# Page 37
# 17.3 Wave soldering
Key characteristics in wave soldering are:
- Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave
- Solder bath specifications, including temperature and impurities
### 17.4 Reflow soldering
Key characteristics in reflow soldering are:
- Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 32) than a SnPb process, thus reducing the process window
- Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board
- Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 31 and 32
Table 31. SnPb eutectic process (from J-STD-020D)
| Package thickness (mm) | Package reflow temperature $\left({ }^{\circ} \mathrm{C}\right)$ | | |
| :-- | :-- | :-- | :-- |
| | Volume $\left(\mathrm{mm}^{3}\right)$ | | |
| | $<350$ | $\geq 350$ | |
| $<2.5$ | 235 | 220 | |
| $\geq 2.5$ | 220 | 220 | |
Table 32. Lead-free process (from J-STD-020D)
| Package thickness (mm) | Package reflow temperature $\left({ }^{\circ} \mathrm{C}\right)$ | | |
| :-- | :-- | :-- | :-- |
| | Volume $\left(\mathrm{mm}^{3}\right)$ | | |
| | $<350$ | 350 to 2000 | $>2000$ |
| $<1.6$ | 260 | 260 | 260 |
| 1.6 to 2.5 | 260 | 250 | 245 |
| $>2.5$ | 250 | 245 | 245 |
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.
Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 32.
# Page 38
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
# 18. Abbreviations
Table 33. Abbreviations
| Acronym | Description |
| :-- | :-- |
| BCD | Binary Coded Decimal |
| CDM | Charged-Device Model |
| CMOS | Complementary Metal Oxide Semiconductor |
| ESD | ElectroStatic Discharge |
| HBM | Human Body Model |
| ${ }^{12} \mathrm{C}$ | Inter-Integrated Circuit |
| IC | Integrated Circuit |
| LSB | Least Significant Bit |
| MSB | Most Significant Bit |
| MSL | Moisture Sensitivity Level |
| PCB | Printed-Circuit Board |
| POR | Power-On Reset |
| RTC | Real-Time Clock |
| SCL | Serial CLock line |
| SDA | Serial DAta line |
| SMD | Surface Mount Device |
# Page 39
# 19. References
[1] AN10365 - Surface mount reflow soldering description
[2] IEC 60134 - Rating systems for electronic tubes and valves and analogous semiconductor devices
[3] IEC 61340-5 - Protection of electronic devices from electrostatic phenomena
[4] IPC/JEDEC J-STD-020 - Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices
[5] JESD22-A114 - Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)
[6] JESD22-C101 - Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components
[7] JESD78 - IC Latch-Up Test
[8] JESD625-A - Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices
[9] UM10569 - NXP store and transport requirements
[10] SNV-FA-01-02 - Marking Formats Integrated Circuits
[11] UM10204 - $\mathrm{I}^{2} \mathrm{C}$-bus specification and user manual
# Page 40
# 20. Revision history
Table 34. Revision history
| Document ID | Release date | Data sheet status | Change notice | Supersedes |
| :--: | :--: | :--: | :--: | :--: |
| PCF8563 v. 11 | 20151026 | Product data sheet | - | PCF8563 v. 10 |
| Modifications: | - Removed DIP8 package <br> - Table 3: Corrected Table note 1 <br> - Table 28, Table note 4: Corrected "the devices have to be stored" to "the devices should be stored" <br> - Table 29: <br> - Deleted Table note 1 from $\mathrm{V}_{\mathrm{DD}} \mathrm{f}_{\mathrm{SCL}}=400 \mathrm{kHz}$ <br> - $\mathrm{V}_{\mathrm{IL}}$ : Corrected $\mathrm{V}_{\mathrm{SS}}$ to -0.5 <br> - $\mathrm{V}_{\mathrm{IH}}$ : Corrected $\mathrm{V}_{\mathrm{DD}}$ to 5.5 <br> - Corrected Table note 1 | | | |
| PCF8563 v. 10 | 20120403 | Product data sheet | - | PCF8563 v. 9 |
| Modifications: | - Adjusted marking codes <br> - Adjusted text for $\mathrm{FE}=0$ in Table 22 | | | |
| PCF8563 v. 9 | 20110616 | Product data sheet | - | PCF8563 v. 8 |
| PCF8563 v. 8 | 20101118 | Product data sheet | - | PCF8563 v. 7 |
| PCF8563 v. 7 | 20100723 | Product data sheet | - | PCF8563_6 |
| PCF8563_6 | 20080221 | Product data sheet | - | PCF8563_5 |
| PCF8563_5 | 20070717 | Product data sheet | - | PCF8563-04 |
| PCF8563-04 <br> (9397 750 12999) | 20040312 | Product data | - | PCF8563-03 |
| PCF8563-03 <br> (9397 750 11158) | 20030414 | Product data | - | PCF8563-02 |
| PCF8563-02 <br> (9397 750 04855) | 19990416 | Product data | - | PCF8563_N_1 |
| PCF8563_N_1 <br> (9397 750 03282) | 19980325 | Objective specification | - | - |
# Page 41
# 21. Legal information
### 21.1 Data sheet status
| Document status ${ }^{[1]}$ | Product status ${ }^{[2]}$ | Definition |
| :-- | :-- | :-- |
| Objective [short] data sheet | Development | This document contains data from the objective specification for product development. |
| Preliminary [short] data sheet | Qualification | This document contains data from the preliminary specification. |
| Product [short] data sheet | Production | This document contains the product specification. |
[^0]
## 21.2 Definitions
Draft - The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.
Short data sheet - A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Product specification - The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
### 21.3 Disclaimers
Limited warranty and liability - Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes - NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
Suitability for use - NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
Applications - Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect.
Limiting values - Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.
Terms and conditions of commercial sale - NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.
No offer to sell or license - Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
[^0]: [1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
# Page 42
Export control - This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.
Non-automotive qualified products - Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's
own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
Translations - A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
### 21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
${ }^{12} \mathrm{C}$-bus - logo is a trademark of NXP Semiconductors N.V.
# 22. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
# Page 43
# 23. Tables
Table 1. Ordering information ..... 2
Table 2. Marking codes ..... 2
Table 3. Pin description ..... 5
Table 4. Formatted registers overview ..... 6
Table 5. Control_status_1 - control and status register 1(address 00h) bit description7
Table 6. Control_status_2 - control and status register 2(address 01h) bit description7
Table 7. $\overline{\mathrm{INT}}$ operation (bit $\mathrm{TI} \_\mathrm{TP}=1$ ) ..... 9
Table 8. VL_seconds - seconds and clock integrity statusregister (address 02h) bit description9
Table 9. Seconds coded in BCD format ..... 9
Table 10. Minutes - minutes register (address 03h)bit description10
Table 11. Hours - hours register (address 04h)bit description10
Table 12. Days - days register (address 05h)bit description10
Table 13. Weekdays - weekdays register (address 06h)bit description11
Table 14. Weekday assignments ..... 11
Table 15. Century_months - century flag and monthsegister (address 07h) bit description ..... 11
Table 16. Month assignments in BCD format ..... 11
Table 17. Years - years register (08h) bit description ..... 12
Table 18. Minute_alarm - minute alarm register(address 09h) bit description13
Table 19. Hour_alarm - hour alarm register (address 0Ah)bit description14
Table 20. Day_alarm - day alarm register (address 0Bh)bit description ..... 14
Table 21. Weekday_alarm - weekday alarm register(address 0Ch) bit description14
Table 22. CLKOUT_control - CLKOUT control register(address 0Dh) bit description15
Table 23. Timer_control - timer control register(address 0Eh) bit description16
Table 24. Timer - timer value register (address 0Fh)bit description16
Table 25. Timer register bits value range ..... 16
Table 26. First increment of time circuits after STOPbit release19
Table 27. Register reset value ..... 20
Table 28. Limiting values ..... 27
Table 29. Static characteristics ..... 28
Table 30. Dynamic characteristics ..... 30
Table 31. SnPb eutectic process (from J-STD-020D) ..... 37
Table 32. Lead-free process (from J-STD-020D) ..... 37
Table 33. Abbreviations ..... 38
Table 34. Revision history ..... 40
# Page 44
# 24. Figures
Fig 1. Block diagram of PCF8563 ..... 3
Fig 2. Pin configuration for HVSON10 (PCF8563BS) ..... 4
Fig 3. Pin configuration for SO8 (PCF8563T) ..... 4
Fig 4. Pin configuration for TSSOP8 (PCF8563TS). ..... 4
Fig 5. Interrupt scheme ..... 8
Fig 6. Voltage-low detection. ..... 10
Fig 7. Data flow for the time function ..... 12
Fig 8. Access time for read/write operations ..... 13
Fig 9. Alarm function block diagram. ..... 15
Fig 10. STOP bit functional diagram ..... 18
Fig 11. STOP bit release timing ..... 18
Fig 12. POR override sequence ..... 20
Fig 13. Bit transfer ..... 21
Fig 14. Definition of START and STOP conditions. ..... 21
Fig 15. System configuration ..... 22
Fig 16. Acknowledgement on the I²C-bus ..... 22
Fig 17. Slave address ..... 23
Fig 18. Master transmits to slave receiver (WRITE mode) ..... 23
Fig 19. Master reads after setting register address (write register address; READ data) ..... 24
Fig 20. Master reads slave immediately after first byte (READ mode) ..... 24
Fig 21. Interface watchdog timer ..... 25
Fig 22. Device diode protection diagram ..... 26
Fig 23. Supply current $\mathrm{I}_{\mathrm{DD}}$ as a function of supply voltage $\mathrm{V}_{\mathrm{DD}}$; CLKOUT disabled ..... 29
Fig 24. Supply current $\mathrm{I}_{\mathrm{DD}}$ as a function of supply voltage $\mathrm{V}_{\mathrm{DD}} ;$ CLKOUT $=32 \mathrm{kHz}$ ..... 29
Fig 25. Supply current $\mathrm{I}_{\mathrm{DD}}$ as a function of temperature T; CLKOUT $=32 \mathrm{kHz}$ ..... 30
Fig 26. Frequency deviation as a function of supply voltage $\mathrm{V}_{\mathrm{DD}}$ ..... 30
Fig 27. I²C-bus timing waveforms ..... 31
Fig 28. Application diagram ..... 32
Fig 29. Package outline SOT650-1 (HVSON10) of PCF8563BS ..... 33
Fig 30. Package outline SOT96-1 (SO8) of PCF8563T. ..... 34
Fig 31. Package outline SOT505-1 (TSSOP8) of PCF8563TS ..... 35
Fig 32. Temperature profiles for large and small components ..... 38
# Page 45
# 25. Contents
1 General description ..... 1
9.5 $\mathrm{I}^{2} \mathrm{C}$-bus protocol ..... 23
2 Features and benefits ..... 1
9.5.1 Addressing ..... 23
3 Applications ..... 1
9.5.2 Clock and calendar READ or WRITE cycles ..... 23
4 Ordering information ..... 2
9.6 Interface watchdog timer ..... 25
5 Marking ..... 2
10 Internal circuitry ..... 26
6 Block diagram ..... 3
11 Limiting values ..... 27
7 Pinning information ..... 4
12 Static characteristics ..... 28
7.1 Pinning ..... 4
13 Dynamic characteristics ..... 30
7.2 Pin description ..... 5
14 Application information ..... 32
8 Functional description ..... 6
14.1 Quartz frequency adjustment ..... 32
8.1 CLKOUT output ..... 6
14.1.1 Method 1: fixed OSCI capacitor ..... 32
8.2 Register organization ..... 6
14.1.2 Method 2: OSCI trimmer ..... 32
8.3 Control registers ..... 7
14.1.3 Method 3: OSCO output ..... 32
8.3.1 Register Control_status_1 ..... 7
Package outline ..... 33
8.3.2 Register Control_status_2 ..... 7
16 Handling information ..... 36
8.3.2.1 Interrupt output ..... 8
17 Soldering of SMD packages ..... 36
8.4 Time and date registers ..... 9
17.1 Introduction to soldering ..... 36
8.4.1 Register VL_seconds ..... 9
Wave and reflow soldering ..... 36
8.4.1.1 Voltage-low detector and clock monitor ..... 10 Wave soldering ..... 37
8.4.2 Register Minutes ..... 10
Reflow soldering ..... 37
8.4.3 Register Hours ..... 10
Abbreviations ..... 38
8.4.4 Register Days ..... 10
19 References ..... 39
8.4.5 Register Weekdays ..... 11
20 Revision history ..... 40
8.4.6 Register Century_months ..... 16
21 Legal information ..... 41
8.4.7 Register Years ..... 12
21.1 Data sheet status ..... 41
8.5 Setting and reading the time ..... 12
21.2 Definitions ..... 41
8.6 Alarm registers ..... 13
21.3 Disclaimers ..... 41
8.6.1 Register Minute_alarm ..... 13
21.4 Trademarks ..... 42
8.6.2 Register Hour_alarm ..... 14
22 Contact information ..... 42
8.6.3 Register Day_alarm ..... 14
23 Tables ..... 43
8.6.4 Register Weekday_alarm ..... 14
24 Figures ..... 44
8.6.5 Alarm flag ..... 14
25 Contents ..... 45
8.7 Register CLKOUT_control and clock output ..... 15
8.8 Timer function ..... 16
8.8.1 Register Timer_control ..... 16
8.8.2 Register Timer ..... 16
8.9 EXT_CLK test mode ..... 17
8.9.1 Operation example: ..... 17
8.10 STOP bit function ..... 18
8.11 Reset ..... 19
8.11.1 Power-On Reset (POR) override ..... 20
9 Characteristics of the $\mathrm{I}^{2} \mathrm{C}$-bus ..... 21
9.1 Bit transfer ..... 21
9.2 START and STOP conditions ..... 21
9.3 System configuration ..... 21
9.4 Acknowledge ..... 22
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'.
© NXP Semiconductors N.V. 2015. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 26 October 2015
Document identifier: PCF8563