pub struct Board {Show 70 fields
pub pins: Pins,
pub CBP: CBP,
pub CPUID: CPUID,
pub DCB: DCB,
pub DWT: DWT,
pub FPB: FPB,
pub FPU: FPU,
pub ITM: ITM,
pub MPU: MPU,
pub NVIC: NVIC,
pub SCB: SCB,
pub SYST: SYST,
pub TPIU: TPIU,
pub FICR: FICR,
pub UICR: UICR,
pub POWER: POWER,
pub CLOCK: CLOCK,
pub RADIO: RADIO,
pub UART0: UART0,
pub SPIM0: SPIM0,
pub SPIS0: SPIS0,
pub TWIM0: TWIM0,
pub TWIS0: TWIS0,
pub SPI0: SPI0,
pub TWI0: TWI0,
pub SPIM1: SPIM1,
pub SPIS1: SPIS1,
pub TWIS1: TWIS1,
pub SPI1: SPI1,
pub TWI1: TWI1,
pub NFCT: NFCT,
pub GPIOTE: GPIOTE,
pub SAADC: SAADC,
pub TIMER0: TIMER0,
pub TIMER1: TIMER1,
pub TIMER2: TIMER2,
pub RTC0: RTC0,
pub TEMP: TEMP,
pub RNG: RNG,
pub ECB: ECB,
pub CCM: CCM,
pub AAR: AAR,
pub WDT: WDT,
pub RTC1: RTC1,
pub QDEC: QDEC,
pub COMP: COMP,
pub LPCOMP: LPCOMP,
pub SWI0: SWI0,
pub EGU0: EGU0,
pub SWI1: SWI1,
pub EGU1: EGU1,
pub SWI2: SWI2,
pub EGU2: EGU2,
pub SWI3: SWI3,
pub EGU3: EGU3,
pub SWI4: SWI4,
pub EGU4: EGU4,
pub SWI5: SWI5,
pub EGU5: EGU5,
pub TIMER3: TIMER3,
pub TIMER4: TIMER4,
pub PWM0: PWM0,
pub PDM: PDM,
pub NVMC: NVMC,
pub PPI: PPI,
pub MWU: MWU,
pub PWM1: PWM1,
pub PWM2: PWM2,
pub RTC2: RTC2,
pub I2S: I2S,
}
Fields§
§pins: Pins
§CBP: CBP
Core peripheral: Cache and branch predictor maintenance operations
CPUID: CPUID
Core peripheral: CPUID
DCB: DCB
Core peripheral: Debug Control Block
DWT: DWT
Core peripheral: Data Watchpoint and Trace unit
FPB: FPB
Core peripheral: Flash Patch and Breakpoint unit
FPU: FPU
Core peripheral: Floating Point Unit
ITM: ITM
Core peripheral: Instrumentation Trace Macrocell
MPU: MPU
Core peripheral: Memory Protection Unit
NVIC: NVIC
Core peripheral: Nested Vector Interrupt Controller
SCB: SCB
Core peripheral: System Control Block
SYST: SYST
Core peripheral: SysTick Timer
TPIU: TPIU
Core peripheral: Trace Port Interface Unit
FICR: FICR
nRF52 peripheral: FICR
UICR: UICR
nRF52 peripheral: UICR
POWER: POWER
nRF52 peripheral: POWER
CLOCK: CLOCK
nRF52 peripheral: CLOCK
RADIO: RADIO
nRF52 peripheral: RADIO
UART0: UART0
nRF52 peripheral: UART0
SPIM0: SPIM0
nRF52 peripheral: SPIM0
SPIS0: SPIS0
nRF52 peripheral: SPIS0
TWIM0: TWIM0
nRF52 peripheral: TWIM0
TWIS0: TWIS0
nRF52 peripheral: TWIS0
SPI0: SPI0
nRF52 peripheral: SPI0
TWI0: TWI0
nRF52 peripheral: TWI0
SPIM1: SPIM1
nRF52 peripheral: SPIM1
SPIS1: SPIS1
nRF52 peripheral: SPIS1
TWIS1: TWIS1
nRF52 peripheral: TWIS1
SPI1: SPI1
nRF52 peripheral: SPI1
TWI1: TWI1
nRF52 peripheral: TWI1
NFCT: NFCT
nRF52 peripheral: NFCT
GPIOTE: GPIOTE
nRF52 peripheral: GPIOTE
SAADC: SAADC
nRF52 peripheral: SAADC
TIMER0: TIMER0
nRF52 peripheral: TIMER0
TIMER1: TIMER1
nRF52 peripheral: TIMER1
TIMER2: TIMER2
nRF52 peripheral: TIMER2
RTC0: RTC0
nRF52 peripheral: RTC0
TEMP: TEMP
nRF52 peripheral: TEMP
RNG: RNG
nRF52 peripheral: RNG
ECB: ECB
nRF52 peripheral: ECB
CCM: CCM
nRF52 peripheral: CCM
AAR: AAR
nRF52 peripheral: AAR
WDT: WDT
nRF52 peripheral: WDT
RTC1: RTC1
nRF52 peripheral: RTC1
QDEC: QDEC
nRF52 peripheral: QDEC
COMP: COMP
nRF52 peripheral: COMP
LPCOMP: LPCOMP
nRF52 peripheral: LPCOMP
SWI0: SWI0
nRF52 peripheral: SWI0
EGU0: EGU0
nRF52 peripheral: EGU0
SWI1: SWI1
nRF52 peripheral: SWI1
EGU1: EGU1
nRF52 peripheral: EGU1
SWI2: SWI2
nRF52 peripheral: SWI2
EGU2: EGU2
nRF52 peripheral: EGU2
SWI3: SWI3
nRF52 peripheral: SWI3
EGU3: EGU3
nRF52 peripheral: EGU3
SWI4: SWI4
nRF52 peripheral: SWI4
EGU4: EGU4
nRF52 peripheral: EGU4
SWI5: SWI5
nRF52 peripheral: SWI5
EGU5: EGU5
nRF52 peripheral: EGU5
TIMER3: TIMER3
nRF52 peripheral: TIMER3
TIMER4: TIMER4
nRF52 peripheral: TIMER4
PWM0: PWM0
nRF52 peripheral: PWM0
PDM: PDM
nRF52 peripheral: PDM
NVMC: NVMC
nRF52 peripheral: NVMC
PPI: PPI
nRF52 peripheral: PPI
MWU: MWU
nRF52 peripheral: MWU
PWM1: PWM1
nRF52 peripheral: PWM1
PWM2: PWM2
nRF52 peripheral: PWM2
RTC2: RTC2
nRF52 peripheral: RTC2
I2S: I2S
nRF52 peripheral: I2S