1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
use std::sync::Arc;
use parasol_concurrency::AtomicRefCell;
use crate::{
Ciphertext, Register, Result,
proc::{DispatchIsaOp, fhe_processor::FheProcessor},
tomasulo::{registers::RobEntryRef, tomasulo_processor::RetirementInfo},
unwrap_registers,
};
impl FheProcessor {
/// Zero-extend the register `src` to the width `new_width` and store the
/// result in `dst`.
pub fn zext(
&mut self,
retirement_info: RetirementInfo<DispatchIsaOp>,
dst: RobEntryRef<Register>,
src: RobEntryRef<Register>,
new_width: u32,
instruction_id: usize,
pc: u32,
) {
self.ext(
retirement_info,
dst,
src,
new_width,
instruction_id,
pc,
false,
)
}
pub fn sext(
&mut self,
retirement_info: RetirementInfo<DispatchIsaOp>,
dst: RobEntryRef<Register>,
src: RobEntryRef<Register>,
new_width: u32,
instruction_id: usize,
pc: u32,
) {
self.ext(
retirement_info,
dst,
src,
new_width,
instruction_id,
pc,
true,
)
}
#[allow(clippy::too_many_arguments)]
pub fn ext(
&mut self,
retirement_info: RetirementInfo<DispatchIsaOp>,
dst: RobEntryRef<Register>,
src: RobEntryRef<Register>,
new_width: u32,
instruction_id: usize,
pc: u32,
signed: bool,
) {
let ext_impl = || -> Result<()> {
unwrap_registers!((mut dst) (src));
if (new_width as usize) < src.width() {
return Err(crate::Error::WidthMismatch {
inst_id: instruction_id,
pc,
});
}
match src {
Register::Plaintext { val, width } => {
*dst = Register::Plaintext {
val: if signed {
if val >> (width - 1) == 0 {
*val
} else {
let old_mask = (1 << width) - 1;
let new_mask = (1 << new_width) - 1;
(val | !old_mask) & new_mask
}
} else {
*val
},
width: new_width,
};
FheProcessor::retire(&retirement_info, Ok(()));
}
Register::Ciphertext(Ciphertext::L1Glwe { data }) => {
let current_width = data.len() as u32;
// Get trivial zeros
let pad = if signed {
data.last().unwrap().clone()
} else {
Arc::new(AtomicRefCell::new(self.aux_data.l1glwe_zero.clone()))
};
// We are little endian so we append zeros to the end
let output = data
.iter()
.chain(std::iter::repeat_n(
&pad,
(new_width - current_width) as usize,
))
.cloned()
.collect();
*dst = Register::Ciphertext(Ciphertext::L1Glwe { data: output });
FheProcessor::retire(&retirement_info, Ok(()));
}
// We expect the inputs to an instruction to either be plaintext
// or L1 GLWE ciphertexts
_ => {
return Err(crate::Error::EncryptionMismatch);
}
}
Ok(())
};
if let Err(e) = ext_impl() {
FheProcessor::retire(&retirement_info, Err(e));
}
}
/// Truncate the register `src` to the width `new_width` and store the
/// result in `dst`.
pub fn trunc(
&mut self,
retirement_info: RetirementInfo<DispatchIsaOp>,
dst: RobEntryRef<Register>,
src: RobEntryRef<Register>,
new_width: u32,
instruction_id: usize,
pc: u32,
) {
let trunc_impl = || -> Result<()> {
unwrap_registers!((mut dst) (src));
if (new_width as usize) > src.width() {
return Err(crate::Error::WidthMismatch {
inst_id: instruction_id,
pc,
});
}
match src {
Register::Plaintext { val, width: _ } => {
let mask = (0x1 << new_width) - 1;
*dst = Register::Plaintext {
val: (*val) & mask,
width: new_width,
};
FheProcessor::retire(&retirement_info, Ok(()));
}
Register::Ciphertext(Ciphertext::L1Glwe { data }) => {
// Little endian, we just take the first `new_width` elements
// let output = data.iter().take(new_width as usize).cloned().collect();
let output = data[0..new_width as usize].to_vec();
*dst = Register::Ciphertext(Ciphertext::L1Glwe { data: output });
FheProcessor::retire(&retirement_info, Ok(()));
}
// We expect the inputs to an instruction to either be plaintext
// or L1 GLWE ciphertexts
_ => {
return Err(crate::Error::EncryptionMismatch);
}
}
Ok(())
};
if let Err(e) = trunc_impl() {
FheProcessor::retire(&retirement_info, Err(e));
}
}
}