page_table_entry 0.6.0

Page table entry definition for various hardware architectures
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70

# THIS FILE IS AUTOMATICALLY GENERATED BY CARGO
#
# When uploading crates to the registry Cargo will automatically
# "normalize" Cargo.toml files for maximal compatibility
# with all versions of Cargo and also rewrite `path` dependencies
# to registry (e.g., crates.io) dependencies.
#
# If you are reading this file be aware that the original Cargo.toml
# will likely look very different (and much more reasonable).
# See Cargo.toml.orig for the original contents.

[package]
edition = "2024"
rust-version = "1.85"
name = "page_table_entry"
version = "0.6.0"
authors = ["Yuekai Jia <equation618@gmail.com>"]
build = false
autolib = false
autobins = false
autoexamples = false
autotests = false
autobenches = false
description = "Page table entry definition for various hardware architectures"
homepage = "https://github.com/arceos-org/arceos"
documentation = "https://docs.rs/page_table_entry"
readme = "README.md"
keywords = [
    "arceos",
    "paging",
    "page-table",
    "virtual-memory",
]
categories = [
    "os",
    "hardware-support",
    "memory-management",
    "no-std",
]
license = "GPL-3.0-or-later OR Apache-2.0 OR MulanPSL-2.0"
repository = "https://github.com/arceos-org/page_table_multiarch"
resolver = "2"

[package.metadata.docs.rs]
rustc-args = [
    "--cfg",
    "docsrs",
]
all-features = true

[features]
arm-el2 = []
xuantie-c9xx = []

[lib]
name = "page_table_entry"
path = "src/lib.rs"

[dependencies.bitflags]
version = "2.9"

[dependencies.memory_addr]
version = "0.4"

[target.'cfg(any(target_arch = "aarch64", doc, docsrs))'.dependencies.aarch64-cpu]
version = "10.0"

[target.'cfg(any(target_arch = "x86_64", doc, docsrs))'.dependencies.x86_64]
version = "0.15"
default-features = false