padlock-core 0.6.2

Core IR, analysis passes, and findings for the padlock struct layout analyzer
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93

#[derive(Clone, Copy, Debug, PartialEq)]
pub enum Endianness {
    Little,
    Big,
}

#[derive(Clone, Copy, Debug, PartialEq)]
pub struct ArchConfig {
    pub name: &'static str,
    pub pointer_size: usize,
    pub cache_line_size: usize,
    pub max_align: usize,
    pub endianness: Endianness,
}

pub const X86_64_SYSV: ArchConfig = ArchConfig {
    name: "x86_64",
    pointer_size: 8,
    cache_line_size: 64,
    max_align: 16,
    endianness: Endianness::Little,
};

pub const AARCH64: ArchConfig = ArchConfig {
    name: "aarch64",
    pointer_size: 8,
    cache_line_size: 64,
    max_align: 16,
    endianness: Endianness::Little,
};

pub const AARCH64_APPLE: ArchConfig = ArchConfig {
    name: "aarch64-apple",
    pointer_size: 8,
    cache_line_size: 128,
    max_align: 16,
    endianness: Endianness::Little,
};

pub const WASM32: ArchConfig = ArchConfig {
    name: "wasm32",
    pointer_size: 4,
    cache_line_size: 64,
    max_align: 8,
    endianness: Endianness::Little,
};

pub const RISCV64: ArchConfig = ArchConfig {
    name: "riscv64",
    pointer_size: 8,
    cache_line_size: 64,
    max_align: 16,
    endianness: Endianness::Little,
};

/// Create a custom `ArchConfig` by overriding specific fields of a base arch.
///
/// Useful for `--cache-line-size` and `--word-size` CLI overrides.
/// The returned reference is intentionally leaked — CLI binaries are short-lived.
pub fn with_overrides(
    base: &ArchConfig,
    cache_line_size: Option<usize>,
    word_size: Option<usize>,
) -> &'static ArchConfig {
    let ptr = word_size.unwrap_or(base.pointer_size);
    let max_align = if word_size.is_some() {
        // 32-bit targets typically cap natural alignment at 8; 64-bit at 16
        if ptr <= 4 { 8 } else { base.max_align }
    } else {
        base.max_align
    };
    Box::leak(Box::new(ArchConfig {
        name: "custom",
        pointer_size: ptr,
        cache_line_size: cache_line_size.unwrap_or(base.cache_line_size),
        max_align,
        endianness: base.endianness,
    }))
}

/// Resolve an architecture name string to a static `ArchConfig` reference.
///
/// Accepted values: `x86_64`, `aarch64`, `aarch64_apple`, `wasm32`, `riscv64`.
pub fn arch_by_name(name: &str) -> Option<&'static ArchConfig> {
    match name {
        "x86_64" => Some(&X86_64_SYSV),
        "aarch64" => Some(&AARCH64),
        "aarch64_apple" => Some(&AARCH64_APPLE),
        "wasm32" => Some(&WASM32),
        "riscv64" => Some(&RISCV64),
        _ => None,
    }
}