#![doc = "Peripheral access API for PAC52XX microcontrollers (generated using svd2rust v0.35.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.35.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
use core::marker::PhantomData;
use core::ops::Deref;
#[doc = r"Number available in the NVIC for configuring priority"]
pub const NVIC_PRIO_BITS: u8 = 2;
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
pub use cortex_m::peripheral::Peripherals as CorePeripherals;
pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU};
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
#[cfg(feature = "rt")]
extern "C" {
fn IRQ_MEMCTL();
fn IRQ_SYSCLK();
fn IRQ_WDT();
fn IRQ_GPIOA();
fn IRQ_GPIOB();
fn IRQ_GPIOC();
fn IRQ_GPIOD();
fn IRQ_GPIOE();
fn IRQ_TIMERA();
fn IRQ_TIMERB();
fn IRQ_TIMERC();
fn I_TIMERD();
fn IRQ_ADC();
fn IRQ_SOCB();
fn IRQ_SPI();
fn IRQ_UART();
fn IRQ_I2C();
fn IRQ_RTC();
}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
_handler: unsafe extern "C" fn(),
_reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 20] = [
Vector {
_handler: IRQ_MEMCTL,
},
Vector {
_handler: IRQ_SYSCLK,
},
Vector { _handler: IRQ_WDT },
Vector {
_handler: IRQ_GPIOA,
},
Vector {
_handler: IRQ_GPIOB,
},
Vector {
_handler: IRQ_GPIOC,
},
Vector {
_handler: IRQ_GPIOD,
},
Vector {
_handler: IRQ_GPIOE,
},
Vector {
_handler: IRQ_TIMERA,
},
Vector { _reserved: 0 },
Vector {
_handler: IRQ_TIMERB,
},
Vector {
_handler: IRQ_TIMERC,
},
Vector { _handler: I_TIMERD },
Vector { _handler: IRQ_ADC },
Vector { _handler: IRQ_SOCB },
Vector { _handler: IRQ_SPI },
Vector { _handler: IRQ_UART },
Vector { _handler: IRQ_I2C },
Vector { _reserved: 0 },
Vector { _handler: IRQ_RTC },
];
#[doc = r"Enumeration of all the interrupts."]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
#[doc = "0 - IRQ_MEMCTL"]
IRQ_MEMCTL = 0,
#[doc = "1 - IRQ_SYSCLK"]
IRQ_SYSCLK = 1,
#[doc = "2 - IRQ_WDT"]
IRQ_WDT = 2,
#[doc = "3 - IRQ_GPIOA"]
IRQ_GPIOA = 3,
#[doc = "4 - IRQ_GPIOB"]
IRQ_GPIOB = 4,
#[doc = "5 - IRQ_GPIOC"]
IRQ_GPIOC = 5,
#[doc = "6 - IRQ_GPIOD"]
IRQ_GPIOD = 6,
#[doc = "7 - IRQ_GPIOE"]
IRQ_GPIOE = 7,
#[doc = "8 - IRQ_TIMERA"]
IRQ_TIMERA = 8,
#[doc = "10 - IRQ_TIMERB"]
IRQ_TIMERB = 10,
#[doc = "11 - IRQ_TIMERC"]
IRQ_TIMERC = 11,
#[doc = "12 - Timer Interrupt Register"]
I_TIMERD = 12,
#[doc = "13 - IRQ_ADC"]
IRQ_ADC = 13,
#[doc = "14 - IRQ_SOCB"]
IRQ_SOCB = 14,
#[doc = "15 - IRQ_SPI"]
IRQ_SPI = 15,
#[doc = "16 - IRQ_UART"]
IRQ_UART = 16,
#[doc = "17 - IRQ_I2C"]
IRQ_I2C = 17,
#[doc = "19 - IRQ_RTC"]
IRQ_RTC = 19,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
#[inline(always)]
fn number(self) -> u16 {
self as u16
}
}
#[doc = "System and Clock Control"]
pub struct SYSCLK {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for SYSCLK {}
impl SYSCLK {
#[doc = r"Pointer to the register block"]
pub const PTR: *const sysclk::RegisterBlock = 0x4000_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const sysclk::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for SYSCLK {
type Target = sysclk::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for SYSCLK {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SYSCLK").finish()
}
}
#[doc = "System and Clock Control"]
pub mod sysclk {
#[repr(C)]
#[derive(Debug)]
#[doc = "Register block"]
pub struct RegisterBlock {
scctl: SCCTL,
pllctl: PLLCTL,
roscctl: ROSCCTL,
xtalctl: XTALCTL,
}
impl RegisterBlock {
#[doc = "0x00 - System Clock Control Register"]
#[inline(always)]
pub const fn scctl(&self) -> &SCCTL {
&self.scctl
}
#[doc = "0x04 - PLL Control Register"]
#[inline(always)]
pub const fn pllctl(&self) -> &PLLCTL {
&self.pllctl
}
#[doc = "0x08 - Ring Oscillator Control Register"]
#[inline(always)]
pub const fn roscctl(&self) -> &ROSCCTL {
&self.roscctl
}
#[doc = "0x0c - Crystal Driver Control Register"]
#[inline(always)]
pub const fn xtalctl(&self) -> &XTALCTL {
&self.xtalctl
}
}
#[doc = "SCCTL (rw) register accessor: System Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scctl`]
module"]
pub type SCCTL = crate::Reg<scctl::SCCTLrs>;
#[doc = "System Clock Control Register"]
pub mod scctl {
#[doc = "Register `SCCTL` reader"]
pub type R = crate::R<SCCTLrs>;
#[doc = "Register `SCCTL` writer"]
pub type W = crate::W<SCCTLrs>;
#[doc = "FRCLK input clock select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum CLKIN {
#[doc = "0: Internal Ring Oscillator"]
Rosc = 0,
#[doc = "1: CLKREF input"]
Clkref = 1,
#[doc = "2: External Clock Input"]
Extclk = 2,
#[doc = "3: Crystal Driver XIN/XOUT Input"]
Xtal = 3,
}
impl From<CLKIN> for u8 {
#[inline(always)]
fn from(variant: CLKIN) -> Self {
variant as _
}
}
impl crate::FieldSpec for CLKIN {
type Ux = u8;
}
impl crate::IsEnum for CLKIN {}
#[doc = "Field `CLKIN` reader - FRCLK input clock select"]
pub type CLKIN_R = crate::FieldReader<CLKIN>;
impl CLKIN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CLKIN {
match self.bits {
0 => CLKIN::Rosc,
1 => CLKIN::Clkref,
2 => CLKIN::Extclk,
3 => CLKIN::Xtal,
_ => unreachable!(),
}
}
#[doc = "Internal Ring Oscillator"]
#[inline(always)]
pub fn is_rosc(&self) -> bool {
*self == CLKIN::Rosc
}
#[doc = "CLKREF input"]
#[inline(always)]
pub fn is_clkref(&self) -> bool {
*self == CLKIN::Clkref
}
#[doc = "External Clock Input"]
#[inline(always)]
pub fn is_extclk(&self) -> bool {
*self == CLKIN::Extclk
}
#[doc = "Crystal Driver XIN/XOUT Input"]
#[inline(always)]
pub fn is_xtal(&self) -> bool {
*self == CLKIN::Xtal
}
}
#[doc = "Field `CLKIN` writer - FRCLK input clock select"]
pub type CLKIN_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CLKIN, crate::Safe>;
impl<'a, REG> CLKIN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Internal Ring Oscillator"]
#[inline(always)]
pub fn rosc(self) -> &'a mut crate::W<REG> {
self.variant(CLKIN::Rosc)
}
#[doc = "CLKREF input"]
#[inline(always)]
pub fn clkref(self) -> &'a mut crate::W<REG> {
self.variant(CLKIN::Clkref)
}
#[doc = "External Clock Input"]
#[inline(always)]
pub fn extclk(self) -> &'a mut crate::W<REG> {
self.variant(CLKIN::Extclk)
}
#[doc = "Crystal Driver XIN/XOUT Input"]
#[inline(always)]
pub fn xtal(self) -> &'a mut crate::W<REG> {
self.variant(CLKIN::Xtal)
}
}
#[doc = "ACLK divider\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum ACLKDIV {
#[doc = "0: ACLK = FCLK /1"]
FclkDiv1 = 0,
#[doc = "1: ACLK = FCLK /2"]
FclkDiv2 = 1,
#[doc = "2: ACLK = FCLK /4"]
FclkDiv4 = 2,
#[doc = "3: ACLK = FCLK /8"]
FclkDiv8 = 3,
#[doc = "4: ACLK = FCLK /16"]
FclkDiv16 = 4,
#[doc = "5: ACLK = FCLK /32"]
FclkDiv32 = 5,
#[doc = "6: ACLK = FCLK /64"]
FclkDiv64 = 6,
#[doc = "7: ACLK = FCLK /128"]
FclkDiv128 = 7,
}
impl From<ACLKDIV> for u8 {
#[inline(always)]
fn from(variant: ACLKDIV) -> Self {
variant as _
}
}
impl crate::FieldSpec for ACLKDIV {
type Ux = u8;
}
impl crate::IsEnum for ACLKDIV {}
#[doc = "Field `ACLKDIV` reader - ACLK divider"]
pub type ACLKDIV_R = crate::FieldReader<ACLKDIV>;
impl ACLKDIV_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ACLKDIV {
match self.bits {
0 => ACLKDIV::FclkDiv1,
1 => ACLKDIV::FclkDiv2,
2 => ACLKDIV::FclkDiv4,
3 => ACLKDIV::FclkDiv8,
4 => ACLKDIV::FclkDiv16,
5 => ACLKDIV::FclkDiv32,
6 => ACLKDIV::FclkDiv64,
7 => ACLKDIV::FclkDiv128,
_ => unreachable!(),
}
}
#[doc = "ACLK = FCLK /1"]
#[inline(always)]
pub fn is_fclk_div_1(&self) -> bool {
*self == ACLKDIV::FclkDiv1
}
#[doc = "ACLK = FCLK /2"]
#[inline(always)]
pub fn is_fclk_div_2(&self) -> bool {
*self == ACLKDIV::FclkDiv2
}
#[doc = "ACLK = FCLK /4"]
#[inline(always)]
pub fn is_fclk_div_4(&self) -> bool {
*self == ACLKDIV::FclkDiv4
}
#[doc = "ACLK = FCLK /8"]
#[inline(always)]
pub fn is_fclk_div_8(&self) -> bool {
*self == ACLKDIV::FclkDiv8
}
#[doc = "ACLK = FCLK /16"]
#[inline(always)]
pub fn is_fclk_div_16(&self) -> bool {
*self == ACLKDIV::FclkDiv16
}
#[doc = "ACLK = FCLK /32"]
#[inline(always)]
pub fn is_fclk_div_32(&self) -> bool {
*self == ACLKDIV::FclkDiv32
}
#[doc = "ACLK = FCLK /64"]
#[inline(always)]
pub fn is_fclk_div_64(&self) -> bool {
*self == ACLKDIV::FclkDiv64
}
#[doc = "ACLK = FCLK /128"]
#[inline(always)]
pub fn is_fclk_div_128(&self) -> bool {
*self == ACLKDIV::FclkDiv128
}
}
#[doc = "Field `ACLKDIV` writer - ACLK divider"]
pub type ACLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 3, ACLKDIV, crate::Safe>;
impl<'a, REG> ACLKDIV_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ACLK = FCLK /1"]
#[inline(always)]
pub fn fclk_div_1(self) -> &'a mut crate::W<REG> {
self.variant(ACLKDIV::FclkDiv1)
}
#[doc = "ACLK = FCLK /2"]
#[inline(always)]
pub fn fclk_div_2(self) -> &'a mut crate::W<REG> {
self.variant(ACLKDIV::FclkDiv2)
}
#[doc = "ACLK = FCLK /4"]
#[inline(always)]
pub fn fclk_div_4(self) -> &'a mut crate::W<REG> {
self.variant(ACLKDIV::FclkDiv4)
}
#[doc = "ACLK = FCLK /8"]
#[inline(always)]
pub fn fclk_div_8(self) -> &'a mut crate::W<REG> {
self.variant(ACLKDIV::FclkDiv8)
}
#[doc = "ACLK = FCLK /16"]
#[inline(always)]
pub fn fclk_div_16(self) -> &'a mut crate::W<REG> {
self.variant(ACLKDIV::FclkDiv16)
}
#[doc = "ACLK = FCLK /32"]
#[inline(always)]
pub fn fclk_div_32(self) -> &'a mut crate::W<REG> {
self.variant(ACLKDIV::FclkDiv32)
}
#[doc = "ACLK = FCLK /64"]
#[inline(always)]
pub fn fclk_div_64(self) -> &'a mut crate::W<REG> {
self.variant(ACLKDIV::FclkDiv64)
}
#[doc = "ACLK = FCLK /128"]
#[inline(always)]
pub fn fclk_div_128(self) -> &'a mut crate::W<REG> {
self.variant(ACLKDIV::FclkDiv128)
}
}
#[doc = "HCLK divider\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum HCLKDIV {
#[doc = "0: HCLK = FCLK /1"]
FclkDiv1 = 0,
#[doc = "1: HCLK = FCLK /2"]
FclkDiv2 = 1,
#[doc = "2: HCLK = FCLK /4"]
FclkDiv4 = 2,
#[doc = "3: HCLK = FCLK /8"]
FclkDiv8 = 3,
}
impl From<HCLKDIV> for u8 {
#[inline(always)]
fn from(variant: HCLKDIV) -> Self {
variant as _
}
}
impl crate::FieldSpec for HCLKDIV {
type Ux = u8;
}
impl crate::IsEnum for HCLKDIV {}
#[doc = "Field `HCLKDIV` reader - HCLK divider"]
pub type HCLKDIV_R = crate::FieldReader<HCLKDIV>;
impl HCLKDIV_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> HCLKDIV {
match self.bits {
0 => HCLKDIV::FclkDiv1,
1 => HCLKDIV::FclkDiv2,
2 => HCLKDIV::FclkDiv4,
3 => HCLKDIV::FclkDiv8,
_ => unreachable!(),
}
}
#[doc = "HCLK = FCLK /1"]
#[inline(always)]
pub fn is_fclk_div_1(&self) -> bool {
*self == HCLKDIV::FclkDiv1
}
#[doc = "HCLK = FCLK /2"]
#[inline(always)]
pub fn is_fclk_div_2(&self) -> bool {
*self == HCLKDIV::FclkDiv2
}
#[doc = "HCLK = FCLK /4"]
#[inline(always)]
pub fn is_fclk_div_4(&self) -> bool {
*self == HCLKDIV::FclkDiv4
}
#[doc = "HCLK = FCLK /8"]
#[inline(always)]
pub fn is_fclk_div_8(&self) -> bool {
*self == HCLKDIV::FclkDiv8
}
}
#[doc = "Field `HCLKDIV` writer - HCLK divider"]
pub type HCLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 2, HCLKDIV, crate::Safe>;
impl<'a, REG> HCLKDIV_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "HCLK = FCLK /1"]
#[inline(always)]
pub fn fclk_div_1(self) -> &'a mut crate::W<REG> {
self.variant(HCLKDIV::FclkDiv1)
}
#[doc = "HCLK = FCLK /2"]
#[inline(always)]
pub fn fclk_div_2(self) -> &'a mut crate::W<REG> {
self.variant(HCLKDIV::FclkDiv2)
}
#[doc = "HCLK = FCLK /4"]
#[inline(always)]
pub fn fclk_div_4(self) -> &'a mut crate::W<REG> {
self.variant(HCLKDIV::FclkDiv4)
}
#[doc = "HCLK = FCLK /8"]
#[inline(always)]
pub fn fclk_div_8(self) -> &'a mut crate::W<REG> {
self.variant(HCLKDIV::FclkDiv8)
}
}
#[doc = "FCLK input clock select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum FCLK {
#[doc = "0: FCLK = FRCLK"]
Frclk = 0,
#[doc = "1: FCLK = PLLOUT clock"]
Pllout = 1,
}
impl From<FCLK> for bool {
#[inline(always)]
fn from(variant: FCLK) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `FCLK` reader - FCLK input clock select"]
pub type FCLK_R = crate::BitReader<FCLK>;
impl FCLK_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> FCLK {
match self.bits {
false => FCLK::Frclk,
true => FCLK::Pllout,
}
}
#[doc = "FCLK = FRCLK"]
#[inline(always)]
pub fn is_frclk(&self) -> bool {
*self == FCLK::Frclk
}
#[doc = "FCLK = PLLOUT clock"]
#[inline(always)]
pub fn is_pllout(&self) -> bool {
*self == FCLK::Pllout
}
}
#[doc = "Field `FCLK` writer - FCLK input clock select"]
pub type FCLK_W<'a, REG> = crate::BitWriter<'a, REG, FCLK>;
impl<'a, REG> FCLK_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "FCLK = FRCLK"]
#[inline(always)]
pub fn frclk(self) -> &'a mut crate::W<REG> {
self.variant(FCLK::Frclk)
}
#[doc = "FCLK = PLLOUT clock"]
#[inline(always)]
pub fn pllout(self) -> &'a mut crate::W<REG> {
self.variant(FCLK::Pllout)
}
}
impl R {
#[doc = "Bits 0:1 - FRCLK input clock select"]
#[inline(always)]
pub fn clkin(&self) -> CLKIN_R {
CLKIN_R::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:4 - ACLK divider"]
#[inline(always)]
pub fn aclkdiv(&self) -> ACLKDIV_R {
ACLKDIV_R::new(((self.bits >> 2) & 7) as u8)
}
#[doc = "Bits 5:6 - HCLK divider"]
#[inline(always)]
pub fn hclkdiv(&self) -> HCLKDIV_R {
HCLKDIV_R::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7 - FCLK input clock select"]
#[inline(always)]
pub fn fclk(&self) -> FCLK_R {
FCLK_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SCCTL")
.field("clkin", &self.clkin())
.field("aclkdiv", &self.aclkdiv())
.field("hclkdiv", &self.hclkdiv())
.field("fclk", &self.fclk())
.finish()
}
}
impl W {
#[doc = "Bits 0:1 - FRCLK input clock select"]
#[inline(always)]
pub fn clkin(&mut self) -> CLKIN_W<SCCTLrs> {
CLKIN_W::new(self, 0)
}
#[doc = "Bits 2:4 - ACLK divider"]
#[inline(always)]
pub fn aclkdiv(&mut self) -> ACLKDIV_W<SCCTLrs> {
ACLKDIV_W::new(self, 2)
}
#[doc = "Bits 5:6 - HCLK divider"]
#[inline(always)]
pub fn hclkdiv(&mut self) -> HCLKDIV_W<SCCTLrs> {
HCLKDIV_W::new(self, 5)
}
#[doc = "Bit 7 - FCLK input clock select"]
#[inline(always)]
pub fn fclk(&mut self) -> FCLK_W<SCCTLrs> {
FCLK_W::new(self, 7)
}
}
#[doc = "System Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`scctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SCCTLrs;
impl crate::RegisterSpec for SCCTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`scctl::R`](R) reader structure"]
impl crate::Readable for SCCTLrs {}
#[doc = "`write(|w| ..)` method takes [`scctl::W`](W) writer structure"]
impl crate::Writable for SCCTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SCCTL to value 0"]
impl crate::Resettable for SCCTLrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PLLCTL (rw) register accessor: PLL Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pllctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pllctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pllctl`]
module"]
pub type PLLCTL = crate::Reg<pllctl::PLLCTLrs>;
#[doc = "PLL Control Register"]
pub mod pllctl {
#[doc = "Register `PLLCTL` reader"]
pub type R = crate::R<PLLCTLrs>;
#[doc = "Register `PLLCTL` writer"]
pub type W = crate::W<PLLCTLrs>;
#[doc = "PLL enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum PLLEN {
#[doc = "0: Disable PLL"]
Disable = 0,
#[doc = "1: Enable PLL"]
Enable = 1,
}
impl From<PLLEN> for bool {
#[inline(always)]
fn from(variant: PLLEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `PLLEN` reader - PLL enable"]
pub type PLLEN_R = crate::BitReader<PLLEN>;
impl PLLEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> PLLEN {
match self.bits {
false => PLLEN::Disable,
true => PLLEN::Enable,
}
}
#[doc = "Disable PLL"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == PLLEN::Disable
}
#[doc = "Enable PLL"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == PLLEN::Enable
}
}
#[doc = "Field `PLLEN` writer - PLL enable"]
pub type PLLEN_W<'a, REG> = crate::BitWriter<'a, REG, PLLEN>;
impl<'a, REG> PLLEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable PLL"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(PLLEN::Disable)
}
#[doc = "Enable PLL"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(PLLEN::Enable)
}
}
#[doc = "PLL Input Divider (divider = /\\[value+2\\])\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum PLLINDIV {
#[doc = "0: PLL input divider: /2"]
Div2 = 0,
}
impl From<PLLINDIV> for u8 {
#[inline(always)]
fn from(variant: PLLINDIV) -> Self {
variant as _
}
}
impl crate::FieldSpec for PLLINDIV {
type Ux = u8;
}
impl crate::IsEnum for PLLINDIV {}
#[doc = "Field `PLLINDIV` reader - PLL Input Divider (divider = /\\[value+2\\])"]
pub type PLLINDIV_R = crate::FieldReader<PLLINDIV>;
impl PLLINDIV_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<PLLINDIV> {
match self.bits {
0 => Some(PLLINDIV::Div2),
_ => None,
}
}
#[doc = "PLL input divider: /2"]
#[inline(always)]
pub fn is_div_2(&self) -> bool {
*self == PLLINDIV::Div2
}
}
#[doc = "Field `PLLINDIV` writer - PLL Input Divider (divider = /\\[value+2\\])"]
pub type PLLINDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 5, PLLINDIV>;
impl<'a, REG> PLLINDIV_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PLL input divider: /2"]
#[inline(always)]
pub fn div_2(self) -> &'a mut crate::W<REG> {
self.variant(PLLINDIV::Div2)
}
}
#[doc = "PLL Feedback Divider (divider = /\\[value + 2\\])\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum PLLFBDIV {
#[doc = "0: PLL feedback divider: /2"]
Div2 = 0,
}
impl From<PLLFBDIV> for u16 {
#[inline(always)]
fn from(variant: PLLFBDIV) -> Self {
variant as _
}
}
impl crate::FieldSpec for PLLFBDIV {
type Ux = u16;
}
impl crate::IsEnum for PLLFBDIV {}
#[doc = "Field `PLLFBDIV` reader - PLL Feedback Divider (divider = /\\[value + 2\\])"]
pub type PLLFBDIV_R = crate::FieldReader<PLLFBDIV>;
impl PLLFBDIV_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<PLLFBDIV> {
match self.bits {
0 => Some(PLLFBDIV::Div2),
_ => None,
}
}
#[doc = "PLL feedback divider: /2"]
#[inline(always)]
pub fn is_div_2(&self) -> bool {
*self == PLLFBDIV::Div2
}
}
#[doc = "Field `PLLFBDIV` writer - PLL Feedback Divider (divider = /\\[value + 2\\])"]
pub type PLLFBDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 9, PLLFBDIV>;
impl<'a, REG> PLLFBDIV_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u16>,
{
#[doc = "PLL feedback divider: /2"]
#[inline(always)]
pub fn div_2(self) -> &'a mut crate::W<REG> {
self.variant(PLLFBDIV::Div2)
}
}
#[doc = "PLL Output Divider (divider = /\\[value+1\\], 0 reserved)\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum PLLOUTDIV {
#[doc = "1: PLL output divider: /1"]
Div1 = 1,
}
impl From<PLLOUTDIV> for u8 {
#[inline(always)]
fn from(variant: PLLOUTDIV) -> Self {
variant as _
}
}
impl crate::FieldSpec for PLLOUTDIV {
type Ux = u8;
}
impl crate::IsEnum for PLLOUTDIV {}
#[doc = "Field `PLLOUTDIV` reader - PLL Output Divider (divider = /\\[value+1\\], 0 reserved)"]
pub type PLLOUTDIV_R = crate::FieldReader<PLLOUTDIV>;
impl PLLOUTDIV_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<PLLOUTDIV> {
match self.bits {
1 => Some(PLLOUTDIV::Div1),
_ => None,
}
}
#[doc = "PLL output divider: /1"]
#[inline(always)]
pub fn is_div_1(&self) -> bool {
*self == PLLOUTDIV::Div1
}
}
#[doc = "Field `PLLOUTDIV` writer - PLL Output Divider (divider = /\\[value+1\\], 0 reserved)"]
pub type PLLOUTDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PLLOUTDIV>;
impl<'a, REG> PLLOUTDIV_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PLL output divider: /1"]
#[inline(always)]
pub fn div_1(self) -> &'a mut crate::W<REG> {
self.variant(PLLOUTDIV::Div1)
}
}
impl R {
#[doc = "Bit 0 - PLL enable"]
#[inline(always)]
pub fn pllen(&self) -> PLLEN_R {
PLLEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bits 2:6 - PLL Input Divider (divider = /\\[value+2\\])"]
#[inline(always)]
pub fn pllindiv(&self) -> PLLINDIV_R {
PLLINDIV_R::new(((self.bits >> 2) & 0x1f) as u8)
}
#[doc = "Bits 7:15 - PLL Feedback Divider (divider = /\\[value + 2\\])"]
#[inline(always)]
pub fn pllfbdiv(&self) -> PLLFBDIV_R {
PLLFBDIV_R::new(((self.bits >> 7) & 0x01ff) as u16)
}
#[doc = "Bits 16:19 - PLL Output Divider (divider = /\\[value+1\\], 0 reserved)"]
#[inline(always)]
pub fn plloutdiv(&self) -> PLLOUTDIV_R {
PLLOUTDIV_R::new(((self.bits >> 16) & 0x0f) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PLLCTL")
.field("pllen", &self.pllen())
.field("pllindiv", &self.pllindiv())
.field("pllfbdiv", &self.pllfbdiv())
.field("plloutdiv", &self.plloutdiv())
.finish()
}
}
impl W {
#[doc = "Bit 0 - PLL enable"]
#[inline(always)]
pub fn pllen(&mut self) -> PLLEN_W<PLLCTLrs> {
PLLEN_W::new(self, 0)
}
#[doc = "Bits 2:6 - PLL Input Divider (divider = /\\[value+2\\])"]
#[inline(always)]
pub fn pllindiv(&mut self) -> PLLINDIV_W<PLLCTLrs> {
PLLINDIV_W::new(self, 2)
}
#[doc = "Bits 7:15 - PLL Feedback Divider (divider = /\\[value + 2\\])"]
#[inline(always)]
pub fn pllfbdiv(&mut self) -> PLLFBDIV_W<PLLCTLrs> {
PLLFBDIV_W::new(self, 7)
}
#[doc = "Bits 16:19 - PLL Output Divider (divider = /\\[value+1\\], 0 reserved)"]
#[inline(always)]
pub fn plloutdiv(&mut self) -> PLLOUTDIV_W<PLLCTLrs> {
PLLOUTDIV_W::new(self, 16)
}
}
#[doc = "PLL Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pllctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pllctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PLLCTLrs;
impl crate::RegisterSpec for PLLCTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`pllctl::R`](R) reader structure"]
impl crate::Readable for PLLCTLrs {}
#[doc = "`write(|w| ..)` method takes [`pllctl::W`](W) writer structure"]
impl crate::Writable for PLLCTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PLLCTL to value 0"]
impl crate::Resettable for PLLCTLrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ROSCCTL (rw) register accessor: Ring Oscillator Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`roscctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`roscctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@roscctl`]
module"]
pub type ROSCCTL = crate::Reg<roscctl::ROSCCTLrs>;
#[doc = "Ring Oscillator Control Register"]
pub mod roscctl {
#[doc = "Register `ROSCCTL` reader"]
pub type R = crate::R<ROSCCTLrs>;
#[doc = "Register `ROSCCTL` writer"]
pub type W = crate::W<ROSCCTLrs>;
#[doc = "Ring Oscillator Enable\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ROSCEN {
#[doc = "0: Disable Ring Oscillator"]
Disable = 0,
#[doc = "1: Enable Ring Oscillator"]
Enable = 1,
}
impl From<ROSCEN> for bool {
#[inline(always)]
fn from(variant: ROSCEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ROSCEN` reader - Ring Oscillator Enable"]
pub type ROSCEN_R = crate::BitReader<ROSCEN>;
impl ROSCEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ROSCEN {
match self.bits {
false => ROSCEN::Disable,
true => ROSCEN::Enable,
}
}
#[doc = "Disable Ring Oscillator"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == ROSCEN::Disable
}
#[doc = "Enable Ring Oscillator"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == ROSCEN::Enable
}
}
#[doc = "Field `ROSCEN` writer - Ring Oscillator Enable"]
pub type ROSCEN_W<'a, REG> = crate::BitWriter<'a, REG, ROSCEN>;
impl<'a, REG> ROSCEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable Ring Oscillator"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(ROSCEN::Disable)
}
#[doc = "Enable Ring Oscillator"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(ROSCEN::Enable)
}
}
#[doc = "Ring Oscillator Frequency Setting\n\nValue on reset: 3"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum ROSCP {
#[doc = "0: Set Ring Oscillator to 28.7 MHz"]
Mhz28_7 = 0,
#[doc = "1: Set Ring Oscillator to 15.3 MHz"]
Mhz15_3 = 1,
#[doc = "2: Set Ring Oscillator to 10.7 MHz"]
Mhz10_7 = 2,
#[doc = "3: Set Ring Oscillator to 8.3 MHz"]
Mhz8_3 = 3,
}
impl From<ROSCP> for u8 {
#[inline(always)]
fn from(variant: ROSCP) -> Self {
variant as _
}
}
impl crate::FieldSpec for ROSCP {
type Ux = u8;
}
impl crate::IsEnum for ROSCP {}
#[doc = "Field `ROSCP` reader - Ring Oscillator Frequency Setting"]
pub type ROSCP_R = crate::FieldReader<ROSCP>;
impl ROSCP_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ROSCP {
match self.bits {
0 => ROSCP::Mhz28_7,
1 => ROSCP::Mhz15_3,
2 => ROSCP::Mhz10_7,
3 => ROSCP::Mhz8_3,
_ => unreachable!(),
}
}
#[doc = "Set Ring Oscillator to 28.7 MHz"]
#[inline(always)]
pub fn is_mhz_28_7(&self) -> bool {
*self == ROSCP::Mhz28_7
}
#[doc = "Set Ring Oscillator to 15.3 MHz"]
#[inline(always)]
pub fn is_mhz_15_3(&self) -> bool {
*self == ROSCP::Mhz15_3
}
#[doc = "Set Ring Oscillator to 10.7 MHz"]
#[inline(always)]
pub fn is_mhz_10_7(&self) -> bool {
*self == ROSCP::Mhz10_7
}
#[doc = "Set Ring Oscillator to 8.3 MHz"]
#[inline(always)]
pub fn is_mhz_8_3(&self) -> bool {
*self == ROSCP::Mhz8_3
}
}
#[doc = "Field `ROSCP` writer - Ring Oscillator Frequency Setting"]
pub type ROSCP_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ROSCP, crate::Safe>;
impl<'a, REG> ROSCP_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Set Ring Oscillator to 28.7 MHz"]
#[inline(always)]
pub fn mhz_28_7(self) -> &'a mut crate::W<REG> {
self.variant(ROSCP::Mhz28_7)
}
#[doc = "Set Ring Oscillator to 15.3 MHz"]
#[inline(always)]
pub fn mhz_15_3(self) -> &'a mut crate::W<REG> {
self.variant(ROSCP::Mhz15_3)
}
#[doc = "Set Ring Oscillator to 10.7 MHz"]
#[inline(always)]
pub fn mhz_10_7(self) -> &'a mut crate::W<REG> {
self.variant(ROSCP::Mhz10_7)
}
#[doc = "Set Ring Oscillator to 8.3 MHz"]
#[inline(always)]
pub fn mhz_8_3(self) -> &'a mut crate::W<REG> {
self.variant(ROSCP::Mhz8_3)
}
}
impl R {
#[doc = "Bit 0 - Ring Oscillator Enable"]
#[inline(always)]
pub fn roscen(&self) -> ROSCEN_R {
ROSCEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2 - Ring Oscillator Frequency Setting"]
#[inline(always)]
pub fn roscp(&self) -> ROSCP_R {
ROSCP_R::new(((self.bits >> 1) & 3) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ROSCCTL")
.field("roscen", &self.roscen())
.field("roscp", &self.roscp())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Ring Oscillator Enable"]
#[inline(always)]
pub fn roscen(&mut self) -> ROSCEN_W<ROSCCTLrs> {
ROSCEN_W::new(self, 0)
}
#[doc = "Bits 1:2 - Ring Oscillator Frequency Setting"]
#[inline(always)]
pub fn roscp(&mut self) -> ROSCP_W<ROSCCTLrs> {
ROSCP_W::new(self, 1)
}
}
#[doc = "Ring Oscillator Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`roscctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`roscctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ROSCCTLrs;
impl crate::RegisterSpec for ROSCCTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`roscctl::R`](R) reader structure"]
impl crate::Readable for ROSCCTLrs {}
#[doc = "`write(|w| ..)` method takes [`roscctl::W`](W) writer structure"]
impl crate::Writable for ROSCCTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ROSCCTL to value 0x07"]
impl crate::Resettable for ROSCCTLrs {
const RESET_VALUE: u32 = 0x07;
}
}
#[doc = "XTALCTL (rw) register accessor: Crystal Driver Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`xtalctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xtalctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@xtalctl`]
module"]
pub type XTALCTL = crate::Reg<xtalctl::XTALCTLrs>;
#[doc = "Crystal Driver Control Register"]
pub mod xtalctl {
#[doc = "Register `XTALCTL` reader"]
pub type R = crate::R<XTALCTLrs>;
#[doc = "Register `XTALCTL` writer"]
pub type W = crate::W<XTALCTLrs>;
#[doc = "Enable XTAL driver\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum XTALEN {
#[doc = "0: Disable XTAL Driver"]
Disable = 0,
#[doc = "1: Enable XTAL Driver"]
Enable = 1,
}
impl From<XTALEN> for bool {
#[inline(always)]
fn from(variant: XTALEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `XTALEN` reader - Enable XTAL driver"]
pub type XTALEN_R = crate::BitReader<XTALEN>;
impl XTALEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> XTALEN {
match self.bits {
false => XTALEN::Disable,
true => XTALEN::Enable,
}
}
#[doc = "Disable XTAL Driver"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == XTALEN::Disable
}
#[doc = "Enable XTAL Driver"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == XTALEN::Enable
}
}
#[doc = "Field `XTALEN` writer - Enable XTAL driver"]
pub type XTALEN_W<'a, REG> = crate::BitWriter<'a, REG, XTALEN>;
impl<'a, REG> XTALEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable XTAL Driver"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(XTALEN::Disable)
}
#[doc = "Enable XTAL Driver"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(XTALEN::Enable)
}
}
impl R {
#[doc = "Bit 0 - Enable XTAL driver"]
#[inline(always)]
pub fn xtalen(&self) -> XTALEN_R {
XTALEN_R::new((self.bits & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("XTALCTL")
.field("xtalen", &self.xtalen())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Enable XTAL driver"]
#[inline(always)]
pub fn xtalen(&mut self) -> XTALEN_W<XTALCTLrs> {
XTALEN_W::new(self, 0)
}
}
#[doc = "Crystal Driver Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`xtalctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xtalctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct XTALCTLrs;
impl crate::RegisterSpec for XTALCTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`xtalctl::R`](R) reader structure"]
impl crate::Readable for XTALCTLrs {}
#[doc = "`write(|w| ..)` method takes [`xtalctl::W`](W) writer structure"]
impl crate::Writable for XTALCTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets XTALCTL to value 0"]
impl crate::Resettable for XTALCTLrs {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "FLASH Memory Controller"]
pub struct MEMCTL {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for MEMCTL {}
impl MEMCTL {
#[doc = r"Pointer to the register block"]
pub const PTR: *const memctl::RegisterBlock = 0x4002_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const memctl::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for MEMCTL {
type Target = memctl::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for MEMCTL {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("MEMCTL").finish()
}
}
#[doc = "FLASH Memory Controller"]
pub mod memctl {
#[repr(C)]
#[derive(Debug)]
#[doc = "Register block"]
pub struct RegisterBlock {
flashlock: FLASHLOCK,
flashstatus: FLASHSTATUS,
flashpage: FLASHPAGE,
_reserved3: [u8; 0x08],
flashperase: FLASHPERASE,
_reserved4: [u8; 0x0c],
swdaccess: SWDACCESS,
flashwstate: FLASHWSTATE,
flashbwrite: FLASHBWRITE,
}
impl RegisterBlock {
#[doc = "0x00 - FLASH Lock Register"]
#[inline(always)]
pub const fn flashlock(&self) -> &FLASHLOCK {
&self.flashlock
}
#[doc = "0x04 - FLASH Status Register"]
#[inline(always)]
pub const fn flashstatus(&self) -> &FLASHSTATUS {
&self.flashstatus
}
#[doc = "0x08 - FLASH page select register"]
#[inline(always)]
pub const fn flashpage(&self) -> &FLASHPAGE {
&self.flashpage
}
#[doc = "0x14 - FLASH page erase register"]
#[inline(always)]
pub const fn flashperase(&self) -> &FLASHPERASE {
&self.flashperase
}
#[doc = "0x24 - SWD access status"]
#[inline(always)]
pub const fn swdaccess(&self) -> &SWDACCESS {
&self.swdaccess
}
#[doc = "0x28 - FLASH Wait State Register"]
#[inline(always)]
pub const fn flashwstate(&self) -> &FLASHWSTATE {
&self.flashwstate
}
#[doc = "0x2c - FLASH Buffered Write Data"]
#[inline(always)]
pub const fn flashbwrite(&self) -> &FLASHBWRITE {
&self.flashbwrite
}
}
#[doc = "FLASHLOCK (rw) register accessor: FLASH Lock Register\n\nYou can [`read`](crate::Reg::read) this register and get [`flashlock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flashlock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flashlock`]
module"]
pub type FLASHLOCK = crate::Reg<flashlock::FLASHLOCKrs>;
#[doc = "FLASH Lock Register"]
pub mod flashlock {
#[doc = "Register `FLASHLOCK` reader"]
pub type R = crate::R<FLASHLOCKrs>;
#[doc = "Register `FLASHLOCK` writer"]
pub type W = crate::W<FLASHLOCKrs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "FLASH Lock Register\n\nYou can [`read`](crate::Reg::read) this register and get [`flashlock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flashlock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASHLOCKrs;
impl crate::RegisterSpec for FLASHLOCKrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`flashlock::R`](R) reader structure"]
impl crate::Readable for FLASHLOCKrs {}
#[doc = "`write(|w| ..)` method takes [`flashlock::W`](W) writer structure"]
impl crate::Writable for FLASHLOCKrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASHLOCK to value 0"]
impl crate::Resettable for FLASHLOCKrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "FLASHSTATUS (rw) register accessor: FLASH Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`flashstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flashstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flashstatus`]
module"]
pub type FLASHSTATUS = crate::Reg<flashstatus::FLASHSTATUSrs>;
#[doc = "FLASH Status Register"]
pub mod flashstatus {
#[doc = "Register `FLASHSTATUS` reader"]
pub type R = crate::R<FLASHSTATUSrs>;
#[doc = "Register `FLASHSTATUS` writer"]
pub type W = crate::W<FLASHSTATUSrs>;
#[doc = "Buffered Write Active\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum WRITE {
#[doc = "0: Buffered write inactive"]
Inactive = 0,
#[doc = "1: Buffered write active"]
Active = 1,
}
impl From<WRITE> for bool {
#[inline(always)]
fn from(variant: WRITE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `WRITE` reader - Buffered Write Active"]
pub type WRITE_R = crate::BitReader<WRITE>;
impl WRITE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> WRITE {
match self.bits {
false => WRITE::Inactive,
true => WRITE::Active,
}
}
#[doc = "Buffered write inactive"]
#[inline(always)]
pub fn is_inactive(&self) -> bool {
*self == WRITE::Inactive
}
#[doc = "Buffered write active"]
#[inline(always)]
pub fn is_active(&self) -> bool {
*self == WRITE::Active
}
}
#[doc = "Field `WRITE` writer - Buffered Write Active"]
pub type WRITE_W<'a, REG> = crate::BitWriter<'a, REG, WRITE>;
impl<'a, REG> WRITE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Buffered write inactive"]
#[inline(always)]
pub fn inactive(self) -> &'a mut crate::W<REG> {
self.variant(WRITE::Inactive)
}
#[doc = "Buffered write active"]
#[inline(always)]
pub fn active(self) -> &'a mut crate::W<REG> {
self.variant(WRITE::Active)
}
}
#[doc = "Page Erase Active\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum PERASE {
#[doc = "0: Page erase finished or no page erase in progress"]
Inactive = 0,
#[doc = "1: Page erase in progress"]
Active = 1,
}
impl From<PERASE> for bool {
#[inline(always)]
fn from(variant: PERASE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `PERASE` reader - Page Erase Active"]
pub type PERASE_R = crate::BitReader<PERASE>;
impl PERASE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> PERASE {
match self.bits {
false => PERASE::Inactive,
true => PERASE::Active,
}
}
#[doc = "Page erase finished or no page erase in progress"]
#[inline(always)]
pub fn is_inactive(&self) -> bool {
*self == PERASE::Inactive
}
#[doc = "Page erase in progress"]
#[inline(always)]
pub fn is_active(&self) -> bool {
*self == PERASE::Active
}
}
#[doc = "Field `PERASE` writer - Page Erase Active"]
pub type PERASE_W<'a, REG> = crate::BitWriter<'a, REG, PERASE>;
impl<'a, REG> PERASE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Page erase finished or no page erase in progress"]
#[inline(always)]
pub fn inactive(self) -> &'a mut crate::W<REG> {
self.variant(PERASE::Inactive)
}
#[doc = "Page erase in progress"]
#[inline(always)]
pub fn active(self) -> &'a mut crate::W<REG> {
self.variant(PERASE::Active)
}
}
impl R {
#[doc = "Bit 0 - Buffered Write Active"]
#[inline(always)]
pub fn write(&self) -> WRITE_R {
WRITE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Page Erase Active"]
#[inline(always)]
pub fn perase(&self) -> PERASE_R {
PERASE_R::new(((self.bits >> 1) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASHSTATUS")
.field("write", &self.write())
.field("perase", &self.perase())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Buffered Write Active"]
#[inline(always)]
pub fn write(&mut self) -> WRITE_W<FLASHSTATUSrs> {
WRITE_W::new(self, 0)
}
#[doc = "Bit 1 - Page Erase Active"]
#[inline(always)]
pub fn perase(&mut self) -> PERASE_W<FLASHSTATUSrs> {
PERASE_W::new(self, 1)
}
}
#[doc = "FLASH Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`flashstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flashstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASHSTATUSrs;
impl crate::RegisterSpec for FLASHSTATUSrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`flashstatus::R`](R) reader structure"]
impl crate::Readable for FLASHSTATUSrs {}
#[doc = "`write(|w| ..)` method takes [`flashstatus::W`](W) writer structure"]
impl crate::Writable for FLASHSTATUSrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASHSTATUS to value 0"]
impl crate::Resettable for FLASHSTATUSrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "FLASHPAGE (rw) register accessor: FLASH page select register\n\nYou can [`read`](crate::Reg::read) this register and get [`flashpage::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flashpage::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flashpage`]
module"]
pub type FLASHPAGE = crate::Reg<flashpage::FLASHPAGErs>;
#[doc = "FLASH page select register"]
pub mod flashpage {
#[doc = "Register `FLASHPAGE` reader"]
pub type R = crate::R<FLASHPAGErs>;
#[doc = "Register `FLASHPAGE` writer"]
pub type W = crate::W<FLASHPAGErs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "FLASH page select register\n\nYou can [`read`](crate::Reg::read) this register and get [`flashpage::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flashpage::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASHPAGErs;
impl crate::RegisterSpec for FLASHPAGErs {
type Ux = u32;
}
#[doc = "`read()` method returns [`flashpage::R`](R) reader structure"]
impl crate::Readable for FLASHPAGErs {}
#[doc = "`write(|w| ..)` method takes [`flashpage::W`](W) writer structure"]
impl crate::Writable for FLASHPAGErs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASHPAGE to value 0"]
impl crate::Resettable for FLASHPAGErs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "FLASHPERASE (rw) register accessor: FLASH page erase register\n\nYou can [`read`](crate::Reg::read) this register and get [`flashperase::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flashperase::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flashperase`]
module"]
pub type FLASHPERASE = crate::Reg<flashperase::FLASHPERASErs>;
#[doc = "FLASH page erase register"]
pub mod flashperase {
#[doc = "Register `FLASHPERASE` reader"]
pub type R = crate::R<FLASHPERASErs>;
#[doc = "Register `FLASHPERASE` writer"]
pub type W = crate::W<FLASHPERASErs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "FLASH page erase register\n\nYou can [`read`](crate::Reg::read) this register and get [`flashperase::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flashperase::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASHPERASErs;
impl crate::RegisterSpec for FLASHPERASErs {
type Ux = u32;
}
#[doc = "`read()` method returns [`flashperase::R`](R) reader structure"]
impl crate::Readable for FLASHPERASErs {}
#[doc = "`write(|w| ..)` method takes [`flashperase::W`](W) writer structure"]
impl crate::Writable for FLASHPERASErs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASHPERASE to value 0"]
impl crate::Resettable for FLASHPERASErs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SWDACCESS (rw) register accessor: SWD access status\n\nYou can [`read`](crate::Reg::read) this register and get [`swdaccess::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdaccess::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swdaccess`]
module"]
pub type SWDACCESS = crate::Reg<swdaccess::SWDACCESSrs>;
#[doc = "SWD access status"]
pub mod swdaccess {
#[doc = "Register `SWDACCESS` reader"]
pub type R = crate::R<SWDACCESSrs>;
#[doc = "Register `SWDACCESS` writer"]
pub type W = crate::W<SWDACCESSrs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "SWD access status\n\nYou can [`read`](crate::Reg::read) this register and get [`swdaccess::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swdaccess::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SWDACCESSrs;
impl crate::RegisterSpec for SWDACCESSrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`swdaccess::R`](R) reader structure"]
impl crate::Readable for SWDACCESSrs {}
#[doc = "`write(|w| ..)` method takes [`swdaccess::W`](W) writer structure"]
impl crate::Writable for SWDACCESSrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SWDACCESS to value 0"]
impl crate::Resettable for SWDACCESSrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "FLASHWSTATE (rw) register accessor: FLASH Wait State Register\n\nYou can [`read`](crate::Reg::read) this register and get [`flashwstate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flashwstate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flashwstate`]
module"]
pub type FLASHWSTATE = crate::Reg<flashwstate::FLASHWSTATErs>;
#[doc = "FLASH Wait State Register"]
pub mod flashwstate {
#[doc = "Register `FLASHWSTATE` reader"]
pub type R = crate::R<FLASHWSTATErs>;
#[doc = "Register `FLASHWSTATE` writer"]
pub type W = crate::W<FLASHWSTATErs>;
#[doc = "FLASH access wait state\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum WSTATE {
#[doc = "0: 0 FLASH wait states"]
_0 = 0,
#[doc = "1: 1 FLASH wait states"]
_1 = 1,
#[doc = "2: 2 FLASH wait states"]
_2 = 2,
#[doc = "3: 3 FLASH wait states"]
_3 = 3,
}
impl From<WSTATE> for u8 {
#[inline(always)]
fn from(variant: WSTATE) -> Self {
variant as _
}
}
impl crate::FieldSpec for WSTATE {
type Ux = u8;
}
impl crate::IsEnum for WSTATE {}
#[doc = "Field `WSTATE` reader - FLASH access wait state"]
pub type WSTATE_R = crate::FieldReader<WSTATE>;
impl WSTATE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> WSTATE {
match self.bits {
0 => WSTATE::_0,
1 => WSTATE::_1,
2 => WSTATE::_2,
3 => WSTATE::_3,
_ => unreachable!(),
}
}
#[doc = "0 FLASH wait states"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == WSTATE::_0
}
#[doc = "1 FLASH wait states"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == WSTATE::_1
}
#[doc = "2 FLASH wait states"]
#[inline(always)]
pub fn is_2(&self) -> bool {
*self == WSTATE::_2
}
#[doc = "3 FLASH wait states"]
#[inline(always)]
pub fn is_3(&self) -> bool {
*self == WSTATE::_3
}
}
#[doc = "Field `WSTATE` writer - FLASH access wait state"]
pub type WSTATE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, WSTATE, crate::Safe>;
impl<'a, REG> WSTATE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "0 FLASH wait states"]
#[inline(always)]
pub fn _0(self) -> &'a mut crate::W<REG> {
self.variant(WSTATE::_0)
}
#[doc = "1 FLASH wait states"]
#[inline(always)]
pub fn _1(self) -> &'a mut crate::W<REG> {
self.variant(WSTATE::_1)
}
#[doc = "2 FLASH wait states"]
#[inline(always)]
pub fn _2(self) -> &'a mut crate::W<REG> {
self.variant(WSTATE::_2)
}
#[doc = "3 FLASH wait states"]
#[inline(always)]
pub fn _3(self) -> &'a mut crate::W<REG> {
self.variant(WSTATE::_3)
}
}
impl R {
#[doc = "Bits 0:1 - FLASH access wait state"]
#[inline(always)]
pub fn wstate(&self) -> WSTATE_R {
WSTATE_R::new((self.bits & 3) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASHWSTATE")
.field("wstate", &self.wstate())
.finish()
}
}
impl W {
#[doc = "Bits 0:1 - FLASH access wait state"]
#[inline(always)]
pub fn wstate(&mut self) -> WSTATE_W<FLASHWSTATErs> {
WSTATE_W::new(self, 0)
}
}
#[doc = "FLASH Wait State Register\n\nYou can [`read`](crate::Reg::read) this register and get [`flashwstate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flashwstate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASHWSTATErs;
impl crate::RegisterSpec for FLASHWSTATErs {
type Ux = u32;
}
#[doc = "`read()` method returns [`flashwstate::R`](R) reader structure"]
impl crate::Readable for FLASHWSTATErs {}
#[doc = "`write(|w| ..)` method takes [`flashwstate::W`](W) writer structure"]
impl crate::Writable for FLASHWSTATErs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASHWSTATE to value 0"]
impl crate::Resettable for FLASHWSTATErs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "FLASHBWRITE (rw) register accessor: FLASH Buffered Write Data\n\nYou can [`read`](crate::Reg::read) this register and get [`flashbwrite::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flashbwrite::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flashbwrite`]
module"]
pub type FLASHBWRITE = crate::Reg<flashbwrite::FLASHBWRITErs>;
#[doc = "FLASH Buffered Write Data"]
pub mod flashbwrite {
#[doc = "Register `FLASHBWRITE` reader"]
pub type R = crate::R<FLASHBWRITErs>;
#[doc = "Register `FLASHBWRITE` writer"]
pub type W = crate::W<FLASHBWRITErs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "FLASH Buffered Write Data\n\nYou can [`read`](crate::Reg::read) this register and get [`flashbwrite::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flashbwrite::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FLASHBWRITErs;
impl crate::RegisterSpec for FLASHBWRITErs {
type Ux = u32;
}
#[doc = "`read()` method returns [`flashbwrite::R`](R) reader structure"]
impl crate::Readable for FLASHBWRITErs {}
#[doc = "`write(|w| ..)` method takes [`flashbwrite::W`](W) writer structure"]
impl crate::Writable for FLASHBWRITErs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASHBWRITE to value 0"]
impl crate::Resettable for FLASHBWRITErs {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "Watchdog Timer"]
pub struct WDT {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for WDT {}
impl WDT {
#[doc = r"Pointer to the register block"]
pub const PTR: *const wdt::RegisterBlock = 0x4003_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const wdt::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for WDT {
type Target = wdt::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for WDT {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("WDT").finish()
}
}
#[doc = "Watchdog Timer"]
pub mod wdt {
#[repr(C)]
#[derive(Debug)]
#[doc = "Register block"]
pub struct RegisterBlock {
wdtctl: WDTCTL,
wdtcdv: WDTCDV,
wdtctr: WDTCTR,
}
impl RegisterBlock {
#[doc = "0x00 - Watchdog Timer Control Register"]
#[inline(always)]
pub const fn wdtctl(&self) -> &WDTCTL {
&self.wdtctl
}
#[doc = "0x04 - Watchdog Timer Count-down Value Register"]
#[inline(always)]
pub const fn wdtcdv(&self) -> &WDTCDV {
&self.wdtcdv
}
#[doc = "0x08 - Watchdog Timer Counter Register"]
#[inline(always)]
pub const fn wdtctr(&self) -> &WDTCTR {
&self.wdtctr
}
}
#[doc = "WDTCTL (rw) register accessor: Watchdog Timer Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtctl`]
module"]
pub type WDTCTL = crate::Reg<wdtctl::WDTCTLrs>;
#[doc = "Watchdog Timer Control Register"]
pub mod wdtctl {
#[doc = "Register `WDTCTL` reader"]
pub type R = crate::R<WDTCTLrs>;
#[doc = "Register `WDTCTL` writer"]
pub type W = crate::W<WDTCTLrs>;
#[doc = "Watchdog Timer Counter Reset\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum WDTCTRRST {
#[doc = "5: WDTCTL Reset Key"]
Key = 5,
}
impl From<WDTCTRRST> for u8 {
#[inline(always)]
fn from(variant: WDTCTRRST) -> Self {
variant as _
}
}
impl crate::FieldSpec for WDTCTRRST {
type Ux = u8;
}
impl crate::IsEnum for WDTCTRRST {}
#[doc = "Field `WDTCTRRST` reader - Watchdog Timer Counter Reset"]
pub type WDTCTRRST_R = crate::FieldReader<WDTCTRRST>;
impl WDTCTRRST_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<WDTCTRRST> {
match self.bits {
5 => Some(WDTCTRRST::Key),
_ => None,
}
}
#[doc = "WDTCTL Reset Key"]
#[inline(always)]
pub fn is_key(&self) -> bool {
*self == WDTCTRRST::Key
}
}
#[doc = "Field `WDTCTRRST` writer - Watchdog Timer Counter Reset"]
pub type WDTCTRRST_W<'a, REG> = crate::FieldWriter<'a, REG, 3, WDTCTRRST>;
impl<'a, REG> WDTCTRRST_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "WDTCTL Reset Key"]
#[inline(always)]
pub fn key(self) -> &'a mut crate::W<REG> {
self.variant(WDTCTRRST::Key)
}
}
#[doc = "Watchdog Interval Timer Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum WDTINTEN {
#[doc = "0: Watchdog timer interval interrupt disabled"]
Disabled = 0,
#[doc = "1: Watchdog timer interval interrupt enabled"]
Enabled = 1,
}
impl From<WDTINTEN> for bool {
#[inline(always)]
fn from(variant: WDTINTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `WDTINTEN` reader - Watchdog Interval Timer Interrupt Enable"]
pub type WDTINTEN_R = crate::BitReader<WDTINTEN>;
impl WDTINTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> WDTINTEN {
match self.bits {
false => WDTINTEN::Disabled,
true => WDTINTEN::Enabled,
}
}
#[doc = "Watchdog timer interval interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == WDTINTEN::Disabled
}
#[doc = "Watchdog timer interval interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == WDTINTEN::Enabled
}
}
#[doc = "Field `WDTINTEN` writer - Watchdog Interval Timer Interrupt Enable"]
pub type WDTINTEN_W<'a, REG> = crate::BitWriter<'a, REG, WDTINTEN>;
impl<'a, REG> WDTINTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Watchdog timer interval interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(WDTINTEN::Disabled)
}
#[doc = "Watchdog timer interval interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(WDTINTEN::Enabled)
}
}
#[doc = "Watchdog Interval Timer Interrupt Flag\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum WDTINT {
#[doc = "0: Watchdog timer interrupt flag clear"]
Clear = 0,
#[doc = "1: Watchdog timer interrupt flag set"]
Set = 1,
}
impl From<WDTINT> for bool {
#[inline(always)]
fn from(variant: WDTINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `WDTINT` reader - Watchdog Interval Timer Interrupt Flag"]
pub type WDTINT_R = crate::BitReader<WDTINT>;
impl WDTINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> WDTINT {
match self.bits {
false => WDTINT::Clear,
true => WDTINT::Set,
}
}
#[doc = "Watchdog timer interrupt flag clear"]
#[inline(always)]
pub fn is_clear(&self) -> bool {
*self == WDTINT::Clear
}
#[doc = "Watchdog timer interrupt flag set"]
#[inline(always)]
pub fn is_set(&self) -> bool {
*self == WDTINT::Set
}
}
#[doc = "Watchdog Timer Device Reset Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum WDTRESETEN {
#[doc = "0: Watchdog timer device reset disabled"]
Disabled = 0,
#[doc = "1: Watchdog timer device reset enabled"]
Enabled = 1,
}
impl From<WDTRESETEN> for bool {
#[inline(always)]
fn from(variant: WDTRESETEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `WDTRESETEN` reader - Watchdog Timer Device Reset Enable"]
pub type WDTRESETEN_R = crate::BitReader<WDTRESETEN>;
impl WDTRESETEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> WDTRESETEN {
match self.bits {
false => WDTRESETEN::Disabled,
true => WDTRESETEN::Enabled,
}
}
#[doc = "Watchdog timer device reset disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == WDTRESETEN::Disabled
}
#[doc = "Watchdog timer device reset enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == WDTRESETEN::Enabled
}
}
#[doc = "Field `WDTRESETEN` writer - Watchdog Timer Device Reset Enable"]
pub type WDTRESETEN_W<'a, REG> = crate::BitWriter<'a, REG, WDTRESETEN>;
impl<'a, REG> WDTRESETEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Watchdog timer device reset disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(WDTRESETEN::Disabled)
}
#[doc = "Watchdog timer device reset enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(WDTRESETEN::Enabled)
}
}
#[doc = "Watchdog Timer Input Clock Divider\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum WDTCLKDIV {
#[doc = "0: WDT clock divider: /2"]
Div2 = 0,
#[doc = "1: WDT clock divider: /4"]
Div4 = 1,
#[doc = "2: WDT clock divider: /8"]
Div8 = 2,
#[doc = "3: WDT clock divider: /16"]
Div16 = 3,
#[doc = "4: WDT clock divider: /32"]
Div32 = 4,
#[doc = "5: WDT clock divider: /64"]
Div64 = 5,
#[doc = "6: WDT clock divider: /128"]
Div128 = 6,
#[doc = "7: WDT clock divider: /256"]
Div256 = 7,
#[doc = "8: WDT clock divider: /512"]
Div512 = 8,
#[doc = "9: WDT clock divider: /1024"]
Div1024 = 9,
#[doc = "10: WDT clock divider: /2048"]
Div2048 = 10,
#[doc = "11: WDT clock divider: /4096"]
Div4096 = 11,
#[doc = "12: WDT clock divider: /8192"]
Div8192 = 12,
#[doc = "13: WDT clock divider: /16384"]
Div16384 = 13,
#[doc = "14: WDT clock divider: /32768"]
Div32768 = 14,
#[doc = "15: WDT clock divider: /65536"]
Div65536 = 15,
}
impl From<WDTCLKDIV> for u8 {
#[inline(always)]
fn from(variant: WDTCLKDIV) -> Self {
variant as _
}
}
impl crate::FieldSpec for WDTCLKDIV {
type Ux = u8;
}
impl crate::IsEnum for WDTCLKDIV {}
#[doc = "Field `WDTCLKDIV` reader - Watchdog Timer Input Clock Divider"]
pub type WDTCLKDIV_R = crate::FieldReader<WDTCLKDIV>;
impl WDTCLKDIV_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> WDTCLKDIV {
match self.bits {
0 => WDTCLKDIV::Div2,
1 => WDTCLKDIV::Div4,
2 => WDTCLKDIV::Div8,
3 => WDTCLKDIV::Div16,
4 => WDTCLKDIV::Div32,
5 => WDTCLKDIV::Div64,
6 => WDTCLKDIV::Div128,
7 => WDTCLKDIV::Div256,
8 => WDTCLKDIV::Div512,
9 => WDTCLKDIV::Div1024,
10 => WDTCLKDIV::Div2048,
11 => WDTCLKDIV::Div4096,
12 => WDTCLKDIV::Div8192,
13 => WDTCLKDIV::Div16384,
14 => WDTCLKDIV::Div32768,
15 => WDTCLKDIV::Div65536,
_ => unreachable!(),
}
}
#[doc = "WDT clock divider: /2"]
#[inline(always)]
pub fn is_div_2(&self) -> bool {
*self == WDTCLKDIV::Div2
}
#[doc = "WDT clock divider: /4"]
#[inline(always)]
pub fn is_div_4(&self) -> bool {
*self == WDTCLKDIV::Div4
}
#[doc = "WDT clock divider: /8"]
#[inline(always)]
pub fn is_div_8(&self) -> bool {
*self == WDTCLKDIV::Div8
}
#[doc = "WDT clock divider: /16"]
#[inline(always)]
pub fn is_div_16(&self) -> bool {
*self == WDTCLKDIV::Div16
}
#[doc = "WDT clock divider: /32"]
#[inline(always)]
pub fn is_div_32(&self) -> bool {
*self == WDTCLKDIV::Div32
}
#[doc = "WDT clock divider: /64"]
#[inline(always)]
pub fn is_div_64(&self) -> bool {
*self == WDTCLKDIV::Div64
}
#[doc = "WDT clock divider: /128"]
#[inline(always)]
pub fn is_div_128(&self) -> bool {
*self == WDTCLKDIV::Div128
}
#[doc = "WDT clock divider: /256"]
#[inline(always)]
pub fn is_div_256(&self) -> bool {
*self == WDTCLKDIV::Div256
}
#[doc = "WDT clock divider: /512"]
#[inline(always)]
pub fn is_div_512(&self) -> bool {
*self == WDTCLKDIV::Div512
}
#[doc = "WDT clock divider: /1024"]
#[inline(always)]
pub fn is_div_1024(&self) -> bool {
*self == WDTCLKDIV::Div1024
}
#[doc = "WDT clock divider: /2048"]
#[inline(always)]
pub fn is_div_2048(&self) -> bool {
*self == WDTCLKDIV::Div2048
}
#[doc = "WDT clock divider: /4096"]
#[inline(always)]
pub fn is_div_4096(&self) -> bool {
*self == WDTCLKDIV::Div4096
}
#[doc = "WDT clock divider: /8192"]
#[inline(always)]
pub fn is_div_8192(&self) -> bool {
*self == WDTCLKDIV::Div8192
}
#[doc = "WDT clock divider: /16384"]
#[inline(always)]
pub fn is_div_16384(&self) -> bool {
*self == WDTCLKDIV::Div16384
}
#[doc = "WDT clock divider: /32768"]
#[inline(always)]
pub fn is_div_32768(&self) -> bool {
*self == WDTCLKDIV::Div32768
}
#[doc = "WDT clock divider: /65536"]
#[inline(always)]
pub fn is_div_65536(&self) -> bool {
*self == WDTCLKDIV::Div65536
}
}
#[doc = "Field `WDTCLKDIV` writer - Watchdog Timer Input Clock Divider"]
pub type WDTCLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 4, WDTCLKDIV, crate::Safe>;
impl<'a, REG> WDTCLKDIV_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "WDT clock divider: /2"]
#[inline(always)]
pub fn div_2(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKDIV::Div2)
}
#[doc = "WDT clock divider: /4"]
#[inline(always)]
pub fn div_4(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKDIV::Div4)
}
#[doc = "WDT clock divider: /8"]
#[inline(always)]
pub fn div_8(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKDIV::Div8)
}
#[doc = "WDT clock divider: /16"]
#[inline(always)]
pub fn div_16(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKDIV::Div16)
}
#[doc = "WDT clock divider: /32"]
#[inline(always)]
pub fn div_32(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKDIV::Div32)
}
#[doc = "WDT clock divider: /64"]
#[inline(always)]
pub fn div_64(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKDIV::Div64)
}
#[doc = "WDT clock divider: /128"]
#[inline(always)]
pub fn div_128(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKDIV::Div128)
}
#[doc = "WDT clock divider: /256"]
#[inline(always)]
pub fn div_256(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKDIV::Div256)
}
#[doc = "WDT clock divider: /512"]
#[inline(always)]
pub fn div_512(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKDIV::Div512)
}
#[doc = "WDT clock divider: /1024"]
#[inline(always)]
pub fn div_1024(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKDIV::Div1024)
}
#[doc = "WDT clock divider: /2048"]
#[inline(always)]
pub fn div_2048(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKDIV::Div2048)
}
#[doc = "WDT clock divider: /4096"]
#[inline(always)]
pub fn div_4096(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKDIV::Div4096)
}
#[doc = "WDT clock divider: /8192"]
#[inline(always)]
pub fn div_8192(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKDIV::Div8192)
}
#[doc = "WDT clock divider: /16384"]
#[inline(always)]
pub fn div_16384(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKDIV::Div16384)
}
#[doc = "WDT clock divider: /32768"]
#[inline(always)]
pub fn div_32768(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKDIV::Div32768)
}
#[doc = "WDT clock divider: /65536"]
#[inline(always)]
pub fn div_65536(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKDIV::Div65536)
}
}
#[doc = "Watchdog Timer Input Clock Select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum WDTCLKSEL {
#[doc = "0: Watchdog timer input clock: FRCLK"]
Frclk = 0,
#[doc = "1: Watchdog timer input clock: FCLK"]
Fclk = 1,
}
impl From<WDTCLKSEL> for bool {
#[inline(always)]
fn from(variant: WDTCLKSEL) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `WDTCLKSEL` reader - Watchdog Timer Input Clock Select"]
pub type WDTCLKSEL_R = crate::BitReader<WDTCLKSEL>;
impl WDTCLKSEL_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> WDTCLKSEL {
match self.bits {
false => WDTCLKSEL::Frclk,
true => WDTCLKSEL::Fclk,
}
}
#[doc = "Watchdog timer input clock: FRCLK"]
#[inline(always)]
pub fn is_frclk(&self) -> bool {
*self == WDTCLKSEL::Frclk
}
#[doc = "Watchdog timer input clock: FCLK"]
#[inline(always)]
pub fn is_fclk(&self) -> bool {
*self == WDTCLKSEL::Fclk
}
}
#[doc = "Field `WDTCLKSEL` writer - Watchdog Timer Input Clock Select"]
pub type WDTCLKSEL_W<'a, REG> = crate::BitWriter<'a, REG, WDTCLKSEL>;
impl<'a, REG> WDTCLKSEL_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Watchdog timer input clock: FRCLK"]
#[inline(always)]
pub fn frclk(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKSEL::Frclk)
}
#[doc = "Watchdog timer input clock: FCLK"]
#[inline(always)]
pub fn fclk(self) -> &'a mut crate::W<REG> {
self.variant(WDTCLKSEL::Fclk)
}
}
#[doc = "WDT register write busy\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum WRBUSY {
#[doc = "0: Watchdog timer register write not busy"]
NotBusy = 0,
#[doc = "1: Watchdog timer register write busy"]
Busy = 1,
}
impl From<WRBUSY> for bool {
#[inline(always)]
fn from(variant: WRBUSY) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `WRBUSY` reader - WDT register write busy"]
pub type WRBUSY_R = crate::BitReader<WRBUSY>;
impl WRBUSY_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> WRBUSY {
match self.bits {
false => WRBUSY::NotBusy,
true => WRBUSY::Busy,
}
}
#[doc = "Watchdog timer register write not busy"]
#[inline(always)]
pub fn is_not_busy(&self) -> bool {
*self == WRBUSY::NotBusy
}
#[doc = "Watchdog timer register write busy"]
#[inline(always)]
pub fn is_busy(&self) -> bool {
*self == WRBUSY::Busy
}
}
#[doc = "Field `KEY` reader - WDTCTL register key"]
pub type KEY_R = crate::FieldReader;
#[doc = "Field `KEY` writer - WDTCTL register key"]
pub type KEY_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:2 - Watchdog Timer Counter Reset"]
#[inline(always)]
pub fn wdtctrrst(&self) -> WDTCTRRST_R {
WDTCTRRST_R::new((self.bits & 7) as u8)
}
#[doc = "Bit 3 - Watchdog Interval Timer Interrupt Enable"]
#[inline(always)]
pub fn wdtinten(&self) -> WDTINTEN_R {
WDTINTEN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Watchdog Interval Timer Interrupt Flag"]
#[inline(always)]
pub fn wdtint(&self) -> WDTINT_R {
WDTINT_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Watchdog Timer Device Reset Enable"]
#[inline(always)]
pub fn wdtreseten(&self) -> WDTRESETEN_R {
WDTRESETEN_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:9 - Watchdog Timer Input Clock Divider"]
#[inline(always)]
pub fn wdtclkdiv(&self) -> WDTCLKDIV_R {
WDTCLKDIV_R::new(((self.bits >> 6) & 0x0f) as u8)
}
#[doc = "Bit 10 - Watchdog Timer Input Clock Select"]
#[inline(always)]
pub fn wdtclksel(&self) -> WDTCLKSEL_R {
WDTCLKSEL_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - WDT register write busy"]
#[inline(always)]
pub fn wrbusy(&self) -> WRBUSY_R {
WRBUSY_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 24:31 - WDTCTL register key"]
#[inline(always)]
pub fn key(&self) -> KEY_R {
KEY_R::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("WDTCTL")
.field("wdtctrrst", &self.wdtctrrst())
.field("wdtinten", &self.wdtinten())
.field("wdtint", &self.wdtint())
.field("wdtreseten", &self.wdtreseten())
.field("wdtclkdiv", &self.wdtclkdiv())
.field("wdtclksel", &self.wdtclksel())
.field("wrbusy", &self.wrbusy())
.field("key", &self.key())
.finish()
}
}
impl W {
#[doc = "Bits 0:2 - Watchdog Timer Counter Reset"]
#[inline(always)]
pub fn wdtctrrst(&mut self) -> WDTCTRRST_W<WDTCTLrs> {
WDTCTRRST_W::new(self, 0)
}
#[doc = "Bit 3 - Watchdog Interval Timer Interrupt Enable"]
#[inline(always)]
pub fn wdtinten(&mut self) -> WDTINTEN_W<WDTCTLrs> {
WDTINTEN_W::new(self, 3)
}
#[doc = "Bit 5 - Watchdog Timer Device Reset Enable"]
#[inline(always)]
pub fn wdtreseten(&mut self) -> WDTRESETEN_W<WDTCTLrs> {
WDTRESETEN_W::new(self, 5)
}
#[doc = "Bits 6:9 - Watchdog Timer Input Clock Divider"]
#[inline(always)]
pub fn wdtclkdiv(&mut self) -> WDTCLKDIV_W<WDTCTLrs> {
WDTCLKDIV_W::new(self, 6)
}
#[doc = "Bit 10 - Watchdog Timer Input Clock Select"]
#[inline(always)]
pub fn wdtclksel(&mut self) -> WDTCLKSEL_W<WDTCTLrs> {
WDTCLKSEL_W::new(self, 10)
}
#[doc = "Bits 24:31 - WDTCTL register key"]
#[inline(always)]
pub fn key(&mut self) -> KEY_W<WDTCTLrs> {
KEY_W::new(self, 24)
}
}
#[doc = "Watchdog Timer Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WDTCTLrs;
impl crate::RegisterSpec for WDTCTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdtctl::R`](R) reader structure"]
impl crate::Readable for WDTCTLrs {}
#[doc = "`write(|w| ..)` method takes [`wdtctl::W`](W) writer structure"]
impl crate::Writable for WDTCTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDTCTL to value 0x6300_0000"]
impl crate::Resettable for WDTCTLrs {
const RESET_VALUE: u32 = 0x6300_0000;
}
}
#[doc = "WDTCDV (rw) register accessor: Watchdog Timer Count-down Value Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtcdv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtcdv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtcdv`]
module"]
pub type WDTCDV = crate::Reg<wdtcdv::WDTCDVrs>;
#[doc = "Watchdog Timer Count-down Value Register"]
pub mod wdtcdv {
#[doc = "Register `WDTCDV` reader"]
pub type R = crate::R<WDTCDVrs>;
#[doc = "Register `WDTCDV` writer"]
pub type W = crate::W<WDTCDVrs>;
#[doc = "Field `RSTVALUE` reader - 24b WDT count-down value"]
pub type RSTVALUE_R = crate::FieldReader<u32>;
#[doc = "Field `RSTVALUE` writer - 24b WDT count-down value"]
pub type RSTVALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `KEY` reader - WDTCTL register key"]
pub type KEY_R = crate::FieldReader;
#[doc = "Field `KEY` writer - WDTCTL register key"]
pub type KEY_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - 24b WDT count-down value"]
#[inline(always)]
pub fn rstvalue(&self) -> RSTVALUE_R {
RSTVALUE_R::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31 - WDTCTL register key"]
#[inline(always)]
pub fn key(&self) -> KEY_R {
KEY_R::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("WDTCDV")
.field("rstvalue", &self.rstvalue())
.field("key", &self.key())
.finish()
}
}
impl W {
#[doc = "Bits 0:23 - 24b WDT count-down value"]
#[inline(always)]
pub fn rstvalue(&mut self) -> RSTVALUE_W<WDTCDVrs> {
RSTVALUE_W::new(self, 0)
}
#[doc = "Bits 24:31 - WDTCTL register key"]
#[inline(always)]
pub fn key(&mut self) -> KEY_W<WDTCDVrs> {
KEY_W::new(self, 24)
}
}
#[doc = "Watchdog Timer Count-down Value Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtcdv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtcdv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WDTCDVrs;
impl crate::RegisterSpec for WDTCDVrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdtcdv::R`](R) reader structure"]
impl crate::Readable for WDTCDVrs {}
#[doc = "`write(|w| ..)` method takes [`wdtcdv::W`](W) writer structure"]
impl crate::Writable for WDTCDVrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets WDTCDV to value 0x63ff_ffff"]
impl crate::Resettable for WDTCDVrs {
const RESET_VALUE: u32 = 0x63ff_ffff;
}
}
#[doc = "WDTCTR (r) register accessor: Watchdog Timer Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtctr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtctr`]
module"]
pub type WDTCTR = crate::Reg<wdtctr::WDTCTRrs>;
#[doc = "Watchdog Timer Counter Register"]
pub mod wdtctr {
#[doc = "Register `WDTCTR` reader"]
pub type R = crate::R<WDTCTRrs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
#[doc = "Watchdog Timer Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtctr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WDTCTRrs;
impl crate::RegisterSpec for WDTCTRrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdtctr::R`](R) reader structure"]
impl crate::Readable for WDTCTRrs {}
#[doc = "`reset()` method sets WDTCTR to value 0x00ff_ffff"]
impl crate::Resettable for WDTCTRrs {
const RESET_VALUE: u32 = 0x00ff_ffff;
}
}
}
#[doc = "Real-Time Clock"]
pub struct RTC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for RTC {}
impl RTC {
#[doc = r"Pointer to the register block"]
pub const PTR: *const rtc::RegisterBlock = 0x4004_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const rtc::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for RTC {
type Target = rtc::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for RTC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RTC").finish()
}
}
#[doc = "Real-Time Clock"]
pub mod rtc {
#[repr(C)]
#[derive(Debug)]
#[doc = "Register block"]
pub struct RegisterBlock {
rtcctl: RTCCTL,
rtccdv: RTCCDV,
rtcctr: RTCCTR,
}
impl RegisterBlock {
#[doc = "0x00 - Real-Time Clock Control Register"]
#[inline(always)]
pub const fn rtcctl(&self) -> &RTCCTL {
&self.rtcctl
}
#[doc = "0x04 - Real-Time Clock Count-down Value Register"]
#[inline(always)]
pub const fn rtccdv(&self) -> &RTCCDV {
&self.rtccdv
}
#[doc = "0x08 - Real-Time Clock Counter Register"]
#[inline(always)]
pub const fn rtcctr(&self) -> &RTCCTR {
&self.rtcctr
}
}
#[doc = "RTCCTL (rw) register accessor: Real-Time Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtcctl`]
module"]
pub type RTCCTL = crate::Reg<rtcctl::RTCCTLrs>;
#[doc = "Real-Time Clock Control Register"]
pub mod rtcctl {
#[doc = "Register `RTCCTL` reader"]
pub type R = crate::R<RTCCTLrs>;
#[doc = "Register `RTCCTL` writer"]
pub type W = crate::W<RTCCTLrs>;
#[doc = "Real-Time Clock Counter Reset\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum RTCCTRRST {
#[doc = "5: RTCCTL Reset Key"]
Key = 5,
}
impl From<RTCCTRRST> for u8 {
#[inline(always)]
fn from(variant: RTCCTRRST) -> Self {
variant as _
}
}
impl crate::FieldSpec for RTCCTRRST {
type Ux = u8;
}
impl crate::IsEnum for RTCCTRRST {}
#[doc = "Field `RTCCTRRST` reader - Real-Time Clock Counter Reset"]
pub type RTCCTRRST_R = crate::FieldReader<RTCCTRRST>;
impl RTCCTRRST_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<RTCCTRRST> {
match self.bits {
5 => Some(RTCCTRRST::Key),
_ => None,
}
}
#[doc = "RTCCTL Reset Key"]
#[inline(always)]
pub fn is_key(&self) -> bool {
*self == RTCCTRRST::Key
}
}
#[doc = "Field `RTCCTRRST` writer - Real-Time Clock Counter Reset"]
pub type RTCCTRRST_W<'a, REG> = crate::FieldWriter<'a, REG, 3, RTCCTRRST>;
impl<'a, REG> RTCCTRRST_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "RTCCTL Reset Key"]
#[inline(always)]
pub fn key(self) -> &'a mut crate::W<REG> {
self.variant(RTCCTRRST::Key)
}
}
#[doc = "Real-Time Clock Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RTCINTEN {
#[doc = "0: Real-Time Clock interrupt disable"]
Disabled = 0,
#[doc = "1: Real-Time Clock interrupt enable"]
Enabled = 1,
}
impl From<RTCINTEN> for bool {
#[inline(always)]
fn from(variant: RTCINTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RTCINTEN` reader - Real-Time Clock Interrupt Enable"]
pub type RTCINTEN_R = crate::BitReader<RTCINTEN>;
impl RTCINTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RTCINTEN {
match self.bits {
false => RTCINTEN::Disabled,
true => RTCINTEN::Enabled,
}
}
#[doc = "Real-Time Clock interrupt disable"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == RTCINTEN::Disabled
}
#[doc = "Real-Time Clock interrupt enable"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == RTCINTEN::Enabled
}
}
#[doc = "Field `RTCINTEN` writer - Real-Time Clock Interrupt Enable"]
pub type RTCINTEN_W<'a, REG> = crate::BitWriter<'a, REG, RTCINTEN>;
impl<'a, REG> RTCINTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Real-Time Clock interrupt disable"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(RTCINTEN::Disabled)
}
#[doc = "Real-Time Clock interrupt enable"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(RTCINTEN::Enabled)
}
}
#[doc = "Real-Time Clock Interrupt Flag\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RTCINT {
#[doc = "0: Real-Time Clock interrupt flag clear"]
Clear = 0,
#[doc = "1: Real-Time Clock interrupt flag set"]
Set = 1,
}
impl From<RTCINT> for bool {
#[inline(always)]
fn from(variant: RTCINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RTCINT` reader - Real-Time Clock Interrupt Flag"]
pub type RTCINT_R = crate::BitReader<RTCINT>;
impl RTCINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RTCINT {
match self.bits {
false => RTCINT::Clear,
true => RTCINT::Set,
}
}
#[doc = "Real-Time Clock interrupt flag clear"]
#[inline(always)]
pub fn is_clear(&self) -> bool {
*self == RTCINT::Clear
}
#[doc = "Real-Time Clock interrupt flag set"]
#[inline(always)]
pub fn is_set(&self) -> bool {
*self == RTCINT::Set
}
}
#[doc = "Real-Time Clock Input Clock Divider\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum RTCCLKDIV {
#[doc = "0: Real-Time clock divider: /2"]
Div2 = 0,
#[doc = "1: Real-Time clock divider: /4"]
Div4 = 1,
#[doc = "2: Real-Time clock divider: /8"]
Div8 = 2,
#[doc = "3: Real-Time clock divider: /16"]
Div16 = 3,
#[doc = "4: Real-Time clock divider: /32"]
Div32 = 4,
#[doc = "5: Real-Time clock divider: /64"]
Div64 = 5,
#[doc = "6: Real-Time clock divider: /128"]
Div128 = 6,
#[doc = "7: Real-Time clock divider: /256"]
Div256 = 7,
#[doc = "8: Real-Time clock divider: /512"]
Div512 = 8,
#[doc = "9: Real-Time clock divider: /1024"]
Div1024 = 9,
#[doc = "10: Real-Time clock divider: /2048"]
Div2048 = 10,
#[doc = "11: Real-Time clock divider: /4096"]
Div4096 = 11,
#[doc = "12: Real-Time clock divider: /8192"]
Div8192 = 12,
#[doc = "13: Real-Time clock divider: /16384"]
Div16384 = 13,
#[doc = "14: Real-Time clock divider: /32768"]
Div32768 = 14,
#[doc = "15: Real-Time clock divider: /65536"]
Div65536 = 15,
}
impl From<RTCCLKDIV> for u8 {
#[inline(always)]
fn from(variant: RTCCLKDIV) -> Self {
variant as _
}
}
impl crate::FieldSpec for RTCCLKDIV {
type Ux = u8;
}
impl crate::IsEnum for RTCCLKDIV {}
#[doc = "Field `RTCCLKDIV` reader - Real-Time Clock Input Clock Divider"]
pub type RTCCLKDIV_R = crate::FieldReader<RTCCLKDIV>;
impl RTCCLKDIV_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RTCCLKDIV {
match self.bits {
0 => RTCCLKDIV::Div2,
1 => RTCCLKDIV::Div4,
2 => RTCCLKDIV::Div8,
3 => RTCCLKDIV::Div16,
4 => RTCCLKDIV::Div32,
5 => RTCCLKDIV::Div64,
6 => RTCCLKDIV::Div128,
7 => RTCCLKDIV::Div256,
8 => RTCCLKDIV::Div512,
9 => RTCCLKDIV::Div1024,
10 => RTCCLKDIV::Div2048,
11 => RTCCLKDIV::Div4096,
12 => RTCCLKDIV::Div8192,
13 => RTCCLKDIV::Div16384,
14 => RTCCLKDIV::Div32768,
15 => RTCCLKDIV::Div65536,
_ => unreachable!(),
}
}
#[doc = "Real-Time clock divider: /2"]
#[inline(always)]
pub fn is_div_2(&self) -> bool {
*self == RTCCLKDIV::Div2
}
#[doc = "Real-Time clock divider: /4"]
#[inline(always)]
pub fn is_div_4(&self) -> bool {
*self == RTCCLKDIV::Div4
}
#[doc = "Real-Time clock divider: /8"]
#[inline(always)]
pub fn is_div_8(&self) -> bool {
*self == RTCCLKDIV::Div8
}
#[doc = "Real-Time clock divider: /16"]
#[inline(always)]
pub fn is_div_16(&self) -> bool {
*self == RTCCLKDIV::Div16
}
#[doc = "Real-Time clock divider: /32"]
#[inline(always)]
pub fn is_div_32(&self) -> bool {
*self == RTCCLKDIV::Div32
}
#[doc = "Real-Time clock divider: /64"]
#[inline(always)]
pub fn is_div_64(&self) -> bool {
*self == RTCCLKDIV::Div64
}
#[doc = "Real-Time clock divider: /128"]
#[inline(always)]
pub fn is_div_128(&self) -> bool {
*self == RTCCLKDIV::Div128
}
#[doc = "Real-Time clock divider: /256"]
#[inline(always)]
pub fn is_div_256(&self) -> bool {
*self == RTCCLKDIV::Div256
}
#[doc = "Real-Time clock divider: /512"]
#[inline(always)]
pub fn is_div_512(&self) -> bool {
*self == RTCCLKDIV::Div512
}
#[doc = "Real-Time clock divider: /1024"]
#[inline(always)]
pub fn is_div_1024(&self) -> bool {
*self == RTCCLKDIV::Div1024
}
#[doc = "Real-Time clock divider: /2048"]
#[inline(always)]
pub fn is_div_2048(&self) -> bool {
*self == RTCCLKDIV::Div2048
}
#[doc = "Real-Time clock divider: /4096"]
#[inline(always)]
pub fn is_div_4096(&self) -> bool {
*self == RTCCLKDIV::Div4096
}
#[doc = "Real-Time clock divider: /8192"]
#[inline(always)]
pub fn is_div_8192(&self) -> bool {
*self == RTCCLKDIV::Div8192
}
#[doc = "Real-Time clock divider: /16384"]
#[inline(always)]
pub fn is_div_16384(&self) -> bool {
*self == RTCCLKDIV::Div16384
}
#[doc = "Real-Time clock divider: /32768"]
#[inline(always)]
pub fn is_div_32768(&self) -> bool {
*self == RTCCLKDIV::Div32768
}
#[doc = "Real-Time clock divider: /65536"]
#[inline(always)]
pub fn is_div_65536(&self) -> bool {
*self == RTCCLKDIV::Div65536
}
}
#[doc = "Field `RTCCLKDIV` writer - Real-Time Clock Input Clock Divider"]
pub type RTCCLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 4, RTCCLKDIV, crate::Safe>;
impl<'a, REG> RTCCLKDIV_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Real-Time clock divider: /2"]
#[inline(always)]
pub fn div_2(self) -> &'a mut crate::W<REG> {
self.variant(RTCCLKDIV::Div2)
}
#[doc = "Real-Time clock divider: /4"]
#[inline(always)]
pub fn div_4(self) -> &'a mut crate::W<REG> {
self.variant(RTCCLKDIV::Div4)
}
#[doc = "Real-Time clock divider: /8"]
#[inline(always)]
pub fn div_8(self) -> &'a mut crate::W<REG> {
self.variant(RTCCLKDIV::Div8)
}
#[doc = "Real-Time clock divider: /16"]
#[inline(always)]
pub fn div_16(self) -> &'a mut crate::W<REG> {
self.variant(RTCCLKDIV::Div16)
}
#[doc = "Real-Time clock divider: /32"]
#[inline(always)]
pub fn div_32(self) -> &'a mut crate::W<REG> {
self.variant(RTCCLKDIV::Div32)
}
#[doc = "Real-Time clock divider: /64"]
#[inline(always)]
pub fn div_64(self) -> &'a mut crate::W<REG> {
self.variant(RTCCLKDIV::Div64)
}
#[doc = "Real-Time clock divider: /128"]
#[inline(always)]
pub fn div_128(self) -> &'a mut crate::W<REG> {
self.variant(RTCCLKDIV::Div128)
}
#[doc = "Real-Time clock divider: /256"]
#[inline(always)]
pub fn div_256(self) -> &'a mut crate::W<REG> {
self.variant(RTCCLKDIV::Div256)
}
#[doc = "Real-Time clock divider: /512"]
#[inline(always)]
pub fn div_512(self) -> &'a mut crate::W<REG> {
self.variant(RTCCLKDIV::Div512)
}
#[doc = "Real-Time clock divider: /1024"]
#[inline(always)]
pub fn div_1024(self) -> &'a mut crate::W<REG> {
self.variant(RTCCLKDIV::Div1024)
}
#[doc = "Real-Time clock divider: /2048"]
#[inline(always)]
pub fn div_2048(self) -> &'a mut crate::W<REG> {
self.variant(RTCCLKDIV::Div2048)
}
#[doc = "Real-Time clock divider: /4096"]
#[inline(always)]
pub fn div_4096(self) -> &'a mut crate::W<REG> {
self.variant(RTCCLKDIV::Div4096)
}
#[doc = "Real-Time clock divider: /8192"]
#[inline(always)]
pub fn div_8192(self) -> &'a mut crate::W<REG> {
self.variant(RTCCLKDIV::Div8192)
}
#[doc = "Real-Time clock divider: /16384"]
#[inline(always)]
pub fn div_16384(self) -> &'a mut crate::W<REG> {
self.variant(RTCCLKDIV::Div16384)
}
#[doc = "Real-Time clock divider: /32768"]
#[inline(always)]
pub fn div_32768(self) -> &'a mut crate::W<REG> {
self.variant(RTCCLKDIV::Div32768)
}
#[doc = "Real-Time clock divider: /65536"]
#[inline(always)]
pub fn div_65536(self) -> &'a mut crate::W<REG> {
self.variant(RTCCLKDIV::Div65536)
}
}
#[doc = "RTC register write busy\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum WRBUSY {
#[doc = "0: RTC register write not busy"]
NotBusy = 0,
#[doc = "1: RTC register write busy"]
Busy = 1,
}
impl From<WRBUSY> for bool {
#[inline(always)]
fn from(variant: WRBUSY) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `WRBUSY` reader - RTC register write busy"]
pub type WRBUSY_R = crate::BitReader<WRBUSY>;
impl WRBUSY_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> WRBUSY {
match self.bits {
false => WRBUSY::NotBusy,
true => WRBUSY::Busy,
}
}
#[doc = "RTC register write not busy"]
#[inline(always)]
pub fn is_not_busy(&self) -> bool {
*self == WRBUSY::NotBusy
}
#[doc = "RTC register write busy"]
#[inline(always)]
pub fn is_busy(&self) -> bool {
*self == WRBUSY::Busy
}
}
#[doc = "Field `KEY` reader - RTCCTL register key"]
pub type KEY_R = crate::FieldReader;
#[doc = "Field `KEY` writer - RTCCTL register key"]
pub type KEY_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:2 - Real-Time Clock Counter Reset"]
#[inline(always)]
pub fn rtcctrrst(&self) -> RTCCTRRST_R {
RTCCTRRST_R::new((self.bits & 7) as u8)
}
#[doc = "Bit 3 - Real-Time Clock Interrupt Enable"]
#[inline(always)]
pub fn rtcinten(&self) -> RTCINTEN_R {
RTCINTEN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Real-Time Clock Interrupt Flag"]
#[inline(always)]
pub fn rtcint(&self) -> RTCINT_R {
RTCINT_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 6:9 - Real-Time Clock Input Clock Divider"]
#[inline(always)]
pub fn rtcclkdiv(&self) -> RTCCLKDIV_R {
RTCCLKDIV_R::new(((self.bits >> 6) & 0x0f) as u8)
}
#[doc = "Bit 11 - RTC register write busy"]
#[inline(always)]
pub fn wrbusy(&self) -> WRBUSY_R {
WRBUSY_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 24:31 - RTCCTL register key"]
#[inline(always)]
pub fn key(&self) -> KEY_R {
KEY_R::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RTCCTL")
.field("rtcctrrst", &self.rtcctrrst())
.field("rtcinten", &self.rtcinten())
.field("rtcint", &self.rtcint())
.field("rtcclkdiv", &self.rtcclkdiv())
.field("wrbusy", &self.wrbusy())
.field("key", &self.key())
.finish()
}
}
impl W {
#[doc = "Bits 0:2 - Real-Time Clock Counter Reset"]
#[inline(always)]
pub fn rtcctrrst(&mut self) -> RTCCTRRST_W<RTCCTLrs> {
RTCCTRRST_W::new(self, 0)
}
#[doc = "Bit 3 - Real-Time Clock Interrupt Enable"]
#[inline(always)]
pub fn rtcinten(&mut self) -> RTCINTEN_W<RTCCTLrs> {
RTCINTEN_W::new(self, 3)
}
#[doc = "Bits 6:9 - Real-Time Clock Input Clock Divider"]
#[inline(always)]
pub fn rtcclkdiv(&mut self) -> RTCCLKDIV_W<RTCCTLrs> {
RTCCLKDIV_W::new(self, 6)
}
#[doc = "Bits 24:31 - RTCCTL register key"]
#[inline(always)]
pub fn key(&mut self) -> KEY_W<RTCCTLrs> {
KEY_W::new(self, 24)
}
}
#[doc = "Real-Time Clock Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RTCCTLrs;
impl crate::RegisterSpec for RTCCTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtcctl::R`](R) reader structure"]
impl crate::Readable for RTCCTLrs {}
#[doc = "`write(|w| ..)` method takes [`rtcctl::W`](W) writer structure"]
impl crate::Writable for RTCCTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RTCCTL to value 0x6300_0000"]
impl crate::Resettable for RTCCTLrs {
const RESET_VALUE: u32 = 0x6300_0000;
}
}
#[doc = "RTCCDV (rw) register accessor: Real-Time Clock Count-down Value Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtccdv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtccdv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtccdv`]
module"]
pub type RTCCDV = crate::Reg<rtccdv::RTCCDVrs>;
#[doc = "Real-Time Clock Count-down Value Register"]
pub mod rtccdv {
#[doc = "Register `RTCCDV` reader"]
pub type R = crate::R<RTCCDVrs>;
#[doc = "Register `RTCCDV` writer"]
pub type W = crate::W<RTCCDVrs>;
#[doc = "Field `RSTVALUE` reader - 24b RTC count-down value"]
pub type RSTVALUE_R = crate::FieldReader<u32>;
#[doc = "Field `RSTVALUE` writer - 24b RTC count-down value"]
pub type RSTVALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `KEY` reader - RTC register key"]
pub type KEY_R = crate::FieldReader;
#[doc = "Field `KEY` writer - RTC register key"]
pub type KEY_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:23 - 24b RTC count-down value"]
#[inline(always)]
pub fn rstvalue(&self) -> RSTVALUE_R {
RSTVALUE_R::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bits 24:31 - RTC register key"]
#[inline(always)]
pub fn key(&self) -> KEY_R {
KEY_R::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RTCCDV")
.field("rstvalue", &self.rstvalue())
.field("key", &self.key())
.finish()
}
}
impl W {
#[doc = "Bits 0:23 - 24b RTC count-down value"]
#[inline(always)]
pub fn rstvalue(&mut self) -> RSTVALUE_W<RTCCDVrs> {
RSTVALUE_W::new(self, 0)
}
#[doc = "Bits 24:31 - RTC register key"]
#[inline(always)]
pub fn key(&mut self) -> KEY_W<RTCCDVrs> {
KEY_W::new(self, 24)
}
}
#[doc = "Real-Time Clock Count-down Value Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtccdv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtccdv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RTCCDVrs;
impl crate::RegisterSpec for RTCCDVrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtccdv::R`](R) reader structure"]
impl crate::Readable for RTCCDVrs {}
#[doc = "`write(|w| ..)` method takes [`rtccdv::W`](W) writer structure"]
impl crate::Writable for RTCCDVrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets RTCCDV to value 0x63ff_ffff"]
impl crate::Resettable for RTCCDVrs {
const RESET_VALUE: u32 = 0x63ff_ffff;
}
}
#[doc = "RTCCTR (r) register accessor: Real-Time Clock Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcctr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtcctr`]
module"]
pub type RTCCTR = crate::Reg<rtcctr::RTCCTRrs>;
#[doc = "Real-Time Clock Counter Register"]
pub mod rtcctr {
#[doc = "Register `RTCCTR` reader"]
pub type R = crate::R<RTCCTRrs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
#[doc = "Real-Time Clock Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcctr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RTCCTRrs;
impl crate::RegisterSpec for RTCCTRrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtcctr::R`](R) reader structure"]
impl crate::Readable for RTCCTRrs {}
#[doc = "`reset()` method sets RTCCTR to value 0x00ff_ffff"]
impl crate::Resettable for RTCCTRrs {
const RESET_VALUE: u32 = 0x00ff_ffff;
}
}
}
#[doc = "General-Purpose Input-Output Port A"]
pub struct GPIOA {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOA {}
impl GPIOA {
#[doc = r"Pointer to the register block"]
pub const PTR: *const gpioa::RegisterBlock = 0x4007_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const gpioa::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for GPIOA {
type Target = gpioa::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for GPIOA {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOA").finish()
}
}
#[doc = "General-Purpose Input-Output Port A"]
pub mod gpioa {
#[repr(C)]
#[derive(Debug)]
#[doc = "Register block"]
pub struct RegisterBlock {
out: OUT,
outen: OUTEN,
ds: DS,
pu: PU,
pd: PD,
in_: IN,
_reserved6: [u8; 0x04],
psel: PSEL,
intp: INTP,
inte: INTE,
intf: INTF,
intm: INTM,
}
impl RegisterBlock {
#[doc = "0x00 - GPIO Port Output"]
#[inline(always)]
pub const fn out(&self) -> &OUT {
&self.out
}
#[doc = "0x04 - GPIO Port Output Enable"]
#[inline(always)]
pub const fn outen(&self) -> &OUTEN {
&self.outen
}
#[doc = "0x08 - GPIO Port Output Drive Strength Select"]
#[inline(always)]
pub const fn ds(&self) -> &DS {
&self.ds
}
#[doc = "0x0c - GPIO Port Weak Pull Up"]
#[inline(always)]
pub const fn pu(&self) -> &PU {
&self.pu
}
#[doc = "0x10 - GPIO Port Weak Pull Down"]
#[inline(always)]
pub const fn pd(&self) -> &PD {
&self.pd
}
#[doc = "0x14 - GPIO Port Input"]
#[inline(always)]
pub const fn in_(&self) -> &IN {
&self.in_
}
#[doc = "0x1c - GPIO Peripheral Select"]
#[inline(always)]
pub const fn psel(&self) -> &PSEL {
&self.psel
}
#[doc = "0x20 - GPIO Port Interrupt Polarity"]
#[inline(always)]
pub const fn intp(&self) -> &INTP {
&self.intp
}
#[doc = "0x24 - GPIO Port Interrupt Enable"]
#[inline(always)]
pub const fn inte(&self) -> &INTE {
&self.inte
}
#[doc = "0x28 - GPIO Port Interrupt Flag"]
#[inline(always)]
pub const fn intf(&self) -> &INTF {
&self.intf
}
#[doc = "0x2c - GPIO Port Interrupt Mask"]
#[inline(always)]
pub const fn intm(&self) -> &INTM {
&self.intm
}
}
#[doc = "OUT (rw) register accessor: GPIO Port Output\n\nYou can [`read`](crate::Reg::read) this register and get [`out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out`]
module"]
pub type OUT = crate::Reg<out::OUTrs>;
#[doc = "GPIO Port Output"]
pub mod out {
#[doc = "Register `OUT` reader"]
pub type R = crate::R<OUTrs>;
#[doc = "Register `OUT` writer"]
pub type W = crate::W<OUTrs>;
#[doc = "Port output 0\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: Set output low if GPIOn->OUTEN.P0 = 1"]
Low = 0,
#[doc = "1: Set output high if GPIOn->OUTEN.P0 = 1"]
High = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port output 0"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::Low,
true => P0::High,
}
}
#[doc = "Set output low if GPIOn->OUTEN.P0 = 1"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P0::Low
}
#[doc = "Set output high if GPIOn->OUTEN.P0 = 1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P0::High
}
}
#[doc = "Field `P0` writer - Port output 0"]
pub type P0_W<'a, REG> = crate::BitWriter<'a, REG, P0>;
impl<'a, REG> P0_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Set output low if GPIOn->OUTEN.P0 = 1"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P0::Low)
}
#[doc = "Set output high if GPIOn->OUTEN.P0 = 1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P0::High)
}
}
#[doc = "Port output 1\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: Set output low if GPIOn->OUTEN.P1 = 1"]
Low = 0,
#[doc = "1: Set output high if GPIOn->OUTEN.P1 = 1"]
High = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port output 1"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::Low,
true => P1::High,
}
}
#[doc = "Set output low if GPIOn->OUTEN.P1 = 1"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P1::Low
}
#[doc = "Set output high if GPIOn->OUTEN.P1 = 1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P1::High
}
}
#[doc = "Field `P1` writer - Port output 1"]
pub type P1_W<'a, REG> = crate::BitWriter<'a, REG, P1>;
impl<'a, REG> P1_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Set output low if GPIOn->OUTEN.P1 = 1"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P1::Low)
}
#[doc = "Set output high if GPIOn->OUTEN.P1 = 1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P1::High)
}
}
#[doc = "Port output 2\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: Set output low if GPIOn->OUTEN.P2 = 1"]
Low = 0,
#[doc = "1: Set output high if GPIOn->OUTEN.P2 = 1"]
High = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port output 2"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::Low,
true => P2::High,
}
}
#[doc = "Set output low if GPIOn->OUTEN.P2 = 1"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P2::Low
}
#[doc = "Set output high if GPIOn->OUTEN.P2 = 1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P2::High
}
}
#[doc = "Field `P2` writer - Port output 2"]
pub type P2_W<'a, REG> = crate::BitWriter<'a, REG, P2>;
impl<'a, REG> P2_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Set output low if GPIOn->OUTEN.P2 = 1"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P2::Low)
}
#[doc = "Set output high if GPIOn->OUTEN.P2 = 1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P2::High)
}
}
#[doc = "Port output 3\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: Set output low if GPIOn->OUTEN.P3 = 1"]
Low = 0,
#[doc = "1: Set output high if GPIOn->OUTEN.P3 = 1"]
High = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port output 3"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::Low,
true => P3::High,
}
}
#[doc = "Set output low if GPIOn->OUTEN.P3 = 1"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P3::Low
}
#[doc = "Set output high if GPIOn->OUTEN.P3 = 1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P3::High
}
}
#[doc = "Field `P3` writer - Port output 3"]
pub type P3_W<'a, REG> = crate::BitWriter<'a, REG, P3>;
impl<'a, REG> P3_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Set output low if GPIOn->OUTEN.P3 = 1"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P3::Low)
}
#[doc = "Set output high if GPIOn->OUTEN.P3 = 1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P3::High)
}
}
#[doc = "Port output 4\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: Set output low if GPIOn->OUTEN.P4 = 1"]
Low = 0,
#[doc = "1: Set output high if GPIOn->OUTEN.P4 = 1"]
High = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port output 4"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::Low,
true => P4::High,
}
}
#[doc = "Set output low if GPIOn->OUTEN.P4 = 1"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P4::Low
}
#[doc = "Set output high if GPIOn->OUTEN.P4 = 1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P4::High
}
}
#[doc = "Field `P4` writer - Port output 4"]
pub type P4_W<'a, REG> = crate::BitWriter<'a, REG, P4>;
impl<'a, REG> P4_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Set output low if GPIOn->OUTEN.P4 = 1"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P4::Low)
}
#[doc = "Set output high if GPIOn->OUTEN.P4 = 1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P4::High)
}
}
#[doc = "Port output 5\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: Set output low if GPIOn->OUTEN.P5 = 1"]
Low = 0,
#[doc = "1: Set output high if GPIOn->OUTEN.P5 = 1"]
High = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port output 5"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::Low,
true => P5::High,
}
}
#[doc = "Set output low if GPIOn->OUTEN.P5 = 1"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P5::Low
}
#[doc = "Set output high if GPIOn->OUTEN.P5 = 1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P5::High
}
}
#[doc = "Field `P5` writer - Port output 5"]
pub type P5_W<'a, REG> = crate::BitWriter<'a, REG, P5>;
impl<'a, REG> P5_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Set output low if GPIOn->OUTEN.P5 = 1"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P5::Low)
}
#[doc = "Set output high if GPIOn->OUTEN.P5 = 1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P5::High)
}
}
#[doc = "Port output 6\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: Set output low if GPIOn->OUTEN.P6 = 1"]
Low = 0,
#[doc = "1: Set output high if GPIOn->OUTEN.P6 = 1"]
High = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port output 6"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::Low,
true => P6::High,
}
}
#[doc = "Set output low if GPIOn->OUTEN.P6 = 1"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P6::Low
}
#[doc = "Set output high if GPIOn->OUTEN.P6 = 1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P6::High
}
}
#[doc = "Field `P6` writer - Port output 6"]
pub type P6_W<'a, REG> = crate::BitWriter<'a, REG, P6>;
impl<'a, REG> P6_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Set output low if GPIOn->OUTEN.P6 = 1"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P6::Low)
}
#[doc = "Set output high if GPIOn->OUTEN.P6 = 1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P6::High)
}
}
#[doc = "Port output 7\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: Set output low if GPIOn->OUTEN.P7 = 1"]
Low = 0,
#[doc = "1: Set output high if GPIOn->OUTEN.P7 = 1"]
High = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port output 7"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::Low,
true => P7::High,
}
}
#[doc = "Set output low if GPIOn->OUTEN.P7 = 1"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P7::Low
}
#[doc = "Set output high if GPIOn->OUTEN.P7 = 1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P7::High
}
}
#[doc = "Field `P7` writer - Port output 7"]
pub type P7_W<'a, REG> = crate::BitWriter<'a, REG, P7>;
impl<'a, REG> P7_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Set output low if GPIOn->OUTEN.P7 = 1"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P7::Low)
}
#[doc = "Set output high if GPIOn->OUTEN.P7 = 1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P7::High)
}
}
impl R {
#[doc = "Bit 0 - Port output 0"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port output 1"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port output 2"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port output 3"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port output 4"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port output 5"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port output 6"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port output 7"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OUT")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Port output 0"]
#[inline(always)]
pub fn p0(&mut self) -> P0_W<OUTrs> {
P0_W::new(self, 0)
}
#[doc = "Bit 1 - Port output 1"]
#[inline(always)]
pub fn p1(&mut self) -> P1_W<OUTrs> {
P1_W::new(self, 1)
}
#[doc = "Bit 2 - Port output 2"]
#[inline(always)]
pub fn p2(&mut self) -> P2_W<OUTrs> {
P2_W::new(self, 2)
}
#[doc = "Bit 3 - Port output 3"]
#[inline(always)]
pub fn p3(&mut self) -> P3_W<OUTrs> {
P3_W::new(self, 3)
}
#[doc = "Bit 4 - Port output 4"]
#[inline(always)]
pub fn p4(&mut self) -> P4_W<OUTrs> {
P4_W::new(self, 4)
}
#[doc = "Bit 5 - Port output 5"]
#[inline(always)]
pub fn p5(&mut self) -> P5_W<OUTrs> {
P5_W::new(self, 5)
}
#[doc = "Bit 6 - Port output 6"]
#[inline(always)]
pub fn p6(&mut self) -> P6_W<OUTrs> {
P6_W::new(self, 6)
}
#[doc = "Bit 7 - Port output 7"]
#[inline(always)]
pub fn p7(&mut self) -> P7_W<OUTrs> {
P7_W::new(self, 7)
}
}
#[doc = "GPIO Port Output\n\nYou can [`read`](crate::Reg::read) this register and get [`out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OUTrs;
impl crate::RegisterSpec for OUTrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`out::R`](R) reader structure"]
impl crate::Readable for OUTrs {}
#[doc = "`write(|w| ..)` method takes [`out::W`](W) writer structure"]
impl crate::Writable for OUTrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets OUT to value 0"]
impl crate::Resettable for OUTrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "OUTEN (rw) register accessor: GPIO Port Output Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`outen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`outen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outen`]
module"]
pub type OUTEN = crate::Reg<outen::OUTENrs>;
#[doc = "GPIO Port Output Enable"]
pub mod outen {
#[doc = "Register `OUTEN` reader"]
pub type R = crate::R<OUTENrs>;
#[doc = "Register `OUTEN` writer"]
pub type W = crate::W<OUTENrs>;
#[doc = "Port output enable 0\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: Output disabled, high-impedance state"]
Low = 0,
#[doc = "1: Output state set by GPIOn->OUT.P0"]
High = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port output enable 0"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::Low,
true => P0::High,
}
}
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P0::Low
}
#[doc = "Output state set by GPIOn->OUT.P0"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P0::High
}
}
#[doc = "Field `P0` writer - Port output enable 0"]
pub type P0_W<'a, REG> = crate::BitWriter<'a, REG, P0>;
impl<'a, REG> P0_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P0::Low)
}
#[doc = "Output state set by GPIOn->OUT.P0"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P0::High)
}
}
#[doc = "Port output enable 1\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: Output disabled, high-impedance state"]
Low = 0,
#[doc = "1: Output state set by GPIOn->OUT.P1"]
High = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port output enable 1"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::Low,
true => P1::High,
}
}
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P1::Low
}
#[doc = "Output state set by GPIOn->OUT.P1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P1::High
}
}
#[doc = "Field `P1` writer - Port output enable 1"]
pub type P1_W<'a, REG> = crate::BitWriter<'a, REG, P1>;
impl<'a, REG> P1_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P1::Low)
}
#[doc = "Output state set by GPIOn->OUT.P1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P1::High)
}
}
#[doc = "Port output enable 2\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: Output disabled, high-impedance state"]
Low = 0,
#[doc = "1: Output state set by GPIOn->OUT.P2"]
High = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port output enable 2"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::Low,
true => P2::High,
}
}
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P2::Low
}
#[doc = "Output state set by GPIOn->OUT.P2"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P2::High
}
}
#[doc = "Field `P2` writer - Port output enable 2"]
pub type P2_W<'a, REG> = crate::BitWriter<'a, REG, P2>;
impl<'a, REG> P2_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P2::Low)
}
#[doc = "Output state set by GPIOn->OUT.P2"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P2::High)
}
}
#[doc = "Port output enable 3\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: Output disabled, high-impedance state"]
Low = 0,
#[doc = "1: Output state set by GPIOn->OUT.P3"]
High = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port output enable 3"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::Low,
true => P3::High,
}
}
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P3::Low
}
#[doc = "Output state set by GPIOn->OUT.P3"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P3::High
}
}
#[doc = "Field `P3` writer - Port output enable 3"]
pub type P3_W<'a, REG> = crate::BitWriter<'a, REG, P3>;
impl<'a, REG> P3_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P3::Low)
}
#[doc = "Output state set by GPIOn->OUT.P3"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P3::High)
}
}
#[doc = "Port output enable 4\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: Output disabled, high-impedance state"]
Low = 0,
#[doc = "1: Output state set by GPIOn->OUT.P4"]
High = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port output enable 4"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::Low,
true => P4::High,
}
}
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P4::Low
}
#[doc = "Output state set by GPIOn->OUT.P4"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P4::High
}
}
#[doc = "Field `P4` writer - Port output enable 4"]
pub type P4_W<'a, REG> = crate::BitWriter<'a, REG, P4>;
impl<'a, REG> P4_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P4::Low)
}
#[doc = "Output state set by GPIOn->OUT.P4"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P4::High)
}
}
#[doc = "Port output enable 5\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: Output disabled, high-impedance state"]
Low = 0,
#[doc = "1: Output state set by GPIOn->OUT.P5"]
High = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port output enable 5"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::Low,
true => P5::High,
}
}
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P5::Low
}
#[doc = "Output state set by GPIOn->OUT.P5"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P5::High
}
}
#[doc = "Field `P5` writer - Port output enable 5"]
pub type P5_W<'a, REG> = crate::BitWriter<'a, REG, P5>;
impl<'a, REG> P5_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P5::Low)
}
#[doc = "Output state set by GPIOn->OUT.P5"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P5::High)
}
}
#[doc = "Port output enable 6\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: Output disabled, high-impedance state"]
Low = 0,
#[doc = "1: Output state set by GPIOn->OUT.P6"]
High = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port output enable 6"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::Low,
true => P6::High,
}
}
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P6::Low
}
#[doc = "Output state set by GPIOn->OUT.P6"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P6::High
}
}
#[doc = "Field `P6` writer - Port output enable 6"]
pub type P6_W<'a, REG> = crate::BitWriter<'a, REG, P6>;
impl<'a, REG> P6_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P6::Low)
}
#[doc = "Output state set by GPIOn->OUT.P6"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P6::High)
}
}
#[doc = "Port output enable 7\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: Output disabled, high-impedance state"]
Low = 0,
#[doc = "1: Output state set by GPIOn->OUT.P7"]
High = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port output enable 7"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::Low,
true => P7::High,
}
}
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P7::Low
}
#[doc = "Output state set by GPIOn->OUT.P7"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P7::High
}
}
#[doc = "Field `P7` writer - Port output enable 7"]
pub type P7_W<'a, REG> = crate::BitWriter<'a, REG, P7>;
impl<'a, REG> P7_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P7::Low)
}
#[doc = "Output state set by GPIOn->OUT.P7"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P7::High)
}
}
impl R {
#[doc = "Bit 0 - Port output enable 0"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port output enable 1"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port output enable 2"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port output enable 3"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port output enable 4"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port output enable 5"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port output enable 6"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port output enable 7"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OUTEN")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Port output enable 0"]
#[inline(always)]
pub fn p0(&mut self) -> P0_W<OUTENrs> {
P0_W::new(self, 0)
}
#[doc = "Bit 1 - Port output enable 1"]
#[inline(always)]
pub fn p1(&mut self) -> P1_W<OUTENrs> {
P1_W::new(self, 1)
}
#[doc = "Bit 2 - Port output enable 2"]
#[inline(always)]
pub fn p2(&mut self) -> P2_W<OUTENrs> {
P2_W::new(self, 2)
}
#[doc = "Bit 3 - Port output enable 3"]
#[inline(always)]
pub fn p3(&mut self) -> P3_W<OUTENrs> {
P3_W::new(self, 3)
}
#[doc = "Bit 4 - Port output enable 4"]
#[inline(always)]
pub fn p4(&mut self) -> P4_W<OUTENrs> {
P4_W::new(self, 4)
}
#[doc = "Bit 5 - Port output enable 5"]
#[inline(always)]
pub fn p5(&mut self) -> P5_W<OUTENrs> {
P5_W::new(self, 5)
}
#[doc = "Bit 6 - Port output enable 6"]
#[inline(always)]
pub fn p6(&mut self) -> P6_W<OUTENrs> {
P6_W::new(self, 6)
}
#[doc = "Bit 7 - Port output enable 7"]
#[inline(always)]
pub fn p7(&mut self) -> P7_W<OUTENrs> {
P7_W::new(self, 7)
}
}
#[doc = "GPIO Port Output Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`outen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`outen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OUTENrs;
impl crate::RegisterSpec for OUTENrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`outen::R`](R) reader structure"]
impl crate::Readable for OUTENrs {}
#[doc = "`write(|w| ..)` method takes [`outen::W`](W) writer structure"]
impl crate::Writable for OUTENrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets OUTEN to value 0"]
impl crate::Resettable for OUTENrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DS (rw) register accessor: GPIO Port Output Drive Strength Select\n\nYou can [`read`](crate::Reg::read) this register and get [`ds::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ds::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ds`]
module"]
pub type DS = crate::Reg<ds::DSrs>;
#[doc = "GPIO Port Output Drive Strength Select"]
pub mod ds {
#[doc = "Register `DS` reader"]
pub type R = crate::R<DSrs>;
#[doc = "Register `DS` writer"]
pub type W = crate::W<DSrs>;
#[doc = "Port output drive strength select 0\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: Low output drive strength selected"]
Low = 0,
#[doc = "1: High output drive strength selected"]
High = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port output drive strength select 0"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::Low,
true => P0::High,
}
}
#[doc = "Low output drive strength selected"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P0::Low
}
#[doc = "High output drive strength selected"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P0::High
}
}
#[doc = "Field `P0` writer - Port output drive strength select 0"]
pub type P0_W<'a, REG> = crate::BitWriter<'a, REG, P0>;
impl<'a, REG> P0_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Low output drive strength selected"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P0::Low)
}
#[doc = "High output drive strength selected"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P0::High)
}
}
#[doc = "Port output drive strength select 1\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: Low output drive strength selected"]
Low = 0,
#[doc = "1: High output drive strength selected"]
High = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port output drive strength select 1"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::Low,
true => P1::High,
}
}
#[doc = "Low output drive strength selected"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P1::Low
}
#[doc = "High output drive strength selected"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P1::High
}
}
#[doc = "Field `P1` writer - Port output drive strength select 1"]
pub type P1_W<'a, REG> = crate::BitWriter<'a, REG, P1>;
impl<'a, REG> P1_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Low output drive strength selected"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P1::Low)
}
#[doc = "High output drive strength selected"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P1::High)
}
}
#[doc = "Port output drive strength select 2\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: Low output drive strength selected"]
Low = 0,
#[doc = "1: High output drive strength selected"]
High = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port output drive strength select 2"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::Low,
true => P2::High,
}
}
#[doc = "Low output drive strength selected"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P2::Low
}
#[doc = "High output drive strength selected"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P2::High
}
}
#[doc = "Field `P2` writer - Port output drive strength select 2"]
pub type P2_W<'a, REG> = crate::BitWriter<'a, REG, P2>;
impl<'a, REG> P2_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Low output drive strength selected"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P2::Low)
}
#[doc = "High output drive strength selected"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P2::High)
}
}
#[doc = "Port output drive strength select 3\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: Low output drive strength selected"]
Low = 0,
#[doc = "1: High output drive strength selected"]
High = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port output drive strength select 3"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::Low,
true => P3::High,
}
}
#[doc = "Low output drive strength selected"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P3::Low
}
#[doc = "High output drive strength selected"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P3::High
}
}
#[doc = "Field `P3` writer - Port output drive strength select 3"]
pub type P3_W<'a, REG> = crate::BitWriter<'a, REG, P3>;
impl<'a, REG> P3_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Low output drive strength selected"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P3::Low)
}
#[doc = "High output drive strength selected"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P3::High)
}
}
#[doc = "Port output drive strength select 4\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: Low output drive strength selected"]
Low = 0,
#[doc = "1: High output drive strength selected"]
High = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port output drive strength select 4"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::Low,
true => P4::High,
}
}
#[doc = "Low output drive strength selected"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P4::Low
}
#[doc = "High output drive strength selected"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P4::High
}
}
#[doc = "Field `P4` writer - Port output drive strength select 4"]
pub type P4_W<'a, REG> = crate::BitWriter<'a, REG, P4>;
impl<'a, REG> P4_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Low output drive strength selected"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P4::Low)
}
#[doc = "High output drive strength selected"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P4::High)
}
}
#[doc = "Port output drive strength select 5\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: Low output drive strength selected"]
Low = 0,
#[doc = "1: High output drive strength selected"]
High = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port output drive strength select 5"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::Low,
true => P5::High,
}
}
#[doc = "Low output drive strength selected"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P5::Low
}
#[doc = "High output drive strength selected"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P5::High
}
}
#[doc = "Field `P5` writer - Port output drive strength select 5"]
pub type P5_W<'a, REG> = crate::BitWriter<'a, REG, P5>;
impl<'a, REG> P5_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Low output drive strength selected"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P5::Low)
}
#[doc = "High output drive strength selected"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P5::High)
}
}
#[doc = "Port output drive strength select 6\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: Low output drive strength selected"]
Low = 0,
#[doc = "1: High output drive strength selected"]
High = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port output drive strength select 6"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::Low,
true => P6::High,
}
}
#[doc = "Low output drive strength selected"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P6::Low
}
#[doc = "High output drive strength selected"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P6::High
}
}
#[doc = "Field `P6` writer - Port output drive strength select 6"]
pub type P6_W<'a, REG> = crate::BitWriter<'a, REG, P6>;
impl<'a, REG> P6_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Low output drive strength selected"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P6::Low)
}
#[doc = "High output drive strength selected"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P6::High)
}
}
#[doc = "Port output drive strength select 7\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: Low output drive strength selected"]
Low = 0,
#[doc = "1: High output drive strength selected"]
High = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port output drive strength select 7"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::Low,
true => P7::High,
}
}
#[doc = "Low output drive strength selected"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P7::Low
}
#[doc = "High output drive strength selected"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P7::High
}
}
#[doc = "Field `P7` writer - Port output drive strength select 7"]
pub type P7_W<'a, REG> = crate::BitWriter<'a, REG, P7>;
impl<'a, REG> P7_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Low output drive strength selected"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P7::Low)
}
#[doc = "High output drive strength selected"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P7::High)
}
}
impl R {
#[doc = "Bit 0 - Port output drive strength select 0"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port output drive strength select 1"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port output drive strength select 2"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port output drive strength select 3"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port output drive strength select 4"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port output drive strength select 5"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port output drive strength select 6"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port output drive strength select 7"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DS")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Port output drive strength select 0"]
#[inline(always)]
pub fn p0(&mut self) -> P0_W<DSrs> {
P0_W::new(self, 0)
}
#[doc = "Bit 1 - Port output drive strength select 1"]
#[inline(always)]
pub fn p1(&mut self) -> P1_W<DSrs> {
P1_W::new(self, 1)
}
#[doc = "Bit 2 - Port output drive strength select 2"]
#[inline(always)]
pub fn p2(&mut self) -> P2_W<DSrs> {
P2_W::new(self, 2)
}
#[doc = "Bit 3 - Port output drive strength select 3"]
#[inline(always)]
pub fn p3(&mut self) -> P3_W<DSrs> {
P3_W::new(self, 3)
}
#[doc = "Bit 4 - Port output drive strength select 4"]
#[inline(always)]
pub fn p4(&mut self) -> P4_W<DSrs> {
P4_W::new(self, 4)
}
#[doc = "Bit 5 - Port output drive strength select 5"]
#[inline(always)]
pub fn p5(&mut self) -> P5_W<DSrs> {
P5_W::new(self, 5)
}
#[doc = "Bit 6 - Port output drive strength select 6"]
#[inline(always)]
pub fn p6(&mut self) -> P6_W<DSrs> {
P6_W::new(self, 6)
}
#[doc = "Bit 7 - Port output drive strength select 7"]
#[inline(always)]
pub fn p7(&mut self) -> P7_W<DSrs> {
P7_W::new(self, 7)
}
}
#[doc = "GPIO Port Output Drive Strength Select\n\nYou can [`read`](crate::Reg::read) this register and get [`ds::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ds::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DSrs;
impl crate::RegisterSpec for DSrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`ds::R`](R) reader structure"]
impl crate::Readable for DSrs {}
#[doc = "`write(|w| ..)` method takes [`ds::W`](W) writer structure"]
impl crate::Writable for DSrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DS to value 0"]
impl crate::Resettable for DSrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PU (rw) register accessor: GPIO Port Weak Pull Up\n\nYou can [`read`](crate::Reg::read) this register and get [`pu::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pu::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pu`]
module"]
pub type PU = crate::Reg<pu::PUrs>;
#[doc = "GPIO Port Weak Pull Up"]
pub mod pu {
#[doc = "Register `PU` reader"]
pub type R = crate::R<PUrs>;
#[doc = "Register `PU` writer"]
pub type W = crate::W<PUrs>;
#[doc = "Port<n>0 weak pull-up select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: Weak pull-up disabled"]
Disabled = 0,
#[doc = "1: Weak pull-up to VCCIO enabled"]
Enabled = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port<n>0 weak pull-up select"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::Disabled,
true => P0::Enabled,
}
}
#[doc = "Weak pull-up disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P0::Disabled
}
#[doc = "Weak pull-up to VCCIO enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P0::Enabled
}
}
#[doc = "Field `P0` writer - Port<n>0 weak pull-up select"]
pub type P0_W<'a, REG> = crate::BitWriter<'a, REG, P0>;
impl<'a, REG> P0_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Weak pull-up disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P0::Disabled)
}
#[doc = "Weak pull-up to VCCIO enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P0::Enabled)
}
}
#[doc = "Port<n>1 weak pull-up select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: Weak pull-up disabled"]
Disabled = 0,
#[doc = "1: Weak pull-up to VCCIO enabled"]
Enabled = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port<n>1 weak pull-up select"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::Disabled,
true => P1::Enabled,
}
}
#[doc = "Weak pull-up disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P1::Disabled
}
#[doc = "Weak pull-up to VCCIO enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P1::Enabled
}
}
#[doc = "Field `P1` writer - Port<n>1 weak pull-up select"]
pub type P1_W<'a, REG> = crate::BitWriter<'a, REG, P1>;
impl<'a, REG> P1_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Weak pull-up disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P1::Disabled)
}
#[doc = "Weak pull-up to VCCIO enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P1::Enabled)
}
}
#[doc = "Port<n>2 weak pull-up select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: Weak pull-up disabled"]
Disabled = 0,
#[doc = "1: Weak pull-up to VCCIO enabled"]
Enabled = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port<n>2 weak pull-up select"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::Disabled,
true => P2::Enabled,
}
}
#[doc = "Weak pull-up disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P2::Disabled
}
#[doc = "Weak pull-up to VCCIO enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P2::Enabled
}
}
#[doc = "Field `P2` writer - Port<n>2 weak pull-up select"]
pub type P2_W<'a, REG> = crate::BitWriter<'a, REG, P2>;
impl<'a, REG> P2_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Weak pull-up disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P2::Disabled)
}
#[doc = "Weak pull-up to VCCIO enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P2::Enabled)
}
}
#[doc = "Port<n>3 weak pull-up select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: Weak pull-up disabled"]
Disabled = 0,
#[doc = "1: Weak pull-up to VCCIO enabled"]
Enabled = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port<n>3 weak pull-up select"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::Disabled,
true => P3::Enabled,
}
}
#[doc = "Weak pull-up disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P3::Disabled
}
#[doc = "Weak pull-up to VCCIO enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P3::Enabled
}
}
#[doc = "Field `P3` writer - Port<n>3 weak pull-up select"]
pub type P3_W<'a, REG> = crate::BitWriter<'a, REG, P3>;
impl<'a, REG> P3_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Weak pull-up disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P3::Disabled)
}
#[doc = "Weak pull-up to VCCIO enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P3::Enabled)
}
}
#[doc = "Port<n>4 weak pull-up select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: Weak pull-up disabled"]
Disabled = 0,
#[doc = "1: Weak pull-up to VCCIO enabled"]
Enabled = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port<n>4 weak pull-up select"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::Disabled,
true => P4::Enabled,
}
}
#[doc = "Weak pull-up disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P4::Disabled
}
#[doc = "Weak pull-up to VCCIO enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P4::Enabled
}
}
#[doc = "Field `P4` writer - Port<n>4 weak pull-up select"]
pub type P4_W<'a, REG> = crate::BitWriter<'a, REG, P4>;
impl<'a, REG> P4_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Weak pull-up disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P4::Disabled)
}
#[doc = "Weak pull-up to VCCIO enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P4::Enabled)
}
}
#[doc = "Port<n>5 weak pull-up select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: Weak pull-up disabled"]
Disabled = 0,
#[doc = "1: Weak pull-up to VCCIO enabled"]
Enabled = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port<n>5 weak pull-up select"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::Disabled,
true => P5::Enabled,
}
}
#[doc = "Weak pull-up disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P5::Disabled
}
#[doc = "Weak pull-up to VCCIO enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P5::Enabled
}
}
#[doc = "Field `P5` writer - Port<n>5 weak pull-up select"]
pub type P5_W<'a, REG> = crate::BitWriter<'a, REG, P5>;
impl<'a, REG> P5_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Weak pull-up disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P5::Disabled)
}
#[doc = "Weak pull-up to VCCIO enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P5::Enabled)
}
}
#[doc = "Port<n>6 weak pull-up select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: Weak pull-up disabled"]
Disabled = 0,
#[doc = "1: Weak pull-up to VCCIO enabled"]
Enabled = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port<n>6 weak pull-up select"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::Disabled,
true => P6::Enabled,
}
}
#[doc = "Weak pull-up disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P6::Disabled
}
#[doc = "Weak pull-up to VCCIO enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P6::Enabled
}
}
#[doc = "Field `P6` writer - Port<n>6 weak pull-up select"]
pub type P6_W<'a, REG> = crate::BitWriter<'a, REG, P6>;
impl<'a, REG> P6_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Weak pull-up disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P6::Disabled)
}
#[doc = "Weak pull-up to VCCIO enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P6::Enabled)
}
}
#[doc = "Port<n>7 weak pull-up select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: Weak pull-up disabled"]
Disabled = 0,
#[doc = "1: Weak pull-up to VCCIO enabled"]
Enabled = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port<n>7 weak pull-up select"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::Disabled,
true => P7::Enabled,
}
}
#[doc = "Weak pull-up disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P7::Disabled
}
#[doc = "Weak pull-up to VCCIO enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P7::Enabled
}
}
#[doc = "Field `P7` writer - Port<n>7 weak pull-up select"]
pub type P7_W<'a, REG> = crate::BitWriter<'a, REG, P7>;
impl<'a, REG> P7_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Weak pull-up disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P7::Disabled)
}
#[doc = "Weak pull-up to VCCIO enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P7::Enabled)
}
}
impl R {
#[doc = "Bit 0 - Port<n>0 weak pull-up select"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port<n>1 weak pull-up select"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port<n>2 weak pull-up select"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port<n>3 weak pull-up select"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port<n>4 weak pull-up select"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port<n>5 weak pull-up select"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port<n>6 weak pull-up select"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port<n>7 weak pull-up select"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PU")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Port<n>0 weak pull-up select"]
#[inline(always)]
pub fn p0(&mut self) -> P0_W<PUrs> {
P0_W::new(self, 0)
}
#[doc = "Bit 1 - Port<n>1 weak pull-up select"]
#[inline(always)]
pub fn p1(&mut self) -> P1_W<PUrs> {
P1_W::new(self, 1)
}
#[doc = "Bit 2 - Port<n>2 weak pull-up select"]
#[inline(always)]
pub fn p2(&mut self) -> P2_W<PUrs> {
P2_W::new(self, 2)
}
#[doc = "Bit 3 - Port<n>3 weak pull-up select"]
#[inline(always)]
pub fn p3(&mut self) -> P3_W<PUrs> {
P3_W::new(self, 3)
}
#[doc = "Bit 4 - Port<n>4 weak pull-up select"]
#[inline(always)]
pub fn p4(&mut self) -> P4_W<PUrs> {
P4_W::new(self, 4)
}
#[doc = "Bit 5 - Port<n>5 weak pull-up select"]
#[inline(always)]
pub fn p5(&mut self) -> P5_W<PUrs> {
P5_W::new(self, 5)
}
#[doc = "Bit 6 - Port<n>6 weak pull-up select"]
#[inline(always)]
pub fn p6(&mut self) -> P6_W<PUrs> {
P6_W::new(self, 6)
}
#[doc = "Bit 7 - Port<n>7 weak pull-up select"]
#[inline(always)]
pub fn p7(&mut self) -> P7_W<PUrs> {
P7_W::new(self, 7)
}
}
#[doc = "GPIO Port Weak Pull Up\n\nYou can [`read`](crate::Reg::read) this register and get [`pu::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pu::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PUrs;
impl crate::RegisterSpec for PUrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`pu::R`](R) reader structure"]
impl crate::Readable for PUrs {}
#[doc = "`write(|w| ..)` method takes [`pu::W`](W) writer structure"]
impl crate::Writable for PUrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PU to value 0"]
impl crate::Resettable for PUrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PD (rw) register accessor: GPIO Port Weak Pull Down\n\nYou can [`read`](crate::Reg::read) this register and get [`pd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pd`]
module"]
pub type PD = crate::Reg<pd::PDrs>;
#[doc = "GPIO Port Weak Pull Down"]
pub mod pd {
#[doc = "Register `PD` reader"]
pub type R = crate::R<PDrs>;
#[doc = "Register `PD` writer"]
pub type W = crate::W<PDrs>;
#[doc = "Port<n>0 weak pull-down select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: Weak pull-down disabled"]
Disabled = 0,
#[doc = "1: Weak pull-down to VSS enabled"]
Enabled = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port<n>0 weak pull-down select"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::Disabled,
true => P0::Enabled,
}
}
#[doc = "Weak pull-down disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P0::Disabled
}
#[doc = "Weak pull-down to VSS enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P0::Enabled
}
}
#[doc = "Field `P0` writer - Port<n>0 weak pull-down select"]
pub type P0_W<'a, REG> = crate::BitWriter<'a, REG, P0>;
impl<'a, REG> P0_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Weak pull-down disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P0::Disabled)
}
#[doc = "Weak pull-down to VSS enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P0::Enabled)
}
}
#[doc = "Port<n>1 weak pull-down select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: Weak pull-down disabled"]
Disabled = 0,
#[doc = "1: Weak pull-down to VSS enabled"]
Enabled = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port<n>1 weak pull-down select"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::Disabled,
true => P1::Enabled,
}
}
#[doc = "Weak pull-down disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P1::Disabled
}
#[doc = "Weak pull-down to VSS enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P1::Enabled
}
}
#[doc = "Field `P1` writer - Port<n>1 weak pull-down select"]
pub type P1_W<'a, REG> = crate::BitWriter<'a, REG, P1>;
impl<'a, REG> P1_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Weak pull-down disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P1::Disabled)
}
#[doc = "Weak pull-down to VSS enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P1::Enabled)
}
}
#[doc = "Port<n>2 weak pull-down select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: Weak pull-down disabled"]
Disabled = 0,
#[doc = "1: Weak pull-down to VSS enabled"]
Enabled = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port<n>2 weak pull-down select"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::Disabled,
true => P2::Enabled,
}
}
#[doc = "Weak pull-down disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P2::Disabled
}
#[doc = "Weak pull-down to VSS enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P2::Enabled
}
}
#[doc = "Field `P2` writer - Port<n>2 weak pull-down select"]
pub type P2_W<'a, REG> = crate::BitWriter<'a, REG, P2>;
impl<'a, REG> P2_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Weak pull-down disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P2::Disabled)
}
#[doc = "Weak pull-down to VSS enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P2::Enabled)
}
}
#[doc = "Port<n>3 weak pull-down select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: Weak pull-down disabled"]
Disabled = 0,
#[doc = "1: Weak pull-down to VSS enabled"]
Enabled = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port<n>3 weak pull-down select"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::Disabled,
true => P3::Enabled,
}
}
#[doc = "Weak pull-down disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P3::Disabled
}
#[doc = "Weak pull-down to VSS enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P3::Enabled
}
}
#[doc = "Field `P3` writer - Port<n>3 weak pull-down select"]
pub type P3_W<'a, REG> = crate::BitWriter<'a, REG, P3>;
impl<'a, REG> P3_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Weak pull-down disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P3::Disabled)
}
#[doc = "Weak pull-down to VSS enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P3::Enabled)
}
}
#[doc = "Port<n>4 weak pull-down select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: Weak pull-down disabled"]
Disabled = 0,
#[doc = "1: Weak pull-down to VSS enabled"]
Enabled = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port<n>4 weak pull-down select"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::Disabled,
true => P4::Enabled,
}
}
#[doc = "Weak pull-down disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P4::Disabled
}
#[doc = "Weak pull-down to VSS enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P4::Enabled
}
}
#[doc = "Field `P4` writer - Port<n>4 weak pull-down select"]
pub type P4_W<'a, REG> = crate::BitWriter<'a, REG, P4>;
impl<'a, REG> P4_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Weak pull-down disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P4::Disabled)
}
#[doc = "Weak pull-down to VSS enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P4::Enabled)
}
}
#[doc = "Port<n>0 weak pull-down select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: Weak pull-down disabled"]
Disabled = 0,
#[doc = "1: Weak pull-down to VSS enabled"]
Enabled = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port<n>0 weak pull-down select"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::Disabled,
true => P5::Enabled,
}
}
#[doc = "Weak pull-down disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P5::Disabled
}
#[doc = "Weak pull-down to VSS enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P5::Enabled
}
}
#[doc = "Field `P5` writer - Port<n>0 weak pull-down select"]
pub type P5_W<'a, REG> = crate::BitWriter<'a, REG, P5>;
impl<'a, REG> P5_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Weak pull-down disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P5::Disabled)
}
#[doc = "Weak pull-down to VSS enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P5::Enabled)
}
}
#[doc = "Port<n>6 weak pull-down select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: Weak pull-down disabled"]
Disabled = 0,
#[doc = "1: Weak pull-down to VSS enabled"]
Enabled = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port<n>6 weak pull-down select"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::Disabled,
true => P6::Enabled,
}
}
#[doc = "Weak pull-down disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P6::Disabled
}
#[doc = "Weak pull-down to VSS enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P6::Enabled
}
}
#[doc = "Field `P6` writer - Port<n>6 weak pull-down select"]
pub type P6_W<'a, REG> = crate::BitWriter<'a, REG, P6>;
impl<'a, REG> P6_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Weak pull-down disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P6::Disabled)
}
#[doc = "Weak pull-down to VSS enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P6::Enabled)
}
}
#[doc = "Port<n>7 weak pull-down select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: Weak pull-down disabled"]
Disabled = 0,
#[doc = "1: Weak pull-down to VSS enabled"]
Enabled = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port<n>7 weak pull-down select"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::Disabled,
true => P7::Enabled,
}
}
#[doc = "Weak pull-down disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P7::Disabled
}
#[doc = "Weak pull-down to VSS enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P7::Enabled
}
}
#[doc = "Field `P7` writer - Port<n>7 weak pull-down select"]
pub type P7_W<'a, REG> = crate::BitWriter<'a, REG, P7>;
impl<'a, REG> P7_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Weak pull-down disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P7::Disabled)
}
#[doc = "Weak pull-down to VSS enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P7::Enabled)
}
}
impl R {
#[doc = "Bit 0 - Port<n>0 weak pull-down select"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port<n>1 weak pull-down select"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port<n>2 weak pull-down select"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port<n>3 weak pull-down select"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port<n>4 weak pull-down select"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port<n>0 weak pull-down select"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port<n>6 weak pull-down select"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port<n>7 weak pull-down select"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PD")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Port<n>0 weak pull-down select"]
#[inline(always)]
pub fn p0(&mut self) -> P0_W<PDrs> {
P0_W::new(self, 0)
}
#[doc = "Bit 1 - Port<n>1 weak pull-down select"]
#[inline(always)]
pub fn p1(&mut self) -> P1_W<PDrs> {
P1_W::new(self, 1)
}
#[doc = "Bit 2 - Port<n>2 weak pull-down select"]
#[inline(always)]
pub fn p2(&mut self) -> P2_W<PDrs> {
P2_W::new(self, 2)
}
#[doc = "Bit 3 - Port<n>3 weak pull-down select"]
#[inline(always)]
pub fn p3(&mut self) -> P3_W<PDrs> {
P3_W::new(self, 3)
}
#[doc = "Bit 4 - Port<n>4 weak pull-down select"]
#[inline(always)]
pub fn p4(&mut self) -> P4_W<PDrs> {
P4_W::new(self, 4)
}
#[doc = "Bit 5 - Port<n>0 weak pull-down select"]
#[inline(always)]
pub fn p5(&mut self) -> P5_W<PDrs> {
P5_W::new(self, 5)
}
#[doc = "Bit 6 - Port<n>6 weak pull-down select"]
#[inline(always)]
pub fn p6(&mut self) -> P6_W<PDrs> {
P6_W::new(self, 6)
}
#[doc = "Bit 7 - Port<n>7 weak pull-down select"]
#[inline(always)]
pub fn p7(&mut self) -> P7_W<PDrs> {
P7_W::new(self, 7)
}
}
#[doc = "GPIO Port Weak Pull Down\n\nYou can [`read`](crate::Reg::read) this register and get [`pd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PDrs;
impl crate::RegisterSpec for PDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`pd::R`](R) reader structure"]
impl crate::Readable for PDrs {}
#[doc = "`write(|w| ..)` method takes [`pd::W`](W) writer structure"]
impl crate::Writable for PDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PD to value 0"]
impl crate::Resettable for PDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IN (r) register accessor: GPIO Port Input\n\nYou can [`read`](crate::Reg::read) this register and get [`in_::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_`]
module"]
pub type IN = crate::Reg<in_::INrs>;
#[doc = "GPIO Port Input"]
pub mod in_ {
#[doc = "Register `IN` reader"]
pub type R = crate::R<INrs>;
#[doc = "Port<n>0 input state\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: Logic low"]
Low = 0,
#[doc = "1: Logic high"]
High = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port<n>0 input state"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::Low,
true => P0::High,
}
}
#[doc = "Logic low"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P0::Low
}
#[doc = "Logic high"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P0::High
}
}
#[doc = "Port<n>1 input state\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: Logic low"]
Low = 0,
#[doc = "1: Logic high"]
High = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port<n>1 input state"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::Low,
true => P1::High,
}
}
#[doc = "Logic low"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P1::Low
}
#[doc = "Logic high"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P1::High
}
}
#[doc = "Port<n>2 input state\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: Logic low"]
Low = 0,
#[doc = "1: Logic high"]
High = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port<n>2 input state"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::Low,
true => P2::High,
}
}
#[doc = "Logic low"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P2::Low
}
#[doc = "Logic high"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P2::High
}
}
#[doc = "Port<n>3 input state\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: Logic low"]
Low = 0,
#[doc = "1: Logic high"]
High = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port<n>3 input state"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::Low,
true => P3::High,
}
}
#[doc = "Logic low"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P3::Low
}
#[doc = "Logic high"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P3::High
}
}
#[doc = "Port<n>4 input state\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: Logic low"]
Low = 0,
#[doc = "1: Logic high"]
High = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port<n>4 input state"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::Low,
true => P4::High,
}
}
#[doc = "Logic low"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P4::Low
}
#[doc = "Logic high"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P4::High
}
}
#[doc = "Port<n>5 input state\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: Logic low"]
Low = 0,
#[doc = "1: Logic high"]
High = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port<n>5 input state"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::Low,
true => P5::High,
}
}
#[doc = "Logic low"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P5::Low
}
#[doc = "Logic high"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P5::High
}
}
#[doc = "Port<n>6 input state\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: Logic low"]
Low = 0,
#[doc = "1: Logic high"]
High = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port<n>6 input state"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::Low,
true => P6::High,
}
}
#[doc = "Logic low"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P6::Low
}
#[doc = "Logic high"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P6::High
}
}
#[doc = "Port<n>7 input state\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: Logic low"]
Low = 0,
#[doc = "1: Logic high"]
High = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port<n>7 input state"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::Low,
true => P7::High,
}
}
#[doc = "Logic low"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P7::Low
}
#[doc = "Logic high"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P7::High
}
}
impl R {
#[doc = "Bit 0 - Port<n>0 input state"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port<n>1 input state"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port<n>2 input state"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port<n>3 input state"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port<n>4 input state"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port<n>5 input state"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port<n>6 input state"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port<n>7 input state"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("IN")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
#[doc = "GPIO Port Input\n\nYou can [`read`](crate::Reg::read) this register and get [`in_::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INrs;
impl crate::RegisterSpec for INrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`in_::R`](R) reader structure"]
impl crate::Readable for INrs {}
#[doc = "`reset()` method sets IN to value 0"]
impl crate::Resettable for INrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "PSEL (rw) register accessor: GPIO Peripheral Select\n\nYou can [`read`](crate::Reg::read) this register and get [`psel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psel`]
module"]
pub type PSEL = crate::Reg<psel::PSELrs>;
#[doc = "GPIO Peripheral Select"]
pub mod psel {
#[doc = "Register `PSEL` reader"]
pub type R = crate::R<PSELrs>;
#[doc = "Register `PSEL` writer"]
pub type W = crate::W<PSELrs>;
#[doc = "Port<n>0 peripheral select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum P0 {
#[doc = "0: Port in I/O mode"]
Io = 0,
#[doc = "1: Peripheral Configuration 1"]
Peripheral1 = 1,
#[doc = "2: Peripheral Configuration 2"]
Peripheral2 = 2,
#[doc = "3: Peripheral Configuration 3"]
Peripheral3 = 3,
}
impl From<P0> for u8 {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as _
}
}
impl crate::FieldSpec for P0 {
type Ux = u8;
}
impl crate::IsEnum for P0 {}
#[doc = "Field `P0` reader - Port<n>0 peripheral select"]
pub type P0_R = crate::FieldReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
0 => P0::Io,
1 => P0::Peripheral1,
2 => P0::Peripheral2,
3 => P0::Peripheral3,
_ => unreachable!(),
}
}
#[doc = "Port in I/O mode"]
#[inline(always)]
pub fn is_io(&self) -> bool {
*self == P0::Io
}
#[doc = "Peripheral Configuration 1"]
#[inline(always)]
pub fn is_peripheral_1(&self) -> bool {
*self == P0::Peripheral1
}
#[doc = "Peripheral Configuration 2"]
#[inline(always)]
pub fn is_peripheral_2(&self) -> bool {
*self == P0::Peripheral2
}
#[doc = "Peripheral Configuration 3"]
#[inline(always)]
pub fn is_peripheral_3(&self) -> bool {
*self == P0::Peripheral3
}
}
#[doc = "Field `P0` writer - Port<n>0 peripheral select"]
pub type P0_W<'a, REG> = crate::FieldWriter<'a, REG, 2, P0, crate::Safe>;
impl<'a, REG> P0_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Port in I/O mode"]
#[inline(always)]
pub fn io(self) -> &'a mut crate::W<REG> {
self.variant(P0::Io)
}
#[doc = "Peripheral Configuration 1"]
#[inline(always)]
pub fn peripheral_1(self) -> &'a mut crate::W<REG> {
self.variant(P0::Peripheral1)
}
#[doc = "Peripheral Configuration 2"]
#[inline(always)]
pub fn peripheral_2(self) -> &'a mut crate::W<REG> {
self.variant(P0::Peripheral2)
}
#[doc = "Peripheral Configuration 3"]
#[inline(always)]
pub fn peripheral_3(self) -> &'a mut crate::W<REG> {
self.variant(P0::Peripheral3)
}
}
#[doc = "Field `P1` reader - Port<n>1 peripheral select"]
pub use P0_R as P1_R;
#[doc = "Field `P2` reader - Port<n>2 peripheral select"]
pub use P0_R as P2_R;
#[doc = "Field `P3` reader - Port<n>3 peripheral select"]
pub use P0_R as P3_R;
#[doc = "Field `P4` reader - Port<n>4 peripheral select"]
pub use P0_R as P4_R;
#[doc = "Field `P5` reader - Port<n>5 peripheral select"]
pub use P0_R as P5_R;
#[doc = "Field `P6` reader - Port<n>6 peripheral select"]
pub use P0_R as P6_R;
#[doc = "Field `P7` reader - Port<n>7 peripheral select"]
pub use P0_R as P7_R;
#[doc = "Field `P1` writer - Port<n>1 peripheral select"]
pub use P0_W as P1_W;
#[doc = "Field `P2` writer - Port<n>2 peripheral select"]
pub use P0_W as P2_W;
#[doc = "Field `P3` writer - Port<n>3 peripheral select"]
pub use P0_W as P3_W;
#[doc = "Field `P4` writer - Port<n>4 peripheral select"]
pub use P0_W as P4_W;
#[doc = "Field `P5` writer - Port<n>5 peripheral select"]
pub use P0_W as P5_W;
#[doc = "Field `P6` writer - Port<n>6 peripheral select"]
pub use P0_W as P6_W;
#[doc = "Field `P7` writer - Port<n>7 peripheral select"]
pub use P0_W as P7_W;
impl R {
#[doc = "Bits 0:1 - Port<n>0 peripheral select"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3 - Port<n>1 peripheral select"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:5 - Port<n>2 peripheral select"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:7 - Port<n>3 peripheral select"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:9 - Port<n>4 peripheral select"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - Port<n>5 peripheral select"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - Port<n>6 peripheral select"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Port<n>7 peripheral select"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 14) & 3) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PSEL")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
impl W {
#[doc = "Bits 0:1 - Port<n>0 peripheral select"]
#[inline(always)]
pub fn p0(&mut self) -> P0_W<PSELrs> {
P0_W::new(self, 0)
}
#[doc = "Bits 2:3 - Port<n>1 peripheral select"]
#[inline(always)]
pub fn p1(&mut self) -> P1_W<PSELrs> {
P1_W::new(self, 2)
}
#[doc = "Bits 4:5 - Port<n>2 peripheral select"]
#[inline(always)]
pub fn p2(&mut self) -> P2_W<PSELrs> {
P2_W::new(self, 4)
}
#[doc = "Bits 6:7 - Port<n>3 peripheral select"]
#[inline(always)]
pub fn p3(&mut self) -> P3_W<PSELrs> {
P3_W::new(self, 6)
}
#[doc = "Bits 8:9 - Port<n>4 peripheral select"]
#[inline(always)]
pub fn p4(&mut self) -> P4_W<PSELrs> {
P4_W::new(self, 8)
}
#[doc = "Bits 10:11 - Port<n>5 peripheral select"]
#[inline(always)]
pub fn p5(&mut self) -> P5_W<PSELrs> {
P5_W::new(self, 10)
}
#[doc = "Bits 12:13 - Port<n>6 peripheral select"]
#[inline(always)]
pub fn p6(&mut self) -> P6_W<PSELrs> {
P6_W::new(self, 12)
}
#[doc = "Bits 14:15 - Port<n>7 peripheral select"]
#[inline(always)]
pub fn p7(&mut self) -> P7_W<PSELrs> {
P7_W::new(self, 14)
}
}
#[doc = "GPIO Peripheral Select\n\nYou can [`read`](crate::Reg::read) this register and get [`psel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PSELrs;
impl crate::RegisterSpec for PSELrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`psel::R`](R) reader structure"]
impl crate::Readable for PSELrs {}
#[doc = "`write(|w| ..)` method takes [`psel::W`](W) writer structure"]
impl crate::Writable for PSELrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PSEL to value 0"]
impl crate::Resettable for PSELrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INTP (rw) register accessor: GPIO Port Interrupt Polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`intp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intp`]
module"]
pub type INTP = crate::Reg<intp::INTPrs>;
#[doc = "GPIO Port Interrupt Polarity"]
pub mod intp {
#[doc = "Register `INTP` reader"]
pub type R = crate::R<INTPrs>;
#[doc = "Register `INTP` writer"]
pub type W = crate::W<INTPrs>;
#[doc = "Port<n>0 Interrupt Polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: Falling edge, high to low transition"]
Falling = 0,
#[doc = "1: Rising edge, low to high transition"]
Rising = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port<n>0 Interrupt Polarity"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::Falling,
true => P0::Rising,
}
}
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn is_falling(&self) -> bool {
*self == P0::Falling
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == P0::Rising
}
}
#[doc = "Field `P0` writer - Port<n>0 Interrupt Polarity"]
pub type P0_W<'a, REG> = crate::BitWriter<'a, REG, P0>;
impl<'a, REG> P0_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn falling(self) -> &'a mut crate::W<REG> {
self.variant(P0::Falling)
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn rising(self) -> &'a mut crate::W<REG> {
self.variant(P0::Rising)
}
}
#[doc = "Port<n>1 Interrupt Polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: Falling edge, high to low transition"]
Falling = 0,
#[doc = "1: Rising edge, low to high transition"]
Rising = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port<n>1 Interrupt Polarity"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::Falling,
true => P1::Rising,
}
}
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn is_falling(&self) -> bool {
*self == P1::Falling
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == P1::Rising
}
}
#[doc = "Field `P1` writer - Port<n>1 Interrupt Polarity"]
pub type P1_W<'a, REG> = crate::BitWriter<'a, REG, P1>;
impl<'a, REG> P1_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn falling(self) -> &'a mut crate::W<REG> {
self.variant(P1::Falling)
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn rising(self) -> &'a mut crate::W<REG> {
self.variant(P1::Rising)
}
}
#[doc = "Port<n>2 Interrupt Polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: Falling edge, high to low transition"]
Falling = 0,
#[doc = "1: Rising edge, low to high transition"]
Rising = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port<n>2 Interrupt Polarity"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::Falling,
true => P2::Rising,
}
}
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn is_falling(&self) -> bool {
*self == P2::Falling
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == P2::Rising
}
}
#[doc = "Field `P2` writer - Port<n>2 Interrupt Polarity"]
pub type P2_W<'a, REG> = crate::BitWriter<'a, REG, P2>;
impl<'a, REG> P2_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn falling(self) -> &'a mut crate::W<REG> {
self.variant(P2::Falling)
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn rising(self) -> &'a mut crate::W<REG> {
self.variant(P2::Rising)
}
}
#[doc = "Port<n>3 Interrupt Polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: Falling edge, high to low transition"]
Falling = 0,
#[doc = "1: Rising edge, low to high transition"]
Rising = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port<n>3 Interrupt Polarity"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::Falling,
true => P3::Rising,
}
}
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn is_falling(&self) -> bool {
*self == P3::Falling
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == P3::Rising
}
}
#[doc = "Field `P3` writer - Port<n>3 Interrupt Polarity"]
pub type P3_W<'a, REG> = crate::BitWriter<'a, REG, P3>;
impl<'a, REG> P3_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn falling(self) -> &'a mut crate::W<REG> {
self.variant(P3::Falling)
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn rising(self) -> &'a mut crate::W<REG> {
self.variant(P3::Rising)
}
}
#[doc = "Port<n>4 Interrupt Polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: Falling edge, high to low transition"]
Falling = 0,
#[doc = "1: Rising edge, low to high transition"]
Rising = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port<n>4 Interrupt Polarity"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::Falling,
true => P4::Rising,
}
}
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn is_falling(&self) -> bool {
*self == P4::Falling
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == P4::Rising
}
}
#[doc = "Field `P4` writer - Port<n>4 Interrupt Polarity"]
pub type P4_W<'a, REG> = crate::BitWriter<'a, REG, P4>;
impl<'a, REG> P4_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn falling(self) -> &'a mut crate::W<REG> {
self.variant(P4::Falling)
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn rising(self) -> &'a mut crate::W<REG> {
self.variant(P4::Rising)
}
}
#[doc = "Port<n>5 Interrupt Polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: Falling edge, high to low transition"]
Falling = 0,
#[doc = "1: Rising edge, low to high transition"]
Rising = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port<n>5 Interrupt Polarity"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::Falling,
true => P5::Rising,
}
}
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn is_falling(&self) -> bool {
*self == P5::Falling
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == P5::Rising
}
}
#[doc = "Field `P5` writer - Port<n>5 Interrupt Polarity"]
pub type P5_W<'a, REG> = crate::BitWriter<'a, REG, P5>;
impl<'a, REG> P5_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn falling(self) -> &'a mut crate::W<REG> {
self.variant(P5::Falling)
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn rising(self) -> &'a mut crate::W<REG> {
self.variant(P5::Rising)
}
}
#[doc = "Port<n>6 Interrupt Polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: Falling edge, high to low transition"]
Falling = 0,
#[doc = "1: Rising edge, low to high transition"]
Rising = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port<n>6 Interrupt Polarity"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::Falling,
true => P6::Rising,
}
}
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn is_falling(&self) -> bool {
*self == P6::Falling
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == P6::Rising
}
}
#[doc = "Field `P6` writer - Port<n>6 Interrupt Polarity"]
pub type P6_W<'a, REG> = crate::BitWriter<'a, REG, P6>;
impl<'a, REG> P6_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn falling(self) -> &'a mut crate::W<REG> {
self.variant(P6::Falling)
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn rising(self) -> &'a mut crate::W<REG> {
self.variant(P6::Rising)
}
}
#[doc = "Port<n>7 Interrupt Polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: Falling edge, high to low transition"]
Falling = 0,
#[doc = "1: Rising edge, low to high transition"]
Rising = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port<n>7 Interrupt Polarity"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::Falling,
true => P7::Rising,
}
}
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn is_falling(&self) -> bool {
*self == P7::Falling
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == P7::Rising
}
}
#[doc = "Field `P7` writer - Port<n>7 Interrupt Polarity"]
pub type P7_W<'a, REG> = crate::BitWriter<'a, REG, P7>;
impl<'a, REG> P7_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn falling(self) -> &'a mut crate::W<REG> {
self.variant(P7::Falling)
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn rising(self) -> &'a mut crate::W<REG> {
self.variant(P7::Rising)
}
}
impl R {
#[doc = "Bit 0 - Port<n>0 Interrupt Polarity"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port<n>1 Interrupt Polarity"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port<n>2 Interrupt Polarity"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port<n>3 Interrupt Polarity"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port<n>4 Interrupt Polarity"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port<n>5 Interrupt Polarity"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port<n>6 Interrupt Polarity"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port<n>7 Interrupt Polarity"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INTP")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Port<n>0 Interrupt Polarity"]
#[inline(always)]
pub fn p0(&mut self) -> P0_W<INTPrs> {
P0_W::new(self, 0)
}
#[doc = "Bit 1 - Port<n>1 Interrupt Polarity"]
#[inline(always)]
pub fn p1(&mut self) -> P1_W<INTPrs> {
P1_W::new(self, 1)
}
#[doc = "Bit 2 - Port<n>2 Interrupt Polarity"]
#[inline(always)]
pub fn p2(&mut self) -> P2_W<INTPrs> {
P2_W::new(self, 2)
}
#[doc = "Bit 3 - Port<n>3 Interrupt Polarity"]
#[inline(always)]
pub fn p3(&mut self) -> P3_W<INTPrs> {
P3_W::new(self, 3)
}
#[doc = "Bit 4 - Port<n>4 Interrupt Polarity"]
#[inline(always)]
pub fn p4(&mut self) -> P4_W<INTPrs> {
P4_W::new(self, 4)
}
#[doc = "Bit 5 - Port<n>5 Interrupt Polarity"]
#[inline(always)]
pub fn p5(&mut self) -> P5_W<INTPrs> {
P5_W::new(self, 5)
}
#[doc = "Bit 6 - Port<n>6 Interrupt Polarity"]
#[inline(always)]
pub fn p6(&mut self) -> P6_W<INTPrs> {
P6_W::new(self, 6)
}
#[doc = "Bit 7 - Port<n>7 Interrupt Polarity"]
#[inline(always)]
pub fn p7(&mut self) -> P7_W<INTPrs> {
P7_W::new(self, 7)
}
}
#[doc = "GPIO Port Interrupt Polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`intp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INTPrs;
impl crate::RegisterSpec for INTPrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`intp::R`](R) reader structure"]
impl crate::Readable for INTPrs {}
#[doc = "`write(|w| ..)` method takes [`intp::W`](W) writer structure"]
impl crate::Writable for INTPrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INTP to value 0"]
impl crate::Resettable for INTPrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INTE (rw) register accessor: GPIO Port Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inte`]
module"]
pub type INTE = crate::Reg<inte::INTErs>;
#[doc = "GPIO Port Interrupt Enable"]
pub mod inte {
#[doc = "Register `INTE` reader"]
pub type R = crate::R<INTErs>;
#[doc = "Register `INTE` writer"]
pub type W = crate::W<INTErs>;
#[doc = "Port<n>0 Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: Disable interrupt"]
Disable = 0,
#[doc = "1: Enable interrupt"]
Enable = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port<n>0 Interrupt Enable"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::Disable,
true => P0::Enable,
}
}
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == P0::Disable
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == P0::Enable
}
}
#[doc = "Field `P0` writer - Port<n>0 Interrupt Enable"]
pub type P0_W<'a, REG> = crate::BitWriter<'a, REG, P0>;
impl<'a, REG> P0_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(P0::Disable)
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(P0::Enable)
}
}
#[doc = "Port<n>1 Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: Disable interrupt"]
Disable = 0,
#[doc = "1: Enable interrupt"]
Enable = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port<n>1 Interrupt Enable"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::Disable,
true => P1::Enable,
}
}
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == P1::Disable
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == P1::Enable
}
}
#[doc = "Field `P1` writer - Port<n>1 Interrupt Enable"]
pub type P1_W<'a, REG> = crate::BitWriter<'a, REG, P1>;
impl<'a, REG> P1_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(P1::Disable)
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(P1::Enable)
}
}
#[doc = "Port<n>2 Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: Disable interrupt"]
Disable = 0,
#[doc = "1: Enable interrupt"]
Enable = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port<n>2 Interrupt Enable"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::Disable,
true => P2::Enable,
}
}
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == P2::Disable
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == P2::Enable
}
}
#[doc = "Field `P2` writer - Port<n>2 Interrupt Enable"]
pub type P2_W<'a, REG> = crate::BitWriter<'a, REG, P2>;
impl<'a, REG> P2_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(P2::Disable)
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(P2::Enable)
}
}
#[doc = "Port<n>3 Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: Disable interrupt"]
Disable = 0,
#[doc = "1: Enable interrupt"]
Enable = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port<n>3 Interrupt Enable"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::Disable,
true => P3::Enable,
}
}
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == P3::Disable
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == P3::Enable
}
}
#[doc = "Field `P3` writer - Port<n>3 Interrupt Enable"]
pub type P3_W<'a, REG> = crate::BitWriter<'a, REG, P3>;
impl<'a, REG> P3_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(P3::Disable)
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(P3::Enable)
}
}
#[doc = "Port<n>4 Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: Disable interrupt"]
Disable = 0,
#[doc = "1: Enable interrupt"]
Enable = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port<n>4 Interrupt Enable"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::Disable,
true => P4::Enable,
}
}
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == P4::Disable
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == P4::Enable
}
}
#[doc = "Field `P4` writer - Port<n>4 Interrupt Enable"]
pub type P4_W<'a, REG> = crate::BitWriter<'a, REG, P4>;
impl<'a, REG> P4_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(P4::Disable)
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(P4::Enable)
}
}
#[doc = "Port<n>5 Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: Disable interrupt"]
Disable = 0,
#[doc = "1: Enable interrupt"]
Enable = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port<n>5 Interrupt Enable"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::Disable,
true => P5::Enable,
}
}
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == P5::Disable
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == P5::Enable
}
}
#[doc = "Field `P5` writer - Port<n>5 Interrupt Enable"]
pub type P5_W<'a, REG> = crate::BitWriter<'a, REG, P5>;
impl<'a, REG> P5_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(P5::Disable)
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(P5::Enable)
}
}
#[doc = "Port<n>6 Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: Disable interrupt"]
Disable = 0,
#[doc = "1: Enable interrupt"]
Enable = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port<n>6 Interrupt Enable"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::Disable,
true => P6::Enable,
}
}
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == P6::Disable
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == P6::Enable
}
}
#[doc = "Field `P6` writer - Port<n>6 Interrupt Enable"]
pub type P6_W<'a, REG> = crate::BitWriter<'a, REG, P6>;
impl<'a, REG> P6_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(P6::Disable)
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(P6::Enable)
}
}
#[doc = "Port<n>7 Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: Disable interrupt"]
Disable = 0,
#[doc = "1: Enable interrupt"]
Enable = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port<n>7 Interrupt Enable"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::Disable,
true => P7::Enable,
}
}
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == P7::Disable
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == P7::Enable
}
}
#[doc = "Field `P7` writer - Port<n>7 Interrupt Enable"]
pub type P7_W<'a, REG> = crate::BitWriter<'a, REG, P7>;
impl<'a, REG> P7_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(P7::Disable)
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(P7::Enable)
}
}
impl R {
#[doc = "Bit 0 - Port<n>0 Interrupt Enable"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port<n>1 Interrupt Enable"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port<n>2 Interrupt Enable"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port<n>3 Interrupt Enable"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port<n>4 Interrupt Enable"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port<n>5 Interrupt Enable"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port<n>6 Interrupt Enable"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port<n>7 Interrupt Enable"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INTE")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Port<n>0 Interrupt Enable"]
#[inline(always)]
pub fn p0(&mut self) -> P0_W<INTErs> {
P0_W::new(self, 0)
}
#[doc = "Bit 1 - Port<n>1 Interrupt Enable"]
#[inline(always)]
pub fn p1(&mut self) -> P1_W<INTErs> {
P1_W::new(self, 1)
}
#[doc = "Bit 2 - Port<n>2 Interrupt Enable"]
#[inline(always)]
pub fn p2(&mut self) -> P2_W<INTErs> {
P2_W::new(self, 2)
}
#[doc = "Bit 3 - Port<n>3 Interrupt Enable"]
#[inline(always)]
pub fn p3(&mut self) -> P3_W<INTErs> {
P3_W::new(self, 3)
}
#[doc = "Bit 4 - Port<n>4 Interrupt Enable"]
#[inline(always)]
pub fn p4(&mut self) -> P4_W<INTErs> {
P4_W::new(self, 4)
}
#[doc = "Bit 5 - Port<n>5 Interrupt Enable"]
#[inline(always)]
pub fn p5(&mut self) -> P5_W<INTErs> {
P5_W::new(self, 5)
}
#[doc = "Bit 6 - Port<n>6 Interrupt Enable"]
#[inline(always)]
pub fn p6(&mut self) -> P6_W<INTErs> {
P6_W::new(self, 6)
}
#[doc = "Bit 7 - Port<n>7 Interrupt Enable"]
#[inline(always)]
pub fn p7(&mut self) -> P7_W<INTErs> {
P7_W::new(self, 7)
}
}
#[doc = "GPIO Port Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INTErs;
impl crate::RegisterSpec for INTErs {
type Ux = u32;
}
#[doc = "`read()` method returns [`inte::R`](R) reader structure"]
impl crate::Readable for INTErs {}
#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"]
impl crate::Writable for INTErs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INTE to value 0"]
impl crate::Resettable for INTErs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INTF (rw) register accessor: GPIO Port Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf`]
module"]
pub type INTF = crate::Reg<intf::INTFrs>;
#[doc = "GPIO Port Interrupt Flag"]
pub mod intf {
#[doc = "Register `INTF` reader"]
pub type R = crate::R<INTFrs>;
#[doc = "Register `INTF` writer"]
pub type W = crate::W<INTFrs>;
#[doc = "Port<n>0 Interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: No interrupt pending"]
None = 0,
#[doc = "1: Interrupt pending"]
Interrupt = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port<n>0 Interrupt"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::None,
true => P0::Interrupt,
}
}
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == P0::None
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == P0::Interrupt
}
}
#[doc = "Field `P0` writer - Port<n>0 Interrupt"]
pub type P0_W<'a, REG> = crate::BitWriter<'a, REG, P0>;
impl<'a, REG> P0_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(P0::None)
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(P0::Interrupt)
}
}
#[doc = "Port<n>1 Interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: No interrupt pending"]
None = 0,
#[doc = "1: Interrupt pending"]
Interrupt = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port<n>1 Interrupt"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::None,
true => P1::Interrupt,
}
}
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == P1::None
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == P1::Interrupt
}
}
#[doc = "Field `P1` writer - Port<n>1 Interrupt"]
pub type P1_W<'a, REG> = crate::BitWriter<'a, REG, P1>;
impl<'a, REG> P1_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(P1::None)
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(P1::Interrupt)
}
}
#[doc = "Port<n>2 Interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: No interrupt pending"]
None = 0,
#[doc = "1: Interrupt pending"]
Interrupt = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port<n>2 Interrupt"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::None,
true => P2::Interrupt,
}
}
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == P2::None
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == P2::Interrupt
}
}
#[doc = "Field `P2` writer - Port<n>2 Interrupt"]
pub type P2_W<'a, REG> = crate::BitWriter<'a, REG, P2>;
impl<'a, REG> P2_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(P2::None)
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(P2::Interrupt)
}
}
#[doc = "Port<n>3 Interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: No interrupt pending"]
None = 0,
#[doc = "1: Interrupt pending"]
Interrupt = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port<n>3 Interrupt"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::None,
true => P3::Interrupt,
}
}
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == P3::None
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == P3::Interrupt
}
}
#[doc = "Field `P3` writer - Port<n>3 Interrupt"]
pub type P3_W<'a, REG> = crate::BitWriter<'a, REG, P3>;
impl<'a, REG> P3_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(P3::None)
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(P3::Interrupt)
}
}
#[doc = "Port<n>4 Interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: No interrupt pending"]
None = 0,
#[doc = "1: Interrupt pending"]
Interrupt = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port<n>4 Interrupt"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::None,
true => P4::Interrupt,
}
}
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == P4::None
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == P4::Interrupt
}
}
#[doc = "Field `P4` writer - Port<n>4 Interrupt"]
pub type P4_W<'a, REG> = crate::BitWriter<'a, REG, P4>;
impl<'a, REG> P4_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(P4::None)
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(P4::Interrupt)
}
}
#[doc = "Port<n>5 Interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: No interrupt pending"]
None = 0,
#[doc = "1: Interrupt pending"]
Interrupt = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port<n>5 Interrupt"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::None,
true => P5::Interrupt,
}
}
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == P5::None
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == P5::Interrupt
}
}
#[doc = "Field `P5` writer - Port<n>5 Interrupt"]
pub type P5_W<'a, REG> = crate::BitWriter<'a, REG, P5>;
impl<'a, REG> P5_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(P5::None)
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(P5::Interrupt)
}
}
#[doc = "Port<n>6 Interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: No interrupt pending"]
None = 0,
#[doc = "1: Interrupt pending"]
Interrupt = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port<n>6 Interrupt"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::None,
true => P6::Interrupt,
}
}
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == P6::None
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == P6::Interrupt
}
}
#[doc = "Field `P6` writer - Port<n>6 Interrupt"]
pub type P6_W<'a, REG> = crate::BitWriter<'a, REG, P6>;
impl<'a, REG> P6_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(P6::None)
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(P6::Interrupt)
}
}
#[doc = "Port<n>7 Interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: No interrupt pending"]
None = 0,
#[doc = "1: Interrupt pending"]
Interrupt = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port<n>7 Interrupt"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::None,
true => P7::Interrupt,
}
}
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == P7::None
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == P7::Interrupt
}
}
#[doc = "Field `P7` writer - Port<n>7 Interrupt"]
pub type P7_W<'a, REG> = crate::BitWriter<'a, REG, P7>;
impl<'a, REG> P7_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(P7::None)
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(P7::Interrupt)
}
}
impl R {
#[doc = "Bit 0 - Port<n>0 Interrupt"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port<n>1 Interrupt"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port<n>2 Interrupt"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port<n>3 Interrupt"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port<n>4 Interrupt"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port<n>5 Interrupt"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port<n>6 Interrupt"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port<n>7 Interrupt"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INTF")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Port<n>0 Interrupt"]
#[inline(always)]
pub fn p0(&mut self) -> P0_W<INTFrs> {
P0_W::new(self, 0)
}
#[doc = "Bit 1 - Port<n>1 Interrupt"]
#[inline(always)]
pub fn p1(&mut self) -> P1_W<INTFrs> {
P1_W::new(self, 1)
}
#[doc = "Bit 2 - Port<n>2 Interrupt"]
#[inline(always)]
pub fn p2(&mut self) -> P2_W<INTFrs> {
P2_W::new(self, 2)
}
#[doc = "Bit 3 - Port<n>3 Interrupt"]
#[inline(always)]
pub fn p3(&mut self) -> P3_W<INTFrs> {
P3_W::new(self, 3)
}
#[doc = "Bit 4 - Port<n>4 Interrupt"]
#[inline(always)]
pub fn p4(&mut self) -> P4_W<INTFrs> {
P4_W::new(self, 4)
}
#[doc = "Bit 5 - Port<n>5 Interrupt"]
#[inline(always)]
pub fn p5(&mut self) -> P5_W<INTFrs> {
P5_W::new(self, 5)
}
#[doc = "Bit 6 - Port<n>6 Interrupt"]
#[inline(always)]
pub fn p6(&mut self) -> P6_W<INTFrs> {
P6_W::new(self, 6)
}
#[doc = "Bit 7 - Port<n>7 Interrupt"]
#[inline(always)]
pub fn p7(&mut self) -> P7_W<INTFrs> {
P7_W::new(self, 7)
}
}
#[doc = "GPIO Port Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INTFrs;
impl crate::RegisterSpec for INTFrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`intf::R`](R) reader structure"]
impl crate::Readable for INTFrs {}
#[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"]
impl crate::Writable for INTFrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INTF to value 0"]
impl crate::Resettable for INTFrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INTM (rw) register accessor: GPIO Port Interrupt Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`intm::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intm::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intm`]
module"]
pub type INTM = crate::Reg<intm::INTMrs>;
#[doc = "GPIO Port Interrupt Mask"]
pub mod intm {
#[doc = "Register `INTM` reader"]
pub type R = crate::R<INTMrs>;
#[doc = "Register `INTM` writer"]
pub type W = crate::W<INTMrs>;
#[doc = "Port<n>0 Interrupt Mask\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: Disable interrupt mask"]
Disabled = 0,
#[doc = "1: Enable interrupt mask"]
Enabled = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port<n>0 Interrupt Mask"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::Disabled,
true => P0::Enabled,
}
}
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P0::Disabled
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P0::Enabled
}
}
#[doc = "Field `P0` writer - Port<n>0 Interrupt Mask"]
pub type P0_W<'a, REG> = crate::BitWriter<'a, REG, P0>;
impl<'a, REG> P0_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P0::Disabled)
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P0::Enabled)
}
}
#[doc = "Port<n>1 Interrupt Mask\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: Disable interrupt mask"]
Disabled = 0,
#[doc = "1: Enable interrupt mask"]
Enabled = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port<n>1 Interrupt Mask"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::Disabled,
true => P1::Enabled,
}
}
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P1::Disabled
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P1::Enabled
}
}
#[doc = "Field `P1` writer - Port<n>1 Interrupt Mask"]
pub type P1_W<'a, REG> = crate::BitWriter<'a, REG, P1>;
impl<'a, REG> P1_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P1::Disabled)
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P1::Enabled)
}
}
#[doc = "Port<n>2 Interrupt Mask\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: Disable interrupt mask"]
Disabled = 0,
#[doc = "1: Enable interrupt mask"]
Enabled = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port<n>2 Interrupt Mask"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::Disabled,
true => P2::Enabled,
}
}
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P2::Disabled
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P2::Enabled
}
}
#[doc = "Field `P2` writer - Port<n>2 Interrupt Mask"]
pub type P2_W<'a, REG> = crate::BitWriter<'a, REG, P2>;
impl<'a, REG> P2_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P2::Disabled)
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P2::Enabled)
}
}
#[doc = "Port<n>3 Interrupt Mask\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: Disable interrupt mask"]
Disabled = 0,
#[doc = "1: Enable interrupt mask"]
Enabled = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port<n>3 Interrupt Mask"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::Disabled,
true => P3::Enabled,
}
}
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P3::Disabled
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P3::Enabled
}
}
#[doc = "Field `P3` writer - Port<n>3 Interrupt Mask"]
pub type P3_W<'a, REG> = crate::BitWriter<'a, REG, P3>;
impl<'a, REG> P3_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P3::Disabled)
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P3::Enabled)
}
}
#[doc = "Port<n>4 Interrupt Mask\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: Disable interrupt mask"]
Disabled = 0,
#[doc = "1: Enable interrupt mask"]
Enabled = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port<n>4 Interrupt Mask"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::Disabled,
true => P4::Enabled,
}
}
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P4::Disabled
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P4::Enabled
}
}
#[doc = "Field `P4` writer - Port<n>4 Interrupt Mask"]
pub type P4_W<'a, REG> = crate::BitWriter<'a, REG, P4>;
impl<'a, REG> P4_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P4::Disabled)
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P4::Enabled)
}
}
#[doc = "Port<n>5 Interrupt Mask\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: Disable interrupt mask"]
Disabled = 0,
#[doc = "1: Enable interrupt mask"]
Enabled = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port<n>5 Interrupt Mask"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::Disabled,
true => P5::Enabled,
}
}
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P5::Disabled
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P5::Enabled
}
}
#[doc = "Field `P5` writer - Port<n>5 Interrupt Mask"]
pub type P5_W<'a, REG> = crate::BitWriter<'a, REG, P5>;
impl<'a, REG> P5_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P5::Disabled)
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P5::Enabled)
}
}
#[doc = "Port<n>6 Interrupt Mask\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: Disable interrupt mask"]
Disabled = 0,
#[doc = "1: Enable interrupt mask"]
Enabled = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port<n>6 Interrupt Mask"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::Disabled,
true => P6::Enabled,
}
}
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P6::Disabled
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P6::Enabled
}
}
#[doc = "Field `P6` writer - Port<n>6 Interrupt Mask"]
pub type P6_W<'a, REG> = crate::BitWriter<'a, REG, P6>;
impl<'a, REG> P6_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P6::Disabled)
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P6::Enabled)
}
}
#[doc = "Port<n>7 Interrupt Mask\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: Disable interrupt mask"]
Disabled = 0,
#[doc = "1: Enable interrupt mask"]
Enabled = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port<n>7 Interrupt Mask"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::Disabled,
true => P7::Enabled,
}
}
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P7::Disabled
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P7::Enabled
}
}
#[doc = "Field `P7` writer - Port<n>7 Interrupt Mask"]
pub type P7_W<'a, REG> = crate::BitWriter<'a, REG, P7>;
impl<'a, REG> P7_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P7::Disabled)
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P7::Enabled)
}
}
impl R {
#[doc = "Bit 0 - Port<n>0 Interrupt Mask"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port<n>1 Interrupt Mask"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port<n>2 Interrupt Mask"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port<n>3 Interrupt Mask"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port<n>4 Interrupt Mask"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port<n>5 Interrupt Mask"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port<n>6 Interrupt Mask"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port<n>7 Interrupt Mask"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INTM")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Port<n>0 Interrupt Mask"]
#[inline(always)]
pub fn p0(&mut self) -> P0_W<INTMrs> {
P0_W::new(self, 0)
}
#[doc = "Bit 1 - Port<n>1 Interrupt Mask"]
#[inline(always)]
pub fn p1(&mut self) -> P1_W<INTMrs> {
P1_W::new(self, 1)
}
#[doc = "Bit 2 - Port<n>2 Interrupt Mask"]
#[inline(always)]
pub fn p2(&mut self) -> P2_W<INTMrs> {
P2_W::new(self, 2)
}
#[doc = "Bit 3 - Port<n>3 Interrupt Mask"]
#[inline(always)]
pub fn p3(&mut self) -> P3_W<INTMrs> {
P3_W::new(self, 3)
}
#[doc = "Bit 4 - Port<n>4 Interrupt Mask"]
#[inline(always)]
pub fn p4(&mut self) -> P4_W<INTMrs> {
P4_W::new(self, 4)
}
#[doc = "Bit 5 - Port<n>5 Interrupt Mask"]
#[inline(always)]
pub fn p5(&mut self) -> P5_W<INTMrs> {
P5_W::new(self, 5)
}
#[doc = "Bit 6 - Port<n>6 Interrupt Mask"]
#[inline(always)]
pub fn p6(&mut self) -> P6_W<INTMrs> {
P6_W::new(self, 6)
}
#[doc = "Bit 7 - Port<n>7 Interrupt Mask"]
#[inline(always)]
pub fn p7(&mut self) -> P7_W<INTMrs> {
P7_W::new(self, 7)
}
}
#[doc = "GPIO Port Interrupt Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`intm::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intm::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INTMrs;
impl crate::RegisterSpec for INTMrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`intm::R`](R) reader structure"]
impl crate::Readable for INTMrs {}
#[doc = "`write(|w| ..)` method takes [`intm::W`](W) writer structure"]
impl crate::Writable for INTMrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INTM to value 0"]
impl crate::Resettable for INTMrs {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "General-Purpose Input-Output Port B"]
pub struct GPIOB {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOB {}
impl GPIOB {
#[doc = r"Pointer to the register block"]
pub const PTR: *const gpioa::RegisterBlock = 0x4007_0040 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const gpioa::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for GPIOB {
type Target = gpioa::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for GPIOB {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOB").finish()
}
}
#[doc = "General-Purpose Input-Output Port B"]
pub use self::gpioa as gpiob;
#[doc = "General-Purpose Input-Output Port C"]
pub struct GPIOC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOC {}
impl GPIOC {
#[doc = r"Pointer to the register block"]
pub const PTR: *const gpioc::RegisterBlock = 0x4008_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const gpioc::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for GPIOC {
type Target = gpioc::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for GPIOC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOC").finish()
}
}
#[doc = "General-Purpose Input-Output Port C"]
pub mod gpioc {
#[repr(C)]
#[derive(Debug)]
#[doc = "Register block"]
pub struct RegisterBlock {
out: OUT,
outen: OUTEN,
_reserved2: [u8; 0x0c],
in_: IN,
ine: INE,
_reserved4: [u8; 0x04],
intp: INTP,
inte: INTE,
intf: INTF,
intm: INTM,
}
impl RegisterBlock {
#[doc = "0x00 - GPIO Port Output"]
#[inline(always)]
pub const fn out(&self) -> &OUT {
&self.out
}
#[doc = "0x04 - GPIO Port Output Enable"]
#[inline(always)]
pub const fn outen(&self) -> &OUTEN {
&self.outen
}
#[doc = "0x14 - GPIO Port Input"]
#[inline(always)]
pub const fn in_(&self) -> &IN {
&self.in_
}
#[doc = "0x18 - GPIO Port Input Enable"]
#[inline(always)]
pub const fn ine(&self) -> &INE {
&self.ine
}
#[doc = "0x20 - GPIO Port Interrupt Polarity"]
#[inline(always)]
pub const fn intp(&self) -> &INTP {
&self.intp
}
#[doc = "0x24 - GPIO Port Interrupt Enable"]
#[inline(always)]
pub const fn inte(&self) -> &INTE {
&self.inte
}
#[doc = "0x28 - GPIO Port Interrupt Flag"]
#[inline(always)]
pub const fn intf(&self) -> &INTF {
&self.intf
}
#[doc = "0x2c - GPIO Port Interrupt Mask"]
#[inline(always)]
pub const fn intm(&self) -> &INTM {
&self.intm
}
}
#[doc = "OUT (rw) register accessor: GPIO Port Output\n\nYou can [`read`](crate::Reg::read) this register and get [`out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out`]
module"]
pub type OUT = crate::Reg<out::OUTrs>;
#[doc = "GPIO Port Output"]
pub mod out {
#[doc = "Register `OUT` reader"]
pub type R = crate::R<OUTrs>;
#[doc = "Register `OUT` writer"]
pub type W = crate::W<OUTrs>;
#[doc = "Port output 0\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: Set output low if GPIOn->OUTEN.P0 = 1"]
Low = 0,
#[doc = "1: Set output high if GPIOn->OUTEN.P0 = 1"]
High = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port output 0"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::Low,
true => P0::High,
}
}
#[doc = "Set output low if GPIOn->OUTEN.P0 = 1"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P0::Low
}
#[doc = "Set output high if GPIOn->OUTEN.P0 = 1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P0::High
}
}
#[doc = "Field `P0` writer - Port output 0"]
pub type P0_W<'a, REG> = crate::BitWriter<'a, REG, P0>;
impl<'a, REG> P0_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Set output low if GPIOn->OUTEN.P0 = 1"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P0::Low)
}
#[doc = "Set output high if GPIOn->OUTEN.P0 = 1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P0::High)
}
}
#[doc = "Port output 1\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: Set output low if GPIOn->OUTEN.P1 = 1"]
Low = 0,
#[doc = "1: Set output high if GPIOn->OUTEN.P1 = 1"]
High = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port output 1"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::Low,
true => P1::High,
}
}
#[doc = "Set output low if GPIOn->OUTEN.P1 = 1"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P1::Low
}
#[doc = "Set output high if GPIOn->OUTEN.P1 = 1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P1::High
}
}
#[doc = "Field `P1` writer - Port output 1"]
pub type P1_W<'a, REG> = crate::BitWriter<'a, REG, P1>;
impl<'a, REG> P1_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Set output low if GPIOn->OUTEN.P1 = 1"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P1::Low)
}
#[doc = "Set output high if GPIOn->OUTEN.P1 = 1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P1::High)
}
}
#[doc = "Port output 2\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: Set output low if GPIOn->OUTEN.P2 = 1"]
Low = 0,
#[doc = "1: Set output high if GPIOn->OUTEN.P2 = 1"]
High = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port output 2"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::Low,
true => P2::High,
}
}
#[doc = "Set output low if GPIOn->OUTEN.P2 = 1"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P2::Low
}
#[doc = "Set output high if GPIOn->OUTEN.P2 = 1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P2::High
}
}
#[doc = "Field `P2` writer - Port output 2"]
pub type P2_W<'a, REG> = crate::BitWriter<'a, REG, P2>;
impl<'a, REG> P2_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Set output low if GPIOn->OUTEN.P2 = 1"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P2::Low)
}
#[doc = "Set output high if GPIOn->OUTEN.P2 = 1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P2::High)
}
}
#[doc = "Port output 3\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: Set output low if GPIOn->OUTEN.P3 = 1"]
Low = 0,
#[doc = "1: Set output high if GPIOn->OUTEN.P3 = 1"]
High = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port output 3"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::Low,
true => P3::High,
}
}
#[doc = "Set output low if GPIOn->OUTEN.P3 = 1"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P3::Low
}
#[doc = "Set output high if GPIOn->OUTEN.P3 = 1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P3::High
}
}
#[doc = "Field `P3` writer - Port output 3"]
pub type P3_W<'a, REG> = crate::BitWriter<'a, REG, P3>;
impl<'a, REG> P3_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Set output low if GPIOn->OUTEN.P3 = 1"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P3::Low)
}
#[doc = "Set output high if GPIOn->OUTEN.P3 = 1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P3::High)
}
}
#[doc = "Port output 4\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: Set output low if GPIOn->OUTEN.P4 = 1"]
Low = 0,
#[doc = "1: Set output high if GPIOn->OUTEN.P4 = 1"]
High = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port output 4"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::Low,
true => P4::High,
}
}
#[doc = "Set output low if GPIOn->OUTEN.P4 = 1"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P4::Low
}
#[doc = "Set output high if GPIOn->OUTEN.P4 = 1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P4::High
}
}
#[doc = "Field `P4` writer - Port output 4"]
pub type P4_W<'a, REG> = crate::BitWriter<'a, REG, P4>;
impl<'a, REG> P4_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Set output low if GPIOn->OUTEN.P4 = 1"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P4::Low)
}
#[doc = "Set output high if GPIOn->OUTEN.P4 = 1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P4::High)
}
}
#[doc = "Port output 5\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: Set output low if GPIOn->OUTEN.P5 = 1"]
Low = 0,
#[doc = "1: Set output high if GPIOn->OUTEN.P5 = 1"]
High = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port output 5"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::Low,
true => P5::High,
}
}
#[doc = "Set output low if GPIOn->OUTEN.P5 = 1"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P5::Low
}
#[doc = "Set output high if GPIOn->OUTEN.P5 = 1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P5::High
}
}
#[doc = "Field `P5` writer - Port output 5"]
pub type P5_W<'a, REG> = crate::BitWriter<'a, REG, P5>;
impl<'a, REG> P5_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Set output low if GPIOn->OUTEN.P5 = 1"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P5::Low)
}
#[doc = "Set output high if GPIOn->OUTEN.P5 = 1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P5::High)
}
}
#[doc = "Port output 6\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: Set output low if GPIOn->OUTEN.P6 = 1"]
Low = 0,
#[doc = "1: Set output high if GPIOn->OUTEN.P6 = 1"]
High = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port output 6"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::Low,
true => P6::High,
}
}
#[doc = "Set output low if GPIOn->OUTEN.P6 = 1"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P6::Low
}
#[doc = "Set output high if GPIOn->OUTEN.P6 = 1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P6::High
}
}
#[doc = "Field `P6` writer - Port output 6"]
pub type P6_W<'a, REG> = crate::BitWriter<'a, REG, P6>;
impl<'a, REG> P6_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Set output low if GPIOn->OUTEN.P6 = 1"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P6::Low)
}
#[doc = "Set output high if GPIOn->OUTEN.P6 = 1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P6::High)
}
}
#[doc = "Port output 7\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: Set output low if GPIOn->OUTEN.P7 = 1"]
Low = 0,
#[doc = "1: Set output high if GPIOn->OUTEN.P7 = 1"]
High = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port output 7"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::Low,
true => P7::High,
}
}
#[doc = "Set output low if GPIOn->OUTEN.P7 = 1"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P7::Low
}
#[doc = "Set output high if GPIOn->OUTEN.P7 = 1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P7::High
}
}
#[doc = "Field `P7` writer - Port output 7"]
pub type P7_W<'a, REG> = crate::BitWriter<'a, REG, P7>;
impl<'a, REG> P7_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Set output low if GPIOn->OUTEN.P7 = 1"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P7::Low)
}
#[doc = "Set output high if GPIOn->OUTEN.P7 = 1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P7::High)
}
}
impl R {
#[doc = "Bit 0 - Port output 0"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port output 1"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port output 2"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port output 3"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port output 4"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port output 5"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port output 6"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port output 7"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OUT")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Port output 0"]
#[inline(always)]
pub fn p0(&mut self) -> P0_W<OUTrs> {
P0_W::new(self, 0)
}
#[doc = "Bit 1 - Port output 1"]
#[inline(always)]
pub fn p1(&mut self) -> P1_W<OUTrs> {
P1_W::new(self, 1)
}
#[doc = "Bit 2 - Port output 2"]
#[inline(always)]
pub fn p2(&mut self) -> P2_W<OUTrs> {
P2_W::new(self, 2)
}
#[doc = "Bit 3 - Port output 3"]
#[inline(always)]
pub fn p3(&mut self) -> P3_W<OUTrs> {
P3_W::new(self, 3)
}
#[doc = "Bit 4 - Port output 4"]
#[inline(always)]
pub fn p4(&mut self) -> P4_W<OUTrs> {
P4_W::new(self, 4)
}
#[doc = "Bit 5 - Port output 5"]
#[inline(always)]
pub fn p5(&mut self) -> P5_W<OUTrs> {
P5_W::new(self, 5)
}
#[doc = "Bit 6 - Port output 6"]
#[inline(always)]
pub fn p6(&mut self) -> P6_W<OUTrs> {
P6_W::new(self, 6)
}
#[doc = "Bit 7 - Port output 7"]
#[inline(always)]
pub fn p7(&mut self) -> P7_W<OUTrs> {
P7_W::new(self, 7)
}
}
#[doc = "GPIO Port Output\n\nYou can [`read`](crate::Reg::read) this register and get [`out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OUTrs;
impl crate::RegisterSpec for OUTrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`out::R`](R) reader structure"]
impl crate::Readable for OUTrs {}
#[doc = "`write(|w| ..)` method takes [`out::W`](W) writer structure"]
impl crate::Writable for OUTrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets OUT to value 0"]
impl crate::Resettable for OUTrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "OUTEN (rw) register accessor: GPIO Port Output Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`outen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`outen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outen`]
module"]
pub type OUTEN = crate::Reg<outen::OUTENrs>;
#[doc = "GPIO Port Output Enable"]
pub mod outen {
#[doc = "Register `OUTEN` reader"]
pub type R = crate::R<OUTENrs>;
#[doc = "Register `OUTEN` writer"]
pub type W = crate::W<OUTENrs>;
#[doc = "Port output enable 0\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: Output disabled, high-impedance state"]
Low = 0,
#[doc = "1: Output state set by GPIOn->OUT.P0"]
High = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port output enable 0"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::Low,
true => P0::High,
}
}
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P0::Low
}
#[doc = "Output state set by GPIOn->OUT.P0"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P0::High
}
}
#[doc = "Field `P0` writer - Port output enable 0"]
pub type P0_W<'a, REG> = crate::BitWriter<'a, REG, P0>;
impl<'a, REG> P0_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P0::Low)
}
#[doc = "Output state set by GPIOn->OUT.P0"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P0::High)
}
}
#[doc = "Port output enable 1\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: Output disabled, high-impedance state"]
Low = 0,
#[doc = "1: Output state set by GPIOn->OUT.P1"]
High = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port output enable 1"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::Low,
true => P1::High,
}
}
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P1::Low
}
#[doc = "Output state set by GPIOn->OUT.P1"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P1::High
}
}
#[doc = "Field `P1` writer - Port output enable 1"]
pub type P1_W<'a, REG> = crate::BitWriter<'a, REG, P1>;
impl<'a, REG> P1_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P1::Low)
}
#[doc = "Output state set by GPIOn->OUT.P1"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P1::High)
}
}
#[doc = "Port output enable 2\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: Output disabled, high-impedance state"]
Low = 0,
#[doc = "1: Output state set by GPIOn->OUT.P2"]
High = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port output enable 2"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::Low,
true => P2::High,
}
}
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P2::Low
}
#[doc = "Output state set by GPIOn->OUT.P2"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P2::High
}
}
#[doc = "Field `P2` writer - Port output enable 2"]
pub type P2_W<'a, REG> = crate::BitWriter<'a, REG, P2>;
impl<'a, REG> P2_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P2::Low)
}
#[doc = "Output state set by GPIOn->OUT.P2"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P2::High)
}
}
#[doc = "Port output enable 3\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: Output disabled, high-impedance state"]
Low = 0,
#[doc = "1: Output state set by GPIOn->OUT.P3"]
High = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port output enable 3"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::Low,
true => P3::High,
}
}
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P3::Low
}
#[doc = "Output state set by GPIOn->OUT.P3"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P3::High
}
}
#[doc = "Field `P3` writer - Port output enable 3"]
pub type P3_W<'a, REG> = crate::BitWriter<'a, REG, P3>;
impl<'a, REG> P3_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P3::Low)
}
#[doc = "Output state set by GPIOn->OUT.P3"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P3::High)
}
}
#[doc = "Port output enable 4\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: Output disabled, high-impedance state"]
Low = 0,
#[doc = "1: Output state set by GPIOn->OUT.P4"]
High = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port output enable 4"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::Low,
true => P4::High,
}
}
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P4::Low
}
#[doc = "Output state set by GPIOn->OUT.P4"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P4::High
}
}
#[doc = "Field `P4` writer - Port output enable 4"]
pub type P4_W<'a, REG> = crate::BitWriter<'a, REG, P4>;
impl<'a, REG> P4_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P4::Low)
}
#[doc = "Output state set by GPIOn->OUT.P4"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P4::High)
}
}
#[doc = "Port output enable 5\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: Output disabled, high-impedance state"]
Low = 0,
#[doc = "1: Output state set by GPIOn->OUT.P5"]
High = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port output enable 5"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::Low,
true => P5::High,
}
}
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P5::Low
}
#[doc = "Output state set by GPIOn->OUT.P5"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P5::High
}
}
#[doc = "Field `P5` writer - Port output enable 5"]
pub type P5_W<'a, REG> = crate::BitWriter<'a, REG, P5>;
impl<'a, REG> P5_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P5::Low)
}
#[doc = "Output state set by GPIOn->OUT.P5"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P5::High)
}
}
#[doc = "Port output enable 6\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: Output disabled, high-impedance state"]
Low = 0,
#[doc = "1: Output state set by GPIOn->OUT.P6"]
High = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port output enable 6"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::Low,
true => P6::High,
}
}
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P6::Low
}
#[doc = "Output state set by GPIOn->OUT.P6"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P6::High
}
}
#[doc = "Field `P6` writer - Port output enable 6"]
pub type P6_W<'a, REG> = crate::BitWriter<'a, REG, P6>;
impl<'a, REG> P6_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P6::Low)
}
#[doc = "Output state set by GPIOn->OUT.P6"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P6::High)
}
}
#[doc = "Port output enable 7\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: Output disabled, high-impedance state"]
Low = 0,
#[doc = "1: Output state set by GPIOn->OUT.P7"]
High = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port output enable 7"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::Low,
true => P7::High,
}
}
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P7::Low
}
#[doc = "Output state set by GPIOn->OUT.P7"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P7::High
}
}
#[doc = "Field `P7` writer - Port output enable 7"]
pub type P7_W<'a, REG> = crate::BitWriter<'a, REG, P7>;
impl<'a, REG> P7_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Output disabled, high-impedance state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(P7::Low)
}
#[doc = "Output state set by GPIOn->OUT.P7"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P7::High)
}
}
impl R {
#[doc = "Bit 0 - Port output enable 0"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port output enable 1"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port output enable 2"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port output enable 3"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port output enable 4"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port output enable 5"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port output enable 6"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port output enable 7"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("OUTEN")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Port output enable 0"]
#[inline(always)]
pub fn p0(&mut self) -> P0_W<OUTENrs> {
P0_W::new(self, 0)
}
#[doc = "Bit 1 - Port output enable 1"]
#[inline(always)]
pub fn p1(&mut self) -> P1_W<OUTENrs> {
P1_W::new(self, 1)
}
#[doc = "Bit 2 - Port output enable 2"]
#[inline(always)]
pub fn p2(&mut self) -> P2_W<OUTENrs> {
P2_W::new(self, 2)
}
#[doc = "Bit 3 - Port output enable 3"]
#[inline(always)]
pub fn p3(&mut self) -> P3_W<OUTENrs> {
P3_W::new(self, 3)
}
#[doc = "Bit 4 - Port output enable 4"]
#[inline(always)]
pub fn p4(&mut self) -> P4_W<OUTENrs> {
P4_W::new(self, 4)
}
#[doc = "Bit 5 - Port output enable 5"]
#[inline(always)]
pub fn p5(&mut self) -> P5_W<OUTENrs> {
P5_W::new(self, 5)
}
#[doc = "Bit 6 - Port output enable 6"]
#[inline(always)]
pub fn p6(&mut self) -> P6_W<OUTENrs> {
P6_W::new(self, 6)
}
#[doc = "Bit 7 - Port output enable 7"]
#[inline(always)]
pub fn p7(&mut self) -> P7_W<OUTENrs> {
P7_W::new(self, 7)
}
}
#[doc = "GPIO Port Output Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`outen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`outen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OUTENrs;
impl crate::RegisterSpec for OUTENrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`outen::R`](R) reader structure"]
impl crate::Readable for OUTENrs {}
#[doc = "`write(|w| ..)` method takes [`outen::W`](W) writer structure"]
impl crate::Writable for OUTENrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets OUTEN to value 0"]
impl crate::Resettable for OUTENrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "IN (r) register accessor: GPIO Port Input\n\nYou can [`read`](crate::Reg::read) this register and get [`in_::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_`]
module"]
pub type IN = crate::Reg<in_::INrs>;
#[doc = "GPIO Port Input"]
pub mod in_ {
#[doc = "Register `IN` reader"]
pub type R = crate::R<INrs>;
#[doc = "Port<n>0 input state\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: Logic low"]
Low = 0,
#[doc = "1: Logic high"]
High = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port<n>0 input state"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::Low,
true => P0::High,
}
}
#[doc = "Logic low"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P0::Low
}
#[doc = "Logic high"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P0::High
}
}
#[doc = "Port<n>1 input state\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: Logic low"]
Low = 0,
#[doc = "1: Logic high"]
High = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port<n>1 input state"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::Low,
true => P1::High,
}
}
#[doc = "Logic low"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P1::Low
}
#[doc = "Logic high"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P1::High
}
}
#[doc = "Port<n>2 input state\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: Logic low"]
Low = 0,
#[doc = "1: Logic high"]
High = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port<n>2 input state"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::Low,
true => P2::High,
}
}
#[doc = "Logic low"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P2::Low
}
#[doc = "Logic high"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P2::High
}
}
#[doc = "Port<n>3 input state\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: Logic low"]
Low = 0,
#[doc = "1: Logic high"]
High = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port<n>3 input state"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::Low,
true => P3::High,
}
}
#[doc = "Logic low"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P3::Low
}
#[doc = "Logic high"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P3::High
}
}
#[doc = "Port<n>4 input state\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: Logic low"]
Low = 0,
#[doc = "1: Logic high"]
High = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port<n>4 input state"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::Low,
true => P4::High,
}
}
#[doc = "Logic low"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P4::Low
}
#[doc = "Logic high"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P4::High
}
}
#[doc = "Port<n>5 input state\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: Logic low"]
Low = 0,
#[doc = "1: Logic high"]
High = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port<n>5 input state"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::Low,
true => P5::High,
}
}
#[doc = "Logic low"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P5::Low
}
#[doc = "Logic high"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P5::High
}
}
#[doc = "Port<n>6 input state\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: Logic low"]
Low = 0,
#[doc = "1: Logic high"]
High = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port<n>6 input state"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::Low,
true => P6::High,
}
}
#[doc = "Logic low"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P6::Low
}
#[doc = "Logic high"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P6::High
}
}
#[doc = "Port<n>7 input state\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: Logic low"]
Low = 0,
#[doc = "1: Logic high"]
High = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port<n>7 input state"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::Low,
true => P7::High,
}
}
#[doc = "Logic low"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == P7::Low
}
#[doc = "Logic high"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P7::High
}
}
impl R {
#[doc = "Bit 0 - Port<n>0 input state"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port<n>1 input state"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port<n>2 input state"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port<n>3 input state"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port<n>4 input state"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port<n>5 input state"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port<n>6 input state"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port<n>7 input state"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("IN")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
#[doc = "GPIO Port Input\n\nYou can [`read`](crate::Reg::read) this register and get [`in_::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INrs;
impl crate::RegisterSpec for INrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`in_::R`](R) reader structure"]
impl crate::Readable for INrs {}
#[doc = "`reset()` method sets IN to value 0"]
impl crate::Resettable for INrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INE (rw) register accessor: GPIO Port Input Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ine::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ine::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ine`]
module"]
pub type INE = crate::Reg<ine::INErs>;
#[doc = "GPIO Port Input Enable"]
pub mod ine {
#[doc = "Register `INE` reader"]
pub type R = crate::R<INErs>;
#[doc = "Register `INE` writer"]
pub type W = crate::W<INErs>;
#[doc = "Port input enable 0\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: Input disabled"]
Disabled = 0,
#[doc = "1: Input enabled, for I/O operation"]
Enabled = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port input enable 0"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::Disabled,
true => P0::Enabled,
}
}
#[doc = "Input disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P0::Disabled
}
#[doc = "Input enabled, for I/O operation"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P0::Enabled
}
}
#[doc = "Field `P0` writer - Port input enable 0"]
pub type P0_W<'a, REG> = crate::BitWriter<'a, REG, P0>;
impl<'a, REG> P0_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Input disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P0::Disabled)
}
#[doc = "Input enabled, for I/O operation"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P0::Enabled)
}
}
#[doc = "Port input enable 1\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: Input disabled"]
Disabled = 0,
#[doc = "1: Input enabled, for I/O operation"]
Enabled = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port input enable 1"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::Disabled,
true => P1::Enabled,
}
}
#[doc = "Input disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P1::Disabled
}
#[doc = "Input enabled, for I/O operation"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P1::Enabled
}
}
#[doc = "Field `P1` writer - Port input enable 1"]
pub type P1_W<'a, REG> = crate::BitWriter<'a, REG, P1>;
impl<'a, REG> P1_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Input disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P1::Disabled)
}
#[doc = "Input enabled, for I/O operation"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P1::Enabled)
}
}
#[doc = "Port input enable 2\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: Input disabled"]
Disabled = 0,
#[doc = "1: Input enabled, for I/O operation"]
High = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port input enable 2"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::Disabled,
true => P2::High,
}
}
#[doc = "Input disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P2::Disabled
}
#[doc = "Input enabled, for I/O operation"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == P2::High
}
}
#[doc = "Field `P2` writer - Port input enable 2"]
pub type P2_W<'a, REG> = crate::BitWriter<'a, REG, P2>;
impl<'a, REG> P2_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Input disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P2::Disabled)
}
#[doc = "Input enabled, for I/O operation"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(P2::High)
}
}
#[doc = "Port input enable 3\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: Input disabled"]
Disabled = 0,
#[doc = "1: Input enabled, for I/O operation"]
Enabled = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port input enable 3"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::Disabled,
true => P3::Enabled,
}
}
#[doc = "Input disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P3::Disabled
}
#[doc = "Input enabled, for I/O operation"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P3::Enabled
}
}
#[doc = "Field `P3` writer - Port input enable 3"]
pub type P3_W<'a, REG> = crate::BitWriter<'a, REG, P3>;
impl<'a, REG> P3_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Input disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P3::Disabled)
}
#[doc = "Input enabled, for I/O operation"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P3::Enabled)
}
}
#[doc = "Port input enable 4\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: Input disabled"]
Disabled = 0,
#[doc = "1: Input enabled, for I/O operation"]
Enabled = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port input enable 4"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::Disabled,
true => P4::Enabled,
}
}
#[doc = "Input disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P4::Disabled
}
#[doc = "Input enabled, for I/O operation"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P4::Enabled
}
}
#[doc = "Field `P4` writer - Port input enable 4"]
pub type P4_W<'a, REG> = crate::BitWriter<'a, REG, P4>;
impl<'a, REG> P4_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Input disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P4::Disabled)
}
#[doc = "Input enabled, for I/O operation"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P4::Enabled)
}
}
#[doc = "Port input enable 5\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: Input disabled"]
Disabled = 0,
#[doc = "1: Input enabled, for I/O operation"]
Enabled = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port input enable 5"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::Disabled,
true => P5::Enabled,
}
}
#[doc = "Input disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P5::Disabled
}
#[doc = "Input enabled, for I/O operation"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P5::Enabled
}
}
#[doc = "Field `P5` writer - Port input enable 5"]
pub type P5_W<'a, REG> = crate::BitWriter<'a, REG, P5>;
impl<'a, REG> P5_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Input disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P5::Disabled)
}
#[doc = "Input enabled, for I/O operation"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P5::Enabled)
}
}
#[doc = "Port input enable 6\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: Input disabled"]
Disabled = 0,
#[doc = "1: Input enabled, for I/O operation"]
Enabled = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port input enable 6"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::Disabled,
true => P6::Enabled,
}
}
#[doc = "Input disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P6::Disabled
}
#[doc = "Input enabled, for I/O operation"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P6::Enabled
}
}
#[doc = "Field `P6` writer - Port input enable 6"]
pub type P6_W<'a, REG> = crate::BitWriter<'a, REG, P6>;
impl<'a, REG> P6_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Input disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P6::Disabled)
}
#[doc = "Input enabled, for I/O operation"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P6::Enabled)
}
}
#[doc = "Port input enable 7\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: Input disabled"]
Disabled = 0,
#[doc = "1: Input enabled, for I/O operation"]
Enabled = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port input enable 7"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::Disabled,
true => P7::Enabled,
}
}
#[doc = "Input disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P7::Disabled
}
#[doc = "Input enabled, for I/O operation"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P7::Enabled
}
}
#[doc = "Field `P7` writer - Port input enable 7"]
pub type P7_W<'a, REG> = crate::BitWriter<'a, REG, P7>;
impl<'a, REG> P7_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Input disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P7::Disabled)
}
#[doc = "Input enabled, for I/O operation"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P7::Enabled)
}
}
impl R {
#[doc = "Bit 0 - Port input enable 0"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port input enable 1"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port input enable 2"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port input enable 3"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port input enable 4"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port input enable 5"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port input enable 6"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port input enable 7"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INE")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Port input enable 0"]
#[inline(always)]
pub fn p0(&mut self) -> P0_W<INErs> {
P0_W::new(self, 0)
}
#[doc = "Bit 1 - Port input enable 1"]
#[inline(always)]
pub fn p1(&mut self) -> P1_W<INErs> {
P1_W::new(self, 1)
}
#[doc = "Bit 2 - Port input enable 2"]
#[inline(always)]
pub fn p2(&mut self) -> P2_W<INErs> {
P2_W::new(self, 2)
}
#[doc = "Bit 3 - Port input enable 3"]
#[inline(always)]
pub fn p3(&mut self) -> P3_W<INErs> {
P3_W::new(self, 3)
}
#[doc = "Bit 4 - Port input enable 4"]
#[inline(always)]
pub fn p4(&mut self) -> P4_W<INErs> {
P4_W::new(self, 4)
}
#[doc = "Bit 5 - Port input enable 5"]
#[inline(always)]
pub fn p5(&mut self) -> P5_W<INErs> {
P5_W::new(self, 5)
}
#[doc = "Bit 6 - Port input enable 6"]
#[inline(always)]
pub fn p6(&mut self) -> P6_W<INErs> {
P6_W::new(self, 6)
}
#[doc = "Bit 7 - Port input enable 7"]
#[inline(always)]
pub fn p7(&mut self) -> P7_W<INErs> {
P7_W::new(self, 7)
}
}
#[doc = "GPIO Port Input Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ine::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ine::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INErs;
impl crate::RegisterSpec for INErs {
type Ux = u32;
}
#[doc = "`read()` method returns [`ine::R`](R) reader structure"]
impl crate::Readable for INErs {}
#[doc = "`write(|w| ..)` method takes [`ine::W`](W) writer structure"]
impl crate::Writable for INErs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INE to value 0"]
impl crate::Resettable for INErs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INTP (rw) register accessor: GPIO Port Interrupt Polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`intp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intp`]
module"]
pub type INTP = crate::Reg<intp::INTPrs>;
#[doc = "GPIO Port Interrupt Polarity"]
pub mod intp {
#[doc = "Register `INTP` reader"]
pub type R = crate::R<INTPrs>;
#[doc = "Register `INTP` writer"]
pub type W = crate::W<INTPrs>;
#[doc = "Port<n>0 Interrupt Polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: Falling edge, high to low transition"]
Falling = 0,
#[doc = "1: Rising edge, low to high transition"]
Rising = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port<n>0 Interrupt Polarity"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::Falling,
true => P0::Rising,
}
}
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn is_falling(&self) -> bool {
*self == P0::Falling
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == P0::Rising
}
}
#[doc = "Field `P0` writer - Port<n>0 Interrupt Polarity"]
pub type P0_W<'a, REG> = crate::BitWriter<'a, REG, P0>;
impl<'a, REG> P0_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn falling(self) -> &'a mut crate::W<REG> {
self.variant(P0::Falling)
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn rising(self) -> &'a mut crate::W<REG> {
self.variant(P0::Rising)
}
}
#[doc = "Port<n>1 Interrupt Polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: Falling edge, high to low transition"]
Falling = 0,
#[doc = "1: Rising edge, low to high transition"]
Rising = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port<n>1 Interrupt Polarity"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::Falling,
true => P1::Rising,
}
}
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn is_falling(&self) -> bool {
*self == P1::Falling
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == P1::Rising
}
}
#[doc = "Field `P1` writer - Port<n>1 Interrupt Polarity"]
pub type P1_W<'a, REG> = crate::BitWriter<'a, REG, P1>;
impl<'a, REG> P1_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn falling(self) -> &'a mut crate::W<REG> {
self.variant(P1::Falling)
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn rising(self) -> &'a mut crate::W<REG> {
self.variant(P1::Rising)
}
}
#[doc = "Port<n>2 Interrupt Polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: Falling edge, high to low transition"]
Falling = 0,
#[doc = "1: Rising edge, low to high transition"]
Rising = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port<n>2 Interrupt Polarity"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::Falling,
true => P2::Rising,
}
}
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn is_falling(&self) -> bool {
*self == P2::Falling
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == P2::Rising
}
}
#[doc = "Field `P2` writer - Port<n>2 Interrupt Polarity"]
pub type P2_W<'a, REG> = crate::BitWriter<'a, REG, P2>;
impl<'a, REG> P2_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn falling(self) -> &'a mut crate::W<REG> {
self.variant(P2::Falling)
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn rising(self) -> &'a mut crate::W<REG> {
self.variant(P2::Rising)
}
}
#[doc = "Port<n>3 Interrupt Polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: Falling edge, high to low transition"]
Falling = 0,
#[doc = "1: Rising edge, low to high transition"]
Rising = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port<n>3 Interrupt Polarity"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::Falling,
true => P3::Rising,
}
}
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn is_falling(&self) -> bool {
*self == P3::Falling
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == P3::Rising
}
}
#[doc = "Field `P3` writer - Port<n>3 Interrupt Polarity"]
pub type P3_W<'a, REG> = crate::BitWriter<'a, REG, P3>;
impl<'a, REG> P3_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn falling(self) -> &'a mut crate::W<REG> {
self.variant(P3::Falling)
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn rising(self) -> &'a mut crate::W<REG> {
self.variant(P3::Rising)
}
}
#[doc = "Port<n>4 Interrupt Polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: Falling edge, high to low transition"]
Falling = 0,
#[doc = "1: Rising edge, low to high transition"]
Rising = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port<n>4 Interrupt Polarity"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::Falling,
true => P4::Rising,
}
}
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn is_falling(&self) -> bool {
*self == P4::Falling
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == P4::Rising
}
}
#[doc = "Field `P4` writer - Port<n>4 Interrupt Polarity"]
pub type P4_W<'a, REG> = crate::BitWriter<'a, REG, P4>;
impl<'a, REG> P4_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn falling(self) -> &'a mut crate::W<REG> {
self.variant(P4::Falling)
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn rising(self) -> &'a mut crate::W<REG> {
self.variant(P4::Rising)
}
}
#[doc = "Port<n>5 Interrupt Polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: Falling edge, high to low transition"]
Falling = 0,
#[doc = "1: Rising edge, low to high transition"]
Rising = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port<n>5 Interrupt Polarity"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::Falling,
true => P5::Rising,
}
}
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn is_falling(&self) -> bool {
*self == P5::Falling
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == P5::Rising
}
}
#[doc = "Field `P5` writer - Port<n>5 Interrupt Polarity"]
pub type P5_W<'a, REG> = crate::BitWriter<'a, REG, P5>;
impl<'a, REG> P5_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn falling(self) -> &'a mut crate::W<REG> {
self.variant(P5::Falling)
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn rising(self) -> &'a mut crate::W<REG> {
self.variant(P5::Rising)
}
}
#[doc = "Port<n>6 Interrupt Polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: Falling edge, high to low transition"]
Falling = 0,
#[doc = "1: Rising edge, low to high transition"]
Rising = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port<n>6 Interrupt Polarity"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::Falling,
true => P6::Rising,
}
}
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn is_falling(&self) -> bool {
*self == P6::Falling
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == P6::Rising
}
}
#[doc = "Field `P6` writer - Port<n>6 Interrupt Polarity"]
pub type P6_W<'a, REG> = crate::BitWriter<'a, REG, P6>;
impl<'a, REG> P6_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn falling(self) -> &'a mut crate::W<REG> {
self.variant(P6::Falling)
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn rising(self) -> &'a mut crate::W<REG> {
self.variant(P6::Rising)
}
}
#[doc = "Port<n>7 Interrupt Polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: Falling edge, high to low transition"]
Falling = 0,
#[doc = "1: Rising edge, low to high transition"]
Rising = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port<n>7 Interrupt Polarity"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::Falling,
true => P7::Rising,
}
}
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn is_falling(&self) -> bool {
*self == P7::Falling
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == P7::Rising
}
}
#[doc = "Field `P7` writer - Port<n>7 Interrupt Polarity"]
pub type P7_W<'a, REG> = crate::BitWriter<'a, REG, P7>;
impl<'a, REG> P7_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Falling edge, high to low transition"]
#[inline(always)]
pub fn falling(self) -> &'a mut crate::W<REG> {
self.variant(P7::Falling)
}
#[doc = "Rising edge, low to high transition"]
#[inline(always)]
pub fn rising(self) -> &'a mut crate::W<REG> {
self.variant(P7::Rising)
}
}
impl R {
#[doc = "Bit 0 - Port<n>0 Interrupt Polarity"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port<n>1 Interrupt Polarity"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port<n>2 Interrupt Polarity"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port<n>3 Interrupt Polarity"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port<n>4 Interrupt Polarity"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port<n>5 Interrupt Polarity"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port<n>6 Interrupt Polarity"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port<n>7 Interrupt Polarity"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INTP")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Port<n>0 Interrupt Polarity"]
#[inline(always)]
pub fn p0(&mut self) -> P0_W<INTPrs> {
P0_W::new(self, 0)
}
#[doc = "Bit 1 - Port<n>1 Interrupt Polarity"]
#[inline(always)]
pub fn p1(&mut self) -> P1_W<INTPrs> {
P1_W::new(self, 1)
}
#[doc = "Bit 2 - Port<n>2 Interrupt Polarity"]
#[inline(always)]
pub fn p2(&mut self) -> P2_W<INTPrs> {
P2_W::new(self, 2)
}
#[doc = "Bit 3 - Port<n>3 Interrupt Polarity"]
#[inline(always)]
pub fn p3(&mut self) -> P3_W<INTPrs> {
P3_W::new(self, 3)
}
#[doc = "Bit 4 - Port<n>4 Interrupt Polarity"]
#[inline(always)]
pub fn p4(&mut self) -> P4_W<INTPrs> {
P4_W::new(self, 4)
}
#[doc = "Bit 5 - Port<n>5 Interrupt Polarity"]
#[inline(always)]
pub fn p5(&mut self) -> P5_W<INTPrs> {
P5_W::new(self, 5)
}
#[doc = "Bit 6 - Port<n>6 Interrupt Polarity"]
#[inline(always)]
pub fn p6(&mut self) -> P6_W<INTPrs> {
P6_W::new(self, 6)
}
#[doc = "Bit 7 - Port<n>7 Interrupt Polarity"]
#[inline(always)]
pub fn p7(&mut self) -> P7_W<INTPrs> {
P7_W::new(self, 7)
}
}
#[doc = "GPIO Port Interrupt Polarity\n\nYou can [`read`](crate::Reg::read) this register and get [`intp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INTPrs;
impl crate::RegisterSpec for INTPrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`intp::R`](R) reader structure"]
impl crate::Readable for INTPrs {}
#[doc = "`write(|w| ..)` method takes [`intp::W`](W) writer structure"]
impl crate::Writable for INTPrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INTP to value 0"]
impl crate::Resettable for INTPrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INTE (rw) register accessor: GPIO Port Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inte`]
module"]
pub type INTE = crate::Reg<inte::INTErs>;
#[doc = "GPIO Port Interrupt Enable"]
pub mod inte {
#[doc = "Register `INTE` reader"]
pub type R = crate::R<INTErs>;
#[doc = "Register `INTE` writer"]
pub type W = crate::W<INTErs>;
#[doc = "Port<n>0 Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: Disable interrupt"]
Disable = 0,
#[doc = "1: Enable interrupt"]
Enable = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port<n>0 Interrupt Enable"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::Disable,
true => P0::Enable,
}
}
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == P0::Disable
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == P0::Enable
}
}
#[doc = "Field `P0` writer - Port<n>0 Interrupt Enable"]
pub type P0_W<'a, REG> = crate::BitWriter<'a, REG, P0>;
impl<'a, REG> P0_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(P0::Disable)
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(P0::Enable)
}
}
#[doc = "Port<n>1 Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: Disable interrupt"]
Disable = 0,
#[doc = "1: Enable interrupt"]
Enable = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port<n>1 Interrupt Enable"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::Disable,
true => P1::Enable,
}
}
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == P1::Disable
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == P1::Enable
}
}
#[doc = "Field `P1` writer - Port<n>1 Interrupt Enable"]
pub type P1_W<'a, REG> = crate::BitWriter<'a, REG, P1>;
impl<'a, REG> P1_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(P1::Disable)
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(P1::Enable)
}
}
#[doc = "Port<n>2 Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: Disable interrupt"]
Disable = 0,
#[doc = "1: Enable interrupt"]
Enable = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port<n>2 Interrupt Enable"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::Disable,
true => P2::Enable,
}
}
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == P2::Disable
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == P2::Enable
}
}
#[doc = "Field `P2` writer - Port<n>2 Interrupt Enable"]
pub type P2_W<'a, REG> = crate::BitWriter<'a, REG, P2>;
impl<'a, REG> P2_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(P2::Disable)
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(P2::Enable)
}
}
#[doc = "Port<n>3 Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: Disable interrupt"]
Disable = 0,
#[doc = "1: Enable interrupt"]
Enable = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port<n>3 Interrupt Enable"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::Disable,
true => P3::Enable,
}
}
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == P3::Disable
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == P3::Enable
}
}
#[doc = "Field `P3` writer - Port<n>3 Interrupt Enable"]
pub type P3_W<'a, REG> = crate::BitWriter<'a, REG, P3>;
impl<'a, REG> P3_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(P3::Disable)
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(P3::Enable)
}
}
#[doc = "Port<n>4 Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: Disable interrupt"]
Disable = 0,
#[doc = "1: Enable interrupt"]
Enable = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port<n>4 Interrupt Enable"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::Disable,
true => P4::Enable,
}
}
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == P4::Disable
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == P4::Enable
}
}
#[doc = "Field `P4` writer - Port<n>4 Interrupt Enable"]
pub type P4_W<'a, REG> = crate::BitWriter<'a, REG, P4>;
impl<'a, REG> P4_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(P4::Disable)
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(P4::Enable)
}
}
#[doc = "Port<n>5 Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: Disable interrupt"]
Disable = 0,
#[doc = "1: Enable interrupt"]
Enable = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port<n>5 Interrupt Enable"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::Disable,
true => P5::Enable,
}
}
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == P5::Disable
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == P5::Enable
}
}
#[doc = "Field `P5` writer - Port<n>5 Interrupt Enable"]
pub type P5_W<'a, REG> = crate::BitWriter<'a, REG, P5>;
impl<'a, REG> P5_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(P5::Disable)
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(P5::Enable)
}
}
#[doc = "Port<n>6 Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: Disable interrupt"]
Disable = 0,
#[doc = "1: Enable interrupt"]
Enable = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port<n>6 Interrupt Enable"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::Disable,
true => P6::Enable,
}
}
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == P6::Disable
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == P6::Enable
}
}
#[doc = "Field `P6` writer - Port<n>6 Interrupt Enable"]
pub type P6_W<'a, REG> = crate::BitWriter<'a, REG, P6>;
impl<'a, REG> P6_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(P6::Disable)
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(P6::Enable)
}
}
#[doc = "Port<n>7 Interrupt Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: Disable interrupt"]
Disable = 0,
#[doc = "1: Enable interrupt"]
Enable = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port<n>7 Interrupt Enable"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::Disable,
true => P7::Enable,
}
}
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == P7::Disable
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == P7::Enable
}
}
#[doc = "Field `P7` writer - Port<n>7 Interrupt Enable"]
pub type P7_W<'a, REG> = crate::BitWriter<'a, REG, P7>;
impl<'a, REG> P7_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(P7::Disable)
}
#[doc = "Enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(P7::Enable)
}
}
impl R {
#[doc = "Bit 0 - Port<n>0 Interrupt Enable"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port<n>1 Interrupt Enable"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port<n>2 Interrupt Enable"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port<n>3 Interrupt Enable"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port<n>4 Interrupt Enable"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port<n>5 Interrupt Enable"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port<n>6 Interrupt Enable"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port<n>7 Interrupt Enable"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INTE")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Port<n>0 Interrupt Enable"]
#[inline(always)]
pub fn p0(&mut self) -> P0_W<INTErs> {
P0_W::new(self, 0)
}
#[doc = "Bit 1 - Port<n>1 Interrupt Enable"]
#[inline(always)]
pub fn p1(&mut self) -> P1_W<INTErs> {
P1_W::new(self, 1)
}
#[doc = "Bit 2 - Port<n>2 Interrupt Enable"]
#[inline(always)]
pub fn p2(&mut self) -> P2_W<INTErs> {
P2_W::new(self, 2)
}
#[doc = "Bit 3 - Port<n>3 Interrupt Enable"]
#[inline(always)]
pub fn p3(&mut self) -> P3_W<INTErs> {
P3_W::new(self, 3)
}
#[doc = "Bit 4 - Port<n>4 Interrupt Enable"]
#[inline(always)]
pub fn p4(&mut self) -> P4_W<INTErs> {
P4_W::new(self, 4)
}
#[doc = "Bit 5 - Port<n>5 Interrupt Enable"]
#[inline(always)]
pub fn p5(&mut self) -> P5_W<INTErs> {
P5_W::new(self, 5)
}
#[doc = "Bit 6 - Port<n>6 Interrupt Enable"]
#[inline(always)]
pub fn p6(&mut self) -> P6_W<INTErs> {
P6_W::new(self, 6)
}
#[doc = "Bit 7 - Port<n>7 Interrupt Enable"]
#[inline(always)]
pub fn p7(&mut self) -> P7_W<INTErs> {
P7_W::new(self, 7)
}
}
#[doc = "GPIO Port Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INTErs;
impl crate::RegisterSpec for INTErs {
type Ux = u32;
}
#[doc = "`read()` method returns [`inte::R`](R) reader structure"]
impl crate::Readable for INTErs {}
#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"]
impl crate::Writable for INTErs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INTE to value 0"]
impl crate::Resettable for INTErs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INTF (rw) register accessor: GPIO Port Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intf`]
module"]
pub type INTF = crate::Reg<intf::INTFrs>;
#[doc = "GPIO Port Interrupt Flag"]
pub mod intf {
#[doc = "Register `INTF` reader"]
pub type R = crate::R<INTFrs>;
#[doc = "Register `INTF` writer"]
pub type W = crate::W<INTFrs>;
#[doc = "Port<n>0 Interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: No interrupt pending"]
None = 0,
#[doc = "1: Interrupt pending"]
Interrupt = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port<n>0 Interrupt"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::None,
true => P0::Interrupt,
}
}
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == P0::None
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == P0::Interrupt
}
}
#[doc = "Field `P0` writer - Port<n>0 Interrupt"]
pub type P0_W<'a, REG> = crate::BitWriter<'a, REG, P0>;
impl<'a, REG> P0_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(P0::None)
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(P0::Interrupt)
}
}
#[doc = "Port<n>1 Interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: No interrupt pending"]
None = 0,
#[doc = "1: Interrupt pending"]
Interrupt = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port<n>1 Interrupt"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::None,
true => P1::Interrupt,
}
}
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == P1::None
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == P1::Interrupt
}
}
#[doc = "Field `P1` writer - Port<n>1 Interrupt"]
pub type P1_W<'a, REG> = crate::BitWriter<'a, REG, P1>;
impl<'a, REG> P1_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(P1::None)
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(P1::Interrupt)
}
}
#[doc = "Port<n>2 Interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: No interrupt pending"]
None = 0,
#[doc = "1: Interrupt pending"]
Interrupt = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port<n>2 Interrupt"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::None,
true => P2::Interrupt,
}
}
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == P2::None
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == P2::Interrupt
}
}
#[doc = "Field `P2` writer - Port<n>2 Interrupt"]
pub type P2_W<'a, REG> = crate::BitWriter<'a, REG, P2>;
impl<'a, REG> P2_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(P2::None)
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(P2::Interrupt)
}
}
#[doc = "Port<n>3 Interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: No interrupt pending"]
None = 0,
#[doc = "1: Interrupt pending"]
Interrupt = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port<n>3 Interrupt"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::None,
true => P3::Interrupt,
}
}
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == P3::None
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == P3::Interrupt
}
}
#[doc = "Field `P3` writer - Port<n>3 Interrupt"]
pub type P3_W<'a, REG> = crate::BitWriter<'a, REG, P3>;
impl<'a, REG> P3_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(P3::None)
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(P3::Interrupt)
}
}
#[doc = "Port<n>4 Interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: No interrupt pending"]
None = 0,
#[doc = "1: Interrupt pending"]
Interrupt = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port<n>4 Interrupt"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::None,
true => P4::Interrupt,
}
}
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == P4::None
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == P4::Interrupt
}
}
#[doc = "Field `P4` writer - Port<n>4 Interrupt"]
pub type P4_W<'a, REG> = crate::BitWriter<'a, REG, P4>;
impl<'a, REG> P4_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(P4::None)
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(P4::Interrupt)
}
}
#[doc = "Port<n>5 Interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: No interrupt pending"]
None = 0,
#[doc = "1: Interrupt pending"]
Interrupt = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port<n>5 Interrupt"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::None,
true => P5::Interrupt,
}
}
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == P5::None
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == P5::Interrupt
}
}
#[doc = "Field `P5` writer - Port<n>5 Interrupt"]
pub type P5_W<'a, REG> = crate::BitWriter<'a, REG, P5>;
impl<'a, REG> P5_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(P5::None)
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(P5::Interrupt)
}
}
#[doc = "Port<n>6 Interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: No interrupt pending"]
None = 0,
#[doc = "1: Interrupt pending"]
Interrupt = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port<n>6 Interrupt"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::None,
true => P6::Interrupt,
}
}
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == P6::None
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == P6::Interrupt
}
}
#[doc = "Field `P6` writer - Port<n>6 Interrupt"]
pub type P6_W<'a, REG> = crate::BitWriter<'a, REG, P6>;
impl<'a, REG> P6_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(P6::None)
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(P6::Interrupt)
}
}
#[doc = "Port<n>7 Interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: No interrupt pending"]
None = 0,
#[doc = "1: Interrupt pending"]
Interrupt = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port<n>7 Interrupt"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::None,
true => P7::Interrupt,
}
}
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == P7::None
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == P7::Interrupt
}
}
#[doc = "Field `P7` writer - Port<n>7 Interrupt"]
pub type P7_W<'a, REG> = crate::BitWriter<'a, REG, P7>;
impl<'a, REG> P7_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No interrupt pending"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(P7::None)
}
#[doc = "Interrupt pending"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(P7::Interrupt)
}
}
impl R {
#[doc = "Bit 0 - Port<n>0 Interrupt"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port<n>1 Interrupt"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port<n>2 Interrupt"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port<n>3 Interrupt"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port<n>4 Interrupt"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port<n>5 Interrupt"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port<n>6 Interrupt"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port<n>7 Interrupt"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INTF")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Port<n>0 Interrupt"]
#[inline(always)]
pub fn p0(&mut self) -> P0_W<INTFrs> {
P0_W::new(self, 0)
}
#[doc = "Bit 1 - Port<n>1 Interrupt"]
#[inline(always)]
pub fn p1(&mut self) -> P1_W<INTFrs> {
P1_W::new(self, 1)
}
#[doc = "Bit 2 - Port<n>2 Interrupt"]
#[inline(always)]
pub fn p2(&mut self) -> P2_W<INTFrs> {
P2_W::new(self, 2)
}
#[doc = "Bit 3 - Port<n>3 Interrupt"]
#[inline(always)]
pub fn p3(&mut self) -> P3_W<INTFrs> {
P3_W::new(self, 3)
}
#[doc = "Bit 4 - Port<n>4 Interrupt"]
#[inline(always)]
pub fn p4(&mut self) -> P4_W<INTFrs> {
P4_W::new(self, 4)
}
#[doc = "Bit 5 - Port<n>5 Interrupt"]
#[inline(always)]
pub fn p5(&mut self) -> P5_W<INTFrs> {
P5_W::new(self, 5)
}
#[doc = "Bit 6 - Port<n>6 Interrupt"]
#[inline(always)]
pub fn p6(&mut self) -> P6_W<INTFrs> {
P6_W::new(self, 6)
}
#[doc = "Bit 7 - Port<n>7 Interrupt"]
#[inline(always)]
pub fn p7(&mut self) -> P7_W<INTFrs> {
P7_W::new(self, 7)
}
}
#[doc = "GPIO Port Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INTFrs;
impl crate::RegisterSpec for INTFrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`intf::R`](R) reader structure"]
impl crate::Readable for INTFrs {}
#[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"]
impl crate::Writable for INTFrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INTF to value 0"]
impl crate::Resettable for INTFrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "INTM (rw) register accessor: GPIO Port Interrupt Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`intm::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intm::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intm`]
module"]
pub type INTM = crate::Reg<intm::INTMrs>;
#[doc = "GPIO Port Interrupt Mask"]
pub mod intm {
#[doc = "Register `INTM` reader"]
pub type R = crate::R<INTMrs>;
#[doc = "Register `INTM` writer"]
pub type W = crate::W<INTMrs>;
#[doc = "Port<n>0 Interrupt Mask\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P0 {
#[doc = "0: Disable interrupt mask"]
Disabled = 0,
#[doc = "1: Enable interrupt mask"]
Enabled = 1,
}
impl From<P0> for bool {
#[inline(always)]
fn from(variant: P0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P0` reader - Port<n>0 Interrupt Mask"]
pub type P0_R = crate::BitReader<P0>;
impl P0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P0 {
match self.bits {
false => P0::Disabled,
true => P0::Enabled,
}
}
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P0::Disabled
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P0::Enabled
}
}
#[doc = "Field `P0` writer - Port<n>0 Interrupt Mask"]
pub type P0_W<'a, REG> = crate::BitWriter<'a, REG, P0>;
impl<'a, REG> P0_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P0::Disabled)
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P0::Enabled)
}
}
#[doc = "Port<n>1 Interrupt Mask\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P1 {
#[doc = "0: Disable interrupt mask"]
Disabled = 0,
#[doc = "1: Enable interrupt mask"]
Enabled = 1,
}
impl From<P1> for bool {
#[inline(always)]
fn from(variant: P1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P1` reader - Port<n>1 Interrupt Mask"]
pub type P1_R = crate::BitReader<P1>;
impl P1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P1 {
match self.bits {
false => P1::Disabled,
true => P1::Enabled,
}
}
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P1::Disabled
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P1::Enabled
}
}
#[doc = "Field `P1` writer - Port<n>1 Interrupt Mask"]
pub type P1_W<'a, REG> = crate::BitWriter<'a, REG, P1>;
impl<'a, REG> P1_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P1::Disabled)
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P1::Enabled)
}
}
#[doc = "Port<n>2 Interrupt Mask\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P2 {
#[doc = "0: Disable interrupt mask"]
Disabled = 0,
#[doc = "1: Enable interrupt mask"]
Enabled = 1,
}
impl From<P2> for bool {
#[inline(always)]
fn from(variant: P2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P2` reader - Port<n>2 Interrupt Mask"]
pub type P2_R = crate::BitReader<P2>;
impl P2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P2 {
match self.bits {
false => P2::Disabled,
true => P2::Enabled,
}
}
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P2::Disabled
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P2::Enabled
}
}
#[doc = "Field `P2` writer - Port<n>2 Interrupt Mask"]
pub type P2_W<'a, REG> = crate::BitWriter<'a, REG, P2>;
impl<'a, REG> P2_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P2::Disabled)
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P2::Enabled)
}
}
#[doc = "Port<n>3 Interrupt Mask\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P3 {
#[doc = "0: Disable interrupt mask"]
Disabled = 0,
#[doc = "1: Enable interrupt mask"]
Enabled = 1,
}
impl From<P3> for bool {
#[inline(always)]
fn from(variant: P3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P3` reader - Port<n>3 Interrupt Mask"]
pub type P3_R = crate::BitReader<P3>;
impl P3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P3 {
match self.bits {
false => P3::Disabled,
true => P3::Enabled,
}
}
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P3::Disabled
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P3::Enabled
}
}
#[doc = "Field `P3` writer - Port<n>3 Interrupt Mask"]
pub type P3_W<'a, REG> = crate::BitWriter<'a, REG, P3>;
impl<'a, REG> P3_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P3::Disabled)
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P3::Enabled)
}
}
#[doc = "Port<n>4 Interrupt Mask\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P4 {
#[doc = "0: Disable interrupt mask"]
Disabled = 0,
#[doc = "1: Enable interrupt mask"]
Enabled = 1,
}
impl From<P4> for bool {
#[inline(always)]
fn from(variant: P4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P4` reader - Port<n>4 Interrupt Mask"]
pub type P4_R = crate::BitReader<P4>;
impl P4_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P4 {
match self.bits {
false => P4::Disabled,
true => P4::Enabled,
}
}
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P4::Disabled
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P4::Enabled
}
}
#[doc = "Field `P4` writer - Port<n>4 Interrupt Mask"]
pub type P4_W<'a, REG> = crate::BitWriter<'a, REG, P4>;
impl<'a, REG> P4_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P4::Disabled)
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P4::Enabled)
}
}
#[doc = "Port<n>5 Interrupt Mask\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P5 {
#[doc = "0: Disable interrupt mask"]
Disabled = 0,
#[doc = "1: Enable interrupt mask"]
Enabled = 1,
}
impl From<P5> for bool {
#[inline(always)]
fn from(variant: P5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P5` reader - Port<n>5 Interrupt Mask"]
pub type P5_R = crate::BitReader<P5>;
impl P5_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P5 {
match self.bits {
false => P5::Disabled,
true => P5::Enabled,
}
}
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P5::Disabled
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P5::Enabled
}
}
#[doc = "Field `P5` writer - Port<n>5 Interrupt Mask"]
pub type P5_W<'a, REG> = crate::BitWriter<'a, REG, P5>;
impl<'a, REG> P5_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P5::Disabled)
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P5::Enabled)
}
}
#[doc = "Port<n>6 Interrupt Mask\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P6 {
#[doc = "0: Disable interrupt mask"]
Disabled = 0,
#[doc = "1: Enable interrupt mask"]
Enabled = 1,
}
impl From<P6> for bool {
#[inline(always)]
fn from(variant: P6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P6` reader - Port<n>6 Interrupt Mask"]
pub type P6_R = crate::BitReader<P6>;
impl P6_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P6 {
match self.bits {
false => P6::Disabled,
true => P6::Enabled,
}
}
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P6::Disabled
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P6::Enabled
}
}
#[doc = "Field `P6` writer - Port<n>6 Interrupt Mask"]
pub type P6_W<'a, REG> = crate::BitWriter<'a, REG, P6>;
impl<'a, REG> P6_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P6::Disabled)
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P6::Enabled)
}
}
#[doc = "Port<n>7 Interrupt Mask\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum P7 {
#[doc = "0: Disable interrupt mask"]
Disabled = 0,
#[doc = "1: Enable interrupt mask"]
Enabled = 1,
}
impl From<P7> for bool {
#[inline(always)]
fn from(variant: P7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `P7` reader - Port<n>7 Interrupt Mask"]
pub type P7_R = crate::BitReader<P7>;
impl P7_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> P7 {
match self.bits {
false => P7::Disabled,
true => P7::Enabled,
}
}
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == P7::Disabled
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == P7::Enabled
}
}
#[doc = "Field `P7` writer - Port<n>7 Interrupt Mask"]
pub type P7_W<'a, REG> = crate::BitWriter<'a, REG, P7>;
impl<'a, REG> P7_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable interrupt mask"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(P7::Disabled)
}
#[doc = "Enable interrupt mask"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(P7::Enabled)
}
}
impl R {
#[doc = "Bit 0 - Port<n>0 Interrupt Mask"]
#[inline(always)]
pub fn p0(&self) -> P0_R {
P0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Port<n>1 Interrupt Mask"]
#[inline(always)]
pub fn p1(&self) -> P1_R {
P1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port<n>2 Interrupt Mask"]
#[inline(always)]
pub fn p2(&self) -> P2_R {
P2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port<n>3 Interrupt Mask"]
#[inline(always)]
pub fn p3(&self) -> P3_R {
P3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Port<n>4 Interrupt Mask"]
#[inline(always)]
pub fn p4(&self) -> P4_R {
P4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Port<n>5 Interrupt Mask"]
#[inline(always)]
pub fn p5(&self) -> P5_R {
P5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Port<n>6 Interrupt Mask"]
#[inline(always)]
pub fn p6(&self) -> P6_R {
P6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Port<n>7 Interrupt Mask"]
#[inline(always)]
pub fn p7(&self) -> P7_R {
P7_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INTM")
.field("p0", &self.p0())
.field("p1", &self.p1())
.field("p2", &self.p2())
.field("p3", &self.p3())
.field("p4", &self.p4())
.field("p5", &self.p5())
.field("p6", &self.p6())
.field("p7", &self.p7())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Port<n>0 Interrupt Mask"]
#[inline(always)]
pub fn p0(&mut self) -> P0_W<INTMrs> {
P0_W::new(self, 0)
}
#[doc = "Bit 1 - Port<n>1 Interrupt Mask"]
#[inline(always)]
pub fn p1(&mut self) -> P1_W<INTMrs> {
P1_W::new(self, 1)
}
#[doc = "Bit 2 - Port<n>2 Interrupt Mask"]
#[inline(always)]
pub fn p2(&mut self) -> P2_W<INTMrs> {
P2_W::new(self, 2)
}
#[doc = "Bit 3 - Port<n>3 Interrupt Mask"]
#[inline(always)]
pub fn p3(&mut self) -> P3_W<INTMrs> {
P3_W::new(self, 3)
}
#[doc = "Bit 4 - Port<n>4 Interrupt Mask"]
#[inline(always)]
pub fn p4(&mut self) -> P4_W<INTMrs> {
P4_W::new(self, 4)
}
#[doc = "Bit 5 - Port<n>5 Interrupt Mask"]
#[inline(always)]
pub fn p5(&mut self) -> P5_W<INTMrs> {
P5_W::new(self, 5)
}
#[doc = "Bit 6 - Port<n>6 Interrupt Mask"]
#[inline(always)]
pub fn p6(&mut self) -> P6_W<INTMrs> {
P6_W::new(self, 6)
}
#[doc = "Bit 7 - Port<n>7 Interrupt Mask"]
#[inline(always)]
pub fn p7(&mut self) -> P7_W<INTMrs> {
P7_W::new(self, 7)
}
}
#[doc = "GPIO Port Interrupt Mask\n\nYou can [`read`](crate::Reg::read) this register and get [`intm::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intm::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INTMrs;
impl crate::RegisterSpec for INTMrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`intm::R`](R) reader structure"]
impl crate::Readable for INTMrs {}
#[doc = "`write(|w| ..)` method takes [`intm::W`](W) writer structure"]
impl crate::Writable for INTMrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INTM to value 0"]
impl crate::Resettable for INTMrs {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "General-Purpose Input-Output Port D"]
pub struct GPIOD {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOD {}
impl GPIOD {
#[doc = r"Pointer to the register block"]
pub const PTR: *const gpioa::RegisterBlock = 0x4008_0040 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const gpioa::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for GPIOD {
type Target = gpioa::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for GPIOD {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOD").finish()
}
}
#[doc = "General-Purpose Input-Output Port D"]
pub use self::gpioa as gpiod;
#[doc = "General-Purpose Input-Output Port E"]
pub struct GPIOE {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOE {}
impl GPIOE {
#[doc = r"Pointer to the register block"]
pub const PTR: *const gpioa::RegisterBlock = 0x4009_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const gpioa::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for GPIOE {
type Target = gpioa::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for GPIOE {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOE").finish()
}
}
#[doc = "General-Purpose Input-Output Port E"]
pub use self::gpioa as gpioe;
#[doc = "Timer A Peripheral"]
pub struct TIMERA {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIMERA {}
impl TIMERA {
#[doc = r"Pointer to the register block"]
pub const PTR: *const timera::RegisterBlock = 0x400d_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const timera::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for TIMERA {
type Target = timera::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for TIMERA {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIMERA").finish()
}
}
#[doc = "Timer A Peripheral"]
pub mod timera {
#[repr(C)]
#[derive(Debug)]
#[doc = "Register block"]
pub struct RegisterBlock {
tx_ctl: TX_CTL,
tx_prd: TX_PRD,
tx_ctr: TX_CTR,
_reserved3: [u8; 0x34],
tx_cc0ctl: TX_CC0CTL,
tx_cc0ctr: TX_CC0CTR,
tx_cc1ctl: TX_CC1CTL,
tx_cc1ctr: TX_CC1CTR,
tx_cc2ctl: TX_CC2CTL,
tx_cc2ctr: TX_CC2CTR,
tx_cc3ctl: TX_CC3CTL,
tx_cc3ctr: TX_CC3CTR,
tx_cc4ctl: TX_CC4CTL,
tx_cc4ctr: TX_CC4CTR,
tx_cc5ctl: TX_CC5CTL,
tx_cc5ctr: TX_CC5CTR,
tx_cc6ctl: TX_CC6CTL,
tx_cc6ctr: TX_CC6CTR,
tx_cc7ctl: TX_CC7CTL,
tx_cc7ctr: TX_CC7CTR,
_reserved19: [u8; 0x20],
dtga0ctl: DTGA0CTL,
dtga0led: DTGA0LED,
dtga0ted: DTGA0TED,
_reserved22: [u8; 0x04],
dtga1ctl: DTGA1CTL,
dtga1led: DTGA1LED,
dtga1ted: DTGA1TED,
_reserved25: [u8; 0x04],
dtga2ctl: DTGA2CTL,
dtga2led: DTGA2LED,
dtga2ted: DTGA2TED,
_reserved28: [u8; 0x04],
dtga3ctl: DTGA3CTL,
dtga3led: DTGA3LED,
dtga3ted: DTGA3TED,
}
impl RegisterBlock {
#[doc = "0x00 - Timer Control Register"]
#[inline(always)]
pub const fn tx_ctl(&self) -> &TX_CTL {
&self.tx_ctl
}
#[doc = "0x04 - timer period"]
#[inline(always)]
pub const fn tx_prd(&self) -> &TX_PRD {
&self.tx_prd
}
#[doc = "0x08 - timer counter"]
#[inline(always)]
pub const fn tx_ctr(&self) -> &TX_CTR {
&self.tx_ctr
}
#[doc = "0x40 - timer capture and compare control unit 0"]
#[inline(always)]
pub const fn tx_cc0ctl(&self) -> &TX_CC0CTL {
&self.tx_cc0ctl
}
#[doc = "0x44 - capture and compare counter unit 0"]
#[inline(always)]
pub const fn tx_cc0ctr(&self) -> &TX_CC0CTR {
&self.tx_cc0ctr
}
#[doc = "0x48 - timer capture and compare control unit 0"]
#[inline(always)]
pub const fn tx_cc1ctl(&self) -> &TX_CC1CTL {
&self.tx_cc1ctl
}
#[doc = "0x4c - capture and compare counter unit 1"]
#[inline(always)]
pub const fn tx_cc1ctr(&self) -> &TX_CC1CTR {
&self.tx_cc1ctr
}
#[doc = "0x50 - timer capture and compare control unit 2"]
#[inline(always)]
pub const fn tx_cc2ctl(&self) -> &TX_CC2CTL {
&self.tx_cc2ctl
}
#[doc = "0x54 - capture and compare counter unit 2"]
#[inline(always)]
pub const fn tx_cc2ctr(&self) -> &TX_CC2CTR {
&self.tx_cc2ctr
}
#[doc = "0x58 - timer capture and compare control unit 3"]
#[inline(always)]
pub const fn tx_cc3ctl(&self) -> &TX_CC3CTL {
&self.tx_cc3ctl
}
#[doc = "0x5c - capture and compare counter unit 3"]
#[inline(always)]
pub const fn tx_cc3ctr(&self) -> &TX_CC3CTR {
&self.tx_cc3ctr
}
#[doc = "0x60 - timer capture and compare control unit 4"]
#[inline(always)]
pub const fn tx_cc4ctl(&self) -> &TX_CC4CTL {
&self.tx_cc4ctl
}
#[doc = "0x64 - capture and compare counter unit 4"]
#[inline(always)]
pub const fn tx_cc4ctr(&self) -> &TX_CC4CTR {
&self.tx_cc4ctr
}
#[doc = "0x68 - timer capture and compare control unit 5"]
#[inline(always)]
pub const fn tx_cc5ctl(&self) -> &TX_CC5CTL {
&self.tx_cc5ctl
}
#[doc = "0x6c - capture and compare counter unit 5"]
#[inline(always)]
pub const fn tx_cc5ctr(&self) -> &TX_CC5CTR {
&self.tx_cc5ctr
}
#[doc = "0x70 - timer capture and compare control unit 6"]
#[inline(always)]
pub const fn tx_cc6ctl(&self) -> &TX_CC6CTL {
&self.tx_cc6ctl
}
#[doc = "0x74 - capture and compare counter unit 6"]
#[inline(always)]
pub const fn tx_cc6ctr(&self) -> &TX_CC6CTR {
&self.tx_cc6ctr
}
#[doc = "0x78 - timer capture and compare control unit 7"]
#[inline(always)]
pub const fn tx_cc7ctl(&self) -> &TX_CC7CTL {
&self.tx_cc7ctl
}
#[doc = "0x7c - capture and compare counter unit 7"]
#[inline(always)]
pub const fn tx_cc7ctr(&self) -> &TX_CC7CTR {
&self.tx_cc7ctr
}
#[doc = "0xa0 - Timer A dead-time generator control unit 0"]
#[inline(always)]
pub const fn dtga0ctl(&self) -> &DTGA0CTL {
&self.dtga0ctl
}
#[doc = "0xa4 - Timer A dead-time generator leading-edge delay counter unit 0"]
#[inline(always)]
pub const fn dtga0led(&self) -> &DTGA0LED {
&self.dtga0led
}
#[doc = "0xa8 - Timer A dead-time generator trailing-edge delay counter unit 0"]
#[inline(always)]
pub const fn dtga0ted(&self) -> &DTGA0TED {
&self.dtga0ted
}
#[doc = "0xb0 - Timer A dead-time generator control unit 1"]
#[inline(always)]
pub const fn dtga1ctl(&self) -> &DTGA1CTL {
&self.dtga1ctl
}
#[doc = "0xb4 - Timer A dead-time generator leading-edge delay counter unit 1"]
#[inline(always)]
pub const fn dtga1led(&self) -> &DTGA1LED {
&self.dtga1led
}
#[doc = "0xb8 - Timer A dead-time generator trailing-edge delay counter unit 1"]
#[inline(always)]
pub const fn dtga1ted(&self) -> &DTGA1TED {
&self.dtga1ted
}
#[doc = "0xc0 - Timer A dead-time generator control unit 2"]
#[inline(always)]
pub const fn dtga2ctl(&self) -> &DTGA2CTL {
&self.dtga2ctl
}
#[doc = "0xc4 - Timer A dead-time generator leading-edge delay counter unit 2"]
#[inline(always)]
pub const fn dtga2led(&self) -> &DTGA2LED {
&self.dtga2led
}
#[doc = "0xc8 - Timer A dead-time generator trailing-edge delay counter unit 2"]
#[inline(always)]
pub const fn dtga2ted(&self) -> &DTGA2TED {
&self.dtga2ted
}
#[doc = "0xd0 - Timer A dead-time generator control unit 3"]
#[inline(always)]
pub const fn dtga3ctl(&self) -> &DTGA3CTL {
&self.dtga3ctl
}
#[doc = "0xd4 - Timer A dead-time generator leading-edge delay counter unit 3"]
#[inline(always)]
pub const fn dtga3led(&self) -> &DTGA3LED {
&self.dtga3led
}
#[doc = "0xd8 - Timer A dead-time generator trailing-edge delay counter unit 0"]
#[inline(always)]
pub const fn dtga3ted(&self) -> &DTGA3TED {
&self.dtga3ted
}
}
#[doc = "TxCTL (rw) register accessor: Timer Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_ctl`]
module"]
#[doc(alias = "TxCTL")]
pub type TX_CTL = crate::Reg<tx_ctl::TX_CTLrs>;
#[doc = "Timer Control Register"]
pub mod tx_ctl {
#[doc = "Register `TxCTL` reader"]
pub type R = crate::R<TX_CTLrs>;
#[doc = "Register `TxCTL` writer"]
pub type W = crate::W<TX_CTLrs>;
#[doc = "Timer Period Latch\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum PRDL {
#[doc = "0: Latch timer values counting up at TxPRD-1"]
Period = 0,
#[doc = "1: Latch timer values when counting down to 1"]
Wrap = 1,
}
impl From<PRDL> for bool {
#[inline(always)]
fn from(variant: PRDL) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `PRDL` reader - Timer Period Latch"]
pub type PRDL_R = crate::BitReader<PRDL>;
impl PRDL_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> PRDL {
match self.bits {
false => PRDL::Period,
true => PRDL::Wrap,
}
}
#[doc = "Latch timer values counting up at TxPRD-1"]
#[inline(always)]
pub fn is_period(&self) -> bool {
*self == PRDL::Period
}
#[doc = "Latch timer values when counting down to 1"]
#[inline(always)]
pub fn is_wrap(&self) -> bool {
*self == PRDL::Wrap
}
}
#[doc = "Field `PRDL` writer - Timer Period Latch"]
pub type PRDL_W<'a, REG> = crate::BitWriter<'a, REG, PRDL>;
impl<'a, REG> PRDL_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Latch timer values counting up at TxPRD-1"]
#[inline(always)]
pub fn period(self) -> &'a mut crate::W<REG> {
self.variant(PRDL::Period)
}
#[doc = "Latch timer values when counting down to 1"]
#[inline(always)]
pub fn wrap(self) -> &'a mut crate::W<REG> {
self.variant(PRDL::Wrap)
}
}
#[doc = "Timer clear\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CLR {
#[doc = "0: Clear Timer, hold in reset, set SYNC_OUT"]
Clear = 0,
#[doc = "1: Do not clear timer, clear SYNC_OUT"]
Noclear = 1,
}
impl From<CLR> for bool {
#[inline(always)]
fn from(variant: CLR) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CLR` reader - Timer clear"]
pub type CLR_R = crate::BitReader<CLR>;
impl CLR_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CLR {
match self.bits {
false => CLR::Clear,
true => CLR::Noclear,
}
}
#[doc = "Clear Timer, hold in reset, set SYNC_OUT"]
#[inline(always)]
pub fn is_clear(&self) -> bool {
*self == CLR::Clear
}
#[doc = "Do not clear timer, clear SYNC_OUT"]
#[inline(always)]
pub fn is_noclear(&self) -> bool {
*self == CLR::Noclear
}
}
#[doc = "Field `CLR` writer - Timer clear"]
pub type CLR_W<'a, REG> = crate::BitWriter<'a, REG, CLR>;
impl<'a, REG> CLR_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Clear Timer, hold in reset, set SYNC_OUT"]
#[inline(always)]
pub fn clear(self) -> &'a mut crate::W<REG> {
self.variant(CLR::Clear)
}
#[doc = "Do not clear timer, clear SYNC_OUT"]
#[inline(always)]
pub fn noclear(self) -> &'a mut crate::W<REG> {
self.variant(CLR::Noclear)
}
}
#[doc = "Timer single shot\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SS {
#[doc = "0: Continuous mode"]
Continuous = 0,
#[doc = "1: Single shot mode"]
Single = 1,
}
impl From<SS> for bool {
#[inline(always)]
fn from(variant: SS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SS` reader - Timer single shot"]
pub type SS_R = crate::BitReader<SS>;
impl SS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SS {
match self.bits {
false => SS::Continuous,
true => SS::Single,
}
}
#[doc = "Continuous mode"]
#[inline(always)]
pub fn is_continuous(&self) -> bool {
*self == SS::Continuous
}
#[doc = "Single shot mode"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == SS::Single
}
}
#[doc = "Field `SS` writer - Timer single shot"]
pub type SS_W<'a, REG> = crate::BitWriter<'a, REG, SS>;
impl<'a, REG> SS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Continuous mode"]
#[inline(always)]
pub fn continuous(self) -> &'a mut crate::W<REG> {
self.variant(SS::Continuous)
}
#[doc = "Single shot mode"]
#[inline(always)]
pub fn single(self) -> &'a mut crate::W<REG> {
self.variant(SS::Single)
}
}
#[doc = "Timer interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INT {
#[doc = "0: interrupt flag, write 1 to clear"]
Interrupt = 0,
#[doc = "1: No interrupt"]
Noint = 1,
}
impl From<INT> for bool {
#[inline(always)]
fn from(variant: INT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INT` reader - Timer interrupt"]
pub type INT_R = crate::BitReader<INT>;
impl INT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INT {
match self.bits {
false => INT::Interrupt,
true => INT::Noint,
}
}
#[doc = "interrupt flag, write 1 to clear"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == INT::Interrupt
}
#[doc = "No interrupt"]
#[inline(always)]
pub fn is_noint(&self) -> bool {
*self == INT::Noint
}
}
#[doc = "Field `INT` writer - Timer interrupt"]
pub type INT_W<'a, REG> = crate::BitWriter<'a, REG, INT>;
impl<'a, REG> INT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt flag, write 1 to clear"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(INT::Interrupt)
}
#[doc = "No interrupt"]
#[inline(always)]
pub fn noint(self) -> &'a mut crate::W<REG> {
self.variant(INT::Noint)
}
}
#[doc = "Timer interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INTEN {
#[doc = "0: timer interrupt enabled"]
Enabled = 0,
#[doc = "1: timer interrupt disabled"]
Disabled = 1,
}
impl From<INTEN> for bool {
#[inline(always)]
fn from(variant: INTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INTEN` reader - Timer interrupt enable"]
pub type INTEN_R = crate::BitReader<INTEN>;
impl INTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INTEN {
match self.bits {
false => INTEN::Enabled,
true => INTEN::Disabled,
}
}
#[doc = "timer interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INTEN::Enabled
}
#[doc = "timer interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INTEN::Disabled
}
}
#[doc = "Field `INTEN` writer - Timer interrupt enable"]
pub type INTEN_W<'a, REG> = crate::BitWriter<'a, REG, INTEN>;
impl<'a, REG> INTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "timer interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INTEN::Enabled)
}
#[doc = "timer interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INTEN::Disabled)
}
}
#[doc = "timer clock divider\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum CLKDIV {
#[doc = "0: divide by 1"]
Div1 = 0,
#[doc = "1: divide by 2"]
Div2 = 1,
#[doc = "2: divide by 4"]
Div4 = 2,
#[doc = "3: divide by 8"]
Div8 = 3,
#[doc = "4: divide by 16"]
Div16 = 4,
#[doc = "5: divide by 32"]
Div32 = 5,
#[doc = "6: divide by 64"]
Div64 = 6,
#[doc = "7: divide by 128"]
Div128 = 7,
}
impl From<CLKDIV> for u8 {
#[inline(always)]
fn from(variant: CLKDIV) -> Self {
variant as _
}
}
impl crate::FieldSpec for CLKDIV {
type Ux = u8;
}
impl crate::IsEnum for CLKDIV {}
#[doc = "Field `CLKDIV` reader - timer clock divider"]
pub type CLKDIV_R = crate::FieldReader<CLKDIV>;
impl CLKDIV_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CLKDIV {
match self.bits {
0 => CLKDIV::Div1,
1 => CLKDIV::Div2,
2 => CLKDIV::Div4,
3 => CLKDIV::Div8,
4 => CLKDIV::Div16,
5 => CLKDIV::Div32,
6 => CLKDIV::Div64,
7 => CLKDIV::Div128,
_ => unreachable!(),
}
}
#[doc = "divide by 1"]
#[inline(always)]
pub fn is_div_1(&self) -> bool {
*self == CLKDIV::Div1
}
#[doc = "divide by 2"]
#[inline(always)]
pub fn is_div_2(&self) -> bool {
*self == CLKDIV::Div2
}
#[doc = "divide by 4"]
#[inline(always)]
pub fn is_div_4(&self) -> bool {
*self == CLKDIV::Div4
}
#[doc = "divide by 8"]
#[inline(always)]
pub fn is_div_8(&self) -> bool {
*self == CLKDIV::Div8
}
#[doc = "divide by 16"]
#[inline(always)]
pub fn is_div_16(&self) -> bool {
*self == CLKDIV::Div16
}
#[doc = "divide by 32"]
#[inline(always)]
pub fn is_div_32(&self) -> bool {
*self == CLKDIV::Div32
}
#[doc = "divide by 64"]
#[inline(always)]
pub fn is_div_64(&self) -> bool {
*self == CLKDIV::Div64
}
#[doc = "divide by 128"]
#[inline(always)]
pub fn is_div_128(&self) -> bool {
*self == CLKDIV::Div128
}
}
#[doc = "Field `CLKDIV` writer - timer clock divider"]
pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CLKDIV, crate::Safe>;
impl<'a, REG> CLKDIV_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "divide by 1"]
#[inline(always)]
pub fn div_1(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div1)
}
#[doc = "divide by 2"]
#[inline(always)]
pub fn div_2(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div2)
}
#[doc = "divide by 4"]
#[inline(always)]
pub fn div_4(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div4)
}
#[doc = "divide by 8"]
#[inline(always)]
pub fn div_8(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div8)
}
#[doc = "divide by 16"]
#[inline(always)]
pub fn div_16(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div16)
}
#[doc = "divide by 32"]
#[inline(always)]
pub fn div_32(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div32)
}
#[doc = "divide by 64"]
#[inline(always)]
pub fn div_64(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div64)
}
#[doc = "divide by 128"]
#[inline(always)]
pub fn div_128(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div128)
}
}
#[doc = "timer clock input source\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CLK {
#[doc = "0: HCLK"]
Hclk = 0,
#[doc = "1: ACLK"]
Aclk = 1,
}
impl From<CLK> for bool {
#[inline(always)]
fn from(variant: CLK) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CLK` reader - timer clock input source"]
pub type CLK_R = crate::BitReader<CLK>;
impl CLK_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CLK {
match self.bits {
false => CLK::Hclk,
true => CLK::Aclk,
}
}
#[doc = "HCLK"]
#[inline(always)]
pub fn is_hclk(&self) -> bool {
*self == CLK::Hclk
}
#[doc = "ACLK"]
#[inline(always)]
pub fn is_aclk(&self) -> bool {
*self == CLK::Aclk
}
}
#[doc = "Field `CLK` writer - timer clock input source"]
pub type CLK_W<'a, REG> = crate::BitWriter<'a, REG, CLK>;
impl<'a, REG> CLK_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "HCLK"]
#[inline(always)]
pub fn hclk(self) -> &'a mut crate::W<REG> {
self.variant(CLK::Hclk)
}
#[doc = "ACLK"]
#[inline(always)]
pub fn aclk(self) -> &'a mut crate::W<REG> {
self.variant(CLK::Aclk)
}
}
#[doc = "timer mode\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum MODE {
#[doc = "0: timer disabled"]
Disabled = 0,
#[doc = "1: up mode"]
Up = 1,
#[doc = "2: up/down mode"]
Updown = 2,
}
impl From<MODE> for u8 {
#[inline(always)]
fn from(variant: MODE) -> Self {
variant as _
}
}
impl crate::FieldSpec for MODE {
type Ux = u8;
}
impl crate::IsEnum for MODE {}
#[doc = "Field `MODE` reader - timer mode"]
pub type MODE_R = crate::FieldReader<MODE>;
impl MODE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<MODE> {
match self.bits {
0 => Some(MODE::Disabled),
1 => Some(MODE::Up),
2 => Some(MODE::Updown),
_ => None,
}
}
#[doc = "timer disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == MODE::Disabled
}
#[doc = "up mode"]
#[inline(always)]
pub fn is_up(&self) -> bool {
*self == MODE::Up
}
#[doc = "up/down mode"]
#[inline(always)]
pub fn is_updown(&self) -> bool {
*self == MODE::Updown
}
}
#[doc = "Field `MODE` writer - timer mode"]
pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, MODE>;
impl<'a, REG> MODE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "timer disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(MODE::Disabled)
}
#[doc = "up mode"]
#[inline(always)]
pub fn up(self) -> &'a mut crate::W<REG> {
self.variant(MODE::Up)
}
#[doc = "up/down mode"]
#[inline(always)]
pub fn updown(self) -> &'a mut crate::W<REG> {
self.variant(MODE::Updown)
}
}
#[doc = "DTG clock select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum DTGCLK {
#[doc = "0: DTG uses clock selected by TxTCL.CLK"]
Clk = 0,
#[doc = "1: DTG uses clock selected by TxCTL.CLKDIV"]
Clkdiv = 1,
}
impl From<DTGCLK> for bool {
#[inline(always)]
fn from(variant: DTGCLK) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `DTGCLK` reader - DTG clock select"]
pub type DTGCLK_R = crate::BitReader<DTGCLK>;
impl DTGCLK_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> DTGCLK {
match self.bits {
false => DTGCLK::Clk,
true => DTGCLK::Clkdiv,
}
}
#[doc = "DTG uses clock selected by TxTCL.CLK"]
#[inline(always)]
pub fn is_clk(&self) -> bool {
*self == DTGCLK::Clk
}
#[doc = "DTG uses clock selected by TxCTL.CLKDIV"]
#[inline(always)]
pub fn is_clkdiv(&self) -> bool {
*self == DTGCLK::Clkdiv
}
}
#[doc = "Field `DTGCLK` writer - DTG clock select"]
pub type DTGCLK_W<'a, REG> = crate::BitWriter<'a, REG, DTGCLK>;
impl<'a, REG> DTGCLK_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "DTG uses clock selected by TxTCL.CLK"]
#[inline(always)]
pub fn clk(self) -> &'a mut crate::W<REG> {
self.variant(DTGCLK::Clk)
}
#[doc = "DTG uses clock selected by TxCTL.CLKDIV"]
#[inline(always)]
pub fn clkdiv(self) -> &'a mut crate::W<REG> {
self.variant(DTGCLK::Clkdiv)
}
}
impl R {
#[doc = "Bit 0 - Timer Period Latch"]
#[inline(always)]
pub fn prdl(&self) -> PRDL_R {
PRDL_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 2 - Timer clear"]
#[inline(always)]
pub fn clr(&self) -> CLR_R {
CLR_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Timer single shot"]
#[inline(always)]
pub fn ss(&self) -> SS_R {
SS_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Timer interrupt"]
#[inline(always)]
pub fn int(&self) -> INT_R {
INT_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Timer interrupt enable"]
#[inline(always)]
pub fn inten(&self) -> INTEN_R {
INTEN_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:8 - timer clock divider"]
#[inline(always)]
pub fn clkdiv(&self) -> CLKDIV_R {
CLKDIV_R::new(((self.bits >> 6) & 7) as u8)
}
#[doc = "Bit 9 - timer clock input source"]
#[inline(always)]
pub fn clk(&self) -> CLK_R {
CLK_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:11 - timer mode"]
#[inline(always)]
pub fn mode(&self) -> MODE_R {
MODE_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bit 13 - DTG clock select"]
#[inline(always)]
pub fn dtgclk(&self) -> DTGCLK_R {
DTGCLK_R::new(((self.bits >> 13) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxCTL")
.field("prdl", &self.prdl())
.field("clr", &self.clr())
.field("ss", &self.ss())
.field("int", &self.int())
.field("inten", &self.inten())
.field("clkdiv", &self.clkdiv())
.field("clk", &self.clk())
.field("mode", &self.mode())
.field("dtgclk", &self.dtgclk())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Timer Period Latch"]
#[inline(always)]
pub fn prdl(&mut self) -> PRDL_W<TX_CTLrs> {
PRDL_W::new(self, 0)
}
#[doc = "Bit 2 - Timer clear"]
#[inline(always)]
pub fn clr(&mut self) -> CLR_W<TX_CTLrs> {
CLR_W::new(self, 2)
}
#[doc = "Bit 3 - Timer single shot"]
#[inline(always)]
pub fn ss(&mut self) -> SS_W<TX_CTLrs> {
SS_W::new(self, 3)
}
#[doc = "Bit 4 - Timer interrupt"]
#[inline(always)]
pub fn int(&mut self) -> INT_W<TX_CTLrs> {
INT_W::new(self, 4)
}
#[doc = "Bit 5 - Timer interrupt enable"]
#[inline(always)]
pub fn inten(&mut self) -> INTEN_W<TX_CTLrs> {
INTEN_W::new(self, 5)
}
#[doc = "Bits 6:8 - timer clock divider"]
#[inline(always)]
pub fn clkdiv(&mut self) -> CLKDIV_W<TX_CTLrs> {
CLKDIV_W::new(self, 6)
}
#[doc = "Bit 9 - timer clock input source"]
#[inline(always)]
pub fn clk(&mut self) -> CLK_W<TX_CTLrs> {
CLK_W::new(self, 9)
}
#[doc = "Bits 10:11 - timer mode"]
#[inline(always)]
pub fn mode(&mut self) -> MODE_W<TX_CTLrs> {
MODE_W::new(self, 10)
}
#[doc = "Bit 13 - DTG clock select"]
#[inline(always)]
pub fn dtgclk(&mut self) -> DTGCLK_W<TX_CTLrs> {
DTGCLK_W::new(self, 13)
}
}
#[doc = "Timer Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_CTLrs;
impl crate::RegisterSpec for TX_CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_ctl::R`](R) reader structure"]
impl crate::Readable for TX_CTLrs {}
#[doc = "`write(|w| ..)` method takes [`tx_ctl::W`](W) writer structure"]
impl crate::Writable for TX_CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TxCTL to value 0"]
impl crate::Resettable for TX_CTLrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TxPRD (rw) register accessor: timer period\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_prd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_prd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_prd`]
module"]
#[doc(alias = "TxPRD")]
pub type TX_PRD = crate::Reg<tx_prd::TX_PRDrs>;
#[doc = "timer period"]
pub mod tx_prd {
#[doc = "Register `TxPRD` reader"]
pub type R = crate::R<TX_PRDrs>;
#[doc = "Register `TxPRD` writer"]
pub type W = crate::W<TX_PRDrs>;
#[doc = "Field `PERIOD` reader - timer period value"]
pub type PERIOD_R = crate::FieldReader<u16>;
#[doc = "Field `PERIOD` writer - timer period value"]
pub type PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - timer period value"]
#[inline(always)]
pub fn period(&self) -> PERIOD_R {
PERIOD_R::new((self.bits & 0xffff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxPRD")
.field("period", &self.period())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - timer period value"]
#[inline(always)]
pub fn period(&mut self) -> PERIOD_W<TX_PRDrs> {
PERIOD_W::new(self, 0)
}
}
#[doc = "timer period\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_prd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_prd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_PRDrs;
impl crate::RegisterSpec for TX_PRDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_prd::R`](R) reader structure"]
impl crate::Readable for TX_PRDrs {}
#[doc = "`write(|w| ..)` method takes [`tx_prd::W`](W) writer structure"]
impl crate::Writable for TX_PRDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TxPRD to value 0"]
impl crate::Resettable for TX_PRDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TxCTR (r) register accessor: timer counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_ctr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_ctr`]
module"]
#[doc(alias = "TxCTR")]
pub type TX_CTR = crate::Reg<tx_ctr::TX_CTRrs>;
#[doc = "timer counter"]
pub mod tx_ctr {
#[doc = "Register `TxCTR` reader"]
pub type R = crate::R<TX_CTRrs>;
#[doc = "Field `CTR` reader - timer counter value"]
pub type CTR_R = crate::FieldReader<u16>;
impl R {
#[doc = "Bits 0:15 - timer counter value"]
#[inline(always)]
pub fn ctr(&self) -> CTR_R {
CTR_R::new((self.bits & 0xffff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxCTR").field("ctr", &self.ctr()).finish()
}
}
#[doc = "timer counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_ctr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_CTRrs;
impl crate::RegisterSpec for TX_CTRrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_ctr::R`](R) reader structure"]
impl crate::Readable for TX_CTRrs {}
#[doc = "`reset()` method sets TxCTR to value 0"]
impl crate::Resettable for TX_CTRrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TxCC0CTL (rw) register accessor: timer capture and compare control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc0ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc0ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_cc0ctl`]
module"]
#[doc(alias = "TxCC0CTL")]
pub type TX_CC0CTL = crate::Reg<tx_cc0ctl::TX_CC0CTLrs>;
#[doc = "timer capture and compare control unit 0"]
pub mod tx_cc0ctl {
#[doc = "Register `TxCC0CTL` reader"]
pub type R = crate::R<TX_CC0CTLrs>;
#[doc = "Register `TxCC0CTL` writer"]
pub type W = crate::W<TX_CC0CTLrs>;
#[doc = "capture mode edge detect\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum CCEDG {
#[doc = "0: high to low transition only"]
Hitolow = 0,
#[doc = "1: low to high transitions only"]
Lowtohigh = 1,
#[doc = "2: both high to low and low to high transitions"]
Both = 2,
}
impl From<CCEDG> for u8 {
#[inline(always)]
fn from(variant: CCEDG) -> Self {
variant as _
}
}
impl crate::FieldSpec for CCEDG {
type Ux = u8;
}
impl crate::IsEnum for CCEDG {}
#[doc = "Field `CCEDG` reader - capture mode edge detect"]
pub type CCEDG_R = crate::FieldReader<CCEDG>;
impl CCEDG_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<CCEDG> {
match self.bits {
0 => Some(CCEDG::Hitolow),
1 => Some(CCEDG::Lowtohigh),
2 => Some(CCEDG::Both),
_ => None,
}
}
#[doc = "high to low transition only"]
#[inline(always)]
pub fn is_hitolow(&self) -> bool {
*self == CCEDG::Hitolow
}
#[doc = "low to high transitions only"]
#[inline(always)]
pub fn is_lowtohigh(&self) -> bool {
*self == CCEDG::Lowtohigh
}
#[doc = "both high to low and low to high transitions"]
#[inline(always)]
pub fn is_both(&self) -> bool {
*self == CCEDG::Both
}
}
#[doc = "Field `CCEDG` writer - capture mode edge detect"]
pub type CCEDG_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CCEDG>;
impl<'a, REG> CCEDG_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "high to low transition only"]
#[inline(always)]
pub fn hitolow(self) -> &'a mut crate::W<REG> {
self.variant(CCEDG::Hitolow)
}
#[doc = "low to high transitions only"]
#[inline(always)]
pub fn lowtohigh(self) -> &'a mut crate::W<REG> {
self.variant(CCEDG::Lowtohigh)
}
#[doc = "both high to low and low to high transitions"]
#[inline(always)]
pub fn both(self) -> &'a mut crate::W<REG> {
self.variant(CCEDG::Both)
}
}
#[doc = "capture and compare interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CCINT {
#[doc = "0: no interrupt detected"]
None = 0,
#[doc = "1: interrupt, write 1b to clear"]
Interrupt = 1,
}
impl From<CCINT> for bool {
#[inline(always)]
fn from(variant: CCINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCINT` reader - capture and compare interrupt"]
pub type CCINT_R = crate::BitReader<CCINT>;
impl CCINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CCINT {
match self.bits {
false => CCINT::None,
true => CCINT::Interrupt,
}
}
#[doc = "no interrupt detected"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == CCINT::None
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == CCINT::Interrupt
}
}
#[doc = "Field `CCINT` writer - capture and compare interrupt"]
pub type CCINT_W<'a, REG> = crate::BitWriter<'a, REG, CCINT>;
impl<'a, REG> CCINT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "no interrupt detected"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(CCINT::None)
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(CCINT::Interrupt)
}
}
#[doc = "capture and compare interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CCINTEN {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<CCINTEN> for bool {
#[inline(always)]
fn from(variant: CCINTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCINTEN` reader - capture and compare interrupt enable"]
pub type CCINTEN_R = crate::BitReader<CCINTEN>;
impl CCINTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CCINTEN {
match self.bits {
false => CCINTEN::Disabled,
true => CCINTEN::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == CCINTEN::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == CCINTEN::Enabled
}
}
#[doc = "Field `CCINTEN` writer - capture and compare interrupt enable"]
pub type CCINTEN_W<'a, REG> = crate::BitWriter<'a, REG, CCINTEN>;
impl<'a, REG> CCINTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(CCINTEN::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(CCINTEN::Enabled)
}
}
#[doc = "capture and compare mode\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CCMODE {
#[doc = "0: compare mode"]
CompareMode = 0,
#[doc = "1: capture mode"]
CaptureMode = 1,
}
impl From<CCMODE> for bool {
#[inline(always)]
fn from(variant: CCMODE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCMODE` reader - capture and compare mode"]
pub type CCMODE_R = crate::BitReader<CCMODE>;
impl CCMODE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CCMODE {
match self.bits {
false => CCMODE::CompareMode,
true => CCMODE::CaptureMode,
}
}
#[doc = "compare mode"]
#[inline(always)]
pub fn is_compare_mode(&self) -> bool {
*self == CCMODE::CompareMode
}
#[doc = "capture mode"]
#[inline(always)]
pub fn is_capture_mode(&self) -> bool {
*self == CCMODE::CaptureMode
}
}
#[doc = "Field `CCMODE` writer - capture and compare mode"]
pub type CCMODE_W<'a, REG> = crate::BitWriter<'a, REG, CCMODE>;
impl<'a, REG> CCMODE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "compare mode"]
#[inline(always)]
pub fn compare_mode(self) -> &'a mut crate::W<REG> {
self.variant(CCMODE::CompareMode)
}
#[doc = "capture mode"]
#[inline(always)]
pub fn capture_mode(self) -> &'a mut crate::W<REG> {
self.variant(CCMODE::CaptureMode)
}
}
impl R {
#[doc = "Bits 0:1 - capture mode edge detect"]
#[inline(always)]
pub fn ccedg(&self) -> CCEDG_R {
CCEDG_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - capture and compare interrupt"]
#[inline(always)]
pub fn ccint(&self) -> CCINT_R {
CCINT_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - capture and compare interrupt enable"]
#[inline(always)]
pub fn ccinten(&self) -> CCINTEN_R {
CCINTEN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - capture and compare mode"]
#[inline(always)]
pub fn ccmode(&self) -> CCMODE_R {
CCMODE_R::new(((self.bits >> 4) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxCC0CTL")
.field("ccedg", &self.ccedg())
.field("ccint", &self.ccint())
.field("ccinten", &self.ccinten())
.field("ccmode", &self.ccmode())
.finish()
}
}
impl W {
#[doc = "Bits 0:1 - capture mode edge detect"]
#[inline(always)]
pub fn ccedg(&mut self) -> CCEDG_W<TX_CC0CTLrs> {
CCEDG_W::new(self, 0)
}
#[doc = "Bit 2 - capture and compare interrupt"]
#[inline(always)]
pub fn ccint(&mut self) -> CCINT_W<TX_CC0CTLrs> {
CCINT_W::new(self, 2)
}
#[doc = "Bit 3 - capture and compare interrupt enable"]
#[inline(always)]
pub fn ccinten(&mut self) -> CCINTEN_W<TX_CC0CTLrs> {
CCINTEN_W::new(self, 3)
}
#[doc = "Bit 4 - capture and compare mode"]
#[inline(always)]
pub fn ccmode(&mut self) -> CCMODE_W<TX_CC0CTLrs> {
CCMODE_W::new(self, 4)
}
}
#[doc = "timer capture and compare control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc0ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc0ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_CC0CTLrs;
impl crate::RegisterSpec for TX_CC0CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_cc0ctl::R`](R) reader structure"]
impl crate::Readable for TX_CC0CTLrs {}
#[doc = "`write(|w| ..)` method takes [`tx_cc0ctl::W`](W) writer structure"]
impl crate::Writable for TX_CC0CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TxCC0CTL to value 0"]
impl crate::Resettable for TX_CC0CTLrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TxCC0CTR (rw) register accessor: capture and compare counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc0ctr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc0ctr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_cc0ctr`]
module"]
#[doc(alias = "TxCC0CTR")]
pub type TX_CC0CTR = crate::Reg<tx_cc0ctr::TX_CC0CTRrs>;
#[doc = "capture and compare counter unit 0"]
pub mod tx_cc0ctr {
#[doc = "Register `TxCC0CTR` reader"]
pub type R = crate::R<TX_CC0CTRrs>;
#[doc = "Register `TxCC0CTR` writer"]
pub type W = crate::W<TX_CC0CTRrs>;
#[doc = "Field `CCCTR` reader - capture and compare counter value"]
pub type CCCTR_R = crate::FieldReader<u16>;
#[doc = "Field `CCCTR` writer - capture and compare counter value"]
pub type CCCTR_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - capture and compare counter value"]
#[inline(always)]
pub fn ccctr(&self) -> CCCTR_R {
CCCTR_R::new((self.bits & 0xffff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxCC0CTR")
.field("ccctr", &self.ccctr())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - capture and compare counter value"]
#[inline(always)]
pub fn ccctr(&mut self) -> CCCTR_W<TX_CC0CTRrs> {
CCCTR_W::new(self, 0)
}
}
#[doc = "capture and compare counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc0ctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc0ctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_CC0CTRrs;
impl crate::RegisterSpec for TX_CC0CTRrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_cc0ctr::R`](R) reader structure"]
impl crate::Readable for TX_CC0CTRrs {}
#[doc = "`write(|w| ..)` method takes [`tx_cc0ctr::W`](W) writer structure"]
impl crate::Writable for TX_CC0CTRrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TxCC0CTR to value 0"]
impl crate::Resettable for TX_CC0CTRrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TxCC1CTL (rw) register accessor: timer capture and compare control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc1ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc1ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_cc1ctl`]
module"]
#[doc(alias = "TxCC1CTL")]
pub type TX_CC1CTL = crate::Reg<tx_cc1ctl::TX_CC1CTLrs>;
#[doc = "timer capture and compare control unit 0"]
pub mod tx_cc1ctl {
#[doc = "Register `TxCC1CTL` reader"]
pub type R = crate::R<TX_CC1CTLrs>;
#[doc = "Register `TxCC1CTL` writer"]
pub type W = crate::W<TX_CC1CTLrs>;
#[doc = "capture mode edge detect\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum CCEDG {
#[doc = "0: high to low transition only"]
Hitolow = 0,
#[doc = "1: low to high transitions only"]
Lowtohigh = 1,
#[doc = "2: both high to low and low to high transitions"]
Both = 2,
}
impl From<CCEDG> for u8 {
#[inline(always)]
fn from(variant: CCEDG) -> Self {
variant as _
}
}
impl crate::FieldSpec for CCEDG {
type Ux = u8;
}
impl crate::IsEnum for CCEDG {}
#[doc = "Field `CCEDG` reader - capture mode edge detect"]
pub type CCEDG_R = crate::FieldReader<CCEDG>;
impl CCEDG_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<CCEDG> {
match self.bits {
0 => Some(CCEDG::Hitolow),
1 => Some(CCEDG::Lowtohigh),
2 => Some(CCEDG::Both),
_ => None,
}
}
#[doc = "high to low transition only"]
#[inline(always)]
pub fn is_hitolow(&self) -> bool {
*self == CCEDG::Hitolow
}
#[doc = "low to high transitions only"]
#[inline(always)]
pub fn is_lowtohigh(&self) -> bool {
*self == CCEDG::Lowtohigh
}
#[doc = "both high to low and low to high transitions"]
#[inline(always)]
pub fn is_both(&self) -> bool {
*self == CCEDG::Both
}
}
#[doc = "Field `CCEDG` writer - capture mode edge detect"]
pub type CCEDG_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CCEDG>;
impl<'a, REG> CCEDG_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "high to low transition only"]
#[inline(always)]
pub fn hitolow(self) -> &'a mut crate::W<REG> {
self.variant(CCEDG::Hitolow)
}
#[doc = "low to high transitions only"]
#[inline(always)]
pub fn lowtohigh(self) -> &'a mut crate::W<REG> {
self.variant(CCEDG::Lowtohigh)
}
#[doc = "both high to low and low to high transitions"]
#[inline(always)]
pub fn both(self) -> &'a mut crate::W<REG> {
self.variant(CCEDG::Both)
}
}
#[doc = "capture and compare interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CCINT {
#[doc = "0: no interrupt detected"]
None = 0,
#[doc = "1: interrupt, write 1b to clear"]
Interrupt = 1,
}
impl From<CCINT> for bool {
#[inline(always)]
fn from(variant: CCINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCINT` reader - capture and compare interrupt"]
pub type CCINT_R = crate::BitReader<CCINT>;
impl CCINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CCINT {
match self.bits {
false => CCINT::None,
true => CCINT::Interrupt,
}
}
#[doc = "no interrupt detected"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == CCINT::None
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == CCINT::Interrupt
}
}
#[doc = "Field `CCINT` writer - capture and compare interrupt"]
pub type CCINT_W<'a, REG> = crate::BitWriter<'a, REG, CCINT>;
impl<'a, REG> CCINT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "no interrupt detected"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(CCINT::None)
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(CCINT::Interrupt)
}
}
#[doc = "capture and compare interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CCINTEN {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<CCINTEN> for bool {
#[inline(always)]
fn from(variant: CCINTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCINTEN` reader - capture and compare interrupt enable"]
pub type CCINTEN_R = crate::BitReader<CCINTEN>;
impl CCINTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CCINTEN {
match self.bits {
false => CCINTEN::Disabled,
true => CCINTEN::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == CCINTEN::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == CCINTEN::Enabled
}
}
#[doc = "Field `CCINTEN` writer - capture and compare interrupt enable"]
pub type CCINTEN_W<'a, REG> = crate::BitWriter<'a, REG, CCINTEN>;
impl<'a, REG> CCINTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(CCINTEN::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(CCINTEN::Enabled)
}
}
#[doc = "capture and compare mode\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CCMODE {
#[doc = "0: compare mode"]
CompareMode = 0,
#[doc = "1: capture mode"]
CaptureMode = 1,
}
impl From<CCMODE> for bool {
#[inline(always)]
fn from(variant: CCMODE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCMODE` reader - capture and compare mode"]
pub type CCMODE_R = crate::BitReader<CCMODE>;
impl CCMODE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CCMODE {
match self.bits {
false => CCMODE::CompareMode,
true => CCMODE::CaptureMode,
}
}
#[doc = "compare mode"]
#[inline(always)]
pub fn is_compare_mode(&self) -> bool {
*self == CCMODE::CompareMode
}
#[doc = "capture mode"]
#[inline(always)]
pub fn is_capture_mode(&self) -> bool {
*self == CCMODE::CaptureMode
}
}
#[doc = "Field `CCMODE` writer - capture and compare mode"]
pub type CCMODE_W<'a, REG> = crate::BitWriter<'a, REG, CCMODE>;
impl<'a, REG> CCMODE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "compare mode"]
#[inline(always)]
pub fn compare_mode(self) -> &'a mut crate::W<REG> {
self.variant(CCMODE::CompareMode)
}
#[doc = "capture mode"]
#[inline(always)]
pub fn capture_mode(self) -> &'a mut crate::W<REG> {
self.variant(CCMODE::CaptureMode)
}
}
impl R {
#[doc = "Bits 0:1 - capture mode edge detect"]
#[inline(always)]
pub fn ccedg(&self) -> CCEDG_R {
CCEDG_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - capture and compare interrupt"]
#[inline(always)]
pub fn ccint(&self) -> CCINT_R {
CCINT_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - capture and compare interrupt enable"]
#[inline(always)]
pub fn ccinten(&self) -> CCINTEN_R {
CCINTEN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - capture and compare mode"]
#[inline(always)]
pub fn ccmode(&self) -> CCMODE_R {
CCMODE_R::new(((self.bits >> 4) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxCC1CTL")
.field("ccedg", &self.ccedg())
.field("ccint", &self.ccint())
.field("ccinten", &self.ccinten())
.field("ccmode", &self.ccmode())
.finish()
}
}
impl W {
#[doc = "Bits 0:1 - capture mode edge detect"]
#[inline(always)]
pub fn ccedg(&mut self) -> CCEDG_W<TX_CC1CTLrs> {
CCEDG_W::new(self, 0)
}
#[doc = "Bit 2 - capture and compare interrupt"]
#[inline(always)]
pub fn ccint(&mut self) -> CCINT_W<TX_CC1CTLrs> {
CCINT_W::new(self, 2)
}
#[doc = "Bit 3 - capture and compare interrupt enable"]
#[inline(always)]
pub fn ccinten(&mut self) -> CCINTEN_W<TX_CC1CTLrs> {
CCINTEN_W::new(self, 3)
}
#[doc = "Bit 4 - capture and compare mode"]
#[inline(always)]
pub fn ccmode(&mut self) -> CCMODE_W<TX_CC1CTLrs> {
CCMODE_W::new(self, 4)
}
}
#[doc = "timer capture and compare control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc1ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc1ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_CC1CTLrs;
impl crate::RegisterSpec for TX_CC1CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_cc1ctl::R`](R) reader structure"]
impl crate::Readable for TX_CC1CTLrs {}
#[doc = "`write(|w| ..)` method takes [`tx_cc1ctl::W`](W) writer structure"]
impl crate::Writable for TX_CC1CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TxCC1CTL to value 0"]
impl crate::Resettable for TX_CC1CTLrs {
const RESET_VALUE: u32 = 0;
}
}
pub use tx_cc0ctl as tx_cc2ctl;
pub use tx_cc0ctl as tx_cc3ctl;
pub use tx_cc0ctl as tx_cc4ctl;
pub use tx_cc0ctl as tx_cc5ctl;
pub use tx_cc0ctl as tx_cc6ctl;
pub use tx_cc0ctl as tx_cc7ctl;
pub use tx_cc0ctr as tx_cc1ctr;
pub use tx_cc0ctr as tx_cc2ctr;
pub use tx_cc0ctr as tx_cc3ctr;
pub use tx_cc0ctr as tx_cc4ctr;
pub use tx_cc0ctr as tx_cc5ctr;
pub use tx_cc0ctr as tx_cc6ctr;
pub use tx_cc0ctr as tx_cc7ctr;
pub use TX_CC0CTL as TX_CC2CTL;
pub use TX_CC0CTL as TX_CC3CTL;
pub use TX_CC0CTL as TX_CC4CTL;
pub use TX_CC0CTL as TX_CC5CTL;
pub use TX_CC0CTL as TX_CC6CTL;
pub use TX_CC0CTL as TX_CC7CTL;
pub use TX_CC0CTR as TX_CC1CTR;
pub use TX_CC0CTR as TX_CC2CTR;
pub use TX_CC0CTR as TX_CC3CTR;
pub use TX_CC0CTR as TX_CC4CTR;
pub use TX_CC0CTR as TX_CC5CTR;
pub use TX_CC0CTR as TX_CC6CTR;
pub use TX_CC0CTR as TX_CC7CTR;
#[doc = "DTGA0CTL (rw) register accessor: Timer A dead-time generator control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga0ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga0ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtga0ctl`]
module"]
pub type DTGA0CTL = crate::Reg<dtga0ctl::DTGA0CTLrs>;
#[doc = "Timer A dead-time generator control unit 0"]
pub mod dtga0ctl {
#[doc = "Register `DTGA0CTL` reader"]
pub type R = crate::R<DTGA0CTLrs>;
#[doc = "Register `DTGA0CTL` writer"]
pub type W = crate::W<DTGA0CTLrs>;
#[doc = "Invert low-side output signal\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INVLS {
#[doc = "0: do not invert low-side output signal"]
Disabled = 0,
#[doc = "1: invert low-side output signal"]
Enabled = 1,
}
impl From<INVLS> for bool {
#[inline(always)]
fn from(variant: INVLS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INVLS` reader - Invert low-side output signal"]
pub type INVLS_R = crate::BitReader<INVLS>;
impl INVLS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INVLS {
match self.bits {
false => INVLS::Disabled,
true => INVLS::Enabled,
}
}
#[doc = "do not invert low-side output signal"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INVLS::Disabled
}
#[doc = "invert low-side output signal"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INVLS::Enabled
}
}
#[doc = "Field `INVLS` writer - Invert low-side output signal"]
pub type INVLS_W<'a, REG> = crate::BitWriter<'a, REG, INVLS>;
impl<'a, REG> INVLS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not invert low-side output signal"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INVLS::Disabled)
}
#[doc = "invert low-side output signal"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INVLS::Enabled)
}
}
#[doc = "Invert high-side output signal\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INVHS {
#[doc = "0: do not invert high-side output signal"]
Disabled = 0,
#[doc = "1: invert high-side output signal"]
Enabled = 1,
}
impl From<INVHS> for bool {
#[inline(always)]
fn from(variant: INVHS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INVHS` reader - Invert high-side output signal"]
pub type INVHS_R = crate::BitReader<INVHS>;
impl INVHS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INVHS {
match self.bits {
false => INVHS::Disabled,
true => INVHS::Enabled,
}
}
#[doc = "do not invert high-side output signal"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INVHS::Disabled
}
#[doc = "invert high-side output signal"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INVHS::Enabled
}
}
#[doc = "Field `INVHS` writer - Invert high-side output signal"]
pub type INVHS_W<'a, REG> = crate::BitWriter<'a, REG, INVHS>;
impl<'a, REG> INVHS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not invert high-side output signal"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INVHS::Disabled)
}
#[doc = "invert high-side output signal"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INVHS::Enabled)
}
}
#[doc = "On-time preservation\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum OTP {
#[doc = "0: do not extend on time"]
Disabled = 0,
#[doc = "1: extend on time"]
Enabled = 1,
}
impl From<OTP> for bool {
#[inline(always)]
fn from(variant: OTP) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OTP` reader - On-time preservation"]
pub type OTP_R = crate::BitReader<OTP>;
impl OTP_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> OTP {
match self.bits {
false => OTP::Disabled,
true => OTP::Enabled,
}
}
#[doc = "do not extend on time"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == OTP::Disabled
}
#[doc = "extend on time"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == OTP::Enabled
}
}
#[doc = "Field `OTP` writer - On-time preservation"]
pub type OTP_W<'a, REG> = crate::BitWriter<'a, REG, OTP>;
impl<'a, REG> OTP_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not extend on time"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(OTP::Disabled)
}
#[doc = "extend on time"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(OTP::Enabled)
}
}
#[doc = "bypass dead-time generation\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum BYPASS {
#[doc = "0: do not bypass dead-time generation"]
Disabled = 0,
#[doc = "1: bypass dead-time generation"]
Enabled = 1,
}
impl From<BYPASS> for bool {
#[inline(always)]
fn from(variant: BYPASS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `BYPASS` reader - bypass dead-time generation"]
pub type BYPASS_R = crate::BitReader<BYPASS>;
impl BYPASS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> BYPASS {
match self.bits {
false => BYPASS::Disabled,
true => BYPASS::Enabled,
}
}
#[doc = "do not bypass dead-time generation"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == BYPASS::Disabled
}
#[doc = "bypass dead-time generation"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == BYPASS::Enabled
}
}
#[doc = "Field `BYPASS` writer - bypass dead-time generation"]
pub type BYPASS_W<'a, REG> = crate::BitWriter<'a, REG, BYPASS>;
impl<'a, REG> BYPASS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not bypass dead-time generation"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(BYPASS::Disabled)
}
#[doc = "bypass dead-time generation"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(BYPASS::Enabled)
}
}
impl R {
#[doc = "Bit 4 - Invert low-side output signal"]
#[inline(always)]
pub fn invls(&self) -> INVLS_R {
INVLS_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Invert high-side output signal"]
#[inline(always)]
pub fn invhs(&self) -> INVHS_R {
INVHS_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - On-time preservation"]
#[inline(always)]
pub fn otp(&self) -> OTP_R {
OTP_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - bypass dead-time generation"]
#[inline(always)]
pub fn bypass(&self) -> BYPASS_R {
BYPASS_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGA0CTL")
.field("invls", &self.invls())
.field("invhs", &self.invhs())
.field("otp", &self.otp())
.field("bypass", &self.bypass())
.finish()
}
}
impl W {
#[doc = "Bit 4 - Invert low-side output signal"]
#[inline(always)]
pub fn invls(&mut self) -> INVLS_W<DTGA0CTLrs> {
INVLS_W::new(self, 4)
}
#[doc = "Bit 5 - Invert high-side output signal"]
#[inline(always)]
pub fn invhs(&mut self) -> INVHS_W<DTGA0CTLrs> {
INVHS_W::new(self, 5)
}
#[doc = "Bit 6 - On-time preservation"]
#[inline(always)]
pub fn otp(&mut self) -> OTP_W<DTGA0CTLrs> {
OTP_W::new(self, 6)
}
#[doc = "Bit 7 - bypass dead-time generation"]
#[inline(always)]
pub fn bypass(&mut self) -> BYPASS_W<DTGA0CTLrs> {
BYPASS_W::new(self, 7)
}
}
#[doc = "Timer A dead-time generator control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga0ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga0ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGA0CTLrs;
impl crate::RegisterSpec for DTGA0CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtga0ctl::R`](R) reader structure"]
impl crate::Readable for DTGA0CTLrs {}
#[doc = "`write(|w| ..)` method takes [`dtga0ctl::W`](W) writer structure"]
impl crate::Writable for DTGA0CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGA0CTL to value 0x80"]
impl crate::Resettable for DTGA0CTLrs {
const RESET_VALUE: u32 = 0x80;
}
}
#[doc = "DTGA0LED (rw) register accessor: Timer A dead-time generator leading-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga0led::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga0led::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtga0led`]
module"]
pub type DTGA0LED = crate::Reg<dtga0led::DTGA0LEDrs>;
#[doc = "Timer A dead-time generator leading-edge delay counter unit 0"]
pub mod dtga0led {
#[doc = "Register `DTGA0LED` reader"]
pub type R = crate::R<DTGA0LEDrs>;
#[doc = "Register `DTGA0LED` writer"]
pub type W = crate::W<DTGA0LEDrs>;
#[doc = "Field `LED` reader - leading-edge delay counter"]
pub type LED_R = crate::FieldReader<u16>;
#[doc = "Field `LED` writer - leading-edge delay counter"]
pub type LED_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:11 - leading-edge delay counter"]
#[inline(always)]
pub fn led(&self) -> LED_R {
LED_R::new((self.bits & 0x0fff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGA0LED")
.field("led", &self.led())
.finish()
}
}
impl W {
#[doc = "Bits 0:11 - leading-edge delay counter"]
#[inline(always)]
pub fn led(&mut self) -> LED_W<DTGA0LEDrs> {
LED_W::new(self, 0)
}
}
#[doc = "Timer A dead-time generator leading-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga0led::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga0led::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGA0LEDrs;
impl crate::RegisterSpec for DTGA0LEDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtga0led::R`](R) reader structure"]
impl crate::Readable for DTGA0LEDrs {}
#[doc = "`write(|w| ..)` method takes [`dtga0led::W`](W) writer structure"]
impl crate::Writable for DTGA0LEDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGA0LED to value 0"]
impl crate::Resettable for DTGA0LEDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DTGA0TED (rw) register accessor: Timer A dead-time generator trailing-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga0ted::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga0ted::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtga0ted`]
module"]
pub type DTGA0TED = crate::Reg<dtga0ted::DTGA0TEDrs>;
#[doc = "Timer A dead-time generator trailing-edge delay counter unit 0"]
pub mod dtga0ted {
#[doc = "Register `DTGA0TED` reader"]
pub type R = crate::R<DTGA0TEDrs>;
#[doc = "Register `DTGA0TED` writer"]
pub type W = crate::W<DTGA0TEDrs>;
#[doc = "Field `TED` reader - trailing-edge delay counter"]
pub type TED_R = crate::FieldReader<u16>;
#[doc = "Field `TED` writer - trailing-edge delay counter"]
pub type TED_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:11 - trailing-edge delay counter"]
#[inline(always)]
pub fn ted(&self) -> TED_R {
TED_R::new((self.bits & 0x0fff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGA0TED")
.field("ted", &self.ted())
.finish()
}
}
impl W {
#[doc = "Bits 0:11 - trailing-edge delay counter"]
#[inline(always)]
pub fn ted(&mut self) -> TED_W<DTGA0TEDrs> {
TED_W::new(self, 0)
}
}
#[doc = "Timer A dead-time generator trailing-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga0ted::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga0ted::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGA0TEDrs;
impl crate::RegisterSpec for DTGA0TEDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtga0ted::R`](R) reader structure"]
impl crate::Readable for DTGA0TEDrs {}
#[doc = "`write(|w| ..)` method takes [`dtga0ted::W`](W) writer structure"]
impl crate::Writable for DTGA0TEDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGA0TED to value 0"]
impl crate::Resettable for DTGA0TEDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DTGA1CTL (rw) register accessor: Timer A dead-time generator control unit 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga1ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga1ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtga1ctl`]
module"]
pub type DTGA1CTL = crate::Reg<dtga1ctl::DTGA1CTLrs>;
#[doc = "Timer A dead-time generator control unit 1"]
pub mod dtga1ctl {
#[doc = "Register `DTGA1CTL` reader"]
pub type R = crate::R<DTGA1CTLrs>;
#[doc = "Register `DTGA1CTL` writer"]
pub type W = crate::W<DTGA1CTLrs>;
#[doc = "Invert low-side output signal\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INVLS {
#[doc = "0: do not invert low-side output signal"]
Disabled = 0,
#[doc = "1: invert low-side output signal"]
Enabled = 1,
}
impl From<INVLS> for bool {
#[inline(always)]
fn from(variant: INVLS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INVLS` reader - Invert low-side output signal"]
pub type INVLS_R = crate::BitReader<INVLS>;
impl INVLS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INVLS {
match self.bits {
false => INVLS::Disabled,
true => INVLS::Enabled,
}
}
#[doc = "do not invert low-side output signal"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INVLS::Disabled
}
#[doc = "invert low-side output signal"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INVLS::Enabled
}
}
#[doc = "Field `INVLS` writer - Invert low-side output signal"]
pub type INVLS_W<'a, REG> = crate::BitWriter<'a, REG, INVLS>;
impl<'a, REG> INVLS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not invert low-side output signal"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INVLS::Disabled)
}
#[doc = "invert low-side output signal"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INVLS::Enabled)
}
}
#[doc = "Invert high-side output signal\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INVHS {
#[doc = "0: do not invert high-side output signal"]
Disabled = 0,
#[doc = "1: invert high-side output signal"]
Enabled = 1,
}
impl From<INVHS> for bool {
#[inline(always)]
fn from(variant: INVHS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INVHS` reader - Invert high-side output signal"]
pub type INVHS_R = crate::BitReader<INVHS>;
impl INVHS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INVHS {
match self.bits {
false => INVHS::Disabled,
true => INVHS::Enabled,
}
}
#[doc = "do not invert high-side output signal"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INVHS::Disabled
}
#[doc = "invert high-side output signal"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INVHS::Enabled
}
}
#[doc = "Field `INVHS` writer - Invert high-side output signal"]
pub type INVHS_W<'a, REG> = crate::BitWriter<'a, REG, INVHS>;
impl<'a, REG> INVHS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not invert high-side output signal"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INVHS::Disabled)
}
#[doc = "invert high-side output signal"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INVHS::Enabled)
}
}
#[doc = "On-time preservation\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum OTP {
#[doc = "0: do not extend on time"]
Disabled = 0,
#[doc = "1: extend on time"]
Enabled = 1,
}
impl From<OTP> for bool {
#[inline(always)]
fn from(variant: OTP) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OTP` reader - On-time preservation"]
pub type OTP_R = crate::BitReader<OTP>;
impl OTP_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> OTP {
match self.bits {
false => OTP::Disabled,
true => OTP::Enabled,
}
}
#[doc = "do not extend on time"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == OTP::Disabled
}
#[doc = "extend on time"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == OTP::Enabled
}
}
#[doc = "Field `OTP` writer - On-time preservation"]
pub type OTP_W<'a, REG> = crate::BitWriter<'a, REG, OTP>;
impl<'a, REG> OTP_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not extend on time"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(OTP::Disabled)
}
#[doc = "extend on time"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(OTP::Enabled)
}
}
#[doc = "bypass dead-time generation\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum BYPASS {
#[doc = "0: do not bypass dead-time generation"]
Disabled = 0,
#[doc = "1: bypass dead-time generation"]
Enabled = 1,
}
impl From<BYPASS> for bool {
#[inline(always)]
fn from(variant: BYPASS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `BYPASS` reader - bypass dead-time generation"]
pub type BYPASS_R = crate::BitReader<BYPASS>;
impl BYPASS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> BYPASS {
match self.bits {
false => BYPASS::Disabled,
true => BYPASS::Enabled,
}
}
#[doc = "do not bypass dead-time generation"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == BYPASS::Disabled
}
#[doc = "bypass dead-time generation"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == BYPASS::Enabled
}
}
#[doc = "Field `BYPASS` writer - bypass dead-time generation"]
pub type BYPASS_W<'a, REG> = crate::BitWriter<'a, REG, BYPASS>;
impl<'a, REG> BYPASS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not bypass dead-time generation"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(BYPASS::Disabled)
}
#[doc = "bypass dead-time generation"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(BYPASS::Enabled)
}
}
impl R {
#[doc = "Bit 4 - Invert low-side output signal"]
#[inline(always)]
pub fn invls(&self) -> INVLS_R {
INVLS_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Invert high-side output signal"]
#[inline(always)]
pub fn invhs(&self) -> INVHS_R {
INVHS_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - On-time preservation"]
#[inline(always)]
pub fn otp(&self) -> OTP_R {
OTP_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - bypass dead-time generation"]
#[inline(always)]
pub fn bypass(&self) -> BYPASS_R {
BYPASS_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGA1CTL")
.field("invls", &self.invls())
.field("invhs", &self.invhs())
.field("otp", &self.otp())
.field("bypass", &self.bypass())
.finish()
}
}
impl W {
#[doc = "Bit 4 - Invert low-side output signal"]
#[inline(always)]
pub fn invls(&mut self) -> INVLS_W<DTGA1CTLrs> {
INVLS_W::new(self, 4)
}
#[doc = "Bit 5 - Invert high-side output signal"]
#[inline(always)]
pub fn invhs(&mut self) -> INVHS_W<DTGA1CTLrs> {
INVHS_W::new(self, 5)
}
#[doc = "Bit 6 - On-time preservation"]
#[inline(always)]
pub fn otp(&mut self) -> OTP_W<DTGA1CTLrs> {
OTP_W::new(self, 6)
}
#[doc = "Bit 7 - bypass dead-time generation"]
#[inline(always)]
pub fn bypass(&mut self) -> BYPASS_W<DTGA1CTLrs> {
BYPASS_W::new(self, 7)
}
}
#[doc = "Timer A dead-time generator control unit 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga1ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga1ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGA1CTLrs;
impl crate::RegisterSpec for DTGA1CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtga1ctl::R`](R) reader structure"]
impl crate::Readable for DTGA1CTLrs {}
#[doc = "`write(|w| ..)` method takes [`dtga1ctl::W`](W) writer structure"]
impl crate::Writable for DTGA1CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGA1CTL to value 0x80"]
impl crate::Resettable for DTGA1CTLrs {
const RESET_VALUE: u32 = 0x80;
}
}
#[doc = "DTGA1LED (rw) register accessor: Timer A dead-time generator leading-edge delay counter unit 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga1led::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga1led::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtga1led`]
module"]
pub type DTGA1LED = crate::Reg<dtga1led::DTGA1LEDrs>;
#[doc = "Timer A dead-time generator leading-edge delay counter unit 1"]
pub mod dtga1led {
#[doc = "Register `DTGA1LED` reader"]
pub type R = crate::R<DTGA1LEDrs>;
#[doc = "Register `DTGA1LED` writer"]
pub type W = crate::W<DTGA1LEDrs>;
#[doc = "Field `LED` reader - leading-edge delay counter"]
pub type LED_R = crate::FieldReader<u16>;
#[doc = "Field `LED` writer - leading-edge delay counter"]
pub type LED_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:11 - leading-edge delay counter"]
#[inline(always)]
pub fn led(&self) -> LED_R {
LED_R::new((self.bits & 0x0fff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGA1LED")
.field("led", &self.led())
.finish()
}
}
impl W {
#[doc = "Bits 0:11 - leading-edge delay counter"]
#[inline(always)]
pub fn led(&mut self) -> LED_W<DTGA1LEDrs> {
LED_W::new(self, 0)
}
}
#[doc = "Timer A dead-time generator leading-edge delay counter unit 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga1led::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga1led::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGA1LEDrs;
impl crate::RegisterSpec for DTGA1LEDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtga1led::R`](R) reader structure"]
impl crate::Readable for DTGA1LEDrs {}
#[doc = "`write(|w| ..)` method takes [`dtga1led::W`](W) writer structure"]
impl crate::Writable for DTGA1LEDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGA1LED to value 0"]
impl crate::Resettable for DTGA1LEDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DTGA1TED (rw) register accessor: Timer A dead-time generator trailing-edge delay counter unit 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga1ted::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga1ted::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtga1ted`]
module"]
pub type DTGA1TED = crate::Reg<dtga1ted::DTGA1TEDrs>;
#[doc = "Timer A dead-time generator trailing-edge delay counter unit 1"]
pub mod dtga1ted {
#[doc = "Register `DTGA1TED` reader"]
pub type R = crate::R<DTGA1TEDrs>;
#[doc = "Register `DTGA1TED` writer"]
pub type W = crate::W<DTGA1TEDrs>;
#[doc = "Field `TED` reader - trailing-edge delay counter"]
pub type TED_R = crate::FieldReader<u16>;
#[doc = "Field `TED` writer - trailing-edge delay counter"]
pub type TED_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:11 - trailing-edge delay counter"]
#[inline(always)]
pub fn ted(&self) -> TED_R {
TED_R::new((self.bits & 0x0fff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGA1TED")
.field("ted", &self.ted())
.finish()
}
}
impl W {
#[doc = "Bits 0:11 - trailing-edge delay counter"]
#[inline(always)]
pub fn ted(&mut self) -> TED_W<DTGA1TEDrs> {
TED_W::new(self, 0)
}
}
#[doc = "Timer A dead-time generator trailing-edge delay counter unit 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga1ted::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga1ted::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGA1TEDrs;
impl crate::RegisterSpec for DTGA1TEDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtga1ted::R`](R) reader structure"]
impl crate::Readable for DTGA1TEDrs {}
#[doc = "`write(|w| ..)` method takes [`dtga1ted::W`](W) writer structure"]
impl crate::Writable for DTGA1TEDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGA1TED to value 0"]
impl crate::Resettable for DTGA1TEDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DTGA2CTL (rw) register accessor: Timer A dead-time generator control unit 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga2ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga2ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtga2ctl`]
module"]
pub type DTGA2CTL = crate::Reg<dtga2ctl::DTGA2CTLrs>;
#[doc = "Timer A dead-time generator control unit 2"]
pub mod dtga2ctl {
#[doc = "Register `DTGA2CTL` reader"]
pub type R = crate::R<DTGA2CTLrs>;
#[doc = "Register `DTGA2CTL` writer"]
pub type W = crate::W<DTGA2CTLrs>;
#[doc = "Invert low-side output signal\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INVLS {
#[doc = "0: do not invert low-side output signal"]
Disabled = 0,
#[doc = "1: invert low-side output signal"]
Enabled = 1,
}
impl From<INVLS> for bool {
#[inline(always)]
fn from(variant: INVLS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INVLS` reader - Invert low-side output signal"]
pub type INVLS_R = crate::BitReader<INVLS>;
impl INVLS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INVLS {
match self.bits {
false => INVLS::Disabled,
true => INVLS::Enabled,
}
}
#[doc = "do not invert low-side output signal"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INVLS::Disabled
}
#[doc = "invert low-side output signal"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INVLS::Enabled
}
}
#[doc = "Field `INVLS` writer - Invert low-side output signal"]
pub type INVLS_W<'a, REG> = crate::BitWriter<'a, REG, INVLS>;
impl<'a, REG> INVLS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not invert low-side output signal"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INVLS::Disabled)
}
#[doc = "invert low-side output signal"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INVLS::Enabled)
}
}
#[doc = "Invert high-side output signal\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INVHS {
#[doc = "0: do not invert high-side output signal"]
Disabled = 0,
#[doc = "1: invert high-side output signal"]
Enabled = 1,
}
impl From<INVHS> for bool {
#[inline(always)]
fn from(variant: INVHS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INVHS` reader - Invert high-side output signal"]
pub type INVHS_R = crate::BitReader<INVHS>;
impl INVHS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INVHS {
match self.bits {
false => INVHS::Disabled,
true => INVHS::Enabled,
}
}
#[doc = "do not invert high-side output signal"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INVHS::Disabled
}
#[doc = "invert high-side output signal"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INVHS::Enabled
}
}
#[doc = "Field `INVHS` writer - Invert high-side output signal"]
pub type INVHS_W<'a, REG> = crate::BitWriter<'a, REG, INVHS>;
impl<'a, REG> INVHS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not invert high-side output signal"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INVHS::Disabled)
}
#[doc = "invert high-side output signal"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INVHS::Enabled)
}
}
#[doc = "On-time preservation\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum OTP {
#[doc = "0: do not extend on time"]
Disabled = 0,
#[doc = "1: extend on time"]
Enabled = 1,
}
impl From<OTP> for bool {
#[inline(always)]
fn from(variant: OTP) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OTP` reader - On-time preservation"]
pub type OTP_R = crate::BitReader<OTP>;
impl OTP_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> OTP {
match self.bits {
false => OTP::Disabled,
true => OTP::Enabled,
}
}
#[doc = "do not extend on time"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == OTP::Disabled
}
#[doc = "extend on time"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == OTP::Enabled
}
}
#[doc = "Field `OTP` writer - On-time preservation"]
pub type OTP_W<'a, REG> = crate::BitWriter<'a, REG, OTP>;
impl<'a, REG> OTP_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not extend on time"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(OTP::Disabled)
}
#[doc = "extend on time"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(OTP::Enabled)
}
}
#[doc = "bypass dead-time generation\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum BYPASS {
#[doc = "0: do not bypass dead-time generation"]
Disabled = 0,
#[doc = "1: bypass dead-time generation"]
Enabled = 1,
}
impl From<BYPASS> for bool {
#[inline(always)]
fn from(variant: BYPASS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `BYPASS` reader - bypass dead-time generation"]
pub type BYPASS_R = crate::BitReader<BYPASS>;
impl BYPASS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> BYPASS {
match self.bits {
false => BYPASS::Disabled,
true => BYPASS::Enabled,
}
}
#[doc = "do not bypass dead-time generation"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == BYPASS::Disabled
}
#[doc = "bypass dead-time generation"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == BYPASS::Enabled
}
}
#[doc = "Field `BYPASS` writer - bypass dead-time generation"]
pub type BYPASS_W<'a, REG> = crate::BitWriter<'a, REG, BYPASS>;
impl<'a, REG> BYPASS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not bypass dead-time generation"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(BYPASS::Disabled)
}
#[doc = "bypass dead-time generation"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(BYPASS::Enabled)
}
}
impl R {
#[doc = "Bit 4 - Invert low-side output signal"]
#[inline(always)]
pub fn invls(&self) -> INVLS_R {
INVLS_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Invert high-side output signal"]
#[inline(always)]
pub fn invhs(&self) -> INVHS_R {
INVHS_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - On-time preservation"]
#[inline(always)]
pub fn otp(&self) -> OTP_R {
OTP_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - bypass dead-time generation"]
#[inline(always)]
pub fn bypass(&self) -> BYPASS_R {
BYPASS_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGA2CTL")
.field("invls", &self.invls())
.field("invhs", &self.invhs())
.field("otp", &self.otp())
.field("bypass", &self.bypass())
.finish()
}
}
impl W {
#[doc = "Bit 4 - Invert low-side output signal"]
#[inline(always)]
pub fn invls(&mut self) -> INVLS_W<DTGA2CTLrs> {
INVLS_W::new(self, 4)
}
#[doc = "Bit 5 - Invert high-side output signal"]
#[inline(always)]
pub fn invhs(&mut self) -> INVHS_W<DTGA2CTLrs> {
INVHS_W::new(self, 5)
}
#[doc = "Bit 6 - On-time preservation"]
#[inline(always)]
pub fn otp(&mut self) -> OTP_W<DTGA2CTLrs> {
OTP_W::new(self, 6)
}
#[doc = "Bit 7 - bypass dead-time generation"]
#[inline(always)]
pub fn bypass(&mut self) -> BYPASS_W<DTGA2CTLrs> {
BYPASS_W::new(self, 7)
}
}
#[doc = "Timer A dead-time generator control unit 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga2ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga2ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGA2CTLrs;
impl crate::RegisterSpec for DTGA2CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtga2ctl::R`](R) reader structure"]
impl crate::Readable for DTGA2CTLrs {}
#[doc = "`write(|w| ..)` method takes [`dtga2ctl::W`](W) writer structure"]
impl crate::Writable for DTGA2CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGA2CTL to value 0x80"]
impl crate::Resettable for DTGA2CTLrs {
const RESET_VALUE: u32 = 0x80;
}
}
#[doc = "DTGA2LED (rw) register accessor: Timer A dead-time generator leading-edge delay counter unit 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga2led::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga2led::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtga2led`]
module"]
pub type DTGA2LED = crate::Reg<dtga2led::DTGA2LEDrs>;
#[doc = "Timer A dead-time generator leading-edge delay counter unit 2"]
pub mod dtga2led {
#[doc = "Register `DTGA2LED` reader"]
pub type R = crate::R<DTGA2LEDrs>;
#[doc = "Register `DTGA2LED` writer"]
pub type W = crate::W<DTGA2LEDrs>;
#[doc = "Field `LED` reader - leading-edge delay counter"]
pub type LED_R = crate::FieldReader<u16>;
#[doc = "Field `LED` writer - leading-edge delay counter"]
pub type LED_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:11 - leading-edge delay counter"]
#[inline(always)]
pub fn led(&self) -> LED_R {
LED_R::new((self.bits & 0x0fff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGA2LED")
.field("led", &self.led())
.finish()
}
}
impl W {
#[doc = "Bits 0:11 - leading-edge delay counter"]
#[inline(always)]
pub fn led(&mut self) -> LED_W<DTGA2LEDrs> {
LED_W::new(self, 0)
}
}
#[doc = "Timer A dead-time generator leading-edge delay counter unit 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga2led::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga2led::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGA2LEDrs;
impl crate::RegisterSpec for DTGA2LEDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtga2led::R`](R) reader structure"]
impl crate::Readable for DTGA2LEDrs {}
#[doc = "`write(|w| ..)` method takes [`dtga2led::W`](W) writer structure"]
impl crate::Writable for DTGA2LEDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGA2LED to value 0"]
impl crate::Resettable for DTGA2LEDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DTGA2TED (rw) register accessor: Timer A dead-time generator trailing-edge delay counter unit 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga2ted::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga2ted::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtga2ted`]
module"]
pub type DTGA2TED = crate::Reg<dtga2ted::DTGA2TEDrs>;
#[doc = "Timer A dead-time generator trailing-edge delay counter unit 2"]
pub mod dtga2ted {
#[doc = "Register `DTGA2TED` reader"]
pub type R = crate::R<DTGA2TEDrs>;
#[doc = "Register `DTGA2TED` writer"]
pub type W = crate::W<DTGA2TEDrs>;
#[doc = "Field `TED` reader - trailing-edge delay counter"]
pub type TED_R = crate::FieldReader<u16>;
#[doc = "Field `TED` writer - trailing-edge delay counter"]
pub type TED_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:11 - trailing-edge delay counter"]
#[inline(always)]
pub fn ted(&self) -> TED_R {
TED_R::new((self.bits & 0x0fff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGA2TED")
.field("ted", &self.ted())
.finish()
}
}
impl W {
#[doc = "Bits 0:11 - trailing-edge delay counter"]
#[inline(always)]
pub fn ted(&mut self) -> TED_W<DTGA2TEDrs> {
TED_W::new(self, 0)
}
}
#[doc = "Timer A dead-time generator trailing-edge delay counter unit 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga2ted::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga2ted::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGA2TEDrs;
impl crate::RegisterSpec for DTGA2TEDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtga2ted::R`](R) reader structure"]
impl crate::Readable for DTGA2TEDrs {}
#[doc = "`write(|w| ..)` method takes [`dtga2ted::W`](W) writer structure"]
impl crate::Writable for DTGA2TEDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGA2TED to value 0"]
impl crate::Resettable for DTGA2TEDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DTGA3CTL (rw) register accessor: Timer A dead-time generator control unit 3\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga3ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga3ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtga3ctl`]
module"]
pub type DTGA3CTL = crate::Reg<dtga3ctl::DTGA3CTLrs>;
#[doc = "Timer A dead-time generator control unit 3"]
pub mod dtga3ctl {
#[doc = "Register `DTGA3CTL` reader"]
pub type R = crate::R<DTGA3CTLrs>;
#[doc = "Register `DTGA3CTL` writer"]
pub type W = crate::W<DTGA3CTLrs>;
#[doc = "Invert low-side output signal\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INVLS {
#[doc = "0: do not invert low-side output signal"]
Disabled = 0,
#[doc = "1: invert low-side output signal"]
Enabled = 1,
}
impl From<INVLS> for bool {
#[inline(always)]
fn from(variant: INVLS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INVLS` reader - Invert low-side output signal"]
pub type INVLS_R = crate::BitReader<INVLS>;
impl INVLS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INVLS {
match self.bits {
false => INVLS::Disabled,
true => INVLS::Enabled,
}
}
#[doc = "do not invert low-side output signal"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INVLS::Disabled
}
#[doc = "invert low-side output signal"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INVLS::Enabled
}
}
#[doc = "Field `INVLS` writer - Invert low-side output signal"]
pub type INVLS_W<'a, REG> = crate::BitWriter<'a, REG, INVLS>;
impl<'a, REG> INVLS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not invert low-side output signal"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INVLS::Disabled)
}
#[doc = "invert low-side output signal"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INVLS::Enabled)
}
}
#[doc = "Invert high-side output signal\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INVHS {
#[doc = "0: do not invert high-side output signal"]
Disabled = 0,
#[doc = "1: invert high-side output signal"]
Enabled = 1,
}
impl From<INVHS> for bool {
#[inline(always)]
fn from(variant: INVHS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INVHS` reader - Invert high-side output signal"]
pub type INVHS_R = crate::BitReader<INVHS>;
impl INVHS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INVHS {
match self.bits {
false => INVHS::Disabled,
true => INVHS::Enabled,
}
}
#[doc = "do not invert high-side output signal"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INVHS::Disabled
}
#[doc = "invert high-side output signal"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INVHS::Enabled
}
}
#[doc = "Field `INVHS` writer - Invert high-side output signal"]
pub type INVHS_W<'a, REG> = crate::BitWriter<'a, REG, INVHS>;
impl<'a, REG> INVHS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not invert high-side output signal"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INVHS::Disabled)
}
#[doc = "invert high-side output signal"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INVHS::Enabled)
}
}
#[doc = "On-time preservation\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum OTP {
#[doc = "0: do not extend on time"]
Disabled = 0,
#[doc = "1: extend on time"]
Enabled = 1,
}
impl From<OTP> for bool {
#[inline(always)]
fn from(variant: OTP) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OTP` reader - On-time preservation"]
pub type OTP_R = crate::BitReader<OTP>;
impl OTP_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> OTP {
match self.bits {
false => OTP::Disabled,
true => OTP::Enabled,
}
}
#[doc = "do not extend on time"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == OTP::Disabled
}
#[doc = "extend on time"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == OTP::Enabled
}
}
#[doc = "Field `OTP` writer - On-time preservation"]
pub type OTP_W<'a, REG> = crate::BitWriter<'a, REG, OTP>;
impl<'a, REG> OTP_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not extend on time"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(OTP::Disabled)
}
#[doc = "extend on time"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(OTP::Enabled)
}
}
#[doc = "bypass dead-time generation\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum BYPASS {
#[doc = "0: do not bypass dead-time generation"]
Disabled = 0,
#[doc = "1: bypass dead-time generation"]
Enabled = 1,
}
impl From<BYPASS> for bool {
#[inline(always)]
fn from(variant: BYPASS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `BYPASS` reader - bypass dead-time generation"]
pub type BYPASS_R = crate::BitReader<BYPASS>;
impl BYPASS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> BYPASS {
match self.bits {
false => BYPASS::Disabled,
true => BYPASS::Enabled,
}
}
#[doc = "do not bypass dead-time generation"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == BYPASS::Disabled
}
#[doc = "bypass dead-time generation"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == BYPASS::Enabled
}
}
#[doc = "Field `BYPASS` writer - bypass dead-time generation"]
pub type BYPASS_W<'a, REG> = crate::BitWriter<'a, REG, BYPASS>;
impl<'a, REG> BYPASS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not bypass dead-time generation"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(BYPASS::Disabled)
}
#[doc = "bypass dead-time generation"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(BYPASS::Enabled)
}
}
impl R {
#[doc = "Bit 4 - Invert low-side output signal"]
#[inline(always)]
pub fn invls(&self) -> INVLS_R {
INVLS_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Invert high-side output signal"]
#[inline(always)]
pub fn invhs(&self) -> INVHS_R {
INVHS_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - On-time preservation"]
#[inline(always)]
pub fn otp(&self) -> OTP_R {
OTP_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - bypass dead-time generation"]
#[inline(always)]
pub fn bypass(&self) -> BYPASS_R {
BYPASS_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGA3CTL")
.field("invls", &self.invls())
.field("invhs", &self.invhs())
.field("otp", &self.otp())
.field("bypass", &self.bypass())
.finish()
}
}
impl W {
#[doc = "Bit 4 - Invert low-side output signal"]
#[inline(always)]
pub fn invls(&mut self) -> INVLS_W<DTGA3CTLrs> {
INVLS_W::new(self, 4)
}
#[doc = "Bit 5 - Invert high-side output signal"]
#[inline(always)]
pub fn invhs(&mut self) -> INVHS_W<DTGA3CTLrs> {
INVHS_W::new(self, 5)
}
#[doc = "Bit 6 - On-time preservation"]
#[inline(always)]
pub fn otp(&mut self) -> OTP_W<DTGA3CTLrs> {
OTP_W::new(self, 6)
}
#[doc = "Bit 7 - bypass dead-time generation"]
#[inline(always)]
pub fn bypass(&mut self) -> BYPASS_W<DTGA3CTLrs> {
BYPASS_W::new(self, 7)
}
}
#[doc = "Timer A dead-time generator control unit 3\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga3ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga3ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGA3CTLrs;
impl crate::RegisterSpec for DTGA3CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtga3ctl::R`](R) reader structure"]
impl crate::Readable for DTGA3CTLrs {}
#[doc = "`write(|w| ..)` method takes [`dtga3ctl::W`](W) writer structure"]
impl crate::Writable for DTGA3CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGA3CTL to value 0x80"]
impl crate::Resettable for DTGA3CTLrs {
const RESET_VALUE: u32 = 0x80;
}
}
#[doc = "DTGA3LED (rw) register accessor: Timer A dead-time generator leading-edge delay counter unit 3\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga3led::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga3led::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtga3led`]
module"]
pub type DTGA3LED = crate::Reg<dtga3led::DTGA3LEDrs>;
#[doc = "Timer A dead-time generator leading-edge delay counter unit 3"]
pub mod dtga3led {
#[doc = "Register `DTGA3LED` reader"]
pub type R = crate::R<DTGA3LEDrs>;
#[doc = "Register `DTGA3LED` writer"]
pub type W = crate::W<DTGA3LEDrs>;
#[doc = "Field `LED` reader - leading-edge delay counter"]
pub type LED_R = crate::FieldReader<u16>;
#[doc = "Field `LED` writer - leading-edge delay counter"]
pub type LED_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:11 - leading-edge delay counter"]
#[inline(always)]
pub fn led(&self) -> LED_R {
LED_R::new((self.bits & 0x0fff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGA3LED")
.field("led", &self.led())
.finish()
}
}
impl W {
#[doc = "Bits 0:11 - leading-edge delay counter"]
#[inline(always)]
pub fn led(&mut self) -> LED_W<DTGA3LEDrs> {
LED_W::new(self, 0)
}
}
#[doc = "Timer A dead-time generator leading-edge delay counter unit 3\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga3led::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga3led::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGA3LEDrs;
impl crate::RegisterSpec for DTGA3LEDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtga3led::R`](R) reader structure"]
impl crate::Readable for DTGA3LEDrs {}
#[doc = "`write(|w| ..)` method takes [`dtga3led::W`](W) writer structure"]
impl crate::Writable for DTGA3LEDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGA3LED to value 0"]
impl crate::Resettable for DTGA3LEDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DTGA3TED (rw) register accessor: Timer A dead-time generator trailing-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga3ted::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga3ted::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtga3ted`]
module"]
pub type DTGA3TED = crate::Reg<dtga3ted::DTGA3TEDrs>;
#[doc = "Timer A dead-time generator trailing-edge delay counter unit 0"]
pub mod dtga3ted {
#[doc = "Register `DTGA3TED` reader"]
pub type R = crate::R<DTGA3TEDrs>;
#[doc = "Register `DTGA3TED` writer"]
pub type W = crate::W<DTGA3TEDrs>;
#[doc = "Field `TED` reader - trailing-edge delay counter"]
pub type TED_R = crate::FieldReader<u16>;
#[doc = "Field `TED` writer - trailing-edge delay counter"]
pub type TED_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:11 - trailing-edge delay counter"]
#[inline(always)]
pub fn ted(&self) -> TED_R {
TED_R::new((self.bits & 0x0fff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGA3TED")
.field("ted", &self.ted())
.finish()
}
}
impl W {
#[doc = "Bits 0:11 - trailing-edge delay counter"]
#[inline(always)]
pub fn ted(&mut self) -> TED_W<DTGA3TEDrs> {
TED_W::new(self, 0)
}
}
#[doc = "Timer A dead-time generator trailing-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtga3ted::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtga3ted::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGA3TEDrs;
impl crate::RegisterSpec for DTGA3TEDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtga3ted::R`](R) reader structure"]
impl crate::Readable for DTGA3TEDrs {}
#[doc = "`write(|w| ..)` method takes [`dtga3ted::W`](W) writer structure"]
impl crate::Writable for DTGA3TEDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGA3TED to value 0"]
impl crate::Resettable for DTGA3TEDrs {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "Timer B Peripheral"]
pub struct TIMERB {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIMERB {}
impl TIMERB {
#[doc = r"Pointer to the register block"]
pub const PTR: *const timerb::RegisterBlock = 0x400e_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const timerb::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for TIMERB {
type Target = timerb::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for TIMERB {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIMERB").finish()
}
}
#[doc = "Timer B Peripheral"]
pub mod timerb {
#[repr(C)]
#[derive(Debug)]
#[doc = "Register block"]
pub struct RegisterBlock {
tx_ctl: TX_CTL,
tx_prd: TX_PRD,
tx_ctr: TX_CTR,
_reserved3: [u8; 0x34],
tx_cc0ctl: TX_CC0CTL,
tx_cc0ctr: TX_CC0CTR,
tx_cc1ctl: TX_CC1CTL,
tx_cc1ctr: TX_CC1CTR,
tx_cc2ctl: TX_CC2CTL,
tx_cc2ctr: TX_CC2CTR,
tx_cc3ctl: TX_CC3CTL,
tx_cc3ctr: TX_CC3CTR,
_reserved11: [u8; 0x40],
dtgb0ctl: DTGB0CTL,
dtgb0led: DTGB0LED,
dtgb0ted: DTGB0TED,
}
impl RegisterBlock {
#[doc = "0x00 - Timer Control Register"]
#[inline(always)]
pub const fn tx_ctl(&self) -> &TX_CTL {
&self.tx_ctl
}
#[doc = "0x04 - timer period"]
#[inline(always)]
pub const fn tx_prd(&self) -> &TX_PRD {
&self.tx_prd
}
#[doc = "0x08 - timer counter"]
#[inline(always)]
pub const fn tx_ctr(&self) -> &TX_CTR {
&self.tx_ctr
}
#[doc = "0x40 - timer capture and compare control unit 0"]
#[inline(always)]
pub const fn tx_cc0ctl(&self) -> &TX_CC0CTL {
&self.tx_cc0ctl
}
#[doc = "0x44 - capture and compare counter unit 0"]
#[inline(always)]
pub const fn tx_cc0ctr(&self) -> &TX_CC0CTR {
&self.tx_cc0ctr
}
#[doc = "0x48 - timer capture and compare control unit 1"]
#[inline(always)]
pub const fn tx_cc1ctl(&self) -> &TX_CC1CTL {
&self.tx_cc1ctl
}
#[doc = "0x4c - capture and compare counter unit 1"]
#[inline(always)]
pub const fn tx_cc1ctr(&self) -> &TX_CC1CTR {
&self.tx_cc1ctr
}
#[doc = "0x50 - timer capture and compare control unit 2"]
#[inline(always)]
pub const fn tx_cc2ctl(&self) -> &TX_CC2CTL {
&self.tx_cc2ctl
}
#[doc = "0x54 - capture and compare counter unit 2"]
#[inline(always)]
pub const fn tx_cc2ctr(&self) -> &TX_CC2CTR {
&self.tx_cc2ctr
}
#[doc = "0x58 - timer capture and compare control unit 3"]
#[inline(always)]
pub const fn tx_cc3ctl(&self) -> &TX_CC3CTL {
&self.tx_cc3ctl
}
#[doc = "0x5c - capture and compare counter unit 3"]
#[inline(always)]
pub const fn tx_cc3ctr(&self) -> &TX_CC3CTR {
&self.tx_cc3ctr
}
#[doc = "0xa0 - Timer B dead-time generator control unit 0"]
#[inline(always)]
pub const fn dtgb0ctl(&self) -> &DTGB0CTL {
&self.dtgb0ctl
}
#[doc = "0xa4 - Timer B dead-time generator leading-edge delay counter unit 0"]
#[inline(always)]
pub const fn dtgb0led(&self) -> &DTGB0LED {
&self.dtgb0led
}
#[doc = "0xa8 - Timer B dead-time generator trailing-edge delay counter unit 0"]
#[inline(always)]
pub const fn dtgb0ted(&self) -> &DTGB0TED {
&self.dtgb0ted
}
}
#[doc = "TxCTL (rw) register accessor: Timer Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_ctl`]
module"]
#[doc(alias = "TxCTL")]
pub type TX_CTL = crate::Reg<tx_ctl::TX_CTLrs>;
#[doc = "Timer Control Register"]
pub mod tx_ctl {
#[doc = "Register `TxCTL` reader"]
pub type R = crate::R<TX_CTLrs>;
#[doc = "Register `TxCTL` writer"]
pub type W = crate::W<TX_CTLrs>;
#[doc = "Timer Period Latch\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum PRDL {
#[doc = "0: Latch timer values counting up at TxPRD-1"]
Period = 0,
#[doc = "1: Latch timer values when counting down to 1"]
Wrap = 1,
}
impl From<PRDL> for bool {
#[inline(always)]
fn from(variant: PRDL) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `PRDL` reader - Timer Period Latch"]
pub type PRDL_R = crate::BitReader<PRDL>;
impl PRDL_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> PRDL {
match self.bits {
false => PRDL::Period,
true => PRDL::Wrap,
}
}
#[doc = "Latch timer values counting up at TxPRD-1"]
#[inline(always)]
pub fn is_period(&self) -> bool {
*self == PRDL::Period
}
#[doc = "Latch timer values when counting down to 1"]
#[inline(always)]
pub fn is_wrap(&self) -> bool {
*self == PRDL::Wrap
}
}
#[doc = "Field `PRDL` writer - Timer Period Latch"]
pub type PRDL_W<'a, REG> = crate::BitWriter<'a, REG, PRDL>;
impl<'a, REG> PRDL_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Latch timer values counting up at TxPRD-1"]
#[inline(always)]
pub fn period(self) -> &'a mut crate::W<REG> {
self.variant(PRDL::Period)
}
#[doc = "Latch timer values when counting down to 1"]
#[inline(always)]
pub fn wrap(self) -> &'a mut crate::W<REG> {
self.variant(PRDL::Wrap)
}
}
#[doc = "Timer clear\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CLR {
#[doc = "0: Clear Timer, hold in reset, set SYNC_OUT"]
Clear = 0,
#[doc = "1: Do not clear timer, clear SYNC_OUT"]
Noclear = 1,
}
impl From<CLR> for bool {
#[inline(always)]
fn from(variant: CLR) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CLR` reader - Timer clear"]
pub type CLR_R = crate::BitReader<CLR>;
impl CLR_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CLR {
match self.bits {
false => CLR::Clear,
true => CLR::Noclear,
}
}
#[doc = "Clear Timer, hold in reset, set SYNC_OUT"]
#[inline(always)]
pub fn is_clear(&self) -> bool {
*self == CLR::Clear
}
#[doc = "Do not clear timer, clear SYNC_OUT"]
#[inline(always)]
pub fn is_noclear(&self) -> bool {
*self == CLR::Noclear
}
}
#[doc = "Field `CLR` writer - Timer clear"]
pub type CLR_W<'a, REG> = crate::BitWriter<'a, REG, CLR>;
impl<'a, REG> CLR_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Clear Timer, hold in reset, set SYNC_OUT"]
#[inline(always)]
pub fn clear(self) -> &'a mut crate::W<REG> {
self.variant(CLR::Clear)
}
#[doc = "Do not clear timer, clear SYNC_OUT"]
#[inline(always)]
pub fn noclear(self) -> &'a mut crate::W<REG> {
self.variant(CLR::Noclear)
}
}
#[doc = "Timer single shot\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SS {
#[doc = "0: Continuous mode"]
Continuous = 0,
#[doc = "1: Single shot mode"]
Single = 1,
}
impl From<SS> for bool {
#[inline(always)]
fn from(variant: SS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SS` reader - Timer single shot"]
pub type SS_R = crate::BitReader<SS>;
impl SS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SS {
match self.bits {
false => SS::Continuous,
true => SS::Single,
}
}
#[doc = "Continuous mode"]
#[inline(always)]
pub fn is_continuous(&self) -> bool {
*self == SS::Continuous
}
#[doc = "Single shot mode"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == SS::Single
}
}
#[doc = "Field `SS` writer - Timer single shot"]
pub type SS_W<'a, REG> = crate::BitWriter<'a, REG, SS>;
impl<'a, REG> SS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Continuous mode"]
#[inline(always)]
pub fn continuous(self) -> &'a mut crate::W<REG> {
self.variant(SS::Continuous)
}
#[doc = "Single shot mode"]
#[inline(always)]
pub fn single(self) -> &'a mut crate::W<REG> {
self.variant(SS::Single)
}
}
#[doc = "Timer interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INT {
#[doc = "0: interrupt flag, write 1 to clear"]
Interrupt = 0,
#[doc = "1: No interrupt"]
Noint = 1,
}
impl From<INT> for bool {
#[inline(always)]
fn from(variant: INT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INT` reader - Timer interrupt"]
pub type INT_R = crate::BitReader<INT>;
impl INT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INT {
match self.bits {
false => INT::Interrupt,
true => INT::Noint,
}
}
#[doc = "interrupt flag, write 1 to clear"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == INT::Interrupt
}
#[doc = "No interrupt"]
#[inline(always)]
pub fn is_noint(&self) -> bool {
*self == INT::Noint
}
}
#[doc = "Field `INT` writer - Timer interrupt"]
pub type INT_W<'a, REG> = crate::BitWriter<'a, REG, INT>;
impl<'a, REG> INT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt flag, write 1 to clear"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(INT::Interrupt)
}
#[doc = "No interrupt"]
#[inline(always)]
pub fn noint(self) -> &'a mut crate::W<REG> {
self.variant(INT::Noint)
}
}
#[doc = "Timer interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INTEN {
#[doc = "0: timer interrupt enabled"]
Enabled = 0,
#[doc = "1: timer interrupt disabled"]
Disabled = 1,
}
impl From<INTEN> for bool {
#[inline(always)]
fn from(variant: INTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INTEN` reader - Timer interrupt enable"]
pub type INTEN_R = crate::BitReader<INTEN>;
impl INTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INTEN {
match self.bits {
false => INTEN::Enabled,
true => INTEN::Disabled,
}
}
#[doc = "timer interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INTEN::Enabled
}
#[doc = "timer interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INTEN::Disabled
}
}
#[doc = "Field `INTEN` writer - Timer interrupt enable"]
pub type INTEN_W<'a, REG> = crate::BitWriter<'a, REG, INTEN>;
impl<'a, REG> INTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "timer interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INTEN::Enabled)
}
#[doc = "timer interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INTEN::Disabled)
}
}
#[doc = "timer clock divider\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum CLKDIV {
#[doc = "0: divide by 1"]
Div1 = 0,
#[doc = "1: divide by 2"]
Div2 = 1,
#[doc = "2: divide by 4"]
Div4 = 2,
#[doc = "3: divide by 8"]
Div8 = 3,
#[doc = "4: divide by 16"]
Div16 = 4,
#[doc = "5: divide by 32"]
Div32 = 5,
#[doc = "6: divide by 64"]
Div64 = 6,
#[doc = "7: divide by 128"]
Div128 = 7,
}
impl From<CLKDIV> for u8 {
#[inline(always)]
fn from(variant: CLKDIV) -> Self {
variant as _
}
}
impl crate::FieldSpec for CLKDIV {
type Ux = u8;
}
impl crate::IsEnum for CLKDIV {}
#[doc = "Field `CLKDIV` reader - timer clock divider"]
pub type CLKDIV_R = crate::FieldReader<CLKDIV>;
impl CLKDIV_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CLKDIV {
match self.bits {
0 => CLKDIV::Div1,
1 => CLKDIV::Div2,
2 => CLKDIV::Div4,
3 => CLKDIV::Div8,
4 => CLKDIV::Div16,
5 => CLKDIV::Div32,
6 => CLKDIV::Div64,
7 => CLKDIV::Div128,
_ => unreachable!(),
}
}
#[doc = "divide by 1"]
#[inline(always)]
pub fn is_div_1(&self) -> bool {
*self == CLKDIV::Div1
}
#[doc = "divide by 2"]
#[inline(always)]
pub fn is_div_2(&self) -> bool {
*self == CLKDIV::Div2
}
#[doc = "divide by 4"]
#[inline(always)]
pub fn is_div_4(&self) -> bool {
*self == CLKDIV::Div4
}
#[doc = "divide by 8"]
#[inline(always)]
pub fn is_div_8(&self) -> bool {
*self == CLKDIV::Div8
}
#[doc = "divide by 16"]
#[inline(always)]
pub fn is_div_16(&self) -> bool {
*self == CLKDIV::Div16
}
#[doc = "divide by 32"]
#[inline(always)]
pub fn is_div_32(&self) -> bool {
*self == CLKDIV::Div32
}
#[doc = "divide by 64"]
#[inline(always)]
pub fn is_div_64(&self) -> bool {
*self == CLKDIV::Div64
}
#[doc = "divide by 128"]
#[inline(always)]
pub fn is_div_128(&self) -> bool {
*self == CLKDIV::Div128
}
}
#[doc = "Field `CLKDIV` writer - timer clock divider"]
pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CLKDIV, crate::Safe>;
impl<'a, REG> CLKDIV_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "divide by 1"]
#[inline(always)]
pub fn div_1(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div1)
}
#[doc = "divide by 2"]
#[inline(always)]
pub fn div_2(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div2)
}
#[doc = "divide by 4"]
#[inline(always)]
pub fn div_4(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div4)
}
#[doc = "divide by 8"]
#[inline(always)]
pub fn div_8(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div8)
}
#[doc = "divide by 16"]
#[inline(always)]
pub fn div_16(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div16)
}
#[doc = "divide by 32"]
#[inline(always)]
pub fn div_32(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div32)
}
#[doc = "divide by 64"]
#[inline(always)]
pub fn div_64(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div64)
}
#[doc = "divide by 128"]
#[inline(always)]
pub fn div_128(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div128)
}
}
#[doc = "timer clock input source\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CLK {
#[doc = "0: HCLK"]
Hclk = 0,
#[doc = "1: ACLK"]
Aclk = 1,
}
impl From<CLK> for bool {
#[inline(always)]
fn from(variant: CLK) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CLK` reader - timer clock input source"]
pub type CLK_R = crate::BitReader<CLK>;
impl CLK_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CLK {
match self.bits {
false => CLK::Hclk,
true => CLK::Aclk,
}
}
#[doc = "HCLK"]
#[inline(always)]
pub fn is_hclk(&self) -> bool {
*self == CLK::Hclk
}
#[doc = "ACLK"]
#[inline(always)]
pub fn is_aclk(&self) -> bool {
*self == CLK::Aclk
}
}
#[doc = "Field `CLK` writer - timer clock input source"]
pub type CLK_W<'a, REG> = crate::BitWriter<'a, REG, CLK>;
impl<'a, REG> CLK_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "HCLK"]
#[inline(always)]
pub fn hclk(self) -> &'a mut crate::W<REG> {
self.variant(CLK::Hclk)
}
#[doc = "ACLK"]
#[inline(always)]
pub fn aclk(self) -> &'a mut crate::W<REG> {
self.variant(CLK::Aclk)
}
}
#[doc = "timer mode\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum MODE {
#[doc = "0: timer disabled"]
Disabled = 0,
#[doc = "1: up mode"]
Up = 1,
#[doc = "2: up/down mode"]
Updown = 2,
}
impl From<MODE> for u8 {
#[inline(always)]
fn from(variant: MODE) -> Self {
variant as _
}
}
impl crate::FieldSpec for MODE {
type Ux = u8;
}
impl crate::IsEnum for MODE {}
#[doc = "Field `MODE` reader - timer mode"]
pub type MODE_R = crate::FieldReader<MODE>;
impl MODE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<MODE> {
match self.bits {
0 => Some(MODE::Disabled),
1 => Some(MODE::Up),
2 => Some(MODE::Updown),
_ => None,
}
}
#[doc = "timer disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == MODE::Disabled
}
#[doc = "up mode"]
#[inline(always)]
pub fn is_up(&self) -> bool {
*self == MODE::Up
}
#[doc = "up/down mode"]
#[inline(always)]
pub fn is_updown(&self) -> bool {
*self == MODE::Updown
}
}
#[doc = "Field `MODE` writer - timer mode"]
pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, MODE>;
impl<'a, REG> MODE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "timer disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(MODE::Disabled)
}
#[doc = "up mode"]
#[inline(always)]
pub fn up(self) -> &'a mut crate::W<REG> {
self.variant(MODE::Up)
}
#[doc = "up/down mode"]
#[inline(always)]
pub fn updown(self) -> &'a mut crate::W<REG> {
self.variant(MODE::Updown)
}
}
#[doc = "DTG clock select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum DTGCLK {
#[doc = "0: DTG uses clock selected by TxTCL.CLK"]
Clk = 0,
#[doc = "1: DTG uses clock selected by TxCTL.CLKDIV"]
Clkdiv = 1,
}
impl From<DTGCLK> for bool {
#[inline(always)]
fn from(variant: DTGCLK) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `DTGCLK` reader - DTG clock select"]
pub type DTGCLK_R = crate::BitReader<DTGCLK>;
impl DTGCLK_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> DTGCLK {
match self.bits {
false => DTGCLK::Clk,
true => DTGCLK::Clkdiv,
}
}
#[doc = "DTG uses clock selected by TxTCL.CLK"]
#[inline(always)]
pub fn is_clk(&self) -> bool {
*self == DTGCLK::Clk
}
#[doc = "DTG uses clock selected by TxCTL.CLKDIV"]
#[inline(always)]
pub fn is_clkdiv(&self) -> bool {
*self == DTGCLK::Clkdiv
}
}
#[doc = "Field `DTGCLK` writer - DTG clock select"]
pub type DTGCLK_W<'a, REG> = crate::BitWriter<'a, REG, DTGCLK>;
impl<'a, REG> DTGCLK_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "DTG uses clock selected by TxTCL.CLK"]
#[inline(always)]
pub fn clk(self) -> &'a mut crate::W<REG> {
self.variant(DTGCLK::Clk)
}
#[doc = "DTG uses clock selected by TxCTL.CLKDIV"]
#[inline(always)]
pub fn clkdiv(self) -> &'a mut crate::W<REG> {
self.variant(DTGCLK::Clkdiv)
}
}
impl R {
#[doc = "Bit 0 - Timer Period Latch"]
#[inline(always)]
pub fn prdl(&self) -> PRDL_R {
PRDL_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 2 - Timer clear"]
#[inline(always)]
pub fn clr(&self) -> CLR_R {
CLR_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Timer single shot"]
#[inline(always)]
pub fn ss(&self) -> SS_R {
SS_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Timer interrupt"]
#[inline(always)]
pub fn int(&self) -> INT_R {
INT_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Timer interrupt enable"]
#[inline(always)]
pub fn inten(&self) -> INTEN_R {
INTEN_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:8 - timer clock divider"]
#[inline(always)]
pub fn clkdiv(&self) -> CLKDIV_R {
CLKDIV_R::new(((self.bits >> 6) & 7) as u8)
}
#[doc = "Bit 9 - timer clock input source"]
#[inline(always)]
pub fn clk(&self) -> CLK_R {
CLK_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:11 - timer mode"]
#[inline(always)]
pub fn mode(&self) -> MODE_R {
MODE_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bit 13 - DTG clock select"]
#[inline(always)]
pub fn dtgclk(&self) -> DTGCLK_R {
DTGCLK_R::new(((self.bits >> 13) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxCTL")
.field("prdl", &self.prdl())
.field("clr", &self.clr())
.field("ss", &self.ss())
.field("int", &self.int())
.field("inten", &self.inten())
.field("clkdiv", &self.clkdiv())
.field("clk", &self.clk())
.field("mode", &self.mode())
.field("dtgclk", &self.dtgclk())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Timer Period Latch"]
#[inline(always)]
pub fn prdl(&mut self) -> PRDL_W<TX_CTLrs> {
PRDL_W::new(self, 0)
}
#[doc = "Bit 2 - Timer clear"]
#[inline(always)]
pub fn clr(&mut self) -> CLR_W<TX_CTLrs> {
CLR_W::new(self, 2)
}
#[doc = "Bit 3 - Timer single shot"]
#[inline(always)]
pub fn ss(&mut self) -> SS_W<TX_CTLrs> {
SS_W::new(self, 3)
}
#[doc = "Bit 4 - Timer interrupt"]
#[inline(always)]
pub fn int(&mut self) -> INT_W<TX_CTLrs> {
INT_W::new(self, 4)
}
#[doc = "Bit 5 - Timer interrupt enable"]
#[inline(always)]
pub fn inten(&mut self) -> INTEN_W<TX_CTLrs> {
INTEN_W::new(self, 5)
}
#[doc = "Bits 6:8 - timer clock divider"]
#[inline(always)]
pub fn clkdiv(&mut self) -> CLKDIV_W<TX_CTLrs> {
CLKDIV_W::new(self, 6)
}
#[doc = "Bit 9 - timer clock input source"]
#[inline(always)]
pub fn clk(&mut self) -> CLK_W<TX_CTLrs> {
CLK_W::new(self, 9)
}
#[doc = "Bits 10:11 - timer mode"]
#[inline(always)]
pub fn mode(&mut self) -> MODE_W<TX_CTLrs> {
MODE_W::new(self, 10)
}
#[doc = "Bit 13 - DTG clock select"]
#[inline(always)]
pub fn dtgclk(&mut self) -> DTGCLK_W<TX_CTLrs> {
DTGCLK_W::new(self, 13)
}
}
#[doc = "Timer Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_CTLrs;
impl crate::RegisterSpec for TX_CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_ctl::R`](R) reader structure"]
impl crate::Readable for TX_CTLrs {}
#[doc = "`write(|w| ..)` method takes [`tx_ctl::W`](W) writer structure"]
impl crate::Writable for TX_CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TxCTL to value 0"]
impl crate::Resettable for TX_CTLrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TxPRD (rw) register accessor: timer period\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_prd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_prd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_prd`]
module"]
#[doc(alias = "TxPRD")]
pub type TX_PRD = crate::Reg<tx_prd::TX_PRDrs>;
#[doc = "timer period"]
pub mod tx_prd {
#[doc = "Register `TxPRD` reader"]
pub type R = crate::R<TX_PRDrs>;
#[doc = "Register `TxPRD` writer"]
pub type W = crate::W<TX_PRDrs>;
#[doc = "Field `PERIOD` reader - timer period value"]
pub type PERIOD_R = crate::FieldReader<u16>;
#[doc = "Field `PERIOD` writer - timer period value"]
pub type PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - timer period value"]
#[inline(always)]
pub fn period(&self) -> PERIOD_R {
PERIOD_R::new((self.bits & 0xffff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxPRD")
.field("period", &self.period())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - timer period value"]
#[inline(always)]
pub fn period(&mut self) -> PERIOD_W<TX_PRDrs> {
PERIOD_W::new(self, 0)
}
}
#[doc = "timer period\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_prd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_prd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_PRDrs;
impl crate::RegisterSpec for TX_PRDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_prd::R`](R) reader structure"]
impl crate::Readable for TX_PRDrs {}
#[doc = "`write(|w| ..)` method takes [`tx_prd::W`](W) writer structure"]
impl crate::Writable for TX_PRDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TxPRD to value 0"]
impl crate::Resettable for TX_PRDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TxCTR (r) register accessor: timer counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_ctr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_ctr`]
module"]
#[doc(alias = "TxCTR")]
pub type TX_CTR = crate::Reg<tx_ctr::TX_CTRrs>;
#[doc = "timer counter"]
pub mod tx_ctr {
#[doc = "Register `TxCTR` reader"]
pub type R = crate::R<TX_CTRrs>;
#[doc = "Field `CTR` reader - timer counter value"]
pub type CTR_R = crate::FieldReader<u16>;
impl R {
#[doc = "Bits 0:15 - timer counter value"]
#[inline(always)]
pub fn ctr(&self) -> CTR_R {
CTR_R::new((self.bits & 0xffff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxCTR").field("ctr", &self.ctr()).finish()
}
}
#[doc = "timer counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_ctr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_CTRrs;
impl crate::RegisterSpec for TX_CTRrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_ctr::R`](R) reader structure"]
impl crate::Readable for TX_CTRrs {}
#[doc = "`reset()` method sets TxCTR to value 0"]
impl crate::Resettable for TX_CTRrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TxCC0CTL (rw) register accessor: timer capture and compare control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc0ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc0ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_cc0ctl`]
module"]
#[doc(alias = "TxCC0CTL")]
pub type TX_CC0CTL = crate::Reg<tx_cc0ctl::TX_CC0CTLrs>;
#[doc = "timer capture and compare control unit 0"]
pub mod tx_cc0ctl {
#[doc = "Register `TxCC0CTL` reader"]
pub type R = crate::R<TX_CC0CTLrs>;
#[doc = "Register `TxCC0CTL` writer"]
pub type W = crate::W<TX_CC0CTLrs>;
#[doc = "capture mode edge detect\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum CCEDG {
#[doc = "0: high to low transition only"]
Hitolow = 0,
#[doc = "1: low to high transitions only"]
Lowtohigh = 1,
#[doc = "2: both high to low and low to high transitions"]
Both = 2,
}
impl From<CCEDG> for u8 {
#[inline(always)]
fn from(variant: CCEDG) -> Self {
variant as _
}
}
impl crate::FieldSpec for CCEDG {
type Ux = u8;
}
impl crate::IsEnum for CCEDG {}
#[doc = "Field `CCEDG` reader - capture mode edge detect"]
pub type CCEDG_R = crate::FieldReader<CCEDG>;
impl CCEDG_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<CCEDG> {
match self.bits {
0 => Some(CCEDG::Hitolow),
1 => Some(CCEDG::Lowtohigh),
2 => Some(CCEDG::Both),
_ => None,
}
}
#[doc = "high to low transition only"]
#[inline(always)]
pub fn is_hitolow(&self) -> bool {
*self == CCEDG::Hitolow
}
#[doc = "low to high transitions only"]
#[inline(always)]
pub fn is_lowtohigh(&self) -> bool {
*self == CCEDG::Lowtohigh
}
#[doc = "both high to low and low to high transitions"]
#[inline(always)]
pub fn is_both(&self) -> bool {
*self == CCEDG::Both
}
}
#[doc = "Field `CCEDG` writer - capture mode edge detect"]
pub type CCEDG_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CCEDG>;
impl<'a, REG> CCEDG_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "high to low transition only"]
#[inline(always)]
pub fn hitolow(self) -> &'a mut crate::W<REG> {
self.variant(CCEDG::Hitolow)
}
#[doc = "low to high transitions only"]
#[inline(always)]
pub fn lowtohigh(self) -> &'a mut crate::W<REG> {
self.variant(CCEDG::Lowtohigh)
}
#[doc = "both high to low and low to high transitions"]
#[inline(always)]
pub fn both(self) -> &'a mut crate::W<REG> {
self.variant(CCEDG::Both)
}
}
#[doc = "capture and compare interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CCINT {
#[doc = "0: no interrupt detected"]
None = 0,
#[doc = "1: interrupt, write 1b to clear"]
Interrupt = 1,
}
impl From<CCINT> for bool {
#[inline(always)]
fn from(variant: CCINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCINT` reader - capture and compare interrupt"]
pub type CCINT_R = crate::BitReader<CCINT>;
impl CCINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CCINT {
match self.bits {
false => CCINT::None,
true => CCINT::Interrupt,
}
}
#[doc = "no interrupt detected"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == CCINT::None
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == CCINT::Interrupt
}
}
#[doc = "Field `CCINT` writer - capture and compare interrupt"]
pub type CCINT_W<'a, REG> = crate::BitWriter<'a, REG, CCINT>;
impl<'a, REG> CCINT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "no interrupt detected"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(CCINT::None)
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(CCINT::Interrupt)
}
}
#[doc = "capture and compare interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CCINTEN {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<CCINTEN> for bool {
#[inline(always)]
fn from(variant: CCINTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCINTEN` reader - capture and compare interrupt enable"]
pub type CCINTEN_R = crate::BitReader<CCINTEN>;
impl CCINTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CCINTEN {
match self.bits {
false => CCINTEN::Disabled,
true => CCINTEN::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == CCINTEN::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == CCINTEN::Enabled
}
}
#[doc = "Field `CCINTEN` writer - capture and compare interrupt enable"]
pub type CCINTEN_W<'a, REG> = crate::BitWriter<'a, REG, CCINTEN>;
impl<'a, REG> CCINTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(CCINTEN::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(CCINTEN::Enabled)
}
}
#[doc = "capture and compare mode\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CCMODE {
#[doc = "0: compare mode"]
CompareMode = 0,
#[doc = "1: capture mode"]
CaptureMode = 1,
}
impl From<CCMODE> for bool {
#[inline(always)]
fn from(variant: CCMODE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCMODE` reader - capture and compare mode"]
pub type CCMODE_R = crate::BitReader<CCMODE>;
impl CCMODE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CCMODE {
match self.bits {
false => CCMODE::CompareMode,
true => CCMODE::CaptureMode,
}
}
#[doc = "compare mode"]
#[inline(always)]
pub fn is_compare_mode(&self) -> bool {
*self == CCMODE::CompareMode
}
#[doc = "capture mode"]
#[inline(always)]
pub fn is_capture_mode(&self) -> bool {
*self == CCMODE::CaptureMode
}
}
#[doc = "Field `CCMODE` writer - capture and compare mode"]
pub type CCMODE_W<'a, REG> = crate::BitWriter<'a, REG, CCMODE>;
impl<'a, REG> CCMODE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "compare mode"]
#[inline(always)]
pub fn compare_mode(self) -> &'a mut crate::W<REG> {
self.variant(CCMODE::CompareMode)
}
#[doc = "capture mode"]
#[inline(always)]
pub fn capture_mode(self) -> &'a mut crate::W<REG> {
self.variant(CCMODE::CaptureMode)
}
}
impl R {
#[doc = "Bits 0:1 - capture mode edge detect"]
#[inline(always)]
pub fn ccedg(&self) -> CCEDG_R {
CCEDG_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - capture and compare interrupt"]
#[inline(always)]
pub fn ccint(&self) -> CCINT_R {
CCINT_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - capture and compare interrupt enable"]
#[inline(always)]
pub fn ccinten(&self) -> CCINTEN_R {
CCINTEN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - capture and compare mode"]
#[inline(always)]
pub fn ccmode(&self) -> CCMODE_R {
CCMODE_R::new(((self.bits >> 4) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxCC0CTL")
.field("ccedg", &self.ccedg())
.field("ccint", &self.ccint())
.field("ccinten", &self.ccinten())
.field("ccmode", &self.ccmode())
.finish()
}
}
impl W {
#[doc = "Bits 0:1 - capture mode edge detect"]
#[inline(always)]
pub fn ccedg(&mut self) -> CCEDG_W<TX_CC0CTLrs> {
CCEDG_W::new(self, 0)
}
#[doc = "Bit 2 - capture and compare interrupt"]
#[inline(always)]
pub fn ccint(&mut self) -> CCINT_W<TX_CC0CTLrs> {
CCINT_W::new(self, 2)
}
#[doc = "Bit 3 - capture and compare interrupt enable"]
#[inline(always)]
pub fn ccinten(&mut self) -> CCINTEN_W<TX_CC0CTLrs> {
CCINTEN_W::new(self, 3)
}
#[doc = "Bit 4 - capture and compare mode"]
#[inline(always)]
pub fn ccmode(&mut self) -> CCMODE_W<TX_CC0CTLrs> {
CCMODE_W::new(self, 4)
}
}
#[doc = "timer capture and compare control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc0ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc0ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_CC0CTLrs;
impl crate::RegisterSpec for TX_CC0CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_cc0ctl::R`](R) reader structure"]
impl crate::Readable for TX_CC0CTLrs {}
#[doc = "`write(|w| ..)` method takes [`tx_cc0ctl::W`](W) writer structure"]
impl crate::Writable for TX_CC0CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TxCC0CTL to value 0"]
impl crate::Resettable for TX_CC0CTLrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TxCC0CTR (rw) register accessor: capture and compare counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc0ctr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc0ctr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_cc0ctr`]
module"]
#[doc(alias = "TxCC0CTR")]
pub type TX_CC0CTR = crate::Reg<tx_cc0ctr::TX_CC0CTRrs>;
#[doc = "capture and compare counter unit 0"]
pub mod tx_cc0ctr {
#[doc = "Register `TxCC0CTR` reader"]
pub type R = crate::R<TX_CC0CTRrs>;
#[doc = "Register `TxCC0CTR` writer"]
pub type W = crate::W<TX_CC0CTRrs>;
#[doc = "Field `CCCTR` reader - capture and compare counter value"]
pub type CCCTR_R = crate::FieldReader<u16>;
#[doc = "Field `CCCTR` writer - capture and compare counter value"]
pub type CCCTR_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - capture and compare counter value"]
#[inline(always)]
pub fn ccctr(&self) -> CCCTR_R {
CCCTR_R::new((self.bits & 0xffff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxCC0CTR")
.field("ccctr", &self.ccctr())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - capture and compare counter value"]
#[inline(always)]
pub fn ccctr(&mut self) -> CCCTR_W<TX_CC0CTRrs> {
CCCTR_W::new(self, 0)
}
}
#[doc = "capture and compare counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc0ctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc0ctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_CC0CTRrs;
impl crate::RegisterSpec for TX_CC0CTRrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_cc0ctr::R`](R) reader structure"]
impl crate::Readable for TX_CC0CTRrs {}
#[doc = "`write(|w| ..)` method takes [`tx_cc0ctr::W`](W) writer structure"]
impl crate::Writable for TX_CC0CTRrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TxCC0CTR to value 0"]
impl crate::Resettable for TX_CC0CTRrs {
const RESET_VALUE: u32 = 0;
}
}
pub use tx_cc0ctl as tx_cc1ctl;
pub use tx_cc0ctl as tx_cc2ctl;
pub use tx_cc0ctl as tx_cc3ctl;
pub use tx_cc0ctr as tx_cc1ctr;
pub use tx_cc0ctr as tx_cc2ctr;
pub use tx_cc0ctr as tx_cc3ctr;
pub use TX_CC0CTL as TX_CC1CTL;
pub use TX_CC0CTL as TX_CC2CTL;
pub use TX_CC0CTL as TX_CC3CTL;
pub use TX_CC0CTR as TX_CC1CTR;
pub use TX_CC0CTR as TX_CC2CTR;
pub use TX_CC0CTR as TX_CC3CTR;
#[doc = "DTGB0CTL (rw) register accessor: Timer B dead-time generator control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgb0ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgb0ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtgb0ctl`]
module"]
pub type DTGB0CTL = crate::Reg<dtgb0ctl::DTGB0CTLrs>;
#[doc = "Timer B dead-time generator control unit 0"]
pub mod dtgb0ctl {
#[doc = "Register `DTGB0CTL` reader"]
pub type R = crate::R<DTGB0CTLrs>;
#[doc = "Register `DTGB0CTL` writer"]
pub type W = crate::W<DTGB0CTLrs>;
#[doc = "Invert low-side output signal\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INVLS {
#[doc = "0: do not invert low-side output signal"]
Disabled = 0,
#[doc = "1: invert low-side output signal"]
Enabled = 1,
}
impl From<INVLS> for bool {
#[inline(always)]
fn from(variant: INVLS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INVLS` reader - Invert low-side output signal"]
pub type INVLS_R = crate::BitReader<INVLS>;
impl INVLS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INVLS {
match self.bits {
false => INVLS::Disabled,
true => INVLS::Enabled,
}
}
#[doc = "do not invert low-side output signal"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INVLS::Disabled
}
#[doc = "invert low-side output signal"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INVLS::Enabled
}
}
#[doc = "Field `INVLS` writer - Invert low-side output signal"]
pub type INVLS_W<'a, REG> = crate::BitWriter<'a, REG, INVLS>;
impl<'a, REG> INVLS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not invert low-side output signal"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INVLS::Disabled)
}
#[doc = "invert low-side output signal"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INVLS::Enabled)
}
}
#[doc = "Invert high-side output signal\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INVHS {
#[doc = "0: do not invert high-side output signal"]
Disabled = 0,
#[doc = "1: invert high-side output signal"]
Enabled = 1,
}
impl From<INVHS> for bool {
#[inline(always)]
fn from(variant: INVHS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INVHS` reader - Invert high-side output signal"]
pub type INVHS_R = crate::BitReader<INVHS>;
impl INVHS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INVHS {
match self.bits {
false => INVHS::Disabled,
true => INVHS::Enabled,
}
}
#[doc = "do not invert high-side output signal"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INVHS::Disabled
}
#[doc = "invert high-side output signal"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INVHS::Enabled
}
}
#[doc = "Field `INVHS` writer - Invert high-side output signal"]
pub type INVHS_W<'a, REG> = crate::BitWriter<'a, REG, INVHS>;
impl<'a, REG> INVHS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not invert high-side output signal"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INVHS::Disabled)
}
#[doc = "invert high-side output signal"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INVHS::Enabled)
}
}
#[doc = "On-time preservation\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum OTP {
#[doc = "0: do not extend on time"]
Disabled = 0,
#[doc = "1: extend on time"]
Enabled = 1,
}
impl From<OTP> for bool {
#[inline(always)]
fn from(variant: OTP) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OTP` reader - On-time preservation"]
pub type OTP_R = crate::BitReader<OTP>;
impl OTP_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> OTP {
match self.bits {
false => OTP::Disabled,
true => OTP::Enabled,
}
}
#[doc = "do not extend on time"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == OTP::Disabled
}
#[doc = "extend on time"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == OTP::Enabled
}
}
#[doc = "Field `OTP` writer - On-time preservation"]
pub type OTP_W<'a, REG> = crate::BitWriter<'a, REG, OTP>;
impl<'a, REG> OTP_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not extend on time"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(OTP::Disabled)
}
#[doc = "extend on time"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(OTP::Enabled)
}
}
#[doc = "bypass dead-time generation\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum BYPASS {
#[doc = "0: do not bypass dead-time generation"]
Disabled = 0,
#[doc = "1: bypass dead-time generation"]
Enabled = 1,
}
impl From<BYPASS> for bool {
#[inline(always)]
fn from(variant: BYPASS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `BYPASS` reader - bypass dead-time generation"]
pub type BYPASS_R = crate::BitReader<BYPASS>;
impl BYPASS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> BYPASS {
match self.bits {
false => BYPASS::Disabled,
true => BYPASS::Enabled,
}
}
#[doc = "do not bypass dead-time generation"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == BYPASS::Disabled
}
#[doc = "bypass dead-time generation"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == BYPASS::Enabled
}
}
#[doc = "Field `BYPASS` writer - bypass dead-time generation"]
pub type BYPASS_W<'a, REG> = crate::BitWriter<'a, REG, BYPASS>;
impl<'a, REG> BYPASS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not bypass dead-time generation"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(BYPASS::Disabled)
}
#[doc = "bypass dead-time generation"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(BYPASS::Enabled)
}
}
impl R {
#[doc = "Bit 4 - Invert low-side output signal"]
#[inline(always)]
pub fn invls(&self) -> INVLS_R {
INVLS_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Invert high-side output signal"]
#[inline(always)]
pub fn invhs(&self) -> INVHS_R {
INVHS_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - On-time preservation"]
#[inline(always)]
pub fn otp(&self) -> OTP_R {
OTP_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - bypass dead-time generation"]
#[inline(always)]
pub fn bypass(&self) -> BYPASS_R {
BYPASS_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGB0CTL")
.field("invls", &self.invls())
.field("invhs", &self.invhs())
.field("otp", &self.otp())
.field("bypass", &self.bypass())
.finish()
}
}
impl W {
#[doc = "Bit 4 - Invert low-side output signal"]
#[inline(always)]
pub fn invls(&mut self) -> INVLS_W<DTGB0CTLrs> {
INVLS_W::new(self, 4)
}
#[doc = "Bit 5 - Invert high-side output signal"]
#[inline(always)]
pub fn invhs(&mut self) -> INVHS_W<DTGB0CTLrs> {
INVHS_W::new(self, 5)
}
#[doc = "Bit 6 - On-time preservation"]
#[inline(always)]
pub fn otp(&mut self) -> OTP_W<DTGB0CTLrs> {
OTP_W::new(self, 6)
}
#[doc = "Bit 7 - bypass dead-time generation"]
#[inline(always)]
pub fn bypass(&mut self) -> BYPASS_W<DTGB0CTLrs> {
BYPASS_W::new(self, 7)
}
}
#[doc = "Timer B dead-time generator control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgb0ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgb0ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGB0CTLrs;
impl crate::RegisterSpec for DTGB0CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtgb0ctl::R`](R) reader structure"]
impl crate::Readable for DTGB0CTLrs {}
#[doc = "`write(|w| ..)` method takes [`dtgb0ctl::W`](W) writer structure"]
impl crate::Writable for DTGB0CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGB0CTL to value 0x80"]
impl crate::Resettable for DTGB0CTLrs {
const RESET_VALUE: u32 = 0x80;
}
}
#[doc = "DTGB0LED (rw) register accessor: Timer B dead-time generator leading-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgb0led::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgb0led::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtgb0led`]
module"]
pub type DTGB0LED = crate::Reg<dtgb0led::DTGB0LEDrs>;
#[doc = "Timer B dead-time generator leading-edge delay counter unit 0"]
pub mod dtgb0led {
#[doc = "Register `DTGB0LED` reader"]
pub type R = crate::R<DTGB0LEDrs>;
#[doc = "Register `DTGB0LED` writer"]
pub type W = crate::W<DTGB0LEDrs>;
#[doc = "Field `LED` reader - leading-edge delay counter"]
pub type LED_R = crate::FieldReader<u16>;
#[doc = "Field `LED` writer - leading-edge delay counter"]
pub type LED_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:11 - leading-edge delay counter"]
#[inline(always)]
pub fn led(&self) -> LED_R {
LED_R::new((self.bits & 0x0fff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGB0LED")
.field("led", &self.led())
.finish()
}
}
impl W {
#[doc = "Bits 0:11 - leading-edge delay counter"]
#[inline(always)]
pub fn led(&mut self) -> LED_W<DTGB0LEDrs> {
LED_W::new(self, 0)
}
}
#[doc = "Timer B dead-time generator leading-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgb0led::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgb0led::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGB0LEDrs;
impl crate::RegisterSpec for DTGB0LEDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtgb0led::R`](R) reader structure"]
impl crate::Readable for DTGB0LEDrs {}
#[doc = "`write(|w| ..)` method takes [`dtgb0led::W`](W) writer structure"]
impl crate::Writable for DTGB0LEDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGB0LED to value 0"]
impl crate::Resettable for DTGB0LEDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DTGB0TED (rw) register accessor: Timer B dead-time generator trailing-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgb0ted::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgb0ted::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtgb0ted`]
module"]
pub type DTGB0TED = crate::Reg<dtgb0ted::DTGB0TEDrs>;
#[doc = "Timer B dead-time generator trailing-edge delay counter unit 0"]
pub mod dtgb0ted {
#[doc = "Register `DTGB0TED` reader"]
pub type R = crate::R<DTGB0TEDrs>;
#[doc = "Register `DTGB0TED` writer"]
pub type W = crate::W<DTGB0TEDrs>;
#[doc = "Field `TED` reader - trailing-edge delay counter"]
pub type TED_R = crate::FieldReader<u16>;
#[doc = "Field `TED` writer - trailing-edge delay counter"]
pub type TED_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:11 - trailing-edge delay counter"]
#[inline(always)]
pub fn ted(&self) -> TED_R {
TED_R::new((self.bits & 0x0fff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGB0TED")
.field("ted", &self.ted())
.finish()
}
}
impl W {
#[doc = "Bits 0:11 - trailing-edge delay counter"]
#[inline(always)]
pub fn ted(&mut self) -> TED_W<DTGB0TEDrs> {
TED_W::new(self, 0)
}
}
#[doc = "Timer B dead-time generator trailing-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgb0ted::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgb0ted::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGB0TEDrs;
impl crate::RegisterSpec for DTGB0TEDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtgb0ted::R`](R) reader structure"]
impl crate::Readable for DTGB0TEDrs {}
#[doc = "`write(|w| ..)` method takes [`dtgb0ted::W`](W) writer structure"]
impl crate::Writable for DTGB0TEDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGB0TED to value 0"]
impl crate::Resettable for DTGB0TEDrs {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "Timer C Peripheral"]
pub struct TIMERC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIMERC {}
impl TIMERC {
#[doc = r"Pointer to the register block"]
pub const PTR: *const timerc::RegisterBlock = 0x400f_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const timerc::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for TIMERC {
type Target = timerc::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for TIMERC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIMERC").finish()
}
}
#[doc = "Timer C Peripheral"]
pub mod timerc {
#[repr(C)]
#[derive(Debug)]
#[doc = "Register block"]
pub struct RegisterBlock {
tx_ctl: TX_CTL,
tx_prd: TX_PRD,
tx_ctr: TX_CTR,
_reserved3: [u8; 0x34],
tx_cc0ctl: TX_CC0CTL,
tx_cc0ctr: TX_CC0CTR,
tx_cc1ctl: TX_CC1CTL,
tx_cc1ctr: TX_CC1CTR,
_reserved7: [u8; 0x50],
dtgc0ctl: DTGC0CTL,
dtgc0led: DTGC0LED,
dtgc0ted: DTGC0TED,
}
impl RegisterBlock {
#[doc = "0x00 - Timer Control Register"]
#[inline(always)]
pub const fn tx_ctl(&self) -> &TX_CTL {
&self.tx_ctl
}
#[doc = "0x04 - timer period"]
#[inline(always)]
pub const fn tx_prd(&self) -> &TX_PRD {
&self.tx_prd
}
#[doc = "0x08 - timer counter"]
#[inline(always)]
pub const fn tx_ctr(&self) -> &TX_CTR {
&self.tx_ctr
}
#[doc = "0x40 - timer capture and compare control unit 0"]
#[inline(always)]
pub const fn tx_cc0ctl(&self) -> &TX_CC0CTL {
&self.tx_cc0ctl
}
#[doc = "0x44 - capture and compare counter unit 0"]
#[inline(always)]
pub const fn tx_cc0ctr(&self) -> &TX_CC0CTR {
&self.tx_cc0ctr
}
#[doc = "0x48 - timer capture and compare control unit 1"]
#[inline(always)]
pub const fn tx_cc1ctl(&self) -> &TX_CC1CTL {
&self.tx_cc1ctl
}
#[doc = "0x4c - capture and compare counter unit 1"]
#[inline(always)]
pub const fn tx_cc1ctr(&self) -> &TX_CC1CTR {
&self.tx_cc1ctr
}
#[doc = "0xa0 - Timer C dead-time generator control unit 0"]
#[inline(always)]
pub const fn dtgc0ctl(&self) -> &DTGC0CTL {
&self.dtgc0ctl
}
#[doc = "0xa4 - Timer C dead-time generator leading-edge delay counter unit 0"]
#[inline(always)]
pub const fn dtgc0led(&self) -> &DTGC0LED {
&self.dtgc0led
}
#[doc = "0xa8 - Timer C dead-time generator trailing-edge delay counter unit 0"]
#[inline(always)]
pub const fn dtgc0ted(&self) -> &DTGC0TED {
&self.dtgc0ted
}
}
#[doc = "TxCTL (rw) register accessor: Timer Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_ctl`]
module"]
#[doc(alias = "TxCTL")]
pub type TX_CTL = crate::Reg<tx_ctl::TX_CTLrs>;
#[doc = "Timer Control Register"]
pub mod tx_ctl {
#[doc = "Register `TxCTL` reader"]
pub type R = crate::R<TX_CTLrs>;
#[doc = "Register `TxCTL` writer"]
pub type W = crate::W<TX_CTLrs>;
#[doc = "Timer Period Latch\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum PRDL {
#[doc = "0: Latch timer values counting up at TxPRD-1"]
Period = 0,
#[doc = "1: Latch timer values when counting down to 1"]
Wrap = 1,
}
impl From<PRDL> for bool {
#[inline(always)]
fn from(variant: PRDL) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `PRDL` reader - Timer Period Latch"]
pub type PRDL_R = crate::BitReader<PRDL>;
impl PRDL_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> PRDL {
match self.bits {
false => PRDL::Period,
true => PRDL::Wrap,
}
}
#[doc = "Latch timer values counting up at TxPRD-1"]
#[inline(always)]
pub fn is_period(&self) -> bool {
*self == PRDL::Period
}
#[doc = "Latch timer values when counting down to 1"]
#[inline(always)]
pub fn is_wrap(&self) -> bool {
*self == PRDL::Wrap
}
}
#[doc = "Field `PRDL` writer - Timer Period Latch"]
pub type PRDL_W<'a, REG> = crate::BitWriter<'a, REG, PRDL>;
impl<'a, REG> PRDL_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Latch timer values counting up at TxPRD-1"]
#[inline(always)]
pub fn period(self) -> &'a mut crate::W<REG> {
self.variant(PRDL::Period)
}
#[doc = "Latch timer values when counting down to 1"]
#[inline(always)]
pub fn wrap(self) -> &'a mut crate::W<REG> {
self.variant(PRDL::Wrap)
}
}
#[doc = "Timer clear\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CLR {
#[doc = "0: Clear Timer, hold in reset, set SYNC_OUT"]
Clear = 0,
#[doc = "1: Do not clear timer, clear SYNC_OUT"]
Noclear = 1,
}
impl From<CLR> for bool {
#[inline(always)]
fn from(variant: CLR) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CLR` reader - Timer clear"]
pub type CLR_R = crate::BitReader<CLR>;
impl CLR_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CLR {
match self.bits {
false => CLR::Clear,
true => CLR::Noclear,
}
}
#[doc = "Clear Timer, hold in reset, set SYNC_OUT"]
#[inline(always)]
pub fn is_clear(&self) -> bool {
*self == CLR::Clear
}
#[doc = "Do not clear timer, clear SYNC_OUT"]
#[inline(always)]
pub fn is_noclear(&self) -> bool {
*self == CLR::Noclear
}
}
#[doc = "Field `CLR` writer - Timer clear"]
pub type CLR_W<'a, REG> = crate::BitWriter<'a, REG, CLR>;
impl<'a, REG> CLR_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Clear Timer, hold in reset, set SYNC_OUT"]
#[inline(always)]
pub fn clear(self) -> &'a mut crate::W<REG> {
self.variant(CLR::Clear)
}
#[doc = "Do not clear timer, clear SYNC_OUT"]
#[inline(always)]
pub fn noclear(self) -> &'a mut crate::W<REG> {
self.variant(CLR::Noclear)
}
}
#[doc = "Timer single shot\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SS {
#[doc = "0: Continuous mode"]
Continuous = 0,
#[doc = "1: Single shot mode"]
Single = 1,
}
impl From<SS> for bool {
#[inline(always)]
fn from(variant: SS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SS` reader - Timer single shot"]
pub type SS_R = crate::BitReader<SS>;
impl SS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SS {
match self.bits {
false => SS::Continuous,
true => SS::Single,
}
}
#[doc = "Continuous mode"]
#[inline(always)]
pub fn is_continuous(&self) -> bool {
*self == SS::Continuous
}
#[doc = "Single shot mode"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == SS::Single
}
}
#[doc = "Field `SS` writer - Timer single shot"]
pub type SS_W<'a, REG> = crate::BitWriter<'a, REG, SS>;
impl<'a, REG> SS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Continuous mode"]
#[inline(always)]
pub fn continuous(self) -> &'a mut crate::W<REG> {
self.variant(SS::Continuous)
}
#[doc = "Single shot mode"]
#[inline(always)]
pub fn single(self) -> &'a mut crate::W<REG> {
self.variant(SS::Single)
}
}
#[doc = "Timer interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INT {
#[doc = "0: interrupt flag, write 1 to clear"]
Interrupt = 0,
#[doc = "1: No interrupt"]
Noint = 1,
}
impl From<INT> for bool {
#[inline(always)]
fn from(variant: INT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INT` reader - Timer interrupt"]
pub type INT_R = crate::BitReader<INT>;
impl INT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INT {
match self.bits {
false => INT::Interrupt,
true => INT::Noint,
}
}
#[doc = "interrupt flag, write 1 to clear"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == INT::Interrupt
}
#[doc = "No interrupt"]
#[inline(always)]
pub fn is_noint(&self) -> bool {
*self == INT::Noint
}
}
#[doc = "Field `INT` writer - Timer interrupt"]
pub type INT_W<'a, REG> = crate::BitWriter<'a, REG, INT>;
impl<'a, REG> INT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt flag, write 1 to clear"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(INT::Interrupt)
}
#[doc = "No interrupt"]
#[inline(always)]
pub fn noint(self) -> &'a mut crate::W<REG> {
self.variant(INT::Noint)
}
}
#[doc = "Timer interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INTEN {
#[doc = "0: timer interrupt enabled"]
Enabled = 0,
#[doc = "1: timer interrupt disabled"]
Disabled = 1,
}
impl From<INTEN> for bool {
#[inline(always)]
fn from(variant: INTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INTEN` reader - Timer interrupt enable"]
pub type INTEN_R = crate::BitReader<INTEN>;
impl INTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INTEN {
match self.bits {
false => INTEN::Enabled,
true => INTEN::Disabled,
}
}
#[doc = "timer interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INTEN::Enabled
}
#[doc = "timer interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INTEN::Disabled
}
}
#[doc = "Field `INTEN` writer - Timer interrupt enable"]
pub type INTEN_W<'a, REG> = crate::BitWriter<'a, REG, INTEN>;
impl<'a, REG> INTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "timer interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INTEN::Enabled)
}
#[doc = "timer interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INTEN::Disabled)
}
}
#[doc = "timer clock divider\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum CLKDIV {
#[doc = "0: divide by 1"]
Div1 = 0,
#[doc = "1: divide by 2"]
Div2 = 1,
#[doc = "2: divide by 4"]
Div4 = 2,
#[doc = "3: divide by 8"]
Div8 = 3,
#[doc = "4: divide by 16"]
Div16 = 4,
#[doc = "5: divide by 32"]
Div32 = 5,
#[doc = "6: divide by 64"]
Div64 = 6,
#[doc = "7: divide by 128"]
Div128 = 7,
}
impl From<CLKDIV> for u8 {
#[inline(always)]
fn from(variant: CLKDIV) -> Self {
variant as _
}
}
impl crate::FieldSpec for CLKDIV {
type Ux = u8;
}
impl crate::IsEnum for CLKDIV {}
#[doc = "Field `CLKDIV` reader - timer clock divider"]
pub type CLKDIV_R = crate::FieldReader<CLKDIV>;
impl CLKDIV_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CLKDIV {
match self.bits {
0 => CLKDIV::Div1,
1 => CLKDIV::Div2,
2 => CLKDIV::Div4,
3 => CLKDIV::Div8,
4 => CLKDIV::Div16,
5 => CLKDIV::Div32,
6 => CLKDIV::Div64,
7 => CLKDIV::Div128,
_ => unreachable!(),
}
}
#[doc = "divide by 1"]
#[inline(always)]
pub fn is_div_1(&self) -> bool {
*self == CLKDIV::Div1
}
#[doc = "divide by 2"]
#[inline(always)]
pub fn is_div_2(&self) -> bool {
*self == CLKDIV::Div2
}
#[doc = "divide by 4"]
#[inline(always)]
pub fn is_div_4(&self) -> bool {
*self == CLKDIV::Div4
}
#[doc = "divide by 8"]
#[inline(always)]
pub fn is_div_8(&self) -> bool {
*self == CLKDIV::Div8
}
#[doc = "divide by 16"]
#[inline(always)]
pub fn is_div_16(&self) -> bool {
*self == CLKDIV::Div16
}
#[doc = "divide by 32"]
#[inline(always)]
pub fn is_div_32(&self) -> bool {
*self == CLKDIV::Div32
}
#[doc = "divide by 64"]
#[inline(always)]
pub fn is_div_64(&self) -> bool {
*self == CLKDIV::Div64
}
#[doc = "divide by 128"]
#[inline(always)]
pub fn is_div_128(&self) -> bool {
*self == CLKDIV::Div128
}
}
#[doc = "Field `CLKDIV` writer - timer clock divider"]
pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CLKDIV, crate::Safe>;
impl<'a, REG> CLKDIV_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "divide by 1"]
#[inline(always)]
pub fn div_1(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div1)
}
#[doc = "divide by 2"]
#[inline(always)]
pub fn div_2(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div2)
}
#[doc = "divide by 4"]
#[inline(always)]
pub fn div_4(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div4)
}
#[doc = "divide by 8"]
#[inline(always)]
pub fn div_8(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div8)
}
#[doc = "divide by 16"]
#[inline(always)]
pub fn div_16(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div16)
}
#[doc = "divide by 32"]
#[inline(always)]
pub fn div_32(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div32)
}
#[doc = "divide by 64"]
#[inline(always)]
pub fn div_64(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div64)
}
#[doc = "divide by 128"]
#[inline(always)]
pub fn div_128(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div128)
}
}
#[doc = "timer clock input source\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CLK {
#[doc = "0: HCLK"]
Hclk = 0,
#[doc = "1: ACLK"]
Aclk = 1,
}
impl From<CLK> for bool {
#[inline(always)]
fn from(variant: CLK) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CLK` reader - timer clock input source"]
pub type CLK_R = crate::BitReader<CLK>;
impl CLK_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CLK {
match self.bits {
false => CLK::Hclk,
true => CLK::Aclk,
}
}
#[doc = "HCLK"]
#[inline(always)]
pub fn is_hclk(&self) -> bool {
*self == CLK::Hclk
}
#[doc = "ACLK"]
#[inline(always)]
pub fn is_aclk(&self) -> bool {
*self == CLK::Aclk
}
}
#[doc = "Field `CLK` writer - timer clock input source"]
pub type CLK_W<'a, REG> = crate::BitWriter<'a, REG, CLK>;
impl<'a, REG> CLK_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "HCLK"]
#[inline(always)]
pub fn hclk(self) -> &'a mut crate::W<REG> {
self.variant(CLK::Hclk)
}
#[doc = "ACLK"]
#[inline(always)]
pub fn aclk(self) -> &'a mut crate::W<REG> {
self.variant(CLK::Aclk)
}
}
#[doc = "timer mode\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum MODE {
#[doc = "0: timer disabled"]
Disabled = 0,
#[doc = "1: up mode"]
Up = 1,
#[doc = "2: up/down mode"]
Updown = 2,
}
impl From<MODE> for u8 {
#[inline(always)]
fn from(variant: MODE) -> Self {
variant as _
}
}
impl crate::FieldSpec for MODE {
type Ux = u8;
}
impl crate::IsEnum for MODE {}
#[doc = "Field `MODE` reader - timer mode"]
pub type MODE_R = crate::FieldReader<MODE>;
impl MODE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<MODE> {
match self.bits {
0 => Some(MODE::Disabled),
1 => Some(MODE::Up),
2 => Some(MODE::Updown),
_ => None,
}
}
#[doc = "timer disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == MODE::Disabled
}
#[doc = "up mode"]
#[inline(always)]
pub fn is_up(&self) -> bool {
*self == MODE::Up
}
#[doc = "up/down mode"]
#[inline(always)]
pub fn is_updown(&self) -> bool {
*self == MODE::Updown
}
}
#[doc = "Field `MODE` writer - timer mode"]
pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, MODE>;
impl<'a, REG> MODE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "timer disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(MODE::Disabled)
}
#[doc = "up mode"]
#[inline(always)]
pub fn up(self) -> &'a mut crate::W<REG> {
self.variant(MODE::Up)
}
#[doc = "up/down mode"]
#[inline(always)]
pub fn updown(self) -> &'a mut crate::W<REG> {
self.variant(MODE::Updown)
}
}
#[doc = "DTG clock select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum DTGCLK {
#[doc = "0: DTG uses clock selected by TxTCL.CLK"]
Clk = 0,
#[doc = "1: DTG uses clock selected by TxCTL.CLKDIV"]
Clkdiv = 1,
}
impl From<DTGCLK> for bool {
#[inline(always)]
fn from(variant: DTGCLK) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `DTGCLK` reader - DTG clock select"]
pub type DTGCLK_R = crate::BitReader<DTGCLK>;
impl DTGCLK_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> DTGCLK {
match self.bits {
false => DTGCLK::Clk,
true => DTGCLK::Clkdiv,
}
}
#[doc = "DTG uses clock selected by TxTCL.CLK"]
#[inline(always)]
pub fn is_clk(&self) -> bool {
*self == DTGCLK::Clk
}
#[doc = "DTG uses clock selected by TxCTL.CLKDIV"]
#[inline(always)]
pub fn is_clkdiv(&self) -> bool {
*self == DTGCLK::Clkdiv
}
}
#[doc = "Field `DTGCLK` writer - DTG clock select"]
pub type DTGCLK_W<'a, REG> = crate::BitWriter<'a, REG, DTGCLK>;
impl<'a, REG> DTGCLK_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "DTG uses clock selected by TxTCL.CLK"]
#[inline(always)]
pub fn clk(self) -> &'a mut crate::W<REG> {
self.variant(DTGCLK::Clk)
}
#[doc = "DTG uses clock selected by TxCTL.CLKDIV"]
#[inline(always)]
pub fn clkdiv(self) -> &'a mut crate::W<REG> {
self.variant(DTGCLK::Clkdiv)
}
}
impl R {
#[doc = "Bit 0 - Timer Period Latch"]
#[inline(always)]
pub fn prdl(&self) -> PRDL_R {
PRDL_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 2 - Timer clear"]
#[inline(always)]
pub fn clr(&self) -> CLR_R {
CLR_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Timer single shot"]
#[inline(always)]
pub fn ss(&self) -> SS_R {
SS_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Timer interrupt"]
#[inline(always)]
pub fn int(&self) -> INT_R {
INT_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Timer interrupt enable"]
#[inline(always)]
pub fn inten(&self) -> INTEN_R {
INTEN_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:8 - timer clock divider"]
#[inline(always)]
pub fn clkdiv(&self) -> CLKDIV_R {
CLKDIV_R::new(((self.bits >> 6) & 7) as u8)
}
#[doc = "Bit 9 - timer clock input source"]
#[inline(always)]
pub fn clk(&self) -> CLK_R {
CLK_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:11 - timer mode"]
#[inline(always)]
pub fn mode(&self) -> MODE_R {
MODE_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bit 13 - DTG clock select"]
#[inline(always)]
pub fn dtgclk(&self) -> DTGCLK_R {
DTGCLK_R::new(((self.bits >> 13) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxCTL")
.field("prdl", &self.prdl())
.field("clr", &self.clr())
.field("ss", &self.ss())
.field("int", &self.int())
.field("inten", &self.inten())
.field("clkdiv", &self.clkdiv())
.field("clk", &self.clk())
.field("mode", &self.mode())
.field("dtgclk", &self.dtgclk())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Timer Period Latch"]
#[inline(always)]
pub fn prdl(&mut self) -> PRDL_W<TX_CTLrs> {
PRDL_W::new(self, 0)
}
#[doc = "Bit 2 - Timer clear"]
#[inline(always)]
pub fn clr(&mut self) -> CLR_W<TX_CTLrs> {
CLR_W::new(self, 2)
}
#[doc = "Bit 3 - Timer single shot"]
#[inline(always)]
pub fn ss(&mut self) -> SS_W<TX_CTLrs> {
SS_W::new(self, 3)
}
#[doc = "Bit 4 - Timer interrupt"]
#[inline(always)]
pub fn int(&mut self) -> INT_W<TX_CTLrs> {
INT_W::new(self, 4)
}
#[doc = "Bit 5 - Timer interrupt enable"]
#[inline(always)]
pub fn inten(&mut self) -> INTEN_W<TX_CTLrs> {
INTEN_W::new(self, 5)
}
#[doc = "Bits 6:8 - timer clock divider"]
#[inline(always)]
pub fn clkdiv(&mut self) -> CLKDIV_W<TX_CTLrs> {
CLKDIV_W::new(self, 6)
}
#[doc = "Bit 9 - timer clock input source"]
#[inline(always)]
pub fn clk(&mut self) -> CLK_W<TX_CTLrs> {
CLK_W::new(self, 9)
}
#[doc = "Bits 10:11 - timer mode"]
#[inline(always)]
pub fn mode(&mut self) -> MODE_W<TX_CTLrs> {
MODE_W::new(self, 10)
}
#[doc = "Bit 13 - DTG clock select"]
#[inline(always)]
pub fn dtgclk(&mut self) -> DTGCLK_W<TX_CTLrs> {
DTGCLK_W::new(self, 13)
}
}
#[doc = "Timer Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_CTLrs;
impl crate::RegisterSpec for TX_CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_ctl::R`](R) reader structure"]
impl crate::Readable for TX_CTLrs {}
#[doc = "`write(|w| ..)` method takes [`tx_ctl::W`](W) writer structure"]
impl crate::Writable for TX_CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TxCTL to value 0"]
impl crate::Resettable for TX_CTLrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TxPRD (rw) register accessor: timer period\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_prd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_prd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_prd`]
module"]
#[doc(alias = "TxPRD")]
pub type TX_PRD = crate::Reg<tx_prd::TX_PRDrs>;
#[doc = "timer period"]
pub mod tx_prd {
#[doc = "Register `TxPRD` reader"]
pub type R = crate::R<TX_PRDrs>;
#[doc = "Register `TxPRD` writer"]
pub type W = crate::W<TX_PRDrs>;
#[doc = "Field `PERIOD` reader - timer period value"]
pub type PERIOD_R = crate::FieldReader<u16>;
#[doc = "Field `PERIOD` writer - timer period value"]
pub type PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - timer period value"]
#[inline(always)]
pub fn period(&self) -> PERIOD_R {
PERIOD_R::new((self.bits & 0xffff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxPRD")
.field("period", &self.period())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - timer period value"]
#[inline(always)]
pub fn period(&mut self) -> PERIOD_W<TX_PRDrs> {
PERIOD_W::new(self, 0)
}
}
#[doc = "timer period\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_prd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_prd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_PRDrs;
impl crate::RegisterSpec for TX_PRDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_prd::R`](R) reader structure"]
impl crate::Readable for TX_PRDrs {}
#[doc = "`write(|w| ..)` method takes [`tx_prd::W`](W) writer structure"]
impl crate::Writable for TX_PRDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TxPRD to value 0"]
impl crate::Resettable for TX_PRDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TxCTR (r) register accessor: timer counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_ctr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_ctr`]
module"]
#[doc(alias = "TxCTR")]
pub type TX_CTR = crate::Reg<tx_ctr::TX_CTRrs>;
#[doc = "timer counter"]
pub mod tx_ctr {
#[doc = "Register `TxCTR` reader"]
pub type R = crate::R<TX_CTRrs>;
#[doc = "Field `CTR` reader - timer counter value"]
pub type CTR_R = crate::FieldReader<u16>;
impl R {
#[doc = "Bits 0:15 - timer counter value"]
#[inline(always)]
pub fn ctr(&self) -> CTR_R {
CTR_R::new((self.bits & 0xffff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxCTR").field("ctr", &self.ctr()).finish()
}
}
#[doc = "timer counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_ctr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_CTRrs;
impl crate::RegisterSpec for TX_CTRrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_ctr::R`](R) reader structure"]
impl crate::Readable for TX_CTRrs {}
#[doc = "`reset()` method sets TxCTR to value 0"]
impl crate::Resettable for TX_CTRrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TxCC0CTL (rw) register accessor: timer capture and compare control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc0ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc0ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_cc0ctl`]
module"]
#[doc(alias = "TxCC0CTL")]
pub type TX_CC0CTL = crate::Reg<tx_cc0ctl::TX_CC0CTLrs>;
#[doc = "timer capture and compare control unit 0"]
pub mod tx_cc0ctl {
#[doc = "Register `TxCC0CTL` reader"]
pub type R = crate::R<TX_CC0CTLrs>;
#[doc = "Register `TxCC0CTL` writer"]
pub type W = crate::W<TX_CC0CTLrs>;
#[doc = "capture mode edge detect\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum CCEDG {
#[doc = "0: high to low transition only"]
Hitolow = 0,
#[doc = "1: low to high transitions only"]
Lowtohigh = 1,
#[doc = "2: both high to low and low to high transitions"]
Both = 2,
}
impl From<CCEDG> for u8 {
#[inline(always)]
fn from(variant: CCEDG) -> Self {
variant as _
}
}
impl crate::FieldSpec for CCEDG {
type Ux = u8;
}
impl crate::IsEnum for CCEDG {}
#[doc = "Field `CCEDG` reader - capture mode edge detect"]
pub type CCEDG_R = crate::FieldReader<CCEDG>;
impl CCEDG_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<CCEDG> {
match self.bits {
0 => Some(CCEDG::Hitolow),
1 => Some(CCEDG::Lowtohigh),
2 => Some(CCEDG::Both),
_ => None,
}
}
#[doc = "high to low transition only"]
#[inline(always)]
pub fn is_hitolow(&self) -> bool {
*self == CCEDG::Hitolow
}
#[doc = "low to high transitions only"]
#[inline(always)]
pub fn is_lowtohigh(&self) -> bool {
*self == CCEDG::Lowtohigh
}
#[doc = "both high to low and low to high transitions"]
#[inline(always)]
pub fn is_both(&self) -> bool {
*self == CCEDG::Both
}
}
#[doc = "Field `CCEDG` writer - capture mode edge detect"]
pub type CCEDG_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CCEDG>;
impl<'a, REG> CCEDG_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "high to low transition only"]
#[inline(always)]
pub fn hitolow(self) -> &'a mut crate::W<REG> {
self.variant(CCEDG::Hitolow)
}
#[doc = "low to high transitions only"]
#[inline(always)]
pub fn lowtohigh(self) -> &'a mut crate::W<REG> {
self.variant(CCEDG::Lowtohigh)
}
#[doc = "both high to low and low to high transitions"]
#[inline(always)]
pub fn both(self) -> &'a mut crate::W<REG> {
self.variant(CCEDG::Both)
}
}
#[doc = "capture and compare interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CCINT {
#[doc = "0: no interrupt detected"]
None = 0,
#[doc = "1: interrupt, write 1b to clear"]
Interrupt = 1,
}
impl From<CCINT> for bool {
#[inline(always)]
fn from(variant: CCINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCINT` reader - capture and compare interrupt"]
pub type CCINT_R = crate::BitReader<CCINT>;
impl CCINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CCINT {
match self.bits {
false => CCINT::None,
true => CCINT::Interrupt,
}
}
#[doc = "no interrupt detected"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == CCINT::None
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == CCINT::Interrupt
}
}
#[doc = "Field `CCINT` writer - capture and compare interrupt"]
pub type CCINT_W<'a, REG> = crate::BitWriter<'a, REG, CCINT>;
impl<'a, REG> CCINT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "no interrupt detected"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(CCINT::None)
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(CCINT::Interrupt)
}
}
#[doc = "capture and compare interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CCINTEN {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<CCINTEN> for bool {
#[inline(always)]
fn from(variant: CCINTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCINTEN` reader - capture and compare interrupt enable"]
pub type CCINTEN_R = crate::BitReader<CCINTEN>;
impl CCINTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CCINTEN {
match self.bits {
false => CCINTEN::Disabled,
true => CCINTEN::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == CCINTEN::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == CCINTEN::Enabled
}
}
#[doc = "Field `CCINTEN` writer - capture and compare interrupt enable"]
pub type CCINTEN_W<'a, REG> = crate::BitWriter<'a, REG, CCINTEN>;
impl<'a, REG> CCINTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(CCINTEN::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(CCINTEN::Enabled)
}
}
#[doc = "capture and compare mode\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CCMODE {
#[doc = "0: compare mode"]
CompareMode = 0,
#[doc = "1: capture mode"]
CaptureMode = 1,
}
impl From<CCMODE> for bool {
#[inline(always)]
fn from(variant: CCMODE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCMODE` reader - capture and compare mode"]
pub type CCMODE_R = crate::BitReader<CCMODE>;
impl CCMODE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CCMODE {
match self.bits {
false => CCMODE::CompareMode,
true => CCMODE::CaptureMode,
}
}
#[doc = "compare mode"]
#[inline(always)]
pub fn is_compare_mode(&self) -> bool {
*self == CCMODE::CompareMode
}
#[doc = "capture mode"]
#[inline(always)]
pub fn is_capture_mode(&self) -> bool {
*self == CCMODE::CaptureMode
}
}
#[doc = "Field `CCMODE` writer - capture and compare mode"]
pub type CCMODE_W<'a, REG> = crate::BitWriter<'a, REG, CCMODE>;
impl<'a, REG> CCMODE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "compare mode"]
#[inline(always)]
pub fn compare_mode(self) -> &'a mut crate::W<REG> {
self.variant(CCMODE::CompareMode)
}
#[doc = "capture mode"]
#[inline(always)]
pub fn capture_mode(self) -> &'a mut crate::W<REG> {
self.variant(CCMODE::CaptureMode)
}
}
impl R {
#[doc = "Bits 0:1 - capture mode edge detect"]
#[inline(always)]
pub fn ccedg(&self) -> CCEDG_R {
CCEDG_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - capture and compare interrupt"]
#[inline(always)]
pub fn ccint(&self) -> CCINT_R {
CCINT_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - capture and compare interrupt enable"]
#[inline(always)]
pub fn ccinten(&self) -> CCINTEN_R {
CCINTEN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - capture and compare mode"]
#[inline(always)]
pub fn ccmode(&self) -> CCMODE_R {
CCMODE_R::new(((self.bits >> 4) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxCC0CTL")
.field("ccedg", &self.ccedg())
.field("ccint", &self.ccint())
.field("ccinten", &self.ccinten())
.field("ccmode", &self.ccmode())
.finish()
}
}
impl W {
#[doc = "Bits 0:1 - capture mode edge detect"]
#[inline(always)]
pub fn ccedg(&mut self) -> CCEDG_W<TX_CC0CTLrs> {
CCEDG_W::new(self, 0)
}
#[doc = "Bit 2 - capture and compare interrupt"]
#[inline(always)]
pub fn ccint(&mut self) -> CCINT_W<TX_CC0CTLrs> {
CCINT_W::new(self, 2)
}
#[doc = "Bit 3 - capture and compare interrupt enable"]
#[inline(always)]
pub fn ccinten(&mut self) -> CCINTEN_W<TX_CC0CTLrs> {
CCINTEN_W::new(self, 3)
}
#[doc = "Bit 4 - capture and compare mode"]
#[inline(always)]
pub fn ccmode(&mut self) -> CCMODE_W<TX_CC0CTLrs> {
CCMODE_W::new(self, 4)
}
}
#[doc = "timer capture and compare control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc0ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc0ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_CC0CTLrs;
impl crate::RegisterSpec for TX_CC0CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_cc0ctl::R`](R) reader structure"]
impl crate::Readable for TX_CC0CTLrs {}
#[doc = "`write(|w| ..)` method takes [`tx_cc0ctl::W`](W) writer structure"]
impl crate::Writable for TX_CC0CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TxCC0CTL to value 0"]
impl crate::Resettable for TX_CC0CTLrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TxCC0CTR (rw) register accessor: capture and compare counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc0ctr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc0ctr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_cc0ctr`]
module"]
#[doc(alias = "TxCC0CTR")]
pub type TX_CC0CTR = crate::Reg<tx_cc0ctr::TX_CC0CTRrs>;
#[doc = "capture and compare counter unit 0"]
pub mod tx_cc0ctr {
#[doc = "Register `TxCC0CTR` reader"]
pub type R = crate::R<TX_CC0CTRrs>;
#[doc = "Register `TxCC0CTR` writer"]
pub type W = crate::W<TX_CC0CTRrs>;
#[doc = "Field `CCCTR` reader - capture and compare counter value"]
pub type CCCTR_R = crate::FieldReader<u16>;
#[doc = "Field `CCCTR` writer - capture and compare counter value"]
pub type CCCTR_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - capture and compare counter value"]
#[inline(always)]
pub fn ccctr(&self) -> CCCTR_R {
CCCTR_R::new((self.bits & 0xffff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxCC0CTR")
.field("ccctr", &self.ccctr())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - capture and compare counter value"]
#[inline(always)]
pub fn ccctr(&mut self) -> CCCTR_W<TX_CC0CTRrs> {
CCCTR_W::new(self, 0)
}
}
#[doc = "capture and compare counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc0ctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc0ctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_CC0CTRrs;
impl crate::RegisterSpec for TX_CC0CTRrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_cc0ctr::R`](R) reader structure"]
impl crate::Readable for TX_CC0CTRrs {}
#[doc = "`write(|w| ..)` method takes [`tx_cc0ctr::W`](W) writer structure"]
impl crate::Writable for TX_CC0CTRrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TxCC0CTR to value 0"]
impl crate::Resettable for TX_CC0CTRrs {
const RESET_VALUE: u32 = 0;
}
}
pub use tx_cc0ctl as tx_cc1ctl;
pub use tx_cc0ctr as tx_cc1ctr;
pub use TX_CC0CTL as TX_CC1CTL;
pub use TX_CC0CTR as TX_CC1CTR;
#[doc = "DTGC0CTL (rw) register accessor: Timer C dead-time generator control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgc0ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgc0ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtgc0ctl`]
module"]
pub type DTGC0CTL = crate::Reg<dtgc0ctl::DTGC0CTLrs>;
#[doc = "Timer C dead-time generator control unit 0"]
pub mod dtgc0ctl {
#[doc = "Register `DTGC0CTL` reader"]
pub type R = crate::R<DTGC0CTLrs>;
#[doc = "Register `DTGC0CTL` writer"]
pub type W = crate::W<DTGC0CTLrs>;
#[doc = "Invert low-side output signal\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INVLS {
#[doc = "0: do not invert low-side output signal"]
Disabled = 0,
#[doc = "1: invert low-side output signal"]
Enabled = 1,
}
impl From<INVLS> for bool {
#[inline(always)]
fn from(variant: INVLS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INVLS` reader - Invert low-side output signal"]
pub type INVLS_R = crate::BitReader<INVLS>;
impl INVLS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INVLS {
match self.bits {
false => INVLS::Disabled,
true => INVLS::Enabled,
}
}
#[doc = "do not invert low-side output signal"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INVLS::Disabled
}
#[doc = "invert low-side output signal"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INVLS::Enabled
}
}
#[doc = "Field `INVLS` writer - Invert low-side output signal"]
pub type INVLS_W<'a, REG> = crate::BitWriter<'a, REG, INVLS>;
impl<'a, REG> INVLS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not invert low-side output signal"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INVLS::Disabled)
}
#[doc = "invert low-side output signal"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INVLS::Enabled)
}
}
#[doc = "Invert high-side output signal\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INVHS {
#[doc = "0: do not invert high-side output signal"]
Disabled = 0,
#[doc = "1: invert high-side output signal"]
Enabled = 1,
}
impl From<INVHS> for bool {
#[inline(always)]
fn from(variant: INVHS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INVHS` reader - Invert high-side output signal"]
pub type INVHS_R = crate::BitReader<INVHS>;
impl INVHS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INVHS {
match self.bits {
false => INVHS::Disabled,
true => INVHS::Enabled,
}
}
#[doc = "do not invert high-side output signal"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INVHS::Disabled
}
#[doc = "invert high-side output signal"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INVHS::Enabled
}
}
#[doc = "Field `INVHS` writer - Invert high-side output signal"]
pub type INVHS_W<'a, REG> = crate::BitWriter<'a, REG, INVHS>;
impl<'a, REG> INVHS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not invert high-side output signal"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INVHS::Disabled)
}
#[doc = "invert high-side output signal"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INVHS::Enabled)
}
}
#[doc = "On-time preservation\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum OTP {
#[doc = "0: do not extend on time"]
Disabled = 0,
#[doc = "1: extend on time"]
Enabled = 1,
}
impl From<OTP> for bool {
#[inline(always)]
fn from(variant: OTP) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OTP` reader - On-time preservation"]
pub type OTP_R = crate::BitReader<OTP>;
impl OTP_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> OTP {
match self.bits {
false => OTP::Disabled,
true => OTP::Enabled,
}
}
#[doc = "do not extend on time"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == OTP::Disabled
}
#[doc = "extend on time"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == OTP::Enabled
}
}
#[doc = "Field `OTP` writer - On-time preservation"]
pub type OTP_W<'a, REG> = crate::BitWriter<'a, REG, OTP>;
impl<'a, REG> OTP_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not extend on time"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(OTP::Disabled)
}
#[doc = "extend on time"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(OTP::Enabled)
}
}
#[doc = "bypass dead-time generation\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum BYPASS {
#[doc = "0: do not bypass dead-time generation"]
Disabled = 0,
#[doc = "1: bypass dead-time generation"]
Enabled = 1,
}
impl From<BYPASS> for bool {
#[inline(always)]
fn from(variant: BYPASS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `BYPASS` reader - bypass dead-time generation"]
pub type BYPASS_R = crate::BitReader<BYPASS>;
impl BYPASS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> BYPASS {
match self.bits {
false => BYPASS::Disabled,
true => BYPASS::Enabled,
}
}
#[doc = "do not bypass dead-time generation"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == BYPASS::Disabled
}
#[doc = "bypass dead-time generation"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == BYPASS::Enabled
}
}
#[doc = "Field `BYPASS` writer - bypass dead-time generation"]
pub type BYPASS_W<'a, REG> = crate::BitWriter<'a, REG, BYPASS>;
impl<'a, REG> BYPASS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not bypass dead-time generation"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(BYPASS::Disabled)
}
#[doc = "bypass dead-time generation"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(BYPASS::Enabled)
}
}
impl R {
#[doc = "Bit 4 - Invert low-side output signal"]
#[inline(always)]
pub fn invls(&self) -> INVLS_R {
INVLS_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Invert high-side output signal"]
#[inline(always)]
pub fn invhs(&self) -> INVHS_R {
INVHS_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - On-time preservation"]
#[inline(always)]
pub fn otp(&self) -> OTP_R {
OTP_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - bypass dead-time generation"]
#[inline(always)]
pub fn bypass(&self) -> BYPASS_R {
BYPASS_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGC0CTL")
.field("invls", &self.invls())
.field("invhs", &self.invhs())
.field("otp", &self.otp())
.field("bypass", &self.bypass())
.finish()
}
}
impl W {
#[doc = "Bit 4 - Invert low-side output signal"]
#[inline(always)]
pub fn invls(&mut self) -> INVLS_W<DTGC0CTLrs> {
INVLS_W::new(self, 4)
}
#[doc = "Bit 5 - Invert high-side output signal"]
#[inline(always)]
pub fn invhs(&mut self) -> INVHS_W<DTGC0CTLrs> {
INVHS_W::new(self, 5)
}
#[doc = "Bit 6 - On-time preservation"]
#[inline(always)]
pub fn otp(&mut self) -> OTP_W<DTGC0CTLrs> {
OTP_W::new(self, 6)
}
#[doc = "Bit 7 - bypass dead-time generation"]
#[inline(always)]
pub fn bypass(&mut self) -> BYPASS_W<DTGC0CTLrs> {
BYPASS_W::new(self, 7)
}
}
#[doc = "Timer C dead-time generator control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgc0ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgc0ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGC0CTLrs;
impl crate::RegisterSpec for DTGC0CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtgc0ctl::R`](R) reader structure"]
impl crate::Readable for DTGC0CTLrs {}
#[doc = "`write(|w| ..)` method takes [`dtgc0ctl::W`](W) writer structure"]
impl crate::Writable for DTGC0CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGC0CTL to value 0x80"]
impl crate::Resettable for DTGC0CTLrs {
const RESET_VALUE: u32 = 0x80;
}
}
#[doc = "DTGC0LED (rw) register accessor: Timer C dead-time generator leading-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgc0led::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgc0led::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtgc0led`]
module"]
pub type DTGC0LED = crate::Reg<dtgc0led::DTGC0LEDrs>;
#[doc = "Timer C dead-time generator leading-edge delay counter unit 0"]
pub mod dtgc0led {
#[doc = "Register `DTGC0LED` reader"]
pub type R = crate::R<DTGC0LEDrs>;
#[doc = "Register `DTGC0LED` writer"]
pub type W = crate::W<DTGC0LEDrs>;
#[doc = "Field `LED` reader - leading-edge delay counter"]
pub type LED_R = crate::FieldReader<u16>;
#[doc = "Field `LED` writer - leading-edge delay counter"]
pub type LED_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:11 - leading-edge delay counter"]
#[inline(always)]
pub fn led(&self) -> LED_R {
LED_R::new((self.bits & 0x0fff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGC0LED")
.field("led", &self.led())
.finish()
}
}
impl W {
#[doc = "Bits 0:11 - leading-edge delay counter"]
#[inline(always)]
pub fn led(&mut self) -> LED_W<DTGC0LEDrs> {
LED_W::new(self, 0)
}
}
#[doc = "Timer C dead-time generator leading-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgc0led::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgc0led::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGC0LEDrs;
impl crate::RegisterSpec for DTGC0LEDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtgc0led::R`](R) reader structure"]
impl crate::Readable for DTGC0LEDrs {}
#[doc = "`write(|w| ..)` method takes [`dtgc0led::W`](W) writer structure"]
impl crate::Writable for DTGC0LEDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGC0LED to value 0"]
impl crate::Resettable for DTGC0LEDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DTGC0TED (rw) register accessor: Timer C dead-time generator trailing-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgc0ted::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgc0ted::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtgc0ted`]
module"]
pub type DTGC0TED = crate::Reg<dtgc0ted::DTGC0TEDrs>;
#[doc = "Timer C dead-time generator trailing-edge delay counter unit 0"]
pub mod dtgc0ted {
#[doc = "Register `DTGC0TED` reader"]
pub type R = crate::R<DTGC0TEDrs>;
#[doc = "Register `DTGC0TED` writer"]
pub type W = crate::W<DTGC0TEDrs>;
#[doc = "Field `TED` reader - trailing-edge delay counter"]
pub type TED_R = crate::FieldReader<u16>;
#[doc = "Field `TED` writer - trailing-edge delay counter"]
pub type TED_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:11 - trailing-edge delay counter"]
#[inline(always)]
pub fn ted(&self) -> TED_R {
TED_R::new((self.bits & 0x0fff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGC0TED")
.field("ted", &self.ted())
.finish()
}
}
impl W {
#[doc = "Bits 0:11 - trailing-edge delay counter"]
#[inline(always)]
pub fn ted(&mut self) -> TED_W<DTGC0TEDrs> {
TED_W::new(self, 0)
}
}
#[doc = "Timer C dead-time generator trailing-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgc0ted::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgc0ted::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGC0TEDrs;
impl crate::RegisterSpec for DTGC0TEDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtgc0ted::R`](R) reader structure"]
impl crate::Readable for DTGC0TEDrs {}
#[doc = "`write(|w| ..)` method takes [`dtgc0ted::W`](W) writer structure"]
impl crate::Writable for DTGC0TEDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGC0TED to value 0"]
impl crate::Resettable for DTGC0TEDrs {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "Timer D Peripheral"]
pub struct TIMERD {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIMERD {}
impl TIMERD {
#[doc = r"Pointer to the register block"]
pub const PTR: *const timerd::RegisterBlock = 0x4010_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const timerd::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for TIMERD {
type Target = timerd::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for TIMERD {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIMERD").finish()
}
}
#[doc = "Timer D Peripheral"]
pub mod timerd {
#[repr(C)]
#[derive(Debug)]
#[doc = "Register block"]
pub struct RegisterBlock {
tx_ctl: TX_CTL,
tx_prd: TX_PRD,
tx_ctr: TX_CTR,
_reserved3: [u8; 0x34],
tx_cc0ctl: TX_CC0CTL,
tx_cc0ctr: TX_CC0CTR,
tx_cc1ctl: TX_CC1CTL,
tx_cc1ctr: TX_CC1CTR,
_reserved7: [u8; 0x50],
dtgd0ctl: DTGD0CTL,
dtgd0led: DTGD0LED,
dtgd0ted: DTGD0TED,
}
impl RegisterBlock {
#[doc = "0x00 - Timer Control Register"]
#[inline(always)]
pub const fn tx_ctl(&self) -> &TX_CTL {
&self.tx_ctl
}
#[doc = "0x04 - timer period"]
#[inline(always)]
pub const fn tx_prd(&self) -> &TX_PRD {
&self.tx_prd
}
#[doc = "0x08 - timer counter"]
#[inline(always)]
pub const fn tx_ctr(&self) -> &TX_CTR {
&self.tx_ctr
}
#[doc = "0x40 - timer capture and compare control unit 0"]
#[inline(always)]
pub const fn tx_cc0ctl(&self) -> &TX_CC0CTL {
&self.tx_cc0ctl
}
#[doc = "0x44 - capture and compare counter unit 0"]
#[inline(always)]
pub const fn tx_cc0ctr(&self) -> &TX_CC0CTR {
&self.tx_cc0ctr
}
#[doc = "0x48 - timer capture and compare control unit 1"]
#[inline(always)]
pub const fn tx_cc1ctl(&self) -> &TX_CC1CTL {
&self.tx_cc1ctl
}
#[doc = "0x4c - capture and compare counter unit 1"]
#[inline(always)]
pub const fn tx_cc1ctr(&self) -> &TX_CC1CTR {
&self.tx_cc1ctr
}
#[doc = "0xa0 - Timer A dead-time generator control unit 0"]
#[inline(always)]
pub const fn dtgd0ctl(&self) -> &DTGD0CTL {
&self.dtgd0ctl
}
#[doc = "0xa4 - Timer A dead-time generator leading-edge delay counter unit 0"]
#[inline(always)]
pub const fn dtgd0led(&self) -> &DTGD0LED {
&self.dtgd0led
}
#[doc = "0xa8 - Timer A dead-time generator trailing-edge delay counter unit 0"]
#[inline(always)]
pub const fn dtgd0ted(&self) -> &DTGD0TED {
&self.dtgd0ted
}
}
#[doc = "TxCTL (rw) register accessor: Timer Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_ctl`]
module"]
#[doc(alias = "TxCTL")]
pub type TX_CTL = crate::Reg<tx_ctl::TX_CTLrs>;
#[doc = "Timer Control Register"]
pub mod tx_ctl {
#[doc = "Register `TxCTL` reader"]
pub type R = crate::R<TX_CTLrs>;
#[doc = "Register `TxCTL` writer"]
pub type W = crate::W<TX_CTLrs>;
#[doc = "Timer Period Latch\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum PRDL {
#[doc = "0: Latch timer values counting up at TxPRD-1"]
Period = 0,
#[doc = "1: Latch timer values when counting down to 1"]
Wrap = 1,
}
impl From<PRDL> for bool {
#[inline(always)]
fn from(variant: PRDL) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `PRDL` reader - Timer Period Latch"]
pub type PRDL_R = crate::BitReader<PRDL>;
impl PRDL_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> PRDL {
match self.bits {
false => PRDL::Period,
true => PRDL::Wrap,
}
}
#[doc = "Latch timer values counting up at TxPRD-1"]
#[inline(always)]
pub fn is_period(&self) -> bool {
*self == PRDL::Period
}
#[doc = "Latch timer values when counting down to 1"]
#[inline(always)]
pub fn is_wrap(&self) -> bool {
*self == PRDL::Wrap
}
}
#[doc = "Field `PRDL` writer - Timer Period Latch"]
pub type PRDL_W<'a, REG> = crate::BitWriter<'a, REG, PRDL>;
impl<'a, REG> PRDL_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Latch timer values counting up at TxPRD-1"]
#[inline(always)]
pub fn period(self) -> &'a mut crate::W<REG> {
self.variant(PRDL::Period)
}
#[doc = "Latch timer values when counting down to 1"]
#[inline(always)]
pub fn wrap(self) -> &'a mut crate::W<REG> {
self.variant(PRDL::Wrap)
}
}
#[doc = "Timer clear\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CLR {
#[doc = "0: Clear Timer, hold in reset, set SYNC_OUT"]
Clear = 0,
#[doc = "1: Do not clear timer, clear SYNC_OUT"]
Noclear = 1,
}
impl From<CLR> for bool {
#[inline(always)]
fn from(variant: CLR) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CLR` reader - Timer clear"]
pub type CLR_R = crate::BitReader<CLR>;
impl CLR_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CLR {
match self.bits {
false => CLR::Clear,
true => CLR::Noclear,
}
}
#[doc = "Clear Timer, hold in reset, set SYNC_OUT"]
#[inline(always)]
pub fn is_clear(&self) -> bool {
*self == CLR::Clear
}
#[doc = "Do not clear timer, clear SYNC_OUT"]
#[inline(always)]
pub fn is_noclear(&self) -> bool {
*self == CLR::Noclear
}
}
#[doc = "Field `CLR` writer - Timer clear"]
pub type CLR_W<'a, REG> = crate::BitWriter<'a, REG, CLR>;
impl<'a, REG> CLR_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Clear Timer, hold in reset, set SYNC_OUT"]
#[inline(always)]
pub fn clear(self) -> &'a mut crate::W<REG> {
self.variant(CLR::Clear)
}
#[doc = "Do not clear timer, clear SYNC_OUT"]
#[inline(always)]
pub fn noclear(self) -> &'a mut crate::W<REG> {
self.variant(CLR::Noclear)
}
}
#[doc = "Timer single shot\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SS {
#[doc = "0: Continuous mode"]
Continuous = 0,
#[doc = "1: Single shot mode"]
Single = 1,
}
impl From<SS> for bool {
#[inline(always)]
fn from(variant: SS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SS` reader - Timer single shot"]
pub type SS_R = crate::BitReader<SS>;
impl SS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SS {
match self.bits {
false => SS::Continuous,
true => SS::Single,
}
}
#[doc = "Continuous mode"]
#[inline(always)]
pub fn is_continuous(&self) -> bool {
*self == SS::Continuous
}
#[doc = "Single shot mode"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == SS::Single
}
}
#[doc = "Field `SS` writer - Timer single shot"]
pub type SS_W<'a, REG> = crate::BitWriter<'a, REG, SS>;
impl<'a, REG> SS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Continuous mode"]
#[inline(always)]
pub fn continuous(self) -> &'a mut crate::W<REG> {
self.variant(SS::Continuous)
}
#[doc = "Single shot mode"]
#[inline(always)]
pub fn single(self) -> &'a mut crate::W<REG> {
self.variant(SS::Single)
}
}
#[doc = "Timer interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INT {
#[doc = "0: interrupt flag, write 1 to clear"]
Interrupt = 0,
#[doc = "1: No interrupt"]
Noint = 1,
}
impl From<INT> for bool {
#[inline(always)]
fn from(variant: INT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INT` reader - Timer interrupt"]
pub type INT_R = crate::BitReader<INT>;
impl INT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INT {
match self.bits {
false => INT::Interrupt,
true => INT::Noint,
}
}
#[doc = "interrupt flag, write 1 to clear"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == INT::Interrupt
}
#[doc = "No interrupt"]
#[inline(always)]
pub fn is_noint(&self) -> bool {
*self == INT::Noint
}
}
#[doc = "Field `INT` writer - Timer interrupt"]
pub type INT_W<'a, REG> = crate::BitWriter<'a, REG, INT>;
impl<'a, REG> INT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt flag, write 1 to clear"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(INT::Interrupt)
}
#[doc = "No interrupt"]
#[inline(always)]
pub fn noint(self) -> &'a mut crate::W<REG> {
self.variant(INT::Noint)
}
}
#[doc = "Timer interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INTEN {
#[doc = "0: timer interrupt enabled"]
Enabled = 0,
#[doc = "1: timer interrupt disabled"]
Disabled = 1,
}
impl From<INTEN> for bool {
#[inline(always)]
fn from(variant: INTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INTEN` reader - Timer interrupt enable"]
pub type INTEN_R = crate::BitReader<INTEN>;
impl INTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INTEN {
match self.bits {
false => INTEN::Enabled,
true => INTEN::Disabled,
}
}
#[doc = "timer interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INTEN::Enabled
}
#[doc = "timer interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INTEN::Disabled
}
}
#[doc = "Field `INTEN` writer - Timer interrupt enable"]
pub type INTEN_W<'a, REG> = crate::BitWriter<'a, REG, INTEN>;
impl<'a, REG> INTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "timer interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INTEN::Enabled)
}
#[doc = "timer interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INTEN::Disabled)
}
}
#[doc = "timer clock divider\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum CLKDIV {
#[doc = "0: divide by 1"]
Div1 = 0,
#[doc = "1: divide by 2"]
Div2 = 1,
#[doc = "2: divide by 4"]
Div4 = 2,
#[doc = "3: divide by 8"]
Div8 = 3,
#[doc = "4: divide by 16"]
Div16 = 4,
#[doc = "5: divide by 32"]
Div32 = 5,
#[doc = "6: divide by 64"]
Div64 = 6,
#[doc = "7: divide by 128"]
Div128 = 7,
}
impl From<CLKDIV> for u8 {
#[inline(always)]
fn from(variant: CLKDIV) -> Self {
variant as _
}
}
impl crate::FieldSpec for CLKDIV {
type Ux = u8;
}
impl crate::IsEnum for CLKDIV {}
#[doc = "Field `CLKDIV` reader - timer clock divider"]
pub type CLKDIV_R = crate::FieldReader<CLKDIV>;
impl CLKDIV_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CLKDIV {
match self.bits {
0 => CLKDIV::Div1,
1 => CLKDIV::Div2,
2 => CLKDIV::Div4,
3 => CLKDIV::Div8,
4 => CLKDIV::Div16,
5 => CLKDIV::Div32,
6 => CLKDIV::Div64,
7 => CLKDIV::Div128,
_ => unreachable!(),
}
}
#[doc = "divide by 1"]
#[inline(always)]
pub fn is_div_1(&self) -> bool {
*self == CLKDIV::Div1
}
#[doc = "divide by 2"]
#[inline(always)]
pub fn is_div_2(&self) -> bool {
*self == CLKDIV::Div2
}
#[doc = "divide by 4"]
#[inline(always)]
pub fn is_div_4(&self) -> bool {
*self == CLKDIV::Div4
}
#[doc = "divide by 8"]
#[inline(always)]
pub fn is_div_8(&self) -> bool {
*self == CLKDIV::Div8
}
#[doc = "divide by 16"]
#[inline(always)]
pub fn is_div_16(&self) -> bool {
*self == CLKDIV::Div16
}
#[doc = "divide by 32"]
#[inline(always)]
pub fn is_div_32(&self) -> bool {
*self == CLKDIV::Div32
}
#[doc = "divide by 64"]
#[inline(always)]
pub fn is_div_64(&self) -> bool {
*self == CLKDIV::Div64
}
#[doc = "divide by 128"]
#[inline(always)]
pub fn is_div_128(&self) -> bool {
*self == CLKDIV::Div128
}
}
#[doc = "Field `CLKDIV` writer - timer clock divider"]
pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CLKDIV, crate::Safe>;
impl<'a, REG> CLKDIV_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "divide by 1"]
#[inline(always)]
pub fn div_1(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div1)
}
#[doc = "divide by 2"]
#[inline(always)]
pub fn div_2(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div2)
}
#[doc = "divide by 4"]
#[inline(always)]
pub fn div_4(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div4)
}
#[doc = "divide by 8"]
#[inline(always)]
pub fn div_8(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div8)
}
#[doc = "divide by 16"]
#[inline(always)]
pub fn div_16(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div16)
}
#[doc = "divide by 32"]
#[inline(always)]
pub fn div_32(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div32)
}
#[doc = "divide by 64"]
#[inline(always)]
pub fn div_64(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div64)
}
#[doc = "divide by 128"]
#[inline(always)]
pub fn div_128(self) -> &'a mut crate::W<REG> {
self.variant(CLKDIV::Div128)
}
}
#[doc = "timer clock input source\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CLK {
#[doc = "0: HCLK"]
Hclk = 0,
#[doc = "1: ACLK"]
Aclk = 1,
}
impl From<CLK> for bool {
#[inline(always)]
fn from(variant: CLK) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CLK` reader - timer clock input source"]
pub type CLK_R = crate::BitReader<CLK>;
impl CLK_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CLK {
match self.bits {
false => CLK::Hclk,
true => CLK::Aclk,
}
}
#[doc = "HCLK"]
#[inline(always)]
pub fn is_hclk(&self) -> bool {
*self == CLK::Hclk
}
#[doc = "ACLK"]
#[inline(always)]
pub fn is_aclk(&self) -> bool {
*self == CLK::Aclk
}
}
#[doc = "Field `CLK` writer - timer clock input source"]
pub type CLK_W<'a, REG> = crate::BitWriter<'a, REG, CLK>;
impl<'a, REG> CLK_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "HCLK"]
#[inline(always)]
pub fn hclk(self) -> &'a mut crate::W<REG> {
self.variant(CLK::Hclk)
}
#[doc = "ACLK"]
#[inline(always)]
pub fn aclk(self) -> &'a mut crate::W<REG> {
self.variant(CLK::Aclk)
}
}
#[doc = "timer mode\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum MODE {
#[doc = "0: timer disabled"]
Disabled = 0,
#[doc = "1: up mode"]
Up = 1,
#[doc = "2: up/down mode"]
Updown = 2,
}
impl From<MODE> for u8 {
#[inline(always)]
fn from(variant: MODE) -> Self {
variant as _
}
}
impl crate::FieldSpec for MODE {
type Ux = u8;
}
impl crate::IsEnum for MODE {}
#[doc = "Field `MODE` reader - timer mode"]
pub type MODE_R = crate::FieldReader<MODE>;
impl MODE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<MODE> {
match self.bits {
0 => Some(MODE::Disabled),
1 => Some(MODE::Up),
2 => Some(MODE::Updown),
_ => None,
}
}
#[doc = "timer disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == MODE::Disabled
}
#[doc = "up mode"]
#[inline(always)]
pub fn is_up(&self) -> bool {
*self == MODE::Up
}
#[doc = "up/down mode"]
#[inline(always)]
pub fn is_updown(&self) -> bool {
*self == MODE::Updown
}
}
#[doc = "Field `MODE` writer - timer mode"]
pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, MODE>;
impl<'a, REG> MODE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "timer disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(MODE::Disabled)
}
#[doc = "up mode"]
#[inline(always)]
pub fn up(self) -> &'a mut crate::W<REG> {
self.variant(MODE::Up)
}
#[doc = "up/down mode"]
#[inline(always)]
pub fn updown(self) -> &'a mut crate::W<REG> {
self.variant(MODE::Updown)
}
}
#[doc = "DTG clock select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum DTGCLK {
#[doc = "0: DTG uses clock selected by TxTCL.CLK"]
Clk = 0,
#[doc = "1: DTG uses clock selected by TxCTL.CLKDIV"]
Clkdiv = 1,
}
impl From<DTGCLK> for bool {
#[inline(always)]
fn from(variant: DTGCLK) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `DTGCLK` reader - DTG clock select"]
pub type DTGCLK_R = crate::BitReader<DTGCLK>;
impl DTGCLK_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> DTGCLK {
match self.bits {
false => DTGCLK::Clk,
true => DTGCLK::Clkdiv,
}
}
#[doc = "DTG uses clock selected by TxTCL.CLK"]
#[inline(always)]
pub fn is_clk(&self) -> bool {
*self == DTGCLK::Clk
}
#[doc = "DTG uses clock selected by TxCTL.CLKDIV"]
#[inline(always)]
pub fn is_clkdiv(&self) -> bool {
*self == DTGCLK::Clkdiv
}
}
#[doc = "Field `DTGCLK` writer - DTG clock select"]
pub type DTGCLK_W<'a, REG> = crate::BitWriter<'a, REG, DTGCLK>;
impl<'a, REG> DTGCLK_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "DTG uses clock selected by TxTCL.CLK"]
#[inline(always)]
pub fn clk(self) -> &'a mut crate::W<REG> {
self.variant(DTGCLK::Clk)
}
#[doc = "DTG uses clock selected by TxCTL.CLKDIV"]
#[inline(always)]
pub fn clkdiv(self) -> &'a mut crate::W<REG> {
self.variant(DTGCLK::Clkdiv)
}
}
impl R {
#[doc = "Bit 0 - Timer Period Latch"]
#[inline(always)]
pub fn prdl(&self) -> PRDL_R {
PRDL_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 2 - Timer clear"]
#[inline(always)]
pub fn clr(&self) -> CLR_R {
CLR_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Timer single shot"]
#[inline(always)]
pub fn ss(&self) -> SS_R {
SS_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Timer interrupt"]
#[inline(always)]
pub fn int(&self) -> INT_R {
INT_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Timer interrupt enable"]
#[inline(always)]
pub fn inten(&self) -> INTEN_R {
INTEN_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:8 - timer clock divider"]
#[inline(always)]
pub fn clkdiv(&self) -> CLKDIV_R {
CLKDIV_R::new(((self.bits >> 6) & 7) as u8)
}
#[doc = "Bit 9 - timer clock input source"]
#[inline(always)]
pub fn clk(&self) -> CLK_R {
CLK_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:11 - timer mode"]
#[inline(always)]
pub fn mode(&self) -> MODE_R {
MODE_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bit 13 - DTG clock select"]
#[inline(always)]
pub fn dtgclk(&self) -> DTGCLK_R {
DTGCLK_R::new(((self.bits >> 13) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxCTL")
.field("prdl", &self.prdl())
.field("clr", &self.clr())
.field("ss", &self.ss())
.field("int", &self.int())
.field("inten", &self.inten())
.field("clkdiv", &self.clkdiv())
.field("clk", &self.clk())
.field("mode", &self.mode())
.field("dtgclk", &self.dtgclk())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Timer Period Latch"]
#[inline(always)]
pub fn prdl(&mut self) -> PRDL_W<TX_CTLrs> {
PRDL_W::new(self, 0)
}
#[doc = "Bit 2 - Timer clear"]
#[inline(always)]
pub fn clr(&mut self) -> CLR_W<TX_CTLrs> {
CLR_W::new(self, 2)
}
#[doc = "Bit 3 - Timer single shot"]
#[inline(always)]
pub fn ss(&mut self) -> SS_W<TX_CTLrs> {
SS_W::new(self, 3)
}
#[doc = "Bit 4 - Timer interrupt"]
#[inline(always)]
pub fn int(&mut self) -> INT_W<TX_CTLrs> {
INT_W::new(self, 4)
}
#[doc = "Bit 5 - Timer interrupt enable"]
#[inline(always)]
pub fn inten(&mut self) -> INTEN_W<TX_CTLrs> {
INTEN_W::new(self, 5)
}
#[doc = "Bits 6:8 - timer clock divider"]
#[inline(always)]
pub fn clkdiv(&mut self) -> CLKDIV_W<TX_CTLrs> {
CLKDIV_W::new(self, 6)
}
#[doc = "Bit 9 - timer clock input source"]
#[inline(always)]
pub fn clk(&mut self) -> CLK_W<TX_CTLrs> {
CLK_W::new(self, 9)
}
#[doc = "Bits 10:11 - timer mode"]
#[inline(always)]
pub fn mode(&mut self) -> MODE_W<TX_CTLrs> {
MODE_W::new(self, 10)
}
#[doc = "Bit 13 - DTG clock select"]
#[inline(always)]
pub fn dtgclk(&mut self) -> DTGCLK_W<TX_CTLrs> {
DTGCLK_W::new(self, 13)
}
}
#[doc = "Timer Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_CTLrs;
impl crate::RegisterSpec for TX_CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_ctl::R`](R) reader structure"]
impl crate::Readable for TX_CTLrs {}
#[doc = "`write(|w| ..)` method takes [`tx_ctl::W`](W) writer structure"]
impl crate::Writable for TX_CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TxCTL to value 0"]
impl crate::Resettable for TX_CTLrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TxPRD (rw) register accessor: timer period\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_prd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_prd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_prd`]
module"]
#[doc(alias = "TxPRD")]
pub type TX_PRD = crate::Reg<tx_prd::TX_PRDrs>;
#[doc = "timer period"]
pub mod tx_prd {
#[doc = "Register `TxPRD` reader"]
pub type R = crate::R<TX_PRDrs>;
#[doc = "Register `TxPRD` writer"]
pub type W = crate::W<TX_PRDrs>;
#[doc = "Field `PERIOD` reader - timer period value"]
pub type PERIOD_R = crate::FieldReader<u16>;
#[doc = "Field `PERIOD` writer - timer period value"]
pub type PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - timer period value"]
#[inline(always)]
pub fn period(&self) -> PERIOD_R {
PERIOD_R::new((self.bits & 0xffff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxPRD")
.field("period", &self.period())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - timer period value"]
#[inline(always)]
pub fn period(&mut self) -> PERIOD_W<TX_PRDrs> {
PERIOD_W::new(self, 0)
}
}
#[doc = "timer period\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_prd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_prd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_PRDrs;
impl crate::RegisterSpec for TX_PRDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_prd::R`](R) reader structure"]
impl crate::Readable for TX_PRDrs {}
#[doc = "`write(|w| ..)` method takes [`tx_prd::W`](W) writer structure"]
impl crate::Writable for TX_PRDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TxPRD to value 0"]
impl crate::Resettable for TX_PRDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TxCTR (r) register accessor: timer counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_ctr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_ctr`]
module"]
#[doc(alias = "TxCTR")]
pub type TX_CTR = crate::Reg<tx_ctr::TX_CTRrs>;
#[doc = "timer counter"]
pub mod tx_ctr {
#[doc = "Register `TxCTR` reader"]
pub type R = crate::R<TX_CTRrs>;
#[doc = "Field `CTR` reader - timer counter value"]
pub type CTR_R = crate::FieldReader<u16>;
impl R {
#[doc = "Bits 0:15 - timer counter value"]
#[inline(always)]
pub fn ctr(&self) -> CTR_R {
CTR_R::new((self.bits & 0xffff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxCTR").field("ctr", &self.ctr()).finish()
}
}
#[doc = "timer counter\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_ctr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_CTRrs;
impl crate::RegisterSpec for TX_CTRrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_ctr::R`](R) reader structure"]
impl crate::Readable for TX_CTRrs {}
#[doc = "`reset()` method sets TxCTR to value 0"]
impl crate::Resettable for TX_CTRrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TxCC0CTL (rw) register accessor: timer capture and compare control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc0ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc0ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_cc0ctl`]
module"]
#[doc(alias = "TxCC0CTL")]
pub type TX_CC0CTL = crate::Reg<tx_cc0ctl::TX_CC0CTLrs>;
#[doc = "timer capture and compare control unit 0"]
pub mod tx_cc0ctl {
#[doc = "Register `TxCC0CTL` reader"]
pub type R = crate::R<TX_CC0CTLrs>;
#[doc = "Register `TxCC0CTL` writer"]
pub type W = crate::W<TX_CC0CTLrs>;
#[doc = "capture mode edge detect\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum CCEDG {
#[doc = "0: high to low transition only"]
Hitolow = 0,
#[doc = "1: low to high transitions only"]
Lowtohigh = 1,
#[doc = "2: both high to low and low to high transitions"]
Both = 2,
}
impl From<CCEDG> for u8 {
#[inline(always)]
fn from(variant: CCEDG) -> Self {
variant as _
}
}
impl crate::FieldSpec for CCEDG {
type Ux = u8;
}
impl crate::IsEnum for CCEDG {}
#[doc = "Field `CCEDG` reader - capture mode edge detect"]
pub type CCEDG_R = crate::FieldReader<CCEDG>;
impl CCEDG_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<CCEDG> {
match self.bits {
0 => Some(CCEDG::Hitolow),
1 => Some(CCEDG::Lowtohigh),
2 => Some(CCEDG::Both),
_ => None,
}
}
#[doc = "high to low transition only"]
#[inline(always)]
pub fn is_hitolow(&self) -> bool {
*self == CCEDG::Hitolow
}
#[doc = "low to high transitions only"]
#[inline(always)]
pub fn is_lowtohigh(&self) -> bool {
*self == CCEDG::Lowtohigh
}
#[doc = "both high to low and low to high transitions"]
#[inline(always)]
pub fn is_both(&self) -> bool {
*self == CCEDG::Both
}
}
#[doc = "Field `CCEDG` writer - capture mode edge detect"]
pub type CCEDG_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CCEDG>;
impl<'a, REG> CCEDG_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "high to low transition only"]
#[inline(always)]
pub fn hitolow(self) -> &'a mut crate::W<REG> {
self.variant(CCEDG::Hitolow)
}
#[doc = "low to high transitions only"]
#[inline(always)]
pub fn lowtohigh(self) -> &'a mut crate::W<REG> {
self.variant(CCEDG::Lowtohigh)
}
#[doc = "both high to low and low to high transitions"]
#[inline(always)]
pub fn both(self) -> &'a mut crate::W<REG> {
self.variant(CCEDG::Both)
}
}
#[doc = "capture and compare interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CCINT {
#[doc = "0: no interrupt detected"]
None = 0,
#[doc = "1: interrupt, write 1b to clear"]
Interrupt = 1,
}
impl From<CCINT> for bool {
#[inline(always)]
fn from(variant: CCINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCINT` reader - capture and compare interrupt"]
pub type CCINT_R = crate::BitReader<CCINT>;
impl CCINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CCINT {
match self.bits {
false => CCINT::None,
true => CCINT::Interrupt,
}
}
#[doc = "no interrupt detected"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == CCINT::None
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == CCINT::Interrupt
}
}
#[doc = "Field `CCINT` writer - capture and compare interrupt"]
pub type CCINT_W<'a, REG> = crate::BitWriter<'a, REG, CCINT>;
impl<'a, REG> CCINT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "no interrupt detected"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(CCINT::None)
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(CCINT::Interrupt)
}
}
#[doc = "capture and compare interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CCINTEN {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<CCINTEN> for bool {
#[inline(always)]
fn from(variant: CCINTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCINTEN` reader - capture and compare interrupt enable"]
pub type CCINTEN_R = crate::BitReader<CCINTEN>;
impl CCINTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CCINTEN {
match self.bits {
false => CCINTEN::Disabled,
true => CCINTEN::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == CCINTEN::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == CCINTEN::Enabled
}
}
#[doc = "Field `CCINTEN` writer - capture and compare interrupt enable"]
pub type CCINTEN_W<'a, REG> = crate::BitWriter<'a, REG, CCINTEN>;
impl<'a, REG> CCINTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(CCINTEN::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(CCINTEN::Enabled)
}
}
#[doc = "capture and compare mode\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CCMODE {
#[doc = "0: compare mode"]
CompareMode = 0,
#[doc = "1: capture mode"]
CaptureMode = 1,
}
impl From<CCMODE> for bool {
#[inline(always)]
fn from(variant: CCMODE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCMODE` reader - capture and compare mode"]
pub type CCMODE_R = crate::BitReader<CCMODE>;
impl CCMODE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CCMODE {
match self.bits {
false => CCMODE::CompareMode,
true => CCMODE::CaptureMode,
}
}
#[doc = "compare mode"]
#[inline(always)]
pub fn is_compare_mode(&self) -> bool {
*self == CCMODE::CompareMode
}
#[doc = "capture mode"]
#[inline(always)]
pub fn is_capture_mode(&self) -> bool {
*self == CCMODE::CaptureMode
}
}
#[doc = "Field `CCMODE` writer - capture and compare mode"]
pub type CCMODE_W<'a, REG> = crate::BitWriter<'a, REG, CCMODE>;
impl<'a, REG> CCMODE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "compare mode"]
#[inline(always)]
pub fn compare_mode(self) -> &'a mut crate::W<REG> {
self.variant(CCMODE::CompareMode)
}
#[doc = "capture mode"]
#[inline(always)]
pub fn capture_mode(self) -> &'a mut crate::W<REG> {
self.variant(CCMODE::CaptureMode)
}
}
impl R {
#[doc = "Bits 0:1 - capture mode edge detect"]
#[inline(always)]
pub fn ccedg(&self) -> CCEDG_R {
CCEDG_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - capture and compare interrupt"]
#[inline(always)]
pub fn ccint(&self) -> CCINT_R {
CCINT_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - capture and compare interrupt enable"]
#[inline(always)]
pub fn ccinten(&self) -> CCINTEN_R {
CCINTEN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - capture and compare mode"]
#[inline(always)]
pub fn ccmode(&self) -> CCMODE_R {
CCMODE_R::new(((self.bits >> 4) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxCC0CTL")
.field("ccedg", &self.ccedg())
.field("ccint", &self.ccint())
.field("ccinten", &self.ccinten())
.field("ccmode", &self.ccmode())
.finish()
}
}
impl W {
#[doc = "Bits 0:1 - capture mode edge detect"]
#[inline(always)]
pub fn ccedg(&mut self) -> CCEDG_W<TX_CC0CTLrs> {
CCEDG_W::new(self, 0)
}
#[doc = "Bit 2 - capture and compare interrupt"]
#[inline(always)]
pub fn ccint(&mut self) -> CCINT_W<TX_CC0CTLrs> {
CCINT_W::new(self, 2)
}
#[doc = "Bit 3 - capture and compare interrupt enable"]
#[inline(always)]
pub fn ccinten(&mut self) -> CCINTEN_W<TX_CC0CTLrs> {
CCINTEN_W::new(self, 3)
}
#[doc = "Bit 4 - capture and compare mode"]
#[inline(always)]
pub fn ccmode(&mut self) -> CCMODE_W<TX_CC0CTLrs> {
CCMODE_W::new(self, 4)
}
}
#[doc = "timer capture and compare control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc0ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc0ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_CC0CTLrs;
impl crate::RegisterSpec for TX_CC0CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_cc0ctl::R`](R) reader structure"]
impl crate::Readable for TX_CC0CTLrs {}
#[doc = "`write(|w| ..)` method takes [`tx_cc0ctl::W`](W) writer structure"]
impl crate::Writable for TX_CC0CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TxCC0CTL to value 0"]
impl crate::Resettable for TX_CC0CTLrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "TxCC0CTR (rw) register accessor: capture and compare counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc0ctr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc0ctr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_cc0ctr`]
module"]
#[doc(alias = "TxCC0CTR")]
pub type TX_CC0CTR = crate::Reg<tx_cc0ctr::TX_CC0CTRrs>;
#[doc = "capture and compare counter unit 0"]
pub mod tx_cc0ctr {
#[doc = "Register `TxCC0CTR` reader"]
pub type R = crate::R<TX_CC0CTRrs>;
#[doc = "Register `TxCC0CTR` writer"]
pub type W = crate::W<TX_CC0CTRrs>;
#[doc = "Field `CCCTR` reader - capture and compare counter value"]
pub type CCCTR_R = crate::FieldReader<u16>;
#[doc = "Field `CCCTR` writer - capture and compare counter value"]
pub type CCCTR_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - capture and compare counter value"]
#[inline(always)]
pub fn ccctr(&self) -> CCCTR_R {
CCCTR_R::new((self.bits & 0xffff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TxCC0CTR")
.field("ccctr", &self.ccctr())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - capture and compare counter value"]
#[inline(always)]
pub fn ccctr(&mut self) -> CCCTR_W<TX_CC0CTRrs> {
CCCTR_W::new(self, 0)
}
}
#[doc = "capture and compare counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_cc0ctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_cc0ctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TX_CC0CTRrs;
impl crate::RegisterSpec for TX_CC0CTRrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_cc0ctr::R`](R) reader structure"]
impl crate::Readable for TX_CC0CTRrs {}
#[doc = "`write(|w| ..)` method takes [`tx_cc0ctr::W`](W) writer structure"]
impl crate::Writable for TX_CC0CTRrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TxCC0CTR to value 0"]
impl crate::Resettable for TX_CC0CTRrs {
const RESET_VALUE: u32 = 0;
}
}
pub use tx_cc0ctl as tx_cc1ctl;
pub use tx_cc0ctr as tx_cc1ctr;
pub use TX_CC0CTL as TX_CC1CTL;
pub use TX_CC0CTR as TX_CC1CTR;
#[doc = "DTGD0CTL (rw) register accessor: Timer A dead-time generator control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgd0ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgd0ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtgd0ctl`]
module"]
pub type DTGD0CTL = crate::Reg<dtgd0ctl::DTGD0CTLrs>;
#[doc = "Timer A dead-time generator control unit 0"]
pub mod dtgd0ctl {
#[doc = "Register `DTGD0CTL` reader"]
pub type R = crate::R<DTGD0CTLrs>;
#[doc = "Register `DTGD0CTL` writer"]
pub type W = crate::W<DTGD0CTLrs>;
#[doc = "Invert low-side output signal\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INVLS {
#[doc = "0: do not invert low-side output signal"]
Disabled = 0,
#[doc = "1: invert low-side output signal"]
Enabled = 1,
}
impl From<INVLS> for bool {
#[inline(always)]
fn from(variant: INVLS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INVLS` reader - Invert low-side output signal"]
pub type INVLS_R = crate::BitReader<INVLS>;
impl INVLS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INVLS {
match self.bits {
false => INVLS::Disabled,
true => INVLS::Enabled,
}
}
#[doc = "do not invert low-side output signal"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INVLS::Disabled
}
#[doc = "invert low-side output signal"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INVLS::Enabled
}
}
#[doc = "Field `INVLS` writer - Invert low-side output signal"]
pub type INVLS_W<'a, REG> = crate::BitWriter<'a, REG, INVLS>;
impl<'a, REG> INVLS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not invert low-side output signal"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INVLS::Disabled)
}
#[doc = "invert low-side output signal"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INVLS::Enabled)
}
}
#[doc = "Invert high-side output signal\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum INVHS {
#[doc = "0: do not invert high-side output signal"]
Disabled = 0,
#[doc = "1: invert high-side output signal"]
Enabled = 1,
}
impl From<INVHS> for bool {
#[inline(always)]
fn from(variant: INVHS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `INVHS` reader - Invert high-side output signal"]
pub type INVHS_R = crate::BitReader<INVHS>;
impl INVHS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> INVHS {
match self.bits {
false => INVHS::Disabled,
true => INVHS::Enabled,
}
}
#[doc = "do not invert high-side output signal"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == INVHS::Disabled
}
#[doc = "invert high-side output signal"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == INVHS::Enabled
}
}
#[doc = "Field `INVHS` writer - Invert high-side output signal"]
pub type INVHS_W<'a, REG> = crate::BitWriter<'a, REG, INVHS>;
impl<'a, REG> INVHS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not invert high-side output signal"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(INVHS::Disabled)
}
#[doc = "invert high-side output signal"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(INVHS::Enabled)
}
}
#[doc = "On-time preservation\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum OTP {
#[doc = "0: do not extend on time"]
Disabled = 0,
#[doc = "1: extend on time"]
Enabled = 1,
}
impl From<OTP> for bool {
#[inline(always)]
fn from(variant: OTP) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OTP` reader - On-time preservation"]
pub type OTP_R = crate::BitReader<OTP>;
impl OTP_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> OTP {
match self.bits {
false => OTP::Disabled,
true => OTP::Enabled,
}
}
#[doc = "do not extend on time"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == OTP::Disabled
}
#[doc = "extend on time"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == OTP::Enabled
}
}
#[doc = "Field `OTP` writer - On-time preservation"]
pub type OTP_W<'a, REG> = crate::BitWriter<'a, REG, OTP>;
impl<'a, REG> OTP_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not extend on time"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(OTP::Disabled)
}
#[doc = "extend on time"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(OTP::Enabled)
}
}
#[doc = "bypass dead-time generation\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum BYPASS {
#[doc = "0: do not bypass dead-time generation"]
Disabled = 0,
#[doc = "1: bypass dead-time generation"]
Enabled = 1,
}
impl From<BYPASS> for bool {
#[inline(always)]
fn from(variant: BYPASS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `BYPASS` reader - bypass dead-time generation"]
pub type BYPASS_R = crate::BitReader<BYPASS>;
impl BYPASS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> BYPASS {
match self.bits {
false => BYPASS::Disabled,
true => BYPASS::Enabled,
}
}
#[doc = "do not bypass dead-time generation"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == BYPASS::Disabled
}
#[doc = "bypass dead-time generation"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == BYPASS::Enabled
}
}
#[doc = "Field `BYPASS` writer - bypass dead-time generation"]
pub type BYPASS_W<'a, REG> = crate::BitWriter<'a, REG, BYPASS>;
impl<'a, REG> BYPASS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not bypass dead-time generation"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(BYPASS::Disabled)
}
#[doc = "bypass dead-time generation"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(BYPASS::Enabled)
}
}
impl R {
#[doc = "Bit 4 - Invert low-side output signal"]
#[inline(always)]
pub fn invls(&self) -> INVLS_R {
INVLS_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Invert high-side output signal"]
#[inline(always)]
pub fn invhs(&self) -> INVHS_R {
INVHS_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - On-time preservation"]
#[inline(always)]
pub fn otp(&self) -> OTP_R {
OTP_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - bypass dead-time generation"]
#[inline(always)]
pub fn bypass(&self) -> BYPASS_R {
BYPASS_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGD0CTL")
.field("invls", &self.invls())
.field("invhs", &self.invhs())
.field("otp", &self.otp())
.field("bypass", &self.bypass())
.finish()
}
}
impl W {
#[doc = "Bit 4 - Invert low-side output signal"]
#[inline(always)]
pub fn invls(&mut self) -> INVLS_W<DTGD0CTLrs> {
INVLS_W::new(self, 4)
}
#[doc = "Bit 5 - Invert high-side output signal"]
#[inline(always)]
pub fn invhs(&mut self) -> INVHS_W<DTGD0CTLrs> {
INVHS_W::new(self, 5)
}
#[doc = "Bit 6 - On-time preservation"]
#[inline(always)]
pub fn otp(&mut self) -> OTP_W<DTGD0CTLrs> {
OTP_W::new(self, 6)
}
#[doc = "Bit 7 - bypass dead-time generation"]
#[inline(always)]
pub fn bypass(&mut self) -> BYPASS_W<DTGD0CTLrs> {
BYPASS_W::new(self, 7)
}
}
#[doc = "Timer A dead-time generator control unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgd0ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgd0ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGD0CTLrs;
impl crate::RegisterSpec for DTGD0CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtgd0ctl::R`](R) reader structure"]
impl crate::Readable for DTGD0CTLrs {}
#[doc = "`write(|w| ..)` method takes [`dtgd0ctl::W`](W) writer structure"]
impl crate::Writable for DTGD0CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGD0CTL to value 0x80"]
impl crate::Resettable for DTGD0CTLrs {
const RESET_VALUE: u32 = 0x80;
}
}
#[doc = "DTGD0LED (rw) register accessor: Timer A dead-time generator leading-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgd0led::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgd0led::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtgd0led`]
module"]
pub type DTGD0LED = crate::Reg<dtgd0led::DTGD0LEDrs>;
#[doc = "Timer A dead-time generator leading-edge delay counter unit 0"]
pub mod dtgd0led {
#[doc = "Register `DTGD0LED` reader"]
pub type R = crate::R<DTGD0LEDrs>;
#[doc = "Register `DTGD0LED` writer"]
pub type W = crate::W<DTGD0LEDrs>;
#[doc = "Field `LED` reader - leading-edge delay counter"]
pub type LED_R = crate::FieldReader<u16>;
#[doc = "Field `LED` writer - leading-edge delay counter"]
pub type LED_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:11 - leading-edge delay counter"]
#[inline(always)]
pub fn led(&self) -> LED_R {
LED_R::new((self.bits & 0x0fff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGD0LED")
.field("led", &self.led())
.finish()
}
}
impl W {
#[doc = "Bits 0:11 - leading-edge delay counter"]
#[inline(always)]
pub fn led(&mut self) -> LED_W<DTGD0LEDrs> {
LED_W::new(self, 0)
}
}
#[doc = "Timer A dead-time generator leading-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgd0led::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgd0led::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGD0LEDrs;
impl crate::RegisterSpec for DTGD0LEDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtgd0led::R`](R) reader structure"]
impl crate::Readable for DTGD0LEDrs {}
#[doc = "`write(|w| ..)` method takes [`dtgd0led::W`](W) writer structure"]
impl crate::Writable for DTGD0LEDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGD0LED to value 0"]
impl crate::Resettable for DTGD0LEDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "DTGD0TED (rw) register accessor: Timer A dead-time generator trailing-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgd0ted::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgd0ted::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dtgd0ted`]
module"]
pub type DTGD0TED = crate::Reg<dtgd0ted::DTGD0TEDrs>;
#[doc = "Timer A dead-time generator trailing-edge delay counter unit 0"]
pub mod dtgd0ted {
#[doc = "Register `DTGD0TED` reader"]
pub type R = crate::R<DTGD0TEDrs>;
#[doc = "Register `DTGD0TED` writer"]
pub type W = crate::W<DTGD0TEDrs>;
#[doc = "Field `TED` reader - trailing-edge delay counter"]
pub type TED_R = crate::FieldReader<u16>;
#[doc = "Field `TED` writer - trailing-edge delay counter"]
pub type TED_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
impl R {
#[doc = "Bits 0:11 - trailing-edge delay counter"]
#[inline(always)]
pub fn ted(&self) -> TED_R {
TED_R::new((self.bits & 0x0fff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DTGD0TED")
.field("ted", &self.ted())
.finish()
}
}
impl W {
#[doc = "Bits 0:11 - trailing-edge delay counter"]
#[inline(always)]
pub fn ted(&mut self) -> TED_W<DTGD0TEDrs> {
TED_W::new(self, 0)
}
}
#[doc = "Timer A dead-time generator trailing-edge delay counter unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dtgd0ted::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dtgd0ted::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DTGD0TEDrs;
impl crate::RegisterSpec for DTGD0TEDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`dtgd0ted::R`](R) reader structure"]
impl crate::Readable for DTGD0TEDrs {}
#[doc = "`write(|w| ..)` method takes [`dtgd0ted::W`](W) writer structure"]
impl crate::Writable for DTGD0TEDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DTGD0TED to value 0"]
impl crate::Resettable for DTGD0TEDrs {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "Analog to Digital Converter"]
pub struct ADC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for ADC {}
impl ADC {
#[doc = r"Pointer to the register block"]
pub const PTR: *const adc::RegisterBlock = 0x4015_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const adc::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for ADC {
type Target = adc::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for ADC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ADC").finish()
}
}
#[doc = "Analog to Digital Converter"]
pub mod adc {
#[repr(C)]
#[derive(Debug)]
#[doc = "Register block"]
pub struct RegisterBlock {
emuxctl: EMUXCTL,
emuxdata: EMUXDATA,
adcctl: ADCCTL,
adccr: ADCCR,
adcint: ADCINT,
_reserved5: [u8; 0x2c],
as0ctl: AS0CTL,
as0s0: AS0S0,
as0r0: AS0R0,
as0s1: AS0S1,
as0r1: AS0R1,
as0s2: AS0S2,
as0r2: AS0R2,
as0s3: AS0S3,
as0r3: AS0R3,
as0s4: AS0S4,
as0r4: AS0R4,
as0s5: AS0S5,
as0r5: AS0R5,
as0s6: AS0S6,
as0r6: AS0R6,
as0s7: AS0S7,
as0r7: AS0R7,
_reserved22: [u8; 0x7c],
as1ctl: AS1CTL,
as1s0: AS1S0,
as1r0: AS1R0,
as1s1: AS1S1,
as1r1: AS1R1,
as1s2: AS1S2,
as1r2: AS1R2,
as1s3: AS1S3,
as1r3: AS1R3,
as1s4: AS1S4,
as1r4: AS1R4,
as1s5: AS1S5,
as1r5: AS1R5,
as1s6: AS1S6,
as1r6: AS1R6,
as1s7: AS1S7,
as1r7: AS1R7,
}
impl RegisterBlock {
#[doc = "0x00 - ADC External MUX control register"]
#[inline(always)]
pub const fn emuxctl(&self) -> &EMUXCTL {
&self.emuxctl
}
#[doc = "0x04 - ADC External MUX data register"]
#[inline(always)]
pub const fn emuxdata(&self) -> &EMUXDATA {
&self.emuxdata
}
#[doc = "0x08 - ADC control register"]
#[inline(always)]
pub const fn adcctl(&self) -> &ADCCTL {
&self.adcctl
}
#[doc = "0x0c - ADC conversion result register"]
#[inline(always)]
pub const fn adccr(&self) -> &ADCCR {
&self.adccr
}
#[doc = "0x10 - ADC interrupt register"]
#[inline(always)]
pub const fn adcint(&self) -> &ADCINT {
&self.adcint
}
#[doc = "0x40 - Auto sequencer 0 control register"]
#[inline(always)]
pub const fn as0ctl(&self) -> &AS0CTL {
&self.as0ctl
}
#[doc = "0x44 - Auto sequencer 0 sample 0 control register"]
#[inline(always)]
pub const fn as0s0(&self) -> &AS0S0 {
&self.as0s0
}
#[doc = "0x48 - Auto sequencer 0 sample 0 result register"]
#[inline(always)]
pub const fn as0r0(&self) -> &AS0R0 {
&self.as0r0
}
#[doc = "0x4c - Auto sequencer 0 sample 1 control register"]
#[inline(always)]
pub const fn as0s1(&self) -> &AS0S1 {
&self.as0s1
}
#[doc = "0x50 - Auto sequencer 0 sample 1 result register"]
#[inline(always)]
pub const fn as0r1(&self) -> &AS0R1 {
&self.as0r1
}
#[doc = "0x54 - Auto sequencer 0 sample 2 control register"]
#[inline(always)]
pub const fn as0s2(&self) -> &AS0S2 {
&self.as0s2
}
#[doc = "0x58 - Auto sequencer 0 sample 2 result register"]
#[inline(always)]
pub const fn as0r2(&self) -> &AS0R2 {
&self.as0r2
}
#[doc = "0x5c - Auto sequencer 0 sample 3 control register"]
#[inline(always)]
pub const fn as0s3(&self) -> &AS0S3 {
&self.as0s3
}
#[doc = "0x60 - Auto sequencer 0 sample 3 result register"]
#[inline(always)]
pub const fn as0r3(&self) -> &AS0R3 {
&self.as0r3
}
#[doc = "0x64 - Auto sequencer 0 sample 4 control register"]
#[inline(always)]
pub const fn as0s4(&self) -> &AS0S4 {
&self.as0s4
}
#[doc = "0x68 - Auto sequencer 0 sample 4 result register"]
#[inline(always)]
pub const fn as0r4(&self) -> &AS0R4 {
&self.as0r4
}
#[doc = "0x6c - Auto sequencer 0 sample 5 control register"]
#[inline(always)]
pub const fn as0s5(&self) -> &AS0S5 {
&self.as0s5
}
#[doc = "0x70 - Auto sequencer 0 sample 5 result register"]
#[inline(always)]
pub const fn as0r5(&self) -> &AS0R5 {
&self.as0r5
}
#[doc = "0x74 - Auto sequencer 0 sample 6 control register"]
#[inline(always)]
pub const fn as0s6(&self) -> &AS0S6 {
&self.as0s6
}
#[doc = "0x78 - Auto sequencer 0 sample 6 result register"]
#[inline(always)]
pub const fn as0r6(&self) -> &AS0R6 {
&self.as0r6
}
#[doc = "0x7c - Auto sequencer 0 sample 7 control register"]
#[inline(always)]
pub const fn as0s7(&self) -> &AS0S7 {
&self.as0s7
}
#[doc = "0x80 - Auto sequencer 0 sample 7 result register"]
#[inline(always)]
pub const fn as0r7(&self) -> &AS0R7 {
&self.as0r7
}
#[doc = "0x100 - Auto sequencer 1 control register"]
#[inline(always)]
pub const fn as1ctl(&self) -> &AS1CTL {
&self.as1ctl
}
#[doc = "0x104 - Auto sequencer 1 sample 0 control register"]
#[inline(always)]
pub const fn as1s0(&self) -> &AS1S0 {
&self.as1s0
}
#[doc = "0x108 - Auto sequencer 1 sample 0 result register"]
#[inline(always)]
pub const fn as1r0(&self) -> &AS1R0 {
&self.as1r0
}
#[doc = "0x10c - Auto sequencer 1 sample 1 control register"]
#[inline(always)]
pub const fn as1s1(&self) -> &AS1S1 {
&self.as1s1
}
#[doc = "0x110 - Auto sequencer 1 sample 1 result register"]
#[inline(always)]
pub const fn as1r1(&self) -> &AS1R1 {
&self.as1r1
}
#[doc = "0x114 - Auto sequencer 1 sample 2 control register"]
#[inline(always)]
pub const fn as1s2(&self) -> &AS1S2 {
&self.as1s2
}
#[doc = "0x118 - Auto sequencer 1 sample 2 result register"]
#[inline(always)]
pub const fn as1r2(&self) -> &AS1R2 {
&self.as1r2
}
#[doc = "0x11c - Auto sequencer 1 sample 3 control register"]
#[inline(always)]
pub const fn as1s3(&self) -> &AS1S3 {
&self.as1s3
}
#[doc = "0x120 - Auto sequencer 1 sample 3 result register"]
#[inline(always)]
pub const fn as1r3(&self) -> &AS1R3 {
&self.as1r3
}
#[doc = "0x124 - Auto sequencer 1 sample 4 control register"]
#[inline(always)]
pub const fn as1s4(&self) -> &AS1S4 {
&self.as1s4
}
#[doc = "0x128 - Auto sequencer 1 sample 4 result register"]
#[inline(always)]
pub const fn as1r4(&self) -> &AS1R4 {
&self.as1r4
}
#[doc = "0x12c - Auto sequencer 1 sample 5 control register"]
#[inline(always)]
pub const fn as1s5(&self) -> &AS1S5 {
&self.as1s5
}
#[doc = "0x130 - Auto sequencer 1 sample 5 result register"]
#[inline(always)]
pub const fn as1r5(&self) -> &AS1R5 {
&self.as1r5
}
#[doc = "0x134 - Auto sequencer 1 sample 6 control register"]
#[inline(always)]
pub const fn as1s6(&self) -> &AS1S6 {
&self.as1s6
}
#[doc = "0x138 - Auto sequencer 1 sample 6 result register"]
#[inline(always)]
pub const fn as1r6(&self) -> &AS1R6 {
&self.as1r6
}
#[doc = "0x13c - Auto sequencer 1 sample 7 control register"]
#[inline(always)]
pub const fn as1s7(&self) -> &AS1S7 {
&self.as1s7
}
#[doc = "0x140 - Auto sequencer 1 sample 7 result register"]
#[inline(always)]
pub const fn as1r7(&self) -> &AS1R7 {
&self.as1r7
}
}
#[doc = "EMUXCTL (rw) register accessor: ADC External MUX control register\n\nYou can [`read`](crate::Reg::read) this register and get [`emuxctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emuxctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emuxctl`]
module"]
pub type EMUXCTL = crate::Reg<emuxctl::EMUXCTLrs>;
#[doc = "ADC External MUX control register"]
pub mod emuxctl {
#[doc = "Register `EMUXCTL` reader"]
pub type R = crate::R<EMUXCTLrs>;
#[doc = "Register `EMUXCTL` writer"]
pub type W = crate::W<EMUXCTLrs>;
#[doc = "ADC External MUX clock to FCLK divider\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum EMUXCDIV {
#[doc = "0: FCLK divided by 1"]
FclkDiv1 = 0,
#[doc = "1: FCLK divided by 2"]
FclkDiv2 = 1,
#[doc = "2: FCLK divided by 3"]
FclkDiv3 = 2,
#[doc = "3: FCLK divided by 4"]
FclkDiv4 = 3,
#[doc = "4: FCLK divided by 5"]
FclkDiv5 = 4,
#[doc = "5: FCLK divided by 6"]
FclkDiv6 = 5,
#[doc = "6: FCLK divided by 7"]
FclkDiv7 = 6,
#[doc = "7: FCLK divided by 8"]
FclkDiv8 = 7,
}
impl From<EMUXCDIV> for u8 {
#[inline(always)]
fn from(variant: EMUXCDIV) -> Self {
variant as _
}
}
impl crate::FieldSpec for EMUXCDIV {
type Ux = u8;
}
impl crate::IsEnum for EMUXCDIV {}
#[doc = "Field `EMUXCDIV` reader - ADC External MUX clock to FCLK divider"]
pub type EMUXCDIV_R = crate::FieldReader<EMUXCDIV>;
impl EMUXCDIV_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> EMUXCDIV {
match self.bits {
0 => EMUXCDIV::FclkDiv1,
1 => EMUXCDIV::FclkDiv2,
2 => EMUXCDIV::FclkDiv3,
3 => EMUXCDIV::FclkDiv4,
4 => EMUXCDIV::FclkDiv5,
5 => EMUXCDIV::FclkDiv6,
6 => EMUXCDIV::FclkDiv7,
7 => EMUXCDIV::FclkDiv8,
_ => unreachable!(),
}
}
#[doc = "FCLK divided by 1"]
#[inline(always)]
pub fn is_fclk_div_1(&self) -> bool {
*self == EMUXCDIV::FclkDiv1
}
#[doc = "FCLK divided by 2"]
#[inline(always)]
pub fn is_fclk_div_2(&self) -> bool {
*self == EMUXCDIV::FclkDiv2
}
#[doc = "FCLK divided by 3"]
#[inline(always)]
pub fn is_fclk_div_3(&self) -> bool {
*self == EMUXCDIV::FclkDiv3
}
#[doc = "FCLK divided by 4"]
#[inline(always)]
pub fn is_fclk_div_4(&self) -> bool {
*self == EMUXCDIV::FclkDiv4
}
#[doc = "FCLK divided by 5"]
#[inline(always)]
pub fn is_fclk_div_5(&self) -> bool {
*self == EMUXCDIV::FclkDiv5
}
#[doc = "FCLK divided by 6"]
#[inline(always)]
pub fn is_fclk_div_6(&self) -> bool {
*self == EMUXCDIV::FclkDiv6
}
#[doc = "FCLK divided by 7"]
#[inline(always)]
pub fn is_fclk_div_7(&self) -> bool {
*self == EMUXCDIV::FclkDiv7
}
#[doc = "FCLK divided by 8"]
#[inline(always)]
pub fn is_fclk_div_8(&self) -> bool {
*self == EMUXCDIV::FclkDiv8
}
}
#[doc = "Field `EMUXCDIV` writer - ADC External MUX clock to FCLK divider"]
pub type EMUXCDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 3, EMUXCDIV, crate::Safe>;
impl<'a, REG> EMUXCDIV_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "FCLK divided by 1"]
#[inline(always)]
pub fn fclk_div_1(self) -> &'a mut crate::W<REG> {
self.variant(EMUXCDIV::FclkDiv1)
}
#[doc = "FCLK divided by 2"]
#[inline(always)]
pub fn fclk_div_2(self) -> &'a mut crate::W<REG> {
self.variant(EMUXCDIV::FclkDiv2)
}
#[doc = "FCLK divided by 3"]
#[inline(always)]
pub fn fclk_div_3(self) -> &'a mut crate::W<REG> {
self.variant(EMUXCDIV::FclkDiv3)
}
#[doc = "FCLK divided by 4"]
#[inline(always)]
pub fn fclk_div_4(self) -> &'a mut crate::W<REG> {
self.variant(EMUXCDIV::FclkDiv4)
}
#[doc = "FCLK divided by 5"]
#[inline(always)]
pub fn fclk_div_5(self) -> &'a mut crate::W<REG> {
self.variant(EMUXCDIV::FclkDiv5)
}
#[doc = "FCLK divided by 6"]
#[inline(always)]
pub fn fclk_div_6(self) -> &'a mut crate::W<REG> {
self.variant(EMUXCDIV::FclkDiv6)
}
#[doc = "FCLK divided by 7"]
#[inline(always)]
pub fn fclk_div_7(self) -> &'a mut crate::W<REG> {
self.variant(EMUXCDIV::FclkDiv7)
}
#[doc = "FCLK divided by 8"]
#[inline(always)]
pub fn fclk_div_8(self) -> &'a mut crate::W<REG> {
self.variant(EMUXCDIV::FclkDiv8)
}
}
#[doc = "ADC External MUX data send done\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum EMUXDONE {
#[doc = "0: ADC External MUX busy"]
Busy = 0,
#[doc = "1: ADC External MUX data sent"]
DataSent = 1,
}
impl From<EMUXDONE> for bool {
#[inline(always)]
fn from(variant: EMUXDONE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `EMUXDONE` reader - ADC External MUX data send done"]
pub type EMUXDONE_R = crate::BitReader<EMUXDONE>;
impl EMUXDONE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> EMUXDONE {
match self.bits {
false => EMUXDONE::Busy,
true => EMUXDONE::DataSent,
}
}
#[doc = "ADC External MUX busy"]
#[inline(always)]
pub fn is_busy(&self) -> bool {
*self == EMUXDONE::Busy
}
#[doc = "ADC External MUX data sent"]
#[inline(always)]
pub fn is_data_sent(&self) -> bool {
*self == EMUXDONE::DataSent
}
}
#[doc = "Field `EMUXDONE` writer - ADC External MUX data send done"]
pub type EMUXDONE_W<'a, REG> = crate::BitWriter<'a, REG, EMUXDONE>;
impl<'a, REG> EMUXDONE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "ADC External MUX busy"]
#[inline(always)]
pub fn busy(self) -> &'a mut crate::W<REG> {
self.variant(EMUXDONE::Busy)
}
#[doc = "ADC External MUX data sent"]
#[inline(always)]
pub fn data_sent(self) -> &'a mut crate::W<REG> {
self.variant(EMUXDONE::DataSent)
}
}
#[doc = "ADC External MUX status\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum EMUXBUSY {
#[doc = "0: ADC External MUX busy"]
Busy = 0,
#[doc = "1: ADC External MUX not busy"]
NotBusy = 1,
}
impl From<EMUXBUSY> for bool {
#[inline(always)]
fn from(variant: EMUXBUSY) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `EMUXBUSY` reader - ADC External MUX status"]
pub type EMUXBUSY_R = crate::BitReader<EMUXBUSY>;
impl EMUXBUSY_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> EMUXBUSY {
match self.bits {
false => EMUXBUSY::Busy,
true => EMUXBUSY::NotBusy,
}
}
#[doc = "ADC External MUX busy"]
#[inline(always)]
pub fn is_busy(&self) -> bool {
*self == EMUXBUSY::Busy
}
#[doc = "ADC External MUX not busy"]
#[inline(always)]
pub fn is_not_busy(&self) -> bool {
*self == EMUXBUSY::NotBusy
}
}
#[doc = "Field `EMUXBUSY` writer - ADC External MUX status"]
pub type EMUXBUSY_W<'a, REG> = crate::BitWriter<'a, REG, EMUXBUSY>;
impl<'a, REG> EMUXBUSY_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "ADC External MUX busy"]
#[inline(always)]
pub fn busy(self) -> &'a mut crate::W<REG> {
self.variant(EMUXBUSY::Busy)
}
#[doc = "ADC External MUX not busy"]
#[inline(always)]
pub fn not_busy(self) -> &'a mut crate::W<REG> {
self.variant(EMUXBUSY::NotBusy)
}
}
#[doc = "ADC External MUX control\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum EMUXC {
#[doc = "0: ADC External MUX manual control"]
Manual = 0,
#[doc = "1: ADC External MUX controlled by auto-sequencer unit"]
Auto = 1,
}
impl From<EMUXC> for bool {
#[inline(always)]
fn from(variant: EMUXC) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `EMUXC` reader - ADC External MUX control"]
pub type EMUXC_R = crate::BitReader<EMUXC>;
impl EMUXC_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> EMUXC {
match self.bits {
false => EMUXC::Manual,
true => EMUXC::Auto,
}
}
#[doc = "ADC External MUX manual control"]
#[inline(always)]
pub fn is_manual(&self) -> bool {
*self == EMUXC::Manual
}
#[doc = "ADC External MUX controlled by auto-sequencer unit"]
#[inline(always)]
pub fn is_auto(&self) -> bool {
*self == EMUXC::Auto
}
}
#[doc = "Field `EMUXC` writer - ADC External MUX control"]
pub type EMUXC_W<'a, REG> = crate::BitWriter<'a, REG, EMUXC>;
impl<'a, REG> EMUXC_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "ADC External MUX manual control"]
#[inline(always)]
pub fn manual(self) -> &'a mut crate::W<REG> {
self.variant(EMUXC::Manual)
}
#[doc = "ADC External MUX controlled by auto-sequencer unit"]
#[inline(always)]
pub fn auto(self) -> &'a mut crate::W<REG> {
self.variant(EMUXC::Auto)
}
}
impl R {
#[doc = "Bits 0:2 - ADC External MUX clock to FCLK divider"]
#[inline(always)]
pub fn emuxcdiv(&self) -> EMUXCDIV_R {
EMUXCDIV_R::new((self.bits & 7) as u8)
}
#[doc = "Bit 3 - ADC External MUX data send done"]
#[inline(always)]
pub fn emuxdone(&self) -> EMUXDONE_R {
EMUXDONE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - ADC External MUX status"]
#[inline(always)]
pub fn emuxbusy(&self) -> EMUXBUSY_R {
EMUXBUSY_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - ADC External MUX control"]
#[inline(always)]
pub fn emuxc(&self) -> EMUXC_R {
EMUXC_R::new(((self.bits >> 5) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EMUXCTL")
.field("emuxcdiv", &self.emuxcdiv())
.field("emuxdone", &self.emuxdone())
.field("emuxbusy", &self.emuxbusy())
.field("emuxc", &self.emuxc())
.finish()
}
}
impl W {
#[doc = "Bits 0:2 - ADC External MUX clock to FCLK divider"]
#[inline(always)]
pub fn emuxcdiv(&mut self) -> EMUXCDIV_W<EMUXCTLrs> {
EMUXCDIV_W::new(self, 0)
}
#[doc = "Bit 3 - ADC External MUX data send done"]
#[inline(always)]
pub fn emuxdone(&mut self) -> EMUXDONE_W<EMUXCTLrs> {
EMUXDONE_W::new(self, 3)
}
#[doc = "Bit 4 - ADC External MUX status"]
#[inline(always)]
pub fn emuxbusy(&mut self) -> EMUXBUSY_W<EMUXCTLrs> {
EMUXBUSY_W::new(self, 4)
}
#[doc = "Bit 5 - ADC External MUX control"]
#[inline(always)]
pub fn emuxc(&mut self) -> EMUXC_W<EMUXCTLrs> {
EMUXC_W::new(self, 5)
}
}
#[doc = "ADC External MUX control register\n\nYou can [`read`](crate::Reg::read) this register and get [`emuxctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emuxctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EMUXCTLrs;
impl crate::RegisterSpec for EMUXCTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`emuxctl::R`](R) reader structure"]
impl crate::Readable for EMUXCTLrs {}
#[doc = "`write(|w| ..)` method takes [`emuxctl::W`](W) writer structure"]
impl crate::Writable for EMUXCTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets EMUXCTL to value 0"]
impl crate::Resettable for EMUXCTLrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "EMUXDATA (rw) register accessor: ADC External MUX data register\n\nYou can [`read`](crate::Reg::read) this register and get [`emuxdata::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emuxdata::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emuxdata`]
module"]
pub type EMUXDATA = crate::Reg<emuxdata::EMUXDATArs>;
#[doc = "ADC External MUX data register"]
pub mod emuxdata {
#[doc = "Register `EMUXDATA` reader"]
pub type R = crate::R<EMUXDATArs>;
#[doc = "Register `EMUXDATA` writer"]
pub type W = crate::W<EMUXDATArs>;
#[doc = "Field `DATA` reader - ADC External MUX data register"]
pub type DATA_R = crate::FieldReader<u16>;
#[doc = "Field `DATA` writer - ADC External MUX data register"]
pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - ADC External MUX data register"]
#[inline(always)]
pub fn data(&self) -> DATA_R {
DATA_R::new((self.bits & 0xffff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EMUXDATA")
.field("data", &self.data())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - ADC External MUX data register"]
#[inline(always)]
pub fn data(&mut self) -> DATA_W<EMUXDATArs> {
DATA_W::new(self, 0)
}
}
#[doc = "ADC External MUX data register\n\nYou can [`read`](crate::Reg::read) this register and get [`emuxdata::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emuxdata::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EMUXDATArs;
impl crate::RegisterSpec for EMUXDATArs {
type Ux = u32;
}
#[doc = "`read()` method returns [`emuxdata::R`](R) reader structure"]
impl crate::Readable for EMUXDATArs {}
#[doc = "`write(|w| ..)` method takes [`emuxdata::W`](W) writer structure"]
impl crate::Writable for EMUXDATArs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets EMUXDATA to value 0"]
impl crate::Resettable for EMUXDATArs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ADCCTL (rw) register accessor: ADC control register\n\nYou can [`read`](crate::Reg::read) this register and get [`adcctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcctl`]
module"]
pub type ADCCTL = crate::Reg<adcctl::ADCCTLrs>;
#[doc = "ADC control register"]
pub mod adcctl {
#[doc = "Register `ADCCTL` reader"]
pub type R = crate::R<ADCCTLrs>;
#[doc = "Register `ADCCTL` writer"]
pub type W = crate::W<ADCCTLrs>;
#[doc = "ADC input clock FCLK divider\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum ADCCDIV {
#[doc = "0: FCLK divided by 1"]
FclkDiv1 = 0,
#[doc = "1: FCLK divided by 2"]
FclkDiv2 = 1,
#[doc = "2: FCLK divided by 3"]
FclkDiv3 = 2,
#[doc = "3: FCLK divided by 4"]
FclkDiv4 = 3,
#[doc = "4: FCLK divided by 5"]
FclkDiv5 = 4,
#[doc = "5: FCLK divided by 6"]
FclkDiv6 = 5,
#[doc = "6: FCLK divided by 7"]
FclkDiv7 = 6,
#[doc = "7: FCLK divided by 8"]
FclkDiv8 = 7,
}
impl From<ADCCDIV> for u8 {
#[inline(always)]
fn from(variant: ADCCDIV) -> Self {
variant as _
}
}
impl crate::FieldSpec for ADCCDIV {
type Ux = u8;
}
impl crate::IsEnum for ADCCDIV {}
#[doc = "Field `ADCCDIV` reader - ADC input clock FCLK divider"]
pub type ADCCDIV_R = crate::FieldReader<ADCCDIV>;
impl ADCCDIV_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ADCCDIV {
match self.bits {
0 => ADCCDIV::FclkDiv1,
1 => ADCCDIV::FclkDiv2,
2 => ADCCDIV::FclkDiv3,
3 => ADCCDIV::FclkDiv4,
4 => ADCCDIV::FclkDiv5,
5 => ADCCDIV::FclkDiv6,
6 => ADCCDIV::FclkDiv7,
7 => ADCCDIV::FclkDiv8,
_ => unreachable!(),
}
}
#[doc = "FCLK divided by 1"]
#[inline(always)]
pub fn is_fclk_div_1(&self) -> bool {
*self == ADCCDIV::FclkDiv1
}
#[doc = "FCLK divided by 2"]
#[inline(always)]
pub fn is_fclk_div_2(&self) -> bool {
*self == ADCCDIV::FclkDiv2
}
#[doc = "FCLK divided by 3"]
#[inline(always)]
pub fn is_fclk_div_3(&self) -> bool {
*self == ADCCDIV::FclkDiv3
}
#[doc = "FCLK divided by 4"]
#[inline(always)]
pub fn is_fclk_div_4(&self) -> bool {
*self == ADCCDIV::FclkDiv4
}
#[doc = "FCLK divided by 5"]
#[inline(always)]
pub fn is_fclk_div_5(&self) -> bool {
*self == ADCCDIV::FclkDiv5
}
#[doc = "FCLK divided by 6"]
#[inline(always)]
pub fn is_fclk_div_6(&self) -> bool {
*self == ADCCDIV::FclkDiv6
}
#[doc = "FCLK divided by 7"]
#[inline(always)]
pub fn is_fclk_div_7(&self) -> bool {
*self == ADCCDIV::FclkDiv7
}
#[doc = "FCLK divided by 8"]
#[inline(always)]
pub fn is_fclk_div_8(&self) -> bool {
*self == ADCCDIV::FclkDiv8
}
}
#[doc = "Field `ADCCDIV` writer - ADC input clock FCLK divider"]
pub type ADCCDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 3, ADCCDIV, crate::Safe>;
impl<'a, REG> ADCCDIV_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "FCLK divided by 1"]
#[inline(always)]
pub fn fclk_div_1(self) -> &'a mut crate::W<REG> {
self.variant(ADCCDIV::FclkDiv1)
}
#[doc = "FCLK divided by 2"]
#[inline(always)]
pub fn fclk_div_2(self) -> &'a mut crate::W<REG> {
self.variant(ADCCDIV::FclkDiv2)
}
#[doc = "FCLK divided by 3"]
#[inline(always)]
pub fn fclk_div_3(self) -> &'a mut crate::W<REG> {
self.variant(ADCCDIV::FclkDiv3)
}
#[doc = "FCLK divided by 4"]
#[inline(always)]
pub fn fclk_div_4(self) -> &'a mut crate::W<REG> {
self.variant(ADCCDIV::FclkDiv4)
}
#[doc = "FCLK divided by 5"]
#[inline(always)]
pub fn fclk_div_5(self) -> &'a mut crate::W<REG> {
self.variant(ADCCDIV::FclkDiv5)
}
#[doc = "FCLK divided by 6"]
#[inline(always)]
pub fn fclk_div_6(self) -> &'a mut crate::W<REG> {
self.variant(ADCCDIV::FclkDiv6)
}
#[doc = "FCLK divided by 7"]
#[inline(always)]
pub fn fclk_div_7(self) -> &'a mut crate::W<REG> {
self.variant(ADCCDIV::FclkDiv7)
}
#[doc = "FCLK divided by 8"]
#[inline(always)]
pub fn fclk_div_8(self) -> &'a mut crate::W<REG> {
self.variant(ADCCDIV::FclkDiv8)
}
}
#[doc = "ADC MUX input select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum ADCMUX {
#[doc = "0: AD0 input"]
Ad0 = 0,
#[doc = "2: AD2 input"]
Ad2 = 2,
#[doc = "3: AD3 input"]
Ad3 = 3,
#[doc = "4: AD4 input"]
Ad4 = 4,
#[doc = "5: AD5 input"]
Ad5 = 5,
#[doc = "7: VSSA input"]
Vssa = 7,
}
impl From<ADCMUX> for u8 {
#[inline(always)]
fn from(variant: ADCMUX) -> Self {
variant as _
}
}
impl crate::FieldSpec for ADCMUX {
type Ux = u8;
}
impl crate::IsEnum for ADCMUX {}
#[doc = "Field `ADCMUX` reader - ADC MUX input select"]
pub type ADCMUX_R = crate::FieldReader<ADCMUX>;
impl ADCMUX_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<ADCMUX> {
match self.bits {
0 => Some(ADCMUX::Ad0),
2 => Some(ADCMUX::Ad2),
3 => Some(ADCMUX::Ad3),
4 => Some(ADCMUX::Ad4),
5 => Some(ADCMUX::Ad5),
7 => Some(ADCMUX::Vssa),
_ => None,
}
}
#[doc = "AD0 input"]
#[inline(always)]
pub fn is_ad0(&self) -> bool {
*self == ADCMUX::Ad0
}
#[doc = "AD2 input"]
#[inline(always)]
pub fn is_ad2(&self) -> bool {
*self == ADCMUX::Ad2
}
#[doc = "AD3 input"]
#[inline(always)]
pub fn is_ad3(&self) -> bool {
*self == ADCMUX::Ad3
}
#[doc = "AD4 input"]
#[inline(always)]
pub fn is_ad4(&self) -> bool {
*self == ADCMUX::Ad4
}
#[doc = "AD5 input"]
#[inline(always)]
pub fn is_ad5(&self) -> bool {
*self == ADCMUX::Ad5
}
#[doc = "VSSA input"]
#[inline(always)]
pub fn is_vssa(&self) -> bool {
*self == ADCMUX::Vssa
}
}
#[doc = "Field `ADCMUX` writer - ADC MUX input select"]
pub type ADCMUX_W<'a, REG> = crate::FieldWriter<'a, REG, 3, ADCMUX>;
impl<'a, REG> ADCMUX_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "AD0 input"]
#[inline(always)]
pub fn ad0(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Ad0)
}
#[doc = "AD2 input"]
#[inline(always)]
pub fn ad2(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Ad2)
}
#[doc = "AD3 input"]
#[inline(always)]
pub fn ad3(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Ad3)
}
#[doc = "AD4 input"]
#[inline(always)]
pub fn ad4(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Ad4)
}
#[doc = "AD5 input"]
#[inline(always)]
pub fn ad5(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Ad5)
}
#[doc = "VSSA input"]
#[inline(always)]
pub fn vssa(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Vssa)
}
}
#[doc = "ADC busy\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ADCBUSY {
#[doc = "0: ADC not busy"]
NoOperation = 0,
#[doc = "1: ADC conversion or auto sequencer active"]
Busy = 1,
}
impl From<ADCBUSY> for bool {
#[inline(always)]
fn from(variant: ADCBUSY) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ADCBUSY` reader - ADC busy"]
pub type ADCBUSY_R = crate::BitReader<ADCBUSY>;
impl ADCBUSY_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ADCBUSY {
match self.bits {
false => ADCBUSY::NoOperation,
true => ADCBUSY::Busy,
}
}
#[doc = "ADC not busy"]
#[inline(always)]
pub fn is_no_operation(&self) -> bool {
*self == ADCBUSY::NoOperation
}
#[doc = "ADC conversion or auto sequencer active"]
#[inline(always)]
pub fn is_busy(&self) -> bool {
*self == ADCBUSY::Busy
}
}
#[doc = "ADC conversion mode\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum ADCMODE {
#[doc = "0: single channel"]
Single = 0,
#[doc = "1: automated sequence 0 only"]
Auto0 = 1,
#[doc = "2: automated sequencer 1 only"]
Auto1 = 2,
#[doc = "3: automated sequencer 0 and 1 daisy chained"]
Auto01 = 3,
#[doc = "4: automated sequencer 0 only trigger condition"]
Auto0trig = 4,
#[doc = "5: automated sequencer 1 only trigger condition"]
Auto1trig = 5,
#[doc = "6: automated sequencer 0 and 1 daisy chained trigger"]
Auto01trig = 6,
#[doc = "7: automated sequencer 0 and 1 independently triggered"]
Auto01trigind = 7,
}
impl From<ADCMODE> for u8 {
#[inline(always)]
fn from(variant: ADCMODE) -> Self {
variant as _
}
}
impl crate::FieldSpec for ADCMODE {
type Ux = u8;
}
impl crate::IsEnum for ADCMODE {}
#[doc = "Field `ADCMODE` reader - ADC conversion mode"]
pub type ADCMODE_R = crate::FieldReader<ADCMODE>;
impl ADCMODE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ADCMODE {
match self.bits {
0 => ADCMODE::Single,
1 => ADCMODE::Auto0,
2 => ADCMODE::Auto1,
3 => ADCMODE::Auto01,
4 => ADCMODE::Auto0trig,
5 => ADCMODE::Auto1trig,
6 => ADCMODE::Auto01trig,
7 => ADCMODE::Auto01trigind,
_ => unreachable!(),
}
}
#[doc = "single channel"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == ADCMODE::Single
}
#[doc = "automated sequence 0 only"]
#[inline(always)]
pub fn is_auto0(&self) -> bool {
*self == ADCMODE::Auto0
}
#[doc = "automated sequencer 1 only"]
#[inline(always)]
pub fn is_auto1(&self) -> bool {
*self == ADCMODE::Auto1
}
#[doc = "automated sequencer 0 and 1 daisy chained"]
#[inline(always)]
pub fn is_auto01(&self) -> bool {
*self == ADCMODE::Auto01
}
#[doc = "automated sequencer 0 only trigger condition"]
#[inline(always)]
pub fn is_auto0trig(&self) -> bool {
*self == ADCMODE::Auto0trig
}
#[doc = "automated sequencer 1 only trigger condition"]
#[inline(always)]
pub fn is_auto1trig(&self) -> bool {
*self == ADCMODE::Auto1trig
}
#[doc = "automated sequencer 0 and 1 daisy chained trigger"]
#[inline(always)]
pub fn is_auto01trig(&self) -> bool {
*self == ADCMODE::Auto01trig
}
#[doc = "automated sequencer 0 and 1 independently triggered"]
#[inline(always)]
pub fn is_auto01trigind(&self) -> bool {
*self == ADCMODE::Auto01trigind
}
}
#[doc = "Field `ADCMODE` writer - ADC conversion mode"]
pub type ADCMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, ADCMODE, crate::Safe>;
impl<'a, REG> ADCMODE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "single channel"]
#[inline(always)]
pub fn single(self) -> &'a mut crate::W<REG> {
self.variant(ADCMODE::Single)
}
#[doc = "automated sequence 0 only"]
#[inline(always)]
pub fn auto0(self) -> &'a mut crate::W<REG> {
self.variant(ADCMODE::Auto0)
}
#[doc = "automated sequencer 1 only"]
#[inline(always)]
pub fn auto1(self) -> &'a mut crate::W<REG> {
self.variant(ADCMODE::Auto1)
}
#[doc = "automated sequencer 0 and 1 daisy chained"]
#[inline(always)]
pub fn auto01(self) -> &'a mut crate::W<REG> {
self.variant(ADCMODE::Auto01)
}
#[doc = "automated sequencer 0 only trigger condition"]
#[inline(always)]
pub fn auto0trig(self) -> &'a mut crate::W<REG> {
self.variant(ADCMODE::Auto0trig)
}
#[doc = "automated sequencer 1 only trigger condition"]
#[inline(always)]
pub fn auto1trig(self) -> &'a mut crate::W<REG> {
self.variant(ADCMODE::Auto1trig)
}
#[doc = "automated sequencer 0 and 1 daisy chained trigger"]
#[inline(always)]
pub fn auto01trig(self) -> &'a mut crate::W<REG> {
self.variant(ADCMODE::Auto01trig)
}
#[doc = "automated sequencer 0 and 1 independently triggered"]
#[inline(always)]
pub fn auto01trigind(self) -> &'a mut crate::W<REG> {
self.variant(ADCMODE::Auto01trigind)
}
}
#[doc = "Start ADC Conversion\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ADCSTART {
#[doc = "0: stop ADC conversion"]
Stop = 0,
#[doc = "1: start ADC conversion"]
Start = 1,
}
impl From<ADCSTART> for bool {
#[inline(always)]
fn from(variant: ADCSTART) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ADCSTART` reader - Start ADC Conversion"]
pub type ADCSTART_R = crate::BitReader<ADCSTART>;
impl ADCSTART_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ADCSTART {
match self.bits {
false => ADCSTART::Stop,
true => ADCSTART::Start,
}
}
#[doc = "stop ADC conversion"]
#[inline(always)]
pub fn is_stop(&self) -> bool {
*self == ADCSTART::Stop
}
#[doc = "start ADC conversion"]
#[inline(always)]
pub fn is_start(&self) -> bool {
*self == ADCSTART::Start
}
}
#[doc = "Field `ADCSTART` writer - Start ADC Conversion"]
pub type ADCSTART_W<'a, REG> = crate::BitWriter<'a, REG, ADCSTART>;
impl<'a, REG> ADCSTART_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "stop ADC conversion"]
#[inline(always)]
pub fn stop(self) -> &'a mut crate::W<REG> {
self.variant(ADCSTART::Stop)
}
#[doc = "start ADC conversion"]
#[inline(always)]
pub fn start(self) -> &'a mut crate::W<REG> {
self.variant(ADCSTART::Start)
}
}
#[doc = "ADC Module Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ADCEN {
#[doc = "0: turn off ADC module"]
Disabled = 0,
#[doc = "1: enable ADC module"]
Enabled = 1,
}
impl From<ADCEN> for bool {
#[inline(always)]
fn from(variant: ADCEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ADCEN` reader - ADC Module Enable"]
pub type ADCEN_R = crate::BitReader<ADCEN>;
impl ADCEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ADCEN {
match self.bits {
false => ADCEN::Disabled,
true => ADCEN::Enabled,
}
}
#[doc = "turn off ADC module"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == ADCEN::Disabled
}
#[doc = "enable ADC module"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == ADCEN::Enabled
}
}
#[doc = "Field `ADCEN` writer - ADC Module Enable"]
pub type ADCEN_W<'a, REG> = crate::BitWriter<'a, REG, ADCEN>;
impl<'a, REG> ADCEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "turn off ADC module"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(ADCEN::Disabled)
}
#[doc = "enable ADC module"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(ADCEN::Enabled)
}
}
impl R {
#[doc = "Bits 0:2 - ADC input clock FCLK divider"]
#[inline(always)]
pub fn adccdiv(&self) -> ADCCDIV_R {
ADCCDIV_R::new((self.bits & 7) as u8)
}
#[doc = "Bits 4:6 - ADC MUX input select"]
#[inline(always)]
pub fn adcmux(&self) -> ADCMUX_R {
ADCMUX_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7 - ADC busy"]
#[inline(always)]
pub fn adcbusy(&self) -> ADCBUSY_R {
ADCBUSY_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 10:12 - ADC conversion mode"]
#[inline(always)]
pub fn adcmode(&self) -> ADCMODE_R {
ADCMODE_R::new(((self.bits >> 10) & 7) as u8)
}
#[doc = "Bit 14 - Start ADC Conversion"]
#[inline(always)]
pub fn adcstart(&self) -> ADCSTART_R {
ADCSTART_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - ADC Module Enable"]
#[inline(always)]
pub fn adcen(&self) -> ADCEN_R {
ADCEN_R::new(((self.bits >> 15) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ADCCTL")
.field("adccdiv", &self.adccdiv())
.field("adcmux", &self.adcmux())
.field("adcbusy", &self.adcbusy())
.field("adcmode", &self.adcmode())
.field("adcstart", &self.adcstart())
.field("adcen", &self.adcen())
.finish()
}
}
impl W {
#[doc = "Bits 0:2 - ADC input clock FCLK divider"]
#[inline(always)]
pub fn adccdiv(&mut self) -> ADCCDIV_W<ADCCTLrs> {
ADCCDIV_W::new(self, 0)
}
#[doc = "Bits 4:6 - ADC MUX input select"]
#[inline(always)]
pub fn adcmux(&mut self) -> ADCMUX_W<ADCCTLrs> {
ADCMUX_W::new(self, 4)
}
#[doc = "Bits 10:12 - ADC conversion mode"]
#[inline(always)]
pub fn adcmode(&mut self) -> ADCMODE_W<ADCCTLrs> {
ADCMODE_W::new(self, 10)
}
#[doc = "Bit 14 - Start ADC Conversion"]
#[inline(always)]
pub fn adcstart(&mut self) -> ADCSTART_W<ADCCTLrs> {
ADCSTART_W::new(self, 14)
}
#[doc = "Bit 15 - ADC Module Enable"]
#[inline(always)]
pub fn adcen(&mut self) -> ADCEN_W<ADCCTLrs> {
ADCEN_W::new(self, 15)
}
}
#[doc = "ADC control register\n\nYou can [`read`](crate::Reg::read) this register and get [`adcctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ADCCTLrs;
impl crate::RegisterSpec for ADCCTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`adcctl::R`](R) reader structure"]
impl crate::Readable for ADCCTLrs {}
#[doc = "`write(|w| ..)` method takes [`adcctl::W`](W) writer structure"]
impl crate::Writable for ADCCTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ADCCTL to value 0"]
impl crate::Resettable for ADCCTLrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ADCCR (r) register accessor: ADC conversion result register\n\nYou can [`read`](crate::Reg::read) this register and get [`adccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adccr`]
module"]
pub type ADCCR = crate::Reg<adccr::ADCCRrs>;
#[doc = "ADC conversion result register"]
pub mod adccr {
#[doc = "Register `ADCCR` reader"]
pub type R = crate::R<ADCCRrs>;
#[doc = "Field `ADCRESULT` reader - ADC conversion result"]
pub type ADCRESULT_R = crate::FieldReader<u16>;
impl R {
#[doc = "Bits 0:15 - ADC conversion result"]
#[inline(always)]
pub fn adcresult(&self) -> ADCRESULT_R {
ADCRESULT_R::new((self.bits & 0xffff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ADCCR")
.field("adcresult", &self.adcresult())
.finish()
}
}
#[doc = "ADC conversion result register\n\nYou can [`read`](crate::Reg::read) this register and get [`adccr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ADCCRrs;
impl crate::RegisterSpec for ADCCRrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`adccr::R`](R) reader structure"]
impl crate::Readable for ADCCRrs {}
#[doc = "`reset()` method sets ADCCR to value 0"]
impl crate::Resettable for ADCCRrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "ADCINT (rw) register accessor: ADC interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`adcint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcint`]
module"]
pub type ADCINT = crate::Reg<adcint::ADCINTrs>;
#[doc = "ADC interrupt register"]
pub mod adcint {
#[doc = "Register `ADCINT` reader"]
pub type R = crate::R<ADCINTrs>;
#[doc = "Register `ADCINT` writer"]
pub type W = crate::W<ADCINTrs>;
#[doc = "ADC conversion finished interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ADCINT {
#[doc = "0: no interrupt"]
None = 0,
#[doc = "1: interrupt, write 1b to clear"]
Interrupt = 1,
}
impl From<ADCINT> for bool {
#[inline(always)]
fn from(variant: ADCINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ADCINT` reader - ADC conversion finished interrupt"]
pub type ADCINT_R = crate::BitReader<ADCINT>;
impl ADCINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ADCINT {
match self.bits {
false => ADCINT::None,
true => ADCINT::Interrupt,
}
}
#[doc = "no interrupt"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == ADCINT::None
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == ADCINT::Interrupt
}
}
#[doc = "Field `ADCINT` writer - ADC conversion finished interrupt"]
pub type ADCINT_W<'a, REG> = crate::BitWriter<'a, REG, ADCINT>;
impl<'a, REG> ADCINT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "no interrupt"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(ADCINT::None)
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(ADCINT::Interrupt)
}
}
#[doc = "EMUX data transfer finished interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum EMUXINT {
#[doc = "0: no interrupt"]
None = 0,
#[doc = "1: interrupt, write 1b to clear"]
Interrupt = 1,
}
impl From<EMUXINT> for bool {
#[inline(always)]
fn from(variant: EMUXINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `EMUXINT` reader - EMUX data transfer finished interrupt"]
pub type EMUXINT_R = crate::BitReader<EMUXINT>;
impl EMUXINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> EMUXINT {
match self.bits {
false => EMUXINT::None,
true => EMUXINT::Interrupt,
}
}
#[doc = "no interrupt"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == EMUXINT::None
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == EMUXINT::Interrupt
}
}
#[doc = "Field `EMUXINT` writer - EMUX data transfer finished interrupt"]
pub type EMUXINT_W<'a, REG> = crate::BitWriter<'a, REG, EMUXINT>;
impl<'a, REG> EMUXINT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "no interrupt"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(EMUXINT::None)
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(EMUXINT::Interrupt)
}
}
#[doc = "Auto sequencer 0 conversions finished interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum AS0INT {
#[doc = "0: no interrupt"]
None = 0,
#[doc = "1: interrupt, write 1b to clear"]
Interrupt = 1,
}
impl From<AS0INT> for bool {
#[inline(always)]
fn from(variant: AS0INT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `AS0INT` reader - Auto sequencer 0 conversions finished interrupt"]
pub type AS0INT_R = crate::BitReader<AS0INT>;
impl AS0INT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> AS0INT {
match self.bits {
false => AS0INT::None,
true => AS0INT::Interrupt,
}
}
#[doc = "no interrupt"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == AS0INT::None
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == AS0INT::Interrupt
}
}
#[doc = "Field `AS0INT` writer - Auto sequencer 0 conversions finished interrupt"]
pub type AS0INT_W<'a, REG> = crate::BitWriter<'a, REG, AS0INT>;
impl<'a, REG> AS0INT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "no interrupt"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(AS0INT::None)
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(AS0INT::Interrupt)
}
}
#[doc = "Auto sequencer 1 conversions finished interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum AS1INT {
#[doc = "0: no interrupt"]
None = 0,
#[doc = "1: interrupt, write 1b to clear"]
Interrupt = 1,
}
impl From<AS1INT> for bool {
#[inline(always)]
fn from(variant: AS1INT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `AS1INT` reader - Auto sequencer 1 conversions finished interrupt"]
pub type AS1INT_R = crate::BitReader<AS1INT>;
impl AS1INT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> AS1INT {
match self.bits {
false => AS1INT::None,
true => AS1INT::Interrupt,
}
}
#[doc = "no interrupt"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == AS1INT::None
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == AS1INT::Interrupt
}
}
#[doc = "Field `AS1INT` writer - Auto sequencer 1 conversions finished interrupt"]
pub type AS1INT_W<'a, REG> = crate::BitWriter<'a, REG, AS1INT>;
impl<'a, REG> AS1INT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "no interrupt"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(AS1INT::None)
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(AS1INT::Interrupt)
}
}
#[doc = "Auto sequencer collision interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ASCINT {
#[doc = "0: no interrupt"]
None = 0,
#[doc = "1: interrupt, write 1b to clear"]
Interrupt = 1,
}
impl From<ASCINT> for bool {
#[inline(always)]
fn from(variant: ASCINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ASCINT` reader - Auto sequencer collision interrupt"]
pub type ASCINT_R = crate::BitReader<ASCINT>;
impl ASCINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ASCINT {
match self.bits {
false => ASCINT::None,
true => ASCINT::Interrupt,
}
}
#[doc = "no interrupt"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == ASCINT::None
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == ASCINT::Interrupt
}
}
#[doc = "Field `ASCINT` writer - Auto sequencer collision interrupt"]
pub type ASCINT_W<'a, REG> = crate::BitWriter<'a, REG, ASCINT>;
impl<'a, REG> ASCINT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "no interrupt"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(ASCINT::None)
}
#[doc = "interrupt, write 1b to clear"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(ASCINT::Interrupt)
}
}
#[doc = "ADC conversion finished interrupt enabled\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ADCINT_EN {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<ADCINT_EN> for bool {
#[inline(always)]
fn from(variant: ADCINT_EN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ADCINT_EN` reader - ADC conversion finished interrupt enabled"]
pub type ADCINT_EN_R = crate::BitReader<ADCINT_EN>;
impl ADCINT_EN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ADCINT_EN {
match self.bits {
false => ADCINT_EN::Disabled,
true => ADCINT_EN::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == ADCINT_EN::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == ADCINT_EN::Enabled
}
}
#[doc = "Field `ADCINT_EN` writer - ADC conversion finished interrupt enabled"]
pub type ADCINT_EN_W<'a, REG> = crate::BitWriter<'a, REG, ADCINT_EN>;
impl<'a, REG> ADCINT_EN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(ADCINT_EN::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(ADCINT_EN::Enabled)
}
}
#[doc = "EMUX transfer finished interrupt enabled\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum EMUXINT_EN {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<EMUXINT_EN> for bool {
#[inline(always)]
fn from(variant: EMUXINT_EN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `EMUXINT_EN` reader - EMUX transfer finished interrupt enabled"]
pub type EMUXINT_EN_R = crate::BitReader<EMUXINT_EN>;
impl EMUXINT_EN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> EMUXINT_EN {
match self.bits {
false => EMUXINT_EN::Disabled,
true => EMUXINT_EN::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == EMUXINT_EN::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == EMUXINT_EN::Enabled
}
}
#[doc = "Field `EMUXINT_EN` writer - EMUX transfer finished interrupt enabled"]
pub type EMUXINT_EN_W<'a, REG> = crate::BitWriter<'a, REG, EMUXINT_EN>;
impl<'a, REG> EMUXINT_EN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(EMUXINT_EN::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(EMUXINT_EN::Enabled)
}
}
#[doc = "Enable auto sequencer 0 conversions finished interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum AS0INT_EN {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<AS0INT_EN> for bool {
#[inline(always)]
fn from(variant: AS0INT_EN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `AS0INT_EN` reader - Enable auto sequencer 0 conversions finished interrupt"]
pub type AS0INT_EN_R = crate::BitReader<AS0INT_EN>;
impl AS0INT_EN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> AS0INT_EN {
match self.bits {
false => AS0INT_EN::Disabled,
true => AS0INT_EN::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == AS0INT_EN::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == AS0INT_EN::Enabled
}
}
#[doc = "Field `AS0INT_EN` writer - Enable auto sequencer 0 conversions finished interrupt"]
pub type AS0INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, AS0INT_EN>;
impl<'a, REG> AS0INT_EN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(AS0INT_EN::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(AS0INT_EN::Enabled)
}
}
#[doc = "Enable auto sequencer 1 conversions finished interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum AS1INT_EN {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<AS1INT_EN> for bool {
#[inline(always)]
fn from(variant: AS1INT_EN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `AS1INT_EN` reader - Enable auto sequencer 1 conversions finished interrupt"]
pub type AS1INT_EN_R = crate::BitReader<AS1INT_EN>;
impl AS1INT_EN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> AS1INT_EN {
match self.bits {
false => AS1INT_EN::Disabled,
true => AS1INT_EN::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == AS1INT_EN::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == AS1INT_EN::Enabled
}
}
#[doc = "Field `AS1INT_EN` writer - Enable auto sequencer 1 conversions finished interrupt"]
pub type AS1INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, AS1INT_EN>;
impl<'a, REG> AS1INT_EN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(AS1INT_EN::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(AS1INT_EN::Enabled)
}
}
#[doc = "Enable auto sequencer collision interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ASCINT_EN {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<ASCINT_EN> for bool {
#[inline(always)]
fn from(variant: ASCINT_EN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ASCINT_EN` reader - Enable auto sequencer collision interrupt"]
pub type ASCINT_EN_R = crate::BitReader<ASCINT_EN>;
impl ASCINT_EN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ASCINT_EN {
match self.bits {
false => ASCINT_EN::Disabled,
true => ASCINT_EN::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == ASCINT_EN::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == ASCINT_EN::Enabled
}
}
#[doc = "Field `ASCINT_EN` writer - Enable auto sequencer collision interrupt"]
pub type ASCINT_EN_W<'a, REG> = crate::BitWriter<'a, REG, ASCINT_EN>;
impl<'a, REG> ASCINT_EN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(ASCINT_EN::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(ASCINT_EN::Enabled)
}
}
#[doc = "Last auto sequencer to trigger ADCINT.ASCINT\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum ASCINTSEQ {
#[doc = "0: no trigger"]
None = 0,
#[doc = "1: auto sequencer 0 triggered interrupt"]
As0 = 1,
#[doc = "2: Auto sequencer 1 triggered interrupt"]
As1 = 2,
#[doc = "3: Both auto sequencer 0 and 1 triggered interrupt"]
Both = 3,
}
impl From<ASCINTSEQ> for u8 {
#[inline(always)]
fn from(variant: ASCINTSEQ) -> Self {
variant as _
}
}
impl crate::FieldSpec for ASCINTSEQ {
type Ux = u8;
}
impl crate::IsEnum for ASCINTSEQ {}
#[doc = "Field `ASCINTSEQ` reader - Last auto sequencer to trigger ADCINT.ASCINT"]
pub type ASCINTSEQ_R = crate::FieldReader<ASCINTSEQ>;
impl ASCINTSEQ_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ASCINTSEQ {
match self.bits {
0 => ASCINTSEQ::None,
1 => ASCINTSEQ::As0,
2 => ASCINTSEQ::As1,
3 => ASCINTSEQ::Both,
_ => unreachable!(),
}
}
#[doc = "no trigger"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == ASCINTSEQ::None
}
#[doc = "auto sequencer 0 triggered interrupt"]
#[inline(always)]
pub fn is_as0(&self) -> bool {
*self == ASCINTSEQ::As0
}
#[doc = "Auto sequencer 1 triggered interrupt"]
#[inline(always)]
pub fn is_as1(&self) -> bool {
*self == ASCINTSEQ::As1
}
#[doc = "Both auto sequencer 0 and 1 triggered interrupt"]
#[inline(always)]
pub fn is_both(&self) -> bool {
*self == ASCINTSEQ::Both
}
}
#[doc = "Field `ASCINTSEQ` writer - Last auto sequencer to trigger ADCINT.ASCINT"]
pub type ASCINTSEQ_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ASCINTSEQ, crate::Safe>;
impl<'a, REG> ASCINTSEQ_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "no trigger"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(ASCINTSEQ::None)
}
#[doc = "auto sequencer 0 triggered interrupt"]
#[inline(always)]
pub fn as0(self) -> &'a mut crate::W<REG> {
self.variant(ASCINTSEQ::As0)
}
#[doc = "Auto sequencer 1 triggered interrupt"]
#[inline(always)]
pub fn as1(self) -> &'a mut crate::W<REG> {
self.variant(ASCINTSEQ::As1)
}
#[doc = "Both auto sequencer 0 and 1 triggered interrupt"]
#[inline(always)]
pub fn both(self) -> &'a mut crate::W<REG> {
self.variant(ASCINTSEQ::Both)
}
}
#[doc = "Last auto sequencer to run\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum ASCINTTR {
#[doc = "0: no sequencer ran"]
None = 0,
#[doc = "1: auto sequencer 0 last ran"]
As0 = 1,
#[doc = "2: Auto sequencer 1 last ran"]
As1 = 2,
}
impl From<ASCINTTR> for u8 {
#[inline(always)]
fn from(variant: ASCINTTR) -> Self {
variant as _
}
}
impl crate::FieldSpec for ASCINTTR {
type Ux = u8;
}
impl crate::IsEnum for ASCINTTR {}
#[doc = "Field `ASCINTTR` reader - Last auto sequencer to run"]
pub type ASCINTTR_R = crate::FieldReader<ASCINTTR>;
impl ASCINTTR_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<ASCINTTR> {
match self.bits {
0 => Some(ASCINTTR::None),
1 => Some(ASCINTTR::As0),
2 => Some(ASCINTTR::As1),
_ => None,
}
}
#[doc = "no sequencer ran"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == ASCINTTR::None
}
#[doc = "auto sequencer 0 last ran"]
#[inline(always)]
pub fn is_as0(&self) -> bool {
*self == ASCINTTR::As0
}
#[doc = "Auto sequencer 1 last ran"]
#[inline(always)]
pub fn is_as1(&self) -> bool {
*self == ASCINTTR::As1
}
}
#[doc = "Field `ASCINTTR` writer - Last auto sequencer to run"]
pub type ASCINTTR_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ASCINTTR>;
impl<'a, REG> ASCINTTR_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "no sequencer ran"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(ASCINTTR::None)
}
#[doc = "auto sequencer 0 last ran"]
#[inline(always)]
pub fn as0(self) -> &'a mut crate::W<REG> {
self.variant(ASCINTTR::As0)
}
#[doc = "Auto sequencer 1 last ran"]
#[inline(always)]
pub fn as1(self) -> &'a mut crate::W<REG> {
self.variant(ASCINTTR::As1)
}
}
impl R {
#[doc = "Bit 0 - ADC conversion finished interrupt"]
#[inline(always)]
pub fn adcint(&self) -> ADCINT_R {
ADCINT_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - EMUX data transfer finished interrupt"]
#[inline(always)]
pub fn emuxint(&self) -> EMUXINT_R {
EMUXINT_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Auto sequencer 0 conversions finished interrupt"]
#[inline(always)]
pub fn as0int(&self) -> AS0INT_R {
AS0INT_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Auto sequencer 1 conversions finished interrupt"]
#[inline(always)]
pub fn as1int(&self) -> AS1INT_R {
AS1INT_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Auto sequencer collision interrupt"]
#[inline(always)]
pub fn ascint(&self) -> ASCINT_R {
ASCINT_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 8 - ADC conversion finished interrupt enabled"]
#[inline(always)]
pub fn adcint_en(&self) -> ADCINT_EN_R {
ADCINT_EN_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - EMUX transfer finished interrupt enabled"]
#[inline(always)]
pub fn emuxint_en(&self) -> EMUXINT_EN_R {
EMUXINT_EN_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Enable auto sequencer 0 conversions finished interrupt"]
#[inline(always)]
pub fn as0int_en(&self) -> AS0INT_EN_R {
AS0INT_EN_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Enable auto sequencer 1 conversions finished interrupt"]
#[inline(always)]
pub fn as1int_en(&self) -> AS1INT_EN_R {
AS1INT_EN_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Enable auto sequencer collision interrupt"]
#[inline(always)]
pub fn ascint_en(&self) -> ASCINT_EN_R {
ASCINT_EN_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bits 16:17 - Last auto sequencer to trigger ADCINT.ASCINT"]
#[inline(always)]
pub fn ascintseq(&self) -> ASCINTSEQ_R {
ASCINTSEQ_R::new(((self.bits >> 16) & 3) as u8)
}
#[doc = "Bits 18:19 - Last auto sequencer to run"]
#[inline(always)]
pub fn ascinttr(&self) -> ASCINTTR_R {
ASCINTTR_R::new(((self.bits >> 18) & 3) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ADCINT")
.field("adcint", &self.adcint())
.field("emuxint", &self.emuxint())
.field("as0int", &self.as0int())
.field("as1int", &self.as1int())
.field("ascint", &self.ascint())
.field("adcint_en", &self.adcint_en())
.field("emuxint_en", &self.emuxint_en())
.field("as0int_en", &self.as0int_en())
.field("as1int_en", &self.as1int_en())
.field("ascint_en", &self.ascint_en())
.field("ascintseq", &self.ascintseq())
.field("ascinttr", &self.ascinttr())
.finish()
}
}
impl W {
#[doc = "Bit 0 - ADC conversion finished interrupt"]
#[inline(always)]
pub fn adcint(&mut self) -> ADCINT_W<ADCINTrs> {
ADCINT_W::new(self, 0)
}
#[doc = "Bit 1 - EMUX data transfer finished interrupt"]
#[inline(always)]
pub fn emuxint(&mut self) -> EMUXINT_W<ADCINTrs> {
EMUXINT_W::new(self, 1)
}
#[doc = "Bit 2 - Auto sequencer 0 conversions finished interrupt"]
#[inline(always)]
pub fn as0int(&mut self) -> AS0INT_W<ADCINTrs> {
AS0INT_W::new(self, 2)
}
#[doc = "Bit 3 - Auto sequencer 1 conversions finished interrupt"]
#[inline(always)]
pub fn as1int(&mut self) -> AS1INT_W<ADCINTrs> {
AS1INT_W::new(self, 3)
}
#[doc = "Bit 4 - Auto sequencer collision interrupt"]
#[inline(always)]
pub fn ascint(&mut self) -> ASCINT_W<ADCINTrs> {
ASCINT_W::new(self, 4)
}
#[doc = "Bit 8 - ADC conversion finished interrupt enabled"]
#[inline(always)]
pub fn adcint_en(&mut self) -> ADCINT_EN_W<ADCINTrs> {
ADCINT_EN_W::new(self, 8)
}
#[doc = "Bit 9 - EMUX transfer finished interrupt enabled"]
#[inline(always)]
pub fn emuxint_en(&mut self) -> EMUXINT_EN_W<ADCINTrs> {
EMUXINT_EN_W::new(self, 9)
}
#[doc = "Bit 10 - Enable auto sequencer 0 conversions finished interrupt"]
#[inline(always)]
pub fn as0int_en(&mut self) -> AS0INT_EN_W<ADCINTrs> {
AS0INT_EN_W::new(self, 10)
}
#[doc = "Bit 11 - Enable auto sequencer 1 conversions finished interrupt"]
#[inline(always)]
pub fn as1int_en(&mut self) -> AS1INT_EN_W<ADCINTrs> {
AS1INT_EN_W::new(self, 11)
}
#[doc = "Bit 12 - Enable auto sequencer collision interrupt"]
#[inline(always)]
pub fn ascint_en(&mut self) -> ASCINT_EN_W<ADCINTrs> {
ASCINT_EN_W::new(self, 12)
}
#[doc = "Bits 16:17 - Last auto sequencer to trigger ADCINT.ASCINT"]
#[inline(always)]
pub fn ascintseq(&mut self) -> ASCINTSEQ_W<ADCINTrs> {
ASCINTSEQ_W::new(self, 16)
}
#[doc = "Bits 18:19 - Last auto sequencer to run"]
#[inline(always)]
pub fn ascinttr(&mut self) -> ASCINTTR_W<ADCINTrs> {
ASCINTTR_W::new(self, 18)
}
}
#[doc = "ADC interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`adcint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ADCINTrs;
impl crate::RegisterSpec for ADCINTrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`adcint::R`](R) reader structure"]
impl crate::Readable for ADCINTrs {}
#[doc = "`write(|w| ..)` method takes [`adcint::W`](W) writer structure"]
impl crate::Writable for ADCINTrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ADCINT to value 0"]
impl crate::Resettable for ADCINTrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AS0CTL (rw) register accessor: Auto sequencer 0 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as0ctl`]
module"]
pub type AS0CTL = crate::Reg<as0ctl::AS0CTLrs>;
#[doc = "Auto sequencer 0 control register"]
pub mod as0ctl {
#[doc = "Register `AS0CTL` reader"]
pub type R = crate::R<AS0CTLrs>;
#[doc = "Register `AS0CTL` writer"]
pub type W = crate::W<AS0CTLrs>;
#[doc = "Auto sequencer PWM trigger source\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum ASAX_TRPWM {
#[doc = "0: PWMA0 Trigger"]
Pwma0 = 0,
#[doc = "1: PWMA1 Trigger"]
Pwma1 = 1,
#[doc = "2: PWMA2 Trigger"]
Pwma2 = 2,
#[doc = "3: PWMA3 Trigger"]
Pwma3 = 3,
#[doc = "4: PWMA4 Trigger"]
Pwma4 = 4,
#[doc = "5: PWMA5 Trigger"]
Pwma5 = 5,
#[doc = "6: PWMA6 Trigger"]
Pwma6 = 6,
#[doc = "7: PWMA7 Trigger"]
Pwma7 = 7,
#[doc = "8: PWMB0"]
Pwmb0 = 8,
#[doc = "9: PWMB1"]
Pwmb1 = 9,
#[doc = "10: PWMC0"]
Pwmc0 = 10,
#[doc = "11: PWMC1"]
Pwmc1 = 11,
#[doc = "12: PWMD0"]
Pwmd0 = 12,
#[doc = "13: PWMD1"]
Pwmd1 = 13,
}
impl From<ASAX_TRPWM> for u8 {
#[inline(always)]
fn from(variant: ASAX_TRPWM) -> Self {
variant as _
}
}
impl crate::FieldSpec for ASAX_TRPWM {
type Ux = u8;
}
impl crate::IsEnum for ASAX_TRPWM {}
#[doc = "Field `ASAxTRPWM` reader - Auto sequencer PWM trigger source"]
pub type ASAX_TRPWM_R = crate::FieldReader<ASAX_TRPWM>;
impl ASAX_TRPWM_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<ASAX_TRPWM> {
match self.bits {
0 => Some(ASAX_TRPWM::Pwma0),
1 => Some(ASAX_TRPWM::Pwma1),
2 => Some(ASAX_TRPWM::Pwma2),
3 => Some(ASAX_TRPWM::Pwma3),
4 => Some(ASAX_TRPWM::Pwma4),
5 => Some(ASAX_TRPWM::Pwma5),
6 => Some(ASAX_TRPWM::Pwma6),
7 => Some(ASAX_TRPWM::Pwma7),
8 => Some(ASAX_TRPWM::Pwmb0),
9 => Some(ASAX_TRPWM::Pwmb1),
10 => Some(ASAX_TRPWM::Pwmc0),
11 => Some(ASAX_TRPWM::Pwmc1),
12 => Some(ASAX_TRPWM::Pwmd0),
13 => Some(ASAX_TRPWM::Pwmd1),
_ => None,
}
}
#[doc = "PWMA0 Trigger"]
#[inline(always)]
pub fn is_pwma0(&self) -> bool {
*self == ASAX_TRPWM::Pwma0
}
#[doc = "PWMA1 Trigger"]
#[inline(always)]
pub fn is_pwma1(&self) -> bool {
*self == ASAX_TRPWM::Pwma1
}
#[doc = "PWMA2 Trigger"]
#[inline(always)]
pub fn is_pwma2(&self) -> bool {
*self == ASAX_TRPWM::Pwma2
}
#[doc = "PWMA3 Trigger"]
#[inline(always)]
pub fn is_pwma3(&self) -> bool {
*self == ASAX_TRPWM::Pwma3
}
#[doc = "PWMA4 Trigger"]
#[inline(always)]
pub fn is_pwma4(&self) -> bool {
*self == ASAX_TRPWM::Pwma4
}
#[doc = "PWMA5 Trigger"]
#[inline(always)]
pub fn is_pwma5(&self) -> bool {
*self == ASAX_TRPWM::Pwma5
}
#[doc = "PWMA6 Trigger"]
#[inline(always)]
pub fn is_pwma6(&self) -> bool {
*self == ASAX_TRPWM::Pwma6
}
#[doc = "PWMA7 Trigger"]
#[inline(always)]
pub fn is_pwma7(&self) -> bool {
*self == ASAX_TRPWM::Pwma7
}
#[doc = "PWMB0"]
#[inline(always)]
pub fn is_pwmb0(&self) -> bool {
*self == ASAX_TRPWM::Pwmb0
}
#[doc = "PWMB1"]
#[inline(always)]
pub fn is_pwmb1(&self) -> bool {
*self == ASAX_TRPWM::Pwmb1
}
#[doc = "PWMC0"]
#[inline(always)]
pub fn is_pwmc0(&self) -> bool {
*self == ASAX_TRPWM::Pwmc0
}
#[doc = "PWMC1"]
#[inline(always)]
pub fn is_pwmc1(&self) -> bool {
*self == ASAX_TRPWM::Pwmc1
}
#[doc = "PWMD0"]
#[inline(always)]
pub fn is_pwmd0(&self) -> bool {
*self == ASAX_TRPWM::Pwmd0
}
#[doc = "PWMD1"]
#[inline(always)]
pub fn is_pwmd1(&self) -> bool {
*self == ASAX_TRPWM::Pwmd1
}
}
#[doc = "Field `ASAxTRPWM` writer - Auto sequencer PWM trigger source"]
pub type ASAX_TRPWM_W<'a, REG> = crate::FieldWriter<'a, REG, 4, ASAX_TRPWM>;
impl<'a, REG> ASAX_TRPWM_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWMA0 Trigger"]
#[inline(always)]
pub fn pwma0(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwma0)
}
#[doc = "PWMA1 Trigger"]
#[inline(always)]
pub fn pwma1(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwma1)
}
#[doc = "PWMA2 Trigger"]
#[inline(always)]
pub fn pwma2(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwma2)
}
#[doc = "PWMA3 Trigger"]
#[inline(always)]
pub fn pwma3(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwma3)
}
#[doc = "PWMA4 Trigger"]
#[inline(always)]
pub fn pwma4(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwma4)
}
#[doc = "PWMA5 Trigger"]
#[inline(always)]
pub fn pwma5(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwma5)
}
#[doc = "PWMA6 Trigger"]
#[inline(always)]
pub fn pwma6(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwma6)
}
#[doc = "PWMA7 Trigger"]
#[inline(always)]
pub fn pwma7(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwma7)
}
#[doc = "PWMB0"]
#[inline(always)]
pub fn pwmb0(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwmb0)
}
#[doc = "PWMB1"]
#[inline(always)]
pub fn pwmb1(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwmb1)
}
#[doc = "PWMC0"]
#[inline(always)]
pub fn pwmc0(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwmc0)
}
#[doc = "PWMC1"]
#[inline(always)]
pub fn pwmc1(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwmc1)
}
#[doc = "PWMD0"]
#[inline(always)]
pub fn pwmd0(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwmd0)
}
#[doc = "PWMD1"]
#[inline(always)]
pub fn pwmd1(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwmd1)
}
}
#[doc = "Auto sequencer timer trigger source\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum ASAX_TRTMR {
#[doc = "0: Timer A"]
TimerA = 0,
#[doc = "1: Timer B"]
TimerB = 1,
#[doc = "2: Timer C"]
TimerC = 2,
#[doc = "3: Timer D"]
TimerD = 3,
}
impl From<ASAX_TRTMR> for u8 {
#[inline(always)]
fn from(variant: ASAX_TRTMR) -> Self {
variant as _
}
}
impl crate::FieldSpec for ASAX_TRTMR {
type Ux = u8;
}
impl crate::IsEnum for ASAX_TRTMR {}
#[doc = "Field `ASAxTRTMR` reader - Auto sequencer timer trigger source"]
pub type ASAX_TRTMR_R = crate::FieldReader<ASAX_TRTMR>;
impl ASAX_TRTMR_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ASAX_TRTMR {
match self.bits {
0 => ASAX_TRTMR::TimerA,
1 => ASAX_TRTMR::TimerB,
2 => ASAX_TRTMR::TimerC,
3 => ASAX_TRTMR::TimerD,
_ => unreachable!(),
}
}
#[doc = "Timer A"]
#[inline(always)]
pub fn is_timer_a(&self) -> bool {
*self == ASAX_TRTMR::TimerA
}
#[doc = "Timer B"]
#[inline(always)]
pub fn is_timer_b(&self) -> bool {
*self == ASAX_TRTMR::TimerB
}
#[doc = "Timer C"]
#[inline(always)]
pub fn is_timer_c(&self) -> bool {
*self == ASAX_TRTMR::TimerC
}
#[doc = "Timer D"]
#[inline(always)]
pub fn is_timer_d(&self) -> bool {
*self == ASAX_TRTMR::TimerD
}
}
#[doc = "Field `ASAxTRTMR` writer - Auto sequencer timer trigger source"]
pub type ASAX_TRTMR_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ASAX_TRTMR, crate::Safe>;
impl<'a, REG> ASAX_TRTMR_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A"]
#[inline(always)]
pub fn timer_a(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRTMR::TimerA)
}
#[doc = "Timer B"]
#[inline(always)]
pub fn timer_b(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRTMR::TimerB)
}
#[doc = "Timer C"]
#[inline(always)]
pub fn timer_c(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRTMR::TimerC)
}
#[doc = "Timer D"]
#[inline(always)]
pub fn timer_d(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRTMR::TimerD)
}
}
#[doc = "Auto sequencer trigger source ASxCTL.ASxTR edge\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ASX_TRE {
#[doc = "0: High to low edge"]
HighToLow = 0,
#[doc = "1: Low to high edge"]
LowToHigh = 1,
}
impl From<ASX_TRE> for bool {
#[inline(always)]
fn from(variant: ASX_TRE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ASxTRE` reader - Auto sequencer trigger source ASxCTL.ASxTR edge"]
pub type ASX_TRE_R = crate::BitReader<ASX_TRE>;
impl ASX_TRE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ASX_TRE {
match self.bits {
false => ASX_TRE::HighToLow,
true => ASX_TRE::LowToHigh,
}
}
#[doc = "High to low edge"]
#[inline(always)]
pub fn is_high_to_low(&self) -> bool {
*self == ASX_TRE::HighToLow
}
#[doc = "Low to high edge"]
#[inline(always)]
pub fn is_low_to_high(&self) -> bool {
*self == ASX_TRE::LowToHigh
}
}
#[doc = "Field `ASxTRE` writer - Auto sequencer trigger source ASxCTL.ASxTR edge"]
pub type ASX_TRE_W<'a, REG> = crate::BitWriter<'a, REG, ASX_TRE>;
impl<'a, REG> ASX_TRE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "High to low edge"]
#[inline(always)]
pub fn high_to_low(self) -> &'a mut crate::W<REG> {
self.variant(ASX_TRE::HighToLow)
}
#[doc = "Low to high edge"]
#[inline(always)]
pub fn low_to_high(self) -> &'a mut crate::W<REG> {
self.variant(ASX_TRE::LowToHigh)
}
}
#[doc = "Auto sequencer trigger source\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ASX_TR {
#[doc = "0: PWM, as defined by ASxCTL.ASxTRPWM"]
Pwm = 0,
#[doc = "1: Timer, as defined by ASxCTL.ASxTRTMR"]
Timer = 1,
}
impl From<ASX_TR> for bool {
#[inline(always)]
fn from(variant: ASX_TR) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ASxTR` reader - Auto sequencer trigger source"]
pub type ASX_TR_R = crate::BitReader<ASX_TR>;
impl ASX_TR_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ASX_TR {
match self.bits {
false => ASX_TR::Pwm,
true => ASX_TR::Timer,
}
}
#[doc = "PWM, as defined by ASxCTL.ASxTRPWM"]
#[inline(always)]
pub fn is_pwm(&self) -> bool {
*self == ASX_TR::Pwm
}
#[doc = "Timer, as defined by ASxCTL.ASxTRTMR"]
#[inline(always)]
pub fn is_timer(&self) -> bool {
*self == ASX_TR::Timer
}
}
#[doc = "Field `ASxTR` writer - Auto sequencer trigger source"]
pub type ASX_TR_W<'a, REG> = crate::BitWriter<'a, REG, ASX_TR>;
impl<'a, REG> ASX_TR_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "PWM, as defined by ASxCTL.ASxTRPWM"]
#[inline(always)]
pub fn pwm(self) -> &'a mut crate::W<REG> {
self.variant(ASX_TR::Pwm)
}
#[doc = "Timer, as defined by ASxCTL.ASxTRTMR"]
#[inline(always)]
pub fn timer(self) -> &'a mut crate::W<REG> {
self.variant(ASX_TR::Timer)
}
}
#[doc = "Auto sequencer sampling depth\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum ASX_D {
#[doc = "0: 1 sample"]
_1 = 0,
#[doc = "1: 2 samples"]
_2 = 1,
#[doc = "2: 3 samples"]
_3 = 2,
#[doc = "3: 4 samples"]
_4 = 3,
#[doc = "4: 5 samples"]
_5 = 4,
#[doc = "5: 6 samples"]
_6 = 5,
#[doc = "6: 7 samples"]
_7 = 6,
#[doc = "7: 8 samples"]
_8 = 7,
}
impl From<ASX_D> for u8 {
#[inline(always)]
fn from(variant: ASX_D) -> Self {
variant as _
}
}
impl crate::FieldSpec for ASX_D {
type Ux = u8;
}
impl crate::IsEnum for ASX_D {}
#[doc = "Field `ASxD` reader - Auto sequencer sampling depth"]
pub type ASX_D_R = crate::FieldReader<ASX_D>;
impl ASX_D_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ASX_D {
match self.bits {
0 => ASX_D::_1,
1 => ASX_D::_2,
2 => ASX_D::_3,
3 => ASX_D::_4,
4 => ASX_D::_5,
5 => ASX_D::_6,
6 => ASX_D::_7,
7 => ASX_D::_8,
_ => unreachable!(),
}
}
#[doc = "1 sample"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == ASX_D::_1
}
#[doc = "2 samples"]
#[inline(always)]
pub fn is_2(&self) -> bool {
*self == ASX_D::_2
}
#[doc = "3 samples"]
#[inline(always)]
pub fn is_3(&self) -> bool {
*self == ASX_D::_3
}
#[doc = "4 samples"]
#[inline(always)]
pub fn is_4(&self) -> bool {
*self == ASX_D::_4
}
#[doc = "5 samples"]
#[inline(always)]
pub fn is_5(&self) -> bool {
*self == ASX_D::_5
}
#[doc = "6 samples"]
#[inline(always)]
pub fn is_6(&self) -> bool {
*self == ASX_D::_6
}
#[doc = "7 samples"]
#[inline(always)]
pub fn is_7(&self) -> bool {
*self == ASX_D::_7
}
#[doc = "8 samples"]
#[inline(always)]
pub fn is_8(&self) -> bool {
*self == ASX_D::_8
}
}
#[doc = "Field `ASxD` writer - Auto sequencer sampling depth"]
pub type ASX_D_W<'a, REG> = crate::FieldWriter<'a, REG, 3, ASX_D, crate::Safe>;
impl<'a, REG> ASX_D_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "1 sample"]
#[inline(always)]
pub fn _1(self) -> &'a mut crate::W<REG> {
self.variant(ASX_D::_1)
}
#[doc = "2 samples"]
#[inline(always)]
pub fn _2(self) -> &'a mut crate::W<REG> {
self.variant(ASX_D::_2)
}
#[doc = "3 samples"]
#[inline(always)]
pub fn _3(self) -> &'a mut crate::W<REG> {
self.variant(ASX_D::_3)
}
#[doc = "4 samples"]
#[inline(always)]
pub fn _4(self) -> &'a mut crate::W<REG> {
self.variant(ASX_D::_4)
}
#[doc = "5 samples"]
#[inline(always)]
pub fn _5(self) -> &'a mut crate::W<REG> {
self.variant(ASX_D::_5)
}
#[doc = "6 samples"]
#[inline(always)]
pub fn _6(self) -> &'a mut crate::W<REG> {
self.variant(ASX_D::_6)
}
#[doc = "7 samples"]
#[inline(always)]
pub fn _7(self) -> &'a mut crate::W<REG> {
self.variant(ASX_D::_7)
}
#[doc = "8 samples"]
#[inline(always)]
pub fn _8(self) -> &'a mut crate::W<REG> {
self.variant(ASX_D::_8)
}
}
#[doc = "Auto sequencer enabled\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ASX_EN {
#[doc = "0: auto sequencer disabled"]
Disabled = 0,
#[doc = "1: auto sequencer enabled"]
Enabled = 1,
}
impl From<ASX_EN> for bool {
#[inline(always)]
fn from(variant: ASX_EN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ASxEN` reader - Auto sequencer enabled"]
pub type ASX_EN_R = crate::BitReader<ASX_EN>;
impl ASX_EN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ASX_EN {
match self.bits {
false => ASX_EN::Disabled,
true => ASX_EN::Enabled,
}
}
#[doc = "auto sequencer disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == ASX_EN::Disabled
}
#[doc = "auto sequencer enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == ASX_EN::Enabled
}
}
#[doc = "Field `ASxEN` writer - Auto sequencer enabled"]
pub type ASX_EN_W<'a, REG> = crate::BitWriter<'a, REG, ASX_EN>;
impl<'a, REG> ASX_EN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "auto sequencer disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(ASX_EN::Disabled)
}
#[doc = "auto sequencer enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(ASX_EN::Enabled)
}
}
#[doc = "Auto sequencer busy\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ASX_BUSY {
#[doc = "0: auto sequencer not active"]
NotBusy = 0,
#[doc = "1: auto sequencer sampling active"]
Busy = 1,
}
impl From<ASX_BUSY> for bool {
#[inline(always)]
fn from(variant: ASX_BUSY) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ASxBUSY` reader - Auto sequencer busy"]
pub type ASX_BUSY_R = crate::BitReader<ASX_BUSY>;
impl ASX_BUSY_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ASX_BUSY {
match self.bits {
false => ASX_BUSY::NotBusy,
true => ASX_BUSY::Busy,
}
}
#[doc = "auto sequencer not active"]
#[inline(always)]
pub fn is_not_busy(&self) -> bool {
*self == ASX_BUSY::NotBusy
}
#[doc = "auto sequencer sampling active"]
#[inline(always)]
pub fn is_busy(&self) -> bool {
*self == ASX_BUSY::Busy
}
}
#[doc = "Field `ASxBUSY` writer - Auto sequencer busy"]
pub type ASX_BUSY_W<'a, REG> = crate::BitWriter<'a, REG, ASX_BUSY>;
impl<'a, REG> ASX_BUSY_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "auto sequencer not active"]
#[inline(always)]
pub fn not_busy(self) -> &'a mut crate::W<REG> {
self.variant(ASX_BUSY::NotBusy)
}
#[doc = "auto sequencer sampling active"]
#[inline(always)]
pub fn busy(self) -> &'a mut crate::W<REG> {
self.variant(ASX_BUSY::Busy)
}
}
impl R {
#[doc = "Bits 0:3 - Auto sequencer PWM trigger source"]
#[inline(always)]
pub fn asax_trpwm(&self) -> ASAX_TRPWM_R {
ASAX_TRPWM_R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:5 - Auto sequencer timer trigger source"]
#[inline(always)]
pub fn asax_trtmr(&self) -> ASAX_TRTMR_R {
ASAX_TRTMR_R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bit 6 - Auto sequencer trigger source ASxCTL.ASxTR edge"]
#[inline(always)]
pub fn asx_tre(&self) -> ASX_TRE_R {
ASX_TRE_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Auto sequencer trigger source"]
#[inline(always)]
pub fn asx_tr(&self) -> ASX_TR_R {
ASX_TR_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:10 - Auto sequencer sampling depth"]
#[inline(always)]
pub fn asx_d(&self) -> ASX_D_R {
ASX_D_R::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bit 11 - Auto sequencer enabled"]
#[inline(always)]
pub fn asx_en(&self) -> ASX_EN_R {
ASX_EN_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Auto sequencer busy"]
#[inline(always)]
pub fn asx_busy(&self) -> ASX_BUSY_R {
ASX_BUSY_R::new(((self.bits >> 12) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("AS0CTL")
.field("asax_trpwm", &self.asax_trpwm())
.field("asax_trtmr", &self.asax_trtmr())
.field("asx_tre", &self.asx_tre())
.field("asx_tr", &self.asx_tr())
.field("asx_d", &self.asx_d())
.field("asx_en", &self.asx_en())
.field("asx_busy", &self.asx_busy())
.finish()
}
}
impl W {
#[doc = "Bits 0:3 - Auto sequencer PWM trigger source"]
#[inline(always)]
pub fn asax_trpwm(&mut self) -> ASAX_TRPWM_W<AS0CTLrs> {
ASAX_TRPWM_W::new(self, 0)
}
#[doc = "Bits 4:5 - Auto sequencer timer trigger source"]
#[inline(always)]
pub fn asax_trtmr(&mut self) -> ASAX_TRTMR_W<AS0CTLrs> {
ASAX_TRTMR_W::new(self, 4)
}
#[doc = "Bit 6 - Auto sequencer trigger source ASxCTL.ASxTR edge"]
#[inline(always)]
pub fn asx_tre(&mut self) -> ASX_TRE_W<AS0CTLrs> {
ASX_TRE_W::new(self, 6)
}
#[doc = "Bit 7 - Auto sequencer trigger source"]
#[inline(always)]
pub fn asx_tr(&mut self) -> ASX_TR_W<AS0CTLrs> {
ASX_TR_W::new(self, 7)
}
#[doc = "Bits 8:10 - Auto sequencer sampling depth"]
#[inline(always)]
pub fn asx_d(&mut self) -> ASX_D_W<AS0CTLrs> {
ASX_D_W::new(self, 8)
}
#[doc = "Bit 11 - Auto sequencer enabled"]
#[inline(always)]
pub fn asx_en(&mut self) -> ASX_EN_W<AS0CTLrs> {
ASX_EN_W::new(self, 11)
}
#[doc = "Bit 12 - Auto sequencer busy"]
#[inline(always)]
pub fn asx_busy(&mut self) -> ASX_BUSY_W<AS0CTLrs> {
ASX_BUSY_W::new(self, 12)
}
}
#[doc = "Auto sequencer 0 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS0CTLrs;
impl crate::RegisterSpec for AS0CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as0ctl::R`](R) reader structure"]
impl crate::Readable for AS0CTLrs {}
#[doc = "`write(|w| ..)` method takes [`as0ctl::W`](W) writer structure"]
impl crate::Writable for AS0CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS0CTL to value 0"]
impl crate::Resettable for AS0CTLrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AS0S0 (rw) register accessor: Auto sequencer 0 sample 0 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0s0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0s0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as0s0`]
module"]
pub type AS0S0 = crate::Reg<as0s0::AS0S0rs>;
#[doc = "Auto sequencer 0 sample 0 control register"]
pub mod as0s0 {
#[doc = "Register `AS0S0` reader"]
pub type R = crate::R<AS0S0rs>;
#[doc = "Register `AS0S0` writer"]
pub type W = crate::W<AS0S0rs>;
#[doc = "Field `EMUXD` reader - EMUXD"]
pub type EMUXD_R = crate::FieldReader;
#[doc = "Field `EMUXD` writer - EMUXD"]
pub type EMUXD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "EMUX transmission start\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum EMUXS {
#[doc = "0: Do not send data"]
None = 0,
#[doc = "1: Send EMUXD data at beginning of this sample sequence"]
Before = 1,
#[doc = "2: Send EMUXD data after S/H of ADC"]
End = 2,
}
impl From<EMUXS> for u8 {
#[inline(always)]
fn from(variant: EMUXS) -> Self {
variant as _
}
}
impl crate::FieldSpec for EMUXS {
type Ux = u8;
}
impl crate::IsEnum for EMUXS {}
#[doc = "Field `EMUXS` reader - EMUX transmission start"]
pub type EMUXS_R = crate::FieldReader<EMUXS>;
impl EMUXS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<EMUXS> {
match self.bits {
0 => Some(EMUXS::None),
1 => Some(EMUXS::Before),
2 => Some(EMUXS::End),
_ => None,
}
}
#[doc = "Do not send data"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == EMUXS::None
}
#[doc = "Send EMUXD data at beginning of this sample sequence"]
#[inline(always)]
pub fn is_before(&self) -> bool {
*self == EMUXS::Before
}
#[doc = "Send EMUXD data after S/H of ADC"]
#[inline(always)]
pub fn is_end(&self) -> bool {
*self == EMUXS::End
}
}
#[doc = "Field `EMUXS` writer - EMUX transmission start"]
pub type EMUXS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, EMUXS>;
impl<'a, REG> EMUXS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Do not send data"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(EMUXS::None)
}
#[doc = "Send EMUXD data at beginning of this sample sequence"]
#[inline(always)]
pub fn before(self) -> &'a mut crate::W<REG> {
self.variant(EMUXS::Before)
}
#[doc = "Send EMUXD data after S/H of ADC"]
#[inline(always)]
pub fn end(self) -> &'a mut crate::W<REG> {
self.variant(EMUXS::End)
}
}
#[doc = "Delay between start of sample sequence and start of ADC conversion in input clocks\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum DELAY {
#[doc = "0: 0 ADC input clocks"]
_0 = 0,
#[doc = "1: 4 ADC input clocks"]
_4 = 1,
#[doc = "2: 8 ADC input clocks"]
_8 = 2,
#[doc = "3: 16 ADC input clocks"]
_16 = 3,
}
impl From<DELAY> for u8 {
#[inline(always)]
fn from(variant: DELAY) -> Self {
variant as _
}
}
impl crate::FieldSpec for DELAY {
type Ux = u8;
}
impl crate::IsEnum for DELAY {}
#[doc = "Field `DELAY` reader - Delay between start of sample sequence and start of ADC conversion in input clocks"]
pub type DELAY_R = crate::FieldReader<DELAY>;
impl DELAY_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> DELAY {
match self.bits {
0 => DELAY::_0,
1 => DELAY::_4,
2 => DELAY::_8,
3 => DELAY::_16,
_ => unreachable!(),
}
}
#[doc = "0 ADC input clocks"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == DELAY::_0
}
#[doc = "4 ADC input clocks"]
#[inline(always)]
pub fn is_4(&self) -> bool {
*self == DELAY::_4
}
#[doc = "8 ADC input clocks"]
#[inline(always)]
pub fn is_8(&self) -> bool {
*self == DELAY::_8
}
#[doc = "16 ADC input clocks"]
#[inline(always)]
pub fn is_16(&self) -> bool {
*self == DELAY::_16
}
}
#[doc = "Field `DELAY` writer - Delay between start of sample sequence and start of ADC conversion in input clocks"]
pub type DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DELAY, crate::Safe>;
impl<'a, REG> DELAY_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "0 ADC input clocks"]
#[inline(always)]
pub fn _0(self) -> &'a mut crate::W<REG> {
self.variant(DELAY::_0)
}
#[doc = "4 ADC input clocks"]
#[inline(always)]
pub fn _4(self) -> &'a mut crate::W<REG> {
self.variant(DELAY::_4)
}
#[doc = "8 ADC input clocks"]
#[inline(always)]
pub fn _8(self) -> &'a mut crate::W<REG> {
self.variant(DELAY::_8)
}
#[doc = "16 ADC input clocks"]
#[inline(always)]
pub fn _16(self) -> &'a mut crate::W<REG> {
self.variant(DELAY::_16)
}
}
#[doc = "ADC MUX input select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum ADCMUX {
#[doc = "0: EMUX"]
Emux = 0,
#[doc = "2: AD2"]
Ad2 = 2,
#[doc = "3: AD3"]
Ad3 = 3,
#[doc = "4: AD4"]
Ad4 = 4,
#[doc = "5: AD5"]
Ad5 = 5,
#[doc = "7: VSSA"]
Vssa = 7,
}
impl From<ADCMUX> for u8 {
#[inline(always)]
fn from(variant: ADCMUX) -> Self {
variant as _
}
}
impl crate::FieldSpec for ADCMUX {
type Ux = u8;
}
impl crate::IsEnum for ADCMUX {}
#[doc = "Field `ADCMUX` reader - ADC MUX input select"]
pub type ADCMUX_R = crate::FieldReader<ADCMUX>;
impl ADCMUX_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<ADCMUX> {
match self.bits {
0 => Some(ADCMUX::Emux),
2 => Some(ADCMUX::Ad2),
3 => Some(ADCMUX::Ad3),
4 => Some(ADCMUX::Ad4),
5 => Some(ADCMUX::Ad5),
7 => Some(ADCMUX::Vssa),
_ => None,
}
}
#[doc = "EMUX"]
#[inline(always)]
pub fn is_emux(&self) -> bool {
*self == ADCMUX::Emux
}
#[doc = "AD2"]
#[inline(always)]
pub fn is_ad2(&self) -> bool {
*self == ADCMUX::Ad2
}
#[doc = "AD3"]
#[inline(always)]
pub fn is_ad3(&self) -> bool {
*self == ADCMUX::Ad3
}
#[doc = "AD4"]
#[inline(always)]
pub fn is_ad4(&self) -> bool {
*self == ADCMUX::Ad4
}
#[doc = "AD5"]
#[inline(always)]
pub fn is_ad5(&self) -> bool {
*self == ADCMUX::Ad5
}
#[doc = "VSSA"]
#[inline(always)]
pub fn is_vssa(&self) -> bool {
*self == ADCMUX::Vssa
}
}
#[doc = "Field `ADCMUX` writer - ADC MUX input select"]
pub type ADCMUX_W<'a, REG> = crate::FieldWriter<'a, REG, 3, ADCMUX>;
impl<'a, REG> ADCMUX_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "EMUX"]
#[inline(always)]
pub fn emux(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Emux)
}
#[doc = "AD2"]
#[inline(always)]
pub fn ad2(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Ad2)
}
#[doc = "AD3"]
#[inline(always)]
pub fn ad3(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Ad3)
}
#[doc = "AD4"]
#[inline(always)]
pub fn ad4(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Ad4)
}
#[doc = "AD5"]
#[inline(always)]
pub fn ad5(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Ad5)
}
#[doc = "VSSA"]
#[inline(always)]
pub fn vssa(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Vssa)
}
}
impl R {
#[doc = "Bits 0:7 - EMUXD"]
#[inline(always)]
pub fn emuxd(&self) -> EMUXD_R {
EMUXD_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:9 - EMUX transmission start"]
#[inline(always)]
pub fn emuxs(&self) -> EMUXS_R {
EMUXS_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - Delay between start of sample sequence and start of ADC conversion in input clocks"]
#[inline(always)]
pub fn delay(&self) -> DELAY_R {
DELAY_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:14 - ADC MUX input select"]
#[inline(always)]
pub fn adcmux(&self) -> ADCMUX_R {
ADCMUX_R::new(((self.bits >> 12) & 7) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("AS0S0")
.field("emuxd", &self.emuxd())
.field("emuxs", &self.emuxs())
.field("delay", &self.delay())
.field("adcmux", &self.adcmux())
.finish()
}
}
impl W {
#[doc = "Bits 0:7 - EMUXD"]
#[inline(always)]
pub fn emuxd(&mut self) -> EMUXD_W<AS0S0rs> {
EMUXD_W::new(self, 0)
}
#[doc = "Bits 8:9 - EMUX transmission start"]
#[inline(always)]
pub fn emuxs(&mut self) -> EMUXS_W<AS0S0rs> {
EMUXS_W::new(self, 8)
}
#[doc = "Bits 10:11 - Delay between start of sample sequence and start of ADC conversion in input clocks"]
#[inline(always)]
pub fn delay(&mut self) -> DELAY_W<AS0S0rs> {
DELAY_W::new(self, 10)
}
#[doc = "Bits 12:14 - ADC MUX input select"]
#[inline(always)]
pub fn adcmux(&mut self) -> ADCMUX_W<AS0S0rs> {
ADCMUX_W::new(self, 12)
}
}
#[doc = "Auto sequencer 0 sample 0 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0s0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0s0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS0S0rs;
impl crate::RegisterSpec for AS0S0rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as0s0::R`](R) reader structure"]
impl crate::Readable for AS0S0rs {}
#[doc = "`write(|w| ..)` method takes [`as0s0::W`](W) writer structure"]
impl crate::Writable for AS0S0rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS0S0 to value 0"]
impl crate::Resettable for AS0S0rs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AS0R0 (rw) register accessor: Auto sequencer 0 sample 0 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0r0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0r0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as0r0`]
module"]
pub type AS0R0 = crate::Reg<as0r0::AS0R0rs>;
#[doc = "Auto sequencer 0 sample 0 result register"]
pub mod as0r0 {
#[doc = "Register `AS0R0` reader"]
pub type R = crate::R<AS0R0rs>;
#[doc = "Register `AS0R0` writer"]
pub type W = crate::W<AS0R0rs>;
#[doc = "Field `ADCRESULT` reader - ADC conversion result"]
pub type ADCRESULT_R = crate::FieldReader<u16>;
#[doc = "Field `ADCRESULT` writer - ADC conversion result"]
pub type ADCRESULT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
impl R {
#[doc = "Bits 0:9 - ADC conversion result"]
#[inline(always)]
pub fn adcresult(&self) -> ADCRESULT_R {
ADCRESULT_R::new((self.bits & 0x03ff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("AS0R0")
.field("adcresult", &self.adcresult())
.finish()
}
}
impl W {
#[doc = "Bits 0:9 - ADC conversion result"]
#[inline(always)]
pub fn adcresult(&mut self) -> ADCRESULT_W<AS0R0rs> {
ADCRESULT_W::new(self, 0)
}
}
#[doc = "Auto sequencer 0 sample 0 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0r0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0r0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS0R0rs;
impl crate::RegisterSpec for AS0R0rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as0r0::R`](R) reader structure"]
impl crate::Readable for AS0R0rs {}
#[doc = "`write(|w| ..)` method takes [`as0r0::W`](W) writer structure"]
impl crate::Writable for AS0R0rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS0R0 to value 0"]
impl crate::Resettable for AS0R0rs {
const RESET_VALUE: u32 = 0;
}
}
pub use as0s0 as as0s1;
pub use AS0S0 as AS0S1;
#[doc = "AS0R1 (rw) register accessor: Auto sequencer 0 sample 1 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0r1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0r1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as0r1`]
module"]
pub type AS0R1 = crate::Reg<as0r1::AS0R1rs>;
#[doc = "Auto sequencer 0 sample 1 result register"]
pub mod as0r1 {
#[doc = "Register `AS0R1` reader"]
pub type R = crate::R<AS0R1rs>;
#[doc = "Register `AS0R1` writer"]
pub type W = crate::W<AS0R1rs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Auto sequencer 0 sample 1 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0r1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0r1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS0R1rs;
impl crate::RegisterSpec for AS0R1rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as0r1::R`](R) reader structure"]
impl crate::Readable for AS0R1rs {}
#[doc = "`write(|w| ..)` method takes [`as0r1::W`](W) writer structure"]
impl crate::Writable for AS0R1rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS0R1 to value 0"]
impl crate::Resettable for AS0R1rs {
const RESET_VALUE: u32 = 0;
}
}
pub use as0s0 as as0s2;
pub use AS0S0 as AS0S2;
#[doc = "AS0R2 (rw) register accessor: Auto sequencer 0 sample 2 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0r2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0r2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as0r2`]
module"]
pub type AS0R2 = crate::Reg<as0r2::AS0R2rs>;
#[doc = "Auto sequencer 0 sample 2 result register"]
pub mod as0r2 {
#[doc = "Register `AS0R2` reader"]
pub type R = crate::R<AS0R2rs>;
#[doc = "Register `AS0R2` writer"]
pub type W = crate::W<AS0R2rs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Auto sequencer 0 sample 2 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0r2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0r2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS0R2rs;
impl crate::RegisterSpec for AS0R2rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as0r2::R`](R) reader structure"]
impl crate::Readable for AS0R2rs {}
#[doc = "`write(|w| ..)` method takes [`as0r2::W`](W) writer structure"]
impl crate::Writable for AS0R2rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS0R2 to value 0"]
impl crate::Resettable for AS0R2rs {
const RESET_VALUE: u32 = 0;
}
}
pub use as0s0 as as0s3;
pub use AS0S0 as AS0S3;
#[doc = "AS0R3 (rw) register accessor: Auto sequencer 0 sample 3 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0r3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0r3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as0r3`]
module"]
pub type AS0R3 = crate::Reg<as0r3::AS0R3rs>;
#[doc = "Auto sequencer 0 sample 3 result register"]
pub mod as0r3 {
#[doc = "Register `AS0R3` reader"]
pub type R = crate::R<AS0R3rs>;
#[doc = "Register `AS0R3` writer"]
pub type W = crate::W<AS0R3rs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Auto sequencer 0 sample 3 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0r3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0r3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS0R3rs;
impl crate::RegisterSpec for AS0R3rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as0r3::R`](R) reader structure"]
impl crate::Readable for AS0R3rs {}
#[doc = "`write(|w| ..)` method takes [`as0r3::W`](W) writer structure"]
impl crate::Writable for AS0R3rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS0R3 to value 0"]
impl crate::Resettable for AS0R3rs {
const RESET_VALUE: u32 = 0;
}
}
pub use as0s0 as as0s4;
pub use AS0S0 as AS0S4;
#[doc = "AS0R4 (rw) register accessor: Auto sequencer 0 sample 4 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0r4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0r4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as0r4`]
module"]
pub type AS0R4 = crate::Reg<as0r4::AS0R4rs>;
#[doc = "Auto sequencer 0 sample 4 result register"]
pub mod as0r4 {
#[doc = "Register `AS0R4` reader"]
pub type R = crate::R<AS0R4rs>;
#[doc = "Register `AS0R4` writer"]
pub type W = crate::W<AS0R4rs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Auto sequencer 0 sample 4 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0r4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0r4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS0R4rs;
impl crate::RegisterSpec for AS0R4rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as0r4::R`](R) reader structure"]
impl crate::Readable for AS0R4rs {}
#[doc = "`write(|w| ..)` method takes [`as0r4::W`](W) writer structure"]
impl crate::Writable for AS0R4rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS0R4 to value 0"]
impl crate::Resettable for AS0R4rs {
const RESET_VALUE: u32 = 0;
}
}
pub use as0s0 as as0s5;
pub use AS0S0 as AS0S5;
#[doc = "AS0R5 (rw) register accessor: Auto sequencer 0 sample 5 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0r5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0r5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as0r5`]
module"]
pub type AS0R5 = crate::Reg<as0r5::AS0R5rs>;
#[doc = "Auto sequencer 0 sample 5 result register"]
pub mod as0r5 {
#[doc = "Register `AS0R5` reader"]
pub type R = crate::R<AS0R5rs>;
#[doc = "Register `AS0R5` writer"]
pub type W = crate::W<AS0R5rs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Auto sequencer 0 sample 5 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0r5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0r5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS0R5rs;
impl crate::RegisterSpec for AS0R5rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as0r5::R`](R) reader structure"]
impl crate::Readable for AS0R5rs {}
#[doc = "`write(|w| ..)` method takes [`as0r5::W`](W) writer structure"]
impl crate::Writable for AS0R5rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS0R5 to value 0"]
impl crate::Resettable for AS0R5rs {
const RESET_VALUE: u32 = 0;
}
}
pub use as0s0 as as0s6;
pub use AS0S0 as AS0S6;
#[doc = "AS0R6 (rw) register accessor: Auto sequencer 0 sample 6 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0r6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0r6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as0r6`]
module"]
pub type AS0R6 = crate::Reg<as0r6::AS0R6rs>;
#[doc = "Auto sequencer 0 sample 6 result register"]
pub mod as0r6 {
#[doc = "Register `AS0R6` reader"]
pub type R = crate::R<AS0R6rs>;
#[doc = "Register `AS0R6` writer"]
pub type W = crate::W<AS0R6rs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Auto sequencer 0 sample 6 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0r6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0r6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS0R6rs;
impl crate::RegisterSpec for AS0R6rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as0r6::R`](R) reader structure"]
impl crate::Readable for AS0R6rs {}
#[doc = "`write(|w| ..)` method takes [`as0r6::W`](W) writer structure"]
impl crate::Writable for AS0R6rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS0R6 to value 0"]
impl crate::Resettable for AS0R6rs {
const RESET_VALUE: u32 = 0;
}
}
pub use as0s0 as as0s7;
pub use AS0S0 as AS0S7;
#[doc = "AS0R7 (rw) register accessor: Auto sequencer 0 sample 7 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0r7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0r7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as0r7`]
module"]
pub type AS0R7 = crate::Reg<as0r7::AS0R7rs>;
#[doc = "Auto sequencer 0 sample 7 result register"]
pub mod as0r7 {
#[doc = "Register `AS0R7` reader"]
pub type R = crate::R<AS0R7rs>;
#[doc = "Register `AS0R7` writer"]
pub type W = crate::W<AS0R7rs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Auto sequencer 0 sample 7 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as0r7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as0r7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS0R7rs;
impl crate::RegisterSpec for AS0R7rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as0r7::R`](R) reader structure"]
impl crate::Readable for AS0R7rs {}
#[doc = "`write(|w| ..)` method takes [`as0r7::W`](W) writer structure"]
impl crate::Writable for AS0R7rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS0R7 to value 0"]
impl crate::Resettable for AS0R7rs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AS1CTL (rw) register accessor: Auto sequencer 1 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as1ctl`]
module"]
pub type AS1CTL = crate::Reg<as1ctl::AS1CTLrs>;
#[doc = "Auto sequencer 1 control register"]
pub mod as1ctl {
#[doc = "Register `AS1CTL` reader"]
pub type R = crate::R<AS1CTLrs>;
#[doc = "Register `AS1CTL` writer"]
pub type W = crate::W<AS1CTLrs>;
#[doc = "Auto sequencer PWM trigger source\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum ASAX_TRPWM {
#[doc = "0: PWMA0"]
Pwma0 = 0,
#[doc = "1: PWMA1"]
Pwma1 = 1,
#[doc = "2: PWMA2"]
Pwma2 = 2,
#[doc = "3: PWMA3"]
Pwma3 = 3,
#[doc = "4: PWMA4"]
Pwma4 = 4,
#[doc = "5: PWMA5"]
Pwma5 = 5,
#[doc = "6: PWMA6"]
Pwma6 = 6,
#[doc = "7: PWMA7"]
Pwma7 = 7,
#[doc = "8: PWMB0"]
Pwmb0 = 8,
#[doc = "9: PWMB1"]
Pwmb1 = 9,
#[doc = "10: PWMC0"]
Pwmc0 = 10,
#[doc = "11: PWMC1"]
Pwmc1 = 11,
#[doc = "12: PWMD0"]
Pwmd0 = 12,
#[doc = "13: PWMD1"]
Pwmd1 = 13,
}
impl From<ASAX_TRPWM> for u8 {
#[inline(always)]
fn from(variant: ASAX_TRPWM) -> Self {
variant as _
}
}
impl crate::FieldSpec for ASAX_TRPWM {
type Ux = u8;
}
impl crate::IsEnum for ASAX_TRPWM {}
#[doc = "Field `ASAxTRPWM` reader - Auto sequencer PWM trigger source"]
pub type ASAX_TRPWM_R = crate::FieldReader<ASAX_TRPWM>;
impl ASAX_TRPWM_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<ASAX_TRPWM> {
match self.bits {
0 => Some(ASAX_TRPWM::Pwma0),
1 => Some(ASAX_TRPWM::Pwma1),
2 => Some(ASAX_TRPWM::Pwma2),
3 => Some(ASAX_TRPWM::Pwma3),
4 => Some(ASAX_TRPWM::Pwma4),
5 => Some(ASAX_TRPWM::Pwma5),
6 => Some(ASAX_TRPWM::Pwma6),
7 => Some(ASAX_TRPWM::Pwma7),
8 => Some(ASAX_TRPWM::Pwmb0),
9 => Some(ASAX_TRPWM::Pwmb1),
10 => Some(ASAX_TRPWM::Pwmc0),
11 => Some(ASAX_TRPWM::Pwmc1),
12 => Some(ASAX_TRPWM::Pwmd0),
13 => Some(ASAX_TRPWM::Pwmd1),
_ => None,
}
}
#[doc = "PWMA0"]
#[inline(always)]
pub fn is_pwma0(&self) -> bool {
*self == ASAX_TRPWM::Pwma0
}
#[doc = "PWMA1"]
#[inline(always)]
pub fn is_pwma1(&self) -> bool {
*self == ASAX_TRPWM::Pwma1
}
#[doc = "PWMA2"]
#[inline(always)]
pub fn is_pwma2(&self) -> bool {
*self == ASAX_TRPWM::Pwma2
}
#[doc = "PWMA3"]
#[inline(always)]
pub fn is_pwma3(&self) -> bool {
*self == ASAX_TRPWM::Pwma3
}
#[doc = "PWMA4"]
#[inline(always)]
pub fn is_pwma4(&self) -> bool {
*self == ASAX_TRPWM::Pwma4
}
#[doc = "PWMA5"]
#[inline(always)]
pub fn is_pwma5(&self) -> bool {
*self == ASAX_TRPWM::Pwma5
}
#[doc = "PWMA6"]
#[inline(always)]
pub fn is_pwma6(&self) -> bool {
*self == ASAX_TRPWM::Pwma6
}
#[doc = "PWMA7"]
#[inline(always)]
pub fn is_pwma7(&self) -> bool {
*self == ASAX_TRPWM::Pwma7
}
#[doc = "PWMB0"]
#[inline(always)]
pub fn is_pwmb0(&self) -> bool {
*self == ASAX_TRPWM::Pwmb0
}
#[doc = "PWMB1"]
#[inline(always)]
pub fn is_pwmb1(&self) -> bool {
*self == ASAX_TRPWM::Pwmb1
}
#[doc = "PWMC0"]
#[inline(always)]
pub fn is_pwmc0(&self) -> bool {
*self == ASAX_TRPWM::Pwmc0
}
#[doc = "PWMC1"]
#[inline(always)]
pub fn is_pwmc1(&self) -> bool {
*self == ASAX_TRPWM::Pwmc1
}
#[doc = "PWMD0"]
#[inline(always)]
pub fn is_pwmd0(&self) -> bool {
*self == ASAX_TRPWM::Pwmd0
}
#[doc = "PWMD1"]
#[inline(always)]
pub fn is_pwmd1(&self) -> bool {
*self == ASAX_TRPWM::Pwmd1
}
}
#[doc = "Field `ASAxTRPWM` writer - Auto sequencer PWM trigger source"]
pub type ASAX_TRPWM_W<'a, REG> = crate::FieldWriter<'a, REG, 4, ASAX_TRPWM>;
impl<'a, REG> ASAX_TRPWM_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWMA0"]
#[inline(always)]
pub fn pwma0(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwma0)
}
#[doc = "PWMA1"]
#[inline(always)]
pub fn pwma1(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwma1)
}
#[doc = "PWMA2"]
#[inline(always)]
pub fn pwma2(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwma2)
}
#[doc = "PWMA3"]
#[inline(always)]
pub fn pwma3(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwma3)
}
#[doc = "PWMA4"]
#[inline(always)]
pub fn pwma4(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwma4)
}
#[doc = "PWMA5"]
#[inline(always)]
pub fn pwma5(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwma5)
}
#[doc = "PWMA6"]
#[inline(always)]
pub fn pwma6(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwma6)
}
#[doc = "PWMA7"]
#[inline(always)]
pub fn pwma7(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwma7)
}
#[doc = "PWMB0"]
#[inline(always)]
pub fn pwmb0(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwmb0)
}
#[doc = "PWMB1"]
#[inline(always)]
pub fn pwmb1(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwmb1)
}
#[doc = "PWMC0"]
#[inline(always)]
pub fn pwmc0(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwmc0)
}
#[doc = "PWMC1"]
#[inline(always)]
pub fn pwmc1(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwmc1)
}
#[doc = "PWMD0"]
#[inline(always)]
pub fn pwmd0(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwmd0)
}
#[doc = "PWMD1"]
#[inline(always)]
pub fn pwmd1(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRPWM::Pwmd1)
}
}
#[doc = "Auto sequencer timer trigger source\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum ASAX_TRTMR {
#[doc = "0: Timer A"]
TimerA = 0,
#[doc = "1: Timer B"]
TimerB = 1,
#[doc = "2: Timer C"]
TimerC = 2,
#[doc = "3: Timer D"]
TimerD = 3,
}
impl From<ASAX_TRTMR> for u8 {
#[inline(always)]
fn from(variant: ASAX_TRTMR) -> Self {
variant as _
}
}
impl crate::FieldSpec for ASAX_TRTMR {
type Ux = u8;
}
impl crate::IsEnum for ASAX_TRTMR {}
#[doc = "Field `ASAxTRTMR` reader - Auto sequencer timer trigger source"]
pub type ASAX_TRTMR_R = crate::FieldReader<ASAX_TRTMR>;
impl ASAX_TRTMR_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ASAX_TRTMR {
match self.bits {
0 => ASAX_TRTMR::TimerA,
1 => ASAX_TRTMR::TimerB,
2 => ASAX_TRTMR::TimerC,
3 => ASAX_TRTMR::TimerD,
_ => unreachable!(),
}
}
#[doc = "Timer A"]
#[inline(always)]
pub fn is_timer_a(&self) -> bool {
*self == ASAX_TRTMR::TimerA
}
#[doc = "Timer B"]
#[inline(always)]
pub fn is_timer_b(&self) -> bool {
*self == ASAX_TRTMR::TimerB
}
#[doc = "Timer C"]
#[inline(always)]
pub fn is_timer_c(&self) -> bool {
*self == ASAX_TRTMR::TimerC
}
#[doc = "Timer D"]
#[inline(always)]
pub fn is_timer_d(&self) -> bool {
*self == ASAX_TRTMR::TimerD
}
}
#[doc = "Field `ASAxTRTMR` writer - Auto sequencer timer trigger source"]
pub type ASAX_TRTMR_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ASAX_TRTMR, crate::Safe>;
impl<'a, REG> ASAX_TRTMR_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A"]
#[inline(always)]
pub fn timer_a(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRTMR::TimerA)
}
#[doc = "Timer B"]
#[inline(always)]
pub fn timer_b(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRTMR::TimerB)
}
#[doc = "Timer C"]
#[inline(always)]
pub fn timer_c(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRTMR::TimerC)
}
#[doc = "Timer D"]
#[inline(always)]
pub fn timer_d(self) -> &'a mut crate::W<REG> {
self.variant(ASAX_TRTMR::TimerD)
}
}
#[doc = "Auto sequencer trigger source ASxCTL.ASxTR edge\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ASX_TRE {
#[doc = "0: High to low edge"]
HighToLow = 0,
#[doc = "1: Low to high edge"]
LowToHigh = 1,
}
impl From<ASX_TRE> for bool {
#[inline(always)]
fn from(variant: ASX_TRE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ASxTRE` reader - Auto sequencer trigger source ASxCTL.ASxTR edge"]
pub type ASX_TRE_R = crate::BitReader<ASX_TRE>;
impl ASX_TRE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ASX_TRE {
match self.bits {
false => ASX_TRE::HighToLow,
true => ASX_TRE::LowToHigh,
}
}
#[doc = "High to low edge"]
#[inline(always)]
pub fn is_high_to_low(&self) -> bool {
*self == ASX_TRE::HighToLow
}
#[doc = "Low to high edge"]
#[inline(always)]
pub fn is_low_to_high(&self) -> bool {
*self == ASX_TRE::LowToHigh
}
}
#[doc = "Field `ASxTRE` writer - Auto sequencer trigger source ASxCTL.ASxTR edge"]
pub type ASX_TRE_W<'a, REG> = crate::BitWriter<'a, REG, ASX_TRE>;
impl<'a, REG> ASX_TRE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "High to low edge"]
#[inline(always)]
pub fn high_to_low(self) -> &'a mut crate::W<REG> {
self.variant(ASX_TRE::HighToLow)
}
#[doc = "Low to high edge"]
#[inline(always)]
pub fn low_to_high(self) -> &'a mut crate::W<REG> {
self.variant(ASX_TRE::LowToHigh)
}
}
#[doc = "Auto sequencer trigger source\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ASX_TR {
#[doc = "0: PWM, as defined by ASxCTL.ASxTRPWM"]
Pwm = 0,
#[doc = "1: Timer, as defined by ASxCTL.ASxTRTMR"]
Timer = 1,
}
impl From<ASX_TR> for bool {
#[inline(always)]
fn from(variant: ASX_TR) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ASxTR` reader - Auto sequencer trigger source"]
pub type ASX_TR_R = crate::BitReader<ASX_TR>;
impl ASX_TR_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ASX_TR {
match self.bits {
false => ASX_TR::Pwm,
true => ASX_TR::Timer,
}
}
#[doc = "PWM, as defined by ASxCTL.ASxTRPWM"]
#[inline(always)]
pub fn is_pwm(&self) -> bool {
*self == ASX_TR::Pwm
}
#[doc = "Timer, as defined by ASxCTL.ASxTRTMR"]
#[inline(always)]
pub fn is_timer(&self) -> bool {
*self == ASX_TR::Timer
}
}
#[doc = "Field `ASxTR` writer - Auto sequencer trigger source"]
pub type ASX_TR_W<'a, REG> = crate::BitWriter<'a, REG, ASX_TR>;
impl<'a, REG> ASX_TR_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "PWM, as defined by ASxCTL.ASxTRPWM"]
#[inline(always)]
pub fn pwm(self) -> &'a mut crate::W<REG> {
self.variant(ASX_TR::Pwm)
}
#[doc = "Timer, as defined by ASxCTL.ASxTRTMR"]
#[inline(always)]
pub fn timer(self) -> &'a mut crate::W<REG> {
self.variant(ASX_TR::Timer)
}
}
#[doc = "Auto sequencer sampling depth\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum ASX_D {
#[doc = "0: 1 sample"]
_1 = 0,
#[doc = "1: 2 samples"]
_2 = 1,
#[doc = "2: 3 samples"]
_3 = 2,
#[doc = "3: 4 samples"]
_4 = 3,
#[doc = "4: 5 samples"]
_5 = 4,
#[doc = "5: 6 samples"]
_6 = 5,
#[doc = "6: 7 samples"]
_7 = 6,
#[doc = "7: 8 samples"]
_8 = 7,
}
impl From<ASX_D> for u8 {
#[inline(always)]
fn from(variant: ASX_D) -> Self {
variant as _
}
}
impl crate::FieldSpec for ASX_D {
type Ux = u8;
}
impl crate::IsEnum for ASX_D {}
#[doc = "Field `ASxD` reader - Auto sequencer sampling depth"]
pub type ASX_D_R = crate::FieldReader<ASX_D>;
impl ASX_D_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ASX_D {
match self.bits {
0 => ASX_D::_1,
1 => ASX_D::_2,
2 => ASX_D::_3,
3 => ASX_D::_4,
4 => ASX_D::_5,
5 => ASX_D::_6,
6 => ASX_D::_7,
7 => ASX_D::_8,
_ => unreachable!(),
}
}
#[doc = "1 sample"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == ASX_D::_1
}
#[doc = "2 samples"]
#[inline(always)]
pub fn is_2(&self) -> bool {
*self == ASX_D::_2
}
#[doc = "3 samples"]
#[inline(always)]
pub fn is_3(&self) -> bool {
*self == ASX_D::_3
}
#[doc = "4 samples"]
#[inline(always)]
pub fn is_4(&self) -> bool {
*self == ASX_D::_4
}
#[doc = "5 samples"]
#[inline(always)]
pub fn is_5(&self) -> bool {
*self == ASX_D::_5
}
#[doc = "6 samples"]
#[inline(always)]
pub fn is_6(&self) -> bool {
*self == ASX_D::_6
}
#[doc = "7 samples"]
#[inline(always)]
pub fn is_7(&self) -> bool {
*self == ASX_D::_7
}
#[doc = "8 samples"]
#[inline(always)]
pub fn is_8(&self) -> bool {
*self == ASX_D::_8
}
}
#[doc = "Field `ASxD` writer - Auto sequencer sampling depth"]
pub type ASX_D_W<'a, REG> = crate::FieldWriter<'a, REG, 3, ASX_D, crate::Safe>;
impl<'a, REG> ASX_D_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "1 sample"]
#[inline(always)]
pub fn _1(self) -> &'a mut crate::W<REG> {
self.variant(ASX_D::_1)
}
#[doc = "2 samples"]
#[inline(always)]
pub fn _2(self) -> &'a mut crate::W<REG> {
self.variant(ASX_D::_2)
}
#[doc = "3 samples"]
#[inline(always)]
pub fn _3(self) -> &'a mut crate::W<REG> {
self.variant(ASX_D::_3)
}
#[doc = "4 samples"]
#[inline(always)]
pub fn _4(self) -> &'a mut crate::W<REG> {
self.variant(ASX_D::_4)
}
#[doc = "5 samples"]
#[inline(always)]
pub fn _5(self) -> &'a mut crate::W<REG> {
self.variant(ASX_D::_5)
}
#[doc = "6 samples"]
#[inline(always)]
pub fn _6(self) -> &'a mut crate::W<REG> {
self.variant(ASX_D::_6)
}
#[doc = "7 samples"]
#[inline(always)]
pub fn _7(self) -> &'a mut crate::W<REG> {
self.variant(ASX_D::_7)
}
#[doc = "8 samples"]
#[inline(always)]
pub fn _8(self) -> &'a mut crate::W<REG> {
self.variant(ASX_D::_8)
}
}
#[doc = "Auto sequencer enabled\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ASX_EN {
#[doc = "0: auto sequencer disabled"]
Disabled = 0,
#[doc = "1: auto sequencer enabled"]
Enabled = 1,
}
impl From<ASX_EN> for bool {
#[inline(always)]
fn from(variant: ASX_EN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ASxEN` reader - Auto sequencer enabled"]
pub type ASX_EN_R = crate::BitReader<ASX_EN>;
impl ASX_EN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ASX_EN {
match self.bits {
false => ASX_EN::Disabled,
true => ASX_EN::Enabled,
}
}
#[doc = "auto sequencer disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == ASX_EN::Disabled
}
#[doc = "auto sequencer enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == ASX_EN::Enabled
}
}
#[doc = "Field `ASxEN` writer - Auto sequencer enabled"]
pub type ASX_EN_W<'a, REG> = crate::BitWriter<'a, REG, ASX_EN>;
impl<'a, REG> ASX_EN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "auto sequencer disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(ASX_EN::Disabled)
}
#[doc = "auto sequencer enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(ASX_EN::Enabled)
}
}
#[doc = "Auto sequencer busy\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ASX_BUSY {
#[doc = "0: auto sequencer not active"]
NotBusy = 0,
#[doc = "1: auto sequencer sampling active"]
Busy = 1,
}
impl From<ASX_BUSY> for bool {
#[inline(always)]
fn from(variant: ASX_BUSY) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ASxBUSY` reader - Auto sequencer busy"]
pub type ASX_BUSY_R = crate::BitReader<ASX_BUSY>;
impl ASX_BUSY_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ASX_BUSY {
match self.bits {
false => ASX_BUSY::NotBusy,
true => ASX_BUSY::Busy,
}
}
#[doc = "auto sequencer not active"]
#[inline(always)]
pub fn is_not_busy(&self) -> bool {
*self == ASX_BUSY::NotBusy
}
#[doc = "auto sequencer sampling active"]
#[inline(always)]
pub fn is_busy(&self) -> bool {
*self == ASX_BUSY::Busy
}
}
#[doc = "Field `ASxBUSY` writer - Auto sequencer busy"]
pub type ASX_BUSY_W<'a, REG> = crate::BitWriter<'a, REG, ASX_BUSY>;
impl<'a, REG> ASX_BUSY_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "auto sequencer not active"]
#[inline(always)]
pub fn not_busy(self) -> &'a mut crate::W<REG> {
self.variant(ASX_BUSY::NotBusy)
}
#[doc = "auto sequencer sampling active"]
#[inline(always)]
pub fn busy(self) -> &'a mut crate::W<REG> {
self.variant(ASX_BUSY::Busy)
}
}
impl R {
#[doc = "Bits 0:3 - Auto sequencer PWM trigger source"]
#[inline(always)]
pub fn asax_trpwm(&self) -> ASAX_TRPWM_R {
ASAX_TRPWM_R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:5 - Auto sequencer timer trigger source"]
#[inline(always)]
pub fn asax_trtmr(&self) -> ASAX_TRTMR_R {
ASAX_TRTMR_R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bit 6 - Auto sequencer trigger source ASxCTL.ASxTR edge"]
#[inline(always)]
pub fn asx_tre(&self) -> ASX_TRE_R {
ASX_TRE_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Auto sequencer trigger source"]
#[inline(always)]
pub fn asx_tr(&self) -> ASX_TR_R {
ASX_TR_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:10 - Auto sequencer sampling depth"]
#[inline(always)]
pub fn asx_d(&self) -> ASX_D_R {
ASX_D_R::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bit 11 - Auto sequencer enabled"]
#[inline(always)]
pub fn asx_en(&self) -> ASX_EN_R {
ASX_EN_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Auto sequencer busy"]
#[inline(always)]
pub fn asx_busy(&self) -> ASX_BUSY_R {
ASX_BUSY_R::new(((self.bits >> 12) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("AS1CTL")
.field("asax_trpwm", &self.asax_trpwm())
.field("asax_trtmr", &self.asax_trtmr())
.field("asx_tre", &self.asx_tre())
.field("asx_tr", &self.asx_tr())
.field("asx_d", &self.asx_d())
.field("asx_en", &self.asx_en())
.field("asx_busy", &self.asx_busy())
.finish()
}
}
impl W {
#[doc = "Bits 0:3 - Auto sequencer PWM trigger source"]
#[inline(always)]
pub fn asax_trpwm(&mut self) -> ASAX_TRPWM_W<AS1CTLrs> {
ASAX_TRPWM_W::new(self, 0)
}
#[doc = "Bits 4:5 - Auto sequencer timer trigger source"]
#[inline(always)]
pub fn asax_trtmr(&mut self) -> ASAX_TRTMR_W<AS1CTLrs> {
ASAX_TRTMR_W::new(self, 4)
}
#[doc = "Bit 6 - Auto sequencer trigger source ASxCTL.ASxTR edge"]
#[inline(always)]
pub fn asx_tre(&mut self) -> ASX_TRE_W<AS1CTLrs> {
ASX_TRE_W::new(self, 6)
}
#[doc = "Bit 7 - Auto sequencer trigger source"]
#[inline(always)]
pub fn asx_tr(&mut self) -> ASX_TR_W<AS1CTLrs> {
ASX_TR_W::new(self, 7)
}
#[doc = "Bits 8:10 - Auto sequencer sampling depth"]
#[inline(always)]
pub fn asx_d(&mut self) -> ASX_D_W<AS1CTLrs> {
ASX_D_W::new(self, 8)
}
#[doc = "Bit 11 - Auto sequencer enabled"]
#[inline(always)]
pub fn asx_en(&mut self) -> ASX_EN_W<AS1CTLrs> {
ASX_EN_W::new(self, 11)
}
#[doc = "Bit 12 - Auto sequencer busy"]
#[inline(always)]
pub fn asx_busy(&mut self) -> ASX_BUSY_W<AS1CTLrs> {
ASX_BUSY_W::new(self, 12)
}
}
#[doc = "Auto sequencer 1 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS1CTLrs;
impl crate::RegisterSpec for AS1CTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as1ctl::R`](R) reader structure"]
impl crate::Readable for AS1CTLrs {}
#[doc = "`write(|w| ..)` method takes [`as1ctl::W`](W) writer structure"]
impl crate::Writable for AS1CTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS1CTL to value 0"]
impl crate::Resettable for AS1CTLrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AS1S0 (rw) register accessor: Auto sequencer 1 sample 0 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1s0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1s0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as1s0`]
module"]
pub type AS1S0 = crate::Reg<as1s0::AS1S0rs>;
#[doc = "Auto sequencer 1 sample 0 control register"]
pub mod as1s0 {
#[doc = "Register `AS1S0` reader"]
pub type R = crate::R<AS1S0rs>;
#[doc = "Register `AS1S0` writer"]
pub type W = crate::W<AS1S0rs>;
#[doc = "Field `EMUXD` reader - EMUXD"]
pub type EMUXD_R = crate::FieldReader;
#[doc = "Field `EMUXD` writer - EMUXD"]
pub type EMUXD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "EMUX transmission start\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum EMUXS {
#[doc = "0: Do not send data"]
None = 0,
#[doc = "1: Send EMUXD data at beginning of this sample sequence"]
Before = 1,
#[doc = "2: Send EMUXD data after S/H of ADC"]
End = 2,
}
impl From<EMUXS> for u8 {
#[inline(always)]
fn from(variant: EMUXS) -> Self {
variant as _
}
}
impl crate::FieldSpec for EMUXS {
type Ux = u8;
}
impl crate::IsEnum for EMUXS {}
#[doc = "Field `EMUXS` reader - EMUX transmission start"]
pub type EMUXS_R = crate::FieldReader<EMUXS>;
impl EMUXS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<EMUXS> {
match self.bits {
0 => Some(EMUXS::None),
1 => Some(EMUXS::Before),
2 => Some(EMUXS::End),
_ => None,
}
}
#[doc = "Do not send data"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == EMUXS::None
}
#[doc = "Send EMUXD data at beginning of this sample sequence"]
#[inline(always)]
pub fn is_before(&self) -> bool {
*self == EMUXS::Before
}
#[doc = "Send EMUXD data after S/H of ADC"]
#[inline(always)]
pub fn is_end(&self) -> bool {
*self == EMUXS::End
}
}
#[doc = "Field `EMUXS` writer - EMUX transmission start"]
pub type EMUXS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, EMUXS>;
impl<'a, REG> EMUXS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Do not send data"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(EMUXS::None)
}
#[doc = "Send EMUXD data at beginning of this sample sequence"]
#[inline(always)]
pub fn before(self) -> &'a mut crate::W<REG> {
self.variant(EMUXS::Before)
}
#[doc = "Send EMUXD data after S/H of ADC"]
#[inline(always)]
pub fn end(self) -> &'a mut crate::W<REG> {
self.variant(EMUXS::End)
}
}
#[doc = "Delay between start of sample sequence and start of ADC conversion in input clocks\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum DELAY {
#[doc = "0: 0 ADC input clocks"]
_0 = 0,
#[doc = "1: 4 ADC input clocks"]
_4 = 1,
#[doc = "2: 8 ADC input clocks"]
_8 = 2,
#[doc = "3: 16 ADC input clocks"]
_16 = 3,
}
impl From<DELAY> for u8 {
#[inline(always)]
fn from(variant: DELAY) -> Self {
variant as _
}
}
impl crate::FieldSpec for DELAY {
type Ux = u8;
}
impl crate::IsEnum for DELAY {}
#[doc = "Field `DELAY` reader - Delay between start of sample sequence and start of ADC conversion in input clocks"]
pub type DELAY_R = crate::FieldReader<DELAY>;
impl DELAY_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> DELAY {
match self.bits {
0 => DELAY::_0,
1 => DELAY::_4,
2 => DELAY::_8,
3 => DELAY::_16,
_ => unreachable!(),
}
}
#[doc = "0 ADC input clocks"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == DELAY::_0
}
#[doc = "4 ADC input clocks"]
#[inline(always)]
pub fn is_4(&self) -> bool {
*self == DELAY::_4
}
#[doc = "8 ADC input clocks"]
#[inline(always)]
pub fn is_8(&self) -> bool {
*self == DELAY::_8
}
#[doc = "16 ADC input clocks"]
#[inline(always)]
pub fn is_16(&self) -> bool {
*self == DELAY::_16
}
}
#[doc = "Field `DELAY` writer - Delay between start of sample sequence and start of ADC conversion in input clocks"]
pub type DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DELAY, crate::Safe>;
impl<'a, REG> DELAY_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "0 ADC input clocks"]
#[inline(always)]
pub fn _0(self) -> &'a mut crate::W<REG> {
self.variant(DELAY::_0)
}
#[doc = "4 ADC input clocks"]
#[inline(always)]
pub fn _4(self) -> &'a mut crate::W<REG> {
self.variant(DELAY::_4)
}
#[doc = "8 ADC input clocks"]
#[inline(always)]
pub fn _8(self) -> &'a mut crate::W<REG> {
self.variant(DELAY::_8)
}
#[doc = "16 ADC input clocks"]
#[inline(always)]
pub fn _16(self) -> &'a mut crate::W<REG> {
self.variant(DELAY::_16)
}
}
#[doc = "ADC MUX input select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum ADCMUX {
#[doc = "0: EMUX"]
Emux = 0,
#[doc = "2: AD2"]
Ad2 = 2,
#[doc = "3: AD3"]
Ad3 = 3,
#[doc = "4: AD4"]
Ad4 = 4,
#[doc = "5: AD5"]
Ad5 = 5,
#[doc = "7: VSSA"]
Vssa = 7,
}
impl From<ADCMUX> for u8 {
#[inline(always)]
fn from(variant: ADCMUX) -> Self {
variant as _
}
}
impl crate::FieldSpec for ADCMUX {
type Ux = u8;
}
impl crate::IsEnum for ADCMUX {}
#[doc = "Field `ADCMUX` reader - ADC MUX input select"]
pub type ADCMUX_R = crate::FieldReader<ADCMUX>;
impl ADCMUX_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<ADCMUX> {
match self.bits {
0 => Some(ADCMUX::Emux),
2 => Some(ADCMUX::Ad2),
3 => Some(ADCMUX::Ad3),
4 => Some(ADCMUX::Ad4),
5 => Some(ADCMUX::Ad5),
7 => Some(ADCMUX::Vssa),
_ => None,
}
}
#[doc = "EMUX"]
#[inline(always)]
pub fn is_emux(&self) -> bool {
*self == ADCMUX::Emux
}
#[doc = "AD2"]
#[inline(always)]
pub fn is_ad2(&self) -> bool {
*self == ADCMUX::Ad2
}
#[doc = "AD3"]
#[inline(always)]
pub fn is_ad3(&self) -> bool {
*self == ADCMUX::Ad3
}
#[doc = "AD4"]
#[inline(always)]
pub fn is_ad4(&self) -> bool {
*self == ADCMUX::Ad4
}
#[doc = "AD5"]
#[inline(always)]
pub fn is_ad5(&self) -> bool {
*self == ADCMUX::Ad5
}
#[doc = "VSSA"]
#[inline(always)]
pub fn is_vssa(&self) -> bool {
*self == ADCMUX::Vssa
}
}
#[doc = "Field `ADCMUX` writer - ADC MUX input select"]
pub type ADCMUX_W<'a, REG> = crate::FieldWriter<'a, REG, 3, ADCMUX>;
impl<'a, REG> ADCMUX_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "EMUX"]
#[inline(always)]
pub fn emux(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Emux)
}
#[doc = "AD2"]
#[inline(always)]
pub fn ad2(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Ad2)
}
#[doc = "AD3"]
#[inline(always)]
pub fn ad3(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Ad3)
}
#[doc = "AD4"]
#[inline(always)]
pub fn ad4(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Ad4)
}
#[doc = "AD5"]
#[inline(always)]
pub fn ad5(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Ad5)
}
#[doc = "VSSA"]
#[inline(always)]
pub fn vssa(self) -> &'a mut crate::W<REG> {
self.variant(ADCMUX::Vssa)
}
}
impl R {
#[doc = "Bits 0:7 - EMUXD"]
#[inline(always)]
pub fn emuxd(&self) -> EMUXD_R {
EMUXD_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:9 - EMUX transmission start"]
#[inline(always)]
pub fn emuxs(&self) -> EMUXS_R {
EMUXS_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - Delay between start of sample sequence and start of ADC conversion in input clocks"]
#[inline(always)]
pub fn delay(&self) -> DELAY_R {
DELAY_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:14 - ADC MUX input select"]
#[inline(always)]
pub fn adcmux(&self) -> ADCMUX_R {
ADCMUX_R::new(((self.bits >> 12) & 7) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("AS1S0")
.field("emuxd", &self.emuxd())
.field("emuxs", &self.emuxs())
.field("delay", &self.delay())
.field("adcmux", &self.adcmux())
.finish()
}
}
impl W {
#[doc = "Bits 0:7 - EMUXD"]
#[inline(always)]
pub fn emuxd(&mut self) -> EMUXD_W<AS1S0rs> {
EMUXD_W::new(self, 0)
}
#[doc = "Bits 8:9 - EMUX transmission start"]
#[inline(always)]
pub fn emuxs(&mut self) -> EMUXS_W<AS1S0rs> {
EMUXS_W::new(self, 8)
}
#[doc = "Bits 10:11 - Delay between start of sample sequence and start of ADC conversion in input clocks"]
#[inline(always)]
pub fn delay(&mut self) -> DELAY_W<AS1S0rs> {
DELAY_W::new(self, 10)
}
#[doc = "Bits 12:14 - ADC MUX input select"]
#[inline(always)]
pub fn adcmux(&mut self) -> ADCMUX_W<AS1S0rs> {
ADCMUX_W::new(self, 12)
}
}
#[doc = "Auto sequencer 1 sample 0 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1s0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1s0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS1S0rs;
impl crate::RegisterSpec for AS1S0rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as1s0::R`](R) reader structure"]
impl crate::Readable for AS1S0rs {}
#[doc = "`write(|w| ..)` method takes [`as1s0::W`](W) writer structure"]
impl crate::Writable for AS1S0rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS1S0 to value 0"]
impl crate::Resettable for AS1S0rs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "AS1R0 (rw) register accessor: Auto sequencer 1 sample 0 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1r0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1r0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as1r0`]
module"]
pub type AS1R0 = crate::Reg<as1r0::AS1R0rs>;
#[doc = "Auto sequencer 1 sample 0 result register"]
pub mod as1r0 {
#[doc = "Register `AS1R0` reader"]
pub type R = crate::R<AS1R0rs>;
#[doc = "Register `AS1R0` writer"]
pub type W = crate::W<AS1R0rs>;
#[doc = "Field `ADCRESULT` reader - ADC conversion result"]
pub type ADCRESULT_R = crate::FieldReader<u16>;
#[doc = "Field `ADCRESULT` writer - ADC conversion result"]
pub type ADCRESULT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
impl R {
#[doc = "Bits 0:9 - ADC conversion result"]
#[inline(always)]
pub fn adcresult(&self) -> ADCRESULT_R {
ADCRESULT_R::new((self.bits & 0x03ff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("AS1R0")
.field("adcresult", &self.adcresult())
.finish()
}
}
impl W {
#[doc = "Bits 0:9 - ADC conversion result"]
#[inline(always)]
pub fn adcresult(&mut self) -> ADCRESULT_W<AS1R0rs> {
ADCRESULT_W::new(self, 0)
}
}
#[doc = "Auto sequencer 1 sample 0 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1r0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1r0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS1R0rs;
impl crate::RegisterSpec for AS1R0rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as1r0::R`](R) reader structure"]
impl crate::Readable for AS1R0rs {}
#[doc = "`write(|w| ..)` method takes [`as1r0::W`](W) writer structure"]
impl crate::Writable for AS1R0rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS1R0 to value 0"]
impl crate::Resettable for AS1R0rs {
const RESET_VALUE: u32 = 0;
}
}
pub use as0s0 as as1s1;
pub use AS0S0 as AS1S1;
#[doc = "AS1R1 (rw) register accessor: Auto sequencer 1 sample 1 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1r1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1r1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as1r1`]
module"]
pub type AS1R1 = crate::Reg<as1r1::AS1R1rs>;
#[doc = "Auto sequencer 1 sample 1 result register"]
pub mod as1r1 {
#[doc = "Register `AS1R1` reader"]
pub type R = crate::R<AS1R1rs>;
#[doc = "Register `AS1R1` writer"]
pub type W = crate::W<AS1R1rs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Auto sequencer 1 sample 1 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1r1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1r1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS1R1rs;
impl crate::RegisterSpec for AS1R1rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as1r1::R`](R) reader structure"]
impl crate::Readable for AS1R1rs {}
#[doc = "`write(|w| ..)` method takes [`as1r1::W`](W) writer structure"]
impl crate::Writable for AS1R1rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS1R1 to value 0"]
impl crate::Resettable for AS1R1rs {
const RESET_VALUE: u32 = 0;
}
}
pub use as0s0 as as1s2;
pub use AS0S0 as AS1S2;
#[doc = "AS1R2 (rw) register accessor: Auto sequencer 1 sample 2 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1r2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1r2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as1r2`]
module"]
pub type AS1R2 = crate::Reg<as1r2::AS1R2rs>;
#[doc = "Auto sequencer 1 sample 2 result register"]
pub mod as1r2 {
#[doc = "Register `AS1R2` reader"]
pub type R = crate::R<AS1R2rs>;
#[doc = "Register `AS1R2` writer"]
pub type W = crate::W<AS1R2rs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Auto sequencer 1 sample 2 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1r2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1r2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS1R2rs;
impl crate::RegisterSpec for AS1R2rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as1r2::R`](R) reader structure"]
impl crate::Readable for AS1R2rs {}
#[doc = "`write(|w| ..)` method takes [`as1r2::W`](W) writer structure"]
impl crate::Writable for AS1R2rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS1R2 to value 0"]
impl crate::Resettable for AS1R2rs {
const RESET_VALUE: u32 = 0;
}
}
pub use as0s0 as as1s3;
pub use AS0S0 as AS1S3;
#[doc = "AS1R3 (rw) register accessor: Auto sequencer 1 sample 3 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1r3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1r3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as1r3`]
module"]
pub type AS1R3 = crate::Reg<as1r3::AS1R3rs>;
#[doc = "Auto sequencer 1 sample 3 result register"]
pub mod as1r3 {
#[doc = "Register `AS1R3` reader"]
pub type R = crate::R<AS1R3rs>;
#[doc = "Register `AS1R3` writer"]
pub type W = crate::W<AS1R3rs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Auto sequencer 1 sample 3 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1r3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1r3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS1R3rs;
impl crate::RegisterSpec for AS1R3rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as1r3::R`](R) reader structure"]
impl crate::Readable for AS1R3rs {}
#[doc = "`write(|w| ..)` method takes [`as1r3::W`](W) writer structure"]
impl crate::Writable for AS1R3rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS1R3 to value 0"]
impl crate::Resettable for AS1R3rs {
const RESET_VALUE: u32 = 0;
}
}
pub use as0s0 as as1s4;
pub use AS0S0 as AS1S4;
#[doc = "AS1R4 (rw) register accessor: Auto sequencer 1 sample 4 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1r4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1r4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as1r4`]
module"]
pub type AS1R4 = crate::Reg<as1r4::AS1R4rs>;
#[doc = "Auto sequencer 1 sample 4 result register"]
pub mod as1r4 {
#[doc = "Register `AS1R4` reader"]
pub type R = crate::R<AS1R4rs>;
#[doc = "Register `AS1R4` writer"]
pub type W = crate::W<AS1R4rs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Auto sequencer 1 sample 4 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1r4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1r4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS1R4rs;
impl crate::RegisterSpec for AS1R4rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as1r4::R`](R) reader structure"]
impl crate::Readable for AS1R4rs {}
#[doc = "`write(|w| ..)` method takes [`as1r4::W`](W) writer structure"]
impl crate::Writable for AS1R4rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS1R4 to value 0"]
impl crate::Resettable for AS1R4rs {
const RESET_VALUE: u32 = 0;
}
}
pub use as0s0 as as1s5;
pub use AS0S0 as AS1S5;
#[doc = "AS1R5 (rw) register accessor: Auto sequencer 1 sample 5 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1r5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1r5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as1r5`]
module"]
pub type AS1R5 = crate::Reg<as1r5::AS1R5rs>;
#[doc = "Auto sequencer 1 sample 5 result register"]
pub mod as1r5 {
#[doc = "Register `AS1R5` reader"]
pub type R = crate::R<AS1R5rs>;
#[doc = "Register `AS1R5` writer"]
pub type W = crate::W<AS1R5rs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Auto sequencer 1 sample 5 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1r5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1r5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS1R5rs;
impl crate::RegisterSpec for AS1R5rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as1r5::R`](R) reader structure"]
impl crate::Readable for AS1R5rs {}
#[doc = "`write(|w| ..)` method takes [`as1r5::W`](W) writer structure"]
impl crate::Writable for AS1R5rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS1R5 to value 0"]
impl crate::Resettable for AS1R5rs {
const RESET_VALUE: u32 = 0;
}
}
pub use as0s0 as as1s6;
pub use AS0S0 as AS1S6;
#[doc = "AS1R6 (rw) register accessor: Auto sequencer 1 sample 6 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1r6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1r6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as1r6`]
module"]
pub type AS1R6 = crate::Reg<as1r6::AS1R6rs>;
#[doc = "Auto sequencer 1 sample 6 result register"]
pub mod as1r6 {
#[doc = "Register `AS1R6` reader"]
pub type R = crate::R<AS1R6rs>;
#[doc = "Register `AS1R6` writer"]
pub type W = crate::W<AS1R6rs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Auto sequencer 1 sample 6 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1r6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1r6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS1R6rs;
impl crate::RegisterSpec for AS1R6rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as1r6::R`](R) reader structure"]
impl crate::Readable for AS1R6rs {}
#[doc = "`write(|w| ..)` method takes [`as1r6::W`](W) writer structure"]
impl crate::Writable for AS1R6rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS1R6 to value 0"]
impl crate::Resettable for AS1R6rs {
const RESET_VALUE: u32 = 0;
}
}
pub use as0s0 as as1s7;
pub use AS0S0 as AS1S7;
#[doc = "AS1R7 (rw) register accessor: Auto sequencer 1 sample 7 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1r7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1r7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@as1r7`]
module"]
pub type AS1R7 = crate::Reg<as1r7::AS1R7rs>;
#[doc = "Auto sequencer 1 sample 7 result register"]
pub mod as1r7 {
#[doc = "Register `AS1R7` reader"]
pub type R = crate::R<AS1R7rs>;
#[doc = "Register `AS1R7` writer"]
pub type W = crate::W<AS1R7rs>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Auto sequencer 1 sample 7 result register\n\nYou can [`read`](crate::Reg::read) this register and get [`as1r7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`as1r7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AS1R7rs;
impl crate::RegisterSpec for AS1R7rs {
type Ux = u32;
}
#[doc = "`read()` method returns [`as1r7::R`](R) reader structure"]
impl crate::Readable for AS1R7rs {}
#[doc = "`write(|w| ..)` method takes [`as1r7::W`](W) writer structure"]
impl crate::Writable for AS1R7rs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets AS1R7 to value 0"]
impl crate::Resettable for AS1R7rs {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "I2C"]
pub struct I2C {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for I2C {}
impl I2C {
#[doc = r"Pointer to the register block"]
pub const PTR: *const i2c::RegisterBlock = 0x401b_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const i2c::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for I2C {
type Target = i2c::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for I2C {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C").finish()
}
}
#[doc = "I2C"]
pub mod i2c {
#[repr(C)]
#[derive(Debug)]
#[doc = "Register block"]
pub struct RegisterBlock {
i2ccfg: I2CCFG,
i2cint: I2CINT,
i2cinten: I2CINTEN,
_reserved3: [u8; 0x24],
i2cmactl: I2CMACTL,
i2cmarxdata: I2CMARXDATA,
i2cmatxdata: I2CMATXDATA,
_reserved6: [u8; 0x04],
i2cbaud: I2CBAUD,
_reserved7: [u8; 0x2c],
i2cslrxdata: I2CSLRXDATA,
i2csltxdata: I2CSLTXDATA,
i2csladdr: I2CSLADDR,
}
impl RegisterBlock {
#[doc = "0x00 - I2C Configuration Register"]
#[inline(always)]
pub const fn i2ccfg(&self) -> &I2CCFG {
&self.i2ccfg
}
#[doc = "0x04 - I2C Interrupt"]
#[inline(always)]
pub const fn i2cint(&self) -> &I2CINT {
&self.i2cint
}
#[doc = "0x08 - I2C Interrupt Enable"]
#[inline(always)]
pub const fn i2cinten(&self) -> &I2CINTEN {
&self.i2cinten
}
#[doc = "0x30 - I2C master access control"]
#[inline(always)]
pub const fn i2cmactl(&self) -> &I2CMACTL {
&self.i2cmactl
}
#[doc = "0x34 - I2C master receive data"]
#[inline(always)]
pub const fn i2cmarxdata(&self) -> &I2CMARXDATA {
&self.i2cmarxdata
}
#[doc = "0x38 - I2C master transmit data"]
#[inline(always)]
pub const fn i2cmatxdata(&self) -> &I2CMATXDATA {
&self.i2cmatxdata
}
#[doc = "0x40 - I2C baud rate"]
#[inline(always)]
pub const fn i2cbaud(&self) -> &I2CBAUD {
&self.i2cbaud
}
#[doc = "0x70 - I2C slave receive data"]
#[inline(always)]
pub const fn i2cslrxdata(&self) -> &I2CSLRXDATA {
&self.i2cslrxdata
}
#[doc = "0x74 - I2C slave receive data"]
#[inline(always)]
pub const fn i2csltxdata(&self) -> &I2CSLTXDATA {
&self.i2csltxdata
}
#[doc = "0x78 - I2C slave address"]
#[inline(always)]
pub const fn i2csladdr(&self) -> &I2CSLADDR {
&self.i2csladdr
}
}
#[doc = "I2CCFG (rw) register accessor: I2C Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2ccfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2ccfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2ccfg`]
module"]
pub type I2CCFG = crate::Reg<i2ccfg::I2CCFGrs>;
#[doc = "I2C Configuration Register"]
pub mod i2ccfg {
#[doc = "Register `I2CCFG` reader"]
pub type R = crate::R<I2CCFGrs>;
#[doc = "Register `I2CCFG` writer"]
pub type W = crate::W<I2CCFGrs>;
#[doc = "Slave Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SLEN {
#[doc = "0: I2C Slave disable"]
Disable = 0,
#[doc = "1: I2C Slave enable"]
Enable = 1,
}
impl From<SLEN> for bool {
#[inline(always)]
fn from(variant: SLEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SLEN` reader - Slave Enable"]
pub type SLEN_R = crate::BitReader<SLEN>;
impl SLEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SLEN {
match self.bits {
false => SLEN::Disable,
true => SLEN::Enable,
}
}
#[doc = "I2C Slave disable"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == SLEN::Disable
}
#[doc = "I2C Slave enable"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == SLEN::Enable
}
}
#[doc = "Field `SLEN` writer - Slave Enable"]
pub type SLEN_W<'a, REG> = crate::BitWriter<'a, REG, SLEN>;
impl<'a, REG> SLEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "I2C Slave disable"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(SLEN::Disable)
}
#[doc = "I2C Slave enable"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(SLEN::Enable)
}
}
#[doc = "Master Enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MAEN {
#[doc = "0: I2C master disable"]
Disable = 0,
#[doc = "1: I2C Master enable"]
Enable = 1,
}
impl From<MAEN> for bool {
#[inline(always)]
fn from(variant: MAEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MAEN` reader - Master Enable"]
pub type MAEN_R = crate::BitReader<MAEN>;
impl MAEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MAEN {
match self.bits {
false => MAEN::Disable,
true => MAEN::Enable,
}
}
#[doc = "I2C master disable"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == MAEN::Disable
}
#[doc = "I2C Master enable"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == MAEN::Enable
}
}
#[doc = "Field `MAEN` writer - Master Enable"]
pub type MAEN_W<'a, REG> = crate::BitWriter<'a, REG, MAEN>;
impl<'a, REG> MAEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "I2C master disable"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(MAEN::Disable)
}
#[doc = "I2C Master enable"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(MAEN::Enable)
}
}
#[doc = "Address Mode\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum ADDRMODE {
#[doc = "0: 7-bit addressing"]
Mode7Bit = 0,
#[doc = "1: 10-bit addressing"]
Mode10Bit = 1,
}
impl From<ADDRMODE> for bool {
#[inline(always)]
fn from(variant: ADDRMODE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ADDRMODE` reader - Address Mode"]
pub type ADDRMODE_R = crate::BitReader<ADDRMODE>;
impl ADDRMODE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ADDRMODE {
match self.bits {
false => ADDRMODE::Mode7Bit,
true => ADDRMODE::Mode10Bit,
}
}
#[doc = "7-bit addressing"]
#[inline(always)]
pub fn is_mode_7_bit(&self) -> bool {
*self == ADDRMODE::Mode7Bit
}
#[doc = "10-bit addressing"]
#[inline(always)]
pub fn is_mode_10_bit(&self) -> bool {
*self == ADDRMODE::Mode10Bit
}
}
#[doc = "Field `ADDRMODE` writer - Address Mode"]
pub type ADDRMODE_W<'a, REG> = crate::BitWriter<'a, REG, ADDRMODE>;
impl<'a, REG> ADDRMODE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "7-bit addressing"]
#[inline(always)]
pub fn mode_7_bit(self) -> &'a mut crate::W<REG> {
self.variant(ADDRMODE::Mode7Bit)
}
#[doc = "10-bit addressing"]
#[inline(always)]
pub fn mode_10_bit(self) -> &'a mut crate::W<REG> {
self.variant(ADDRMODE::Mode10Bit)
}
}
impl R {
#[doc = "Bit 0 - Slave Enable"]
#[inline(always)]
pub fn slen(&self) -> SLEN_R {
SLEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 2 - Master Enable"]
#[inline(always)]
pub fn maen(&self) -> MAEN_R {
MAEN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 4 - Address Mode"]
#[inline(always)]
pub fn addrmode(&self) -> ADDRMODE_R {
ADDRMODE_R::new(((self.bits >> 4) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2CCFG")
.field("slen", &self.slen())
.field("maen", &self.maen())
.field("addrmode", &self.addrmode())
.finish()
}
}
impl W {
#[doc = "Bit 0 - Slave Enable"]
#[inline(always)]
pub fn slen(&mut self) -> SLEN_W<I2CCFGrs> {
SLEN_W::new(self, 0)
}
#[doc = "Bit 2 - Master Enable"]
#[inline(always)]
pub fn maen(&mut self) -> MAEN_W<I2CCFGrs> {
MAEN_W::new(self, 2)
}
#[doc = "Bit 4 - Address Mode"]
#[inline(always)]
pub fn addrmode(&mut self) -> ADDRMODE_W<I2CCFGrs> {
ADDRMODE_W::new(self, 4)
}
}
#[doc = "I2C Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2ccfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2ccfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2CCFGrs;
impl crate::RegisterSpec for I2CCFGrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`i2ccfg::R`](R) reader structure"]
impl crate::Readable for I2CCFGrs {}
#[doc = "`write(|w| ..)` method takes [`i2ccfg::W`](W) writer structure"]
impl crate::Writable for I2CCFGrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets I2CCFG to value 0x20"]
impl crate::Resettable for I2CCFGrs {
const RESET_VALUE: u32 = 0x20;
}
}
#[doc = "I2CINT (r) register accessor: I2C Interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`i2cint::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2cint`]
module"]
pub type I2CINT = crate::Reg<i2cint::I2CINTrs>;
#[doc = "I2C Interrupt"]
pub mod i2cint {
#[doc = "Register `I2CINT` reader"]
pub type R = crate::R<I2CINTrs>;
#[doc = "Master transmit data register MATXDATA empty\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MATXE {
#[doc = "0: MATXDATA not transmitted since last read of I2CINT"]
NotTransmitted = 0,
#[doc = "1: MATXDATA transmitted to I2C bus, clears on read"]
Transmitted = 1,
}
impl From<MATXE> for bool {
#[inline(always)]
fn from(variant: MATXE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MATXE` reader - Master transmit data register MATXDATA empty"]
pub type MATXE_R = crate::BitReader<MATXE>;
impl MATXE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MATXE {
match self.bits {
false => MATXE::NotTransmitted,
true => MATXE::Transmitted,
}
}
#[doc = "MATXDATA not transmitted since last read of I2CINT"]
#[inline(always)]
pub fn is_not_transmitted(&self) -> bool {
*self == MATXE::NotTransmitted
}
#[doc = "MATXDATA transmitted to I2C bus, clears on read"]
#[inline(always)]
pub fn is_transmitted(&self) -> bool {
*self == MATXE::Transmitted
}
}
#[doc = "MACCTL access register accessed\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MACTLE {
#[doc = "0: I2CMACTL not accessed by I2C engine since last read of I2CINT"]
False = 0,
#[doc = "1: I2CMACTL processed by I2C engine, clears on read"]
True = 1,
}
impl From<MACTLE> for bool {
#[inline(always)]
fn from(variant: MACTLE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MACTLE` reader - MACCTL access register accessed"]
pub type MACTLE_R = crate::BitReader<MACTLE>;
impl MACTLE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MACTLE {
match self.bits {
false => MACTLE::False,
true => MACTLE::True,
}
}
#[doc = "I2CMACTL not accessed by I2C engine since last read of I2CINT"]
#[inline(always)]
pub fn is_false(&self) -> bool {
*self == MACTLE::False
}
#[doc = "I2CMACTL processed by I2C engine, clears on read"]
#[inline(always)]
pub fn is_true(&self) -> bool {
*self == MACTLE::True
}
}
#[doc = "Master receive data register MARXDATA full\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MARXF {
#[doc = "0: MARXDATA did not receive data since last read of I2CINT"]
False = 0,
#[doc = "1: MARXDATA received data from I2C bus, cleared on read"]
True = 1,
}
impl From<MARXF> for bool {
#[inline(always)]
fn from(variant: MARXF) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MARXF` reader - Master receive data register MARXDATA full"]
pub type MARXF_R = crate::BitReader<MARXF>;
impl MARXF_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MARXF {
match self.bits {
false => MARXF::False,
true => MARXF::True,
}
}
#[doc = "MARXDATA did not receive data since last read of I2CINT"]
#[inline(always)]
pub fn is_false(&self) -> bool {
*self == MARXF::False
}
#[doc = "MARXDATA received data from I2C bus, cleared on read"]
#[inline(always)]
pub fn is_true(&self) -> bool {
*self == MARXF::True
}
}
#[doc = "Master transfer complete\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MAXFERDONEINT {
#[doc = "0: not done"]
False = 0,
#[doc = "1: Master transfer complete, cleared on read"]
True = 1,
}
impl From<MAXFERDONEINT> for bool {
#[inline(always)]
fn from(variant: MAXFERDONEINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MAXFERDONEINT` reader - Master transfer complete"]
pub type MAXFERDONEINT_R = crate::BitReader<MAXFERDONEINT>;
impl MAXFERDONEINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MAXFERDONEINT {
match self.bits {
false => MAXFERDONEINT::False,
true => MAXFERDONEINT::True,
}
}
#[doc = "not done"]
#[inline(always)]
pub fn is_false(&self) -> bool {
*self == MAXFERDONEINT::False
}
#[doc = "Master transfer complete, cleared on read"]
#[inline(always)]
pub fn is_true(&self) -> bool {
*self == MAXFERDONEINT::True
}
}
#[doc = "Master address acknowledged\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MAADDRACKINT {
#[doc = "0: Master address ACK'd"]
Ack = 0,
#[doc = "1: Master address NACK'd, cleared on read"]
Nack = 1,
}
impl From<MAADDRACKINT> for bool {
#[inline(always)]
fn from(variant: MAADDRACKINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MAADDRACKINT` reader - Master address acknowledged"]
pub type MAADDRACKINT_R = crate::BitReader<MAADDRACKINT>;
impl MAADDRACKINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MAADDRACKINT {
match self.bits {
false => MAADDRACKINT::Ack,
true => MAADDRACKINT::Nack,
}
}
#[doc = "Master address ACK'd"]
#[inline(always)]
pub fn is_ack(&self) -> bool {
*self == MAADDRACKINT::Ack
}
#[doc = "Master address NACK'd, cleared on read"]
#[inline(always)]
pub fn is_nack(&self) -> bool {
*self == MAADDRACKINT::Nack
}
}
#[doc = "Master lost arbitration\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MAARBLINT {
#[doc = "0: no error"]
False = 0,
#[doc = "1: Master lost arbitration, clear on read"]
True = 1,
}
impl From<MAARBLINT> for bool {
#[inline(always)]
fn from(variant: MAARBLINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MAARBLINT` reader - Master lost arbitration"]
pub type MAARBLINT_R = crate::BitReader<MAARBLINT>;
impl MAARBLINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MAARBLINT {
match self.bits {
false => MAARBLINT::False,
true => MAARBLINT::True,
}
}
#[doc = "no error"]
#[inline(always)]
pub fn is_false(&self) -> bool {
*self == MAARBLINT::False
}
#[doc = "Master lost arbitration, clear on read"]
#[inline(always)]
pub fn is_true(&self) -> bool {
*self == MAARBLINT::True
}
}
#[doc = "Master data acknowledge\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MADACKINT {
#[doc = "0: Master data ACK'd"]
Ack = 0,
#[doc = "1: Master data NACK'd, cleared on read"]
Nack = 1,
}
impl From<MADACKINT> for bool {
#[inline(always)]
fn from(variant: MADACKINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MADACKINT` reader - Master data acknowledge"]
pub type MADACKINT_R = crate::BitReader<MADACKINT>;
impl MADACKINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MADACKINT {
match self.bits {
false => MADACKINT::Ack,
true => MADACKINT::Nack,
}
}
#[doc = "Master data ACK'd"]
#[inline(always)]
pub fn is_ack(&self) -> bool {
*self == MADACKINT::Ack
}
#[doc = "Master data NACK'd, cleared on read"]
#[inline(always)]
pub fn is_nack(&self) -> bool {
*self == MADACKINT::Nack
}
}
#[doc = "Slave address match\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SLADDRMINT {
#[doc = "0: no match"]
None = 0,
#[doc = "1: Slave address match detected, cleared on read"]
Match = 1,
}
impl From<SLADDRMINT> for bool {
#[inline(always)]
fn from(variant: SLADDRMINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SLADDRMINT` reader - Slave address match"]
pub type SLADDRMINT_R = crate::BitReader<SLADDRMINT>;
impl SLADDRMINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SLADDRMINT {
match self.bits {
false => SLADDRMINT::None,
true => SLADDRMINT::Match,
}
}
#[doc = "no match"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == SLADDRMINT::None
}
#[doc = "Slave address match detected, cleared on read"]
#[inline(always)]
pub fn is_match(&self) -> bool {
*self == SLADDRMINT::Match
}
}
#[doc = "Slave transmit data register SLTXDATA empty\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SLTXEINT {
#[doc = "0: SLTXDATA not transmitted since last read of I2CINT"]
False = 0,
#[doc = "1: SLTXDATA transmitted to I2C bus, cleared on read"]
True = 1,
}
impl From<SLTXEINT> for bool {
#[inline(always)]
fn from(variant: SLTXEINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SLTXEINT` reader - Slave transmit data register SLTXDATA empty"]
pub type SLTXEINT_R = crate::BitReader<SLTXEINT>;
impl SLTXEINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SLTXEINT {
match self.bits {
false => SLTXEINT::False,
true => SLTXEINT::True,
}
}
#[doc = "SLTXDATA not transmitted since last read of I2CINT"]
#[inline(always)]
pub fn is_false(&self) -> bool {
*self == SLTXEINT::False
}
#[doc = "SLTXDATA transmitted to I2C bus, cleared on read"]
#[inline(always)]
pub fn is_true(&self) -> bool {
*self == SLTXEINT::True
}
}
#[doc = "Slave receive data register SLRXDATA full\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SLRXFINT {
#[doc = "0: SLRXDATA did not receive data since last read of I2CINT"]
False = 0,
#[doc = "1: SLRXDATA received data from I2C bus, cleared on read"]
True = 1,
}
impl From<SLRXFINT> for bool {
#[inline(always)]
fn from(variant: SLRXFINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SLRXFINT` reader - Slave receive data register SLRXDATA full"]
pub type SLRXFINT_R = crate::BitReader<SLRXFINT>;
impl SLRXFINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SLRXFINT {
match self.bits {
false => SLRXFINT::False,
true => SLRXFINT::True,
}
}
#[doc = "SLRXDATA did not receive data since last read of I2CINT"]
#[inline(always)]
pub fn is_false(&self) -> bool {
*self == SLRXFINT::False
}
#[doc = "SLRXDATA received data from I2C bus, cleared on read"]
#[inline(always)]
pub fn is_true(&self) -> bool {
*self == SLRXFINT::True
}
}
#[doc = "Slave transfer done interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SLXFERDONEINT {
#[doc = "0: Slave transfer not completed"]
False = 0,
#[doc = "1: Slave transfer complete, cleared on read"]
True = 1,
}
impl From<SLXFERDONEINT> for bool {
#[inline(always)]
fn from(variant: SLXFERDONEINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SLXFERDONEINT` reader - Slave transfer done interrupt"]
pub type SLXFERDONEINT_R = crate::BitReader<SLXFERDONEINT>;
impl SLXFERDONEINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SLXFERDONEINT {
match self.bits {
false => SLXFERDONEINT::False,
true => SLXFERDONEINT::True,
}
}
#[doc = "Slave transfer not completed"]
#[inline(always)]
pub fn is_false(&self) -> bool {
*self == SLXFERDONEINT::False
}
#[doc = "Slave transfer complete, cleared on read"]
#[inline(always)]
pub fn is_true(&self) -> bool {
*self == SLXFERDONEINT::True
}
}
impl R {
#[doc = "Bit 0 - Master transmit data register MATXDATA empty"]
#[inline(always)]
pub fn matxe(&self) -> MATXE_R {
MATXE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - MACCTL access register accessed"]
#[inline(always)]
pub fn mactle(&self) -> MACTLE_R {
MACTLE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Master receive data register MARXDATA full"]
#[inline(always)]
pub fn marxf(&self) -> MARXF_R {
MARXF_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 8 - Master transfer complete"]
#[inline(always)]
pub fn maxferdoneint(&self) -> MAXFERDONEINT_R {
MAXFERDONEINT_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Master address acknowledged"]
#[inline(always)]
pub fn maaddrackint(&self) -> MAADDRACKINT_R {
MAADDRACKINT_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Master lost arbitration"]
#[inline(always)]
pub fn maarblint(&self) -> MAARBLINT_R {
MAARBLINT_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Master data acknowledge"]
#[inline(always)]
pub fn madackint(&self) -> MADACKINT_R {
MADACKINT_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 16 - Slave address match"]
#[inline(always)]
pub fn sladdrmint(&self) -> SLADDRMINT_R {
SLADDRMINT_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Slave transmit data register SLTXDATA empty"]
#[inline(always)]
pub fn sltxeint(&self) -> SLTXEINT_R {
SLTXEINT_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Slave receive data register SLRXDATA full"]
#[inline(always)]
pub fn slrxfint(&self) -> SLRXFINT_R {
SLRXFINT_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 24 - Slave transfer done interrupt"]
#[inline(always)]
pub fn slxferdoneint(&self) -> SLXFERDONEINT_R {
SLXFERDONEINT_R::new(((self.bits >> 24) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2CINT")
.field("matxe", &self.matxe())
.field("mactle", &self.mactle())
.field("marxf", &self.marxf())
.field("maxferdoneint", &self.maxferdoneint())
.field("maaddrackint", &self.maaddrackint())
.field("maarblint", &self.maarblint())
.field("madackint", &self.madackint())
.field("sladdrmint", &self.sladdrmint())
.field("sltxeint", &self.sltxeint())
.field("slrxfint", &self.slrxfint())
.field("slxferdoneint", &self.slxferdoneint())
.finish()
}
}
#[doc = "I2C Interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`i2cint::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2CINTrs;
impl crate::RegisterSpec for I2CINTrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`i2cint::R`](R) reader structure"]
impl crate::Readable for I2CINTrs {}
#[doc = "`reset()` method sets I2CINT to value 0"]
impl crate::Resettable for I2CINTrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "I2CINTEN (rw) register accessor: I2C Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`i2cinten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2cinten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2cinten`]
module"]
pub type I2CINTEN = crate::Reg<i2cinten::I2CINTENrs>;
#[doc = "I2C Interrupt Enable"]
pub mod i2cinten {
#[doc = "Register `I2CINTEN` reader"]
pub type R = crate::R<I2CINTENrs>;
#[doc = "Register `I2CINTEN` writer"]
pub type W = crate::W<I2CINTENrs>;
#[doc = "MATXE interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MATXE {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<MATXE> for bool {
#[inline(always)]
fn from(variant: MATXE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MATXE` reader - MATXE interrupt enable"]
pub type MATXE_R = crate::BitReader<MATXE>;
impl MATXE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MATXE {
match self.bits {
false => MATXE::Disabled,
true => MATXE::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == MATXE::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == MATXE::Enabled
}
}
#[doc = "Field `MATXE` writer - MATXE interrupt enable"]
pub type MATXE_W<'a, REG> = crate::BitWriter<'a, REG, MATXE>;
impl<'a, REG> MATXE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(MATXE::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(MATXE::Enabled)
}
}
#[doc = "MACTLE interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MACTLE {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<MACTLE> for bool {
#[inline(always)]
fn from(variant: MACTLE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MACTLE` reader - MACTLE interrupt enable"]
pub type MACTLE_R = crate::BitReader<MACTLE>;
impl MACTLE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MACTLE {
match self.bits {
false => MACTLE::Disabled,
true => MACTLE::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == MACTLE::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == MACTLE::Enabled
}
}
#[doc = "Field `MACTLE` writer - MACTLE interrupt enable"]
pub type MACTLE_W<'a, REG> = crate::BitWriter<'a, REG, MACTLE>;
impl<'a, REG> MACTLE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(MACTLE::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(MACTLE::Enabled)
}
}
#[doc = "MARXF interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MARXF {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<MARXF> for bool {
#[inline(always)]
fn from(variant: MARXF) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MARXF` reader - MARXF interrupt enable"]
pub type MARXF_R = crate::BitReader<MARXF>;
impl MARXF_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MARXF {
match self.bits {
false => MARXF::Disabled,
true => MARXF::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == MARXF::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == MARXF::Enabled
}
}
#[doc = "Field `MARXF` writer - MARXF interrupt enable"]
pub type MARXF_W<'a, REG> = crate::BitWriter<'a, REG, MARXF>;
impl<'a, REG> MARXF_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(MARXF::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(MARXF::Enabled)
}
}
#[doc = "MAXFERDONE interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MAXFERDONE {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<MAXFERDONE> for bool {
#[inline(always)]
fn from(variant: MAXFERDONE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MAXFERDONE` reader - MAXFERDONE interrupt enable"]
pub type MAXFERDONE_R = crate::BitReader<MAXFERDONE>;
impl MAXFERDONE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MAXFERDONE {
match self.bits {
false => MAXFERDONE::Disabled,
true => MAXFERDONE::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == MAXFERDONE::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == MAXFERDONE::Enabled
}
}
#[doc = "Field `MAXFERDONE` writer - MAXFERDONE interrupt enable"]
pub type MAXFERDONE_W<'a, REG> = crate::BitWriter<'a, REG, MAXFERDONE>;
impl<'a, REG> MAXFERDONE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(MAXFERDONE::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(MAXFERDONE::Enabled)
}
}
#[doc = "SLADDRM interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SLADDRM {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<SLADDRM> for bool {
#[inline(always)]
fn from(variant: SLADDRM) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SLADDRM` reader - SLADDRM interrupt enable"]
pub type SLADDRM_R = crate::BitReader<SLADDRM>;
impl SLADDRM_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SLADDRM {
match self.bits {
false => SLADDRM::Disabled,
true => SLADDRM::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == SLADDRM::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == SLADDRM::Enabled
}
}
#[doc = "Field `SLADDRM` writer - SLADDRM interrupt enable"]
pub type SLADDRM_W<'a, REG> = crate::BitWriter<'a, REG, SLADDRM>;
impl<'a, REG> SLADDRM_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(SLADDRM::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(SLADDRM::Enabled)
}
}
#[doc = "SLTXE interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SLTXE {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<SLTXE> for bool {
#[inline(always)]
fn from(variant: SLTXE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SLTXE` reader - SLTXE interrupt enable"]
pub type SLTXE_R = crate::BitReader<SLTXE>;
impl SLTXE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SLTXE {
match self.bits {
false => SLTXE::Disabled,
true => SLTXE::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == SLTXE::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == SLTXE::Enabled
}
}
#[doc = "Field `SLTXE` writer - SLTXE interrupt enable"]
pub type SLTXE_W<'a, REG> = crate::BitWriter<'a, REG, SLTXE>;
impl<'a, REG> SLTXE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(SLTXE::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(SLTXE::Enabled)
}
}
#[doc = "SLRXF interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SLRXF {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<SLRXF> for bool {
#[inline(always)]
fn from(variant: SLRXF) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SLRXF` reader - SLRXF interrupt enable"]
pub type SLRXF_R = crate::BitReader<SLRXF>;
impl SLRXF_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SLRXF {
match self.bits {
false => SLRXF::Disabled,
true => SLRXF::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == SLRXF::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == SLRXF::Enabled
}
}
#[doc = "Field `SLRXF` writer - SLRXF interrupt enable"]
pub type SLRXF_W<'a, REG> = crate::BitWriter<'a, REG, SLRXF>;
impl<'a, REG> SLRXF_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(SLRXF::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(SLRXF::Enabled)
}
}
#[doc = "SLXFERDONEINTEN interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SLXFERDONEINTEN {
#[doc = "0: interrupt disabled"]
Disabled = 0,
#[doc = "1: interrupt enabled"]
Enabled = 1,
}
impl From<SLXFERDONEINTEN> for bool {
#[inline(always)]
fn from(variant: SLXFERDONEINTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SLXFERDONEINTEN` reader - SLXFERDONEINTEN interrupt enable"]
pub type SLXFERDONEINTEN_R = crate::BitReader<SLXFERDONEINTEN>;
impl SLXFERDONEINTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SLXFERDONEINTEN {
match self.bits {
false => SLXFERDONEINTEN::Disabled,
true => SLXFERDONEINTEN::Enabled,
}
}
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == SLXFERDONEINTEN::Disabled
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == SLXFERDONEINTEN::Enabled
}
}
#[doc = "Field `SLXFERDONEINTEN` writer - SLXFERDONEINTEN interrupt enable"]
pub type SLXFERDONEINTEN_W<'a, REG> = crate::BitWriter<'a, REG, SLXFERDONEINTEN>;
impl<'a, REG> SLXFERDONEINTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "interrupt disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(SLXFERDONEINTEN::Disabled)
}
#[doc = "interrupt enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(SLXFERDONEINTEN::Enabled)
}
}
impl R {
#[doc = "Bit 0 - MATXE interrupt enable"]
#[inline(always)]
pub fn matxe(&self) -> MATXE_R {
MATXE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - MACTLE interrupt enable"]
#[inline(always)]
pub fn mactle(&self) -> MACTLE_R {
MACTLE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - MARXF interrupt enable"]
#[inline(always)]
pub fn marxf(&self) -> MARXF_R {
MARXF_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 8 - MAXFERDONE interrupt enable"]
#[inline(always)]
pub fn maxferdone(&self) -> MAXFERDONE_R {
MAXFERDONE_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 16 - SLADDRM interrupt enable"]
#[inline(always)]
pub fn sladdrm(&self) -> SLADDRM_R {
SLADDRM_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - SLTXE interrupt enable"]
#[inline(always)]
pub fn sltxe(&self) -> SLTXE_R {
SLTXE_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - SLRXF interrupt enable"]
#[inline(always)]
pub fn slrxf(&self) -> SLRXF_R {
SLRXF_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 24 - SLXFERDONEINTEN interrupt enable"]
#[inline(always)]
pub fn slxferdoneinten(&self) -> SLXFERDONEINTEN_R {
SLXFERDONEINTEN_R::new(((self.bits >> 24) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2CINTEN")
.field("matxe", &self.matxe())
.field("mactle", &self.mactle())
.field("marxf", &self.marxf())
.field("maxferdone", &self.maxferdone())
.field("sladdrm", &self.sladdrm())
.field("sltxe", &self.sltxe())
.field("slrxf", &self.slrxf())
.field("slxferdoneinten", &self.slxferdoneinten())
.finish()
}
}
impl W {
#[doc = "Bit 0 - MATXE interrupt enable"]
#[inline(always)]
pub fn matxe(&mut self) -> MATXE_W<I2CINTENrs> {
MATXE_W::new(self, 0)
}
#[doc = "Bit 1 - MACTLE interrupt enable"]
#[inline(always)]
pub fn mactle(&mut self) -> MACTLE_W<I2CINTENrs> {
MACTLE_W::new(self, 1)
}
#[doc = "Bit 2 - MARXF interrupt enable"]
#[inline(always)]
pub fn marxf(&mut self) -> MARXF_W<I2CINTENrs> {
MARXF_W::new(self, 2)
}
#[doc = "Bit 8 - MAXFERDONE interrupt enable"]
#[inline(always)]
pub fn maxferdone(&mut self) -> MAXFERDONE_W<I2CINTENrs> {
MAXFERDONE_W::new(self, 8)
}
#[doc = "Bit 16 - SLADDRM interrupt enable"]
#[inline(always)]
pub fn sladdrm(&mut self) -> SLADDRM_W<I2CINTENrs> {
SLADDRM_W::new(self, 16)
}
#[doc = "Bit 17 - SLTXE interrupt enable"]
#[inline(always)]
pub fn sltxe(&mut self) -> SLTXE_W<I2CINTENrs> {
SLTXE_W::new(self, 17)
}
#[doc = "Bit 18 - SLRXF interrupt enable"]
#[inline(always)]
pub fn slrxf(&mut self) -> SLRXF_W<I2CINTENrs> {
SLRXF_W::new(self, 18)
}
#[doc = "Bit 24 - SLXFERDONEINTEN interrupt enable"]
#[inline(always)]
pub fn slxferdoneinten(&mut self) -> SLXFERDONEINTEN_W<I2CINTENrs> {
SLXFERDONEINTEN_W::new(self, 24)
}
}
#[doc = "I2C Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`i2cinten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2cinten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2CINTENrs;
impl crate::RegisterSpec for I2CINTENrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`i2cinten::R`](R) reader structure"]
impl crate::Readable for I2CINTENrs {}
#[doc = "`write(|w| ..)` method takes [`i2cinten::W`](W) writer structure"]
impl crate::Writable for I2CINTENrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets I2CINTEN to value 0"]
impl crate::Resettable for I2CINTENrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "I2CMACTL (rw) register accessor: I2C master access control\n\nYou can [`read`](crate::Reg::read) this register and get [`i2cmactl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2cmactl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2cmactl`]
module"]
pub type I2CMACTL = crate::Reg<i2cmactl::I2CMACTLrs>;
#[doc = "I2C master access control"]
pub mod i2cmactl {
#[doc = "Register `I2CMACTL` reader"]
pub type R = crate::R<I2CMACTLrs>;
#[doc = "Register `I2CMACTL` writer"]
pub type W = crate::W<I2CMACTLrs>;
#[doc = "Field `I2CADDRL` reader - Lower I2C address bits 6:0"]
pub type I2CADDRL_R = crate::FieldReader;
#[doc = "Field `I2CADDRL` writer - Lower I2C address bits 6:0"]
pub type I2CADDRL_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `I2CADDRU` reader - Upper I2C address bits 9:7"]
pub type I2CADDRU_R = crate::FieldReader;
#[doc = "Field `I2CADDRU` writer - Upper I2C address bits 9:7"]
pub type I2CADDRU_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Repeated start\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RSTART {
#[doc = "0: STOP at end of transfer"]
No = 0,
#[doc = "1: No STOP at end of transfer, repeated START"]
Yes = 1,
}
impl From<RSTART> for bool {
#[inline(always)]
fn from(variant: RSTART) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RSTART` reader - Repeated start"]
pub type RSTART_R = crate::BitReader<RSTART>;
impl RSTART_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RSTART {
match self.bits {
false => RSTART::No,
true => RSTART::Yes,
}
}
#[doc = "STOP at end of transfer"]
#[inline(always)]
pub fn is_no(&self) -> bool {
*self == RSTART::No
}
#[doc = "No STOP at end of transfer, repeated START"]
#[inline(always)]
pub fn is_yes(&self) -> bool {
*self == RSTART::Yes
}
}
#[doc = "Field `RSTART` writer - Repeated start"]
pub type RSTART_W<'a, REG> = crate::BitWriter<'a, REG, RSTART>;
impl<'a, REG> RSTART_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "STOP at end of transfer"]
#[inline(always)]
pub fn no(self) -> &'a mut crate::W<REG> {
self.variant(RSTART::No)
}
#[doc = "No STOP at end of transfer, repeated START"]
#[inline(always)]
pub fn yes(self) -> &'a mut crate::W<REG> {
self.variant(RSTART::Yes)
}
}
#[doc = "Master transfer type\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum XFERTYPE {
#[doc = "0: I2C Master write"]
Write = 0,
#[doc = "1: I2C Master read"]
Read = 1,
}
impl From<XFERTYPE> for bool {
#[inline(always)]
fn from(variant: XFERTYPE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `XFERTYPE` reader - Master transfer type"]
pub type XFERTYPE_R = crate::BitReader<XFERTYPE>;
impl XFERTYPE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> XFERTYPE {
match self.bits {
false => XFERTYPE::Write,
true => XFERTYPE::Read,
}
}
#[doc = "I2C Master write"]
#[inline(always)]
pub fn is_write(&self) -> bool {
*self == XFERTYPE::Write
}
#[doc = "I2C Master read"]
#[inline(always)]
pub fn is_read(&self) -> bool {
*self == XFERTYPE::Read
}
}
#[doc = "Field `XFERTYPE` writer - Master transfer type"]
pub type XFERTYPE_W<'a, REG> = crate::BitWriter<'a, REG, XFERTYPE>;
impl<'a, REG> XFERTYPE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "I2C Master write"]
#[inline(always)]
pub fn write(self) -> &'a mut crate::W<REG> {
self.variant(XFERTYPE::Write)
}
#[doc = "I2C Master read"]
#[inline(always)]
pub fn read(self) -> &'a mut crate::W<REG> {
self.variant(XFERTYPE::Read)
}
}
#[doc = "I2CMACTL full\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum I2CMACTLF {
#[doc = "0: I2CMACTL processed, write allowed"]
NotFull = 0,
#[doc = "1: I2CMACTL full, write not allowed, cleared on read"]
Full = 1,
}
impl From<I2CMACTLF> for bool {
#[inline(always)]
fn from(variant: I2CMACTLF) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `I2CMACTLF` reader - I2CMACTL full"]
pub type I2CMACTLF_R = crate::BitReader<I2CMACTLF>;
impl I2CMACTLF_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> I2CMACTLF {
match self.bits {
false => I2CMACTLF::NotFull,
true => I2CMACTLF::Full,
}
}
#[doc = "I2CMACTL processed, write allowed"]
#[inline(always)]
pub fn is_not_full(&self) -> bool {
*self == I2CMACTLF::NotFull
}
#[doc = "I2CMACTL full, write not allowed, cleared on read"]
#[inline(always)]
pub fn is_full(&self) -> bool {
*self == I2CMACTLF::Full
}
}
#[doc = "Field `I2CMACTLF` writer - I2CMACTL full"]
pub type I2CMACTLF_W<'a, REG> = crate::BitWriter<'a, REG, I2CMACTLF>;
impl<'a, REG> I2CMACTLF_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "I2CMACTL processed, write allowed"]
#[inline(always)]
pub fn not_full(self) -> &'a mut crate::W<REG> {
self.variant(I2CMACTLF::NotFull)
}
#[doc = "I2CMACTL full, write not allowed, cleared on read"]
#[inline(always)]
pub fn full(self) -> &'a mut crate::W<REG> {
self.variant(I2CMACTLF::Full)
}
}
impl R {
#[doc = "Bits 0:6 - Lower I2C address bits 6:0"]
#[inline(always)]
pub fn i2caddrl(&self) -> I2CADDRL_R {
I2CADDRL_R::new((self.bits & 0x7f) as u8)
}
#[doc = "Bits 7:9 - Upper I2C address bits 9:7"]
#[inline(always)]
pub fn i2caddru(&self) -> I2CADDRU_R {
I2CADDRU_R::new(((self.bits >> 7) & 7) as u8)
}
#[doc = "Bit 10 - Repeated start"]
#[inline(always)]
pub fn rstart(&self) -> RSTART_R {
RSTART_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Master transfer type"]
#[inline(always)]
pub fn xfertype(&self) -> XFERTYPE_R {
XFERTYPE_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 13 - I2CMACTL full"]
#[inline(always)]
pub fn i2cmactlf(&self) -> I2CMACTLF_R {
I2CMACTLF_R::new(((self.bits >> 13) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2CMACTL")
.field("i2caddrl", &self.i2caddrl())
.field("i2caddru", &self.i2caddru())
.field("rstart", &self.rstart())
.field("xfertype", &self.xfertype())
.field("i2cmactlf", &self.i2cmactlf())
.finish()
}
}
impl W {
#[doc = "Bits 0:6 - Lower I2C address bits 6:0"]
#[inline(always)]
pub fn i2caddrl(&mut self) -> I2CADDRL_W<I2CMACTLrs> {
I2CADDRL_W::new(self, 0)
}
#[doc = "Bits 7:9 - Upper I2C address bits 9:7"]
#[inline(always)]
pub fn i2caddru(&mut self) -> I2CADDRU_W<I2CMACTLrs> {
I2CADDRU_W::new(self, 7)
}
#[doc = "Bit 10 - Repeated start"]
#[inline(always)]
pub fn rstart(&mut self) -> RSTART_W<I2CMACTLrs> {
RSTART_W::new(self, 10)
}
#[doc = "Bit 11 - Master transfer type"]
#[inline(always)]
pub fn xfertype(&mut self) -> XFERTYPE_W<I2CMACTLrs> {
XFERTYPE_W::new(self, 11)
}
#[doc = "Bit 13 - I2CMACTL full"]
#[inline(always)]
pub fn i2cmactlf(&mut self) -> I2CMACTLF_W<I2CMACTLrs> {
I2CMACTLF_W::new(self, 13)
}
}
#[doc = "I2C master access control\n\nYou can [`read`](crate::Reg::read) this register and get [`i2cmactl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2cmactl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2CMACTLrs;
impl crate::RegisterSpec for I2CMACTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`i2cmactl::R`](R) reader structure"]
impl crate::Readable for I2CMACTLrs {}
#[doc = "`write(|w| ..)` method takes [`i2cmactl::W`](W) writer structure"]
impl crate::Writable for I2CMACTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets I2CMACTL to value 0"]
impl crate::Resettable for I2CMACTLrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "I2CMARXDATA (rw) register accessor: I2C master receive data\n\nYou can [`read`](crate::Reg::read) this register and get [`i2cmarxdata::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2cmarxdata::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2cmarxdata`]
module"]
pub type I2CMARXDATA = crate::Reg<i2cmarxdata::I2CMARXDATArs>;
#[doc = "I2C master receive data"]
pub mod i2cmarxdata {
#[doc = "Register `I2CMARXDATA` reader"]
pub type R = crate::R<I2CMARXDATArs>;
#[doc = "Register `I2CMARXDATA` writer"]
pub type W = crate::W<I2CMARXDATArs>;
#[doc = "Field `MARXDATA` reader - Master data byte received"]
pub type MARXDATA_R = crate::FieldReader;
#[doc = "Field `MARXDATA` writer - Master data byte received"]
pub type MARXDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "I2CMARXDATA full\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum I2CMARXDATAF {
#[doc = "0: I2CMARXDATA register empty"]
Empty = 0,
#[doc = "1: I2CMARXDATA register full, cleared on read"]
Full = 1,
}
impl From<I2CMARXDATAF> for bool {
#[inline(always)]
fn from(variant: I2CMARXDATAF) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `I2CMARXDATAF` reader - I2CMARXDATA full"]
pub type I2CMARXDATAF_R = crate::BitReader<I2CMARXDATAF>;
impl I2CMARXDATAF_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> I2CMARXDATAF {
match self.bits {
false => I2CMARXDATAF::Empty,
true => I2CMARXDATAF::Full,
}
}
#[doc = "I2CMARXDATA register empty"]
#[inline(always)]
pub fn is_empty(&self) -> bool {
*self == I2CMARXDATAF::Empty
}
#[doc = "I2CMARXDATA register full, cleared on read"]
#[inline(always)]
pub fn is_full(&self) -> bool {
*self == I2CMARXDATAF::Full
}
}
impl R {
#[doc = "Bits 0:7 - Master data byte received"]
#[inline(always)]
pub fn marxdata(&self) -> MARXDATA_R {
MARXDATA_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bit 8 - I2CMARXDATA full"]
#[inline(always)]
pub fn i2cmarxdataf(&self) -> I2CMARXDATAF_R {
I2CMARXDATAF_R::new(((self.bits >> 8) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2CMARXDATA")
.field("marxdata", &self.marxdata())
.field("i2cmarxdataf", &self.i2cmarxdataf())
.finish()
}
}
impl W {
#[doc = "Bits 0:7 - Master data byte received"]
#[inline(always)]
pub fn marxdata(&mut self) -> MARXDATA_W<I2CMARXDATArs> {
MARXDATA_W::new(self, 0)
}
}
#[doc = "I2C master receive data\n\nYou can [`read`](crate::Reg::read) this register and get [`i2cmarxdata::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2cmarxdata::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2CMARXDATArs;
impl crate::RegisterSpec for I2CMARXDATArs {
type Ux = u32;
}
#[doc = "`read()` method returns [`i2cmarxdata::R`](R) reader structure"]
impl crate::Readable for I2CMARXDATArs {}
#[doc = "`write(|w| ..)` method takes [`i2cmarxdata::W`](W) writer structure"]
impl crate::Writable for I2CMARXDATArs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets I2CMARXDATA to value 0"]
impl crate::Resettable for I2CMARXDATArs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "I2CMATXDATA (rw) register accessor: I2C master transmit data\n\nYou can [`read`](crate::Reg::read) this register and get [`i2cmatxdata::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2cmatxdata::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2cmatxdata`]
module"]
pub type I2CMATXDATA = crate::Reg<i2cmatxdata::I2CMATXDATArs>;
#[doc = "I2C master transmit data"]
pub mod i2cmatxdata {
#[doc = "Register `I2CMATXDATA` reader"]
pub type R = crate::R<I2CMATXDATArs>;
#[doc = "Register `I2CMATXDATA` writer"]
pub type W = crate::W<I2CMATXDATArs>;
#[doc = "Field `MATXDATA` reader - Master data byte to transmit"]
pub type MATXDATA_R = crate::FieldReader;
#[doc = "Field `MATXDATA` writer - Master data byte to transmit"]
pub type MATXDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "I2CMATXDATA full\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum I2CMATXDATAF {
#[doc = "0: I2CMATXDATA register empty"]
Empty = 0,
#[doc = "1: I2CMATXDATA register full, cleared on read"]
Full = 1,
}
impl From<I2CMATXDATAF> for bool {
#[inline(always)]
fn from(variant: I2CMATXDATAF) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `I2CMATXDATAF` reader - I2CMATXDATA full"]
pub type I2CMATXDATAF_R = crate::BitReader<I2CMATXDATAF>;
impl I2CMATXDATAF_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> I2CMATXDATAF {
match self.bits {
false => I2CMATXDATAF::Empty,
true => I2CMATXDATAF::Full,
}
}
#[doc = "I2CMATXDATA register empty"]
#[inline(always)]
pub fn is_empty(&self) -> bool {
*self == I2CMATXDATAF::Empty
}
#[doc = "I2CMATXDATA register full, cleared on read"]
#[inline(always)]
pub fn is_full(&self) -> bool {
*self == I2CMATXDATAF::Full
}
}
#[doc = "Last byte of transfer\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum LBYTE {
#[doc = "0: not last byte of transfer"]
False = 0,
#[doc = "1: last byte of READ or WRITE indicator, initiate STOP after data transfer"]
True = 1,
}
impl From<LBYTE> for bool {
#[inline(always)]
fn from(variant: LBYTE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `LBYTE` reader - Last byte of transfer"]
pub type LBYTE_R = crate::BitReader<LBYTE>;
impl LBYTE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> LBYTE {
match self.bits {
false => LBYTE::False,
true => LBYTE::True,
}
}
#[doc = "not last byte of transfer"]
#[inline(always)]
pub fn is_false(&self) -> bool {
*self == LBYTE::False
}
#[doc = "last byte of READ or WRITE indicator, initiate STOP after data transfer"]
#[inline(always)]
pub fn is_true(&self) -> bool {
*self == LBYTE::True
}
}
#[doc = "Field `LBYTE` writer - Last byte of transfer"]
pub type LBYTE_W<'a, REG> = crate::BitWriter<'a, REG, LBYTE>;
impl<'a, REG> LBYTE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "not last byte of transfer"]
#[inline(always)]
pub fn false_(self) -> &'a mut crate::W<REG> {
self.variant(LBYTE::False)
}
#[doc = "last byte of READ or WRITE indicator, initiate STOP after data transfer"]
#[inline(always)]
pub fn true_(self) -> &'a mut crate::W<REG> {
self.variant(LBYTE::True)
}
}
impl R {
#[doc = "Bits 0:7 - Master data byte to transmit"]
#[inline(always)]
pub fn matxdata(&self) -> MATXDATA_R {
MATXDATA_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bit 8 - I2CMATXDATA full"]
#[inline(always)]
pub fn i2cmatxdataf(&self) -> I2CMATXDATAF_R {
I2CMATXDATAF_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Last byte of transfer"]
#[inline(always)]
pub fn lbyte(&self) -> LBYTE_R {
LBYTE_R::new(((self.bits >> 9) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2CMATXDATA")
.field("matxdata", &self.matxdata())
.field("i2cmatxdataf", &self.i2cmatxdataf())
.field("lbyte", &self.lbyte())
.finish()
}
}
impl W {
#[doc = "Bits 0:7 - Master data byte to transmit"]
#[inline(always)]
pub fn matxdata(&mut self) -> MATXDATA_W<I2CMATXDATArs> {
MATXDATA_W::new(self, 0)
}
#[doc = "Bit 9 - Last byte of transfer"]
#[inline(always)]
pub fn lbyte(&mut self) -> LBYTE_W<I2CMATXDATArs> {
LBYTE_W::new(self, 9)
}
}
#[doc = "I2C master transmit data\n\nYou can [`read`](crate::Reg::read) this register and get [`i2cmatxdata::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2cmatxdata::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2CMATXDATArs;
impl crate::RegisterSpec for I2CMATXDATArs {
type Ux = u32;
}
#[doc = "`read()` method returns [`i2cmatxdata::R`](R) reader structure"]
impl crate::Readable for I2CMATXDATArs {}
#[doc = "`write(|w| ..)` method takes [`i2cmatxdata::W`](W) writer structure"]
impl crate::Writable for I2CMATXDATArs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets I2CMATXDATA to value 0"]
impl crate::Resettable for I2CMATXDATArs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "I2CBAUD (rw) register accessor: I2C baud rate\n\nYou can [`read`](crate::Reg::read) this register and get [`i2cbaud::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2cbaud::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2cbaud`]
module"]
pub type I2CBAUD = crate::Reg<i2cbaud::I2CBAUDrs>;
#[doc = "I2C baud rate"]
pub mod i2cbaud {
#[doc = "Register `I2CBAUD` reader"]
pub type R = crate::R<I2CBAUDrs>;
#[doc = "Register `I2CBAUD` writer"]
pub type W = crate::W<I2CBAUDrs>;
#[doc = "Field `SCLL` reader - Number of HCLK cycles for I2CCL low time"]
pub type SCLL_R = crate::FieldReader<u16>;
#[doc = "Field `SCLL` writer - Number of HCLK cycles for I2CCL low time"]
pub type SCLL_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
#[doc = "Field `SCLH` reader - Number of HCLK cycles for I2CCCL high time"]
pub type SCLH_R = crate::FieldReader<u16>;
#[doc = "Field `SCLH` writer - Number of HCLK cycles for I2CCCL high time"]
pub type SCLH_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
impl R {
#[doc = "Bits 0:10 - Number of HCLK cycles for I2CCL low time"]
#[inline(always)]
pub fn scll(&self) -> SCLL_R {
SCLL_R::new((self.bits & 0x07ff) as u16)
}
#[doc = "Bits 16:26 - Number of HCLK cycles for I2CCCL high time"]
#[inline(always)]
pub fn sclh(&self) -> SCLH_R {
SCLH_R::new(((self.bits >> 16) & 0x07ff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2CBAUD")
.field("scll", &self.scll())
.field("sclh", &self.sclh())
.finish()
}
}
impl W {
#[doc = "Bits 0:10 - Number of HCLK cycles for I2CCL low time"]
#[inline(always)]
pub fn scll(&mut self) -> SCLL_W<I2CBAUDrs> {
SCLL_W::new(self, 0)
}
#[doc = "Bits 16:26 - Number of HCLK cycles for I2CCCL high time"]
#[inline(always)]
pub fn sclh(&mut self) -> SCLH_W<I2CBAUDrs> {
SCLH_W::new(self, 16)
}
}
#[doc = "I2C baud rate\n\nYou can [`read`](crate::Reg::read) this register and get [`i2cbaud::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2cbaud::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2CBAUDrs;
impl crate::RegisterSpec for I2CBAUDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`i2cbaud::R`](R) reader structure"]
impl crate::Readable for I2CBAUDrs {}
#[doc = "`write(|w| ..)` method takes [`i2cbaud::W`](W) writer structure"]
impl crate::Writable for I2CBAUDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets I2CBAUD to value 0"]
impl crate::Resettable for I2CBAUDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "I2CSLRXDATA (rw) register accessor: I2C slave receive data\n\nYou can [`read`](crate::Reg::read) this register and get [`i2cslrxdata::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2cslrxdata::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2cslrxdata`]
module"]
pub type I2CSLRXDATA = crate::Reg<i2cslrxdata::I2CSLRXDATArs>;
#[doc = "I2C slave receive data"]
pub mod i2cslrxdata {
#[doc = "Register `I2CSLRXDATA` reader"]
pub type R = crate::R<I2CSLRXDATArs>;
#[doc = "Register `I2CSLRXDATA` writer"]
pub type W = crate::W<I2CSLRXDATArs>;
#[doc = "Field `SLRXDATA` reader - Slave data byte received"]
pub type SLRXDATA_R = crate::FieldReader;
#[doc = "Field `SLRXDATA` writer - Slave data byte received"]
pub type SLRXDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "I2CSLRXDATA full\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum I2CSLRXDATAF {
#[doc = "0: I2CSLRXDATA register empty"]
Empty = 0,
#[doc = "1: I2CSLRXDATA register full, data not transmitted"]
Full = 1,
}
impl From<I2CSLRXDATAF> for bool {
#[inline(always)]
fn from(variant: I2CSLRXDATAF) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `I2CSLRXDATAF` reader - I2CSLRXDATA full"]
pub type I2CSLRXDATAF_R = crate::BitReader<I2CSLRXDATAF>;
impl I2CSLRXDATAF_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> I2CSLRXDATAF {
match self.bits {
false => I2CSLRXDATAF::Empty,
true => I2CSLRXDATAF::Full,
}
}
#[doc = "I2CSLRXDATA register empty"]
#[inline(always)]
pub fn is_empty(&self) -> bool {
*self == I2CSLRXDATAF::Empty
}
#[doc = "I2CSLRXDATA register full, data not transmitted"]
#[inline(always)]
pub fn is_full(&self) -> bool {
*self == I2CSLRXDATAF::Full
}
}
impl R {
#[doc = "Bits 0:7 - Slave data byte received"]
#[inline(always)]
pub fn slrxdata(&self) -> SLRXDATA_R {
SLRXDATA_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bit 8 - I2CSLRXDATA full"]
#[inline(always)]
pub fn i2cslrxdataf(&self) -> I2CSLRXDATAF_R {
I2CSLRXDATAF_R::new(((self.bits >> 8) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2CSLRXDATA")
.field("slrxdata", &self.slrxdata())
.field("i2cslrxdataf", &self.i2cslrxdataf())
.finish()
}
}
impl W {
#[doc = "Bits 0:7 - Slave data byte received"]
#[inline(always)]
pub fn slrxdata(&mut self) -> SLRXDATA_W<I2CSLRXDATArs> {
SLRXDATA_W::new(self, 0)
}
}
#[doc = "I2C slave receive data\n\nYou can [`read`](crate::Reg::read) this register and get [`i2cslrxdata::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2cslrxdata::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2CSLRXDATArs;
impl crate::RegisterSpec for I2CSLRXDATArs {
type Ux = u32;
}
#[doc = "`read()` method returns [`i2cslrxdata::R`](R) reader structure"]
impl crate::Readable for I2CSLRXDATArs {}
#[doc = "`write(|w| ..)` method takes [`i2cslrxdata::W`](W) writer structure"]
impl crate::Writable for I2CSLRXDATArs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets I2CSLRXDATA to value 0"]
impl crate::Resettable for I2CSLRXDATArs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "I2CSLTXDATA (rw) register accessor: I2C slave receive data\n\nYou can [`read`](crate::Reg::read) this register and get [`i2csltxdata::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2csltxdata::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2csltxdata`]
module"]
pub type I2CSLTXDATA = crate::Reg<i2csltxdata::I2CSLTXDATArs>;
#[doc = "I2C slave receive data"]
pub mod i2csltxdata {
#[doc = "Register `I2CSLTXDATA` reader"]
pub type R = crate::R<I2CSLTXDATArs>;
#[doc = "Register `I2CSLTXDATA` writer"]
pub type W = crate::W<I2CSLTXDATArs>;
#[doc = "Field `SLTXDATA` reader - Slave data byte to transmit"]
pub type SLTXDATA_R = crate::FieldReader;
#[doc = "Field `SLTXDATA` writer - Slave data byte to transmit"]
pub type SLTXDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Slave ACK or NACK\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum NACK {
#[doc = "0: Issue ACK on I2C write"]
Ack = 0,
#[doc = "1: Issue NACK on I2C write"]
Nack = 1,
}
impl From<NACK> for bool {
#[inline(always)]
fn from(variant: NACK) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `NACK` reader - Slave ACK or NACK"]
pub type NACK_R = crate::BitReader<NACK>;
impl NACK_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> NACK {
match self.bits {
false => NACK::Ack,
true => NACK::Nack,
}
}
#[doc = "Issue ACK on I2C write"]
#[inline(always)]
pub fn is_ack(&self) -> bool {
*self == NACK::Ack
}
#[doc = "Issue NACK on I2C write"]
#[inline(always)]
pub fn is_nack(&self) -> bool {
*self == NACK::Nack
}
}
#[doc = "Field `NACK` writer - Slave ACK or NACK"]
pub type NACK_W<'a, REG> = crate::BitWriter<'a, REG, NACK>;
impl<'a, REG> NACK_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Issue ACK on I2C write"]
#[inline(always)]
pub fn ack(self) -> &'a mut crate::W<REG> {
self.variant(NACK::Ack)
}
#[doc = "Issue NACK on I2C write"]
#[inline(always)]
pub fn nack(self) -> &'a mut crate::W<REG> {
self.variant(NACK::Nack)
}
}
#[doc = "I2CSLTXDATA full\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum I2CSLTXDATAF {
#[doc = "0: I2CSLTXDATA register empty"]
Empty = 0,
#[doc = "1: I2CSLTXDATA register full, data not transmitted"]
Full = 1,
}
impl From<I2CSLTXDATAF> for bool {
#[inline(always)]
fn from(variant: I2CSLTXDATAF) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `I2CSLTXDATAF` reader - I2CSLTXDATA full"]
pub type I2CSLTXDATAF_R = crate::BitReader<I2CSLTXDATAF>;
impl I2CSLTXDATAF_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> I2CSLTXDATAF {
match self.bits {
false => I2CSLTXDATAF::Empty,
true => I2CSLTXDATAF::Full,
}
}
#[doc = "I2CSLTXDATA register empty"]
#[inline(always)]
pub fn is_empty(&self) -> bool {
*self == I2CSLTXDATAF::Empty
}
#[doc = "I2CSLTXDATA register full, data not transmitted"]
#[inline(always)]
pub fn is_full(&self) -> bool {
*self == I2CSLTXDATAF::Full
}
}
impl R {
#[doc = "Bits 0:7 - Slave data byte to transmit"]
#[inline(always)]
pub fn sltxdata(&self) -> SLTXDATA_R {
SLTXDATA_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bit 8 - Slave ACK or NACK"]
#[inline(always)]
pub fn nack(&self) -> NACK_R {
NACK_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - I2CSLTXDATA full"]
#[inline(always)]
pub fn i2csltxdataf(&self) -> I2CSLTXDATAF_R {
I2CSLTXDATAF_R::new(((self.bits >> 9) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2CSLTXDATA")
.field("sltxdata", &self.sltxdata())
.field("nack", &self.nack())
.field("i2csltxdataf", &self.i2csltxdataf())
.finish()
}
}
impl W {
#[doc = "Bits 0:7 - Slave data byte to transmit"]
#[inline(always)]
pub fn sltxdata(&mut self) -> SLTXDATA_W<I2CSLTXDATArs> {
SLTXDATA_W::new(self, 0)
}
#[doc = "Bit 8 - Slave ACK or NACK"]
#[inline(always)]
pub fn nack(&mut self) -> NACK_W<I2CSLTXDATArs> {
NACK_W::new(self, 8)
}
}
#[doc = "I2C slave receive data\n\nYou can [`read`](crate::Reg::read) this register and get [`i2csltxdata::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2csltxdata::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2CSLTXDATArs;
impl crate::RegisterSpec for I2CSLTXDATArs {
type Ux = u32;
}
#[doc = "`read()` method returns [`i2csltxdata::R`](R) reader structure"]
impl crate::Readable for I2CSLTXDATArs {}
#[doc = "`write(|w| ..)` method takes [`i2csltxdata::W`](W) writer structure"]
impl crate::Writable for I2CSLTXDATArs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets I2CSLTXDATA to value 0"]
impl crate::Resettable for I2CSLTXDATArs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "I2CSLADDR (rw) register accessor: I2C slave address\n\nYou can [`read`](crate::Reg::read) this register and get [`i2csladdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2csladdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2csladdr`]
module"]
pub type I2CSLADDR = crate::Reg<i2csladdr::I2CSLADDRrs>;
#[doc = "I2C slave address"]
pub mod i2csladdr {
#[doc = "Register `I2CSLADDR` reader"]
pub type R = crate::R<I2CSLADDRrs>;
#[doc = "Register `I2CSLADDR` writer"]
pub type W = crate::W<I2CSLADDRrs>;
#[doc = "Field `SLADDRL` reader - Lower slave address bits 6:0"]
pub type SLADDRL_R = crate::FieldReader;
#[doc = "Field `SLADDRL` writer - Lower slave address bits 6:0"]
pub type SLADDRL_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `SLADDRH` reader - Higher slave address bits9:7"]
pub type SLADDRH_R = crate::FieldReader;
#[doc = "Field `SLADDRH` writer - Higher slave address bits9:7"]
pub type SLADDRH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
impl R {
#[doc = "Bits 0:6 - Lower slave address bits 6:0"]
#[inline(always)]
pub fn sladdrl(&self) -> SLADDRL_R {
SLADDRL_R::new((self.bits & 0x7f) as u8)
}
#[doc = "Bits 7:9 - Higher slave address bits9:7"]
#[inline(always)]
pub fn sladdrh(&self) -> SLADDRH_R {
SLADDRH_R::new(((self.bits >> 7) & 7) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2CSLADDR")
.field("sladdrl", &self.sladdrl())
.field("sladdrh", &self.sladdrh())
.finish()
}
}
impl W {
#[doc = "Bits 0:6 - Lower slave address bits 6:0"]
#[inline(always)]
pub fn sladdrl(&mut self) -> SLADDRL_W<I2CSLADDRrs> {
SLADDRL_W::new(self, 0)
}
#[doc = "Bits 7:9 - Higher slave address bits9:7"]
#[inline(always)]
pub fn sladdrh(&mut self) -> SLADDRH_W<I2CSLADDRrs> {
SLADDRH_W::new(self, 7)
}
}
#[doc = "I2C slave address\n\nYou can [`read`](crate::Reg::read) this register and get [`i2csladdr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2csladdr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2CSLADDRrs;
impl crate::RegisterSpec for I2CSLADDRrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`i2csladdr::R`](R) reader structure"]
impl crate::Readable for I2CSLADDRrs {}
#[doc = "`write(|w| ..)` method takes [`i2csladdr::W`](W) writer structure"]
impl crate::Writable for I2CSLADDRrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets I2CSLADDR to value 0"]
impl crate::Resettable for I2CSLADDRrs {
const RESET_VALUE: u32 = 0;
}
}
}
#[doc = "UART"]
pub struct UART {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for UART {}
impl UART {
#[doc = r"Pointer to the register block"]
pub const PTR: *const uart::RegisterBlock = 0x401d_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const uart::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for UART {
type Target = uart::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for UART {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UART").finish()
}
}
#[doc = "UART"]
pub mod uart {
#[repr(C)]
#[derive(Debug)]
#[doc = "Register block"]
pub struct RegisterBlock {
uartrxtx: UARTRXTX,
uartien: UARTIEN,
uartii: UARTII,
uartlc: UARTLC,
_reserved4: [u8; 0x04],
uartls: UARTLS,
_reserved5: [u8; 0x08],
uartfctl: UARTFCTL,
uartie_r: UARTIE_R,
uartdl_l: UARTDL_L,
uartdl_h: UARTDL_H,
_reserved9: [u8; 0x08],
uartfd_f: UARTFD_F,
_reserved10: [u8; 0x04],
uartfstat: UARTFSTAT,
}
impl RegisterBlock {
#[doc = "0x00 - UART receive/transmit FIFO"]
#[inline(always)]
pub const fn uartrxtx(&self) -> &UARTRXTX {
&self.uartrxtx
}
#[doc = "0x04 - UART interrupt enable"]
#[inline(always)]
pub const fn uartien(&self) -> &UARTIEN {
&self.uartien
}
#[doc = "0x08 - UART interrupt identification"]
#[inline(always)]
pub const fn uartii(&self) -> &UARTII {
&self.uartii
}
#[doc = "0x0c - UART Line Control"]
#[inline(always)]
pub const fn uartlc(&self) -> &UARTLC {
&self.uartlc
}
#[doc = "0x14 - UART Line Status"]
#[inline(always)]
pub const fn uartls(&self) -> &UARTLS {
&self.uartls
}
#[doc = "0x20 - FIFO control"]
#[inline(always)]
pub const fn uartfctl(&self) -> &UARTFCTL {
&self.uartfctl
}
#[doc = "0x24 - UART interrupt enable remapped"]
#[inline(always)]
pub const fn uartie_r(&self) -> &UARTIE_R {
&self.uartie_r
}
#[doc = "0x28 - UART divisor latch low byte"]
#[inline(always)]
pub const fn uartdl_l(&self) -> &UARTDL_L {
&self.uartdl_l
}
#[doc = "0x2c - UART divisor latch high byte"]
#[inline(always)]
pub const fn uartdl_h(&self) -> &UARTDL_H {
&self.uartdl_h
}
#[doc = "0x38 - UART fractional divisor value"]
#[inline(always)]
pub const fn uartfd_f(&self) -> &UARTFD_F {
&self.uartfd_f
}
#[doc = "0x40 - UART FIFO status"]
#[inline(always)]
pub const fn uartfstat(&self) -> &UARTFSTAT {
&self.uartfstat
}
}
#[doc = "UARTRXTX (rw) register accessor: UART receive/transmit FIFO\n\nYou can [`read`](crate::Reg::read) this register and get [`uartrxtx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartrxtx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uartrxtx`]
module"]
pub type UARTRXTX = crate::Reg<uartrxtx::UARTRXTXrs>;
#[doc = "UART receive/transmit FIFO"]
pub mod uartrxtx {
#[doc = "Register `UARTRXTX` reader"]
pub type R = crate::R<UARTRXTXrs>;
#[doc = "Register `UARTRXTX` writer"]
pub type W = crate::W<UARTRXTXrs>;
#[doc = "Field `RXTX` reader - Receive and Transmit FIFO buffer (read: RX FIFO, write: TX FIFO)"]
pub type RXTX_R = crate::FieldReader;
#[doc = "Field `RXTX` writer - Receive and Transmit FIFO buffer (read: RX FIFO, write: TX FIFO)"]
pub type RXTX_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Receive and Transmit FIFO buffer (read: RX FIFO, write: TX FIFO)"]
#[inline(always)]
pub fn rxtx(&self) -> RXTX_R {
RXTX_R::new((self.bits & 0xff) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UARTRXTX")
.field("rxtx", &self.rxtx())
.finish()
}
}
impl W {
#[doc = "Bits 0:7 - Receive and Transmit FIFO buffer (read: RX FIFO, write: TX FIFO)"]
#[inline(always)]
pub fn rxtx(&mut self) -> RXTX_W<UARTRXTXrs> {
RXTX_W::new(self, 0)
}
}
#[doc = "UART receive/transmit FIFO\n\nYou can [`read`](crate::Reg::read) this register and get [`uartrxtx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartrxtx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct UARTRXTXrs;
impl crate::RegisterSpec for UARTRXTXrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`uartrxtx::R`](R) reader structure"]
impl crate::Readable for UARTRXTXrs {}
#[doc = "`write(|w| ..)` method takes [`uartrxtx::W`](W) writer structure"]
impl crate::Writable for UARTRXTXrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets UARTRXTX to value 0"]
impl crate::Resettable for UARTRXTXrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "UARTIEN (rw) register accessor: UART interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`uartien::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartien::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uartien`]
module"]
pub type UARTIEN = crate::Reg<uartien::UARTIENrs>;
#[doc = "UART interrupt enable"]
pub mod uartien {
#[doc = "Register `UARTIEN` reader"]
pub type R = crate::R<UARTIENrs>;
#[doc = "Register `UARTIEN` writer"]
pub type W = crate::W<UARTIENrs>;
#[doc = "RX register data available interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RXINTEN {
#[doc = "0: disable interrupt"]
Disable = 0,
#[doc = "1: enable interrupt"]
Enable = 1,
}
impl From<RXINTEN> for bool {
#[inline(always)]
fn from(variant: RXINTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RXINTEN` reader - RX register data available interrupt enable"]
pub type RXINTEN_R = crate::BitReader<RXINTEN>;
impl RXINTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RXINTEN {
match self.bits {
false => RXINTEN::Disable,
true => RXINTEN::Enable,
}
}
#[doc = "disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == RXINTEN::Disable
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == RXINTEN::Enable
}
}
#[doc = "Field `RXINTEN` writer - RX register data available interrupt enable"]
pub type RXINTEN_W<'a, REG> = crate::BitWriter<'a, REG, RXINTEN>;
impl<'a, REG> RXINTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(RXINTEN::Disable)
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(RXINTEN::Enable)
}
}
#[doc = "TX register data available interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TXINTEN {
#[doc = "0: disable interrupt"]
Disable = 0,
#[doc = "1: enable interrupt"]
Enable = 1,
}
impl From<TXINTEN> for bool {
#[inline(always)]
fn from(variant: TXINTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TXINTEN` reader - TX register data available interrupt enable"]
pub type TXINTEN_R = crate::BitReader<TXINTEN>;
impl TXINTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> TXINTEN {
match self.bits {
false => TXINTEN::Disable,
true => TXINTEN::Enable,
}
}
#[doc = "disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == TXINTEN::Disable
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == TXINTEN::Enable
}
}
#[doc = "Field `TXINTEN` writer - TX register data available interrupt enable"]
pub type TXINTEN_W<'a, REG> = crate::BitWriter<'a, REG, TXINTEN>;
impl<'a, REG> TXINTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(TXINTEN::Disable)
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(TXINTEN::Enable)
}
}
#[doc = "Receive interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RSINTEN {
#[doc = "0: disable interrupt"]
Disable = 0,
#[doc = "1: enable interrupt"]
Enable = 1,
}
impl From<RSINTEN> for bool {
#[inline(always)]
fn from(variant: RSINTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RSINTEN` reader - Receive interrupt enable"]
pub type RSINTEN_R = crate::BitReader<RSINTEN>;
impl RSINTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RSINTEN {
match self.bits {
false => RSINTEN::Disable,
true => RSINTEN::Enable,
}
}
#[doc = "disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == RSINTEN::Disable
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == RSINTEN::Enable
}
}
#[doc = "Field `RSINTEN` writer - Receive interrupt enable"]
pub type RSINTEN_W<'a, REG> = crate::BitWriter<'a, REG, RSINTEN>;
impl<'a, REG> RSINTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(RSINTEN::Disable)
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(RSINTEN::Enable)
}
}
#[doc = "Model Status interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MSINTEN {
#[doc = "0: disable interrupt"]
Disable = 0,
#[doc = "1: enable interrupt"]
Enable = 1,
}
impl From<MSINTEN> for bool {
#[inline(always)]
fn from(variant: MSINTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MSINTEN` reader - Model Status interrupt enable"]
pub type MSINTEN_R = crate::BitReader<MSINTEN>;
impl MSINTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MSINTEN {
match self.bits {
false => MSINTEN::Disable,
true => MSINTEN::Enable,
}
}
#[doc = "disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == MSINTEN::Disable
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == MSINTEN::Enable
}
}
#[doc = "Field `MSINTEN` writer - Model Status interrupt enable"]
pub type MSINTEN_W<'a, REG> = crate::BitWriter<'a, REG, MSINTEN>;
impl<'a, REG> MSINTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(MSINTEN::Disable)
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(MSINTEN::Enable)
}
}
impl R {
#[doc = "Bit 0 - RX register data available interrupt enable"]
#[inline(always)]
pub fn rxinten(&self) -> RXINTEN_R {
RXINTEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - TX register data available interrupt enable"]
#[inline(always)]
pub fn txinten(&self) -> TXINTEN_R {
TXINTEN_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Receive interrupt enable"]
#[inline(always)]
pub fn rsinten(&self) -> RSINTEN_R {
RSINTEN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Model Status interrupt enable"]
#[inline(always)]
pub fn msinten(&self) -> MSINTEN_R {
MSINTEN_R::new(((self.bits >> 3) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UARTIEN")
.field("rxinten", &self.rxinten())
.field("txinten", &self.txinten())
.field("rsinten", &self.rsinten())
.field("msinten", &self.msinten())
.finish()
}
}
impl W {
#[doc = "Bit 0 - RX register data available interrupt enable"]
#[inline(always)]
pub fn rxinten(&mut self) -> RXINTEN_W<UARTIENrs> {
RXINTEN_W::new(self, 0)
}
#[doc = "Bit 1 - TX register data available interrupt enable"]
#[inline(always)]
pub fn txinten(&mut self) -> TXINTEN_W<UARTIENrs> {
TXINTEN_W::new(self, 1)
}
#[doc = "Bit 2 - Receive interrupt enable"]
#[inline(always)]
pub fn rsinten(&mut self) -> RSINTEN_W<UARTIENrs> {
RSINTEN_W::new(self, 2)
}
#[doc = "Bit 3 - Model Status interrupt enable"]
#[inline(always)]
pub fn msinten(&mut self) -> MSINTEN_W<UARTIENrs> {
MSINTEN_W::new(self, 3)
}
}
#[doc = "UART interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`uartien::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartien::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct UARTIENrs;
impl crate::RegisterSpec for UARTIENrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`uartien::R`](R) reader structure"]
impl crate::Readable for UARTIENrs {}
#[doc = "`write(|w| ..)` method takes [`uartien::W`](W) writer structure"]
impl crate::Writable for UARTIENrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets UARTIEN to value 0"]
impl crate::Resettable for UARTIENrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "UARTII (rw) register accessor: UART interrupt identification\n\nYou can [`read`](crate::Reg::read) this register and get [`uartii::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartii::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uartii`]
module"]
pub type UARTII = crate::Reg<uartii::UARTIIrs>;
#[doc = "UART interrupt identification"]
pub mod uartii {
#[doc = "Register `UARTII` reader"]
pub type R = crate::R<UARTIIrs>;
#[doc = "Register `UARTII` writer"]
pub type W = crate::W<UARTIIrs>;
#[doc = "UART interrupt\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum UARTINT {
#[doc = "0: disable interrupt"]
Disable = 0,
#[doc = "1: enable interrupt"]
Enable = 1,
}
impl From<UARTINT> for bool {
#[inline(always)]
fn from(variant: UARTINT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `UARTINT` reader - UART interrupt"]
pub type UARTINT_R = crate::BitReader<UARTINT>;
impl UARTINT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> UARTINT {
match self.bits {
false => UARTINT::Disable,
true => UARTINT::Enable,
}
}
#[doc = "disable interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == UARTINT::Disable
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == UARTINT::Enable
}
}
#[doc = "Field `UARTINT` writer - UART interrupt"]
pub type UARTINT_W<'a, REG> = crate::BitWriter<'a, REG, UARTINT>;
impl<'a, REG> UARTINT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(UARTINT::Disable)
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(UARTINT::Enable)
}
}
#[doc = "UART interrupt type\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum UARTINTID {
#[doc = "0: modem status"]
ModemStatus = 0,
#[doc = "1: TX hold register empty"]
TxHoldRegEmpty = 1,
#[doc = "2: RX data available"]
RxDataAvailable = 2,
#[doc = "3: RX line status"]
RxLineStatus = 3,
#[doc = "4: Timeout"]
Timeout = 4,
}
impl From<UARTINTID> for u8 {
#[inline(always)]
fn from(variant: UARTINTID) -> Self {
variant as _
}
}
impl crate::FieldSpec for UARTINTID {
type Ux = u8;
}
impl crate::IsEnum for UARTINTID {}
#[doc = "Field `UARTINTID` reader - UART interrupt type"]
pub type UARTINTID_R = crate::FieldReader<UARTINTID>;
impl UARTINTID_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<UARTINTID> {
match self.bits {
0 => Some(UARTINTID::ModemStatus),
1 => Some(UARTINTID::TxHoldRegEmpty),
2 => Some(UARTINTID::RxDataAvailable),
3 => Some(UARTINTID::RxLineStatus),
4 => Some(UARTINTID::Timeout),
_ => None,
}
}
#[doc = "modem status"]
#[inline(always)]
pub fn is_modem_status(&self) -> bool {
*self == UARTINTID::ModemStatus
}
#[doc = "TX hold register empty"]
#[inline(always)]
pub fn is_tx_hold_reg_empty(&self) -> bool {
*self == UARTINTID::TxHoldRegEmpty
}
#[doc = "RX data available"]
#[inline(always)]
pub fn is_rx_data_available(&self) -> bool {
*self == UARTINTID::RxDataAvailable
}
#[doc = "RX line status"]
#[inline(always)]
pub fn is_rx_line_status(&self) -> bool {
*self == UARTINTID::RxLineStatus
}
#[doc = "Timeout"]
#[inline(always)]
pub fn is_timeout(&self) -> bool {
*self == UARTINTID::Timeout
}
}
#[doc = "Field `UARTINTID` writer - UART interrupt type"]
pub type UARTINTID_W<'a, REG> = crate::FieldWriter<'a, REG, 3, UARTINTID>;
impl<'a, REG> UARTINTID_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "modem status"]
#[inline(always)]
pub fn modem_status(self) -> &'a mut crate::W<REG> {
self.variant(UARTINTID::ModemStatus)
}
#[doc = "TX hold register empty"]
#[inline(always)]
pub fn tx_hold_reg_empty(self) -> &'a mut crate::W<REG> {
self.variant(UARTINTID::TxHoldRegEmpty)
}
#[doc = "RX data available"]
#[inline(always)]
pub fn rx_data_available(self) -> &'a mut crate::W<REG> {
self.variant(UARTINTID::RxDataAvailable)
}
#[doc = "RX line status"]
#[inline(always)]
pub fn rx_line_status(self) -> &'a mut crate::W<REG> {
self.variant(UARTINTID::RxLineStatus)
}
#[doc = "Timeout"]
#[inline(always)]
pub fn timeout(self) -> &'a mut crate::W<REG> {
self.variant(UARTINTID::Timeout)
}
}
impl R {
#[doc = "Bit 0 - UART interrupt"]
#[inline(always)]
pub fn uartint(&self) -> UARTINT_R {
UARTINT_R::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:3 - UART interrupt type"]
#[inline(always)]
pub fn uartintid(&self) -> UARTINTID_R {
UARTINTID_R::new(((self.bits >> 1) & 7) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UARTII")
.field("uartint", &self.uartint())
.field("uartintid", &self.uartintid())
.finish()
}
}
impl W {
#[doc = "Bit 0 - UART interrupt"]
#[inline(always)]
pub fn uartint(&mut self) -> UARTINT_W<UARTIIrs> {
UARTINT_W::new(self, 0)
}
#[doc = "Bits 1:3 - UART interrupt type"]
#[inline(always)]
pub fn uartintid(&mut self) -> UARTINTID_W<UARTIIrs> {
UARTINTID_W::new(self, 1)
}
}
#[doc = "UART interrupt identification\n\nYou can [`read`](crate::Reg::read) this register and get [`uartii::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartii::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct UARTIIrs;
impl crate::RegisterSpec for UARTIIrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`uartii::R`](R) reader structure"]
impl crate::Readable for UARTIIrs {}
#[doc = "`write(|w| ..)` method takes [`uartii::W`](W) writer structure"]
impl crate::Writable for UARTIIrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets UARTII to value 0x01"]
impl crate::Resettable for UARTIIrs {
const RESET_VALUE: u32 = 0x01;
}
}
#[doc = "UARTLC (rw) register accessor: UART Line Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uartlc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartlc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uartlc`]
module"]
pub type UARTLC = crate::Reg<uartlc::UARTLCrs>;
#[doc = "UART Line Control"]
pub mod uartlc {
#[doc = "Register `UARTLC` reader"]
pub type R = crate::R<UARTLCrs>;
#[doc = "Register `UARTLC` writer"]
pub type W = crate::W<UARTLCrs>;
#[doc = "Bit per character\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum BPC {
#[doc = "0: 5 bits"]
_5 = 0,
#[doc = "1: 6 bits"]
_6 = 1,
#[doc = "2: 7 bits"]
_7 = 2,
#[doc = "3: 8 bits"]
_8 = 3,
}
impl From<BPC> for u8 {
#[inline(always)]
fn from(variant: BPC) -> Self {
variant as _
}
}
impl crate::FieldSpec for BPC {
type Ux = u8;
}
impl crate::IsEnum for BPC {}
#[doc = "Field `BPC` reader - Bit per character"]
pub type BPC_R = crate::FieldReader<BPC>;
impl BPC_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> BPC {
match self.bits {
0 => BPC::_5,
1 => BPC::_6,
2 => BPC::_7,
3 => BPC::_8,
_ => unreachable!(),
}
}
#[doc = "5 bits"]
#[inline(always)]
pub fn is_5(&self) -> bool {
*self == BPC::_5
}
#[doc = "6 bits"]
#[inline(always)]
pub fn is_6(&self) -> bool {
*self == BPC::_6
}
#[doc = "7 bits"]
#[inline(always)]
pub fn is_7(&self) -> bool {
*self == BPC::_7
}
#[doc = "8 bits"]
#[inline(always)]
pub fn is_8(&self) -> bool {
*self == BPC::_8
}
}
#[doc = "Field `BPC` writer - Bit per character"]
pub type BPC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, BPC, crate::Safe>;
impl<'a, REG> BPC_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "5 bits"]
#[inline(always)]
pub fn _5(self) -> &'a mut crate::W<REG> {
self.variant(BPC::_5)
}
#[doc = "6 bits"]
#[inline(always)]
pub fn _6(self) -> &'a mut crate::W<REG> {
self.variant(BPC::_6)
}
#[doc = "7 bits"]
#[inline(always)]
pub fn _7(self) -> &'a mut crate::W<REG> {
self.variant(BPC::_7)
}
#[doc = "8 bits"]
#[inline(always)]
pub fn _8(self) -> &'a mut crate::W<REG> {
self.variant(BPC::_8)
}
}
#[doc = "Stop bits\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum STB {
#[doc = "0: 1 stop bit"]
_1 = 0,
#[doc = "1: 2 stop bits (1.5 if BPC=00b)"]
_2 = 1,
}
impl From<STB> for bool {
#[inline(always)]
fn from(variant: STB) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `STB` reader - Stop bits"]
pub type STB_R = crate::BitReader<STB>;
impl STB_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> STB {
match self.bits {
false => STB::_1,
true => STB::_2,
}
}
#[doc = "1 stop bit"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == STB::_1
}
#[doc = "2 stop bits (1.5 if BPC=00b)"]
#[inline(always)]
pub fn is_2(&self) -> bool {
*self == STB::_2
}
}
#[doc = "Field `STB` writer - Stop bits"]
pub type STB_W<'a, REG> = crate::BitWriter<'a, REG, STB>;
impl<'a, REG> STB_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "1 stop bit"]
#[inline(always)]
pub fn _1(self) -> &'a mut crate::W<REG> {
self.variant(STB::_1)
}
#[doc = "2 stop bits (1.5 if BPC=00b)"]
#[inline(always)]
pub fn _2(self) -> &'a mut crate::W<REG> {
self.variant(STB::_2)
}
}
#[doc = "Parity enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum PEN {
#[doc = "0: parity disabled"]
Disabled = 0,
#[doc = "1: parity enabled"]
Enabled = 1,
}
impl From<PEN> for bool {
#[inline(always)]
fn from(variant: PEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `PEN` reader - Parity enable"]
pub type PEN_R = crate::BitReader<PEN>;
impl PEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> PEN {
match self.bits {
false => PEN::Disabled,
true => PEN::Enabled,
}
}
#[doc = "parity disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == PEN::Disabled
}
#[doc = "parity enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == PEN::Enabled
}
}
#[doc = "Field `PEN` writer - Parity enable"]
pub type PEN_W<'a, REG> = crate::BitWriter<'a, REG, PEN>;
impl<'a, REG> PEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "parity disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(PEN::Disabled)
}
#[doc = "parity enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(PEN::Enabled)
}
}
#[doc = "Parity type\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum EPS {
#[doc = "0: generate ODD parity"]
Odd = 0,
#[doc = "1: generate EVEN parity"]
Even = 1,
}
impl From<EPS> for bool {
#[inline(always)]
fn from(variant: EPS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `EPS` reader - Parity type"]
pub type EPS_R = crate::BitReader<EPS>;
impl EPS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> EPS {
match self.bits {
false => EPS::Odd,
true => EPS::Even,
}
}
#[doc = "generate ODD parity"]
#[inline(always)]
pub fn is_odd(&self) -> bool {
*self == EPS::Odd
}
#[doc = "generate EVEN parity"]
#[inline(always)]
pub fn is_even(&self) -> bool {
*self == EPS::Even
}
}
#[doc = "Field `EPS` writer - Parity type"]
pub type EPS_W<'a, REG> = crate::BitWriter<'a, REG, EPS>;
impl<'a, REG> EPS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "generate ODD parity"]
#[inline(always)]
pub fn odd(self) -> &'a mut crate::W<REG> {
self.variant(EPS::Odd)
}
#[doc = "generate EVEN parity"]
#[inline(always)]
pub fn even(self) -> &'a mut crate::W<REG> {
self.variant(EPS::Even)
}
}
#[doc = "Stick parity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SP {
#[doc = "0: disable"]
Disable = 0,
#[doc = "1: enable"]
Enable = 1,
}
impl From<SP> for bool {
#[inline(always)]
fn from(variant: SP) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SP` reader - Stick parity"]
pub type SP_R = crate::BitReader<SP>;
impl SP_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SP {
match self.bits {
false => SP::Disable,
true => SP::Enable,
}
}
#[doc = "disable"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == SP::Disable
}
#[doc = "enable"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == SP::Enable
}
}
#[doc = "Field `SP` writer - Stick parity"]
pub type SP_W<'a, REG> = crate::BitWriter<'a, REG, SP>;
impl<'a, REG> SP_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(SP::Disable)
}
#[doc = "enable"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(SP::Enable)
}
}
#[doc = "Break control\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SB {
#[doc = "0: normal operation"]
Normal = 0,
#[doc = "1: force TX to 0"]
_0 = 1,
}
impl From<SB> for bool {
#[inline(always)]
fn from(variant: SB) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SB` reader - Break control"]
pub type SB_R = crate::BitReader<SB>;
impl SB_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SB {
match self.bits {
false => SB::Normal,
true => SB::_0,
}
}
#[doc = "normal operation"]
#[inline(always)]
pub fn is_normal(&self) -> bool {
*self == SB::Normal
}
#[doc = "force TX to 0"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == SB::_0
}
}
#[doc = "Field `SB` writer - Break control"]
pub type SB_W<'a, REG> = crate::BitWriter<'a, REG, SB>;
impl<'a, REG> SB_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "normal operation"]
#[inline(always)]
pub fn normal(self) -> &'a mut crate::W<REG> {
self.variant(SB::Normal)
}
#[doc = "force TX to 0"]
#[inline(always)]
pub fn _0(self) -> &'a mut crate::W<REG> {
self.variant(SB::_0)
}
}
impl R {
#[doc = "Bits 0:1 - Bit per character"]
#[inline(always)]
pub fn bpc(&self) -> BPC_R {
BPC_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - Stop bits"]
#[inline(always)]
pub fn stb(&self) -> STB_R {
STB_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Parity enable"]
#[inline(always)]
pub fn pen(&self) -> PEN_R {
PEN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Parity type"]
#[inline(always)]
pub fn eps(&self) -> EPS_R {
EPS_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Stick parity"]
#[inline(always)]
pub fn sp(&self) -> SP_R {
SP_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Break control"]
#[inline(always)]
pub fn sb(&self) -> SB_R {
SB_R::new(((self.bits >> 6) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UARTLC")
.field("bpc", &self.bpc())
.field("stb", &self.stb())
.field("pen", &self.pen())
.field("eps", &self.eps())
.field("sp", &self.sp())
.field("sb", &self.sb())
.finish()
}
}
impl W {
#[doc = "Bits 0:1 - Bit per character"]
#[inline(always)]
pub fn bpc(&mut self) -> BPC_W<UARTLCrs> {
BPC_W::new(self, 0)
}
#[doc = "Bit 2 - Stop bits"]
#[inline(always)]
pub fn stb(&mut self) -> STB_W<UARTLCrs> {
STB_W::new(self, 2)
}
#[doc = "Bit 3 - Parity enable"]
#[inline(always)]
pub fn pen(&mut self) -> PEN_W<UARTLCrs> {
PEN_W::new(self, 3)
}
#[doc = "Bit 4 - Parity type"]
#[inline(always)]
pub fn eps(&mut self) -> EPS_W<UARTLCrs> {
EPS_W::new(self, 4)
}
#[doc = "Bit 5 - Stick parity"]
#[inline(always)]
pub fn sp(&mut self) -> SP_W<UARTLCrs> {
SP_W::new(self, 5)
}
#[doc = "Bit 6 - Break control"]
#[inline(always)]
pub fn sb(&mut self) -> SB_W<UARTLCrs> {
SB_W::new(self, 6)
}
}
#[doc = "UART Line Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uartlc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartlc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct UARTLCrs;
impl crate::RegisterSpec for UARTLCrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`uartlc::R`](R) reader structure"]
impl crate::Readable for UARTLCrs {}
#[doc = "`write(|w| ..)` method takes [`uartlc::W`](W) writer structure"]
impl crate::Writable for UARTLCrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets UARTLC to value 0"]
impl crate::Resettable for UARTLCrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "UARTLS (rw) register accessor: UART Line Status\n\nYou can [`read`](crate::Reg::read) this register and get [`uartls::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartls::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uartls`]
module"]
pub type UARTLS = crate::Reg<uartls::UARTLSrs>;
#[doc = "UART Line Status"]
pub mod uartls {
#[doc = "Register `UARTLS` reader"]
pub type R = crate::R<UARTLSrs>;
#[doc = "Register `UARTLS` writer"]
pub type W = crate::W<UARTLSrs>;
#[doc = "RX data ready\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RXDR {
#[doc = "0: RX FIFO empty"]
Empty = 0,
#[doc = "1: At least one entry in RX FIFO"]
NotEmpty = 1,
}
impl From<RXDR> for bool {
#[inline(always)]
fn from(variant: RXDR) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RXDR` reader - RX data ready"]
pub type RXDR_R = crate::BitReader<RXDR>;
impl RXDR_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RXDR {
match self.bits {
false => RXDR::Empty,
true => RXDR::NotEmpty,
}
}
#[doc = "RX FIFO empty"]
#[inline(always)]
pub fn is_empty(&self) -> bool {
*self == RXDR::Empty
}
#[doc = "At least one entry in RX FIFO"]
#[inline(always)]
pub fn is_not_empty(&self) -> bool {
*self == RXDR::NotEmpty
}
}
#[doc = "Field `RXDR` writer - RX data ready"]
pub type RXDR_W<'a, REG> = crate::BitWriter<'a, REG, RXDR>;
impl<'a, REG> RXDR_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "RX FIFO empty"]
#[inline(always)]
pub fn empty(self) -> &'a mut crate::W<REG> {
self.variant(RXDR::Empty)
}
#[doc = "At least one entry in RX FIFO"]
#[inline(always)]
pub fn not_empty(self) -> &'a mut crate::W<REG> {
self.variant(RXDR::NotEmpty)
}
}
#[doc = "RX overrun error\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RXOE {
#[doc = "0: error cleared"]
Cleared = 0,
#[doc = "1: RX FIFO full and last entry overwritten, cleared on read"]
Full = 1,
}
impl From<RXOE> for bool {
#[inline(always)]
fn from(variant: RXOE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RXOE` reader - RX overrun error"]
pub type RXOE_R = crate::BitReader<RXOE>;
impl RXOE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RXOE {
match self.bits {
false => RXOE::Cleared,
true => RXOE::Full,
}
}
#[doc = "error cleared"]
#[inline(always)]
pub fn is_cleared(&self) -> bool {
*self == RXOE::Cleared
}
#[doc = "RX FIFO full and last entry overwritten, cleared on read"]
#[inline(always)]
pub fn is_full(&self) -> bool {
*self == RXOE::Full
}
}
#[doc = "Field `RXOE` writer - RX overrun error"]
pub type RXOE_W<'a, REG> = crate::BitWriter<'a, REG, RXOE>;
impl<'a, REG> RXOE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "error cleared"]
#[inline(always)]
pub fn cleared(self) -> &'a mut crate::W<REG> {
self.variant(RXOE::Cleared)
}
#[doc = "RX FIFO full and last entry overwritten, cleared on read"]
#[inline(always)]
pub fn full(self) -> &'a mut crate::W<REG> {
self.variant(RXOE::Full)
}
}
#[doc = "RX parity error\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RXPE {
#[doc = "0: error cleared"]
Cleared = 0,
#[doc = "1: entry on top of RX FIFO has parity error, cleared on read"]
Error = 1,
}
impl From<RXPE> for bool {
#[inline(always)]
fn from(variant: RXPE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RXPE` reader - RX parity error"]
pub type RXPE_R = crate::BitReader<RXPE>;
impl RXPE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RXPE {
match self.bits {
false => RXPE::Cleared,
true => RXPE::Error,
}
}
#[doc = "error cleared"]
#[inline(always)]
pub fn is_cleared(&self) -> bool {
*self == RXPE::Cleared
}
#[doc = "entry on top of RX FIFO has parity error, cleared on read"]
#[inline(always)]
pub fn is_error(&self) -> bool {
*self == RXPE::Error
}
}
#[doc = "Field `RXPE` writer - RX parity error"]
pub type RXPE_W<'a, REG> = crate::BitWriter<'a, REG, RXPE>;
impl<'a, REG> RXPE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "error cleared"]
#[inline(always)]
pub fn cleared(self) -> &'a mut crate::W<REG> {
self.variant(RXPE::Cleared)
}
#[doc = "entry on top of RX FIFO has parity error, cleared on read"]
#[inline(always)]
pub fn error(self) -> &'a mut crate::W<REG> {
self.variant(RXPE::Error)
}
}
#[doc = "RX framing error\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RXFE {
#[doc = "0: error cleared"]
Cleared = 0,
#[doc = "1: entry on top of RX FIFO has framing error, cleared on read"]
Error = 1,
}
impl From<RXFE> for bool {
#[inline(always)]
fn from(variant: RXFE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RXFE` reader - RX framing error"]
pub type RXFE_R = crate::BitReader<RXFE>;
impl RXFE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RXFE {
match self.bits {
false => RXFE::Cleared,
true => RXFE::Error,
}
}
#[doc = "error cleared"]
#[inline(always)]
pub fn is_cleared(&self) -> bool {
*self == RXFE::Cleared
}
#[doc = "entry on top of RX FIFO has framing error, cleared on read"]
#[inline(always)]
pub fn is_error(&self) -> bool {
*self == RXFE::Error
}
}
#[doc = "Field `RXFE` writer - RX framing error"]
pub type RXFE_W<'a, REG> = crate::BitWriter<'a, REG, RXFE>;
impl<'a, REG> RXFE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "error cleared"]
#[inline(always)]
pub fn cleared(self) -> &'a mut crate::W<REG> {
self.variant(RXFE::Cleared)
}
#[doc = "entry on top of RX FIFO has framing error, cleared on read"]
#[inline(always)]
pub fn error(self) -> &'a mut crate::W<REG> {
self.variant(RXFE::Error)
}
}
#[doc = "RX break error\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RXBE {
#[doc = "0: error cleared"]
Cleared = 0,
#[doc = "1: entry on top of RX FIFO has break error, cleared on read"]
Error = 1,
}
impl From<RXBE> for bool {
#[inline(always)]
fn from(variant: RXBE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RXBE` reader - RX break error"]
pub type RXBE_R = crate::BitReader<RXBE>;
impl RXBE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RXBE {
match self.bits {
false => RXBE::Cleared,
true => RXBE::Error,
}
}
#[doc = "error cleared"]
#[inline(always)]
pub fn is_cleared(&self) -> bool {
*self == RXBE::Cleared
}
#[doc = "entry on top of RX FIFO has break error, cleared on read"]
#[inline(always)]
pub fn is_error(&self) -> bool {
*self == RXBE::Error
}
}
#[doc = "Field `RXBE` writer - RX break error"]
pub type RXBE_W<'a, REG> = crate::BitWriter<'a, REG, RXBE>;
impl<'a, REG> RXBE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "error cleared"]
#[inline(always)]
pub fn cleared(self) -> &'a mut crate::W<REG> {
self.variant(RXBE::Cleared)
}
#[doc = "entry on top of RX FIFO has break error, cleared on read"]
#[inline(always)]
pub fn error(self) -> &'a mut crate::W<REG> {
self.variant(RXBE::Error)
}
}
#[doc = "TX FIFO empty\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TCFE {
#[doc = "0: error cleared"]
Cleared = 0,
#[doc = "1: TX FIFO is empty"]
Error = 1,
}
impl From<TCFE> for bool {
#[inline(always)]
fn from(variant: TCFE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TCFE` reader - TX FIFO empty"]
pub type TCFE_R = crate::BitReader<TCFE>;
impl TCFE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> TCFE {
match self.bits {
false => TCFE::Cleared,
true => TCFE::Error,
}
}
#[doc = "error cleared"]
#[inline(always)]
pub fn is_cleared(&self) -> bool {
*self == TCFE::Cleared
}
#[doc = "TX FIFO is empty"]
#[inline(always)]
pub fn is_error(&self) -> bool {
*self == TCFE::Error
}
}
#[doc = "Field `TCFE` writer - TX FIFO empty"]
pub type TCFE_W<'a, REG> = crate::BitWriter<'a, REG, TCFE>;
impl<'a, REG> TCFE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "error cleared"]
#[inline(always)]
pub fn cleared(self) -> &'a mut crate::W<REG> {
self.variant(TCFE::Cleared)
}
#[doc = "TX FIFO is empty"]
#[inline(always)]
pub fn error(self) -> &'a mut crate::W<REG> {
self.variant(TCFE::Error)
}
}
#[doc = "TX empty\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TXE {
#[doc = "0: error cleared"]
Cleared = 0,
#[doc = "1: TX shift register and TX FIFO are empty"]
Error = 1,
}
impl From<TXE> for bool {
#[inline(always)]
fn from(variant: TXE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TXE` reader - TX empty"]
pub type TXE_R = crate::BitReader<TXE>;
impl TXE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> TXE {
match self.bits {
false => TXE::Cleared,
true => TXE::Error,
}
}
#[doc = "error cleared"]
#[inline(always)]
pub fn is_cleared(&self) -> bool {
*self == TXE::Cleared
}
#[doc = "TX shift register and TX FIFO are empty"]
#[inline(always)]
pub fn is_error(&self) -> bool {
*self == TXE::Error
}
}
#[doc = "Field `TXE` writer - TX empty"]
pub type TXE_W<'a, REG> = crate::BitWriter<'a, REG, TXE>;
impl<'a, REG> TXE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "error cleared"]
#[inline(always)]
pub fn cleared(self) -> &'a mut crate::W<REG> {
self.variant(TXE::Cleared)
}
#[doc = "TX shift register and TX FIFO are empty"]
#[inline(always)]
pub fn error(self) -> &'a mut crate::W<REG> {
self.variant(TXE::Error)
}
}
#[doc = "RX FIFO error\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RXE {
#[doc = "0: no error in RX FIFO"]
NoError = 0,
#[doc = "1: At least one parity, framing or break error active in FIFO"]
Error = 1,
}
impl From<RXE> for bool {
#[inline(always)]
fn from(variant: RXE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RXE` reader - RX FIFO error"]
pub type RXE_R = crate::BitReader<RXE>;
impl RXE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RXE {
match self.bits {
false => RXE::NoError,
true => RXE::Error,
}
}
#[doc = "no error in RX FIFO"]
#[inline(always)]
pub fn is_no_error(&self) -> bool {
*self == RXE::NoError
}
#[doc = "At least one parity, framing or break error active in FIFO"]
#[inline(always)]
pub fn is_error(&self) -> bool {
*self == RXE::Error
}
}
#[doc = "Field `RXE` writer - RX FIFO error"]
pub type RXE_W<'a, REG> = crate::BitWriter<'a, REG, RXE>;
impl<'a, REG> RXE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "no error in RX FIFO"]
#[inline(always)]
pub fn no_error(self) -> &'a mut crate::W<REG> {
self.variant(RXE::NoError)
}
#[doc = "At least one parity, framing or break error active in FIFO"]
#[inline(always)]
pub fn error(self) -> &'a mut crate::W<REG> {
self.variant(RXE::Error)
}
}
impl R {
#[doc = "Bit 0 - RX data ready"]
#[inline(always)]
pub fn rxdr(&self) -> RXDR_R {
RXDR_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RX overrun error"]
#[inline(always)]
pub fn rxoe(&self) -> RXOE_R {
RXOE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RX parity error"]
#[inline(always)]
pub fn rxpe(&self) -> RXPE_R {
RXPE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RX framing error"]
#[inline(always)]
pub fn rxfe(&self) -> RXFE_R {
RXFE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RX break error"]
#[inline(always)]
pub fn rxbe(&self) -> RXBE_R {
RXBE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - TX FIFO empty"]
#[inline(always)]
pub fn tcfe(&self) -> TCFE_R {
TCFE_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - TX empty"]
#[inline(always)]
pub fn txe(&self) -> TXE_R {
TXE_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RX FIFO error"]
#[inline(always)]
pub fn rxe(&self) -> RXE_R {
RXE_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UARTLS")
.field("rxdr", &self.rxdr())
.field("rxoe", &self.rxoe())
.field("rxpe", &self.rxpe())
.field("rxfe", &self.rxfe())
.field("rxbe", &self.rxbe())
.field("tcfe", &self.tcfe())
.field("txe", &self.txe())
.field("rxe", &self.rxe())
.finish()
}
}
impl W {
#[doc = "Bit 0 - RX data ready"]
#[inline(always)]
pub fn rxdr(&mut self) -> RXDR_W<UARTLSrs> {
RXDR_W::new(self, 0)
}
#[doc = "Bit 1 - RX overrun error"]
#[inline(always)]
pub fn rxoe(&mut self) -> RXOE_W<UARTLSrs> {
RXOE_W::new(self, 1)
}
#[doc = "Bit 2 - RX parity error"]
#[inline(always)]
pub fn rxpe(&mut self) -> RXPE_W<UARTLSrs> {
RXPE_W::new(self, 2)
}
#[doc = "Bit 3 - RX framing error"]
#[inline(always)]
pub fn rxfe(&mut self) -> RXFE_W<UARTLSrs> {
RXFE_W::new(self, 3)
}
#[doc = "Bit 4 - RX break error"]
#[inline(always)]
pub fn rxbe(&mut self) -> RXBE_W<UARTLSrs> {
RXBE_W::new(self, 4)
}
#[doc = "Bit 5 - TX FIFO empty"]
#[inline(always)]
pub fn tcfe(&mut self) -> TCFE_W<UARTLSrs> {
TCFE_W::new(self, 5)
}
#[doc = "Bit 6 - TX empty"]
#[inline(always)]
pub fn txe(&mut self) -> TXE_W<UARTLSrs> {
TXE_W::new(self, 6)
}
#[doc = "Bit 7 - RX FIFO error"]
#[inline(always)]
pub fn rxe(&mut self) -> RXE_W<UARTLSrs> {
RXE_W::new(self, 7)
}
}
#[doc = "UART Line Status\n\nYou can [`read`](crate::Reg::read) this register and get [`uartls::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartls::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct UARTLSrs;
impl crate::RegisterSpec for UARTLSrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`uartls::R`](R) reader structure"]
impl crate::Readable for UARTLSrs {}
#[doc = "`write(|w| ..)` method takes [`uartls::W`](W) writer structure"]
impl crate::Writable for UARTLSrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets UARTLS to value 0x30"]
impl crate::Resettable for UARTLSrs {
const RESET_VALUE: u32 = 0x30;
}
}
#[doc = "UARTFCTL (rw) register accessor: FIFO control\n\nYou can [`read`](crate::Reg::read) this register and get [`uartfctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartfctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uartfctl`]
module"]
pub type UARTFCTL = crate::Reg<uartfctl::UARTFCTLrs>;
#[doc = "FIFO control"]
pub mod uartfctl {
#[doc = "Register `UARTFCTL` reader"]
pub type R = crate::R<UARTFCTLrs>;
#[doc = "Register `UARTFCTL` writer"]
pub type W = crate::W<UARTFCTLrs>;
#[doc = "FIFO enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum FEN {
#[doc = "0: disable RX, TX FIFO"]
Disabled = 0,
#[doc = "1: enable RX, TX FIFO"]
Enabled = 1,
}
impl From<FEN> for bool {
#[inline(always)]
fn from(variant: FEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `FEN` reader - FIFO enable"]
pub type FEN_R = crate::BitReader<FEN>;
impl FEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> FEN {
match self.bits {
false => FEN::Disabled,
true => FEN::Enabled,
}
}
#[doc = "disable RX, TX FIFO"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == FEN::Disabled
}
#[doc = "enable RX, TX FIFO"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == FEN::Enabled
}
}
#[doc = "Field `FEN` writer - FIFO enable"]
pub type FEN_W<'a, REG> = crate::BitWriter<'a, REG, FEN>;
impl<'a, REG> FEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable RX, TX FIFO"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(FEN::Disabled)
}
#[doc = "enable RX, TX FIFO"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(FEN::Enabled)
}
}
#[doc = "RX FIFO reset\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RXFRESET {
#[doc = "0: no action"]
NoAction = 0,
#[doc = "1: clear RX FIFO, cleared on read"]
Clear = 1,
}
impl From<RXFRESET> for bool {
#[inline(always)]
fn from(variant: RXFRESET) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RXFRESET` reader - RX FIFO reset"]
pub type RXFRESET_R = crate::BitReader<RXFRESET>;
impl RXFRESET_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RXFRESET {
match self.bits {
false => RXFRESET::NoAction,
true => RXFRESET::Clear,
}
}
#[doc = "no action"]
#[inline(always)]
pub fn is_no_action(&self) -> bool {
*self == RXFRESET::NoAction
}
#[doc = "clear RX FIFO, cleared on read"]
#[inline(always)]
pub fn is_clear(&self) -> bool {
*self == RXFRESET::Clear
}
}
#[doc = "Field `RXFRESET` writer - RX FIFO reset"]
pub type RXFRESET_W<'a, REG> = crate::BitWriter<'a, REG, RXFRESET>;
impl<'a, REG> RXFRESET_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "no action"]
#[inline(always)]
pub fn no_action(self) -> &'a mut crate::W<REG> {
self.variant(RXFRESET::NoAction)
}
#[doc = "clear RX FIFO, cleared on read"]
#[inline(always)]
pub fn clear(self) -> &'a mut crate::W<REG> {
self.variant(RXFRESET::Clear)
}
}
#[doc = "RX FIFO reset\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TXFRESET {
#[doc = "0: no action"]
NoAction = 0,
#[doc = "1: clear TX FIFO, cleared on read"]
Clear = 1,
}
impl From<TXFRESET> for bool {
#[inline(always)]
fn from(variant: TXFRESET) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TXFRESET` reader - RX FIFO reset"]
pub type TXFRESET_R = crate::BitReader<TXFRESET>;
impl TXFRESET_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> TXFRESET {
match self.bits {
false => TXFRESET::NoAction,
true => TXFRESET::Clear,
}
}
#[doc = "no action"]
#[inline(always)]
pub fn is_no_action(&self) -> bool {
*self == TXFRESET::NoAction
}
#[doc = "clear TX FIFO, cleared on read"]
#[inline(always)]
pub fn is_clear(&self) -> bool {
*self == TXFRESET::Clear
}
}
#[doc = "Field `TXFRESET` writer - RX FIFO reset"]
pub type TXFRESET_W<'a, REG> = crate::BitWriter<'a, REG, TXFRESET>;
impl<'a, REG> TXFRESET_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "no action"]
#[inline(always)]
pub fn no_action(self) -> &'a mut crate::W<REG> {
self.variant(TXFRESET::NoAction)
}
#[doc = "clear TX FIFO, cleared on read"]
#[inline(always)]
pub fn clear(self) -> &'a mut crate::W<REG> {
self.variant(TXFRESET::Clear)
}
}
#[doc = "RX FIFO Theshold\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum RXFT {
#[doc = "0: 1 byte in FIFO"]
_1 = 0,
#[doc = "1: 4 bytes in FIFO"]
_4 = 1,
#[doc = "2: 8 bytes in FIFO"]
_8 = 2,
#[doc = "3: 14 bytes in FIFO"]
_14 = 3,
}
impl From<RXFT> for u8 {
#[inline(always)]
fn from(variant: RXFT) -> Self {
variant as _
}
}
impl crate::FieldSpec for RXFT {
type Ux = u8;
}
impl crate::IsEnum for RXFT {}
#[doc = "Field `RXFT` reader - RX FIFO Theshold"]
pub type RXFT_R = crate::FieldReader<RXFT>;
impl RXFT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RXFT {
match self.bits {
0 => RXFT::_1,
1 => RXFT::_4,
2 => RXFT::_8,
3 => RXFT::_14,
_ => unreachable!(),
}
}
#[doc = "1 byte in FIFO"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == RXFT::_1
}
#[doc = "4 bytes in FIFO"]
#[inline(always)]
pub fn is_4(&self) -> bool {
*self == RXFT::_4
}
#[doc = "8 bytes in FIFO"]
#[inline(always)]
pub fn is_8(&self) -> bool {
*self == RXFT::_8
}
#[doc = "14 bytes in FIFO"]
#[inline(always)]
pub fn is_14(&self) -> bool {
*self == RXFT::_14
}
}
#[doc = "Field `RXFT` writer - RX FIFO Theshold"]
pub type RXFT_W<'a, REG> = crate::FieldWriter<'a, REG, 2, RXFT, crate::Safe>;
impl<'a, REG> RXFT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "1 byte in FIFO"]
#[inline(always)]
pub fn _1(self) -> &'a mut crate::W<REG> {
self.variant(RXFT::_1)
}
#[doc = "4 bytes in FIFO"]
#[inline(always)]
pub fn _4(self) -> &'a mut crate::W<REG> {
self.variant(RXFT::_4)
}
#[doc = "8 bytes in FIFO"]
#[inline(always)]
pub fn _8(self) -> &'a mut crate::W<REG> {
self.variant(RXFT::_8)
}
#[doc = "14 bytes in FIFO"]
#[inline(always)]
pub fn _14(self) -> &'a mut crate::W<REG> {
self.variant(RXFT::_14)
}
}
impl R {
#[doc = "Bit 0 - FIFO enable"]
#[inline(always)]
pub fn fen(&self) -> FEN_R {
FEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RX FIFO reset"]
#[inline(always)]
pub fn rxfreset(&self) -> RXFRESET_R {
RXFRESET_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RX FIFO reset"]
#[inline(always)]
pub fn txfreset(&self) -> TXFRESET_R {
TXFRESET_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 6:7 - RX FIFO Theshold"]
#[inline(always)]
pub fn rxft(&self) -> RXFT_R {
RXFT_R::new(((self.bits >> 6) & 3) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UARTFCTL")
.field("fen", &self.fen())
.field("rxfreset", &self.rxfreset())
.field("txfreset", &self.txfreset())
.field("rxft", &self.rxft())
.finish()
}
}
impl W {
#[doc = "Bit 0 - FIFO enable"]
#[inline(always)]
pub fn fen(&mut self) -> FEN_W<UARTFCTLrs> {
FEN_W::new(self, 0)
}
#[doc = "Bit 1 - RX FIFO reset"]
#[inline(always)]
pub fn rxfreset(&mut self) -> RXFRESET_W<UARTFCTLrs> {
RXFRESET_W::new(self, 1)
}
#[doc = "Bit 2 - RX FIFO reset"]
#[inline(always)]
pub fn txfreset(&mut self) -> TXFRESET_W<UARTFCTLrs> {
TXFRESET_W::new(self, 2)
}
#[doc = "Bits 6:7 - RX FIFO Theshold"]
#[inline(always)]
pub fn rxft(&mut self) -> RXFT_W<UARTFCTLrs> {
RXFT_W::new(self, 6)
}
}
#[doc = "FIFO control\n\nYou can [`read`](crate::Reg::read) this register and get [`uartfctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartfctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct UARTFCTLrs;
impl crate::RegisterSpec for UARTFCTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`uartfctl::R`](R) reader structure"]
impl crate::Readable for UARTFCTLrs {}
#[doc = "`write(|w| ..)` method takes [`uartfctl::W`](W) writer structure"]
impl crate::Writable for UARTFCTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets UARTFCTL to value 0x40"]
impl crate::Resettable for UARTFCTLrs {
const RESET_VALUE: u32 = 0x40;
}
}
#[doc = "UARTIE_R (rw) register accessor: UART interrupt enable remapped\n\nYou can [`read`](crate::Reg::read) this register and get [`uartie_r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartie_r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uartie_r`]
module"]
pub type UARTIE_R = crate::Reg<uartie_r::UARTIE_Rrs>;
#[doc = "UART interrupt enable remapped"]
pub mod uartie_r {
#[doc = "Register `UARTIE_R` reader"]
pub type R = crate::R<UARTIE_Rrs>;
#[doc = "Register `UARTIE_R` writer"]
pub type W = crate::W<UARTIE_Rrs>;
#[doc = "RX register data available interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RXINTEN {
#[doc = "0: disable interrupt"]
Disabled = 0,
#[doc = "1: enable interrupt"]
Enabled = 1,
}
impl From<RXINTEN> for bool {
#[inline(always)]
fn from(variant: RXINTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RXINTEN` reader - RX register data available interrupt enable"]
pub type RXINTEN_R = crate::BitReader<RXINTEN>;
impl RXINTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RXINTEN {
match self.bits {
false => RXINTEN::Disabled,
true => RXINTEN::Enabled,
}
}
#[doc = "disable interrupt"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == RXINTEN::Disabled
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == RXINTEN::Enabled
}
}
#[doc = "Field `RXINTEN` writer - RX register data available interrupt enable"]
pub type RXINTEN_W<'a, REG> = crate::BitWriter<'a, REG, RXINTEN>;
impl<'a, REG> RXINTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable interrupt"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(RXINTEN::Disabled)
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(RXINTEN::Enabled)
}
}
#[doc = "TX register data available interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TXINTEN {
#[doc = "0: disable interrupt"]
Disabled = 0,
#[doc = "1: enable interrupt"]
Enabled = 1,
}
impl From<TXINTEN> for bool {
#[inline(always)]
fn from(variant: TXINTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TXINTEN` reader - TX register data available interrupt enable"]
pub type TXINTEN_R = crate::BitReader<TXINTEN>;
impl TXINTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> TXINTEN {
match self.bits {
false => TXINTEN::Disabled,
true => TXINTEN::Enabled,
}
}
#[doc = "disable interrupt"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == TXINTEN::Disabled
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == TXINTEN::Enabled
}
}
#[doc = "Field `TXINTEN` writer - TX register data available interrupt enable"]
pub type TXINTEN_W<'a, REG> = crate::BitWriter<'a, REG, TXINTEN>;
impl<'a, REG> TXINTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable interrupt"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(TXINTEN::Disabled)
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(TXINTEN::Enabled)
}
}
#[doc = "Receive interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RSINTEN {
#[doc = "0: disable interrupt"]
Disabled = 0,
#[doc = "1: enable interrupt"]
Enabled = 1,
}
impl From<RSINTEN> for bool {
#[inline(always)]
fn from(variant: RSINTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RSINTEN` reader - Receive interrupt enable"]
pub type RSINTEN_R = crate::BitReader<RSINTEN>;
impl RSINTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RSINTEN {
match self.bits {
false => RSINTEN::Disabled,
true => RSINTEN::Enabled,
}
}
#[doc = "disable interrupt"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == RSINTEN::Disabled
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == RSINTEN::Enabled
}
}
#[doc = "Field `RSINTEN` writer - Receive interrupt enable"]
pub type RSINTEN_W<'a, REG> = crate::BitWriter<'a, REG, RSINTEN>;
impl<'a, REG> RSINTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable interrupt"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(RSINTEN::Disabled)
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(RSINTEN::Enabled)
}
}
#[doc = "Modem status interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MSINTEN {
#[doc = "0: disable interrupt"]
Disabled = 0,
#[doc = "1: enable interrupt"]
Enabled = 1,
}
impl From<MSINTEN> for bool {
#[inline(always)]
fn from(variant: MSINTEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MSINTEN` reader - Modem status interrupt enable"]
pub type MSINTEN_R = crate::BitReader<MSINTEN>;
impl MSINTEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MSINTEN {
match self.bits {
false => MSINTEN::Disabled,
true => MSINTEN::Enabled,
}
}
#[doc = "disable interrupt"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == MSINTEN::Disabled
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == MSINTEN::Enabled
}
}
#[doc = "Field `MSINTEN` writer - Modem status interrupt enable"]
pub type MSINTEN_W<'a, REG> = crate::BitWriter<'a, REG, MSINTEN>;
impl<'a, REG> MSINTEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable interrupt"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(MSINTEN::Disabled)
}
#[doc = "enable interrupt"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(MSINTEN::Enabled)
}
}
impl R {
#[doc = "Bit 0 - RX register data available interrupt enable"]
#[inline(always)]
pub fn rxinten(&self) -> RXINTEN_R {
RXINTEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - TX register data available interrupt enable"]
#[inline(always)]
pub fn txinten(&self) -> TXINTEN_R {
TXINTEN_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Receive interrupt enable"]
#[inline(always)]
pub fn rsinten(&self) -> RSINTEN_R {
RSINTEN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Modem status interrupt enable"]
#[inline(always)]
pub fn msinten(&self) -> MSINTEN_R {
MSINTEN_R::new(((self.bits >> 3) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UARTIE_R")
.field("rxinten", &self.rxinten())
.field("txinten", &self.txinten())
.field("rsinten", &self.rsinten())
.field("msinten", &self.msinten())
.finish()
}
}
impl W {
#[doc = "Bit 0 - RX register data available interrupt enable"]
#[inline(always)]
pub fn rxinten(&mut self) -> RXINTEN_W<UARTIE_Rrs> {
RXINTEN_W::new(self, 0)
}
#[doc = "Bit 1 - TX register data available interrupt enable"]
#[inline(always)]
pub fn txinten(&mut self) -> TXINTEN_W<UARTIE_Rrs> {
TXINTEN_W::new(self, 1)
}
#[doc = "Bit 2 - Receive interrupt enable"]
#[inline(always)]
pub fn rsinten(&mut self) -> RSINTEN_W<UARTIE_Rrs> {
RSINTEN_W::new(self, 2)
}
#[doc = "Bit 3 - Modem status interrupt enable"]
#[inline(always)]
pub fn msinten(&mut self) -> MSINTEN_W<UARTIE_Rrs> {
MSINTEN_W::new(self, 3)
}
}
#[doc = "UART interrupt enable remapped\n\nYou can [`read`](crate::Reg::read) this register and get [`uartie_r::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartie_r::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct UARTIE_Rrs;
impl crate::RegisterSpec for UARTIE_Rrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`uartie_r::R`](R) reader structure"]
impl crate::Readable for UARTIE_Rrs {}
#[doc = "`write(|w| ..)` method takes [`uartie_r::W`](W) writer structure"]
impl crate::Writable for UARTIE_Rrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets UARTIE_R to value 0"]
impl crate::Resettable for UARTIE_Rrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "UARTDL_L (rw) register accessor: UART divisor latch low byte\n\nYou can [`read`](crate::Reg::read) this register and get [`uartdl_l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartdl_l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uartdl_l`]
module"]
pub type UARTDL_L = crate::Reg<uartdl_l::UARTDL_Lrs>;
#[doc = "UART divisor latch low byte"]
pub mod uartdl_l {
#[doc = "Register `UARTDL_L` reader"]
pub type R = crate::R<UARTDL_Lrs>;
#[doc = "Register `UARTDL_L` writer"]
pub type W = crate::W<UARTDL_Lrs>;
#[doc = "Field `DL_L` reader - RX register data available interrupt enable"]
pub type DL_L_R = crate::FieldReader;
#[doc = "Field `DL_L` writer - RX register data available interrupt enable"]
pub type DL_L_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - RX register data available interrupt enable"]
#[inline(always)]
pub fn dl_l(&self) -> DL_L_R {
DL_L_R::new((self.bits & 0xff) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UARTDL_L")
.field("dl_l", &self.dl_l())
.finish()
}
}
impl W {
#[doc = "Bits 0:7 - RX register data available interrupt enable"]
#[inline(always)]
pub fn dl_l(&mut self) -> DL_L_W<UARTDL_Lrs> {
DL_L_W::new(self, 0)
}
}
#[doc = "UART divisor latch low byte\n\nYou can [`read`](crate::Reg::read) this register and get [`uartdl_l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartdl_l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct UARTDL_Lrs;
impl crate::RegisterSpec for UARTDL_Lrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`uartdl_l::R`](R) reader structure"]
impl crate::Readable for UARTDL_Lrs {}
#[doc = "`write(|w| ..)` method takes [`uartdl_l::W`](W) writer structure"]
impl crate::Writable for UARTDL_Lrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets UARTDL_L to value 0"]
impl crate::Resettable for UARTDL_Lrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "UARTDL_H (rw) register accessor: UART divisor latch high byte\n\nYou can [`read`](crate::Reg::read) this register and get [`uartdl_h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartdl_h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uartdl_h`]
module"]
pub type UARTDL_H = crate::Reg<uartdl_h::UARTDL_Hrs>;
#[doc = "UART divisor latch high byte"]
pub mod uartdl_h {
#[doc = "Register `UARTDL_H` reader"]
pub type R = crate::R<UARTDL_Hrs>;
#[doc = "Register `UARTDL_H` writer"]
pub type W = crate::W<UARTDL_Hrs>;
#[doc = "Field `DL_H` reader - Divisor value, high byte"]
pub type DL_H_R = crate::FieldReader;
#[doc = "Field `DL_H` writer - Divisor value, high byte"]
pub type DL_H_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Divisor value, high byte"]
#[inline(always)]
pub fn dl_h(&self) -> DL_H_R {
DL_H_R::new((self.bits & 0xff) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UARTDL_H")
.field("dl_h", &self.dl_h())
.finish()
}
}
impl W {
#[doc = "Bits 0:7 - Divisor value, high byte"]
#[inline(always)]
pub fn dl_h(&mut self) -> DL_H_W<UARTDL_Hrs> {
DL_H_W::new(self, 0)
}
}
#[doc = "UART divisor latch high byte\n\nYou can [`read`](crate::Reg::read) this register and get [`uartdl_h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartdl_h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct UARTDL_Hrs;
impl crate::RegisterSpec for UARTDL_Hrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`uartdl_h::R`](R) reader structure"]
impl crate::Readable for UARTDL_Hrs {}
#[doc = "`write(|w| ..)` method takes [`uartdl_h::W`](W) writer structure"]
impl crate::Writable for UARTDL_Hrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets UARTDL_H to value 0"]
impl crate::Resettable for UARTDL_Hrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "UARTFD_F (rw) register accessor: UART fractional divisor value\n\nYou can [`read`](crate::Reg::read) this register and get [`uartfd_f::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartfd_f::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uartfd_f`]
module"]
pub type UARTFD_F = crate::Reg<uartfd_f::UARTFD_Frs>;
#[doc = "UART fractional divisor value"]
pub mod uartfd_f {
#[doc = "Register `UARTFD_F` reader"]
pub type R = crate::R<UARTFD_Frs>;
#[doc = "Register `UARTFD_F` writer"]
pub type W = crate::W<UARTFD_Frs>;
#[doc = "Field `FRAC` reader - Fractional divisor value"]
pub type FRAC_R = crate::FieldReader;
#[doc = "Field `FRAC` writer - Fractional divisor value"]
pub type FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Fractional divisor value"]
#[inline(always)]
pub fn frac(&self) -> FRAC_R {
FRAC_R::new((self.bits & 0xff) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UARTFD_F")
.field("frac", &self.frac())
.finish()
}
}
impl W {
#[doc = "Bits 0:7 - Fractional divisor value"]
#[inline(always)]
pub fn frac(&mut self) -> FRAC_W<UARTFD_Frs> {
FRAC_W::new(self, 0)
}
}
#[doc = "UART fractional divisor value\n\nYou can [`read`](crate::Reg::read) this register and get [`uartfd_f::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartfd_f::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct UARTFD_Frs;
impl crate::RegisterSpec for UARTFD_Frs {
type Ux = u32;
}
#[doc = "`read()` method returns [`uartfd_f::R`](R) reader structure"]
impl crate::Readable for UARTFD_Frs {}
#[doc = "`write(|w| ..)` method takes [`uartfd_f::W`](W) writer structure"]
impl crate::Writable for UARTFD_Frs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets UARTFD_F to value 0"]
impl crate::Resettable for UARTFD_Frs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "UARTFSTAT (rw) register accessor: UART FIFO status\n\nYou can [`read`](crate::Reg::read) this register and get [`uartfstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartfstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uartfstat`]
module"]
pub type UARTFSTAT = crate::Reg<uartfstat::UARTFSTATrs>;
#[doc = "UART FIFO status"]
pub mod uartfstat {
#[doc = "Register `UARTFSTAT` reader"]
pub type R = crate::R<UARTFSTATrs>;
#[doc = "Register `UARTFSTAT` writer"]
pub type W = crate::W<UARTFSTATrs>;
#[doc = "TX FIFO empty\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TXFE {
#[doc = "0: TX FIFO not empty"]
NotEmpty = 0,
#[doc = "1: TX FIFO empty"]
Empty = 1,
}
impl From<TXFE> for bool {
#[inline(always)]
fn from(variant: TXFE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TXFE` reader - TX FIFO empty"]
pub type TXFE_R = crate::BitReader<TXFE>;
impl TXFE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> TXFE {
match self.bits {
false => TXFE::NotEmpty,
true => TXFE::Empty,
}
}
#[doc = "TX FIFO not empty"]
#[inline(always)]
pub fn is_not_empty(&self) -> bool {
*self == TXFE::NotEmpty
}
#[doc = "TX FIFO empty"]
#[inline(always)]
pub fn is_empty(&self) -> bool {
*self == TXFE::Empty
}
}
#[doc = "Field `TXFE` writer - TX FIFO empty"]
pub type TXFE_W<'a, REG> = crate::BitWriter<'a, REG, TXFE>;
impl<'a, REG> TXFE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "TX FIFO not empty"]
#[inline(always)]
pub fn not_empty(self) -> &'a mut crate::W<REG> {
self.variant(TXFE::NotEmpty)
}
#[doc = "TX FIFO empty"]
#[inline(always)]
pub fn empty(self) -> &'a mut crate::W<REG> {
self.variant(TXFE::Empty)
}
}
#[doc = "TX FIFO full\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TXFF {
#[doc = "0: TX FIFO not full"]
NotFull = 0,
#[doc = "1: TX FIFO full"]
Full = 1,
}
impl From<TXFF> for bool {
#[inline(always)]
fn from(variant: TXFF) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TXFF` reader - TX FIFO full"]
pub type TXFF_R = crate::BitReader<TXFF>;
impl TXFF_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> TXFF {
match self.bits {
false => TXFF::NotFull,
true => TXFF::Full,
}
}
#[doc = "TX FIFO not full"]
#[inline(always)]
pub fn is_not_full(&self) -> bool {
*self == TXFF::NotFull
}
#[doc = "TX FIFO full"]
#[inline(always)]
pub fn is_full(&self) -> bool {
*self == TXFF::Full
}
}
#[doc = "Field `TXFF` writer - TX FIFO full"]
pub type TXFF_W<'a, REG> = crate::BitWriter<'a, REG, TXFF>;
impl<'a, REG> TXFF_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "TX FIFO not full"]
#[inline(always)]
pub fn not_full(self) -> &'a mut crate::W<REG> {
self.variant(TXFF::NotFull)
}
#[doc = "TX FIFO full"]
#[inline(always)]
pub fn full(self) -> &'a mut crate::W<REG> {
self.variant(TXFF::Full)
}
}
#[doc = "RX FIFO empty\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RXFE {
#[doc = "0: RX FIFO not empty"]
NotEmpty = 0,
#[doc = "1: RX FIFO empty"]
Empty = 1,
}
impl From<RXFE> for bool {
#[inline(always)]
fn from(variant: RXFE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RXFE` reader - RX FIFO empty"]
pub type RXFE_R = crate::BitReader<RXFE>;
impl RXFE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RXFE {
match self.bits {
false => RXFE::NotEmpty,
true => RXFE::Empty,
}
}
#[doc = "RX FIFO not empty"]
#[inline(always)]
pub fn is_not_empty(&self) -> bool {
*self == RXFE::NotEmpty
}
#[doc = "RX FIFO empty"]
#[inline(always)]
pub fn is_empty(&self) -> bool {
*self == RXFE::Empty
}
}
#[doc = "Field `RXFE` writer - RX FIFO empty"]
pub type RXFE_W<'a, REG> = crate::BitWriter<'a, REG, RXFE>;
impl<'a, REG> RXFE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "RX FIFO not empty"]
#[inline(always)]
pub fn not_empty(self) -> &'a mut crate::W<REG> {
self.variant(RXFE::NotEmpty)
}
#[doc = "RX FIFO empty"]
#[inline(always)]
pub fn empty(self) -> &'a mut crate::W<REG> {
self.variant(RXFE::Empty)
}
}
#[doc = "RX FIFO full\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RXFF {
#[doc = "0: RX FIFO not full"]
NotFull = 0,
#[doc = "1: RX FIFO full"]
Full = 1,
}
impl From<RXFF> for bool {
#[inline(always)]
fn from(variant: RXFF) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RXFF` reader - RX FIFO full"]
pub type RXFF_R = crate::BitReader<RXFF>;
impl RXFF_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RXFF {
match self.bits {
false => RXFF::NotFull,
true => RXFF::Full,
}
}
#[doc = "RX FIFO not full"]
#[inline(always)]
pub fn is_not_full(&self) -> bool {
*self == RXFF::NotFull
}
#[doc = "RX FIFO full"]
#[inline(always)]
pub fn is_full(&self) -> bool {
*self == RXFF::Full
}
}
#[doc = "Field `RXFF` writer - RX FIFO full"]
pub type RXFF_W<'a, REG> = crate::BitWriter<'a, REG, RXFF>;
impl<'a, REG> RXFF_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "RX FIFO not full"]
#[inline(always)]
pub fn not_full(self) -> &'a mut crate::W<REG> {
self.variant(RXFF::NotFull)
}
#[doc = "RX FIFO full"]
#[inline(always)]
pub fn full(self) -> &'a mut crate::W<REG> {
self.variant(RXFF::Full)
}
}
impl R {
#[doc = "Bit 0 - TX FIFO empty"]
#[inline(always)]
pub fn txfe(&self) -> TXFE_R {
TXFE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - TX FIFO full"]
#[inline(always)]
pub fn txff(&self) -> TXFF_R {
TXFF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RX FIFO empty"]
#[inline(always)]
pub fn rxfe(&self) -> RXFE_R {
RXFE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RX FIFO full"]
#[inline(always)]
pub fn rxff(&self) -> RXFF_R {
RXFF_R::new(((self.bits >> 3) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UARTFSTAT")
.field("txfe", &self.txfe())
.field("txff", &self.txff())
.field("rxfe", &self.rxfe())
.field("rxff", &self.rxff())
.finish()
}
}
impl W {
#[doc = "Bit 0 - TX FIFO empty"]
#[inline(always)]
pub fn txfe(&mut self) -> TXFE_W<UARTFSTATrs> {
TXFE_W::new(self, 0)
}
#[doc = "Bit 1 - TX FIFO full"]
#[inline(always)]
pub fn txff(&mut self) -> TXFF_W<UARTFSTATrs> {
TXFF_W::new(self, 1)
}
#[doc = "Bit 2 - RX FIFO empty"]
#[inline(always)]
pub fn rxfe(&mut self) -> RXFE_W<UARTFSTATrs> {
RXFE_W::new(self, 2)
}
#[doc = "Bit 3 - RX FIFO full"]
#[inline(always)]
pub fn rxff(&mut self) -> RXFF_W<UARTFSTATrs> {
RXFF_W::new(self, 3)
}
}
#[doc = "UART FIFO status\n\nYou can [`read`](crate::Reg::read) this register and get [`uartfstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartfstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct UARTFSTATrs;
impl crate::RegisterSpec for UARTFSTATrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`uartfstat::R`](R) reader structure"]
impl crate::Readable for UARTFSTATrs {}
#[doc = "`write(|w| ..)` method takes [`uartfstat::W`](W) writer structure"]
impl crate::Writable for UARTFSTATrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets UARTFSTAT to value 0x05"]
impl crate::Resettable for UARTFSTATrs {
const RESET_VALUE: u32 = 0x05;
}
}
}
#[doc = "SOC Bus Bridge"]
pub struct SOCB {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for SOCB {}
impl SOCB {
#[doc = r"Pointer to the register block"]
pub const PTR: *const socb::RegisterBlock = 0x4020_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const socb::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for SOCB {
type Target = socb::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for SOCB {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SOCB").finish()
}
}
#[doc = "SOC Bus Bridge"]
pub mod socb {
#[repr(C)]
#[derive(Debug)]
#[doc = "Register block"]
pub struct RegisterBlock {
socbctl: SOCBCTL,
socbcfg: SOCBCFG,
_reserved2: [u8; 0x0c],
socbstat: SOCBSTAT,
_reserved3: [u8; 0x04],
socbd: SOCBD,
socbint_en: SOCBINT_EN,
}
impl RegisterBlock {
#[doc = "0x00 - SOC Bus Bridge Control"]
#[inline(always)]
pub const fn socbctl(&self) -> &SOCBCTL {
&self.socbctl
}
#[doc = "0x04 - SOC Bus Bridge Configuration"]
#[inline(always)]
pub const fn socbcfg(&self) -> &SOCBCFG {
&self.socbcfg
}
#[doc = "0x14 - SOC Bus Bridge Status"]
#[inline(always)]
pub const fn socbstat(&self) -> &SOCBSTAT {
&self.socbstat
}
#[doc = "0x1c - SOC Bus Bridge Data. On READ, retrieve received data word from the incoming holding buffer. On WRITE, write address or data word to the outgoing holding buffer"]
#[inline(always)]
pub const fn socbd(&self) -> &SOCBD {
&self.socbd
}
#[doc = "0x20 - SOC Bus Bridge Interrupt Enable"]
#[inline(always)]
pub const fn socbint_en(&self) -> &SOCBINT_EN {
&self.socbint_en
}
}
#[doc = "SOCBCTL (rw) register accessor: SOC Bus Bridge Control\n\nYou can [`read`](crate::Reg::read) this register and get [`socbctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`socbctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@socbctl`]
module"]
pub type SOCBCTL = crate::Reg<socbctl::SOCBCTLrs>;
#[doc = "SOC Bus Bridge Control"]
pub mod socbctl {
#[doc = "Register `SOCBCTL` reader"]
pub type R = crate::R<SOCBCTLrs>;
#[doc = "Register `SOCBCTL` writer"]
pub type W = crate::W<SOCBCTLrs>;
#[doc = "SOC bus bridge enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SSEN {
#[doc = "0: disable this module"]
Disable = 0,
#[doc = "1: enable this module"]
Enable = 1,
}
impl From<SSEN> for bool {
#[inline(always)]
fn from(variant: SSEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SSEN` reader - SOC bus bridge enable"]
pub type SSEN_R = crate::BitReader<SSEN>;
impl SSEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SSEN {
match self.bits {
false => SSEN::Disable,
true => SSEN::Enable,
}
}
#[doc = "disable this module"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == SSEN::Disable
}
#[doc = "enable this module"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == SSEN::Enable
}
}
#[doc = "Field `SSEN` writer - SOC bus bridge enable"]
pub type SSEN_W<'a, REG> = crate::BitWriter<'a, REG, SSEN>;
impl<'a, REG> SSEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable this module"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(SSEN::Disable)
}
#[doc = "enable this module"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(SSEN::Enable)
}
}
#[doc = "SOC bus bridge interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SIE {
#[doc = "0: disable interrupts"]
Disable = 0,
#[doc = "1: enable interrupts"]
Enable = 1,
}
impl From<SIE> for bool {
#[inline(always)]
fn from(variant: SIE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SIE` reader - SOC bus bridge interrupt enable"]
pub type SIE_R = crate::BitReader<SIE>;
impl SIE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SIE {
match self.bits {
false => SIE::Disable,
true => SIE::Enable,
}
}
#[doc = "disable interrupts"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == SIE::Disable
}
#[doc = "enable interrupts"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == SIE::Enable
}
}
#[doc = "Field `SIE` writer - SOC bus bridge interrupt enable"]
pub type SIE_W<'a, REG> = crate::BitWriter<'a, REG, SIE>;
impl<'a, REG> SIE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable interrupts"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(SIE::Disable)
}
#[doc = "enable interrupts"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(SIE::Enable)
}
}
#[doc = "MTRANS re-arm\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MTRARM {
#[doc = "1: re-arms the SOCBCTL.MTRANS operation by de-asserting CSx chip select and returning the master mode state machine to IDLE."]
ReArm = 1,
}
impl From<MTRARM> for bool {
#[inline(always)]
fn from(variant: MTRARM) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MTRARM` writer - MTRANS re-arm"]
pub type MTRARM_W<'a, REG> = crate::BitWriter<'a, REG, MTRARM>;
impl<'a, REG> MTRARM_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "re-arms the SOCBCTL.MTRANS operation by de-asserting CSx chip select and returning the master mode state machine to IDLE."]
#[inline(always)]
pub fn re_arm(self) -> &'a mut crate::W<REG> {
self.variant(MTRARM::ReArm)
}
}
impl R {
#[doc = "Bit 0 - SOC bus bridge enable"]
#[inline(always)]
pub fn ssen(&self) -> SSEN_R {
SSEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - SOC bus bridge interrupt enable"]
#[inline(always)]
pub fn sie(&self) -> SIE_R {
SIE_R::new(((self.bits >> 1) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SOCBCTL")
.field("ssen", &self.ssen())
.field("sie", &self.sie())
.finish()
}
}
impl W {
#[doc = "Bit 0 - SOC bus bridge enable"]
#[inline(always)]
pub fn ssen(&mut self) -> SSEN_W<SOCBCTLrs> {
SSEN_W::new(self, 0)
}
#[doc = "Bit 1 - SOC bus bridge interrupt enable"]
#[inline(always)]
pub fn sie(&mut self) -> SIE_W<SOCBCTLrs> {
SIE_W::new(self, 1)
}
#[doc = "Bit 5 - MTRANS re-arm"]
#[inline(always)]
pub fn mtrarm(&mut self) -> MTRARM_W<SOCBCTLrs> {
MTRARM_W::new(self, 5)
}
}
#[doc = "SOC Bus Bridge Control\n\nYou can [`read`](crate::Reg::read) this register and get [`socbctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`socbctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SOCBCTLrs;
impl crate::RegisterSpec for SOCBCTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`socbctl::R`](R) reader structure"]
impl crate::Readable for SOCBCTLrs {}
#[doc = "`write(|w| ..)` method takes [`socbctl::W`](W) writer structure"]
impl crate::Writable for SOCBCTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SOCBCTL to value 0"]
impl crate::Resettable for SOCBCTLrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SOCBCFG (rw) register accessor: SOC Bus Bridge Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`socbcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`socbcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@socbcfg`]
module"]
pub type SOCBCFG = crate::Reg<socbcfg::SOCBCFGrs>;
#[doc = "SOC Bus Bridge Configuration"]
pub mod socbcfg {
#[doc = "Register `SOCBCFG` reader"]
pub type R = crate::R<SOCBCFGrs>;
#[doc = "Register `SOCBCFG` writer"]
pub type W = crate::W<SOCBCFGrs>;
#[doc = "Module reset\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MRST {
#[doc = "0: do not hold the module in reset"]
Disable = 0,
#[doc = "1: force soft reset of module. The internal state machines are reset; status register is cleared; however, the soft reset does not affect control register values."]
Reset = 1,
}
impl From<MRST> for bool {
#[inline(always)]
fn from(variant: MRST) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MRST` reader - Module reset"]
pub type MRST_R = crate::BitReader<MRST>;
impl MRST_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MRST {
match self.bits {
false => MRST::Disable,
true => MRST::Reset,
}
}
#[doc = "do not hold the module in reset"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == MRST::Disable
}
#[doc = "force soft reset of module. The internal state machines are reset; status register is cleared; however, the soft reset does not affect control register values."]
#[inline(always)]
pub fn is_reset(&self) -> bool {
*self == MRST::Reset
}
}
#[doc = "Field `MRST` writer - Module reset"]
pub type MRST_W<'a, REG> = crate::BitWriter<'a, REG, MRST>;
impl<'a, REG> MRST_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "do not hold the module in reset"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(MRST::Disable)
}
#[doc = "force soft reset of module. The internal state machines are reset; status register is cleared; however, the soft reset does not affect control register values."]
#[inline(always)]
pub fn reset(self) -> &'a mut crate::W<REG> {
self.variant(MRST::Reset)
}
}
impl R {
#[doc = "Bit 2 - Module reset"]
#[inline(always)]
pub fn mrst(&self) -> MRST_R {
MRST_R::new(((self.bits >> 2) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SOCBCFG")
.field("mrst", &self.mrst())
.finish()
}
}
impl W {
#[doc = "Bit 2 - Module reset"]
#[inline(always)]
pub fn mrst(&mut self) -> MRST_W<SOCBCFGrs> {
MRST_W::new(self, 2)
}
}
#[doc = "SOC Bus Bridge Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`socbcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`socbcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SOCBCFGrs;
impl crate::RegisterSpec for SOCBCFGrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`socbcfg::R`](R) reader structure"]
impl crate::Readable for SOCBCFGrs {}
#[doc = "`write(|w| ..)` method takes [`socbcfg::W`](W) writer structure"]
impl crate::Writable for SOCBCFGrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SOCBCFG to value 0"]
impl crate::Resettable for SOCBCFGrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SOCBSTAT (rw) register accessor: SOC Bus Bridge Status\n\nYou can [`read`](crate::Reg::read) this register and get [`socbstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`socbstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@socbstat`]
module"]
pub type SOCBSTAT = crate::Reg<socbstat::SOCBSTATrs>;
#[doc = "SOC Bus Bridge Status"]
pub mod socbstat {
#[doc = "Register `SOCBSTAT` reader"]
pub type R = crate::R<SOCBSTATrs>;
#[doc = "Register `SOCBSTAT` writer"]
pub type W = crate::W<SOCBSTATrs>;
#[doc = "SOC bus bridge interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SOCB_INT {
#[doc = "0: no interrupt"]
None = 0,
#[doc = "1: interrupt"]
Interrupt = 1,
}
impl From<SOCB_INT> for bool {
#[inline(always)]
fn from(variant: SOCB_INT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SOCB_INT` reader - SOC bus bridge interrupt"]
pub type SOCB_INT_R = crate::BitReader<SOCB_INT>;
impl SOCB_INT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SOCB_INT {
match self.bits {
false => SOCB_INT::None,
true => SOCB_INT::Interrupt,
}
}
#[doc = "no interrupt"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == SOCB_INT::None
}
#[doc = "interrupt"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == SOCB_INT::Interrupt
}
}
#[doc = "Field `SOCB_INT` writer - SOC bus bridge interrupt"]
pub type SOCB_INT_W<'a, REG> = crate::BitWriter<'a, REG, SOCB_INT>;
impl<'a, REG> SOCB_INT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "no interrupt"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(SOCB_INT::None)
}
#[doc = "interrupt"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(SOCB_INT::Interrupt)
}
}
#[doc = "Read buffer overflow\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RDOFL {
#[doc = "0: no read overflow since bit cleared"]
None = 0,
#[doc = "1: read overflow detected, write 1 to clear"]
Overflow = 1,
}
impl From<RDOFL> for bool {
#[inline(always)]
fn from(variant: RDOFL) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RDOFL` reader - Read buffer overflow"]
pub type RDOFL_R = crate::BitReader<RDOFL>;
impl RDOFL_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RDOFL {
match self.bits {
false => RDOFL::None,
true => RDOFL::Overflow,
}
}
#[doc = "no read overflow since bit cleared"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == RDOFL::None
}
#[doc = "read overflow detected, write 1 to clear"]
#[inline(always)]
pub fn is_overflow(&self) -> bool {
*self == RDOFL::Overflow
}
}
#[doc = "Field `RDOFL` writer - Read buffer overflow"]
pub type RDOFL_W<'a, REG> = crate::BitWriter<'a, REG, RDOFL>;
impl<'a, REG> RDOFL_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "no read overflow since bit cleared"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(RDOFL::None)
}
#[doc = "read overflow detected, write 1 to clear"]
#[inline(always)]
pub fn overflow(self) -> &'a mut crate::W<REG> {
self.variant(RDOFL::Overflow)
}
}
#[doc = "Cycle done (current transfer is complete)\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CYC_DONE {
#[doc = "0: No cycle done detected since this bit was cleared"]
NotDone = 0,
#[doc = "1: Cycle done detected, write one to clear"]
Compelted = 1,
}
impl From<CYC_DONE> for bool {
#[inline(always)]
fn from(variant: CYC_DONE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CYC_DONE` reader - Cycle done (current transfer is complete)"]
pub type CYC_DONE_R = crate::BitReader<CYC_DONE>;
impl CYC_DONE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CYC_DONE {
match self.bits {
false => CYC_DONE::NotDone,
true => CYC_DONE::Compelted,
}
}
#[doc = "No cycle done detected since this bit was cleared"]
#[inline(always)]
pub fn is_not_done(&self) -> bool {
*self == CYC_DONE::NotDone
}
#[doc = "Cycle done detected, write one to clear"]
#[inline(always)]
pub fn is_compelted(&self) -> bool {
*self == CYC_DONE::Compelted
}
}
#[doc = "Field `CYC_DONE` writer - Cycle done (current transfer is complete)"]
pub type CYC_DONE_W<'a, REG> = crate::BitWriter<'a, REG, CYC_DONE>;
impl<'a, REG> CYC_DONE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No cycle done detected since this bit was cleared"]
#[inline(always)]
pub fn not_done(self) -> &'a mut crate::W<REG> {
self.variant(CYC_DONE::NotDone)
}
#[doc = "Cycle done detected, write one to clear"]
#[inline(always)]
pub fn compelted(self) -> &'a mut crate::W<REG> {
self.variant(CYC_DONE::Compelted)
}
}
#[doc = "Write buffer underflow\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum WRUFL {
#[doc = "0: No write buffer underflow detected since this bit was cleared"]
None = 0,
#[doc = "1: Write buffer underflow detected, write one to clear"]
Underflow = 1,
}
impl From<WRUFL> for bool {
#[inline(always)]
fn from(variant: WRUFL) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `WRUFL` reader - Write buffer underflow"]
pub type WRUFL_R = crate::BitReader<WRUFL>;
impl WRUFL_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> WRUFL {
match self.bits {
false => WRUFL::None,
true => WRUFL::Underflow,
}
}
#[doc = "No write buffer underflow detected since this bit was cleared"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == WRUFL::None
}
#[doc = "Write buffer underflow detected, write one to clear"]
#[inline(always)]
pub fn is_underflow(&self) -> bool {
*self == WRUFL::Underflow
}
}
#[doc = "Field `WRUFL` writer - Write buffer underflow"]
pub type WRUFL_W<'a, REG> = crate::BitWriter<'a, REG, WRUFL>;
impl<'a, REG> WRUFL_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No write buffer underflow detected since this bit was cleared"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(WRUFL::None)
}
#[doc = "Write buffer underflow detected, write one to clear"]
#[inline(always)]
pub fn underflow(self) -> &'a mut crate::W<REG> {
self.variant(WRUFL::Underflow)
}
}
#[doc = "Transmit holding register in use\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TXFULL {
#[doc = "0: TX transmit holding register ready to accept data word"]
Ready = 0,
#[doc = "1: TX transmit holding register in use and not ready"]
NotReady = 1,
}
impl From<TXFULL> for bool {
#[inline(always)]
fn from(variant: TXFULL) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TXFULL` reader - Transmit holding register in use"]
pub type TXFULL_R = crate::BitReader<TXFULL>;
impl TXFULL_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> TXFULL {
match self.bits {
false => TXFULL::Ready,
true => TXFULL::NotReady,
}
}
#[doc = "TX transmit holding register ready to accept data word"]
#[inline(always)]
pub fn is_ready(&self) -> bool {
*self == TXFULL::Ready
}
#[doc = "TX transmit holding register in use and not ready"]
#[inline(always)]
pub fn is_not_ready(&self) -> bool {
*self == TXFULL::NotReady
}
}
#[doc = "Field `TXFULL` writer - Transmit holding register in use"]
pub type TXFULL_W<'a, REG> = crate::BitWriter<'a, REG, TXFULL>;
impl<'a, REG> TXFULL_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "TX transmit holding register ready to accept data word"]
#[inline(always)]
pub fn ready(self) -> &'a mut crate::W<REG> {
self.variant(TXFULL::Ready)
}
#[doc = "TX transmit holding register in use and not ready"]
#[inline(always)]
pub fn not_ready(self) -> &'a mut crate::W<REG> {
self.variant(TXFULL::NotReady)
}
}
#[doc = "Receive holding register in use\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RXFULL {
#[doc = "0: RX incoming holding register contains no valid data word"]
Empty = 0,
#[doc = "1: RX incoming holding register contains a valid data word"]
Full = 1,
}
impl From<RXFULL> for bool {
#[inline(always)]
fn from(variant: RXFULL) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RXFULL` reader - Receive holding register in use"]
pub type RXFULL_R = crate::BitReader<RXFULL>;
impl RXFULL_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RXFULL {
match self.bits {
false => RXFULL::Empty,
true => RXFULL::Full,
}
}
#[doc = "RX incoming holding register contains no valid data word"]
#[inline(always)]
pub fn is_empty(&self) -> bool {
*self == RXFULL::Empty
}
#[doc = "RX incoming holding register contains a valid data word"]
#[inline(always)]
pub fn is_full(&self) -> bool {
*self == RXFULL::Full
}
}
#[doc = "Field `RXFULL` writer - Receive holding register in use"]
pub type RXFULL_W<'a, REG> = crate::BitWriter<'a, REG, RXFULL>;
impl<'a, REG> RXFULL_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "RX incoming holding register contains no valid data word"]
#[inline(always)]
pub fn empty(self) -> &'a mut crate::W<REG> {
self.variant(RXFULL::Empty)
}
#[doc = "RX incoming holding register contains a valid data word"]
#[inline(always)]
pub fn full(self) -> &'a mut crate::W<REG> {
self.variant(RXFULL::Full)
}
}
#[doc = "Raw status of the SOC bus bridge master state machine's 'current_state' register\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum CURSTATE {
#[doc = "0: IDLE"]
Idle = 0,
#[doc = "1: CSSETUP"]
Cssetup = 1,
#[doc = "2: TRANSFER"]
Transfer = 2,
#[doc = "3: CSHOLD"]
Cshold = 3,
#[doc = "4: CSWAIT"]
Cswait = 4,
#[doc = "5: CKWAIT"]
Ckwait = 5,
#[doc = "6: MTRANS"]
Mtrans = 6,
#[doc = "7: CSBEGIN"]
Csbegin = 7,
}
impl From<CURSTATE> for u8 {
#[inline(always)]
fn from(variant: CURSTATE) -> Self {
variant as _
}
}
impl crate::FieldSpec for CURSTATE {
type Ux = u8;
}
impl crate::IsEnum for CURSTATE {}
#[doc = "Field `CURSTATE` reader - Raw status of the SOC bus bridge master state machine's 'current_state' register"]
pub type CURSTATE_R = crate::FieldReader<CURSTATE>;
impl CURSTATE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CURSTATE {
match self.bits {
0 => CURSTATE::Idle,
1 => CURSTATE::Cssetup,
2 => CURSTATE::Transfer,
3 => CURSTATE::Cshold,
4 => CURSTATE::Cswait,
5 => CURSTATE::Ckwait,
6 => CURSTATE::Mtrans,
7 => CURSTATE::Csbegin,
_ => unreachable!(),
}
}
#[doc = "IDLE"]
#[inline(always)]
pub fn is_idle(&self) -> bool {
*self == CURSTATE::Idle
}
#[doc = "CSSETUP"]
#[inline(always)]
pub fn is_cssetup(&self) -> bool {
*self == CURSTATE::Cssetup
}
#[doc = "TRANSFER"]
#[inline(always)]
pub fn is_transfer(&self) -> bool {
*self == CURSTATE::Transfer
}
#[doc = "CSHOLD"]
#[inline(always)]
pub fn is_cshold(&self) -> bool {
*self == CURSTATE::Cshold
}
#[doc = "CSWAIT"]
#[inline(always)]
pub fn is_cswait(&self) -> bool {
*self == CURSTATE::Cswait
}
#[doc = "CKWAIT"]
#[inline(always)]
pub fn is_ckwait(&self) -> bool {
*self == CURSTATE::Ckwait
}
#[doc = "MTRANS"]
#[inline(always)]
pub fn is_mtrans(&self) -> bool {
*self == CURSTATE::Mtrans
}
#[doc = "CSBEGIN"]
#[inline(always)]
pub fn is_csbegin(&self) -> bool {
*self == CURSTATE::Csbegin
}
}
#[doc = "Field `CURSTATE` writer - Raw status of the SOC bus bridge master state machine's 'current_state' register"]
pub type CURSTATE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CURSTATE, crate::Safe>;
impl<'a, REG> CURSTATE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "IDLE"]
#[inline(always)]
pub fn idle(self) -> &'a mut crate::W<REG> {
self.variant(CURSTATE::Idle)
}
#[doc = "CSSETUP"]
#[inline(always)]
pub fn cssetup(self) -> &'a mut crate::W<REG> {
self.variant(CURSTATE::Cssetup)
}
#[doc = "TRANSFER"]
#[inline(always)]
pub fn transfer(self) -> &'a mut crate::W<REG> {
self.variant(CURSTATE::Transfer)
}
#[doc = "CSHOLD"]
#[inline(always)]
pub fn cshold(self) -> &'a mut crate::W<REG> {
self.variant(CURSTATE::Cshold)
}
#[doc = "CSWAIT"]
#[inline(always)]
pub fn cswait(self) -> &'a mut crate::W<REG> {
self.variant(CURSTATE::Cswait)
}
#[doc = "CKWAIT"]
#[inline(always)]
pub fn ckwait(self) -> &'a mut crate::W<REG> {
self.variant(CURSTATE::Ckwait)
}
#[doc = "MTRANS"]
#[inline(always)]
pub fn mtrans(self) -> &'a mut crate::W<REG> {
self.variant(CURSTATE::Mtrans)
}
#[doc = "CSBEGIN"]
#[inline(always)]
pub fn csbegin(self) -> &'a mut crate::W<REG> {
self.variant(CURSTATE::Csbegin)
}
}
impl R {
#[doc = "Bit 0 - SOC bus bridge interrupt"]
#[inline(always)]
pub fn socb_int(&self) -> SOCB_INT_R {
SOCB_INT_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 2 - Read buffer overflow"]
#[inline(always)]
pub fn rdofl(&self) -> RDOFL_R {
RDOFL_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 5 - Cycle done (current transfer is complete)"]
#[inline(always)]
pub fn cyc_done(&self) -> CYC_DONE_R {
CYC_DONE_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 8 - Write buffer underflow"]
#[inline(always)]
pub fn wrufl(&self) -> WRUFL_R {
WRUFL_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Transmit holding register in use"]
#[inline(always)]
pub fn txfull(&self) -> TXFULL_R {
TXFULL_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Receive holding register in use"]
#[inline(always)]
pub fn rxfull(&self) -> RXFULL_R {
RXFULL_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 12:14 - Raw status of the SOC bus bridge master state machine's 'current_state' register"]
#[inline(always)]
pub fn curstate(&self) -> CURSTATE_R {
CURSTATE_R::new(((self.bits >> 12) & 7) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SOCBSTAT")
.field("socb_int", &self.socb_int())
.field("rdofl", &self.rdofl())
.field("cyc_done", &self.cyc_done())
.field("wrufl", &self.wrufl())
.field("txfull", &self.txfull())
.field("rxfull", &self.rxfull())
.field("curstate", &self.curstate())
.finish()
}
}
impl W {
#[doc = "Bit 0 - SOC bus bridge interrupt"]
#[inline(always)]
pub fn socb_int(&mut self) -> SOCB_INT_W<SOCBSTATrs> {
SOCB_INT_W::new(self, 0)
}
#[doc = "Bit 2 - Read buffer overflow"]
#[inline(always)]
pub fn rdofl(&mut self) -> RDOFL_W<SOCBSTATrs> {
RDOFL_W::new(self, 2)
}
#[doc = "Bit 5 - Cycle done (current transfer is complete)"]
#[inline(always)]
pub fn cyc_done(&mut self) -> CYC_DONE_W<SOCBSTATrs> {
CYC_DONE_W::new(self, 5)
}
#[doc = "Bit 8 - Write buffer underflow"]
#[inline(always)]
pub fn wrufl(&mut self) -> WRUFL_W<SOCBSTATrs> {
WRUFL_W::new(self, 8)
}
#[doc = "Bit 9 - Transmit holding register in use"]
#[inline(always)]
pub fn txfull(&mut self) -> TXFULL_W<SOCBSTATrs> {
TXFULL_W::new(self, 9)
}
#[doc = "Bit 10 - Receive holding register in use"]
#[inline(always)]
pub fn rxfull(&mut self) -> RXFULL_W<SOCBSTATrs> {
RXFULL_W::new(self, 10)
}
#[doc = "Bits 12:14 - Raw status of the SOC bus bridge master state machine's 'current_state' register"]
#[inline(always)]
pub fn curstate(&mut self) -> CURSTATE_W<SOCBSTATrs> {
CURSTATE_W::new(self, 12)
}
}
#[doc = "SOC Bus Bridge Status\n\nYou can [`read`](crate::Reg::read) this register and get [`socbstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`socbstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SOCBSTATrs;
impl crate::RegisterSpec for SOCBSTATrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`socbstat::R`](R) reader structure"]
impl crate::Readable for SOCBSTATrs {}
#[doc = "`write(|w| ..)` method takes [`socbstat::W`](W) writer structure"]
impl crate::Writable for SOCBSTATrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SOCBSTAT to value 0"]
impl crate::Resettable for SOCBSTATrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SOCBD (rw) register accessor: SOC Bus Bridge Data. On READ, retrieve received data word from the incoming holding buffer. On WRITE, write address or data word to the outgoing holding buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`socbd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`socbd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@socbd`]
module"]
pub type SOCBD = crate::Reg<socbd::SOCBDrs>;
#[doc = "SOC Bus Bridge Data. On READ, retrieve received data word from the incoming holding buffer. On WRITE, write address or data word to the outgoing holding buffer"]
pub mod socbd {
#[doc = "Register `SOCBD` reader"]
pub type R = crate::R<SOCBDrs>;
#[doc = "Register `SOCBD` writer"]
pub type W = crate::W<SOCBDrs>;
#[doc = "Field `DATA` reader - SOC bus bridge data"]
pub type DATA_R = crate::FieldReader;
#[doc = "Field `DATA` writer - SOC bus bridge data"]
pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - SOC bus bridge data"]
#[inline(always)]
pub fn data(&self) -> DATA_R {
DATA_R::new((self.bits & 0xff) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SOCBD").field("data", &self.data()).finish()
}
}
impl W {
#[doc = "Bits 0:7 - SOC bus bridge data"]
#[inline(always)]
pub fn data(&mut self) -> DATA_W<SOCBDrs> {
DATA_W::new(self, 0)
}
}
#[doc = "SOC Bus Bridge Data. On READ, retrieve received data word from the incoming holding buffer. On WRITE, write address or data word to the outgoing holding buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`socbd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`socbd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SOCBDrs;
impl crate::RegisterSpec for SOCBDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`socbd::R`](R) reader structure"]
impl crate::Readable for SOCBDrs {}
#[doc = "`write(|w| ..)` method takes [`socbd::W`](W) writer structure"]
impl crate::Writable for SOCBDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SOCBD to value 0"]
impl crate::Resettable for SOCBDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SOCBINT_EN (rw) register accessor: SOC Bus Bridge Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`socbint_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`socbint_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@socbint_en`]
module"]
pub type SOCBINT_EN = crate::Reg<socbint_en::SOCBINT_ENrs>;
#[doc = "SOC Bus Bridge Interrupt Enable"]
pub mod socbint_en {
#[doc = "Register `SOCBINT_EN` reader"]
pub type R = crate::R<SOCBINT_ENrs>;
#[doc = "Register `SOCBINT_EN` writer"]
pub type W = crate::W<SOCBINT_ENrs>;
#[doc = "Read buffer overflow RDOFL interrupt enable\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RDOFL_EN {
#[doc = "0: disable SOCBSTAT.RDOFL interrupt"]
Disable = 0,
#[doc = "1: enable SOCBSTAT.RDOFL interrupt"]
Enable = 1,
}
impl From<RDOFL_EN> for bool {
#[inline(always)]
fn from(variant: RDOFL_EN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RDOFL_EN` reader - Read buffer overflow RDOFL interrupt enable"]
pub type RDOFL_EN_R = crate::BitReader<RDOFL_EN>;
impl RDOFL_EN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RDOFL_EN {
match self.bits {
false => RDOFL_EN::Disable,
true => RDOFL_EN::Enable,
}
}
#[doc = "disable SOCBSTAT.RDOFL interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == RDOFL_EN::Disable
}
#[doc = "enable SOCBSTAT.RDOFL interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == RDOFL_EN::Enable
}
}
#[doc = "Field `RDOFL_EN` writer - Read buffer overflow RDOFL interrupt enable"]
pub type RDOFL_EN_W<'a, REG> = crate::BitWriter<'a, REG, RDOFL_EN>;
impl<'a, REG> RDOFL_EN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable SOCBSTAT.RDOFL interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(RDOFL_EN::Disable)
}
#[doc = "enable SOCBSTAT.RDOFL interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(RDOFL_EN::Enable)
}
}
#[doc = "Write buffer underflow SOCBSTAT.WRUFL interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum WRUFL_EN {
#[doc = "0: disable SOCBSTAT.WRUFL interrupt"]
Disable = 0,
#[doc = "1: enable SOCBSTAT.WRUFL interrupt"]
Enable = 1,
}
impl From<WRUFL_EN> for bool {
#[inline(always)]
fn from(variant: WRUFL_EN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `WRUFL_EN` reader - Write buffer underflow SOCBSTAT.WRUFL interrupt enable"]
pub type WRUFL_EN_R = crate::BitReader<WRUFL_EN>;
impl WRUFL_EN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> WRUFL_EN {
match self.bits {
false => WRUFL_EN::Disable,
true => WRUFL_EN::Enable,
}
}
#[doc = "disable SOCBSTAT.WRUFL interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == WRUFL_EN::Disable
}
#[doc = "enable SOCBSTAT.WRUFL interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == WRUFL_EN::Enable
}
}
#[doc = "Field `WRUFL_EN` writer - Write buffer underflow SOCBSTAT.WRUFL interrupt enable"]
pub type WRUFL_EN_W<'a, REG> = crate::BitWriter<'a, REG, WRUFL_EN>;
impl<'a, REG> WRUFL_EN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable SOCBSTAT.WRUFL interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(WRUFL_EN::Disable)
}
#[doc = "enable SOCBSTAT.WRUFL interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(WRUFL_EN::Enable)
}
}
impl R {
#[doc = "Bit 2 - Read buffer overflow RDOFL interrupt enable"]
#[inline(always)]
pub fn rdofl_en(&self) -> RDOFL_EN_R {
RDOFL_EN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 8 - Write buffer underflow SOCBSTAT.WRUFL interrupt enable"]
#[inline(always)]
pub fn wrufl_en(&self) -> WRUFL_EN_R {
WRUFL_EN_R::new(((self.bits >> 8) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SOCBINT_EN")
.field("rdofl_en", &self.rdofl_en())
.field("wrufl_en", &self.wrufl_en())
.finish()
}
}
impl W {
#[doc = "Bit 2 - Read buffer overflow RDOFL interrupt enable"]
#[inline(always)]
pub fn rdofl_en(&mut self) -> RDOFL_EN_W<SOCBINT_ENrs> {
RDOFL_EN_W::new(self, 2)
}
#[doc = "Bit 8 - Write buffer underflow SOCBSTAT.WRUFL interrupt enable"]
#[inline(always)]
pub fn wrufl_en(&mut self) -> WRUFL_EN_W<SOCBINT_ENrs> {
WRUFL_EN_W::new(self, 8)
}
}
#[doc = "SOC Bus Bridge Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`socbint_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`socbint_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SOCBINT_ENrs;
impl crate::RegisterSpec for SOCBINT_ENrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`socbint_en::R`](R) reader structure"]
impl crate::Readable for SOCBINT_ENrs {}
#[doc = "`write(|w| ..)` method takes [`socbint_en::W`](W) writer structure"]
impl crate::Writable for SOCBINT_ENrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SOCBINT_EN to value 0x3c"]
impl crate::Resettable for SOCBINT_ENrs {
const RESET_VALUE: u32 = 0x3c;
}
}
}
#[doc = "SPI"]
pub struct SPI {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for SPI {}
impl SPI {
#[doc = r"Pointer to the register block"]
pub const PTR: *const spi::RegisterBlock = 0x4021_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const spi::RegisterBlock {
Self::PTR
}
#[doc = r" Steal an instance of this peripheral"]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = r" that may race with any existing instances, for example by only"]
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
#[doc = r" original peripheral and using critical sections to coordinate"]
#[doc = r" access between multiple new instances."]
#[doc = r""]
#[doc = r" Additionally, other software such as HALs may rely on only one"]
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
#[doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: PhantomData,
}
}
}
impl Deref for SPI {
type Target = spi::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for SPI {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI").finish()
}
}
#[doc = "SPI"]
pub mod spi {
#[repr(C)]
#[derive(Debug)]
#[doc = "Register block"]
pub struct RegisterBlock {
spictl: SPICTL,
spicfg: SPICFG,
spiclkdiv: SPICLKDIV,
_reserved3: [u8; 0x08],
spistat: SPISTAT,
spicsstr: SPICSSTR,
spid: SPID,
spiint_en: SPIINT_EN,
}
impl RegisterBlock {
#[doc = "0x00 - SPI Control"]
#[inline(always)]
pub const fn spictl(&self) -> &SPICTL {
&self.spictl
}
#[doc = "0x04 - SPI Configuration"]
#[inline(always)]
pub const fn spicfg(&self) -> &SPICFG {
&self.spicfg
}
#[doc = "0x08 - SPI Clock Divider"]
#[inline(always)]
pub const fn spiclkdiv(&self) -> &SPICLKDIV {
&self.spiclkdiv
}
#[doc = "0x14 - SPI Status"]
#[inline(always)]
pub const fn spistat(&self) -> &SPISTAT {
&self.spistat
}
#[doc = "0x18 - SPI Chip Select Steering Register"]
#[inline(always)]
pub const fn spicsstr(&self) -> &SPICSSTR {
&self.spicsstr
}
#[doc = "0x1c - SPI Data. On READ, retrieve received data word from the incoming holding buffer. On WRITE, write address or data word to the outgoing holding buffer"]
#[inline(always)]
pub const fn spid(&self) -> &SPID {
&self.spid
}
#[doc = "0x20 - SPI Interrupt Enable"]
#[inline(always)]
pub const fn spiint_en(&self) -> &SPIINT_EN {
&self.spiint_en
}
}
#[doc = "SPICTL (rw) register accessor: SPI Control\n\nYou can [`read`](crate::Reg::read) this register and get [`spictl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spictl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spictl`]
module"]
pub type SPICTL = crate::Reg<spictl::SPICTLrs>;
#[doc = "SPI Control"]
pub mod spictl {
#[doc = "Register `SPICTL` reader"]
pub type R = crate::R<SPICTLrs>;
#[doc = "Register `SPICTL` writer"]
pub type W = crate::W<SPICTLrs>;
#[doc = "SPI enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SSEN {
#[doc = "0: disable this module"]
Disable = 0,
#[doc = "1: enable this module"]
Enable = 1,
}
impl From<SSEN> for bool {
#[inline(always)]
fn from(variant: SSEN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SSEN` reader - SPI enable"]
pub type SSEN_R = crate::BitReader<SSEN>;
impl SSEN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SSEN {
match self.bits {
false => SSEN::Disable,
true => SSEN::Enable,
}
}
#[doc = "disable this module"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == SSEN::Disable
}
#[doc = "enable this module"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == SSEN::Enable
}
}
#[doc = "Field `SSEN` writer - SPI enable"]
pub type SSEN_W<'a, REG> = crate::BitWriter<'a, REG, SSEN>;
impl<'a, REG> SSEN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable this module"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(SSEN::Disable)
}
#[doc = "enable this module"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(SSEN::Enable)
}
}
#[doc = "SPI interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SIE {
#[doc = "0: disable interrupts"]
Disable = 0,
#[doc = "1: enable interrupts"]
Enable = 1,
}
impl From<SIE> for bool {
#[inline(always)]
fn from(variant: SIE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SIE` reader - SPI interrupt enable"]
pub type SIE_R = crate::BitReader<SIE>;
impl SIE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SIE {
match self.bits {
false => SIE::Disable,
true => SIE::Enable,
}
}
#[doc = "disable interrupts"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == SIE::Disable
}
#[doc = "enable interrupts"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == SIE::Enable
}
}
#[doc = "Field `SIE` writer - SPI interrupt enable"]
pub type SIE_W<'a, REG> = crate::BitWriter<'a, REG, SIE>;
impl<'a, REG> SIE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable interrupts"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(SIE::Disable)
}
#[doc = "enable interrupts"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(SIE::Enable)
}
}
#[doc = "Internal loopback mode\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum LPBK {
#[doc = "0: normal operation"]
Disabled = 0,
#[doc = "1: tie the serial out source to serial in internally (no IO buffers)"]
Enabled = 1,
}
impl From<LPBK> for bool {
#[inline(always)]
fn from(variant: LPBK) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `LPBK` reader - Internal loopback mode"]
pub type LPBK_R = crate::BitReader<LPBK>;
impl LPBK_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> LPBK {
match self.bits {
false => LPBK::Disabled,
true => LPBK::Enabled,
}
}
#[doc = "normal operation"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == LPBK::Disabled
}
#[doc = "tie the serial out source to serial in internally (no IO buffers)"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == LPBK::Enabled
}
}
#[doc = "Field `LPBK` writer - Internal loopback mode"]
pub type LPBK_W<'a, REG> = crate::BitWriter<'a, REG, LPBK>;
impl<'a, REG> LPBK_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "normal operation"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(LPBK::Disabled)
}
#[doc = "tie the serial out source to serial in internally (no IO buffers)"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(LPBK::Enabled)
}
}
#[doc = "Slave enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SE {
#[doc = "0: SPI is configured as master"]
Disabled = 0,
#[doc = "1: SPI is configured as slave"]
Enabled = 1,
}
impl From<SE> for bool {
#[inline(always)]
fn from(variant: SE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SE` reader - Slave enable"]
pub type SE_R = crate::BitReader<SE>;
impl SE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SE {
match self.bits {
false => SE::Disabled,
true => SE::Enabled,
}
}
#[doc = "SPI is configured as master"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == SE::Disabled
}
#[doc = "SPI is configured as slave"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == SE::Enabled
}
}
#[doc = "Field `SE` writer - Slave enable"]
pub type SE_W<'a, REG> = crate::BitWriter<'a, REG, SE>;
impl<'a, REG> SE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "SPI is configured as master"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(SE::Disabled)
}
#[doc = "SPI is configured as slave"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(SE::Enabled)
}
}
#[doc = "MTRANS re-arm\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MTRARM {
#[doc = "1: re-arms the SOCBCTL.MTRANS operation by de-asserting CSx chip select and returning the master mode state machine to IDLE."]
ReArm = 1,
}
impl From<MTRARM> for bool {
#[inline(always)]
fn from(variant: MTRARM) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MTRARM` writer - MTRANS re-arm"]
pub type MTRARM_W<'a, REG> = crate::BitWriter<'a, REG, MTRARM>;
impl<'a, REG> MTRARM_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "re-arms the SOCBCTL.MTRANS operation by de-asserting CSx chip select and returning the master mode state machine to IDLE."]
#[inline(always)]
pub fn re_arm(self) -> &'a mut crate::W<REG> {
self.variant(MTRARM::ReArm)
}
}
#[doc = "Multiple transfer mode\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MTRANS {
#[doc = "0: Generate single transfers"]
Single = 0,
#[doc = "1: Generate multiple transfers"]
Multiple = 1,
}
impl From<MTRANS> for bool {
#[inline(always)]
fn from(variant: MTRANS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MTRANS` reader - Multiple transfer mode"]
pub type MTRANS_R = crate::BitReader<MTRANS>;
impl MTRANS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MTRANS {
match self.bits {
false => MTRANS::Single,
true => MTRANS::Multiple,
}
}
#[doc = "Generate single transfers"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == MTRANS::Single
}
#[doc = "Generate multiple transfers"]
#[inline(always)]
pub fn is_multiple(&self) -> bool {
*self == MTRANS::Multiple
}
}
#[doc = "Field `MTRANS` writer - Multiple transfer mode"]
pub type MTRANS_W<'a, REG> = crate::BitWriter<'a, REG, MTRANS>;
impl<'a, REG> MTRANS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Generate single transfers"]
#[inline(always)]
pub fn single(self) -> &'a mut crate::W<REG> {
self.variant(MTRANS::Single)
}
#[doc = "Generate multiple transfers"]
#[inline(always)]
pub fn multiple(self) -> &'a mut crate::W<REG> {
self.variant(MTRANS::Multiple)
}
}
#[doc = "Multi-master mode\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MMST_N {
#[doc = "0: Multi-master mode"]
Enabled = 0,
#[doc = "1: Single master mode"]
Disabled = 1,
}
impl From<MMST_N> for bool {
#[inline(always)]
fn from(variant: MMST_N) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MMST_N` reader - Multi-master mode"]
pub type MMST_N_R = crate::BitReader<MMST_N>;
impl MMST_N_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MMST_N {
match self.bits {
false => MMST_N::Enabled,
true => MMST_N::Disabled,
}
}
#[doc = "Multi-master mode"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == MMST_N::Enabled
}
#[doc = "Single master mode"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == MMST_N::Disabled
}
}
#[doc = "Field `MMST_N` writer - Multi-master mode"]
pub type MMST_N_W<'a, REG> = crate::BitWriter<'a, REG, MMST_N>;
impl<'a, REG> MMST_N_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Multi-master mode"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(MMST_N::Enabled)
}
#[doc = "Single master mode"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(MMST_N::Disabled)
}
}
#[doc = "Auto-retrans on clock error\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RTRANS {
#[doc = "0: Retransmit on clock error"]
Enabled = 0,
#[doc = "1: No retransmit on clock error"]
Disabled = 1,
}
impl From<RTRANS> for bool {
#[inline(always)]
fn from(variant: RTRANS) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RTRANS` reader - Auto-retrans on clock error"]
pub type RTRANS_R = crate::BitReader<RTRANS>;
impl RTRANS_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RTRANS {
match self.bits {
false => RTRANS::Enabled,
true => RTRANS::Disabled,
}
}
#[doc = "Retransmit on clock error"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == RTRANS::Enabled
}
#[doc = "No retransmit on clock error"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == RTRANS::Disabled
}
}
#[doc = "Field `RTRANS` writer - Auto-retrans on clock error"]
pub type RTRANS_W<'a, REG> = crate::BitWriter<'a, REG, RTRANS>;
impl<'a, REG> RTRANS_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Retransmit on clock error"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(RTRANS::Enabled)
}
#[doc = "No retransmit on clock error"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(RTRANS::Disabled)
}
}
impl R {
#[doc = "Bit 0 - SPI enable"]
#[inline(always)]
pub fn ssen(&self) -> SSEN_R {
SSEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - SPI interrupt enable"]
#[inline(always)]
pub fn sie(&self) -> SIE_R {
SIE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Internal loopback mode"]
#[inline(always)]
pub fn lpbk(&self) -> LPBK_R {
LPBK_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Slave enable"]
#[inline(always)]
pub fn se(&self) -> SE_R {
SE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 6 - Multiple transfer mode"]
#[inline(always)]
pub fn mtrans(&self) -> MTRANS_R {
MTRANS_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Multi-master mode"]
#[inline(always)]
pub fn mmst_n(&self) -> MMST_N_R {
MMST_N_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Auto-retrans on clock error"]
#[inline(always)]
pub fn rtrans(&self) -> RTRANS_R {
RTRANS_R::new(((self.bits >> 8) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPICTL")
.field("ssen", &self.ssen())
.field("sie", &self.sie())
.field("lpbk", &self.lpbk())
.field("se", &self.se())
.field("mtrans", &self.mtrans())
.field("mmst_n", &self.mmst_n())
.field("rtrans", &self.rtrans())
.finish()
}
}
impl W {
#[doc = "Bit 0 - SPI enable"]
#[inline(always)]
pub fn ssen(&mut self) -> SSEN_W<SPICTLrs> {
SSEN_W::new(self, 0)
}
#[doc = "Bit 1 - SPI interrupt enable"]
#[inline(always)]
pub fn sie(&mut self) -> SIE_W<SPICTLrs> {
SIE_W::new(self, 1)
}
#[doc = "Bit 2 - Internal loopback mode"]
#[inline(always)]
pub fn lpbk(&mut self) -> LPBK_W<SPICTLrs> {
LPBK_W::new(self, 2)
}
#[doc = "Bit 3 - Slave enable"]
#[inline(always)]
pub fn se(&mut self) -> SE_W<SPICTLrs> {
SE_W::new(self, 3)
}
#[doc = "Bit 5 - MTRANS re-arm"]
#[inline(always)]
pub fn mtrarm(&mut self) -> MTRARM_W<SPICTLrs> {
MTRARM_W::new(self, 5)
}
#[doc = "Bit 6 - Multiple transfer mode"]
#[inline(always)]
pub fn mtrans(&mut self) -> MTRANS_W<SPICTLrs> {
MTRANS_W::new(self, 6)
}
#[doc = "Bit 7 - Multi-master mode"]
#[inline(always)]
pub fn mmst_n(&mut self) -> MMST_N_W<SPICTLrs> {
MMST_N_W::new(self, 7)
}
#[doc = "Bit 8 - Auto-retrans on clock error"]
#[inline(always)]
pub fn rtrans(&mut self) -> RTRANS_W<SPICTLrs> {
RTRANS_W::new(self, 8)
}
}
#[doc = "SPI Control\n\nYou can [`read`](crate::Reg::read) this register and get [`spictl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spictl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SPICTLrs;
impl crate::RegisterSpec for SPICTLrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`spictl::R`](R) reader structure"]
impl crate::Readable for SPICTLrs {}
#[doc = "`write(|w| ..)` method takes [`spictl::W`](W) writer structure"]
impl crate::Writable for SPICTLrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SPICTL to value 0"]
impl crate::Resettable for SPICTLrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SPICFG (rw) register accessor: SPI Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`spicfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spicfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spicfg`]
module"]
pub type SPICFG = crate::Reg<spicfg::SPICFGrs>;
#[doc = "SPI Configuration"]
pub mod spicfg {
#[doc = "Register `SPICFG` reader"]
pub type R = crate::R<SPICFGrs>;
#[doc = "Register `SPICFG` writer"]
pub type W = crate::W<SPICFGrs>;
#[doc = "Word length\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum WL {
#[doc = "0: Word Length = 8-bits"]
_8 = 0,
#[doc = "1: Word Length = 16-bits"]
_16 = 1,
#[doc = "2: Word Length = 24-bits"]
_24 = 2,
#[doc = "3: Word Length = 32-bits"]
_32 = 3,
}
impl From<WL> for u8 {
#[inline(always)]
fn from(variant: WL) -> Self {
variant as _
}
}
impl crate::FieldSpec for WL {
type Ux = u8;
}
impl crate::IsEnum for WL {}
#[doc = "Field `WL` reader - Word length"]
pub type WL_R = crate::FieldReader<WL>;
impl WL_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> WL {
match self.bits {
0 => WL::_8,
1 => WL::_16,
2 => WL::_24,
3 => WL::_32,
_ => unreachable!(),
}
}
#[doc = "Word Length = 8-bits"]
#[inline(always)]
pub fn is_8(&self) -> bool {
*self == WL::_8
}
#[doc = "Word Length = 16-bits"]
#[inline(always)]
pub fn is_16(&self) -> bool {
*self == WL::_16
}
#[doc = "Word Length = 24-bits"]
#[inline(always)]
pub fn is_24(&self) -> bool {
*self == WL::_24
}
#[doc = "Word Length = 32-bits"]
#[inline(always)]
pub fn is_32(&self) -> bool {
*self == WL::_32
}
}
#[doc = "Field `WL` writer - Word length"]
pub type WL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, WL, crate::Safe>;
impl<'a, REG> WL_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Word Length = 8-bits"]
#[inline(always)]
pub fn _8(self) -> &'a mut crate::W<REG> {
self.variant(WL::_8)
}
#[doc = "Word Length = 16-bits"]
#[inline(always)]
pub fn _16(self) -> &'a mut crate::W<REG> {
self.variant(WL::_16)
}
#[doc = "Word Length = 24-bits"]
#[inline(always)]
pub fn _24(self) -> &'a mut crate::W<REG> {
self.variant(WL::_24)
}
#[doc = "Word Length = 32-bits"]
#[inline(always)]
pub fn _32(self) -> &'a mut crate::W<REG> {
self.variant(WL::_32)
}
}
#[doc = "Module reset\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MRST {
#[doc = "0: Do not hold module in reset"]
Disabled = 0,
#[doc = "1: Force soft reset of module"]
Enabled = 1,
}
impl From<MRST> for bool {
#[inline(always)]
fn from(variant: MRST) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MRST` reader - Module reset"]
pub type MRST_R = crate::BitReader<MRST>;
impl MRST_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MRST {
match self.bits {
false => MRST::Disabled,
true => MRST::Enabled,
}
}
#[doc = "Do not hold module in reset"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == MRST::Disabled
}
#[doc = "Force soft reset of module"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == MRST::Enabled
}
}
#[doc = "Field `MRST` writer - Module reset"]
pub type MRST_W<'a, REG> = crate::BitWriter<'a, REG, MRST>;
impl<'a, REG> MRST_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Do not hold module in reset"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(MRST::Disabled)
}
#[doc = "Force soft reset of module"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(MRST::Enabled)
}
}
#[doc = "Least bit first\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum LB1ST {
#[doc = "0: MSB is the first serial bit of transfer"]
Msb = 0,
#[doc = "1: LSB is the first serial bit of transfer"]
Lsb = 1,
}
impl From<LB1ST> for bool {
#[inline(always)]
fn from(variant: LB1ST) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `LB1ST` reader - Least bit first"]
pub type LB1ST_R = crate::BitReader<LB1ST>;
impl LB1ST_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> LB1ST {
match self.bits {
false => LB1ST::Msb,
true => LB1ST::Lsb,
}
}
#[doc = "MSB is the first serial bit of transfer"]
#[inline(always)]
pub fn is_msb(&self) -> bool {
*self == LB1ST::Msb
}
#[doc = "LSB is the first serial bit of transfer"]
#[inline(always)]
pub fn is_lsb(&self) -> bool {
*self == LB1ST::Lsb
}
}
#[doc = "Field `LB1ST` writer - Least bit first"]
pub type LB1ST_W<'a, REG> = crate::BitWriter<'a, REG, LB1ST>;
impl<'a, REG> LB1ST_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "MSB is the first serial bit of transfer"]
#[inline(always)]
pub fn msb(self) -> &'a mut crate::W<REG> {
self.variant(LB1ST::Msb)
}
#[doc = "LSB is the first serial bit of transfer"]
#[inline(always)]
pub fn lsb(self) -> &'a mut crate::W<REG> {
self.variant(LB1ST::Lsb)
}
}
#[doc = "Master mode clock polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CP {
#[doc = "0: SPICLK is low in it's inactive state"]
Low = 0,
#[doc = "1: SPICLK is high in it's inactive state"]
High = 1,
}
impl From<CP> for bool {
#[inline(always)]
fn from(variant: CP) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CP` reader - Master mode clock polarity"]
pub type CP_R = crate::BitReader<CP>;
impl CP_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CP {
match self.bits {
false => CP::Low,
true => CP::High,
}
}
#[doc = "SPICLK is low in it's inactive state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == CP::Low
}
#[doc = "SPICLK is high in it's inactive state"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == CP::High
}
}
#[doc = "Field `CP` writer - Master mode clock polarity"]
pub type CP_W<'a, REG> = crate::BitWriter<'a, REG, CP>;
impl<'a, REG> CP_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "SPICLK is low in it's inactive state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(CP::Low)
}
#[doc = "SPICLK is high in it's inactive state"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(CP::High)
}
}
#[doc = "Master mode clock phase\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CPH {
#[doc = "0: First clock transition of a new transfer is used to sample data"]
_1st = 0,
#[doc = "1: Second clock transition of a new transfer is used to sample data"]
_2nd = 1,
}
impl From<CPH> for bool {
#[inline(always)]
fn from(variant: CPH) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CPH` reader - Master mode clock phase"]
pub type CPH_R = crate::BitReader<CPH>;
impl CPH_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CPH {
match self.bits {
false => CPH::_1st,
true => CPH::_2nd,
}
}
#[doc = "First clock transition of a new transfer is used to sample data"]
#[inline(always)]
pub fn is_1st(&self) -> bool {
*self == CPH::_1st
}
#[doc = "Second clock transition of a new transfer is used to sample data"]
#[inline(always)]
pub fn is_2nd(&self) -> bool {
*self == CPH::_2nd
}
}
#[doc = "Field `CPH` writer - Master mode clock phase"]
pub type CPH_W<'a, REG> = crate::BitWriter<'a, REG, CPH>;
impl<'a, REG> CPH_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "First clock transition of a new transfer is used to sample data"]
#[inline(always)]
pub fn _1st(self) -> &'a mut crate::W<REG> {
self.variant(CPH::_1st)
}
#[doc = "Second clock transition of a new transfer is used to sample data"]
#[inline(always)]
pub fn _2nd(self) -> &'a mut crate::W<REG> {
self.variant(CPH::_2nd)
}
}
#[doc = "Slave mode clock polarity\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RCVCP {
#[doc = "0: SPICLK is low in it's inactive state"]
Low = 0,
#[doc = "1: SPICLK is high in it's inactive state"]
High = 1,
}
impl From<RCVCP> for bool {
#[inline(always)]
fn from(variant: RCVCP) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RCVCP` reader - Slave mode clock polarity"]
pub type RCVCP_R = crate::BitReader<RCVCP>;
impl RCVCP_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RCVCP {
match self.bits {
false => RCVCP::Low,
true => RCVCP::High,
}
}
#[doc = "SPICLK is low in it's inactive state"]
#[inline(always)]
pub fn is_low(&self) -> bool {
*self == RCVCP::Low
}
#[doc = "SPICLK is high in it's inactive state"]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == RCVCP::High
}
}
#[doc = "Field `RCVCP` writer - Slave mode clock polarity"]
pub type RCVCP_W<'a, REG> = crate::BitWriter<'a, REG, RCVCP>;
impl<'a, REG> RCVCP_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "SPICLK is low in it's inactive state"]
#[inline(always)]
pub fn low(self) -> &'a mut crate::W<REG> {
self.variant(RCVCP::Low)
}
#[doc = "SPICLK is high in it's inactive state"]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(RCVCP::High)
}
}
#[doc = "Slave mode clock phase\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RCVCPH {
#[doc = "0: First clock transition of a new transfer used to sample data"]
_1st = 0,
#[doc = "1: Second clock transition of a new transfer used to sample data"]
_2nd = 1,
}
impl From<RCVCPH> for bool {
#[inline(always)]
fn from(variant: RCVCPH) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RCVCPH` reader - Slave mode clock phase"]
pub type RCVCPH_R = crate::BitReader<RCVCPH>;
impl RCVCPH_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RCVCPH {
match self.bits {
false => RCVCPH::_1st,
true => RCVCPH::_2nd,
}
}
#[doc = "First clock transition of a new transfer used to sample data"]
#[inline(always)]
pub fn is_1st(&self) -> bool {
*self == RCVCPH::_1st
}
#[doc = "Second clock transition of a new transfer used to sample data"]
#[inline(always)]
pub fn is_2nd(&self) -> bool {
*self == RCVCPH::_2nd
}
}
#[doc = "Field `RCVCPH` writer - Slave mode clock phase"]
pub type RCVCPH_W<'a, REG> = crate::BitWriter<'a, REG, RCVCPH>;
impl<'a, REG> RCVCPH_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "First clock transition of a new transfer used to sample data"]
#[inline(always)]
pub fn _1st(self) -> &'a mut crate::W<REG> {
self.variant(RCVCPH::_1st)
}
#[doc = "Second clock transition of a new transfer used to sample data"]
#[inline(always)]
pub fn _2nd(self) -> &'a mut crate::W<REG> {
self.variant(RCVCPH::_2nd)
}
}
#[doc = "Early transmit data phase\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TXDATPH {
#[doc = "0: Normal transmit data phase, transitions on launch edge of SPICLK"]
Disabled = 0,
#[doc = "1: MISO (slave) or MOSI (Master) transitions occur 1/2 a SPICLK period sooner than normal protocol"]
Enabled = 1,
}
impl From<TXDATPH> for bool {
#[inline(always)]
fn from(variant: TXDATPH) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TXDATPH` reader - Early transmit data phase"]
pub type TXDATPH_R = crate::BitReader<TXDATPH>;
impl TXDATPH_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> TXDATPH {
match self.bits {
false => TXDATPH::Disabled,
true => TXDATPH::Enabled,
}
}
#[doc = "Normal transmit data phase, transitions on launch edge of SPICLK"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == TXDATPH::Disabled
}
#[doc = "MISO (slave) or MOSI (Master) transitions occur 1/2 a SPICLK period sooner than normal protocol"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == TXDATPH::Enabled
}
}
#[doc = "Field `TXDATPH` writer - Early transmit data phase"]
pub type TXDATPH_W<'a, REG> = crate::BitWriter<'a, REG, TXDATPH>;
impl<'a, REG> TXDATPH_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Normal transmit data phase, transitions on launch edge of SPICLK"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(TXDATPH::Disabled)
}
#[doc = "MISO (slave) or MOSI (Master) transitions occur 1/2 a SPICLK period sooner than normal protocol"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(TXDATPH::Enabled)
}
}
#[doc = "Transmit double-buffer mode\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TDBUF {
#[doc = "0: Disable double-buffer, legacy operation with single shift register buffer"]
Disabled = 0,
#[doc = "1: Enable double-buffer 'ping-pong' on shift register transmit output path"]
Enabled = 1,
}
impl From<TDBUF> for bool {
#[inline(always)]
fn from(variant: TDBUF) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TDBUF` reader - Transmit double-buffer mode"]
pub type TDBUF_R = crate::BitReader<TDBUF>;
impl TDBUF_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> TDBUF {
match self.bits {
false => TDBUF::Disabled,
true => TDBUF::Enabled,
}
}
#[doc = "Disable double-buffer, legacy operation with single shift register buffer"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == TDBUF::Disabled
}
#[doc = "Enable double-buffer 'ping-pong' on shift register transmit output path"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == TDBUF::Enabled
}
}
#[doc = "Field `TDBUF` writer - Transmit double-buffer mode"]
pub type TDBUF_W<'a, REG> = crate::BitWriter<'a, REG, TDBUF>;
impl<'a, REG> TDBUF_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable double-buffer, legacy operation with single shift register buffer"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(TDBUF::Disabled)
}
#[doc = "Enable double-buffer 'ping-pong' on shift register transmit output path"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(TDBUF::Enabled)
}
}
#[doc = "Master \"turbo\" operation mode\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MTURBO {
#[doc = "0: Legacy operation down to max 8:1 HCLK:SPICLK ratio"]
Disabled = 0,
#[doc = "1: Enable master turbo mode, using HCLK-based bit count allowing operation down to 2:1 HCLK:SPICLK ratio"]
Enabled = 1,
}
impl From<MTURBO> for bool {
#[inline(always)]
fn from(variant: MTURBO) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MTURBO` reader - Master \"turbo\" operation mode"]
pub type MTURBO_R = crate::BitReader<MTURBO>;
impl MTURBO_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MTURBO {
match self.bits {
false => MTURBO::Disabled,
true => MTURBO::Enabled,
}
}
#[doc = "Legacy operation down to max 8:1 HCLK:SPICLK ratio"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == MTURBO::Disabled
}
#[doc = "Enable master turbo mode, using HCLK-based bit count allowing operation down to 2:1 HCLK:SPICLK ratio"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == MTURBO::Enabled
}
}
#[doc = "Field `MTURBO` writer - Master \"turbo\" operation mode"]
pub type MTURBO_W<'a, REG> = crate::BitWriter<'a, REG, MTURBO>;
impl<'a, REG> MTURBO_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Legacy operation down to max 8:1 HCLK:SPICLK ratio"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(MTURBO::Disabled)
}
#[doc = "Enable master turbo mode, using HCLK-based bit count allowing operation down to 2:1 HCLK:SPICLK ratio"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(MTURBO::Enabled)
}
}
impl R {
#[doc = "Bits 0:1 - Word length"]
#[inline(always)]
pub fn wl(&self) -> WL_R {
WL_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - Module reset"]
#[inline(always)]
pub fn mrst(&self) -> MRST_R {
MRST_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Least bit first"]
#[inline(always)]
pub fn lb1st(&self) -> LB1ST_R {
LB1ST_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Master mode clock polarity"]
#[inline(always)]
pub fn cp(&self) -> CP_R {
CP_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Master mode clock phase"]
#[inline(always)]
pub fn cph(&self) -> CPH_R {
CPH_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Slave mode clock polarity"]
#[inline(always)]
pub fn rcvcp(&self) -> RCVCP_R {
RCVCP_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Slave mode clock phase"]
#[inline(always)]
pub fn rcvcph(&self) -> RCVCPH_R {
RCVCPH_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 9 - Early transmit data phase"]
#[inline(always)]
pub fn txdatph(&self) -> TXDATPH_R {
TXDATPH_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Transmit double-buffer mode"]
#[inline(always)]
pub fn tdbuf(&self) -> TDBUF_R {
TDBUF_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Master \"turbo\" operation mode"]
#[inline(always)]
pub fn mturbo(&self) -> MTURBO_R {
MTURBO_R::new(((self.bits >> 11) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPICFG")
.field("wl", &self.wl())
.field("mrst", &self.mrst())
.field("lb1st", &self.lb1st())
.field("cp", &self.cp())
.field("cph", &self.cph())
.field("rcvcp", &self.rcvcp())
.field("rcvcph", &self.rcvcph())
.field("txdatph", &self.txdatph())
.field("tdbuf", &self.tdbuf())
.field("mturbo", &self.mturbo())
.finish()
}
}
impl W {
#[doc = "Bits 0:1 - Word length"]
#[inline(always)]
pub fn wl(&mut self) -> WL_W<SPICFGrs> {
WL_W::new(self, 0)
}
#[doc = "Bit 2 - Module reset"]
#[inline(always)]
pub fn mrst(&mut self) -> MRST_W<SPICFGrs> {
MRST_W::new(self, 2)
}
#[doc = "Bit 3 - Least bit first"]
#[inline(always)]
pub fn lb1st(&mut self) -> LB1ST_W<SPICFGrs> {
LB1ST_W::new(self, 3)
}
#[doc = "Bit 4 - Master mode clock polarity"]
#[inline(always)]
pub fn cp(&mut self) -> CP_W<SPICFGrs> {
CP_W::new(self, 4)
}
#[doc = "Bit 5 - Master mode clock phase"]
#[inline(always)]
pub fn cph(&mut self) -> CPH_W<SPICFGrs> {
CPH_W::new(self, 5)
}
#[doc = "Bit 6 - Slave mode clock polarity"]
#[inline(always)]
pub fn rcvcp(&mut self) -> RCVCP_W<SPICFGrs> {
RCVCP_W::new(self, 6)
}
#[doc = "Bit 7 - Slave mode clock phase"]
#[inline(always)]
pub fn rcvcph(&mut self) -> RCVCPH_W<SPICFGrs> {
RCVCPH_W::new(self, 7)
}
#[doc = "Bit 9 - Early transmit data phase"]
#[inline(always)]
pub fn txdatph(&mut self) -> TXDATPH_W<SPICFGrs> {
TXDATPH_W::new(self, 9)
}
#[doc = "Bit 10 - Transmit double-buffer mode"]
#[inline(always)]
pub fn tdbuf(&mut self) -> TDBUF_W<SPICFGrs> {
TDBUF_W::new(self, 10)
}
#[doc = "Bit 11 - Master \"turbo\" operation mode"]
#[inline(always)]
pub fn mturbo(&mut self) -> MTURBO_W<SPICFGrs> {
MTURBO_W::new(self, 11)
}
}
#[doc = "SPI Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`spicfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spicfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SPICFGrs;
impl crate::RegisterSpec for SPICFGrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`spicfg::R`](R) reader structure"]
impl crate::Readable for SPICFGrs {}
#[doc = "`write(|w| ..)` method takes [`spicfg::W`](W) writer structure"]
impl crate::Writable for SPICFGrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SPICFG to value 0"]
impl crate::Resettable for SPICFGrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SPICLKDIV (rw) register accessor: SPI Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`spiclkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spiclkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spiclkdiv`]
module"]
pub type SPICLKDIV = crate::Reg<spiclkdiv::SPICLKDIVrs>;
#[doc = "SPI Clock Divider"]
pub mod spiclkdiv {
#[doc = "Register `SPICLKDIV` reader"]
pub type R = crate::R<SPICLKDIVrs>;
#[doc = "Register `SPICLKDIV` writer"]
pub type W = crate::W<SPICLKDIVrs>;
#[doc = "Field `CLKDIV` reader - Clock divisor for SCLK (HCLK / (CLKDIV + 1)*2)"]
pub type CLKDIV_R = crate::FieldReader<u16>;
#[doc = "Field `CLKDIV` writer - Clock divisor for SCLK (HCLK / (CLKDIV + 1)*2)"]
pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Clock divisor for SCLK (HCLK / (CLKDIV + 1)*2)"]
#[inline(always)]
pub fn clkdiv(&self) -> CLKDIV_R {
CLKDIV_R::new((self.bits & 0xffff) as u16)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPICLKDIV")
.field("clkdiv", &self.clkdiv())
.finish()
}
}
impl W {
#[doc = "Bits 0:15 - Clock divisor for SCLK (HCLK / (CLKDIV + 1)*2)"]
#[inline(always)]
pub fn clkdiv(&mut self) -> CLKDIV_W<SPICLKDIVrs> {
CLKDIV_W::new(self, 0)
}
}
#[doc = "SPI Clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`spiclkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spiclkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SPICLKDIVrs;
impl crate::RegisterSpec for SPICLKDIVrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`spiclkdiv::R`](R) reader structure"]
impl crate::Readable for SPICLKDIVrs {}
#[doc = "`write(|w| ..)` method takes [`spiclkdiv::W`](W) writer structure"]
impl crate::Writable for SPICLKDIVrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SPICLKDIV to value 0"]
impl crate::Resettable for SPICLKDIVrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SPISTAT (rw) register accessor: SPI Status\n\nYou can [`read`](crate::Reg::read) this register and get [`spistat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spistat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spistat`]
module"]
pub type SPISTAT = crate::Reg<spistat::SPISTATrs>;
#[doc = "SPI Status"]
pub mod spistat {
#[doc = "Register `SPISTAT` reader"]
pub type R = crate::R<SPISTATrs>;
#[doc = "Register `SPISTAT` writer"]
pub type W = crate::W<SPISTATrs>;
#[doc = "SPI interrupt\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SPI_INT {
#[doc = "0: no interrupt"]
None = 0,
#[doc = "1: interrupt"]
Interrupt = 1,
}
impl From<SPI_INT> for bool {
#[inline(always)]
fn from(variant: SPI_INT) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SPI_INT` reader - SPI interrupt"]
pub type SPI_INT_R = crate::BitReader<SPI_INT>;
impl SPI_INT_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SPI_INT {
match self.bits {
false => SPI_INT::None,
true => SPI_INT::Interrupt,
}
}
#[doc = "no interrupt"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == SPI_INT::None
}
#[doc = "interrupt"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == SPI_INT::Interrupt
}
}
#[doc = "Field `SPI_INT` writer - SPI interrupt"]
pub type SPI_INT_W<'a, REG> = crate::BitWriter<'a, REG, SPI_INT>;
impl<'a, REG> SPI_INT_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "no interrupt"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(SPI_INT::None)
}
#[doc = "interrupt"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(SPI_INT::Interrupt)
}
}
#[doc = "Read buffer overflow\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RDOFL {
#[doc = "0: no read overflow since bit cleared"]
None = 0,
#[doc = "1: read overflow detected, write 1 to clear"]
Overflow = 1,
}
impl From<RDOFL> for bool {
#[inline(always)]
fn from(variant: RDOFL) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RDOFL` reader - Read buffer overflow"]
pub type RDOFL_R = crate::BitReader<RDOFL>;
impl RDOFL_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RDOFL {
match self.bits {
false => RDOFL::None,
true => RDOFL::Overflow,
}
}
#[doc = "no read overflow since bit cleared"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == RDOFL::None
}
#[doc = "read overflow detected, write 1 to clear"]
#[inline(always)]
pub fn is_overflow(&self) -> bool {
*self == RDOFL::Overflow
}
}
#[doc = "Field `RDOFL` writer - Read buffer overflow"]
pub type RDOFL_W<'a, REG> = crate::BitWriter<'a, REG, RDOFL>;
impl<'a, REG> RDOFL_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "no read overflow since bit cleared"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(RDOFL::None)
}
#[doc = "read overflow detected, write 1 to clear"]
#[inline(always)]
pub fn overflow(self) -> &'a mut crate::W<REG> {
self.variant(RDOFL::Overflow)
}
}
#[doc = "Chip select leading edge detect\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum LE {
#[doc = "0: No chip select assertion detected since this bit was cleared"]
None = 0,
#[doc = "1: Chip select assertion detected, write 1 to clear"]
Detected = 1,
}
impl From<LE> for bool {
#[inline(always)]
fn from(variant: LE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `LE` reader - Chip select leading edge detect"]
pub type LE_R = crate::BitReader<LE>;
impl LE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> LE {
match self.bits {
false => LE::None,
true => LE::Detected,
}
}
#[doc = "No chip select assertion detected since this bit was cleared"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == LE::None
}
#[doc = "Chip select assertion detected, write 1 to clear"]
#[inline(always)]
pub fn is_detected(&self) -> bool {
*self == LE::Detected
}
}
#[doc = "Field `LE` writer - Chip select leading edge detect"]
pub type LE_W<'a, REG> = crate::BitWriter<'a, REG, LE>;
impl<'a, REG> LE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No chip select assertion detected since this bit was cleared"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(LE::None)
}
#[doc = "Chip select assertion detected, write 1 to clear"]
#[inline(always)]
pub fn detected(self) -> &'a mut crate::W<REG> {
self.variant(LE::Detected)
}
}
#[doc = "Underclock condition\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum UCLK {
#[doc = "0: No underclock detected since this bit was cleared"]
None = 0,
#[doc = "1: Underclock condition detected, write 1 to clear"]
Detected = 1,
}
impl From<UCLK> for bool {
#[inline(always)]
fn from(variant: UCLK) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `UCLK` reader - Underclock condition"]
pub type UCLK_R = crate::BitReader<UCLK>;
impl UCLK_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> UCLK {
match self.bits {
false => UCLK::None,
true => UCLK::Detected,
}
}
#[doc = "No underclock detected since this bit was cleared"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == UCLK::None
}
#[doc = "Underclock condition detected, write 1 to clear"]
#[inline(always)]
pub fn is_detected(&self) -> bool {
*self == UCLK::Detected
}
}
#[doc = "Field `UCLK` writer - Underclock condition"]
pub type UCLK_W<'a, REG> = crate::BitWriter<'a, REG, UCLK>;
impl<'a, REG> UCLK_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No underclock detected since this bit was cleared"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(UCLK::None)
}
#[doc = "Underclock condition detected, write 1 to clear"]
#[inline(always)]
pub fn detected(self) -> &'a mut crate::W<REG> {
self.variant(UCLK::Detected)
}
}
#[doc = "Cycle done (current transfer is complete)\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CYC_DONE {
#[doc = "0: No cycle done detected since this bit was cleared"]
NotDone = 0,
#[doc = "1: Cycle done detected, write one to clear"]
Compelted = 1,
}
impl From<CYC_DONE> for bool {
#[inline(always)]
fn from(variant: CYC_DONE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CYC_DONE` reader - Cycle done (current transfer is complete)"]
pub type CYC_DONE_R = crate::BitReader<CYC_DONE>;
impl CYC_DONE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CYC_DONE {
match self.bits {
false => CYC_DONE::NotDone,
true => CYC_DONE::Compelted,
}
}
#[doc = "No cycle done detected since this bit was cleared"]
#[inline(always)]
pub fn is_not_done(&self) -> bool {
*self == CYC_DONE::NotDone
}
#[doc = "Cycle done detected, write one to clear"]
#[inline(always)]
pub fn is_compelted(&self) -> bool {
*self == CYC_DONE::Compelted
}
}
#[doc = "Field `CYC_DONE` writer - Cycle done (current transfer is complete)"]
pub type CYC_DONE_W<'a, REG> = crate::BitWriter<'a, REG, CYC_DONE>;
impl<'a, REG> CYC_DONE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No cycle done detected since this bit was cleared"]
#[inline(always)]
pub fn not_done(self) -> &'a mut crate::W<REG> {
self.variant(CYC_DONE::NotDone)
}
#[doc = "Cycle done detected, write one to clear"]
#[inline(always)]
pub fn compelted(self) -> &'a mut crate::W<REG> {
self.variant(CYC_DONE::Compelted)
}
}
#[doc = "Chip select trailing edge detect\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TE {
#[doc = "0: No chip select de-assertion detected since this bit was cleared"]
None = 0,
#[doc = "1: Chip select de-assertion was detected, write 1 to clear"]
Detected = 1,
}
impl From<TE> for bool {
#[inline(always)]
fn from(variant: TE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TE` reader - Chip select trailing edge detect"]
pub type TE_R = crate::BitReader<TE>;
impl TE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> TE {
match self.bits {
false => TE::None,
true => TE::Detected,
}
}
#[doc = "No chip select de-assertion detected since this bit was cleared"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == TE::None
}
#[doc = "Chip select de-assertion was detected, write 1 to clear"]
#[inline(always)]
pub fn is_detected(&self) -> bool {
*self == TE::Detected
}
}
#[doc = "Field `TE` writer - Chip select trailing edge detect"]
pub type TE_W<'a, REG> = crate::BitWriter<'a, REG, TE>;
impl<'a, REG> TE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No chip select de-assertion detected since this bit was cleared"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(TE::None)
}
#[doc = "Chip select de-assertion was detected, write 1 to clear"]
#[inline(always)]
pub fn detected(self) -> &'a mut crate::W<REG> {
self.variant(TE::Detected)
}
}
#[doc = "Write buffer underflow\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum WRUFL {
#[doc = "0: No write buffer underflow detected since this bit was cleared"]
None = 0,
#[doc = "1: Write buffer underflow detected, write one to clear"]
Underflow = 1,
}
impl From<WRUFL> for bool {
#[inline(always)]
fn from(variant: WRUFL) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `WRUFL` reader - Write buffer underflow"]
pub type WRUFL_R = crate::BitReader<WRUFL>;
impl WRUFL_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> WRUFL {
match self.bits {
false => WRUFL::None,
true => WRUFL::Underflow,
}
}
#[doc = "No write buffer underflow detected since this bit was cleared"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == WRUFL::None
}
#[doc = "Write buffer underflow detected, write one to clear"]
#[inline(always)]
pub fn is_underflow(&self) -> bool {
*self == WRUFL::Underflow
}
}
#[doc = "Field `WRUFL` writer - Write buffer underflow"]
pub type WRUFL_W<'a, REG> = crate::BitWriter<'a, REG, WRUFL>;
impl<'a, REG> WRUFL_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "No write buffer underflow detected since this bit was cleared"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(WRUFL::None)
}
#[doc = "Write buffer underflow detected, write one to clear"]
#[inline(always)]
pub fn underflow(self) -> &'a mut crate::W<REG> {
self.variant(WRUFL::Underflow)
}
}
#[doc = "Transmit holding register in use\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TXFULL {
#[doc = "0: TX transmit holding register ready to accept data word"]
Ready = 0,
#[doc = "1: TX transmit holding register in use and not ready"]
NotReady = 1,
}
impl From<TXFULL> for bool {
#[inline(always)]
fn from(variant: TXFULL) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TXFULL` reader - Transmit holding register in use"]
pub type TXFULL_R = crate::BitReader<TXFULL>;
impl TXFULL_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> TXFULL {
match self.bits {
false => TXFULL::Ready,
true => TXFULL::NotReady,
}
}
#[doc = "TX transmit holding register ready to accept data word"]
#[inline(always)]
pub fn is_ready(&self) -> bool {
*self == TXFULL::Ready
}
#[doc = "TX transmit holding register in use and not ready"]
#[inline(always)]
pub fn is_not_ready(&self) -> bool {
*self == TXFULL::NotReady
}
}
#[doc = "Field `TXFULL` writer - Transmit holding register in use"]
pub type TXFULL_W<'a, REG> = crate::BitWriter<'a, REG, TXFULL>;
impl<'a, REG> TXFULL_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "TX transmit holding register ready to accept data word"]
#[inline(always)]
pub fn ready(self) -> &'a mut crate::W<REG> {
self.variant(TXFULL::Ready)
}
#[doc = "TX transmit holding register in use and not ready"]
#[inline(always)]
pub fn not_ready(self) -> &'a mut crate::W<REG> {
self.variant(TXFULL::NotReady)
}
}
#[doc = "Receive holding register in use\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RXFULL {
#[doc = "0: RX incoming holding register contains no valid data word"]
Empty = 0,
#[doc = "1: RX incoming holding register contains a valid data word"]
Full = 1,
}
impl From<RXFULL> for bool {
#[inline(always)]
fn from(variant: RXFULL) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RXFULL` reader - Receive holding register in use"]
pub type RXFULL_R = crate::BitReader<RXFULL>;
impl RXFULL_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RXFULL {
match self.bits {
false => RXFULL::Empty,
true => RXFULL::Full,
}
}
#[doc = "RX incoming holding register contains no valid data word"]
#[inline(always)]
pub fn is_empty(&self) -> bool {
*self == RXFULL::Empty
}
#[doc = "RX incoming holding register contains a valid data word"]
#[inline(always)]
pub fn is_full(&self) -> bool {
*self == RXFULL::Full
}
}
#[doc = "Field `RXFULL` writer - Receive holding register in use"]
pub type RXFULL_W<'a, REG> = crate::BitWriter<'a, REG, RXFULL>;
impl<'a, REG> RXFULL_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "RX incoming holding register contains no valid data word"]
#[inline(always)]
pub fn empty(self) -> &'a mut crate::W<REG> {
self.variant(RXFULL::Empty)
}
#[doc = "RX incoming holding register contains a valid data word"]
#[inline(always)]
pub fn full(self) -> &'a mut crate::W<REG> {
self.variant(RXFULL::Full)
}
}
#[doc = "Raw status of the SOC bus bridge master state machine's 'current_state' register\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum CURSTATE {
#[doc = "0: IDLE"]
Idle = 0,
#[doc = "1: CSSETUP"]
Cssetup = 1,
#[doc = "2: TRANSFER"]
Transfer = 2,
#[doc = "3: CSHOLD"]
Cshold = 3,
#[doc = "4: CSWAIT"]
Cswait = 4,
#[doc = "5: CKWAIT"]
Ckwait = 5,
#[doc = "6: MTRANS"]
Mtrans = 6,
#[doc = "7: CSBEGIN"]
Csbegin = 7,
}
impl From<CURSTATE> for u8 {
#[inline(always)]
fn from(variant: CURSTATE) -> Self {
variant as _
}
}
impl crate::FieldSpec for CURSTATE {
type Ux = u8;
}
impl crate::IsEnum for CURSTATE {}
#[doc = "Field `CURSTATE` reader - Raw status of the SOC bus bridge master state machine's 'current_state' register"]
pub type CURSTATE_R = crate::FieldReader<CURSTATE>;
impl CURSTATE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CURSTATE {
match self.bits {
0 => CURSTATE::Idle,
1 => CURSTATE::Cssetup,
2 => CURSTATE::Transfer,
3 => CURSTATE::Cshold,
4 => CURSTATE::Cswait,
5 => CURSTATE::Ckwait,
6 => CURSTATE::Mtrans,
7 => CURSTATE::Csbegin,
_ => unreachable!(),
}
}
#[doc = "IDLE"]
#[inline(always)]
pub fn is_idle(&self) -> bool {
*self == CURSTATE::Idle
}
#[doc = "CSSETUP"]
#[inline(always)]
pub fn is_cssetup(&self) -> bool {
*self == CURSTATE::Cssetup
}
#[doc = "TRANSFER"]
#[inline(always)]
pub fn is_transfer(&self) -> bool {
*self == CURSTATE::Transfer
}
#[doc = "CSHOLD"]
#[inline(always)]
pub fn is_cshold(&self) -> bool {
*self == CURSTATE::Cshold
}
#[doc = "CSWAIT"]
#[inline(always)]
pub fn is_cswait(&self) -> bool {
*self == CURSTATE::Cswait
}
#[doc = "CKWAIT"]
#[inline(always)]
pub fn is_ckwait(&self) -> bool {
*self == CURSTATE::Ckwait
}
#[doc = "MTRANS"]
#[inline(always)]
pub fn is_mtrans(&self) -> bool {
*self == CURSTATE::Mtrans
}
#[doc = "CSBEGIN"]
#[inline(always)]
pub fn is_csbegin(&self) -> bool {
*self == CURSTATE::Csbegin
}
}
#[doc = "Field `CURSTATE` writer - Raw status of the SOC bus bridge master state machine's 'current_state' register"]
pub type CURSTATE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CURSTATE, crate::Safe>;
impl<'a, REG> CURSTATE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "IDLE"]
#[inline(always)]
pub fn idle(self) -> &'a mut crate::W<REG> {
self.variant(CURSTATE::Idle)
}
#[doc = "CSSETUP"]
#[inline(always)]
pub fn cssetup(self) -> &'a mut crate::W<REG> {
self.variant(CURSTATE::Cssetup)
}
#[doc = "TRANSFER"]
#[inline(always)]
pub fn transfer(self) -> &'a mut crate::W<REG> {
self.variant(CURSTATE::Transfer)
}
#[doc = "CSHOLD"]
#[inline(always)]
pub fn cshold(self) -> &'a mut crate::W<REG> {
self.variant(CURSTATE::Cshold)
}
#[doc = "CSWAIT"]
#[inline(always)]
pub fn cswait(self) -> &'a mut crate::W<REG> {
self.variant(CURSTATE::Cswait)
}
#[doc = "CKWAIT"]
#[inline(always)]
pub fn ckwait(self) -> &'a mut crate::W<REG> {
self.variant(CURSTATE::Ckwait)
}
#[doc = "MTRANS"]
#[inline(always)]
pub fn mtrans(self) -> &'a mut crate::W<REG> {
self.variant(CURSTATE::Mtrans)
}
#[doc = "CSBEGIN"]
#[inline(always)]
pub fn csbegin(self) -> &'a mut crate::W<REG> {
self.variant(CURSTATE::Csbegin)
}
}
impl R {
#[doc = "Bit 0 - SPI interrupt"]
#[inline(always)]
pub fn spi_int(&self) -> SPI_INT_R {
SPI_INT_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 2 - Read buffer overflow"]
#[inline(always)]
pub fn rdofl(&self) -> RDOFL_R {
RDOFL_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Chip select leading edge detect"]
#[inline(always)]
pub fn le(&self) -> LE_R {
LE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Underclock condition"]
#[inline(always)]
pub fn uclk(&self) -> UCLK_R {
UCLK_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Cycle done (current transfer is complete)"]
#[inline(always)]
pub fn cyc_done(&self) -> CYC_DONE_R {
CYC_DONE_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Chip select trailing edge detect"]
#[inline(always)]
pub fn te(&self) -> TE_R {
TE_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 8 - Write buffer underflow"]
#[inline(always)]
pub fn wrufl(&self) -> WRUFL_R {
WRUFL_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Transmit holding register in use"]
#[inline(always)]
pub fn txfull(&self) -> TXFULL_R {
TXFULL_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Receive holding register in use"]
#[inline(always)]
pub fn rxfull(&self) -> RXFULL_R {
RXFULL_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 12:14 - Raw status of the SOC bus bridge master state machine's 'current_state' register"]
#[inline(always)]
pub fn curstate(&self) -> CURSTATE_R {
CURSTATE_R::new(((self.bits >> 12) & 7) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPISTAT")
.field("spi_int", &self.spi_int())
.field("rdofl", &self.rdofl())
.field("le", &self.le())
.field("uclk", &self.uclk())
.field("cyc_done", &self.cyc_done())
.field("te", &self.te())
.field("wrufl", &self.wrufl())
.field("txfull", &self.txfull())
.field("rxfull", &self.rxfull())
.field("curstate", &self.curstate())
.finish()
}
}
impl W {
#[doc = "Bit 0 - SPI interrupt"]
#[inline(always)]
pub fn spi_int(&mut self) -> SPI_INT_W<SPISTATrs> {
SPI_INT_W::new(self, 0)
}
#[doc = "Bit 2 - Read buffer overflow"]
#[inline(always)]
pub fn rdofl(&mut self) -> RDOFL_W<SPISTATrs> {
RDOFL_W::new(self, 2)
}
#[doc = "Bit 3 - Chip select leading edge detect"]
#[inline(always)]
pub fn le(&mut self) -> LE_W<SPISTATrs> {
LE_W::new(self, 3)
}
#[doc = "Bit 4 - Underclock condition"]
#[inline(always)]
pub fn uclk(&mut self) -> UCLK_W<SPISTATrs> {
UCLK_W::new(self, 4)
}
#[doc = "Bit 5 - Cycle done (current transfer is complete)"]
#[inline(always)]
pub fn cyc_done(&mut self) -> CYC_DONE_W<SPISTATrs> {
CYC_DONE_W::new(self, 5)
}
#[doc = "Bit 6 - Chip select trailing edge detect"]
#[inline(always)]
pub fn te(&mut self) -> TE_W<SPISTATrs> {
TE_W::new(self, 6)
}
#[doc = "Bit 8 - Write buffer underflow"]
#[inline(always)]
pub fn wrufl(&mut self) -> WRUFL_W<SPISTATrs> {
WRUFL_W::new(self, 8)
}
#[doc = "Bit 9 - Transmit holding register in use"]
#[inline(always)]
pub fn txfull(&mut self) -> TXFULL_W<SPISTATrs> {
TXFULL_W::new(self, 9)
}
#[doc = "Bit 10 - Receive holding register in use"]
#[inline(always)]
pub fn rxfull(&mut self) -> RXFULL_W<SPISTATrs> {
RXFULL_W::new(self, 10)
}
#[doc = "Bits 12:14 - Raw status of the SOC bus bridge master state machine's 'current_state' register"]
#[inline(always)]
pub fn curstate(&mut self) -> CURSTATE_W<SPISTATrs> {
CURSTATE_W::new(self, 12)
}
}
#[doc = "SPI Status\n\nYou can [`read`](crate::Reg::read) this register and get [`spistat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spistat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SPISTATrs;
impl crate::RegisterSpec for SPISTATrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`spistat::R`](R) reader structure"]
impl crate::Readable for SPISTATrs {}
#[doc = "`write(|w| ..)` method takes [`spistat::W`](W) writer structure"]
impl crate::Writable for SPISTATrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SPISTAT to value 0"]
impl crate::Resettable for SPISTATrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SPICSSTR (rw) register accessor: SPI Chip Select Steering Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spicsstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spicsstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spicsstr`]
module"]
pub type SPICSSTR = crate::Reg<spicsstr::SPICSSTRrs>;
#[doc = "SPI Chip Select Steering Register"]
pub mod spicsstr {
#[doc = "Register `SPICSSTR` reader"]
pub type R = crate::R<SPICSSTRrs>;
#[doc = "Register `SPICSSTR` writer"]
pub type W = crate::W<SPICSSTRrs>;
#[doc = "Chip select number\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum CSNUM {
#[doc = "0: SPICS0"]
Spics0 = 0,
#[doc = "1: SPICS1"]
Spics1 = 1,
#[doc = "2: SPICS2"]
Spics2 = 2,
}
impl From<CSNUM> for u8 {
#[inline(always)]
fn from(variant: CSNUM) -> Self {
variant as _
}
}
impl crate::FieldSpec for CSNUM {
type Ux = u8;
}
impl crate::IsEnum for CSNUM {}
#[doc = "Field `CSNUM` reader - Chip select number"]
pub type CSNUM_R = crate::FieldReader<CSNUM>;
impl CSNUM_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<CSNUM> {
match self.bits {
0 => Some(CSNUM::Spics0),
1 => Some(CSNUM::Spics1),
2 => Some(CSNUM::Spics2),
_ => None,
}
}
#[doc = "SPICS0"]
#[inline(always)]
pub fn is_spics0(&self) -> bool {
*self == CSNUM::Spics0
}
#[doc = "SPICS1"]
#[inline(always)]
pub fn is_spics1(&self) -> bool {
*self == CSNUM::Spics1
}
#[doc = "SPICS2"]
#[inline(always)]
pub fn is_spics2(&self) -> bool {
*self == CSNUM::Spics2
}
}
#[doc = "Field `CSNUM` writer - Chip select number"]
pub type CSNUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CSNUM>;
impl<'a, REG> CSNUM_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "SPICS0"]
#[inline(always)]
pub fn spics0(self) -> &'a mut crate::W<REG> {
self.variant(CSNUM::Spics0)
}
#[doc = "SPICS1"]
#[inline(always)]
pub fn spics1(self) -> &'a mut crate::W<REG> {
self.variant(CSNUM::Spics1)
}
#[doc = "SPICS2"]
#[inline(always)]
pub fn spics2(self) -> &'a mut crate::W<REG> {
self.variant(CSNUM::Spics2)
}
}
#[doc = "Chip select active high level select\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CSL {
#[doc = "0: Active-low outgoing (master) or incoming (slave) chip select"]
ActiveLow = 0,
#[doc = "1: Active-high outgoing (master) or incoming (slave) ship select"]
ActiveHigh = 1,
}
impl From<CSL> for bool {
#[inline(always)]
fn from(variant: CSL) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CSL` reader - Chip select active high level select"]
pub type CSL_R = crate::BitReader<CSL>;
impl CSL_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CSL {
match self.bits {
false => CSL::ActiveLow,
true => CSL::ActiveHigh,
}
}
#[doc = "Active-low outgoing (master) or incoming (slave) chip select"]
#[inline(always)]
pub fn is_active_low(&self) -> bool {
*self == CSL::ActiveLow
}
#[doc = "Active-high outgoing (master) or incoming (slave) ship select"]
#[inline(always)]
pub fn is_active_high(&self) -> bool {
*self == CSL::ActiveHigh
}
}
#[doc = "Field `CSL` writer - Chip select active high level select"]
pub type CSL_W<'a, REG> = crate::BitWriter<'a, REG, CSL>;
impl<'a, REG> CSL_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Active-low outgoing (master) or incoming (slave) chip select"]
#[inline(always)]
pub fn active_low(self) -> &'a mut crate::W<REG> {
self.variant(CSL::ActiveLow)
}
#[doc = "Active-high outgoing (master) or incoming (slave) ship select"]
#[inline(always)]
pub fn active_high(self) -> &'a mut crate::W<REG> {
self.variant(CSL::ActiveHigh)
}
}
#[doc = "Field `CSSETUP` reader - Chip select setup. Minimum number of SPICLK periods to wait from assertion of CS<n> to the first SPICLK transition"]
pub type CSSETUP_R = crate::FieldReader;
#[doc = "Field `CSSETUP` writer - Chip select setup. Minimum number of SPICLK periods to wait from assertion of CS<n> to the first SPICLK transition"]
pub type CSSETUP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `CSHOLD` reader - Chip select hold. Minimum number of SPICLK periods to wait from the last SPICLK transition to de-assertion of CS<n>"]
pub type CSHOLD_R = crate::FieldReader;
#[doc = "Field `CSHOLD` writer - Chip select hold. Minimum number of SPICLK periods to wait from the last SPICLK transition to de-assertion of CS<n>"]
pub type CSHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `CSWAIT` reader - Chip select wait. The minimum number of SPICLK periods to wait between the de-assertion of CS<n> and the re-assertion of CS<n>"]
pub type CSWAIT_R = crate::FieldReader;
#[doc = "Field `CSWAIT` writer - Chip select wait. The minimum number of SPICLK periods to wait between the de-assertion of CS<n> and the re-assertion of CS<n>"]
pub type CSWAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `CKWAIT` reader - SPI clock wait. Only applies if SPICTL.MTRANS=1b(multiple transfers with one chip select assertion). This value determines the minimum number of SPICLK periods to wait between back-to-back transfers. During this wait time, SPICLK does not toggle but CSx remains active."]
pub type CKWAIT_R = crate::FieldReader;
#[doc = "Field `CKWAIT` writer - SPI clock wait. Only applies if SPICTL.MTRANS=1b(multiple transfers with one chip select assertion). This value determines the minimum number of SPICLK periods to wait between back-to-back transfers. During this wait time, SPICLK does not toggle but CSx remains active."]
pub type CKWAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:1 - Chip select number"]
#[inline(always)]
pub fn csnum(&self) -> CSNUM_R {
CSNUM_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - Chip select active high level select"]
#[inline(always)]
pub fn csl(&self) -> CSL_R {
CSL_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 8:11 - Chip select setup. Minimum number of SPICLK periods to wait from assertion of CS<n> to the first SPICLK transition"]
#[inline(always)]
pub fn cssetup(&self) -> CSSETUP_R {
CSSETUP_R::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bits 12:15 - Chip select hold. Minimum number of SPICLK periods to wait from the last SPICLK transition to de-assertion of CS<n>"]
#[inline(always)]
pub fn cshold(&self) -> CSHOLD_R {
CSHOLD_R::new(((self.bits >> 12) & 0x0f) as u8)
}
#[doc = "Bits 16:19 - Chip select wait. The minimum number of SPICLK periods to wait between the de-assertion of CS<n> and the re-assertion of CS<n>"]
#[inline(always)]
pub fn cswait(&self) -> CSWAIT_R {
CSWAIT_R::new(((self.bits >> 16) & 0x0f) as u8)
}
#[doc = "Bits 20:23 - SPI clock wait. Only applies if SPICTL.MTRANS=1b(multiple transfers with one chip select assertion). This value determines the minimum number of SPICLK periods to wait between back-to-back transfers. During this wait time, SPICLK does not toggle but CSx remains active."]
#[inline(always)]
pub fn ckwait(&self) -> CKWAIT_R {
CKWAIT_R::new(((self.bits >> 20) & 0x0f) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPICSSTR")
.field("csnum", &self.csnum())
.field("csl", &self.csl())
.field("cssetup", &self.cssetup())
.field("cshold", &self.cshold())
.field("cswait", &self.cswait())
.field("ckwait", &self.ckwait())
.finish()
}
}
impl W {
#[doc = "Bits 0:1 - Chip select number"]
#[inline(always)]
pub fn csnum(&mut self) -> CSNUM_W<SPICSSTRrs> {
CSNUM_W::new(self, 0)
}
#[doc = "Bit 2 - Chip select active high level select"]
#[inline(always)]
pub fn csl(&mut self) -> CSL_W<SPICSSTRrs> {
CSL_W::new(self, 2)
}
#[doc = "Bits 8:11 - Chip select setup. Minimum number of SPICLK periods to wait from assertion of CS<n> to the first SPICLK transition"]
#[inline(always)]
pub fn cssetup(&mut self) -> CSSETUP_W<SPICSSTRrs> {
CSSETUP_W::new(self, 8)
}
#[doc = "Bits 12:15 - Chip select hold. Minimum number of SPICLK periods to wait from the last SPICLK transition to de-assertion of CS<n>"]
#[inline(always)]
pub fn cshold(&mut self) -> CSHOLD_W<SPICSSTRrs> {
CSHOLD_W::new(self, 12)
}
#[doc = "Bits 16:19 - Chip select wait. The minimum number of SPICLK periods to wait between the de-assertion of CS<n> and the re-assertion of CS<n>"]
#[inline(always)]
pub fn cswait(&mut self) -> CSWAIT_W<SPICSSTRrs> {
CSWAIT_W::new(self, 16)
}
#[doc = "Bits 20:23 - SPI clock wait. Only applies if SPICTL.MTRANS=1b(multiple transfers with one chip select assertion). This value determines the minimum number of SPICLK periods to wait between back-to-back transfers. During this wait time, SPICLK does not toggle but CSx remains active."]
#[inline(always)]
pub fn ckwait(&mut self) -> CKWAIT_W<SPICSSTRrs> {
CKWAIT_W::new(self, 20)
}
}
#[doc = "SPI Chip Select Steering Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spicsstr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spicsstr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SPICSSTRrs;
impl crate::RegisterSpec for SPICSSTRrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`spicsstr::R`](R) reader structure"]
impl crate::Readable for SPICSSTRrs {}
#[doc = "`write(|w| ..)` method takes [`spicsstr::W`](W) writer structure"]
impl crate::Writable for SPICSSTRrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SPICSSTR to value 0"]
impl crate::Resettable for SPICSSTRrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SPID (rw) register accessor: SPI Data. On READ, retrieve received data word from the incoming holding buffer. On WRITE, write address or data word to the outgoing holding buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`spid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spid`]
module"]
pub type SPID = crate::Reg<spid::SPIDrs>;
#[doc = "SPI Data. On READ, retrieve received data word from the incoming holding buffer. On WRITE, write address or data word to the outgoing holding buffer"]
pub mod spid {
#[doc = "Register `SPID` reader"]
pub type R = crate::R<SPIDrs>;
#[doc = "Register `SPID` writer"]
pub type W = crate::W<SPIDrs>;
#[doc = "Field `DATA` reader - SOC bus bridge data"]
pub type DATA_R = crate::FieldReader;
#[doc = "Field `DATA` writer - SOC bus bridge data"]
pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - SOC bus bridge data"]
#[inline(always)]
pub fn data(&self) -> DATA_R {
DATA_R::new((self.bits & 0xff) as u8)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPID").field("data", &self.data()).finish()
}
}
impl W {
#[doc = "Bits 0:7 - SOC bus bridge data"]
#[inline(always)]
pub fn data(&mut self) -> DATA_W<SPIDrs> {
DATA_W::new(self, 0)
}
}
#[doc = "SPI Data. On READ, retrieve received data word from the incoming holding buffer. On WRITE, write address or data word to the outgoing holding buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`spid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SPIDrs;
impl crate::RegisterSpec for SPIDrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`spid::R`](R) reader structure"]
impl crate::Readable for SPIDrs {}
#[doc = "`write(|w| ..)` method takes [`spid::W`](W) writer structure"]
impl crate::Writable for SPIDrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SPID to value 0"]
impl crate::Resettable for SPIDrs {
const RESET_VALUE: u32 = 0;
}
}
#[doc = "SPIINT_EN (rw) register accessor: SPI Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`spiint_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spiint_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spiint_en`]
module"]
pub type SPIINT_EN = crate::Reg<spiint_en::SPIINT_ENrs>;
#[doc = "SPI Interrupt Enable"]
pub mod spiint_en {
#[doc = "Register `SPIINT_EN` reader"]
pub type R = crate::R<SPIINT_ENrs>;
#[doc = "Register `SPIINT_EN` writer"]
pub type W = crate::W<SPIINT_ENrs>;
#[doc = "Read buffer overflow RDOFL interrupt enable\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RDOFL_EN {
#[doc = "0: disable SOCBSTAT.RDOFL interrupt"]
Disable = 0,
#[doc = "1: enable SOCBSTAT.RDOFL interrupt"]
Enable = 1,
}
impl From<RDOFL_EN> for bool {
#[inline(always)]
fn from(variant: RDOFL_EN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RDOFL_EN` reader - Read buffer overflow RDOFL interrupt enable"]
pub type RDOFL_EN_R = crate::BitReader<RDOFL_EN>;
impl RDOFL_EN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RDOFL_EN {
match self.bits {
false => RDOFL_EN::Disable,
true => RDOFL_EN::Enable,
}
}
#[doc = "disable SOCBSTAT.RDOFL interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == RDOFL_EN::Disable
}
#[doc = "enable SOCBSTAT.RDOFL interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == RDOFL_EN::Enable
}
}
#[doc = "Field `RDOFL_EN` writer - Read buffer overflow RDOFL interrupt enable"]
pub type RDOFL_EN_W<'a, REG> = crate::BitWriter<'a, REG, RDOFL_EN>;
impl<'a, REG> RDOFL_EN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable SOCBSTAT.RDOFL interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(RDOFL_EN::Disable)
}
#[doc = "enable SOCBSTAT.RDOFL interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(RDOFL_EN::Enable)
}
}
#[doc = "Leading edge detect LE interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum LE_EN {
#[doc = "0: disable SOCBSTAT.LE interrupt"]
Disable = 0,
#[doc = "1: enable SOCBSTAT.LE interrupt"]
Enable = 1,
}
impl From<LE_EN> for bool {
#[inline(always)]
fn from(variant: LE_EN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `LE_EN` reader - Leading edge detect LE interrupt enable"]
pub type LE_EN_R = crate::BitReader<LE_EN>;
impl LE_EN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> LE_EN {
match self.bits {
false => LE_EN::Disable,
true => LE_EN::Enable,
}
}
#[doc = "disable SOCBSTAT.LE interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == LE_EN::Disable
}
#[doc = "enable SOCBSTAT.LE interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == LE_EN::Enable
}
}
#[doc = "Field `LE_EN` writer - Leading edge detect LE interrupt enable"]
pub type LE_EN_W<'a, REG> = crate::BitWriter<'a, REG, LE_EN>;
impl<'a, REG> LE_EN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable SOCBSTAT.LE interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(LE_EN::Disable)
}
#[doc = "enable SOCBSTAT.LE interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(LE_EN::Enable)
}
}
#[doc = "Underclock UCLK interrupt enable\n\nValue on reset: 1"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum UCLK_EN {
#[doc = "0: disable SOCBSTAT.UCLK interrupt"]
Disable = 0,
#[doc = "1: enable SOCBSTAT.UCLK interrupt"]
Enable = 1,
}
impl From<UCLK_EN> for bool {
#[inline(always)]
fn from(variant: UCLK_EN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `UCLK_EN` reader - Underclock UCLK interrupt enable"]
pub type UCLK_EN_R = crate::BitReader<UCLK_EN>;
impl UCLK_EN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> UCLK_EN {
match self.bits {
false => UCLK_EN::Disable,
true => UCLK_EN::Enable,
}
}
#[doc = "disable SOCBSTAT.UCLK interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == UCLK_EN::Disable
}
#[doc = "enable SOCBSTAT.UCLK interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == UCLK_EN::Enable
}
}
#[doc = "Field `UCLK_EN` writer - Underclock UCLK interrupt enable"]
pub type UCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG, UCLK_EN>;
impl<'a, REG> UCLK_EN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable SOCBSTAT.UCLK interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(UCLK_EN::Disable)
}
#[doc = "enable SOCBSTAT.UCLK interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(UCLK_EN::Enable)
}
}
#[doc = "Cycle done CYC_DONE interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CYC_DONE_EN {
#[doc = "0: disable SOCBSTAT.CYC_DONE interrupt"]
Disable = 0,
#[doc = "1: enable SOCBSTAT.CYC_DONE interrupt"]
Enable = 1,
}
impl From<CYC_DONE_EN> for bool {
#[inline(always)]
fn from(variant: CYC_DONE_EN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CYC_DONE_EN` reader - Cycle done CYC_DONE interrupt enable"]
pub type CYC_DONE_EN_R = crate::BitReader<CYC_DONE_EN>;
impl CYC_DONE_EN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CYC_DONE_EN {
match self.bits {
false => CYC_DONE_EN::Disable,
true => CYC_DONE_EN::Enable,
}
}
#[doc = "disable SOCBSTAT.CYC_DONE interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == CYC_DONE_EN::Disable
}
#[doc = "enable SOCBSTAT.CYC_DONE interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == CYC_DONE_EN::Enable
}
}
#[doc = "Field `CYC_DONE_EN` writer - Cycle done CYC_DONE interrupt enable"]
pub type CYC_DONE_EN_W<'a, REG> = crate::BitWriter<'a, REG, CYC_DONE_EN>;
impl<'a, REG> CYC_DONE_EN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable SOCBSTAT.CYC_DONE interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(CYC_DONE_EN::Disable)
}
#[doc = "enable SOCBSTAT.CYC_DONE interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(CYC_DONE_EN::Enable)
}
}
#[doc = "Trailing edge detect TE interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TE_EN {
#[doc = "0: disable SOCBSTAT.TE interrupt"]
Disable = 0,
#[doc = "1: enable SOCBSTAT.TE interrupt"]
Enable = 1,
}
impl From<TE_EN> for bool {
#[inline(always)]
fn from(variant: TE_EN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TE_EN` reader - Trailing edge detect TE interrupt enable"]
pub type TE_EN_R = crate::BitReader<TE_EN>;
impl TE_EN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> TE_EN {
match self.bits {
false => TE_EN::Disable,
true => TE_EN::Enable,
}
}
#[doc = "disable SOCBSTAT.TE interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == TE_EN::Disable
}
#[doc = "enable SOCBSTAT.TE interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == TE_EN::Enable
}
}
#[doc = "Field `TE_EN` writer - Trailing edge detect TE interrupt enable"]
pub type TE_EN_W<'a, REG> = crate::BitWriter<'a, REG, TE_EN>;
impl<'a, REG> TE_EN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable SOCBSTAT.TE interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(TE_EN::Disable)
}
#[doc = "enable SOCBSTAT.TE interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(TE_EN::Enable)
}
}
#[doc = "Byte packing BP_DONE interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum BP_DONE {
#[doc = "0: disable SOCBSTAT. BP_DONE interrupt"]
Disable = 0,
#[doc = "1: enable SOCBSTAT.BP_DONE interrupt"]
Enable = 1,
}
impl From<BP_DONE> for bool {
#[inline(always)]
fn from(variant: BP_DONE) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `BP_DONE` reader - Byte packing BP_DONE interrupt enable"]
pub type BP_DONE_R = crate::BitReader<BP_DONE>;
impl BP_DONE_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> BP_DONE {
match self.bits {
false => BP_DONE::Disable,
true => BP_DONE::Enable,
}
}
#[doc = "disable SOCBSTAT. BP_DONE interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == BP_DONE::Disable
}
#[doc = "enable SOCBSTAT.BP_DONE interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == BP_DONE::Enable
}
}
#[doc = "Field `BP_DONE` writer - Byte packing BP_DONE interrupt enable"]
pub type BP_DONE_W<'a, REG> = crate::BitWriter<'a, REG, BP_DONE>;
impl<'a, REG> BP_DONE_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable SOCBSTAT. BP_DONE interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(BP_DONE::Disable)
}
#[doc = "enable SOCBSTAT.BP_DONE interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(BP_DONE::Enable)
}
}
#[doc = "Write buffer underflow SOCBSTAT.WRUFL interrupt enable\n\nValue on reset: 0"]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum WRUFL_EN {
#[doc = "0: disable SOCBSTAT.WRUFL interrupt"]
Disable = 0,
#[doc = "1: enable SOCBSTAT.WRUFL interrupt"]
Enable = 1,
}
impl From<WRUFL_EN> for bool {
#[inline(always)]
fn from(variant: WRUFL_EN) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `WRUFL_EN` reader - Write buffer underflow SOCBSTAT.WRUFL interrupt enable"]
pub type WRUFL_EN_R = crate::BitReader<WRUFL_EN>;
impl WRUFL_EN_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> WRUFL_EN {
match self.bits {
false => WRUFL_EN::Disable,
true => WRUFL_EN::Enable,
}
}
#[doc = "disable SOCBSTAT.WRUFL interrupt"]
#[inline(always)]
pub fn is_disable(&self) -> bool {
*self == WRUFL_EN::Disable
}
#[doc = "enable SOCBSTAT.WRUFL interrupt"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == WRUFL_EN::Enable
}
}
#[doc = "Field `WRUFL_EN` writer - Write buffer underflow SOCBSTAT.WRUFL interrupt enable"]
pub type WRUFL_EN_W<'a, REG> = crate::BitWriter<'a, REG, WRUFL_EN>;
impl<'a, REG> WRUFL_EN_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "disable SOCBSTAT.WRUFL interrupt"]
#[inline(always)]
pub fn disable(self) -> &'a mut crate::W<REG> {
self.variant(WRUFL_EN::Disable)
}
#[doc = "enable SOCBSTAT.WRUFL interrupt"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(WRUFL_EN::Enable)
}
}
impl R {
#[doc = "Bit 2 - Read buffer overflow RDOFL interrupt enable"]
#[inline(always)]
pub fn rdofl_en(&self) -> RDOFL_EN_R {
RDOFL_EN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Leading edge detect LE interrupt enable"]
#[inline(always)]
pub fn le_en(&self) -> LE_EN_R {
LE_EN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Underclock UCLK interrupt enable"]
#[inline(always)]
pub fn uclk_en(&self) -> UCLK_EN_R {
UCLK_EN_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Cycle done CYC_DONE interrupt enable"]
#[inline(always)]
pub fn cyc_done_en(&self) -> CYC_DONE_EN_R {
CYC_DONE_EN_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Trailing edge detect TE interrupt enable"]
#[inline(always)]
pub fn te_en(&self) -> TE_EN_R {
TE_EN_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Byte packing BP_DONE interrupt enable"]
#[inline(always)]
pub fn bp_done(&self) -> BP_DONE_R {
BP_DONE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Write buffer underflow SOCBSTAT.WRUFL interrupt enable"]
#[inline(always)]
pub fn wrufl_en(&self) -> WRUFL_EN_R {
WRUFL_EN_R::new(((self.bits >> 8) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPIINT_EN")
.field("rdofl_en", &self.rdofl_en())
.field("le_en", &self.le_en())
.field("uclk_en", &self.uclk_en())
.field("cyc_done_en", &self.cyc_done_en())
.field("te_en", &self.te_en())
.field("bp_done", &self.bp_done())
.field("wrufl_en", &self.wrufl_en())
.finish()
}
}
impl W {
#[doc = "Bit 2 - Read buffer overflow RDOFL interrupt enable"]
#[inline(always)]
pub fn rdofl_en(&mut self) -> RDOFL_EN_W<SPIINT_ENrs> {
RDOFL_EN_W::new(self, 2)
}
#[doc = "Bit 3 - Leading edge detect LE interrupt enable"]
#[inline(always)]
pub fn le_en(&mut self) -> LE_EN_W<SPIINT_ENrs> {
LE_EN_W::new(self, 3)
}
#[doc = "Bit 4 - Underclock UCLK interrupt enable"]
#[inline(always)]
pub fn uclk_en(&mut self) -> UCLK_EN_W<SPIINT_ENrs> {
UCLK_EN_W::new(self, 4)
}
#[doc = "Bit 5 - Cycle done CYC_DONE interrupt enable"]
#[inline(always)]
pub fn cyc_done_en(&mut self) -> CYC_DONE_EN_W<SPIINT_ENrs> {
CYC_DONE_EN_W::new(self, 5)
}
#[doc = "Bit 6 - Trailing edge detect TE interrupt enable"]
#[inline(always)]
pub fn te_en(&mut self) -> TE_EN_W<SPIINT_ENrs> {
TE_EN_W::new(self, 6)
}
#[doc = "Bit 7 - Byte packing BP_DONE interrupt enable"]
#[inline(always)]
pub fn bp_done(&mut self) -> BP_DONE_W<SPIINT_ENrs> {
BP_DONE_W::new(self, 7)
}
#[doc = "Bit 8 - Write buffer underflow SOCBSTAT.WRUFL interrupt enable"]
#[inline(always)]
pub fn wrufl_en(&mut self) -> WRUFL_EN_W<SPIINT_ENrs> {
WRUFL_EN_W::new(self, 8)
}
}
#[doc = "SPI Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`spiint_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spiint_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SPIINT_ENrs;
impl crate::RegisterSpec for SPIINT_ENrs {
type Ux = u32;
}
#[doc = "`read()` method returns [`spiint_en::R`](R) reader structure"]
impl crate::Readable for SPIINT_ENrs {}
#[doc = "`write(|w| ..)` method takes [`spiint_en::W`](W) writer structure"]
impl crate::Writable for SPIINT_ENrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SPIINT_EN to value 0x14"]
impl crate::Resettable for SPIINT_ENrs {
const RESET_VALUE: u32 = 0x14;
}
}
}
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
#[doc = r" All the peripherals."]
#[allow(non_snake_case)]
pub struct Peripherals {
#[doc = "SYSCLK"]
pub SYSCLK: SYSCLK,
#[doc = "MEMCTL"]
pub MEMCTL: MEMCTL,
#[doc = "WDT"]
pub WDT: WDT,
#[doc = "RTC"]
pub RTC: RTC,
#[doc = "GPIOA"]
pub GPIOA: GPIOA,
#[doc = "GPIOB"]
pub GPIOB: GPIOB,
#[doc = "GPIOC"]
pub GPIOC: GPIOC,
#[doc = "GPIOD"]
pub GPIOD: GPIOD,
#[doc = "GPIOE"]
pub GPIOE: GPIOE,
#[doc = "TIMERA"]
pub TIMERA: TIMERA,
#[doc = "TIMERB"]
pub TIMERB: TIMERB,
#[doc = "TIMERC"]
pub TIMERC: TIMERC,
#[doc = "TIMERD"]
pub TIMERD: TIMERD,
#[doc = "ADC"]
pub ADC: ADC,
#[doc = "I2C"]
pub I2C: I2C,
#[doc = "UART"]
pub UART: UART,
#[doc = "SOCB"]
pub SOCB: SOCB,
#[doc = "SPI"]
pub SPI: SPI,
}
impl Peripherals {
#[doc = r" Returns all the peripherals *once*."]
#[cfg(feature = "critical-section")]
#[inline]
pub fn take() -> Option<Self> {
critical_section::with(|_| {
if unsafe { DEVICE_PERIPHERALS } {
return None;
}
Some(unsafe { Peripherals::steal() })
})
}
#[doc = r" Unchecked version of `Peripherals::take`."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Each of the returned peripherals must be used at most once."]
#[inline]
pub unsafe fn steal() -> Self {
DEVICE_PERIPHERALS = true;
Peripherals {
SYSCLK: SYSCLK::steal(),
MEMCTL: MEMCTL::steal(),
WDT: WDT::steal(),
RTC: RTC::steal(),
GPIOA: GPIOA::steal(),
GPIOB: GPIOB::steal(),
GPIOC: GPIOC::steal(),
GPIOD: GPIOD::steal(),
GPIOE: GPIOE::steal(),
TIMERA: TIMERA::steal(),
TIMERB: TIMERB::steal(),
TIMERC: TIMERC::steal(),
TIMERD: TIMERD::steal(),
ADC: ADC::steal(),
I2C: I2C::steal(),
UART: UART::steal(),
SOCB: SOCB::steal(),
SPI: SPI::steal(),
}
}
}