ordvec 0.2.0

Training-free ordinal & sign quantization for vector retrieval
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

# Codecov is a dashboard + README badge for this repo. The *enforced* coverage
# gate is the cargo-llvm-cov `--fail-under-lines 78` floor in
# .github/workflows/coverage.yml — set under the AVX-512-free runner figure:
# the hosted coverage runner has no AVX-512, so the runtime SIMD dispatch never
# reaches the AVX-512 kernels (they are exercised by the separate `avx512` job
# under Intel SDE). See issue #68.
coverage:
  status:
    project:
      default:
        target: 78%       # mirror the enforced cargo-llvm-cov floor
        threshold: 1%
    patch:
      default:
        # The AVX-512 kernels cannot be covered on the no-AVX-512 coverage
        # runner, so patch coverage on any SIMD-kernel change is a false signal
        # (touching a kernel re-indents lines the runner never executes — see
        # #68). Keep patch advisory rather than blocking PRs on it; real
        # coverage enforcement lives in the workflow floor above.
        informational: true

# The cargo-fuzz workspace is excluded from the crate build and is not part of
# the tested surface measured by cargo-llvm-cov.
ignore:
  - "fuzz"