Oak VHDL Parser

High-performance incremental VHDL parser for the oak ecosystem with flexible configuration, optimized for hardware description and digital circuit design.

🎯 Overview

Oak VHDL is a robust parser for VHDL, designed to handle complete VHDL syntax including modern features. Built on the solid foundation of oak-core, it provides both high-level convenience and detailed AST generation for hardware description and digital circuit design.

✨ Features

Complete VHDL Syntax: Supports all VHDL features including modern specifications
Full AST Generation: Generates comprehensive Abstract Syntax Trees
Lexer Support: Built-in tokenization with proper span information
Error Recovery: Graceful handling of syntax errors with detailed diagnostics

🚀 Quick Start

Basic example:

use oak_vhdl::{Parser, VhdlLanguage, SourceText};

fn main() -> Result<(), Box<dyn std::error::Error>> {
    let parser = Parser::new();
    let source = SourceText::new(r#"
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity counter is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           count : out STD_LOGIC_VECTOR (3 downto 0));
end counter;

architecture Behavioral of counter is
    signal internal_count : unsigned(3 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            internal_count <= (others => '0');
        elsif rising_edge(clk) then
            internal_count <= internal_count + 1;
        end if;
    end process;
    
    count <= std_logic_vector(internal_count);
end Behavioral;
    "#);
    
    let result = parser.parse(&source);
    println!("Parsed VHDL successfully.");
    Ok(())
}

📋 Parsing Examples

Entity Parsing

use oak_vhdl::{Parser, VhdlLanguage, SourceText};

let parser = Parser::new();
let source = SourceText::new(r#"
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity full_adder is
    Port ( a : in STD_LOGIC;
           b : in STD_LOGIC;
           cin : in STD_LOGIC;
           sum : out STD_LOGIC;
           cout : out STD_LOGIC);
end full_adder;
"#);

let result = parser.parse(&source);
println!("Entity parsed successfully.");

Architecture Parsing

use oak_vhdl::{Parser, VhdlLanguage, SourceText};

let parser = Parser::new();
let source = SourceText::new(r#"
architecture Behavioral of full_adder is
begin
    sum <= a xor b xor cin;
    cout <= (a and b) or (b and cin) or (a and cin);
end Behavioral;
"#);

let result = parser.parse(&source);
println!("Architecture parsed successfully.");

🔧 Advanced Features

Token-Level Parsing

use oak_vhdl::{Parser, VhdlLanguage, SourceText};

let parser = Parser::new();
let source = SourceText::new("entity test is end test;");
let result = parser.parse(&source);
println!("Token parsing completed.");

Error Handling

use oak_vhdl::{Parser, VhdlLanguage, SourceText};

let parser = Parser::new();
let source = SourceText::new(r#"
entity broken_entity is
    Port ( clk : in STD_LOGIC
    -- Missing semicolon
           reset : in STD_LOGIC);
end broken_entity;

architecture Behavioral of broken_entity is
begin
    process(clk)
    begin
        if rising_edge(clk then  -- Missing closing parenthesis
            -- Some process logic
        end if;
    end process;
end Behavioral;
"#);

let result = parser.parse(&source);
if let Some(errors) = result.result.err() {
    println!("Parse errors found: {:?}", errors);
} else {
    println!("Parsed successfully.");
}

🏗️ AST Structure

The parser generates a comprehensive AST with the following main structures:

VhdlSource: Root container for VHDL source files
DesignUnit: VHDL design units (entity, architecture, package, etc.)
Entity: Entity declarations with ports and generics
Architecture: Architecture implementations with statements
Process: Process statements with sensitivity lists
SignalDeclaration: Signal and variable declarations
ConcurrentStatement: Concurrent statements (assignments, instances, etc.)
SequentialStatement: Sequential statements within processes

📊 Performance

Streaming: Parse large VHDL files without loading entirely into memory
Incremental: Re-parse only changed sections
Memory Efficient: Smart AST node allocation
Fast Recovery: Quick error recovery for better IDE integration

🔗 Integration

Oak VHDL integrates seamlessly with:

Hardware Design: Building hardware design tools
Simulation: Creating simulation and verification tools
Synthesis: Front-end for synthesis tools
IDE Support: Language server protocol compatibility for VHDL
Educational Tools: Building VHDL learning environments

📚 Examples

Check out the examples directory for comprehensive examples:

Complete VHDL design unit parsing
Hardware description analysis
Integration with development workflows

🤝 Contributing

Contributions are welcome!

Please feel free to submit pull requests at the project repository or open issues.

oak-vhdl 0.0.0