1#[doc = "Reader of register PWRCON"]
2pub type R = crate::R<u32, super::PWRCON>;
3#[doc = "Writer for register PWRCON"]
4pub type W = crate::W<u32, super::PWRCON>;
5#[doc = "Register PWRCON `reset()`'s with value 0x10"]
6impl crate::ResetValue for super::PWRCON {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0x10
11 }
12}
13#[doc = "Reader of field `XTL12M_EN`"]
14pub type XTL12M_EN_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `XTL12M_EN`"]
16pub struct XTL12M_EN_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> XTL12M_EN_W<'a> {
20 #[doc = r"Sets the field bit"]
21 #[inline(always)]
22 pub fn set_bit(self) -> &'a mut W {
23 self.bit(true)
24 }
25 #[doc = r"Clears the field bit"]
26 #[inline(always)]
27 pub fn clear_bit(self) -> &'a mut W {
28 self.bit(false)
29 }
30 #[doc = r"Writes raw bits to the field"]
31 #[inline(always)]
32 pub fn bit(self, value: bool) -> &'a mut W {
33 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34 self.w
35 }
36}
37#[doc = "Reader of field `XTL32K_EN`"]
38pub type XTL32K_EN_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `XTL32K_EN`"]
40pub struct XTL32K_EN_W<'a> {
41 w: &'a mut W,
42}
43impl<'a> XTL32K_EN_W<'a> {
44 #[doc = r"Sets the field bit"]
45 #[inline(always)]
46 pub fn set_bit(self) -> &'a mut W {
47 self.bit(true)
48 }
49 #[doc = r"Clears the field bit"]
50 #[inline(always)]
51 pub fn clear_bit(self) -> &'a mut W {
52 self.bit(false)
53 }
54 #[doc = r"Writes raw bits to the field"]
55 #[inline(always)]
56 pub fn bit(self, value: bool) -> &'a mut W {
57 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
58 self.w
59 }
60}
61#[doc = "Reader of field `OSC22M_EN`"]
62pub type OSC22M_EN_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `OSC22M_EN`"]
64pub struct OSC22M_EN_W<'a> {
65 w: &'a mut W,
66}
67impl<'a> OSC22M_EN_W<'a> {
68 #[doc = r"Sets the field bit"]
69 #[inline(always)]
70 pub fn set_bit(self) -> &'a mut W {
71 self.bit(true)
72 }
73 #[doc = r"Clears the field bit"]
74 #[inline(always)]
75 pub fn clear_bit(self) -> &'a mut W {
76 self.bit(false)
77 }
78 #[doc = r"Writes raw bits to the field"]
79 #[inline(always)]
80 pub fn bit(self, value: bool) -> &'a mut W {
81 self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
82 self.w
83 }
84}
85#[doc = "Reader of field `OSC10K_EN`"]
86pub type OSC10K_EN_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `OSC10K_EN`"]
88pub struct OSC10K_EN_W<'a> {
89 w: &'a mut W,
90}
91impl<'a> OSC10K_EN_W<'a> {
92 #[doc = r"Sets the field bit"]
93 #[inline(always)]
94 pub fn set_bit(self) -> &'a mut W {
95 self.bit(true)
96 }
97 #[doc = r"Clears the field bit"]
98 #[inline(always)]
99 pub fn clear_bit(self) -> &'a mut W {
100 self.bit(false)
101 }
102 #[doc = r"Writes raw bits to the field"]
103 #[inline(always)]
104 pub fn bit(self, value: bool) -> &'a mut W {
105 self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
106 self.w
107 }
108}
109#[doc = "Reader of field `PD_WU_DLY`"]
110pub type PD_WU_DLY_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `PD_WU_DLY`"]
112pub struct PD_WU_DLY_W<'a> {
113 w: &'a mut W,
114}
115impl<'a> PD_WU_DLY_W<'a> {
116 #[doc = r"Sets the field bit"]
117 #[inline(always)]
118 pub fn set_bit(self) -> &'a mut W {
119 self.bit(true)
120 }
121 #[doc = r"Clears the field bit"]
122 #[inline(always)]
123 pub fn clear_bit(self) -> &'a mut W {
124 self.bit(false)
125 }
126 #[doc = r"Writes raw bits to the field"]
127 #[inline(always)]
128 pub fn bit(self, value: bool) -> &'a mut W {
129 self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
130 self.w
131 }
132}
133#[doc = "Reader of field `PD_WU_INT_EN`"]
134pub type PD_WU_INT_EN_R = crate::R<bool, bool>;
135#[doc = "Write proxy for field `PD_WU_INT_EN`"]
136pub struct PD_WU_INT_EN_W<'a> {
137 w: &'a mut W,
138}
139impl<'a> PD_WU_INT_EN_W<'a> {
140 #[doc = r"Sets the field bit"]
141 #[inline(always)]
142 pub fn set_bit(self) -> &'a mut W {
143 self.bit(true)
144 }
145 #[doc = r"Clears the field bit"]
146 #[inline(always)]
147 pub fn clear_bit(self) -> &'a mut W {
148 self.bit(false)
149 }
150 #[doc = r"Writes raw bits to the field"]
151 #[inline(always)]
152 pub fn bit(self, value: bool) -> &'a mut W {
153 self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
154 self.w
155 }
156}
157#[doc = "Reader of field `PD_WU_STS`"]
158pub type PD_WU_STS_R = crate::R<bool, bool>;
159#[doc = "Write proxy for field `PD_WU_STS`"]
160pub struct PD_WU_STS_W<'a> {
161 w: &'a mut W,
162}
163impl<'a> PD_WU_STS_W<'a> {
164 #[doc = r"Sets the field bit"]
165 #[inline(always)]
166 pub fn set_bit(self) -> &'a mut W {
167 self.bit(true)
168 }
169 #[doc = r"Clears the field bit"]
170 #[inline(always)]
171 pub fn clear_bit(self) -> &'a mut W {
172 self.bit(false)
173 }
174 #[doc = r"Writes raw bits to the field"]
175 #[inline(always)]
176 pub fn bit(self, value: bool) -> &'a mut W {
177 self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
178 self.w
179 }
180}
181#[doc = "Reader of field `PWR_DOWN_EN`"]
182pub type PWR_DOWN_EN_R = crate::R<bool, bool>;
183#[doc = "Write proxy for field `PWR_DOWN_EN`"]
184pub struct PWR_DOWN_EN_W<'a> {
185 w: &'a mut W,
186}
187impl<'a> PWR_DOWN_EN_W<'a> {
188 #[doc = r"Sets the field bit"]
189 #[inline(always)]
190 pub fn set_bit(self) -> &'a mut W {
191 self.bit(true)
192 }
193 #[doc = r"Clears the field bit"]
194 #[inline(always)]
195 pub fn clear_bit(self) -> &'a mut W {
196 self.bit(false)
197 }
198 #[doc = r"Writes raw bits to the field"]
199 #[inline(always)]
200 pub fn bit(self, value: bool) -> &'a mut W {
201 self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
202 self.w
203 }
204}
205#[doc = "Reader of field `PD_WAIT_CPU`"]
206pub type PD_WAIT_CPU_R = crate::R<bool, bool>;
207#[doc = "Write proxy for field `PD_WAIT_CPU`"]
208pub struct PD_WAIT_CPU_W<'a> {
209 w: &'a mut W,
210}
211impl<'a> PD_WAIT_CPU_W<'a> {
212 #[doc = r"Sets the field bit"]
213 #[inline(always)]
214 pub fn set_bit(self) -> &'a mut W {
215 self.bit(true)
216 }
217 #[doc = r"Clears the field bit"]
218 #[inline(always)]
219 pub fn clear_bit(self) -> &'a mut W {
220 self.bit(false)
221 }
222 #[doc = r"Writes raw bits to the field"]
223 #[inline(always)]
224 pub fn bit(self, value: bool) -> &'a mut W {
225 self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
226 self.w
227 }
228}
229impl R {
230 #[doc = "Bit 0 - External 4~24 MHz Crystal Enable (write-protection bit) The bit default value is set by flash controller user configuration register config0 \\[26:24\\]. When the default clock source is from external 4~24 MHz crystal, this bit is set to 1 automatically 1 = Enable external 4~24 MHz crystal 0 = Disable external 4~24 MHz crystal"]
231 #[inline(always)]
232 pub fn xtl12m_en(&self) -> XTL12M_EN_R {
233 XTL12M_EN_R::new((self.bits & 0x01) != 0)
234 }
235 #[doc = "Bit 1 - External 32.768 KHz Crystal Enable (write-protection bit) 1 = Enable external 32.768 kHz Crystal (Normal operation) 0 = Disable external 32.768 kHz Crystal"]
236 #[inline(always)]
237 pub fn xtl32k_en(&self) -> XTL32K_EN_R {
238 XTL32K_EN_R::new(((self.bits >> 1) & 0x01) != 0)
239 }
240 #[doc = "Bit 2 - Internal 22.1184MHz Oscillator Enable (write-protection bit) 1 = Enable 22.1184MHz Oscillation 0 = Disable 22.1184MHz Oscillation"]
241 #[inline(always)]
242 pub fn osc22m_en(&self) -> OSC22M_EN_R {
243 OSC22M_EN_R::new(((self.bits >> 2) & 0x01) != 0)
244 }
245 #[doc = "Bit 3 - Internal 10KHz Oscillator Enable (write-protection bit) 1 = Enable 10KHz Oscillation 0 = Disable 10KHz Oscillation"]
246 #[inline(always)]
247 pub fn osc10k_en(&self) -> OSC10K_EN_R {
248 OSC10K_EN_R::new(((self.bits >> 3) & 0x01) != 0)
249 }
250 #[doc = "Bit 4 - Enable the wake up delay counter (write-protection bit) When the chip wakes up from power down mode, the clock control will delay certain clock cycles to wait system clock stable. The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz crystal, and 256 clock cycles when chip work at internal 22.1184 MHz oscillator. 1 = Enable clock cycles delay 0 = Disable clock cycles delay"]
251 #[inline(always)]
252 pub fn pd_wu_dly(&self) -> PD_WU_DLY_R {
253 PD_WU_DLY_R::new(((self.bits >> 4) & 0x01) != 0)
254 }
255 #[doc = "Bit 5 - Power down mode wake up Interrupt enable (write-protection bit) 0 = Disable 1 = Enable. The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high."]
256 #[inline(always)]
257 pub fn pd_wu_int_en(&self) -> PD_WU_INT_EN_R {
258 PD_WU_INT_EN_R::new(((self.bits >> 5) & 0x01) != 0)
259 }
260 #[doc = "Bit 6 - Power down mode wake up interrupt status Set by \"power down wake up\", it indicates that resume from power down mode The flag is set if the GPIO, USB, UART, WDT, CAN, ACMP, BOD or RTC wakeup occurred Write 1 to clear the bit Note: This bit is working only if PD_WU_INT_EN (PWRCON\\[5\\]) set to 1."]
261 #[inline(always)]
262 pub fn pd_wu_sts(&self) -> PD_WU_STS_R {
263 PD_WU_STS_R::new(((self.bits >> 6) & 0x01) != 0)
264 }
265 #[doc = "Bit 7 - System power down enable bit (write-protection bit) When CPU sets this bit \"1\" the chip power down mode is enabled, and chip power-down behavior will depends on the PD_WAIT_CPU bit. (a) If the PD_WAIT_CPU is \"0\", then the chip enters power down mode immediately after the PWR_DOWN_EN bit set. (b) if the PD_WAIT_CPU is \"1\", then the chip keeps active till the CPU sleep mode is also active and then the chip enters power down mode. When chip wakes up from power down mode, this bit is auto cleared. Users need to set this bit again for next power down. When in power down mode, external 4~24 MHz crystal and the internal 22.1184 MHz oscillator will be disabled in this mode, but the external 32 kHz crystal and internal 10 kHz oscillator are not controlled by power down mode. When in power down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by power down mode, if the peripheral clock source is from 32 kHz crystal or the 10 kHz oscillator. 1 = Chip enter the power down mode instant or wait CPU sleep command WFI. 0 = Chip operate in normal mode or CPU in idle mode (sleep mode) because of WFI command."]
266 #[inline(always)]
267 pub fn pwr_down_en(&self) -> PWR_DOWN_EN_R {
268 PWR_DOWN_EN_R::new(((self.bits >> 7) & 0x01) != 0)
269 }
270 #[doc = "Bit 8 - This bit control the power down entry condition (write-protection bit) 1 = Chip enter power down mode when the both PWR_DOWN_EN bit is set to 1 and CPU run WFI instruction. 0 = Chip entry power down mode when the PWR_DOWN_EN bit is set to 1."]
271 #[inline(always)]
272 pub fn pd_wait_cpu(&self) -> PD_WAIT_CPU_R {
273 PD_WAIT_CPU_R::new(((self.bits >> 8) & 0x01) != 0)
274 }
275}
276impl W {
277 #[doc = "Bit 0 - External 4~24 MHz Crystal Enable (write-protection bit) The bit default value is set by flash controller user configuration register config0 \\[26:24\\]. When the default clock source is from external 4~24 MHz crystal, this bit is set to 1 automatically 1 = Enable external 4~24 MHz crystal 0 = Disable external 4~24 MHz crystal"]
278 #[inline(always)]
279 pub fn xtl12m_en(&mut self) -> XTL12M_EN_W {
280 XTL12M_EN_W { w: self }
281 }
282 #[doc = "Bit 1 - External 32.768 KHz Crystal Enable (write-protection bit) 1 = Enable external 32.768 kHz Crystal (Normal operation) 0 = Disable external 32.768 kHz Crystal"]
283 #[inline(always)]
284 pub fn xtl32k_en(&mut self) -> XTL32K_EN_W {
285 XTL32K_EN_W { w: self }
286 }
287 #[doc = "Bit 2 - Internal 22.1184MHz Oscillator Enable (write-protection bit) 1 = Enable 22.1184MHz Oscillation 0 = Disable 22.1184MHz Oscillation"]
288 #[inline(always)]
289 pub fn osc22m_en(&mut self) -> OSC22M_EN_W {
290 OSC22M_EN_W { w: self }
291 }
292 #[doc = "Bit 3 - Internal 10KHz Oscillator Enable (write-protection bit) 1 = Enable 10KHz Oscillation 0 = Disable 10KHz Oscillation"]
293 #[inline(always)]
294 pub fn osc10k_en(&mut self) -> OSC10K_EN_W {
295 OSC10K_EN_W { w: self }
296 }
297 #[doc = "Bit 4 - Enable the wake up delay counter (write-protection bit) When the chip wakes up from power down mode, the clock control will delay certain clock cycles to wait system clock stable. The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz crystal, and 256 clock cycles when chip work at internal 22.1184 MHz oscillator. 1 = Enable clock cycles delay 0 = Disable clock cycles delay"]
298 #[inline(always)]
299 pub fn pd_wu_dly(&mut self) -> PD_WU_DLY_W {
300 PD_WU_DLY_W { w: self }
301 }
302 #[doc = "Bit 5 - Power down mode wake up Interrupt enable (write-protection bit) 0 = Disable 1 = Enable. The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high."]
303 #[inline(always)]
304 pub fn pd_wu_int_en(&mut self) -> PD_WU_INT_EN_W {
305 PD_WU_INT_EN_W { w: self }
306 }
307 #[doc = "Bit 6 - Power down mode wake up interrupt status Set by \"power down wake up\", it indicates that resume from power down mode The flag is set if the GPIO, USB, UART, WDT, CAN, ACMP, BOD or RTC wakeup occurred Write 1 to clear the bit Note: This bit is working only if PD_WU_INT_EN (PWRCON\\[5\\]) set to 1."]
308 #[inline(always)]
309 pub fn pd_wu_sts(&mut self) -> PD_WU_STS_W {
310 PD_WU_STS_W { w: self }
311 }
312 #[doc = "Bit 7 - System power down enable bit (write-protection bit) When CPU sets this bit \"1\" the chip power down mode is enabled, and chip power-down behavior will depends on the PD_WAIT_CPU bit. (a) If the PD_WAIT_CPU is \"0\", then the chip enters power down mode immediately after the PWR_DOWN_EN bit set. (b) if the PD_WAIT_CPU is \"1\", then the chip keeps active till the CPU sleep mode is also active and then the chip enters power down mode. When chip wakes up from power down mode, this bit is auto cleared. Users need to set this bit again for next power down. When in power down mode, external 4~24 MHz crystal and the internal 22.1184 MHz oscillator will be disabled in this mode, but the external 32 kHz crystal and internal 10 kHz oscillator are not controlled by power down mode. When in power down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by power down mode, if the peripheral clock source is from 32 kHz crystal or the 10 kHz oscillator. 1 = Chip enter the power down mode instant or wait CPU sleep command WFI. 0 = Chip operate in normal mode or CPU in idle mode (sleep mode) because of WFI command."]
313 #[inline(always)]
314 pub fn pwr_down_en(&mut self) -> PWR_DOWN_EN_W {
315 PWR_DOWN_EN_W { w: self }
316 }
317 #[doc = "Bit 8 - This bit control the power down entry condition (write-protection bit) 1 = Chip enter power down mode when the both PWR_DOWN_EN bit is set to 1 and CPU run WFI instruction. 0 = Chip entry power down mode when the PWR_DOWN_EN bit is set to 1."]
318 #[inline(always)]
319 pub fn pd_wait_cpu(&mut self) -> PD_WAIT_CPU_W {
320 PD_WAIT_CPU_W { w: self }
321 }
322}