Expand description
Peripheral access API for NRF9160 microcontrollers (generated using svd2rust v0.14.0)
You can find an overview of the API here.
Modules§
- Clock management 0
- ARM TrustZone CryptoCell register interface
- Control access port
- Distributed Programmable Peripheral Interconnect Controller 0
- Event Generator Unit 0
- Factory Information Configuration Registers
- FPU 0
- GPIO Tasks and Events 0
- Inter-IC Sound 0
- Inter Processor Communication 0
- Key management unit 0
- Non-volatile memory controller 0
- GPIO Port 0
- Pulse Density Modulation (Digital Microphone) Interface 0
- Power control 0
- Pulse width modulation unit 0
- Voltage regulators control 0
- Real-time counter 0
- Analog to Digital Converter 0
- Serial Peripheral Interface Master with EasyDMA 0
- SPI Slave 0
- System protection unit
- Trace and debug control
- Timer/Counter 0
- I2C compatible Two-Wire Master Interface with EasyDMA 0
- I2C compatible Two-Wire Slave Interface with EasyDMA 0
- UART with EasyDMA 0
- User information configuration registers User information configuration registers
- Volatile Memory controller 0
- Watchdog Timer 0
Structs§
- Cache and branch predictor maintenance operations
- Clock management 0
- Clock management 1
- CPUID
- ARM TrustZone CryptoCell register interface
- Control access port
- Core peripherals
- Debug Control Block
- Distributed Programmable Peripheral Interconnect Controller 0
- Distributed Programmable Peripheral Interconnect Controller 1
- Data Watchpoint and Trace unit
- Event Generator Unit 0
- Event Generator Unit 1
- Event Generator Unit 2
- Event Generator Unit 3
- Event Generator Unit 4
- Event Generator Unit 5
- Event Generator Unit 6
- Event Generator Unit 7
- Event Generator Unit 8
- Event Generator Unit 9
- Event Generator Unit 10
- Event Generator Unit 11
- Factory Information Configuration Registers
- Flash Patch and Breakpoint unit
- Floating Point Unit
- FPU 0
- FPU 1
- GPIO Tasks and Events 0
- GPIO Tasks and Events 1
- Inter-IC Sound 0
- Inter-IC Sound 1
- Inter Processor Communication 0
- Inter Processor Communication 1
- Instrumentation Trace Macrocell
- Key management unit 0
- Key management unit 1
- Memory Protection Unit
- Nested Vector Interrupt Controller
- Non-volatile memory controller 0
- Non-volatile memory controller 1
- GPIO Port 0
- GPIO Port 1
- Pulse Density Modulation (Digital Microphone) Interface 0
- Pulse Density Modulation (Digital Microphone) Interface 1
- Power control 0
- Power control 1
- Pulse width modulation unit 0
- Pulse width modulation unit 1
- Pulse width modulation unit 2
- Pulse width modulation unit 3
- Pulse width modulation unit 4
- Pulse width modulation unit 5
- Pulse width modulation unit 6
- Pulse width modulation unit 7
- All the peripherals
- Voltage regulators control 0
- Voltage regulators control 1
- Real-time counter 0
- Real-time counter 1
- Real-time counter 2
- Real-time counter 3
- Analog to Digital Converter 0
- Analog to Digital Converter 1
- System Control Block
- Serial Peripheral Interface Master with EasyDMA 0
- Serial Peripheral Interface Master with EasyDMA 1
- Serial Peripheral Interface Master with EasyDMA 2
- Serial Peripheral Interface Master with EasyDMA 3
- Serial Peripheral Interface Master with EasyDMA 4
- Serial Peripheral Interface Master with EasyDMA 5
- Serial Peripheral Interface Master with EasyDMA 6
- Serial Peripheral Interface Master with EasyDMA 7
- SPI Slave 0
- SPI Slave 1
- SPI Slave 2
- SPI Slave 3
- SPI Slave 4
- SPI Slave 5
- SPI Slave 6
- SPI Slave 7
- System protection unit
- SysTick: System Timer
- Trace and debug control
- Timer/Counter 0
- Timer/Counter 1
- Timer/Counter 2
- Timer/Counter 3
- Timer/Counter 4
- Timer/Counter 5
- Trace Port Interface Unit
- I2C compatible Two-Wire Master Interface with EasyDMA 0
- I2C compatible Two-Wire Master Interface with EasyDMA 1
- I2C compatible Two-Wire Master Interface with EasyDMA 2
- I2C compatible Two-Wire Master Interface with EasyDMA 3
- I2C compatible Two-Wire Master Interface with EasyDMA 4
- I2C compatible Two-Wire Master Interface with EasyDMA 5
- I2C compatible Two-Wire Master Interface with EasyDMA 6
- I2C compatible Two-Wire Master Interface with EasyDMA 7
- I2C compatible Two-Wire Slave Interface with EasyDMA 0
- I2C compatible Two-Wire Slave Interface with EasyDMA 1
- I2C compatible Two-Wire Slave Interface with EasyDMA 2
- I2C compatible Two-Wire Slave Interface with EasyDMA 3
- I2C compatible Two-Wire Slave Interface with EasyDMA 4
- I2C compatible Two-Wire Slave Interface with EasyDMA 5
- I2C compatible Two-Wire Slave Interface with EasyDMA 6
- I2C compatible Two-Wire Slave Interface with EasyDMA 7
- UART with EasyDMA 0
- UART with EasyDMA 1
- UART with EasyDMA 2
- UART with EasyDMA 3
- UART with EasyDMA 4
- UART with EasyDMA 5
- UART with EasyDMA 6
- UART with EasyDMA 7
- User information configuration registers User information configuration registers
- Volatile Memory controller 0
- Volatile Memory controller 1
- Watchdog Timer 0
- Watchdog Timer 1
Enums§
- Enumeration of all the interrupts
Constants§
- Number available in the NVIC for configuring priority