nrf52/power/dcdcen/
mod.rs

1#[doc = r" Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::DCDCEN {
10    #[doc = r" Modifies the contents of the register"]
11    #[inline]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        let r = R { bits: bits };
18        let mut w = W { bits: bits };
19        f(&r, &mut w);
20        self.register.set(w.bits);
21    }
22    #[doc = r" Reads the contents of the register"]
23    #[inline]
24    pub fn read(&self) -> R {
25        R {
26            bits: self.register.get(),
27        }
28    }
29    #[doc = r" Writes to the register"]
30    #[inline]
31    pub fn write<F>(&self, f: F)
32    where
33        F: FnOnce(&mut W) -> &mut W,
34    {
35        let mut w = W::reset_value();
36        f(&mut w);
37        self.register.set(w.bits);
38    }
39    #[doc = r" Writes the reset value to the register"]
40    #[inline]
41    pub fn reset(&self) {
42        self.write(|w| w)
43    }
44}
45#[doc = "Possible values of the field `DCDCEN`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum DCDCENR {
48    #[doc = "Disable"]
49    DISABLED,
50    #[doc = "Enable"]
51    ENABLED,
52}
53impl DCDCENR {
54    #[doc = r" Returns `true` if the bit is clear (0)"]
55    #[inline]
56    pub fn bit_is_clear(&self) -> bool {
57        !self.bit()
58    }
59    #[doc = r" Returns `true` if the bit is set (1)"]
60    #[inline]
61    pub fn bit_is_set(&self) -> bool {
62        self.bit()
63    }
64    #[doc = r" Value of the field as raw bits"]
65    #[inline]
66    pub fn bit(&self) -> bool {
67        match *self {
68            DCDCENR::DISABLED => false,
69            DCDCENR::ENABLED => true,
70        }
71    }
72    #[allow(missing_docs)]
73    #[doc(hidden)]
74    #[inline]
75    pub fn _from(value: bool) -> DCDCENR {
76        match value {
77            false => DCDCENR::DISABLED,
78            true => DCDCENR::ENABLED,
79        }
80    }
81    #[doc = "Checks if the value of the field is `DISABLED`"]
82    #[inline]
83    pub fn is_disabled(&self) -> bool {
84        *self == DCDCENR::DISABLED
85    }
86    #[doc = "Checks if the value of the field is `ENABLED`"]
87    #[inline]
88    pub fn is_enabled(&self) -> bool {
89        *self == DCDCENR::ENABLED
90    }
91}
92#[doc = "Values that can be written to the field `DCDCEN`"]
93pub enum DCDCENW {
94    #[doc = "Disable"]
95    DISABLED,
96    #[doc = "Enable"]
97    ENABLED,
98}
99impl DCDCENW {
100    #[allow(missing_docs)]
101    #[doc(hidden)]
102    #[inline]
103    pub fn _bits(&self) -> bool {
104        match *self {
105            DCDCENW::DISABLED => false,
106            DCDCENW::ENABLED => true,
107        }
108    }
109}
110#[doc = r" Proxy"]
111pub struct _DCDCENW<'a> {
112    w: &'a mut W,
113}
114impl<'a> _DCDCENW<'a> {
115    #[doc = r" Writes `variant` to the field"]
116    #[inline]
117    pub fn variant(self, variant: DCDCENW) -> &'a mut W {
118        {
119            self.bit(variant._bits())
120        }
121    }
122    #[doc = "Disable"]
123    #[inline]
124    pub fn disabled(self) -> &'a mut W {
125        self.variant(DCDCENW::DISABLED)
126    }
127    #[doc = "Enable"]
128    #[inline]
129    pub fn enabled(self) -> &'a mut W {
130        self.variant(DCDCENW::ENABLED)
131    }
132    #[doc = r" Sets the field bit"]
133    pub fn set_bit(self) -> &'a mut W {
134        self.bit(true)
135    }
136    #[doc = r" Clears the field bit"]
137    pub fn clear_bit(self) -> &'a mut W {
138        self.bit(false)
139    }
140    #[doc = r" Writes raw bits to the field"]
141    #[inline]
142    pub fn bit(self, value: bool) -> &'a mut W {
143        const MASK: bool = true;
144        const OFFSET: u8 = 0;
145        self.w.bits &= !((MASK as u32) << OFFSET);
146        self.w.bits |= ((value & MASK) as u32) << OFFSET;
147        self.w
148    }
149}
150impl R {
151    #[doc = r" Value of the register as raw bits"]
152    #[inline]
153    pub fn bits(&self) -> u32 {
154        self.bits
155    }
156    #[doc = "Bit 0 - Enable or disable DC/DC converter"]
157    #[inline]
158    pub fn dcdcen(&self) -> DCDCENR {
159        DCDCENR::_from({
160            const MASK: bool = true;
161            const OFFSET: u8 = 0;
162            ((self.bits >> OFFSET) & MASK as u32) != 0
163        })
164    }
165}
166impl W {
167    #[doc = r" Reset value of the register"]
168    #[inline]
169    pub fn reset_value() -> W {
170        W { bits: 0 }
171    }
172    #[doc = r" Writes raw bits to the register"]
173    #[inline]
174    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
175        self.bits = bits;
176        self
177    }
178    #[doc = "Bit 0 - Enable or disable DC/DC converter"]
179    #[inline]
180    pub fn dcdcen(&mut self) -> _DCDCENW {
181        _DCDCENW { w: self }
182    }
183}
nrf52/power/dcdcen/mod.rs

nrf52/power/dcdcen/
mod.rs
