nrf24l01_commands/registers.rs
1//! Register bitfields for the nRF24L01+.
2//!
3//! ## Example with the CONFIG register
4//! ```rust
5//! use nrf24l01_commands::{fields, registers};
6//!
7//! // Default value
8//! let reg = registers::Config::new();
9//! assert_eq!(reg.into_bits(), 0b0000_1000);
10//!
11//! // Read fields
12//! let reg = registers::Config::from_bits(0b0000_0110);
13//! assert!(!reg.mask_rx_dr());
14//! assert!(!reg.mask_tx_ds());
15//! assert!(!reg.mask_max_rt());
16//! assert!(!reg.en_crc());
17//! assert_eq!(reg.crco(), fields::Crco::TwoByte);
18//! assert!(reg.pwr_up());
19//! assert!(!reg.prim_rx());
20//!
21//! // Write fields
22//! let reg = registers::Config::new()
23//! .with_mask_rx_dr(true)
24//! .with_mask_tx_ds(false)
25//! .with_mask_max_rt(false)
26//! .with_en_crc(false)
27//! .with_crco(fields::Crco::TwoByte)
28//! .with_pwr_up(true)
29//! .with_prim_rx(false);
30//! assert_eq!(reg.into_bits(), 0b0100_0110);
31//! ```
32use crate::fields::{self, EnumField};
33use bitfield_struct::bitfield;
34
35/// A trait for nRF24L01+ registers.
36#[const_trait]
37pub trait Register: Copy {
38 /// Register address.
39 const ADDRESS: u8;
40 /// Convert register to bits.
41 fn into_bits(self) -> u8;
42}
43
44/// A trait for nRF24L01+ address registers which can be 3-5 bytes.
45/// - RxAddrP0
46/// - RxAddrP1
47/// - TxAddr
48#[const_trait]
49pub trait AddressRegister<const N: usize>: Copy {
50 /// Register address.
51 const ADDRESS: u8;
52 /// Creates a new default initialized bitfield.
53 fn new() -> Self;
54 /// Convert from bits.
55 fn from_bits(bits: u64) -> Self;
56 /// Convert into bits.
57 fn into_bits(self) -> u64;
58 /// Convert into bytes ordered by LSByte first.
59 fn into_bytes(self) -> [u8; N];
60}
61
62/// # CONFIG register
63///
64/// Address = `0x00`
65///
66/// ## Fields
67///
68/// #### `mask_rx_dr` | bit 6
69/// Mask/unmask interrupt caused by __RX_DR__.
70///
71/// `0`: unmasked, interrupt reflected on IRQ
72///
73/// `1`: masked, interrupt not reflected on IRQ
74///
75/// #### `mask_tx_ds` | bit 5
76/// Mask/unmask interrupt caused by __TX_DS__.
77///
78/// `0`: unmasked, interrupt reflected on IRQ
79///
80/// `1`: masked, interrupt not reflected on IRQ
81///
82/// #### `mask_max_rt` | bit 4
83/// Mask/unmask interrupt caused by __MAX_RT__.
84///
85/// `0`: unmasked, interrupt reflected on IRQ
86///
87/// `1`: masked, interrupt not reflected on IRQ
88///
89/// #### `en_crc` | bit 3
90/// Enable/disable CRC. Default value: `1` (enabled)
91///
92/// #### `crco` | bit 2
93/// CRC encoding scheme. Enum: [`Crco`](crate::fields::Crco).
94///
95/// #### `pwr_up` | bit 1
96/// Power down/up.
97///
98/// `0`: Power down
99///
100/// `1`: Power up
101///
102/// #### `prim_rx` | bit 0
103/// Set primary TX/RX.
104///
105/// `0`: primary TX
106///
107/// `1`: primary RX
108///
109/// ## Example
110/// ```rust
111/// use nrf24l01_commands::{fields, registers};
112///
113/// // Default value
114/// let reg = registers::Config::new();
115/// assert_eq!(reg.into_bits(), 0b0000_1000);
116///
117/// // Write fields
118/// let reg = registers::Config::new()
119/// .with_mask_rx_dr(true)
120/// .with_mask_tx_ds(false)
121/// .with_mask_max_rt(false)
122/// .with_en_crc(false)
123/// .with_crco(fields::Crco::TwoByte)
124/// .with_pwr_up(true)
125/// .with_prim_rx(false);
126/// assert_eq!(reg.into_bits(), 0b0100_0110);
127/// ```
128#[bitfield(u8, order = Msb)]
129pub struct Config {
130 #[bits(1)]
131 __: bool,
132
133 /// Mask/unmask interrupt caused by __RX_DR__.
134 ///
135 /// `0`: unmasked, interrupt reflected on IRQ
136 ///
137 /// `1`: masked, interrupt not reflected on IRQ
138 #[bits(1)]
139 pub mask_rx_dr: bool,
140
141 /// Mask/unmask interrupt caused by __TX_DS__.
142 ///
143 /// `0`: unmasked, interrupt reflected on IRQ
144 ///
145 /// `1`: masked, interrupt not reflected on IRQ
146 #[bits(1)]
147 pub mask_tx_ds: bool,
148
149 /// Mask/unmask interrupt caused by __MAX_RT__.
150 ///
151 /// `0`: unmasked, interrupt reflected on IRQ
152 ///
153 /// `1`: masked, interrupt not reflected on IRQ
154 #[bits(1)]
155 pub mask_max_rt: bool,
156
157 /// Enable/disable CRC. Default value: `1` (enabled)
158 #[bits(1, default = true)]
159 pub en_crc: bool,
160
161 /// CRC encoding scheme. Enum: [`Crco`](crate::fields::Crco).
162 #[bits(1)]
163 pub crco: fields::Crco,
164
165 /// Power down/up.
166 ///
167 /// `0`: Power down
168 ///
169 /// `1`: Power up
170 #[bits(1)]
171 pub pwr_up: bool,
172
173 /// Set primary TX/RX.
174 ///
175 /// `0`: primary TX
176 ///
177 /// `1`: primary RX
178 #[bits(1)]
179 pub prim_rx: bool,
180}
181
182impl const Register for Config {
183 const ADDRESS: u8 = 0x00;
184
185 fn into_bits(self) -> u8 {
186 self.into_bits()
187 }
188}
189
190/// # EN_AA register
191/// Enable 'Auto Acknowledgement' on data pipes 0-5.
192///
193/// Address = `0x01`
194///
195/// ## Fields
196/// All fields default to 1.
197///
198/// #### `enaa_pN` | bit `N`
199/// Enable 'Auto Acknowledgement' on data pipes `N` = 0-5.
200///
201/// ## Example
202/// ```rust
203/// use nrf24l01_commands::registers;
204///
205/// // Default value
206/// let reg = registers::EnAa::new();
207/// assert_eq!(reg.into_bits(), 0b0011_1111);
208///
209/// // Write fields
210/// let reg = registers::EnAa::new()
211/// .with_enaa_p5(true)
212/// .with_enaa_p4(true)
213/// .with_enaa_p3(false)
214/// .with_enaa_p2(false)
215/// .with_enaa_p1(false)
216/// .with_enaa_p0(false);
217/// assert_eq!(reg.into_bits(), 0b0011_0000);
218/// ```
219#[bitfield(u8, order = Msb)]
220pub struct EnAa {
221 #[bits(2)]
222 __: u8,
223 /// Enable 'Auto Acknowledgement' on data pipe 5.
224 #[bits(1, default = true)]
225 pub enaa_p5: bool,
226 /// Enable 'Auto Acknowledgement' on data pipe 4.
227 #[bits(1, default = true)]
228 pub enaa_p4: bool,
229 /// Enable 'Auto Acknowledgement' on data pipe 3.
230 #[bits(1, default = true)]
231 pub enaa_p3: bool,
232 /// Enable 'Auto Acknowledgement' on data pipe 2.
233 #[bits(1, default = true)]
234 pub enaa_p2: bool,
235 /// Enable 'Auto Acknowledgement' on data pipe 1.
236 #[bits(1, default = true)]
237 pub enaa_p1: bool,
238 /// Enable 'Auto Acknowledgement' on data pipe 0.
239 #[bits(1, default = true)]
240 pub enaa_p0: bool,
241}
242
243impl const Register for EnAa {
244 const ADDRESS: u8 = 0x01;
245
246 fn into_bits(self) -> u8 {
247 self.into_bits()
248 }
249}
250
251/// # EN_RXADDR register
252/// Enable RX address on data pipes 0-5.
253///
254/// Address = `0x02`
255///
256/// ## Fields
257///
258/// `erx_p0` and `erx_p1` default to 1.
259///
260/// #### `erx_pN` | bit `N`
261/// Enable RX adddress on data pipes `N` = 0-5.
262///
263/// ## Example
264/// ```rust
265/// use nrf24l01_commands::registers;
266///
267/// // Default value
268/// let reg = registers::EnRxaddr::new();
269/// assert_eq!(reg.into_bits(), 0b0000_0011);
270///
271/// // Write fields
272/// let reg = registers::EnRxaddr::new()
273/// .with_erx_p5(true)
274/// .with_erx_p4(false)
275/// .with_erx_p3(false)
276/// .with_erx_p2(false)
277/// .with_erx_p1(true)
278/// .with_erx_p0(false);
279/// assert_eq!(reg.into_bits(), 0b0010_0010);
280/// ```
281#[bitfield(u8, order = Msb)]
282pub struct EnRxaddr {
283 #[bits(2)]
284 __: u8,
285 /// Enable RX address for data pipe 5.
286 #[bits(1)]
287 pub erx_p5: bool,
288 /// Enable RX address for data pipe 4.
289 #[bits(1)]
290 pub erx_p4: bool,
291 /// Enable RX address for data pipe 3.
292 #[bits(1)]
293 pub erx_p3: bool,
294 /// Enable RX address for data pipe 2.
295 #[bits(1)]
296 pub erx_p2: bool,
297 /// Enable RX address for data pipe 1.
298 #[bits(1, default = true)]
299 pub erx_p1: bool,
300 /// Enable RX address for data pipe 0.
301 #[bits(1, default = true)]
302 pub erx_p0: bool,
303}
304
305impl const Register for EnRxaddr {
306 const ADDRESS: u8 = 0x02;
307
308 fn into_bits(self) -> u8 {
309 self.into_bits()
310 }
311}
312
313/// # SETUP_AW register
314/// Set up address width. This applies to [`TxAddr`] and all RX addresses for data pipes.
315///
316/// Address = `0x03`
317///
318/// ## Fields
319///
320/// #### `aw` | bits 1:0
321/// Address width. Default value: `11` (5 byte address).
322/// Enum: [`AddressWidth`](crate::fields::AddressWidth).
323///
324/// ## Example
325/// ```rust
326/// use nrf24l01_commands::{fields, registers};
327///
328/// // Default value
329/// let reg = registers::SetupAw::new();
330/// assert_eq!(reg.into_bits(), 0b0000_0011);
331///
332/// // Write fields
333/// let reg = registers::SetupAw::new().with_aw(fields::AddressWidth::FourByte);
334/// assert_eq!(reg.into_bits(), 0b0000_0010);
335/// ```
336#[bitfield(u8, order = Msb)]
337pub struct SetupAw {
338 #[bits(6)]
339 __: u8,
340
341 /// Address width. Default value: `11` (5 byte address).
342 /// Enum: [`AddressWidth`](crate::fields::AddressWidth).
343 #[bits(2, default = fields::AddressWidth::FiveByte)]
344 pub aw: fields::AddressWidth,
345}
346
347impl const Register for SetupAw {
348 const ADDRESS: u8 = 0x03;
349
350 fn into_bits(self) -> u8 {
351 self.into_bits()
352 }
353}
354
355/// # SETUP_RETR register
356/// Set up 'Automatic Retransmission'.
357///
358/// Address = `0x04`
359///
360/// ## Fields
361///
362/// #### `ard` | bits 7:4
363/// Auto retransmit delay. Enum: [`AutoRetransmitDelay`](crate::fields::AutoRetransmitDelay).
364///
365/// #### `arc` | bits 3:0
366/// Maximum auto retransmits. Default value: `0011` (3 retransmits)
367///
368/// `0000`: Auto retransmit disabled
369///
370/// `0001`: Up to 1 retransmit
371///
372/// `0010`: Up to 2 retransmits
373///
374/// ……
375///
376/// `1111`: Up to 15 retransmits
377///
378/// ## Example
379/// ```rust
380/// use nrf24l01_commands::{fields, registers};
381///
382/// // Default value
383/// let reg = registers::SetupRetr::new();
384/// assert_eq!(reg.into_bits(), 0b0000_0011);
385///
386/// // Write fields
387/// let reg = registers::SetupRetr::new()
388/// .with_ard(fields::AutoRetransmitDelay::US750)
389/// .with_arc(0b1111);
390/// assert_eq!(reg.into_bits(), 0b0010_1111);
391/// ```
392#[bitfield(u8, order = Msb)]
393pub struct SetupRetr {
394 /// Auto retransmit delay. Enum: [`AutoRetransmitDelay`](crate::fields::AutoRetransmitDelay).
395 #[bits(4)]
396 pub ard: fields::AutoRetransmitDelay,
397
398 /// Maximum auto retransmits. Default value: `0011` (3 retransmits)
399 ///
400 /// `0000`: Auto retransmit disabled
401 ///
402 /// `0001`: Up to 1 retransmit
403 ///
404 /// `0010`: Up to 2 retransmits
405 ///
406 /// ……
407 ///
408 /// `1111`: Up to 15 retransmits
409 #[bits(4, default = 3)]
410 pub arc: u8,
411}
412
413impl const Register for SetupRetr {
414 const ADDRESS: u8 = 0x04;
415
416 fn into_bits(self) -> u8 {
417 self.into_bits()
418 }
419}
420
421/// # RF_CH register
422/// Set RF channel.
423///
424/// Address = `0x05`
425///
426/// ## Fields
427/// #### `rf_ch` | bits 6:0
428/// Sets the frequency channel to operate on 0 - 125. Default value: `2`.
429///
430/// ## Example
431/// ```rust
432/// use nrf24l01_commands::registers;
433///
434/// // Default value
435/// let reg = registers::RfCh::new();
436/// assert_eq!(reg.into_bits(), 0b0000_0010);
437///
438/// // Write fields
439/// let reg = registers::RfCh::new().with_rf_ch(89);
440/// assert_eq!(reg.into_bits(), 89);
441/// ```
442#[bitfield(u8, order = Msb)]
443pub struct RfCh {
444 #[bits(1)]
445 __: bool,
446
447 /// Sets the frequency channel to operate on 0 - 125. Default value: `2`.
448 #[bits(7, default = 2)]
449 pub rf_ch: u8,
450}
451
452impl const Register for RfCh {
453 const ADDRESS: u8 = 0x05;
454
455 fn into_bits(self) -> u8 {
456 self.into_bits()
457 }
458}
459
460/// # RF_SETUP register
461/// Set RF air data rate and output power.
462///
463/// Address = `0x06`
464///
465/// ## Fields
466/// #### `cont_wave` | bit 7
467/// Enables continuous carrier transmit.
468///
469/// #### `rf_dr_low` | bit 5
470/// Set RF data rate to 250kbps. See `rf_dr_high`.
471///
472/// #### `pll_lock` | bit 4
473/// Force PLL lock signal. Only used in test.
474///
475/// #### `rf_dr_high` | bit 3
476/// Select between the high speed data rates. This bit
477/// is don’t care if `rf_dr_low` is set. Enum: [`RfDrHigh`](crate::fields::RfDrHigh).
478/// Default value: `1` (2 Mbps).
479///
480/// Encoding [RF_DR_LOW, RF_DR_HIGH]:
481///
482/// `00` - 1Mbps
483///
484/// `01` - 2Mbps
485///
486/// `10` - 250kbps
487///
488/// `11` - Reserved
489///
490/// #### `rf_pwr` | bits 2:1
491/// RF output power in TX mode. Enum: [`RfPower`](crate::fields::RfPower).
492/// Default value: `11` (0 dBm).
493///
494/// ## Example
495/// ```rust
496/// use nrf24l01_commands::{fields, registers};
497///
498/// // Default value
499/// let reg = registers::RfSetup::new();
500/// assert_eq!(reg.into_bits(), 0b0000_1110);
501///
502/// // Write fields
503/// let reg = registers::RfSetup::new()
504/// .with_pll_lock(false)
505/// .with_rf_dr_low(true)
506/// .with_rf_dr_high(fields::RfDrHigh::Mbps1)
507/// .with_rf_pwr(fields::RfPower::Neg6Dbm);
508/// assert_eq!(reg.into_bits(), 0b0010_0100);
509///
510/// // Read fields
511/// assert_eq!(reg.rf_pwr(), fields::RfPower::Neg6Dbm);
512/// ```
513#[bitfield(u8, order = Msb)]
514pub struct RfSetup {
515 /// Enables continuous carrier transmit.
516 #[bits(1)]
517 pub cont_wave: bool,
518
519 #[bits(1)]
520 __: bool,
521
522 /// Set RF data rate to 250kbps. See `rf_dr_high`.
523 #[bits(1)]
524 pub rf_dr_low: bool,
525
526 /// Force PLL lock signal. Only used in test.
527 #[bits(1)]
528 pub pll_lock: bool,
529
530 /// Select between the high speed data rates. This bit
531 /// is don’t care if `rf_dr_low` is set. Enum: [`RfDrHigh`](crate::fields::RfDrHigh).
532 /// Default value: `1` (2 Mbps).
533 ///
534 /// Encoding [RF_DR_LOW, RF_DR_HIGH]:
535 ///
536 /// `00` - 1Mbps
537 ///
538 /// `01` - 2Mbps
539 ///
540 /// `10` - 250kbps
541 ///
542 /// `11` - Reserved
543 #[bits(1, default = fields::RfDrHigh::Mbps2)]
544 pub rf_dr_high: fields::RfDrHigh,
545
546 /// RF output power in TX mode. Enum: [`RfPower`](crate::fields::RfPower).
547 /// Default value: `11` (0 dBm).
548 #[bits(2, default = fields::RfPower::Dbm0)]
549 pub rf_pwr: fields::RfPower,
550
551 #[bits(1)]
552 __: bool,
553}
554
555impl const Register for RfSetup {
556 const ADDRESS: u8 = 0x06;
557
558 fn into_bits(self) -> u8 {
559 self.into_bits()
560 }
561}
562
563/// # STATUS register
564///
565/// Address = `0x07`
566///
567/// ## Fields
568/// #### `rx_dr` | bit 6
569/// Data ready RX FIFO interrupt. Asserted when new data arrives in RX FIFO. Write 1 to clear bit.
570///
571/// #### `tx_ds` | bit 5
572/// Data sent TX FIFO interrupt. Asserted when packet is transmitted. If AUTO_ACK is activated, ACK must be received before interrupt goes high. Write 1 to clear bit.
573///
574/// #### `max_rt` | bit 4
575/// Maximum number of TX retransmits interrupt. If MAX_RT is asserted it must be cleared before communication can continue. Write 1 to clear bit.
576///
577/// #### `rx_p_no` | bits 3:1
578/// Data pipe number for the payload available from reading RX FIFO. This field is read-only.
579/// Enum: [`RxPipeNo`](crate::fields::RxPipeNo).
580///
581/// #### `tx_full` | bit 0
582/// TX FIFO full flag. This field is read-only.
583///
584/// `0`: Not full
585///
586/// `1`: TX FIFO full
587///
588/// ## Example
589/// ```rust
590/// use nrf24l01_commands::{fields, registers};
591///
592/// // Default value
593/// let reg = registers::Status::new();
594/// assert_eq!(reg.into_bits(), 0);
595///
596/// // Read fields
597/// let reg = registers::Status::from_bits(0b0011_0101);
598/// assert!(!reg.rx_dr());
599/// assert!(reg.tx_ds());
600/// assert!(reg.max_rt());
601/// assert_eq!(reg.rx_p_no(), fields::RxPipeNo::Pipe2);
602/// assert!(reg.tx_full());
603///
604/// // Write fields
605/// let reg = registers::Status::new()
606/// .with_rx_dr(false)
607/// .with_tx_ds(true)
608/// .with_max_rt(false);
609/// assert_eq!(reg.into_bits(), 0b0010_0000);
610/// ```
611#[bitfield(u8, order = Msb)]
612pub struct Status {
613 #[bits(1)]
614 __: bool,
615
616 /// Data ready RX FIFO interrupt. Asserted when new data arrives in RX FIFO. Write 1 to clear bit.
617 #[bits(1)]
618 pub rx_dr: bool,
619
620 /// Data sent TX FIFO interrupt. Asserted when packet is transmitted. If AUTO_ACK is activated, ACK must be received before interrupt goes high. Write 1 to clear bit.
621 #[bits(1)]
622 pub tx_ds: bool,
623
624 /// Maximum number of TX retransmits interrupt. If MAX_RT is asserted it must be cleared before communication can continue. Write 1 to clear bit.
625 #[bits(1)]
626 pub max_rt: bool,
627
628 /// Data pipe number for the payload available from reading RX FIFO. This field is read-only.
629 /// Enum: [`RxPipeNo`](crate::fields::RxPipeNo).
630 #[bits(3, access = RO)]
631 pub rx_p_no: fields::RxPipeNo,
632
633 /// TX FIFO full flag. This field is read-only.
634 ///
635 /// `0`: Not full
636 ///
637 /// `1`: TX FIFO full
638 #[bits(1, access = RO)]
639 pub tx_full: bool,
640}
641
642impl const Register for Status {
643 const ADDRESS: u8 = 0x07;
644
645 fn into_bits(self) -> u8 {
646 self.into_bits()
647 }
648}
649
650/// # OBSERVE_TX register
651/// Transmit observe register.
652///
653/// Address = `0x08`
654///
655/// #### `plos_cnt` | bits 7:4
656/// Count lost packets. This counter is overflow protected to 15,
657/// and continues at max until reset. This counter is reset by writing
658/// to [`RfCh`]. This field is read-only.
659///
660/// #### `arc_cnt` | 3:0
661/// Count retransmitted packets. The counter is reset when transmission
662/// of a new packet starts. This field is read-only.
663///
664/// ## Example
665/// ```rust
666/// use nrf24l01_commands::registers;
667///
668/// // Default value
669/// let reg = registers::ObserveTx::new();
670/// assert_eq!(reg.into_bits(), 0);
671///
672/// // Read fields
673/// let reg = registers::ObserveTx::from_bits(0b1010_1100);
674/// assert_eq!(reg.plos_cnt(), 10);
675/// assert_eq!(reg.arc_cnt(), 12);
676/// ```
677#[bitfield(u8, order = Msb)]
678pub struct ObserveTx {
679 /// Count lost packets. This counter is overflow protected to 15,
680 /// and continues at max until reset. This counter is reset by writing
681 /// to __RF_CH__. This field is read-only.
682 #[bits(4, access = RO)]
683 pub plos_cnt: u8,
684
685 /// Count retransmitted packets. The counter is reset when transmission
686 /// of a new packet starts. This field is read-only.
687 #[bits(4, access = RO)]
688 pub arc_cnt: u8,
689}
690
691impl const Register for ObserveTx {
692 const ADDRESS: u8 = 0x08;
693
694 fn into_bits(self) -> u8 {
695 self.into_bits()
696 }
697}
698
699/// # RPD register
700/// Received power detector.
701///
702/// Address = `0x09`
703///
704/// ## Fields
705/// #### `rpd` | bit 0
706/// Triggers at received power levels above -64 dBm that are present
707/// in the RF channel you receive on. If the received power is less
708/// than -64 dBm, RDP = 0.
709///
710/// ## Example
711/// ```rust
712/// use nrf24l01_commands::registers;
713///
714/// let reg = registers::Rpd::from_bits(1);
715/// assert!(reg.rpd());
716/// ```
717#[bitfield(u8, order = Msb)]
718pub struct Rpd {
719 #[bits(7)]
720 __: u8,
721
722 /// Triggers at received power levels above -64 dBm that are present
723 /// in the RF channel you receive on. If the received power is less
724 /// than -64 dBm, RDP = 0.
725 #[bits(1, access = RO)]
726 pub rpd: bool,
727}
728
729impl const Register for Rpd {
730 const ADDRESS: u8 = 0x09;
731
732 fn into_bits(self) -> u8 {
733 self.into_bits()
734 }
735}
736
737/// # RX_ADDR_P0 register
738/// RX address data pipe 0.
739///
740/// Address = `0x0A`
741///
742/// Const parameter `N`: address width in bytes.
743/// <div class="warning">
744/// N must be of {3, 4, 5}.
745/// </div>
746///
747/// ## Fields
748/// #### `rx_addr_p0` | bits 39:0
749/// RX address data pipe 0. Default value: `0xE7E7E7E7E7`.
750///
751/// ## Example
752/// ```rust
753/// use nrf24l01_commands::registers::{self, AddressRegister};
754///
755/// // Default value
756/// let reg = registers::RxAddrP0::<4>::new();
757/// assert_eq!(reg.into_bits(), 0xE7E7E7E7E7);
758///
759/// // Write fields
760/// let reg = registers::RxAddrP0::<5>::new().with_rx_addr_p0(0xC2840DF659);
761/// assert_eq!(reg.into_bits(), 0xC2840DF659);
762///
763/// // Convert to little-endian bytes
764/// assert_eq!(reg.into_bytes(), [0x59, 0xF6, 0x0D, 0x84, 0xC2]);
765///
766/// // 3 byte address width
767/// let reg = registers::RxAddrP0::<3>::new().with_rx_addr_p0(0xC2840DF659);
768/// assert_eq!(reg.into_bytes(), [0x59, 0xF6, 0x0D]);
769/// ```
770#[derive(Copy, Clone)]
771pub struct RxAddrP0<const N: usize>(RxAddrP0Fields);
772
773#[bitfield(u64, order = Msb)]
774struct RxAddrP0Fields {
775 #[bits(24)]
776 __: u32,
777
778 /// RX address data pipe 0. Default value: `0xE7E7E7E7E7`.
779 #[bits(40, default = 0xE7E7E7E7E7)]
780 rx_addr_p0: u64,
781}
782
783/// Convert u64 address to little-endian bytes.
784/// Const parameter `N`: address width in bytes. Constraint: `N` in {3, 4, 5}.
785#[inline(always)]
786const fn address_into_bytes<const N: usize>(addr: u64) -> [u8; N] {
787 let le_bytes: [u8; 8] = addr.to_le_bytes();
788 let mut bytes = [0; N];
789 let mut i = 0;
790 while i < N {
791 bytes[i] = le_bytes[i];
792 i += 1;
793 }
794 bytes
795}
796
797impl<const N: usize> const AddressRegister<N> for RxAddrP0<N> {
798 const ADDRESS: u8 = 0x0A;
799
800 fn new() -> Self {
801 Self(RxAddrP0Fields::new())
802 }
803
804 fn from_bits(bits: u64) -> Self {
805 Self(RxAddrP0Fields::from_bits(bits))
806 }
807
808 fn into_bits(self) -> u64 {
809 self.0.into_bits()
810 }
811
812 fn into_bytes(self) -> [u8; N] {
813 address_into_bytes(self.0.0)
814 }
815}
816
817impl<const N: usize> RxAddrP0<N> {
818 /// RX address data pipe 0. Default value: `0xE7E7E7E7E7`.
819 pub const fn rx_addr_p0(&self) -> u64 {
820 self.0.rx_addr_p0()
821 }
822
823 /// RX address data pipe 0. Default value: `0xE7E7E7E7E7`.
824 pub const fn with_rx_addr_p0(mut self, value: u64) -> Self {
825 self.0 = self.0.with_rx_addr_p0(value);
826 self
827 }
828}
829
830impl<const N: usize> Default for RxAddrP0<N> {
831 fn default() -> Self {
832 Self::new()
833 }
834}
835
836/// # RX_ADDR_P1 register
837/// RX address data pipe 1.
838///
839/// Address = `0x0B`
840///
841/// Const parameter `N`: address width in bytes.
842/// <div class="warning">
843/// N must be of {3, 4, 5}.
844/// </div>
845///
846/// ## Fields
847/// #### `rx_addr_p1` | bits 39:0
848/// RX address data pipe 1. Default value: `0xC2C2C2C2C2`.
849///
850/// ## Example
851/// ```rust
852/// use nrf24l01_commands::{registers, registers::AddressRegister};
853///
854/// // Default value
855/// let reg = registers::RxAddrP1::<4>::new();
856/// assert_eq!(reg.into_bits(), 0xC2C2C2C2C2);
857///
858/// // Write fields
859/// let reg = registers::RxAddrP1::<5>::new().with_rx_addr_p1(0xC2840DF659);
860/// assert_eq!(reg.into_bits(), 0xC2840DF659);
861///
862/// // Convert to little-endian bytes
863/// assert_eq!(reg.into_bytes(), [0x59, 0xF6, 0x0D, 0x84, 0xC2]);
864///
865/// // 3 byte address width
866/// let reg = registers::RxAddrP1::<3>::new().with_rx_addr_p1(0xC2840DF659);
867/// assert_eq!(reg.into_bytes(), [0x59, 0xF6, 0x0D]);
868/// ```
869#[derive(Copy, Clone)]
870pub struct RxAddrP1<const N: usize>(RxAddrP1Fields);
871
872#[bitfield(u64, order = Msb)]
873struct RxAddrP1Fields {
874 #[bits(24)]
875 __: u32,
876
877 /// RX address data pipe 1. Default value: `0xC2C2C2C2C2`.
878 #[bits(40, default = 0xC2C2C2C2C2)]
879 rx_addr_p1: u64,
880}
881
882impl<const N: usize> const AddressRegister<N> for RxAddrP1<N> {
883 const ADDRESS: u8 = 0x0B;
884
885 fn new() -> Self {
886 Self(RxAddrP1Fields::new())
887 }
888
889 fn from_bits(bits: u64) -> Self {
890 Self(RxAddrP1Fields::from_bits(bits))
891 }
892
893 fn into_bits(self) -> u64 {
894 self.0.into_bits()
895 }
896
897 fn into_bytes(self) -> [u8; N] {
898 address_into_bytes(self.0.0)
899 }
900}
901
902impl<const N: usize> RxAddrP1<N> {
903 /// RX address data pipe 1. Default value: `0xC2C2C2C2C2`.
904 pub const fn rx_addr_p1(&self) -> u64 {
905 self.0.rx_addr_p1()
906 }
907
908 /// RX address data pipe 1. Default value: `0xC2C2C2C2C2`.
909 pub const fn with_rx_addr_p1(mut self, value: u64) -> Self {
910 self.0 = self.0.with_rx_addr_p1(value);
911 self
912 }
913}
914
915impl<const N: usize> Default for RxAddrP1<N> {
916 fn default() -> Self {
917 Self::new()
918 }
919}
920
921/// # RX_ADDR_P2 register
922/// RX address data pipe 2. Only LSByte is stored.
923/// MSBytes are equal to [`RxAddrP1`] bits 39:8.
924///
925/// Address = `0x0C`
926///
927/// ## Fields
928/// #### `rx_addr_p2` | bits 7:0
929/// RX address data pipe 2. Default value: `0xC3`.
930///
931/// ## Example
932/// ```rust
933/// use nrf24l01_commands::registers;
934///
935/// // Default value
936/// let reg = registers::RxAddrP2::new();
937/// assert_eq!(reg.into_bits(), 0xC3);
938///
939/// // Write fields
940/// let reg = registers::RxAddrP2::new().with_rx_addr_p2(172);
941/// assert_eq!(reg.into_bits(), 172);
942/// ```
943#[bitfield(u8)]
944pub struct RxAddrP2 {
945 /// RX address data pipe 2. Default value: `0xC3`.
946 #[bits(8, default = 0xC3)]
947 pub rx_addr_p2: u8,
948}
949
950impl const Register for RxAddrP2 {
951 const ADDRESS: u8 = 0x0C;
952
953 fn into_bits(self) -> u8 {
954 self.into_bits()
955 }
956}
957
958/// # RX_ADDR_P3 register
959/// RX address data pipe 3. Only LSByte is stored.
960/// MSBytes are equal to [`RxAddrP1`] bits 39:8.
961///
962/// Address = `0x0D`
963///
964/// ## Fields
965/// #### `rx_addr_p3` | bits 7:0
966/// RX address data pipe 3. Default value: `0xC4`.
967///
968/// ## Example
969/// ```rust
970/// use nrf24l01_commands::registers;
971///
972/// // Default value
973/// let reg = registers::RxAddrP3::new();
974/// assert_eq!(reg.into_bits(), 0xC4);
975///
976/// // Write fields
977/// let reg = registers::RxAddrP3::new().with_rx_addr_p3(172);
978/// assert_eq!(reg.into_bits(), 172);
979/// ```
980#[bitfield(u8)]
981pub struct RxAddrP3 {
982 /// RX address data pipe 3. Default value: `0xC4`.
983 #[bits(8, default = 0xC4)]
984 pub rx_addr_p3: u8,
985}
986
987impl const Register for RxAddrP3 {
988 const ADDRESS: u8 = 0x0D;
989
990 fn into_bits(self) -> u8 {
991 self.into_bits()
992 }
993}
994
995/// # RX_ADDR_P4 register
996/// RX address data pipe 4. Only LSByte is stored.
997/// MSBytes are equal to [`RxAddrP1`] bits 39:8.
998///
999/// Address = `0x0E`
1000///
1001/// ## Fields
1002/// #### `rx_addr_p4` | bits 7:0
1003/// RX address data pipe 4. Default value: `0xC5`.
1004///
1005/// ## Example
1006/// ```rust
1007/// use nrf24l01_commands::registers;
1008///
1009/// // Default value
1010/// let reg = registers::RxAddrP4::new();
1011/// assert_eq!(reg.into_bits(), 0xC5);
1012///
1013/// // Write fields
1014/// let reg = registers::RxAddrP4::new().with_rx_addr_p4(172);
1015/// assert_eq!(reg.into_bits(), 172);
1016/// ```
1017#[bitfield(u8)]
1018pub struct RxAddrP4 {
1019 /// RX address data pipe 4. Default value: `0xC5`.
1020 #[bits(8, default = 0xC5)]
1021 pub rx_addr_p4: u8,
1022}
1023
1024impl const Register for RxAddrP4 {
1025 const ADDRESS: u8 = 0x0E;
1026
1027 fn into_bits(self) -> u8 {
1028 self.into_bits()
1029 }
1030}
1031
1032/// # RX_ADDR_P5 register
1033/// RX address data pipe 5. Only LSByte is stored.
1034/// MSBytes are equal to [`RxAddrP1`] bits 39:8.
1035///
1036/// Address = `0x0F`
1037///
1038/// ## Fields
1039/// #### `rx_addr_p5` | bits 7:0
1040/// RX address data pipe 5. Default value: `0xC6`.
1041///
1042/// ## Example
1043/// ```rust
1044/// use nrf24l01_commands::registers;
1045///
1046/// // Default value
1047/// let reg = registers::RxAddrP5::new();
1048/// assert_eq!(reg.into_bits(), 0xC6);
1049///
1050/// // Write fields
1051/// let reg = registers::RxAddrP5::new().with_rx_addr_p5(172);
1052/// assert_eq!(reg.into_bits(), 172);
1053/// ```
1054#[bitfield(u8)]
1055pub struct RxAddrP5 {
1056 /// RX address data pipe 5. Default value: `0xC6`.
1057 #[bits(8, default = 0xC6)]
1058 pub rx_addr_p5: u8,
1059}
1060
1061impl const Register for RxAddrP5 {
1062 const ADDRESS: u8 = 0x0F;
1063
1064 fn into_bits(self) -> u8 {
1065 self.into_bits()
1066 }
1067}
1068
1069/// # TX_ADDR register
1070/// TX address. Set [`RxAddrP0`] equal to this address to handle ACK automatically.
1071///
1072/// Address = `0x10`
1073///
1074/// Const parameter `N`: address width in bytes.
1075/// <div class="warning">
1076/// N must be of {3, 4, 5}.
1077/// </div>
1078///
1079/// ## Fields
1080/// #### `tx_addr` | bits 39:0
1081/// TX address. Default value: `0xE7E7E7E7E7`.
1082///
1083/// ## Example
1084/// ```rust
1085/// use nrf24l01_commands::{registers, registers::AddressRegister};
1086///
1087/// // Default value
1088/// let reg = registers::TxAddr::<4>::new();
1089/// assert_eq!(reg.into_bits(), 0xE7E7E7E7E7);
1090///
1091/// // Write fields
1092/// let reg = registers::TxAddr::<5>::new().with_tx_addr(0xC2840DF659);
1093/// assert_eq!(reg.into_bits(), 0xC2840DF659);
1094///
1095/// // Convert to little-endian bytes
1096/// assert_eq!(reg.into_bytes(), [0x59, 0xF6, 0x0D, 0x84, 0xC2]);
1097///
1098/// // 3 byte address width
1099/// let reg = registers::TxAddr::<3>::new().with_tx_addr(0xC2840DF659);
1100/// assert_eq!(reg.into_bytes(), [0x59, 0xF6, 0x0D]);
1101/// ```
1102#[derive(Copy, Clone)]
1103pub struct TxAddr<const N: usize>(TxAddrFields);
1104
1105#[bitfield(u64, order = Msb)]
1106struct TxAddrFields {
1107 #[bits(24)]
1108 __: u32,
1109
1110 /// TX address. Default value: `0xE7E7E7E7E7`.
1111 #[bits(40, default = 0xE7E7E7E7E7)]
1112 tx_addr: u64,
1113}
1114
1115impl<const N: usize> const AddressRegister<N> for TxAddr<N> {
1116 const ADDRESS: u8 = 0x10;
1117
1118 fn new() -> Self {
1119 Self(TxAddrFields::new())
1120 }
1121
1122 fn from_bits(bits: u64) -> Self {
1123 Self(TxAddrFields::from_bits(bits))
1124 }
1125
1126 fn into_bits(self) -> u64 {
1127 self.0.into_bits()
1128 }
1129
1130 fn into_bytes(self) -> [u8; N] {
1131 address_into_bytes(self.0.0)
1132 }
1133}
1134
1135impl<const N: usize> TxAddr<N> {
1136 /// TX address. Default value: `0xE7E7E7E7E7`.
1137 pub const fn tx_addr(&self) -> u64 {
1138 self.0.tx_addr()
1139 }
1140
1141 /// TX address. Default value: `0xE7E7E7E7E7`.
1142 pub const fn with_tx_addr(mut self, value: u64) -> Self {
1143 self.0 = self.0.with_tx_addr(value);
1144 self
1145 }
1146}
1147
1148impl<const N: usize> Default for TxAddr<N> {
1149 fn default() -> Self {
1150 Self::new()
1151 }
1152}
1153
1154/// # RX_PW_P0 register
1155/// RX payload width for data pipe 0.
1156///
1157/// Address = `0x11`
1158///
1159/// ## Fields
1160/// #### `rx_pw_p0` | bits 7:0
1161/// RX payload width for data pipe 0. 1 - 32 bytes. `0` = pipe not used.
1162///
1163/// ## Example
1164/// ```rust
1165/// use nrf24l01_commands::registers;
1166///
1167/// // Default value
1168/// let reg = registers::RxPwP0::new();
1169/// assert_eq!(reg.into_bits(), 0);
1170///
1171/// // Write fields
1172/// let reg = registers::RxPwP0::new().with_rx_pw_p0(31);
1173/// assert_eq!(reg.into_bits(), 31);
1174/// ```
1175#[bitfield(u8, order = Msb)]
1176pub struct RxPwP0 {
1177 #[bits(2)]
1178 __: u8,
1179
1180 /// RX payload width for data pipe 0. 1 - 32 bytes. `0` = pipe not used.
1181 #[bits(6)]
1182 pub rx_pw_p0: u8,
1183}
1184
1185impl const Register for RxPwP0 {
1186 const ADDRESS: u8 = 0x11;
1187
1188 fn into_bits(self) -> u8 {
1189 self.into_bits()
1190 }
1191}
1192
1193/// # RX_PW_P1 register
1194/// RX payload width for data pipe 1.
1195///
1196/// Address = `0x12`
1197///
1198/// ## Fields
1199/// #### `rx_pw_p1` | bits 7:0
1200/// RX payload width for data pipe 1. 1 - 32 bytes. `0` = pipe not used.
1201///
1202/// ## Example
1203/// ```rust
1204/// use nrf24l01_commands::registers;
1205///
1206/// // Default value
1207/// let reg = registers::RxPwP1::new();
1208/// assert_eq!(reg.into_bits(), 0);
1209///
1210/// // Write fields
1211/// let reg = registers::RxPwP1::new().with_rx_pw_p1(31);
1212/// assert_eq!(reg.into_bits(), 31);
1213/// ```
1214#[bitfield(u8, order = Msb)]
1215pub struct RxPwP1 {
1216 #[bits(2)]
1217 __: u8,
1218
1219 /// RX payload width for data pipe 1. 1 - 32 bytes. `0` = pipe not used.
1220 #[bits(6)]
1221 pub rx_pw_p1: u8,
1222}
1223
1224impl const Register for RxPwP1 {
1225 const ADDRESS: u8 = 0x12;
1226
1227 fn into_bits(self) -> u8 {
1228 self.into_bits()
1229 }
1230}
1231
1232/// # RX_PW_P2 register
1233/// RX payload width for data pipe 2.
1234///
1235/// Address = `0x13`
1236///
1237/// ## Fields
1238/// #### `rx_pw_p2` | bits 7:0
1239/// RX payload width for data pipe 2. 1 - 32 bytes. `0` = pipe not used.
1240///
1241/// ## Example
1242/// ```rust
1243/// use nrf24l01_commands::registers;
1244///
1245/// // Default value
1246/// let reg = registers::RxPwP2::new();
1247/// assert_eq!(reg.into_bits(), 0);
1248///
1249/// // Write fields
1250/// let reg = registers::RxPwP2::new().with_rx_pw_p2(31);
1251/// assert_eq!(reg.into_bits(), 31);
1252/// ```
1253#[bitfield(u8, order = Msb)]
1254pub struct RxPwP2 {
1255 #[bits(2)]
1256 __: u8,
1257
1258 /// RX payload width for data pipe 2. 1 - 32 bytes. `0` = pipe not used.
1259 #[bits(6)]
1260 pub rx_pw_p2: u8,
1261}
1262
1263impl const Register for RxPwP2 {
1264 const ADDRESS: u8 = 0x13;
1265
1266 fn into_bits(self) -> u8 {
1267 self.into_bits()
1268 }
1269}
1270
1271/// # RX_PW_P3 register
1272/// RX payload width for data pipe 3.
1273///
1274/// Address = `0x14`
1275///
1276/// ## Fields
1277/// #### `rx_pw_p3` | bits 7:0
1278/// RX payload width for data pipe 3. 1 - 32 bytes. `0` = pipe not used.
1279///
1280/// ## Example
1281/// ```rust
1282/// use nrf24l01_commands::registers;
1283///
1284/// // Default value
1285/// let reg = registers::RxPwP3::new();
1286/// assert_eq!(reg.into_bits(), 0);
1287///
1288/// // Write fields
1289/// let reg = registers::RxPwP3::new().with_rx_pw_p3(31);
1290/// assert_eq!(reg.into_bits(), 31);
1291/// ```
1292#[bitfield(u8, order = Msb)]
1293pub struct RxPwP3 {
1294 #[bits(2)]
1295 __: u8,
1296
1297 /// RX payload width for data pipe 3. 1 - 32 bytes. `0` = pipe not used.
1298 #[bits(6)]
1299 pub rx_pw_p3: u8,
1300}
1301
1302impl const Register for RxPwP3 {
1303 const ADDRESS: u8 = 0x14;
1304
1305 fn into_bits(self) -> u8 {
1306 self.into_bits()
1307 }
1308}
1309
1310/// # RX_PW_P4 register
1311/// RX payload width for data pipe 4.
1312///
1313/// Address = `0x15`
1314///
1315/// ## Fields
1316/// #### `rx_pw_p4` | bits 7:0
1317/// RX payload width for data pipe 4. 1 - 32 bytes. `0` = pipe not used.
1318///
1319/// ## Example
1320/// ```rust
1321/// use nrf24l01_commands::registers;
1322///
1323/// // Default value
1324/// let reg = registers::RxPwP4::new();
1325/// assert_eq!(reg.into_bits(), 0);
1326///
1327/// // Write fields
1328/// let reg = registers::RxPwP4::new().with_rx_pw_p4(31);
1329/// assert_eq!(reg.into_bits(), 31);
1330/// ```
1331#[bitfield(u8, order = Msb)]
1332pub struct RxPwP4 {
1333 #[bits(2)]
1334 __: u8,
1335
1336 /// RX payload width for data pipe 4. 1 - 32 bytes. `0` = pipe not used.
1337 #[bits(6)]
1338 pub rx_pw_p4: u8,
1339}
1340
1341impl const Register for RxPwP4 {
1342 const ADDRESS: u8 = 0x15;
1343
1344 fn into_bits(self) -> u8 {
1345 self.into_bits()
1346 }
1347}
1348
1349/// # RX_PW_P5 register
1350/// RX payload width for data pipe 5.
1351///
1352/// Address = `0x16`
1353///
1354/// ## Fields
1355/// #### `rx_pw_p5` | bits 7:0
1356/// RX payload width for data pipe 5. 1 - 32 bytes. `0` = pipe not used.
1357///
1358/// ## Example
1359/// ```rust
1360/// use nrf24l01_commands::registers;
1361///
1362/// // Default value
1363/// let reg = registers::RxPwP5::new();
1364/// assert_eq!(reg.into_bits(), 0);
1365///
1366/// // Write fields
1367/// let reg = registers::RxPwP5::new().with_rx_pw_p5(31);
1368/// assert_eq!(reg.into_bits(), 31);
1369/// ```
1370#[bitfield(u8, order = Msb)]
1371pub struct RxPwP5 {
1372 #[bits(2)]
1373 __: u8,
1374
1375 /// RX payload width for data pipe 5. 1 - 32 bytes. `0` = pipe not used.
1376 #[bits(6)]
1377 pub rx_pw_p5: u8,
1378}
1379
1380impl const Register for RxPwP5 {
1381 const ADDRESS: u8 = 0x16;
1382
1383 fn into_bits(self) -> u8 {
1384 self.into_bits()
1385 }
1386}
1387
1388/// # FIFO_STATUS register
1389/// Status of TX/RX FIFOs.
1390///
1391/// Address = `0x17`
1392///
1393/// ## Fields
1394/// All fields are read-only.
1395///
1396/// #### `tx_reuse` | bit 6
1397/// Reuse last transmitted data packet if set high.
1398/// The packet is repeatedly retransmitted as long as CE is high.
1399/// TX_REUSE is set by the [`REUSE_TX_PL`][crate::commands::ReuseTxPl] command and reset by
1400/// [`W_TX_PAYLOAD`][crate::commands::WTxPayloadNoack] or [`FLUSH_TX`][crate::commands::FlushTx].
1401///
1402/// #### `tx_full` | bit 5
1403/// TX FIFO full flag.
1404///
1405/// #### `tx_empty` | bit 4
1406/// TX FIFO empty flag.
1407///
1408/// #### `rx_full` | bit 1
1409/// RX FIFO full flag.
1410///
1411/// #### `rx_empty` | bit 0
1412/// RX FIFO empty flag.
1413///
1414/// ## Example
1415/// ```rust
1416/// use nrf24l01_commands::registers;
1417///
1418/// // Default value
1419/// let reg = registers::FifoStatus::new();
1420/// assert_eq!(reg.into_bits(), 0);
1421///
1422/// // Read fields
1423/// let reg = registers::FifoStatus::from_bits(0b0010_0010);
1424/// assert!(!reg.tx_reuse());
1425/// assert!(reg.tx_full());
1426/// assert!(!reg.tx_empty());
1427/// assert!(reg.rx_full());
1428/// assert!(!reg.rx_empty());
1429/// ```
1430#[bitfield(u8, order = Msb)]
1431pub struct FifoStatus {
1432 #[bits(1)]
1433 __: bool,
1434
1435 /// Reuse last transmitted data packet if set high.
1436 /// The packet is repeatedly retransmitted as long as CE is high.
1437 /// TX_REUSE is set by the REUSE_TX_PL command and reset by
1438 /// W_TX_PAYLOAD or FLUSH_TX.
1439 #[bits(1, access = RO)]
1440 pub tx_reuse: bool,
1441
1442 /// TX FIFO full flag.
1443 #[bits(1, access = RO)]
1444 pub tx_full: bool,
1445
1446 /// TX FIFO empty flag.
1447 #[bits(1, access = RO)]
1448 pub tx_empty: bool,
1449
1450 #[bits(2)]
1451 __: u8,
1452
1453 /// RX FIFO full flag.
1454 #[bits(1, access = RO)]
1455 pub rx_full: bool,
1456
1457 /// RX FIFO empty flag.
1458 #[bits(1, access = RO)]
1459 pub rx_empty: bool,
1460}
1461
1462impl const Register for FifoStatus {
1463 const ADDRESS: u8 = 0x17;
1464
1465 fn into_bits(self) -> u8 {
1466 self.into_bits()
1467 }
1468}
1469
1470/// # DYNPD register
1471/// Enable dynamic payload length for data pipes 0-5.
1472///
1473/// Address = `0x1C`
1474///
1475/// ## Fields
1476///
1477/// #### `dpl_pN` | bit `N`
1478/// Enable dynamic payload length on data pipes `N` = 0-5.
1479///
1480/// ## Example
1481/// ```rust
1482/// use nrf24l01_commands::registers;
1483///
1484/// // Default value
1485/// let reg = registers::Dynpd::new();
1486/// assert_eq!(reg.into_bits(), 0);
1487///
1488/// // Write fields
1489/// let reg = registers::Dynpd::new()
1490/// .with_dpl_p5(true)
1491/// .with_dpl_p4(false)
1492/// .with_dpl_p3(false)
1493/// .with_dpl_p2(false)
1494/// .with_dpl_p1(true)
1495/// .with_dpl_p0(false);
1496/// assert_eq!(reg.into_bits(), 0b0010_0010);
1497/// ```
1498#[bitfield(u8, order = Msb)]
1499pub struct Dynpd {
1500 #[bits(2)]
1501 __: u8,
1502
1503 /// Enable dynamic payload length for data pipe 5.
1504 /// Requires `en_dpl` in [`Feature`] and `enaa_p5` in [`EnAa`].
1505 #[bits(1)]
1506 pub dpl_p5: bool,
1507 /// Enable dynamic payload length for data pipe 4.
1508 /// Requires `en_dpl` in [`Feature`] and `enaa_p4` in [`EnAa`].
1509 #[bits(1)]
1510 pub dpl_p4: bool,
1511 /// Enable dynamic payload length for data pipe 3.
1512 /// Requires `en_dpl` in [`Feature`] and `enaa_p3` in [`EnAa`].
1513 #[bits(1)]
1514 pub dpl_p3: bool,
1515 /// Enable dynamic payload length for data pipe 2.
1516 /// Requires `en_dpl` in [`Feature`] and `enaa_p2` in [`EnAa`].
1517 #[bits(1)]
1518 pub dpl_p2: bool,
1519 /// Enable dynamic payload length for data pipe 1.
1520 /// Requires `en_dpl` in [`Feature`] and `enaa_p1` in [`EnAa`].
1521 #[bits(1)]
1522 pub dpl_p1: bool,
1523 /// Enable dynamic payload length for data pipe 0.
1524 /// Requires `en_dpl` in [`Feature`] and `enaa_p0` in [`EnAa`].
1525 #[bits(1)]
1526 pub dpl_p0: bool,
1527}
1528
1529impl const Register for Dynpd {
1530 const ADDRESS: u8 = 0x1C;
1531
1532 fn into_bits(self) -> u8 {
1533 self.into_bits()
1534 }
1535}
1536
1537/// # FEATURE register
1538/// Enable features _Dynamic Payload Length_, _Payload with ACK_ and `W_TX_PAYLOAD_NO_ACK` command.
1539///
1540/// Address = `0x01D`
1541///
1542/// ## Fields
1543/// #### `en_dpl` | bit 2
1544/// Enables _Dynamic Payload Length_.
1545///
1546/// #### `en_ack_pay` | bit 1
1547/// Enables _Payload with ACK_.
1548///
1549/// #### `en_dyn_ack` | bit 0
1550/// Enables `W_TX_PAYLOAD_NO_ACK` command.
1551///
1552/// ## Example
1553/// ```rust
1554/// use nrf24l01_commands::registers;
1555///
1556/// // Default value
1557/// let reg = registers::Feature::new();
1558/// assert_eq!(reg.into_bits(), 0);
1559///
1560/// // Write fields
1561/// let reg = registers::Feature::new()
1562/// .with_en_dpl(false)
1563/// .with_en_ack_pay(true)
1564/// .with_en_dyn_ack(true);
1565/// assert_eq!(reg.into_bits(), 0b0000_0011);
1566/// ```
1567#[bitfield(u8, order = Msb)]
1568pub struct Feature {
1569 #[bits(5)]
1570 __: u8,
1571
1572 /// Enables _Dynamic Payload Length_.
1573 #[bits(1)]
1574 pub en_dpl: bool,
1575
1576 /// Enables _Payload with ACK_.
1577 #[bits(1)]
1578 pub en_ack_pay: bool,
1579
1580 /// Enables 'W_TX_PAYLOAD_NO_ACK' command.
1581 #[bits(1)]
1582 pub en_dyn_ack: bool,
1583}
1584
1585impl const Register for Feature {
1586 const ADDRESS: u8 = 0x1D;
1587
1588 fn into_bits(self) -> u8 {
1589 self.into_bits()
1590 }
1591}