netlistdb 0.3.1

Heterogeneous VLSI circuit netlist database with support for vector nets, hierarchical modules, assignments, etc.
Documentation 
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use netlistdb::*;
use std::fs;
use arcstr::{ArcStr, Substr};
use itertools::Itertools;

#[test]
fn not_simple() {
    clilog::init_stderr_color_debug();
    
    let verilog = fs::read_to_string(
        concat!(env!("CARGO_MANIFEST_DIR"), "/tests/notsimple.v")
    ).expect("unable to read notsimple.v");

    let directions = |r#macro: &Substr, pin: &Substr, pinwidth: Option<isize>| {
        assert_eq!(pinwidth, None);
        use Direction::*;
        match (r#macro.as_str(), pin.as_str()) {
            (_, "a" | "b" | "ck" | "d") => I,
            (_, "o" | "q") => O,
            _ => Unknown
        }
    };
    
    let db: NetlistDB = NetlistDB::from_sverilog(
        ArcStr::from(verilog), None, &directions
    ).unwrap();
    
    println!("The database: {db:?}");
    assert_eq!(db.num_cells, 9);
    assert_eq!(db.num_pins, 24);
    assert_eq!(db.num_nets, 12);
    assert_eq!(format!("{}", db.cellnames.iter().skip(1).format(", ")),
               "u1, f1, dins1/u2, dins1/u3, dins2/u2, dins2/u3, ud12, u4");  // first one is empty.
    assert_eq!(format!("{}", db.celltypes.iter().format(", ")),
               "simple2_test, NAND2_X1, DFF_X80, INV_X1, INV_X2, INV_X1, INV_X2, NAND2_X1, NOR2_X1");
    assert_eq!(format!(
        "{}",
        db.pinnames.iter().map(|(hier, pin, idx)| {
            let hier = match hier.is_empty() {
                true => "".to_string(),
                false => format!("{}:", hier)
            };
            let idx = match idx {
                Some(v) => format!("[{}]", *v),
                None => "".to_string()
            };
            format!("{}{}{}", hier, pin, idx)
        }).format(", ")),
               "inp1, inp2, tau2015_clk, out, u1:a, u1:b, u1:o, f1:d, f1:ck, f1:q, dins1/u2:a, dins1/u2:o, dins1/u3:a, dins1/u3:o, dins2/u2:a, dins2/u2:o, dins2/u3:a, dins2/u3:o, ud12:a, ud12:b, ud12:o, u4:a, u4:b, u4:o");

    assert_eq!(db.pin2cell, vec![0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 7, 8, 8, 8].into());
    assert_eq!(db.pin2net, vec![0, 1, 2, 3, 0, 1, 6, 5, 2, 4, 4, 8, 8, 9, 4, 10, 10, 11, 9, 11, 3, 6, 4, 5].into());
    use Direction::*;
    assert_eq!(db.pindirect, vec![O, O, O, I, I, I, O, I, I, O, I, O, I, O, I, O, I, O, I, I, O, I, I, O].into());
    
    assert_eq!(db.net_zero, Some(7));
    assert_eq!(db.net_one, None);
}