netlistdb 0.3.1

Heterogeneous VLSI circuit netlist database with support for vector nets, hierarchical modules, assignments, etc.
Documentation 
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use netlistdb::NetlistDB;
use std::env;
use std::fs;
use arcstr::ArcStr;

fn main() {
    clilog::init_stderr_color_debug();
    let args: Vec<String> = env::args().collect();
    assert!(args.len() == 2 || args.len() == 3,
            "Usage: {} <verilog_path> [<top_module>]", args[0]);

    let verilog = fs::read_to_string(&args[1])
        .expect("Error reading sverilog source file");

    let db = NetlistDB::from_sverilog(
        ArcStr::from(verilog),
        args.get(2).map(|x| x.as_ref()),
        &netlistdb::NoDirection()
    ).expect("Error parsing the verilog into netlist");

    println!("Benchmark statistics for {}", args[1]);
    println!("top module: {}", db.name);
    println!("num cells:  {}", db.num_cells);
    println!("num nets:   {}", db.num_nets);
    println!("num pins:   {}", db.num_pins);
}