netlist 0.1.15

generic netlist data structure for VLSI design
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134

use super::base::{hier_identifier, number, tstring, ws};
use crate::model::PinDirection;
use nom::branch::alt;
use nom::bytes::complete::{is_not, tag};
use nom::combinator::{map, opt, value};
use nom::error::context;
use nom::multi::separated_list1;
use nom::sequence::{delimited, pair, preceded, separated_pair, terminated, tuple};

use super::ParseRes;

type BindingT<'a> = (&'a str, &'a str);

pub fn instantiate_stmt(s: &str) -> ParseRes<&str, (&str, &str, Vec<BindingT>)> {
    context(
        "Instantiate Statement",
        terminated(
            tuple((
                tstring,
                hier_identifier,
                delimited(
                    tag("("),
                    separated_list1(ws(tag(",")), binding_parser),
                    tag(")"),
                ),
            )),
            ws(tag(";")),
        ),
    )(s)
}

pub fn port_map_stmt(s: &str) -> ParseRes<&str, Vec<&str>> {
    context(
        "Port Map Statement",
        terminated(
            delimited(
                tag("("),
                separated_list1(ws(tag(",")), hier_identifier),
                tag(")"),
            ),
            ws(tag(";")),
        ),
    )(s)
}

pub fn port_direction_declare_stmt(
    s: &str,
) -> ParseRes<&str, (PinDirection, Option<(u32, u32)>, Vec<&str>)> {
    context(
        "Port Direction Declare Statement",
        alt((
            map(
                delimited(
                    ws(tag("input")),
                    tuple((opt(bitwidth), separated_list1(tag(","), hier_identifier))),
                    ws(tag(";")),
                ),
                |d| (PinDirection::Input, d.0, d.1),
            ),
            map(
                delimited(
                    ws(tag("output")),
                    tuple((opt(bitwidth), separated_list1(tag(","), hier_identifier))),
                    ws(tag(";")),
                ),
                |d| (PinDirection::Output, d.0, d.1),
            ),
        )),
    )(s)
}

// wire declare

// examples
// wire a1;
// wire [2:0] a2;
// wire a1, a2, a3;
pub fn wire_declare_stmt(s: &str) -> ParseRes<&str, (Option<(u32, u32)>, Vec<&str>)> {
    context(
        "Wire Declare Statement",
        delimited(
            ws(tag("wire")),
            tuple((opt(bitwidth), separated_list1(tag(","), hier_identifier))),
            ws(tag(";")),
        ),
    )(s)
}

// bus bit in wire declare or port declare

// examples
// wire [11:0] a;
// input [2:0] b;
pub fn bitwidth(s: &str) -> ParseRes<&str, (u32, u32)> {
    delimited(
        ws(tag("[")),
        separated_pair(number, ws(tag(":")), number),
        ws(tag("]")),
    )(s)
}

// verilog comment statment
pub fn comment(s: &str) -> ParseRes<&str, ()> {
    value(
        (), // Output is thrown away.
        pair(ws(tag("//")), is_not("\n\r")),
    )(s)
}

// pin2net binding

// examples
// .A(n1)
fn binding_parser(s: &str) -> ParseRes<&str, BindingT> {
    tuple((
        preceded(ws(tag(".")), tstring),
        delimited(ws(tag("(")), hier_identifier, ws(tag(")"))),
    ))(s)
}

#[cfg(test)]
mod test {
    use super::*;
    #[test]
    fn test_comment_1() {
        let input = "// Date      : Mon Jul 20 00:19:01 2020";
        let (_, _) = comment(input).unwrap();
    }
    #[test]
    fn test_comment_2() {
        let input = "///////////\n\r";
        let (_, _) = comment(input).unwrap();
    }
}