neoh 0.1.4

A declarative HDL transpiler for rapid testbench development.
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`timescale 1ns / 1ps

module my_logic();
  assign  x = a + b;
  assign  z = a - b;
  reg y;
endmodule
module tb_my_tb();
  my_logic dut();
  initial begin
    x 10 10;
  end
endmodule