n32g4/n32g455/comp/
comp4_ctrl.rs

1///Register `COMP4_CTRL` reader
2pub type R = crate::R<Comp4CtrlSpec>;
3///Register `COMP4_CTRL` writer
4pub type W = crate::W<Comp4CtrlSpec>;
5///Field `EN` reader - EN
6pub type EnR = crate::BitReader;
7///Field `EN` writer - EN
8pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `INMSEL` reader - INMSEL
10pub type InmselR = crate::FieldReader;
11///Field `INMSEL` writer - INMSEL
12pub type InmselW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13///Field `INPSEL` reader - INPSEL
14pub type InpselR = crate::FieldReader;
15///Field `INPSEL` writer - INPSEL
16pub type InpselW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17///Field `OUTSEL` reader - OUTSEL
18pub type OutselR = crate::FieldReader;
19///Field `OUTSEL` writer - OUTSEL
20pub type OutselW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21///Field `POL` reader - POL
22pub type PolR = crate::BitReader;
23///Field `POL` writer - POL
24pub type PolW<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `HYST` reader - HYST
26pub type HystR = crate::FieldReader;
27///Field `HYST` writer - HYST
28pub type HystW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29///Field `BLKING` reader - BLKING
30pub type BlkingR = crate::FieldReader;
31///Field `BLKING` writer - BLKING
32pub type BlkingW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
33///Field `OUT` reader - OUT
34pub type OutR = crate::BitReader;
35///Field `INPDAC` reader - INPDAC
36pub type InpdacR = crate::BitReader;
37///Field `INPDAC` writer - INPDAC
38pub type InpdacW<'a, REG> = crate::BitWriter<'a, REG>;
39impl R {
40    ///Bit 0 - EN
41    #[inline(always)]
42    pub fn en(&self) -> EnR {
43        EnR::new((self.bits & 1) != 0)
44    }
45    ///Bits 1:3 - INMSEL
46    #[inline(always)]
47    pub fn inmsel(&self) -> InmselR {
48        InmselR::new(((self.bits >> 1) & 7) as u8)
49    }
50    ///Bits 4:6 - INPSEL
51    #[inline(always)]
52    pub fn inpsel(&self) -> InpselR {
53        InpselR::new(((self.bits >> 4) & 7) as u8)
54    }
55    ///Bits 7:10 - OUTSEL
56    #[inline(always)]
57    pub fn outsel(&self) -> OutselR {
58        OutselR::new(((self.bits >> 7) & 0x0f) as u8)
59    }
60    ///Bit 11 - POL
61    #[inline(always)]
62    pub fn pol(&self) -> PolR {
63        PolR::new(((self.bits >> 11) & 1) != 0)
64    }
65    ///Bits 12:13 - HYST
66    #[inline(always)]
67    pub fn hyst(&self) -> HystR {
68        HystR::new(((self.bits >> 12) & 3) as u8)
69    }
70    ///Bits 14:16 - BLKING
71    #[inline(always)]
72    pub fn blking(&self) -> BlkingR {
73        BlkingR::new(((self.bits >> 14) & 7) as u8)
74    }
75    ///Bit 17 - OUT
76    #[inline(always)]
77    pub fn out(&self) -> OutR {
78        OutR::new(((self.bits >> 17) & 1) != 0)
79    }
80    ///Bit 18 - INPDAC
81    #[inline(always)]
82    pub fn inpdac(&self) -> InpdacR {
83        InpdacR::new(((self.bits >> 18) & 1) != 0)
84    }
85}
86impl W {
87    ///Bit 0 - EN
88    #[inline(always)]
89    #[must_use]
90    pub fn en(&mut self) -> EnW<Comp4CtrlSpec> {
91        EnW::new(self, 0)
92    }
93    ///Bits 1:3 - INMSEL
94    #[inline(always)]
95    #[must_use]
96    pub fn inmsel(&mut self) -> InmselW<Comp4CtrlSpec> {
97        InmselW::new(self, 1)
98    }
99    ///Bits 4:6 - INPSEL
100    #[inline(always)]
101    #[must_use]
102    pub fn inpsel(&mut self) -> InpselW<Comp4CtrlSpec> {
103        InpselW::new(self, 4)
104    }
105    ///Bits 7:10 - OUTSEL
106    #[inline(always)]
107    #[must_use]
108    pub fn outsel(&mut self) -> OutselW<Comp4CtrlSpec> {
109        OutselW::new(self, 7)
110    }
111    ///Bit 11 - POL
112    #[inline(always)]
113    #[must_use]
114    pub fn pol(&mut self) -> PolW<Comp4CtrlSpec> {
115        PolW::new(self, 11)
116    }
117    ///Bits 12:13 - HYST
118    #[inline(always)]
119    #[must_use]
120    pub fn hyst(&mut self) -> HystW<Comp4CtrlSpec> {
121        HystW::new(self, 12)
122    }
123    ///Bits 14:16 - BLKING
124    #[inline(always)]
125    #[must_use]
126    pub fn blking(&mut self) -> BlkingW<Comp4CtrlSpec> {
127        BlkingW::new(self, 14)
128    }
129    ///Bit 18 - INPDAC
130    #[inline(always)]
131    #[must_use]
132    pub fn inpdac(&mut self) -> InpdacW<Comp4CtrlSpec> {
133        InpdacW::new(self, 18)
134    }
135}
136///COMP4_CTRL
137///
138///You can [`read`](crate::generic::Reg::read) this register and get [`comp4_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`comp4_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
139pub struct Comp4CtrlSpec;
140impl crate::RegisterSpec for Comp4CtrlSpec {
141    type Ux = u32;
142}
143///`read()` method returns [`comp4_ctrl::R`](R) reader structure
144impl crate::Readable for Comp4CtrlSpec {}
145///`write(|w| ..)` method takes [`comp4_ctrl::W`](W) writer structure
146impl crate::Writable for Comp4CtrlSpec {
147    type Safety = crate::Unsafe;
148    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
149    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
150}
151///`reset()` method sets COMP4_CTRL to value 0
152impl crate::Resettable for Comp4CtrlSpec {
153    const RESET_VALUE: u32 = 0;
154}
n32g4/n32g455/comp/comp4_ctrl.rs

n32g4/n32g455/comp/
comp4_ctrl.rs
