<device xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.3" xsi:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
<vendor>ARM Ltd.</vendor>
<vendorID>ARM</vendorID>
<name>Musca_B1</name>
<series>ARMv8-M Mainline</series>
<version>1.0</version>
<description>ARM 32-bit v8-M Mainline based device</description>
<licenseText>
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
processor based microcontroller, but can be equally used for other\n
suitable processor architectures. This file can be freely distributed.\n
Modifications to this file shall be clearly marked.\n
\n
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
</licenseText>
<cpu>
<name>CM33</name>
<revision>r0p2</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>true</fpuPresent>
<nvicPrioBits>4</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
<sauNumRegions>8</sauNumRegions>
</cpu>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<peripherals>
<peripheral> <name>SYSINFO</name>
<version>1.0</version>
<description>System Information</description>
<groupName>SYSINFO</groupName>
<baseAddress>0x40020000</baseAddress>
<size>32</size>
<access>read-only</access>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SYS_VERSION</name>
<description>System Version Register</description>
<addressOffset>0x00</addressOffset>
<resetValue>0x22041743</resetValue>
<access>read-only</access>
<fields>
<field> <name>PART_NUMBER</name>
<description>Part Number for the SSE-200</description>
<bitRange>[11:0]</bitRange>
</field>
<field> <name>DESIGNER_ID</name>
<description>Arm Product with designer code 0x41</description>
<bitRange>[19:12]</bitRange>
</field>
<field> <name>MINOR_REVISION</name>
<description>Minor Revision</description>
<bitRange>[23:20]</bitRange>
</field>
<field> <name>MAJOR_REVISION</name>
<description>Major Revision</description>
<bitRange>[27:24]</bitRange>
</field>
<field> <name>CONFIGURATION</name>
<description>CONFIGURATION for SSE-200 r2: 0x2</description>
<bitRange>[31:28]</bitRange>
</field>
</fields>
</register>
<register>
<name>SYS_CONFIG</name>
<description>System Hardware Configuration register</description>
<addressOffset>0x04</addressOffset>
<access>read-only</access>
<fields>
<field> <name>SRAM_NUM_BANK</name>
<description>SRAM Number of Banks</description>
<bitRange>[3:0]</bitRange>
</field>
<field> <name>SRAM_ADDR_WIDTH</name>
<description>SRAM Bank Address Width</description>
<bitRange>[8:4]</bitRange>
</field>
<field> <name>CPU0_HAS_TCM</name>
<description>CPU 0 has Data TCM:</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>No</name>
<description>CPU 0 does not have Data TCM</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Yes</name>
<description>CPU 0 has Data TCM</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CPU1_HAS_TCM</name>
<description>CPU 1 has Data TCM:</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>No</name>
<description>CPU 1 does not have Data TCM</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Yes</name>
<description>CPU 1 has Data TCM</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>HAS_CRYPTO</name>
<description>Whether CryptoCell Included:</description>
<bitRange>[12:12]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>No</name>
<description>CryptoCell Not Included</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Yes</name>
<description>CryptoCell Included</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CPU0_TCM_BANK_NUM</name>
<description>The SRAM Bank that maps CPU0 Data TCM</description>
<bitRange>[19:16]</bitRange>
</field>
<field> <name>CPU1_TCM_BANK_NUM</name>
<description>Number of SRAM banks</description>
<bitRange>[23:20]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>Four</name>
<description>4 SRAM Banks</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>Three</name>
<description>3 SRAM Banks</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>Two</name>
<description>2 SRAM Banks</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>Otherwise</name>
<description>Otherwise</description>
<value>0x0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CPU0_TYPE</name>
<description>CPU 0 Core Type</description>
<bitRange>[27:24]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>Not Exist</name>
<description>Does Not Exist</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CM33</name>
<description>Cortex-M33 Core</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CPU1_TYPE</name>
<description>CPU 1 Core Type</description>
<bitRange>[31:28]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>Not Exist</name>
<description>Does Not Exist</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>CM33</name>
<description>Cortex-M33 Core</description>
<value>0x2</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PIDR4</name>
<description>Peripheral ID 4</description>
<addressOffset>0xFD0</addressOffset>
<access>read-only</access>
<resetValue>0x00000004</resetValue>
</register>
<register>
<name>PIDR0</name>
<description>Peripheral ID 0</description>
<addressOffset>0xFE0</addressOffset>
<access>read-only</access>
<resetValue>0x00000058</resetValue>
</register>
<register>
<name>PIDR1</name>
<description>Peripheral ID 1</description>
<addressOffset>0xFE4</addressOffset>
<access>read-only</access>
<resetValue>0x000000B8</resetValue>
</register>
<register>
<name>PIDR2</name>
<description>Peripheral ID 2</description>
<addressOffset>0xFE8</addressOffset>
<access>read-only</access>
<resetValue>0x0000000B</resetValue>
</register>
<register>
<name>PIDR3</name>
<description>Peripheral ID 3</description>
<addressOffset>0xFEC</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
</register>
<register>
<name>CIDR0</name>
<description>Component ID 0</description>
<addressOffset>0xFF0</addressOffset>
<access>read-only</access>
<resetValue>0x0000000D</resetValue>
</register>
<register>
<name>CIDR1</name>
<description>Component ID 1</description>
<addressOffset>0xFF4</addressOffset>
<access>read-only</access>
<resetValue>0x000000F0</resetValue>
</register>
<register>
<name>CIDR2</name>
<description>Component ID 2</description>
<addressOffset>0xFF8</addressOffset>
<access>read-only</access>
<resetValue>0x00000005</resetValue>
</register>
<register>
<name>CIDR3</name>
<description>Component ID 3</description>
<addressOffset>0xFFC</addressOffset>
<access>read-only</access>
<resetValue>0x000000B1</resetValue>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="SYSINFO"> <name>SYSINFO_Secure</name>
<description>System Information (Secure)</description>
<groupName>SYSINFO (Secure)</groupName>
<baseAddress>0x50020000</baseAddress>
</peripheral>
<peripheral> <name>SystemControl</name>
<version>1.0</version>
<description>System Control</description>
<groupName>SYSCTRL</groupName>
<baseAddress>0x50021000</baseAddress>
<size>32</size>
<access>read-write</access>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register> <name>SECDBGSTAT</name>
<description>Secure Debug Configuration Status</description>
<addressOffset>0x00</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field> <name>DBGEN_I_STATUS</name>
<description>Debug enable value</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>debug enable</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>debug disable</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>DBGEN_SEL_STATUS</name>
<description>Debug enable selector value</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>debug enable selector</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>debug disable selector</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>NIDEN_I_STATUS</name>
<description>Non-invasive debug enable value</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>non-invasive debug enable</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>non-invasive debug disable</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>NIDEN_SEL_STATUS</name>
<description>Non-invasive debug enable selector value</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>non-invasive debug enable selector</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>non-invasive debug disable selector</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SPIDEN_I_STATUS</name>
<description>Secure privilege invasive debug enable value</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Secure privilege invasive debug enable</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Secure privilege invasive debug disable</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SPIDEN_SEL_STATUS</name>
<description>Secure privilege invasive debug enable selector value</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Secure privilege invasive debug enable selector</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Secure privilege invasive debug disable selector</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SPNIDEN_STATUS</name>
<description>Secure privilege non-invasive debug enable value</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Secure privilege non-invasive debug enable</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Secure privilege non-invasive debug disable</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SPNIDEN_SEL_STATUS</name>
<description>Secure privilege non-invasive debug enable selector value</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Secure privilege non-invasive debug enable selector</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Secure privilege non-invasive debug disable selector</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>SECDBGSET</name>
<description>Secure Debug Configuration Set</description>
<addressOffset>0x04</addressOffset>
<access>write-only</access>
<fields>
<field> <name>DBGEN_I_SET</name>
<description>High active debug enable set control</description>
<bitRange>[0:0]</bitRange>
</field>
<field> <name>DBGEN_SEL_SET</name>
<description>Debug enable selector set control</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>debug enable selector set control</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>debug disable selector set control</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>NIDEN_I_SET</name>
<description>Non-invasive debug enable set control</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>non-invasive debug enable set control</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>non-invasive debug disable set control</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>NIDEN_SEL_SET</name>
<description>Non-invasive debug enable selector set control</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>non-invasive debug enable selector set control</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>non-invasive debug disable selector set control</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SPIDEN_I_SET</name>
<description>Secure privilege invasive debug enable set control</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Secure privilege invasive debug enable set control</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Secure privilege invasive debug disable set control</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SPIDEN_SEL_SET</name>
<description>Secure privilege invasive debug enable selector set control</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Secure privilege invasive debug enable selector set control</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Secure privilege invasive debug disable selector set control</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SPNIDEN_I_SET</name>
<description>Secure privilege non-invasive debug enable set control</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Secure privilege non-invasive debug enable set control</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Secure privilege non-invasive debug disable set control</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SPNIDEN_SEL_SET</name>
<description>Secure privilege non-invasive debug enable selector set control</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Secure privilege non-invasive debug enable selector set control</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Secure privilege non-invasive debug disable selector set control</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>SECDBGCLR</name>
<description>Secure Debug Configuration Clear</description>
<addressOffset>0x08</addressOffset>
<access>write-only</access>
<fields>
<field> <name>DBGEN_I_CLR</name>
<description>Debug enable clear control</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>debug enable clear control</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>debug disable clear control</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>DBGEN_SEL_CLR</name>
<description>Debug enable selector clear control</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>debug enable selector clear control</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>debug disable selector clear control</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>NIDEN_I_CLR</name>
<description>Non-invasive debug enable clear control</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>non-invasive debug enable clear control</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>non-invasive debug disable clear control</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>NIDEN_SEL_CLR</name>
<description>Non-invasive debug enable selector clear control</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>non-invasive debug enable selector clear control</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>non-invasive debug disable selector clear control</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SPIDEN_I_CLR</name>
<description>Secure privilege invasive debug enable clear control</description>
<bitRange>[4:4]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Secure privilege invasive debug enable clear control</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Secure privilege invasive debug disable clear control</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SPIDEN_SEL_CLR</name>
<description>Secure privilege invasive debug enable selector clear control</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Secure privilege invasive debug enable selector clear control</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Secure privilege invasive debug disable selector clear control</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SPNIDEN_I_CLR</name>
<description>Secure privilege non-invasive debug enable clear control</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Secure privilege non-invasive debug enable clear control</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Secure privilege non-invasive debug disable clear control</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SPNIDEN_SEL_CLR</name>
<description>Secure privilege non-invasive debug enable selector clear control</description>
<bitRange>[7:7]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Secure privilege non-invasive debug enable selector clear control</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Secure privilege non-invasive debug disable selector clear control</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>SCSECCTRL</name>
<description>System Security Control</description>
<addressOffset>0x0C</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-write</access>
<fields>
<field> <name>CERTDISABLE</name>
<description>Control to disable certification path</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>disable</name>
<description>control to disable certification path</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>enable</name>
<description>control to enable certification path</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CERTREADEN</name>
<description>Control to enable read access on the certification path as
long as CERTDISABLE is also LOW
</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>control to enable read access on the certification path as long as CERTDISABLE is also LOW</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>control to disable read access on the certification path as long as CERTDISABLE is also LOW</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SCSECCFGLOCK</name>
<description>Control to disable writes to security-related control registers in this register block</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>disable</name>
<description>control to disable writes to security-related control registers in this register block</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>enable</name>
<description>control to enable writes to security-related control registers in this register block</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CERTDISABLED</name>
<description>Indicates that the Certification write path has been disabled</description>
<bitRange>[16:16]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>disabled</name>
<description>Certification write path has been disabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>enabled</name>
<description>Certification write path has been enabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CERTREADENABLED</name>
<description>Indicates whether the certification read access is enabled</description>
<bitRange>[17:17]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>certification read access is enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>certification read access is disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>FCLK_DIV</name>
<description>Fast Clock Divider Configuration</description>
<addressOffset>0x10</addressOffset>
<access>read-write</access>
<fields>
<field> <name>FCLKDIV</name>
<description>FCLK from MAINCLK Clock Divider Ratio Request</description>
<bitRange>[4:0]</bitRange>
</field>
<field> <name>FCLKDIV_CUR</name>
<description>Clock Divider Current Value.</description>
<bitRange>[20:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register> <name>SYSCLK_DIV</name>
<description>System Clock Divider Configuration</description>
<addressOffset>0x14</addressOffset>
<access>read-write</access>
<fields>
<field> <name>SYSCLKDIV</name>
<description>SYSCLK from FCLK Clock Divider Ratio Request</description>
<bitRange>[4:0]</bitRange>
</field>
<field> <name>SYSCLKDIV_CUR</name>
<description>Clock Divider Current Value</description>
<bitRange>[20:16]</bitRange>
<access>read-only</access>
</field>
</fields>
</register>
<register> <name>CLOCK_FORCE</name>
<description>Clock Force</description>
<addressOffset>0x18</addressOffset>
<access>read-write</access>
<fields>
<field> <name>MAINCLK_FORCE</name>
<description>Force MAINCLK to run when set to HIGH</description>
<bitRange>[0:0]</bitRange>
</field>
<field> <name>SYSSYSCLK_FORCE</name>
<description>Force Base element Local SYSCLK to run when set to HIGH</description>
<bitRange>[1:1]</bitRange>
</field>
<field> <name>SYSFCLK_FORCE</name>
<description>Force Base element Local FCLK to run when set to HIGH</description>
<bitRange>[2:2]</bitRange>
</field>
<field> <name>SRAMSYSCLK_FORCE</name>
<description>Force SRAM Local SYSCLK to run when set to HIGH</description>
<bitRange>[3:3]</bitRange>
</field>
<field> <name>SRAMFCLK_FORCE</name>
<description>Force SRAM Local FCLK to run when set to HIGH</description>
<bitRange>[4:4]</bitRange>
</field>
<field> <name>CPUSYSCLK_FORCE</name>
<description>Force all CPU SYSCLK to run when set to HIGH</description>
<bitRange>[5:5]</bitRange>
</field>
<field> <name>CPUFCLK_FORCE</name>
<description>Force all CPU FCLK to run when set to HIGH</description>
<bitRange>[6:6]</bitRange>
</field>
<field> <name>CRYPTOSYSCLK_FORCE</name>
<description>Force all CryptoCell clocks to run when set to HIGH</description>
<bitRange>[7:7]</bitRange>
</field>
<field> <name>FCLKHINTGATE_ENABLE</name>
<description>Enable FCLK gating by HINTSYSCLKEN when CPU 1 is OFF</description>
<bitRange>[8:8]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable FCLK gating by HINTSYSCLKEN when CPU 1 is OFF</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>latency</name>
<description>improve SRAM3 access latency at the cost of increased power consumption</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>RESET_SYNDROME</name>
<description>Reset Syndrome</description>
<addressOffset>0x100</addressOffset>
<access>read-write</access>
<resetValue>0x00000001</resetValue>
<fields>
<field> <name>PoR</name>
<description>Power-on</description>
<bitRange>[0:0]</bitRange>
<access>write-only</access>
</field>
<field> <name>NSWD</name>
<description>Non-secure watchdog</description>
<bitRange>[1:1]</bitRange>
<access>write-only</access>
</field>
<field> <name>SWD</name>
<description>Secure watchdog</description>
<bitRange>[2:2]</bitRange>
<access>write-only</access>
</field>
<field> <name>S32KWD</name>
<description>Watchdog on the S32KCLK clock</description>
<bitRange>[3:3]</bitRange>
<access>write-only</access>
</field>
<field> <name>SYSRSTREQ0</name>
<description>CPU 0 System Reset Request</description>
<bitRange>[4:4]</bitRange>
<access>write-only</access>
</field>
<field> <name>SYSRSTREQ1</name>
<description>CPU 1 System Reset Request</description>
<bitRange>[5:5]</bitRange>
<access>write-only</access>
</field>
<field> <name>LOCKUP0</name>
<description>CPU 0 Lock-up Status</description>
<bitRange>[6:6]</bitRange>
<access>write-only</access>
</field>
<field> <name>LOCKUP1</name>
<description>CPU 1 Lock-up Status</description>
<bitRange>[7:7]</bitRange>
<access>write-only</access>
</field>
<field> <name>RESETREQ</name>
<description>External Reset Request</description>
<bitRange>[8:8]</bitRange>
<access>write-only</access>
</field>
<field> <name>SWRESETREQ</name>
<description>Software Reset Request</description>
<bitRange>[9:9]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register> <name>RESET_MASK</name>
<description>Reset Mask</description>
<addressOffset>0x104</addressOffset>
<access>read-write</access>
<resetValue>0x00000030</resetValue>
<fields>
<field> <name>NSWD_EN</name>
<description>Enable NON-SECURE WATCHDOG Reset</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>Enable NON-SECURE WATCHDOG Reset</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>Disabled NON-SECURE WATCHDOG Reset</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SYSRSTREQ0_EN</name>
<description>Enable Merging CPU 0 System Reset Request</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>Enable Merging CPU 0 System Reset Request</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>Disabled Merging CPU 0 System Reset Request</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SYSRSTREQ1_EN</name>
<description>Enable Merging CPU 0 System Reset Request</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>Enable Merging CPU 1 System Reset Request</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>Disabled Merging CPU 1 System Reset Request</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>SWRESET</name>
<description>Software Reset</description>
<addressOffset>0x108</addressOffset>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<fields>
<field> <name>SWRESETREQ</name>
<description>High Active Software Reset Request</description>
<bitRange>[9:9]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register> <name>GRETREG</name>
<description>General Purpose Retention</description>
<addressOffset>0x10C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field> <name>GRETREG</name>
<description>General Purpose Retention Register</description>
<bitRange>[15:0]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register> <name>INITSVRTOR0</name>
<description>Initial Secure Reset Vector Register For CPU 0</description>
<addressOffset>0x110</addressOffset>
<access>read-write</access>
<fields>
<field> <name>INITSVTOR0</name>
<description>Default Secure Vector table offset at reset for CPU 0</description>
<bitRange>[31:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register> <name>INITSVRTOR1</name>
<description>Initial Secure Reset Vector Register For CPU 1</description>
<addressOffset>0x114</addressOffset>
<access>read-write</access>
<fields>
<field> <name>INITSVTOR1</name>
<description>Default Secure Vector table offset at reset for CPU 1</description>
<bitRange>[31:7]</bitRange>
<access>read-write</access>
</field>
</fields>
</register>
<register> <name>CPUWAIT</name>
<description>CPU Boot wait control after reset</description>
<addressOffset>0x118</addressOffset>
<access>read-write</access>
<fields>
<field> <name>CPU0WAIT</name>
<description>CPU 0 waits at boot and whether CPU1 powers up</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>normally or power-up</name>
<description>CPU0 boot normally. From Power ON reset, nSRST reset or Watchdog Reset, CPU 1 powers up</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>wait or no power-up</name>
<description>CPU0 wait. From Power ON reset, nSRST reset or Watchdog Reset, CPU 1 do not power up</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CPU1WAIT</name>
<description>CPU 1 waits at boot and whether CPU0 powers up</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>normally or power-up</name>
<description>CPU1 boot normally. From Power ON reset, nSRST reset or Watchdog Reset, CPU 0 powers up</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>wait or no power-up</name>
<description>CPU1 wait. From Power ON reset, nSRST reset or Watchdog Reset, CPU 0 do not power up</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>NMI_ENABLE</name>
<description>NMI Enable Register</description>
<addressOffset>0x11C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field> <name>CPU0_INTNMI_ENABLE</name>
<description>CPU0 Internally Sourced NMI Enable</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>CPU0 Internally Sourced NMI Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>CPU0 Internally Sourced NMI Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CPU1_INTNMI_ENABLE</name>
<description>CPU1 Internally Sourced NMI Enable</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>CPU1 Internally Sourced NMI Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>CPU1 Internally Sourced NMI Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CPU0_EXPNMI_ENABLE</name>
<description>CPU0 Externally Sourced NMI Enable</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>CPU0 Externally Sourced NMI Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>CPU0 Externally Sourced NMI Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CPU1_EXPNMI_ENABLE</name>
<description>CPU1 Externally Sourced NMI Enable</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>CPU1 Externally Sourced NMI Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>CPU1 Externally Sourced NMI Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>WICCTRL</name>
<description>WIC request and acknowledge handshake</description>
<addressOffset>0x120</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field> <name>CPU0WICEN_STATUS</name>
<description>CPU 0 WIC Enable Request Status</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>CPU 0 WIC request enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>CPU 0 WIC request disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CPU1WICEN_STATUS</name>
<description>CPU 1 WIC Enable Request Status</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>CPU 1 WIC request enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>CPU 1 WIC request disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CPU0WICEN_SET</name>
<description>High Active CPU 0 WIC Enable Request Set</description>
<bitRange>[4:4]</bitRange>
<access>write-only</access>
</field>
<field> <name>CPU1WICEN_SET</name>
<description>High Active CPU 1 WIC Enable Request Set</description>
<bitRange>[5:5]</bitRange>
<access>write-only</access>
</field>
<field> <name>CPU0WICEN_CLR</name>
<description>High Active CPU 0 WIC Enable Request Clear</description>
<bitRange>[8:8]</bitRange>
<access>write-only</access>
</field>
<field> <name>CPU1WICEN_CLR</name>
<description>High Active CPU 1 WIC Enable Request Clear</description>
<bitRange>[9:9]</bitRange>
<access>write-only</access>
</field>
<field> <name>CPU0WICRDY</name>
<description>CPU 0 WIC Enable Acknowledge</description>
<bitRange>[16:16]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>CPU 0 WIC Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>CPU 0 WIC Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CPU1WICRDY</name>
<description>CPU 1 WIC Enable Acknowledge</description>
<bitRange>[17:17]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>enabled</name>
<description>CPU 1 WIC Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>CPU 1 WIC Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>EWCTRL</name>
<description>External Wakeup Control</description>
<addressOffset>0x124</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field> <name>EWC0EN_STATUS</name>
<description>External Wakeup Controller 0 Enable</description>
<bitRange>[0:0]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>External Wakeup Controller 0 Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>External Wakeup Controller 0 Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>EWC1EN_STATUS</name>
<description>External Wakeup Controller 1 Enable</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>External Wakeup Controller 1 Enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>External Wakeup Controller 1 Disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>EWC0EN_SET</name>
<description>EHigh Active External Wakeup Controller 0 Set</description>
<bitRange>[4:4]</bitRange>
<access>write-only</access>
</field>
<field> <name>EWC1EN_SET</name>
<description>High Active External Wakeup Controller 1 Set</description>
<bitRange>[5:5]</bitRange>
<access>write-only</access>
</field>
<field> <name>EWC0EN_CLR</name>
<description>High Active External Wakeup Controller 0 Clear</description>
<bitRange>[8:8]</bitRange>
<access>write-only</access>
</field>
<field> <name>EWC1EN_CLR</name>
<description>High Active External Wakeup Controller 1 Clear</description>
<bitRange>[9:9]</bitRange>
<access>write-only</access>
</field>
</fields>
</register>
<register> <name>PDCM_PD_SYS_SENSE</name>
<description>External Wakeup Control</description>
<addressOffset>0x200</addressOffset>
<access>read-write</access>
<resetValue>0x0000007F</resetValue>
<fields>
<field> <name>S_PD_SYS_ON</name>
<description>Enable PD_SYS ON Sensitivity</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Keep PD_SYS awake after powered ON</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_CPU0CORE_ON</name>
<description>Tied to HIGH</description>
<bitRange>[1:1]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>high</name>
<description>PD_SYS always tries to stay ON if PD_CPU0CORE is ON</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_CPU1CORE_ON</name>
<description>Tied to HIGH</description>
<bitRange>[2:2]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>high</name>
<description>PD_SYS always tries to stay ON if PD_CPU1CORE is ON</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM0_ON</name>
<description>Tied to HIGH</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>high</name>
<description>PD_SYS always tries to keep ON if SRAM0 power domain is ON</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM1_ON</name>
<description>Tied to HIGH</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>high</name>
<description>PD_SYS always tries to keep ON if SRAM1 power domain is ON</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM2_ON</name>
<description>Tied to HIGH</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>high</name>
<description>PD_SYS always tries to keep ON if SRAM2 power domain is ON</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM3_ON</name>
<description>Tied to HIGH</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>high</name>
<description>PD_SYS always tries to keep ON if SRAM3 power domain is ON</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_CRYPTO_ON</name>
<description>Tied to HIGH</description>
<bitRange>[12:12]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>high</name>
<description>PD_SYS always tries to keep ON if S_PD_CRYPTO_ON is ON</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP0_IN</name>
<description>Enable PDEXPIN[0] signal Sensitivity</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[0] signal Sensitivity.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>Disable PDEXPIN[0] signal Sensitivity.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP1_IN</name>
<description>Enable PDEXPIN[1] signal Sensitivity</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[1] signal Sensitivity.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>Disable PDEXPIN[1] signal Sensitivity.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP2_IN</name>
<description>Enable PDEXPIN[2] signal Sensitivity</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[2] signal Sensitivity.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>Disable PDEXPIN[2] signal Sensitivity.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP3_IN</name>
<description>Enable PDEXPIN[3] signal Sensitivity</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[3] signal Sensitivity.</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disabled</name>
<description>Disable PDEXPIN[3] signal Sensitivity.</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>PDCM_PD_SRAM0_SENSE</name>
<description>Power Control Depedendency Matrix PD_SRAM0 Power Domain Sensitivity</description>
<addressOffset>0x20C</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field> <name>S_PD_SYS_ON</name>
<description>Enable sensitivity to PD_SYS</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable sensitivity to PD_SYS</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable sensitivity to PD_SYS</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_CPU0CORE_ON</name>
<description>Enable sensitivity to PD_CPU0CORE</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable sensitivity to PD_CPU0CORE</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable sensitivity to PD_CPU0CORE</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_CPU1CORE_ON</name>
<description>Enable sensitivity to PD_CPU1CORE</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable sensitivity to PD_CPU1CORE</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable sensitivity to PD_CPU1CORE</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM0_ON</name>
<description>Enable sensitivity to PD_SRAM0</description>
<bitRange>[3:3]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable sensitivity to PD_SRAM0</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable sensitivity to PD_SRAM0</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM1_ON</name>
<description>Tied LOW</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Low</name>
<description>Ignores PD_SRAM1 state</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM2_ON</name>
<description>Tied LOW</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Low</name>
<description>Ignores PD_SRAM2 state</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM3_ON</name>
<description>Tied LOW</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Low</name>
<description>Ignores PD_SRAM3 state</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_CRYPTO_ON</name>
<description>Tied LOW</description>
<bitRange>[12:12]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Low</name>
<description>Ignores PD_CRYPTO</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP0_IN</name>
<description>Enable PDEXPIN[0] signal Sensitivity</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[0] signal Sensitivity</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable PDEXPIN[0] signal Sensitivity</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP1_IN</name>
<description>Enable PDEXPIN[1] signal Sensitivity</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[1] signal Sensitivity</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable PDEXPIN[1] signal Sensitivity</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP2_IN</name>
<description>Enable PDEXPIN[2] signal Sensitivity</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[2] signal Sensitivity</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable PDEXPIN[2] signal Sensitivity</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP3_IN</name>
<description>Enable PDEXPIN[3] signal Sensitivity</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[3] signal Sensitivity</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable PDEXPIN[3] signal Sensitivity</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>PDCM_PD_SRAM1_SENSE</name>
<description>Power Control Depedendency Matrix PD_SRAM1 Power Domain Sensitivity</description>
<addressOffset>0x210</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field> <name>S_PD_SYS_ON</name>
<description>Enable sensitivity to PD_SYS</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable sensitivity to PD_SYS</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable sensitivity to PD_SYS</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_CPU0CORE_ON</name>
<description>Enable sensitivity to PD_CPU0CORE</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable sensitivity to PD_CPU0CORE</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable sensitivity to PD_CPU0CORE</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_CPU1CORE_ON</name>
<description>Enable sensitivity to PD_CPU1CORE</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable sensitivity to PD_CPU1CORE</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable sensitivity to PD_CPU1CORE</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM0_ON</name>
<description>Tied LOW</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Low</name>
<description>Ignores PD_SRAM0 state</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM1_ON</name>
<description>Enable sensitivity to PD_SRAM1</description>
<bitRange>[4:4]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable sensitivity to PD_SRAM1</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable sensitivity to PD_SRAM1</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM2_ON</name>
<description>Tied LOW</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Low</name>
<description>Ignores PD_SRAM2 state</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM3_ON</name>
<description>Tied LOW</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Low</name>
<description>Ignores PD_SRAM3 state</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_CRYPTO_ON</name>
<description>Tied LOW</description>
<bitRange>[12:12]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Low</name>
<description>Ignores PD_CRYPTO</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP0_IN</name>
<description>Enable PDEXPIN[0] signal Sensitivity</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[0] signal Sensitivity</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable PDEXPIN[0] signal Sensitivity</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP1_IN</name>
<description>Enable PDEXPIN[1] signal Sensitivity</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[1] signal Sensitivity</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable PDEXPIN[1] signal Sensitivity</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP2_IN</name>
<description>Enable PDEXPIN[2] signal Sensitivity</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[2] signal Sensitivity</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable PDEXPIN[2] signal Sensitivity</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP3_IN</name>
<description>Enable PDEXPIN[3] signal Sensitivity</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[3] signal Sensitivity</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable PDEXPIN[3] signal Sensitivity</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>PDCM_PD_SRAM2_SENSE</name>
<description>Power Control Depedendency Matrix PD_SRAM2 Power Domain Sensitivity</description>
<addressOffset>0x214</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field> <name>S_PD_SYS_ON</name>
<description>Enable sensitivity to PD_SYS</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable sensitivity to PD_SYS</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable sensitivity to PD_SYS</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_CPU0CORE_ON</name>
<description>Enable sensitivity to PD_CPU0CORE</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable sensitivity to PD_CPU0CORE</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable sensitivity to PD_CPU0CORE</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_CPU1CORE_ON</name>
<description>Enable sensitivity to PD_CPU1CORE</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable sensitivity to PD_CPU1CORE</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable sensitivity to PD_CPU1CORE</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM0_ON</name>
<description>Tied LOW</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Low</name>
<description>Ignores PD_SRAM0 state</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM1_ON</name>
<description>Tied LOW</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Low</name>
<description>Ignores PD_SRAM1 state</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM2_ON</name>
<description>Enable sensitivity to PD_SRAM2</description>
<bitRange>[5:5]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable sensitivity to PD_SRAM2</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable sensitivity to PD_SRAM2</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM3_ON</name>
<description>Tied LOW</description>
<bitRange>[6:6]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Low</name>
<description>Ignores PD_SRAM3 state</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_CRYPTO_ON</name>
<description>Tied LOW</description>
<bitRange>[12:12]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Low</name>
<description>Ignores PD_CRYPTO</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP0_IN</name>
<description>Enable PDEXPIN[0] signal Sensitivity</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[0] signal Sensitivity</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable PDEXPIN[0] signal Sensitivity</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP1_IN</name>
<description>Enable PDEXPIN[1] signal Sensitivity</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[1] signal Sensitivity</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable PDEXPIN[1] signal Sensitivity</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP2_IN</name>
<description>Enable PDEXPIN[2] signal Sensitivity</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[2] signal Sensitivity</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable PDEXPIN[2] signal Sensitivity</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP3_IN</name>
<description>Enable PDEXPIN[3] signal Sensitivity</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[3] signal Sensitivity</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable PDEXPIN[3] signal Sensitivity</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>PDCM_PD_SRAM3_SENSE</name>
<description>Power Control Depedendency Matrix PD_SRAM3 Power Domain Sensitivity</description>
<addressOffset>0x218</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field> <name>S_PD_SYS_ON</name>
<description>Enable sensitivity to PD_SYS</description>
<bitRange>[0:0]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable sensitivity to PD_SYS</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable sensitivity to PD_SYS</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_CPU0CORE_ON</name>
<description>Enable sensitivity to PD_CPU0CORE</description>
<bitRange>[1:1]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable sensitivity to PD_CPU0CORE</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable sensitivity to PD_CPU0CORE</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_CPU1CORE_ON</name>
<description>Enable sensitivity to PD_CPU1CORE</description>
<bitRange>[2:2]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable sensitivity to PD_CPU1CORE</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable sensitivity to PD_CPU1CORE</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM0_ON</name>
<description>Tied LOW</description>
<bitRange>[3:3]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Low</name>
<description>Ignores PD_SRAM0 state</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM1_ON</name>
<description>Tied LOW</description>
<bitRange>[4:4]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Low</name>
<description>Ignores PD_SRAM1 state</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM2_ON</name>
<description>Tied LOW</description>
<bitRange>[5:5]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Low</name>
<description>Ignores PD_SRAM2 state</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_SRAM3_ON</name>
<description>Enable sensitivity to PD_SRAM3</description>
<bitRange>[6:6]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable sensitivity to PD_SRAM3</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable sensitivity to PD_SRAM3</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_CRYPTO_ON</name>
<description>Tied LOW</description>
<bitRange>[12:12]</bitRange>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Low</name>
<description>Ignores PD_CRYPTO</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP0_IN</name>
<description>Enable PDEXPIN[0] signal Sensitivity</description>
<bitRange>[16:16]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[0] signal Sensitivity</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable PDEXPIN[0] signal Sensitivity</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP1_IN</name>
<description>Enable PDEXPIN[1] signal Sensitivity</description>
<bitRange>[17:17]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[1] signal Sensitivity</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable PDEXPIN[1] signal Sensitivity</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP2_IN</name>
<description>Enable PDEXPIN[2] signal Sensitivity</description>
<bitRange>[18:18]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[2] signal Sensitivity</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable PDEXPIN[2] signal Sensitivity</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>S_PD_EXP3_IN</name>
<description>Enable PDEXPIN[3] signal Sensitivity</description>
<bitRange>[19:19]</bitRange>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>enable</name>
<description>Enable PDEXPIN[3] signal Sensitivity</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>disable</name>
<description>Disable PDEXPIN[3] signal Sensitivity</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>PIDR4</name>
<description>Peripheral ID 4</description>
<addressOffset>0xFD0</addressOffset>
<access>read-only</access>
<resetValue>0x00000004</resetValue>
</register>
<register> <name>PIDR0</name>
<description>Peripheral ID 0</description>
<addressOffset>0xFE0</addressOffset>
<access>read-only</access>
<resetValue>0x00000054</resetValue>
</register>
<register> <name>PIDR1</name>
<description>Peripheral ID 1</description>
<addressOffset>0xFE4</addressOffset>
<access>read-only</access>
<resetValue>0x000000B8</resetValue>
</register>
<register> <name>PIDR2</name>
<description>Peripheral ID 2</description>
<addressOffset>0xFE8</addressOffset>
<access>read-only</access>
<resetValue>0x0000001B</resetValue>
</register>
<register> <name>PIDR3</name>
<description>Peripheral ID 3</description>
<addressOffset>0xFEC</addressOffset>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
</register>
<register> <name>CIDR0</name>
<description>Component ID 0</description>
<addressOffset>0xFF0</addressOffset>
<access>read-only</access>
<resetValue>0x0000000D</resetValue>
</register>
<register> <name>CIDR1</name>
<description>Component ID 1</description>
<addressOffset>0xFF4</addressOffset>
<access>read-only</access>
<resetValue>0x000000F0</resetValue>
</register>
<register> <name>CIDR2</name>
<description>Component ID 2</description>
<addressOffset>0xFF8</addressOffset>
<access>read-only</access>
<resetValue>0x00000005</resetValue>
</register>
<register> <name>CIDR3</name>
<description>Component ID 3</description>
<addressOffset>0xFFC</addressOffset>
<access>read-only</access>
<resetValue>0x000000B1</resetValue>
</register>
</registers>
</peripheral>
<peripheral> <name>SAU</name>
<version>1.0</version>
<description>Security Attribution Unit</description>
<groupName>SAU</groupName>
<baseAddress>0xE000EDD0</baseAddress>
<size>32</size>
<access>read-write</access>
<addressBlock>
<offset>0</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CTRL</name>
<description>Control Register</description>
<addressOffset>0x00</addressOffset>
<fields>
<field>
<name>ENABLE</name>
<description>Enable</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>SAU is disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>SAU is enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ALLNS</name>
<description>Security attribution if SAU disabled</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>Secure</name>
<description>Memory is marked as secure</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Non_Secure</name>
<description>Memory is marked as non-secure</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>TYPE</name>
<description>Type Register</description>
<addressOffset>0x04</addressOffset>
<access>read-only</access>
<fields>
<field>
<name>SREGION</name>
<description>Number of implemented SAU regions</description>
<bitRange>[7:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>RNR</name>
<description>Region Number Register</description>
<addressOffset>0x08</addressOffset>
<fields>
<field>
<name>REGION</name>
<description>Currently selected SAU region</description>
<bitRange>[7:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>SAU_Region_0</name>
<description>Select SAU Region 0</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SAU_Region_1</name>
<description>Select SAU Region 1</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>SAU_Region_2</name>
<description>Select SAU Region 2</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>SAU_Region_3</name>
<description>Select SAU Region 3</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>RBAR</name>
<description>Region Base Address Register</description>
<addressOffset>0x0C</addressOffset>
<fields>
<field>
<name>BADDR</name>
<description>Base Address</description>
<bitRange>[31:5]</bitRange>
</field>
</fields>
</register>
<register>
<name>RLAR</name>
<description>Region Limit Address Register</description>
<addressOffset>0x10</addressOffset>
<fields>
<field>
<name>LADDR</name>
<description>Limit Address</description>
<bitRange>[31:5]</bitRange>
</field>
<field>
<name>NSC</name>
<description>Non-Secure Callable</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>ENABLE</name>
<description>SAU Region enabled</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>SFSR</name>
<description>Secure Fault Status Register</description>
<addressOffset>0x14</addressOffset>
<fields>
<field>
<name>LSERR</name>
<description>Lazy state error flag</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>SFARVALID</name>
<description>Secure fault address valid</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>LSPERR</name>
<description>Lazy state preservation error flag</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>INVTRAN</name>
<description>Invalid transition flag</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>AUVIOL</name>
<description>Attribution unit violation flag</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>INVER</name>
<description>Invalid exception return flag</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>INVIS</name>
<description>Invalid integrity signature flag</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>INVEP</name>
<description>Invalid entry pointd</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral> <name>TIMER0</name>
<version>1.0</version>
<description>Timer 0</description>
<groupName>Timer</groupName>
<baseAddress>0x40000000</baseAddress>
<size>32</size>
<access>read-write</access>
<addressBlock>
<offset>0</offset>
<size>0x10</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TIMER0</name>
<description>Timer 0</description>
<value>3</value>
</interrupt>
<registers>
<register> <name>CTRL</name>
<description>Control Register</description>
<addressOffset>0x000</addressOffset>
<fields>
<field> <name>ENABLE</name>
<description>Enable</description>
<bitRange>[0:0]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>Timer is disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Timer is enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>EXTIN</name>
<description>External Input as Enable</description>
<bitRange>[1:1]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>External Input as Enable is disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>External Input as Enable is enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>EXTCLK</name>
<description>External Clock Enable</description>
<bitRange>[2:2]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>External Clock is disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>External Clock is enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>INTEN</name>
<description>Interrupt Enable</description>
<bitRange>[3:3]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>Interrupt is disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Interrupt is enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>VALUE</name>
<description>Current Timer Counter Value</description>
<addressOffset>0x004</addressOffset>
</register>
<register> <name>RELOAD</name>
<description>Counter Reload Value</description>
<addressOffset>0x008</addressOffset>
</register>
<register> <name>INTSTATUS</name>
<description>Timer Interrupt status register</description>
<addressOffset>0x00C</addressOffset>
<access>read-only</access>
</register>
<register> <name>INTCLEAR</name>
<description>Timer Interrupt clear register</description>
<alternateRegister>INTSTATUS</alternateRegister>
<addressOffset>0x00C</addressOffset>
<access>write-only</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</register>
</registers>
</peripheral>
<peripheral> <name>DUALTIMER</name>
<version>1.0</version>
<description>Dual Timer</description>
<groupName>Timer</groupName>
<baseAddress>0x40002000</baseAddress>
<size>32</size>
<access>read-write</access>
<addressBlock>
<offset>0</offset>
<size>0x3C</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>DUALTIMER</name>
<description>Dual Timer</description>
<value>5</value>
</interrupt>
<registers>
<register> <name>TIMER1LOAD</name>
<description>Timer 1 Load Register</description>
<addressOffset>0x000</addressOffset>
<resetValue>0x00000000</resetValue>
</register>
<register> <name>TIMER1VALUE</name>
<description>Timer 1 Value Register</description>
<addressOffset>0x004</addressOffset>
<resetValue>0xFFFFFFFF</resetValue>
<access>read-only</access>
</register>
<register> <name>TIMER1CONTROL</name>
<description>Timer 1 Control Register</description>
<addressOffset>0x008</addressOffset>
<resetValue>0x20</resetValue>
<fields>
<field> <name>OneShotCount</name>
<description>Selects one-shot or wrapping counter mode.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Wrapping</name>
<description>Wrapping counter mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OneShot</name>
<description>One-shot counter mode</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>TimerSize</name>
<description>Selects 16-bit or 32- bit counter operation.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>16-bit</name>
<description>16-bit counter mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>32-bit</name>
<description>32-bit counter mode</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>TimerPre</name>
<description>Timer prescale bits.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>divided by 1</name>
<description>clock is divided by 1</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>divided by 16</name>
<description>clock is divided by 16</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>divided by 256</name>
<description>clock is divided by 256</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>InterruptEnable</name>
<description>Interrupt Enable bit.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>Interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Interrupt is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>TimerMode</name>
<description>Timer Mode bit.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Free-Running</name>
<description>Free-Running timer mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Periodic</name>
<description>Periodic timer mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>TimerEnable</name>
<description>Timer Enable Enable bit.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>Timer is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Timer is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>TIMER1INTCLR</name>
<description>Timer 1 Interrupt Clear Register</description>
<addressOffset>0x00C</addressOffset>
<resetValue>0x00000000</resetValue>
<access>write-only</access>
<fields>
<field> <name>INT</name>
<description>Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
</fields>
</register>
<register> <name>TIMER1RIS</name>
<description>Timer 1 Raw Interrupt Status Register</description>
<addressOffset>0x010</addressOffset>
<resetValue>0x0</resetValue>
<access>read-only</access>
<fields>
<field> <name>RIS</name>
<description>Raw Timer Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register> <name>TIMER1MIS</name>
<description>Timer 1 Mask Interrupt Status Register</description>
<addressOffset>0x014</addressOffset>
<resetValue>0x0</resetValue>
<access>read-only</access>
<fields>
<field> <name>MIS</name>
<description>Masked Timer Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register> <name>TIMER1BGLOAD</name>
<description>Timer 1 Background Load Register</description>
<addressOffset>0x018</addressOffset>
<resetValue>0x00000000</resetValue>
</register>
<register> <name>TIMER2LOAD</name>
<description>Timer 2 Load Register</description>
<addressOffset>0x020</addressOffset>
<resetValue>0x00000000</resetValue>
</register>
<register> <name>TIMER2VALUE</name>
<description>Timer 2 Value Register</description>
<addressOffset>0x024</addressOffset>
<resetValue>0xFFFFFFFF</resetValue>
<access>read-only</access>
</register>
<register> <name>TIMER2CONTROL</name>
<description>Timer 2 Control Register</description>
<addressOffset>0x028</addressOffset>
<resetValue>0x20</resetValue>
<fields>
<field> <name>OneShotCount</name>
<description>Selects one-shot or wrapping counter mode.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Wrapping</name>
<description>Wrapping counter mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>OneShot</name>
<description>One-shot counter mode</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>TimerSize</name>
<description>Selects 16-bit or 32- bit counter operation.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>16-bit</name>
<description>16-bit counter mode</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>32-bit</name>
<description>32-bit counter mode</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>TimerPre</name>
<description>Timer prescale bits.</description>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>divided by 1</name>
<description>clock is divided by 1</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>divided by 16</name>
<description>clock is divided by 16</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>divided by 256</name>
<description>clock is divided by 256</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>InterruptEnable</name>
<description>Interrupt Enable bit.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>Interrupt is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Interrupt is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>TimerMode</name>
<description>Timer Mode bit.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Free-Running</name>
<description>Free-Running timer mode.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Periodic</name>
<description>Periodic timer mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>TimerEnable</name>
<description>Timer Enable Enable bit.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>Timer is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Timer is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>TIMER2INTCLR</name>
<description>Timer 2 Interrupt Clear Register</description>
<addressOffset>0x02C</addressOffset>
<resetValue>0x00000000</resetValue>
<access>write-only</access>
<fields>
<field>
<name>INT</name>
<description>Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
</fields>
</register>
<register> <name>TIMER2RIS</name>
<description>Timer 2 Raw Interrupt Status Register</description>
<addressOffset>0x030</addressOffset>
<resetValue>0x0</resetValue>
<access>read-only</access>
<fields>
<field> <name>RIS</name>
<description>Raw Timer Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register> <name>TIMER2MIS</name>
<description>Timer 2 Mask Interrupt Status Register</description>
<addressOffset>0x034</addressOffset>
<resetValue>0x0</resetValue>
<access>read-only</access>
<fields>
<field> <name>MIS</name>
<description>Masked Timer Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register> <name>TIMER2BGLOAD</name>
<description>Timer 2 Background Load Register</description>
<addressOffset>0x038</addressOffset>
<resetValue>0x00000000</resetValue>
</register>
</registers>
</peripheral>
<peripheral> <name>GPTIMER</name>
<version>1.0</version>
<description>General-Purpose Timer</description>
<groupName>Timer</groupName>
<baseAddress>0x4010C000</baseAddress>
<size>32</size>
<access>read-write</access>
<addressBlock>
<offset>0</offset>
<size>0x20</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>GPTIMERINTR</name>
<description>General-Purpose Timer interrupt</description>
<value>33</value>
<name>GPTIMERINT0</name>
<description>General-Purpose Timer (Comparator 0)</description>
<value>73</value>
<name>GPTIMERINT1</name>
<description>General-Purpose Timer (Comparator 1)</description>
<value>72</value>
</interrupt>
<registers>
<register>
<name>GPTRESET</name>
<description>Control Reset Register</description>
<addressOffset>0x0000</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-only</access>
<fields>
<field>
<name>GPTRESET</name>
<description>CPU0 interrupt status</description>
<bitRange>[1:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>GPTINTM</name>
<description>Masked interrupt status register</description>
<addressOffset>0x0004</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-write</access>
<fields>
<field>
<name>GPTINTM</name>
<description>Current masked status of the interrupt</description>
<bitRange>[1:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>GPTINTC</name>
<description>Interrupt clear register</description>
<addressOffset>0x0008</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-write</access>
<fields>
<field>
<name>GPTINTC</name>
<description>Writing 0b1 disables the ALARM[n] interrupt</description>
<bitRange>[1:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>GPTALARM0</name>
<description>ALARM0 data value register</description>
<addressOffset>0x0010</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-write</access>
<fields>
<field>
<name> GPTALARM0_DATA</name>
<description>Value that triggers the ALARM0 interrupt when the counter reaches that value</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>GPTALARM1</name>
<description>ALARM1 data value register</description>
<addressOffset>0x0014</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-write</access>
<fields>
<field>
<name> GPTALARM1_DATA</name>
<description>Value that triggers the ALARM1 interrupt when the counter reaches that value</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>GPTINTR</name>
<description>Raw interrupt status register</description>
<addressOffset>0x0018</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-only</access>
<fields>
<field>
<name>GPTINTR</name>
<description>Raw interrupt state, before masking of GPTINTR interrupt</description>
<bitRange>[2:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>GPTCOUNTER</name>
<description>Counter data value register</description>
<addressOffset>0x001C</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-only</access>
<fields>
<field>
<name>GPTCOUNTER</name>
<description>Current value of 32-bit Timer Counter</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="TIMER0"> <name>TIMER0_Secure</name>
<description>Timer 0 (Secure)</description>
<groupName>Timer (Secure)</groupName>
<baseAddress>0x50000000</baseAddress>
</peripheral>
<peripheral derivedFrom="DUALTIMER"> <name>DUALTIMER_Secure</name>
<description>Dual Timer (Secure)</description>
<groupName>Timer (Secure)</groupName>
<baseAddress>0x50002000</baseAddress>
</peripheral>
<peripheral derivedFrom="GPTIMER"> <name>GPTIMER_Secure</name>
<description>General-Purpose Timer (Secure)</description>
<groupName>Timer (Secure)</groupName>
<baseAddress>0x5010C000</baseAddress>
</peripheral>
<peripheral> <name>GPIO0</name>
<version>1.0</version>
<description>General-purpose I/O 0</description>
<groupName>GPIO</groupName>
<baseAddress>0x41000000</baseAddress>
<size>32</size>
<access>read-write</access>
<addressBlock>
<offset>0</offset>
<size>0x3C</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>GPIO0</name>
<description>GPIO 0 combined</description>
<value>68</value>
</interrupt>
<registers>
<register> <name>DATA</name>
<description>Data Register</description>
<addressOffset>0x000</addressOffset>
</register>
<register> <name>DATAOUT</name>
<description>Data Output Register</description>
<addressOffset>0x004</addressOffset>
</register>
<register> <name>OUTENSET</name>
<description>Ouptut enable set Register</description>
<addressOffset>0x010</addressOffset>
</register>
<register> <name>OUTENCLR</name>
<description>Ouptut enable clear Register</description>
<addressOffset>0x014</addressOffset>
</register>
<register> <name>ALTFUNCSET</name>
<description>Alternate function set Register</description>
<addressOffset>0x018</addressOffset>
</register>
<register> <name>ALTFUNCCLR</name>
<description>Alternate function clear Register</description>
<addressOffset>0x01C</addressOffset>
</register>
<register> <name>INTENSET</name>
<description>Interrupt enable set Register</description>
<addressOffset>0x020</addressOffset>
</register>
<register> <name>INTENCLR</name>
<description>Interrupt enable clear Register</description>
<addressOffset>0x024</addressOffset>
</register>
<register> <name>INTTYPESET</name>
<description>Interrupt type set Register</description>
<addressOffset>0x028</addressOffset>
</register>
<register> <name>INTTYPECLR</name>
<description>Interrupt type clear Register</description>
<addressOffset>0x02C</addressOffset>
</register>
<register> <name>INTPOLSET</name>
<description>Polarity-level, edge interrupt configuration set Register</description>
<addressOffset>0x030</addressOffset>
</register>
<register> <name>INTPOLCLR</name>
<description>Polarity-level, edge interrupt configuration clear Register</description>
<addressOffset>0x034</addressOffset>
</register>
<register> <name>INTSTATUS</name>
<description>Interrupt Status Register</description>
<addressOffset>0x038</addressOffset>
<access>read-only</access>
</register>
<register> <name>INTCLEAR</name>
<description>Interrupt CLEAR Register</description>
<alternateRegister>INTSTATUS</alternateRegister>
<addressOffset>0x038</addressOffset>
<access>write-only</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="GPIO0"> <name>GPIO0_Secure</name>
<description>General-purpose I/O 0 (Secure)</description>
<baseAddress>0x51000000</baseAddress>
<groupName>GPIO (Secure)</groupName>
</peripheral>
<peripheral> <name>UART0</name>
<version>1.0</version>
<description>UART 0</description>
<groupName>UART</groupName>
<baseAddress>0x40105000</baseAddress>
<size>32</size>
<access>read-write</access>
<addressBlock>
<offset>0</offset>
<size>0x4C</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UARTRXINTR0</name>
<description>UART0 receive FIFO interrupt</description>
<value>39</value>
<name>UARTTXINTR0</name>
<description>UART0 transmit FIFO interrupt</description>
<value>40</value>
<name>UARTRTINTR0</name>
<description>UART0 receive timeout interrupt</description>
<value>41</value>
<name>UARTMSINTR0</name>
<description>UART0 modem status interrupt</description>
<value>42</value>
<name>UARTEINTR0</name>
<description>UART0 error interrupt</description>
<value>43</value>
<name>UARTINTR0</name>
<description>UART0 interrupt</description>
<value>44</value>
</interrupt>
<registers>
<register> <name>UARTDR</name>
<description>Data register</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<fields>
<field> <name>Data</name>
<description>Receive/Transmit data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field> <name>FE</name>
<description>Framing error: Indicates the received character
did not had a valid stop bit</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>PE</name>
<description>Parity error: Indicates that the parity of the
received data character does not match the parity
selected</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>BE</name>
<description>Break error: Indicates that the received data input
was held LOW for longer than a full-word transmission
time</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>OE</name>
<description>Overrun error: Indicates if data is received and the
receive FIFO is already full.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register> <name>UARTRSR_UARTECR</name>
<description>Receive status register/error clear register</description>
<addressOffset>0x004</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-write</access>
<fields>
<field> <name>FE</name>
<description>Framing error: Indicates the received character
did not had a valid stop bit</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>PE</name>
<description>Parity error: Indicates that the parity of the
received data character does not match the parity
selected</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>BE</name>
<description>Break error: Indicates that the received data input
was held LOW for longer than a full-word transmission
time</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>OE</name>
<description>Overrunerror: Indicates if data is received and the
receive FIFO is already full.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register> <name>UARTRFR</name>
<description>Flag register</description>
<addressOffset>0x018</addressOffset>
<access>read-only</access>
<fields>
<field> <name>CTS</name>
<description>Clear to send</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>DSR</name>
<description>Data set ready</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>DCD</name>
<description>Data carrier detect</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>BUSY</name>
<description>UART busy</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>RXFE</name>
<description>Receive FIFO empty</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>TXFF</name>
<description>Transmit FIFO full</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>RXFF</name>
<description>Receive FIFO full</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>TXFE</name>
<description>Transmit FIFO empty</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>RI</name>
<description>Ring indicator</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register> <name>UARTILPR</name>
<description>IrDA low-power counter register</description>
<addressOffset>0x020</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-write</access>
<fields>
<field> <name>ILPDVSR</name>
<description>8-bit low-power divisor value</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register> <name>UARTIBRD</name>
<description>Integer baud rate register</description>
<addressOffset>0x024</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-write</access>
<fields>
<field> <name>BAUD_DIVINT</name>
<description>The integer baud rate divisor</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register> <name>UARTFBRD</name>
<description>Fractional baud rate register</description>
<addressOffset>0x028</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-write</access>
<fields>
<field> <name>BAUD_DIVINT</name>
<description>The integer baud rate divisor</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register> <name>UARTLCR_H</name>
<description>Line control register</description>
<addressOffset>0x02C</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-write</access>
<fields>
<field> <name>BRK</name>
<description>Send break</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>PEN</name>
<description>Parity enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>EPS</name>
<description>Even parity select</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>STP2</name>
<description>Two stop bits select</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>FEN</name>
<description>Enable FIFOs</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>WLEN</name>
<description>Word length</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field> <name>SPS</name>
<description>Stick parity select</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register> <name>UARTCR</name>
<description>Control register</description>
<addressOffset>0x030</addressOffset>
<resetValue>0x00000300</resetValue>
<access>read-write</access>
<fields>
<field> <name>UARTEN</name>
<description>UART enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>UART is disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>UART is enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SIREN</name>
<description>SIR enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>SIR is disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>SIR is enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SIRLP</name>
<description>IrDA SIR low power mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>SIR low power mode is disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>SIR low power mode is enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>LBE</name>
<description>Loop back enable</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>Loop back mode is disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Loop back mode is enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>TXE</name>
<description>Transmit enable</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>Transmission is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Transmission is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>RXE</name>
<description>Receive enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description> Reception is disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Reception is enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>DTR</name>
<description>Data transmit ready</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>RTS</name>
<description>Request to send</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>Out1</name>
<description>Complement of the UART Out1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>Out2</name>
<description>Complement of the UART Out2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>RTSEn</name>
<description>RTS hardware flow control enable</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>RTS hardware flow control is disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>RTS hardware flow control is enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CTSEn</name>
<description>CTS hardware flow control enable</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>CTS hardware flow control is disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>CTS hardware flow control is enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>UARTIFLS</name>
<description>Interrupt FIFO level select register</description>
<addressOffset>0x034</addressOffset>
<resetValue>0x00000012</resetValue>
<access>read-write</access>
<fields>
<field> <name>TXIFLSEL</name>
<description>Transmit interrupt FIFO level select</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>1/8 full</name>
<description>Transmit FIFO becomes less than or equal to 1/8 full</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1/4 full</name>
<description>Transmit FIFO becomes less than or equal to 1/4 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>1/2 full</name>
<description>Transmit FIFO becomes less than or equal to 1/2 full</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>3/4 full</name>
<description>Transmit FIFO becomes less than or equal to 3/4 full</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>7/8 full</name>
<description>Transmit FIFO becomes less than or equal to 7/8 full</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>RXIFLSEL</name>
<description>Receive interrupt FIFO level select</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>1/8 full</name>
<description>Receive FIFO becomes greater than or equal to 1/8 full</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>1/4 full</name>
<description>Receive FIFO becomes greater than or equal to 1/4 full</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>1/2 full</name>
<description>Receive FIFO becomes greater than or equal to 1/2 full</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>3/4 full</name>
<description>Receive FIFO becomes greater than or equal to 3/4 full</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>7/8 full</name>
<description>Receive FIFO becomes greater than or equal to 7/8 full</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>UARTIMSC</name>
<description>Interrupt mask set/clear register</description>
<addressOffset>0x038</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-write</access>
<fields>
<field> <name>RIMIM</name>
<description>nUARTRI modem interrupt mask</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Clears the mask</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Set</name>
<description>Sets the mask</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CTSMIM</name>
<description>nUARTCTS modem interrupt mask.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Clears the mask</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Set</name>
<description>Sets the mask</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>DCDMIM</name>
<description>nUARTDCD modem interrupt mask</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Clears the mask</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Set</name>
<description>Sets the mask</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>DSRMIM</name>
<description>nUARTDSR modem interrupt mask</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Clears the mask</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Set</name>
<description>Sets the mask</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>RXIM</name>
<description>Receive interrupt mask</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Clears the mask</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Set</name>
<description>Sets the mask</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>TXIM</name>
<description>Transmit interrupt mask</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Clears the mask</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Set</name>
<description>Sets the mask</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>RTIM</name>
<description>Receive timeout interrupt mask</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Clears the mask</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Set</name>
<description>Sets the mask</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>FEIM</name>
<description>Framing error interrupt mask</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Clears the mask</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Set</name>
<description>Sets the mask</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>PEIM</name>
<description>Parity error interrupt mask</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Clears the mask</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Set</name>
<description>Sets the mask</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>BEIM</name>
<description>Break error interrupt mask</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Clears the mask</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Set</name>
<description>Sets the mask</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>OEIM</name>
<description>Overrun error interrupt mask</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Clears the mask</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Set</name>
<description>Sets the mask</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>UARTRIS</name>
<description>Raw interrupt status register</description>
<addressOffset>0x03C</addressOffset>
<access>read-only</access>
<fields>
<field> <name>RIRMIS</name>
<description>nUARTRI modem interrupt status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>CTSRMIS</name>
<description>nUARTCTS modem interrupt status.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>DCDRMIS</name>
<description>nUARTDCD modem interrupt status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>DSRRMIS</name>
<description>nUARTDSR modem interrupt status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>RXRIS</name>
<description>Receive interrupt status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>TXRIS</name>
<description>Transmit interrupt status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>RTRIS</name>
<description>Receive timeout interrupt status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>FERIS</name>
<description>Framing error interrupt status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>PERIS</name>
<description>Parity error interrupt status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>BERIS</name>
<description>Break error interrupt status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>OERIS</name>
<description>Overrun error interrupt status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register> <name>UARTMIS</name>
<description>Masked interrupt status register</description>
<addressOffset>0x040</addressOffset>
<access>read-only</access>
<fields>
<field> <name>RIMMIS</name>
<description>nUARTRI modem masked interrupt status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>CTSMMIS</name>
<description>nUARTCTS modem masked interrupt status.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>DCDMMIS</name>
<description>nUARTDCD modem masked interrupt status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>DSRMMIS</name>
<description>nUARTDSR modem masked interrupt status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>RXMIS</name>
<description>Receive masked interrupt status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>TXMIS</name>
<description>Transmit masked interrupt status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>RTMIS</name>
<description>Receive timeout masked interrupt status</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>FEMIS</name>
<description>Framing error masked interrupt status</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>PEMIS</name>
<description>Parity error masked interrupt status</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>BEMIS</name>
<description>Break error masked interrupt status</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>OEMIS</name>
<description>Overrun error masked interrupt status</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register> <name>UARTICR</name>
<description>Interrupt clear register</description>
<addressOffset>0x044</addressOffset>
<access>write-only</access>
<fields>
<field> <name>RIMIC</name>
<description>nUARTRI modem interrupt clear, write 1 to clear, write 0 has no effect</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>CTSMIC</name>
<description>nUARTCTS modem interrupt clear, write 1 to clear, write 0 has no effect</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>DCDMIC</name>
<description>nUARTDCD modem interrupt clear, write 1 to clear, write 0 has no effect</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>DSRIC</name>
<description>nUARTDSR modem interrupt clear, write 1 to clear, write 0 has no effect</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>RXIC</name>
<description>Receive interrupt clear, write 1 to clear, write 0 has no effect</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>TXIC</name>
<description>Transmit interrupt clear, write 1 to clear, write 0 has no effect</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>RTIC</name>
<description>Receive timeout interrupt clear, write 1 to clear, write 0 has no effect</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>FEIC</name>
<description>Framing error interrupt clear, write 1 to clear, write 0 has no effect</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>PEIC</name>
<description>Parity error interrupt clear, write 1 to clear, write 0 has no effect</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>BEIC</name>
<description>Break error interrupt clear, write 1 to clear, write 0 has no effect</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>OEIC</name>
<description>Overrun error interrupt clear, write 1 to clear, write 0 has no effect</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register> <name>UARTDMACR</name>
<description>DMA control register</description>
<addressOffset>0x048</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-write</access>
<fields>
<field> <name>RXDMAE</name>
<description>Receive DMA enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>Receive DMA is disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Receive DMA is enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>TXDMAE</name>
<description>Transmit DMA enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>Transmit DMA is disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Transmit DMA is enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>DMAONERR</name>
<description>DMA on error</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>DMA receive request outputs are
enabled when the UART error interrupt is
asserted</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>DMA receive request outputs are
disabled when the UART error interrupt is
asserted</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="UART0"> <name>UART0_Secure</name>
<description>UART 0 (Secure)</description>
<baseAddress>0x50105000</baseAddress>
<groupName>UART (Secure)</groupName>
</peripheral>
<peripheral> <name>WATCHDOG</name>
<description>Non-secure Watchdog Timer</description>
<groupName>WATCHDOG</groupName>
<baseAddress>0x40081000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0xC04</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>NONSEC_WATCHDOG_IRQ</name>
<description>Non-Secure Watchdog Interrupt</description>
<value>1</value>
</interrupt>
<registers>
<register> <name>WDOGLOAD</name>
<description>Watchdog Load Register</description>
<addressOffset>0x000</addressOffset>
<resetValue>0xFFFFFFFF</resetValue>
</register>
<register> <name>WDOGVALUE</name>
<description>Watchdog Value Register</description>
<addressOffset>0x004</addressOffset>
<resetValue>0xFFFFFFFF</resetValue>
<access>read-only</access>
</register>
<register> <name>WDOGCONTROL</name>
<description>Watchdog Control Register</description>
<addressOffset>0x008</addressOffset>
<resetValue>0x0</resetValue>
<fields>
<field> <name>INTEN</name>
<description>Enable the interrupt event</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>Disable Watchdog interrupt</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Enable Watchdog interrupt.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>RESEN</name>
<description>Enable watchdog reset output</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Disable</name>
<description>Disable Watchdog reset</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Enable Watchdog reset</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>WDOGINTCLR</name>
<description>Watchdog Interrupt Clear Register</description>
<addressOffset>0x00C</addressOffset>
<resetValue>0x00000000</resetValue>
<access>write-only</access>
<fields>
<field>
<name>INT</name>
<description>Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
</field>
</fields>
</register>
<register> <name>WDOGRIS</name>
<description>Watchdog Raw Interrupt Status Register</description>
<addressOffset>0x010</addressOffset>
<resetValue>0x0</resetValue>
<access>read-only</access>
<fields>
<field> <name>RIS</name>
<description>Raw watchdog Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register> <name>WDOGMIS</name>
<description>Watchdog Mask Interrupt Status Register</description>
<addressOffset>0x014</addressOffset>
<resetValue>0x0</resetValue>
<access>read-only</access>
<fields>
<field> <name>MIS</name>
<description>Masked Watchdog Interrupt</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register> <name>WDOGLOCK</name>
<description>Watchdog Lock Register</description>
<addressOffset>0xC00</addressOffset>
<resetValue>0x00000000</resetValue>
<fields>
<field> <name>Access</name>
<description>Enable register writes</description>
<bitOffset>1</bitOffset>
<bitWidth>31</bitWidth>
</field>
<field> <name>Status</name>
<description>Register write enable status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>Enabled</name>
<description>Write access to all other registers is enabled. This is the default.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Disabled</name>
<description>Write access to all other registers is disabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral> <name>iCache</name>
<version>1.0</version>
<description>Cache</description>
<groupName>Cache</groupName>
<baseAddress>0x50010000</baseAddress>
<size>32</size>
<access>read-write</access>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register> <name>ICHWPARAMS</name>
<description>Hardware Parameter Register</description>
<addressOffset>0x00</addressOffset>
<access>read-only</access>
<fields>
<field> <name>CSIZE</name>
<description>Cache size: Defines the size of
the instruction cache</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field> <name>STATS</name>
<description>Presence of Statistic Functionality</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field> <name>DMA</name>
<description>Presence of DMA Engine</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Support</name>
<description>The Instruction cache supports
pre-fetch and locking</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Unsupport</name>
<description>The Instruction cache does not
support pre-fetch and locking</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>INVMAT</name>
<description>Indicates whether invalidate cache line
on write match is enabled</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Enabled</name>
<description>Indicates Invalidate Cache Line
on Write Match is enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>COFFSIZE</name>
<description>Cacheable Block Size</description>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
<access>read-only</access>
</field>
<field> <name>COFFSET</name>
<description>Cacheable Offset Address</description>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register> <name>ICCTRL</name>
<description>Instruction Cache Control Register</description>
<addressOffset>0x04</addressOffset>
<resetValue>0x0</resetValue>
<access>read-write</access>
<fields>
<field> <name>CACHEEN</name>
<description>Enable Cache</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Enabled</name>
<description>Caching is enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Disabled</name>
<description>All accesses bypass the cache</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>FINV</name>
<description>Full Cache Invalidate</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Invalidate</name>
<description>Triggers the instruction cache to start
invalidating all cache lines</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>STATEN</name>
<description>Enable Statistic function</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Enabled</name>
<description>Cache statistic counters are enabled</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Disabled</name>
<description>Cache statistic counters are disabled</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>STATC</name>
<description>Clear Statistic values</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Triggers the instruction cache to start
clear all cache statistic counters</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>HALLOC</name>
<description>Enable Handler Allocation</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>LOW</name>
<description>All incoming handler code fetches are not
allocated a cache line if a miss occurs</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>HIGH</name>
<description>Handler code access is treated like any other
code access arriving at its interface</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>ICIRQSTAT</name>
<description>Interrupt Request Status Register</description>
<addressOffset>0x100</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-only</access>
<fields>
<field> <name>IC_STATUS</name>
<description>Invalidate Complete IRQ Status</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Completed</name>
<description>Indicates that a cache invalidation
process has been completed</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CDC_STATUS</name>
<description>Cache Disable Complete IRQ Status</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Completed</name>
<description>Indicates that a request to disable
the cache has been completed</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CEC_STATUS</name>
<description>Cache Enable Complete IRQ Status</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Completed</name>
<description>Indicates that a request to enable
the cache has been completed</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CFE_STATUS</name>
<description>Cache Fill Error IRQ Status</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Err_Occurred</name>
<description>Indicates that a bus error occurred
while filling a cache line</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SV_STATUS</name>
<description>Security violation IRQ Status</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field> <name>SS_STATUS</name>
<description>Statistics Saturated Status</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Saturated</name>
<description>Indicates that the internal
statistic counters have saturated</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>ICIRQSCLR</name>
<description>Interrupt Status Clear register</description>
<addressOffset>0x104</addressOffset>
<resetValue>0x0</resetValue>
<access>write-only</access>
<fields>
<field> <name>IC_CLR</name>
<description>Invalidate Complete IRQ
Status Clear</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Clear the Invalidate Complete
IRQ Status</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CDC_CLR</name>
<description>Cache Disable Complete IRQ
Status Clear</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Clear Cache Disable Complete IRQ
Status</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CEC_CLR</name>
<description>Cache Enable Complete IRQ
Status Clear</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Clear the Cache Enable Complete
IRQ Status</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CFE_CLR</name>
<description>Cache Fill Error IRQ Status
Clear</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Clear the Cache Fill Error
IRQ Status</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SV_CLR</name>
<description>Security violation IRQ Status
Clear</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Clear the Security violation
IRQ Status</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SS_CLR</name>
<description>Statistics Saturated Status
Clear</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Clear</name>
<description>Clear the Statistics Saturated
Status</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>ICIRQEN</name>
<description>Interrupt Enable register</description>
<addressOffset>0x108</addressOffset>
<resetValue>0x0</resetValue>
<access>read-write</access>
<fields>
<field> <name>IC_EN</name>
<description>Invalidate Complete IRQ Enable</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Enabled</name>
<description>Enable the Invalidate
Complete IRQ</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Disabled</name>
<description>Disable the Invalidate
Complete IRQ</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CDC_EN</name>
<description>Cache Disable Complete
IRQ Enable</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Enabled</name>
<description>Enable the Cache Disable
Complete IRQ</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Disabled</name>
<description>Disable the Cache Disable
Complete IRQ</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CEC_EN</name>
<description>Cache Enable Complete IRQ
Enable</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Enabled</name>
<description>Enable the Cache Enable
Complete IRQ</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Disabled</name>
<description>Disable the Cache Enable
Complete IRQ</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>CFE_EN</name>
<description>Cache Fill Error IRQ Enable</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Enabled</name>
<description>Enable the Cache Fill
Error IRQ</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Disabled</name>
<description>Disable the Cache Fill
Error IRQ</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SV_EN</name>
<description>Security violation IRQ Enable</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Enabled</name>
<description>Enable the Security
violation IRQ</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Disabled</name>
<description>Disable the Security
violation IRQ</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>SS_EN</name>
<description>Statistics Saturated Enable</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Enabled</name>
<description>Enable the Statistics Saturated</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Disabled</name>
<description>Disable the Statistics Saturated</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>ICDBGFILLERR</name>
<description>Address where the latest fill error was seen</description>
<addressOffset>0x10C</addressOffset>
<resetValue>0x0</resetValue>
<access>read-only</access>
</register>
<register> <name>ICSH</name>
<description>Instruction Cache Statistic Hit Count register</description>
<addressOffset>0x300</addressOffset>
<resetValue>0x0</resetValue>
<access>read-only</access>
</register>
<register> <name>ICSM</name>
<description>Instruction Cache Statistic Miss Count register</description>
<addressOffset>0x304</addressOffset>
<resetValue>0x0</resetValue>
<access>read-only</access>
</register>
<register> <name>ICSUC</name>
<description>Instruction Cache Statistic Uncached
Count register</description>
<addressOffset>0x308</addressOffset>
<resetValue>0x0</resetValue>
<access>read-only</access>
</register>
<register> <name>PIDR4</name>
<description>Product ID Register 4</description>
<addressOffset>0xFD0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x04</resetValue>
</register>
<register> <name>PIDR5</name>
<description>Product ID Register 5</description>
<addressOffset>0xFD4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>PIDR6</name>
<description>Product ID Register 6</description>
<addressOffset>0xFD8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>PIDR7</name>
<description>Product ID Register 7</description>
<addressOffset>0xFDC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>PIDR0</name>
<description>Product ID Register 0</description>
<addressOffset>0xFE0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x57</resetValue>
</register>
<register> <name>PIDR1</name>
<description>Product ID Register 1</description>
<addressOffset>0xFE4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xB8</resetValue>
</register>
<register> <name>PIDR2</name>
<description>Product ID Register 2</description>
<addressOffset>0xFE8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0B</resetValue>
</register>
<register> <name>PIDR3</name>
<description>Product ID Register 3</description>
<addressOffset>0xFEC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>CIDR0</name>
<description>Component ID Register 0</description>
<addressOffset>0xFF0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0D</resetValue>
</register>
<register> <name>CIDR1</name>
<description>Component ID Register 1</description>
<addressOffset>0xFF4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xF0</resetValue>
</register>
<register> <name>CIDR2</name>
<description>Component ID Register 2</description>
<addressOffset>0xFF8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x05</resetValue>
</register>
<register> <name>CIDR3</name>
<description>Component ID Register 3</description>
<addressOffset>0xFFC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xB1</resetValue>
</register>
</registers>
</peripheral>
<peripheral> <name>PWM</name>
<description>PWM_IP6512</description>
<groupName>PWM</groupName>
<baseAddress>0x40107000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x020</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PWMINT0</name>
<description>PWM0 interrupt</description>
<value>70</value>
<name>PWMINT1</name>
<description>PWM1 interrupt</description>
<value>74</value>
<name>PWMINT2</name>
<description>PWM2 interrupt</description>
<value>75</value>
</interrupt>
<registers>
<register> <name>PWMCR</name>
<description>PWM Control Register</description>
<addressOffset>0x000</addressOffset>
<resetValue>0x0</resetValue>
<access>read-write</access>
<fields>
<field> <name>OUTPUT_SET</name>
<description>Start stop bit for the pwm_output</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
<enumeratedValues>
<enumeratedValue>
<name>Enabled</name>
<description>Generate programmed waveform on
pwm_output</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Disabled</name>
<description>Set pwm_output continually high</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>PWMPR</name>
<description>PWM Period Register. Number of system clock cycles
indicating the period of PWM cycle.The minimum and maximum
values have special significance. 0x0: pwm_output continually high
0xFFFFFFFF: pwm_output continually low</description>
<addressOffset>0x004</addressOffset>
<resetValue>0x0</resetValue>
<access>read-write</access>
</register>
<register> <name>PWMHR</name>
<description>PWM High Iime Register. This register contains
the number of system clock cycles for during which the pwm_output
should be kept high in a PWM cycle</description>
<addressOffset>0x008</addressOffset>
<resetValue>0x0</resetValue>
<access>read-write</access>
</register>
<register> <name>PWMEI</name>
<description>PWM Enable Interrupt Register</description>
<addressOffset>0x010</addressOffset>
<access>write-only</access>
<fields>
<field> <name>Enable_BIT</name>
<description>Determines whether the write accesses
the Interrupt Enable register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Enabled</name>
<description>Enable the Interrupt generation</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>PWMDI</name>
<description>PWM Disable Interrupt Register</description>
<addressOffset>0x014</addressOffset>
<access>write-only</access>
<fields>
<field> <name>Disable_BIT</name>
<description>Determines whether the write accesses
the Interrupt Disable register</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Disabled</name>
<description>Disable the Interrupt generation</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>PWMRI</name>
<description>PWM Read Intr Enable Register.Reading from this
address accesses the current state of the interrupt
control registers</description>
<addressOffset>0x018</addressOffset>
<resetValue>0x0</resetValue>
<access>read-only</access>
<fields>
<field> <name>Enable_BIT</name>
<description>Check whether the Interrupt is Enabled</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Enabled</name>
<description>Interrupt is Enabled</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register> <name>PWMIS</name>
<description>PWM Read Interrupt Status Register</description>
<addressOffset>0x01c</addressOffset>
<resetValue>0x0</resetValue>
<access>read-only</access>
<fields>
<field> <name>Status</name>
<description>Reading from this address returns the current
state of the PWM Interrupt output, and then sets the
bit low</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
<enumeratedValues>
<enumeratedValue>
<name>Active</name>
<description>Interrupt is active</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>Not active</name>
<description>Interrupt is not active</description>
<value>0</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="WATCHDOG"> <name>WATCHDOG_Secure</name>
<description>Watchdog (Secure)</description>
<groupName>WATCHDOG (Secure)</groupName>
<baseAddress>0x50081000</baseAddress>
</peripheral>
<peripheral derivedFrom="WATCHDOG"> <name>S32KWATCHDOG</name>
<description>S32K Watchdog (Secure)</description>
<groupName>WATCHDOG (Secure)</groupName>
<baseAddress>0x5002E000</baseAddress>
</peripheral>
<peripheral> <name>SCC</name>
<description>Serial Communication Controller</description>
<groupName>SCC</groupName>
<baseAddress>0x5010B000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register> <name>CLK_CTRL_SEL</name>
<addressOffset>0x000</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000072</resetValue>
<fields>
<field>
<name>sel_premux_clk</name>
<description>0: 32k 1: FASTCLK</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>sel_dapswmux_clk</name>
<description>0: PRE_MUX_CLK 1: TCK</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>sel_mainmux_clk</name>
<description>0: PLL0_CLK 1: PRE_MUX_CLK</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>sel_refmux_clk</name>
<description>0: PRE_MUX_CLK 1: PRE_PLL_CLK</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>sel_rm38kmux_clk</name>
<description>0: REF_MUX_CLK 1: RM38K</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>sel_sccmux_clk</name>
<description>0: SCCCLK 1: PRE_MUX_CLK</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>sel_rm38p4_premux_clk</name>
<description>0: SYSSYSSUGCLK 1: NRM138P4</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>ctrl_sel_test_mux_clk</name>
<description>ctrl_sel_test_mux_clk</description>
<bitRange>[11:7]</bitRange>
</field>
</fields>
</register>
<register> <name>CLK_PLL_PREDIV_CTRL</name>
<addressOffset>0x004</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>prediv_ctrl</name>
<description>prediv_ctrl</description>
<bitRange>[9:0]</bitRange>
</field>
</fields>
</register>
<register> <name>CLK_POSTDIV_CTRL_FLASH</name>
<addressOffset>0x00C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<fields>
<field>
<name>postdiv_ctrl_flash_div</name>
<description>postdiv_ctrl_flash_div</description>
<bitRange>[7:0]</bitRange>
</field>
</fields>
</register>
<register> <name>CLK_POSTDIV_CTRL_QSPI</name>
<addressOffset>0x010</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<fields>
<field>
<name>postdiv_ctrl_qspi_div</name>
<description>postdiv_ctrl_qspi_div</description>
<bitRange>[7:0]</bitRange>
</field>
</fields>
</register>
<register> <name>CLK_POSTDIV_CTRL_RTC</name>
<addressOffset>0x014</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>postdiv_ctrl_rtc_div</name>
<description>postdiv_ctrl_rtc_div</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>CLK_POSTDIV_CTRL_SD</name>
<addressOffset>0x018</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<fields>
<field>
<name>postdiv_ctrl_sd_div</name>
<description>postdiv_ctrl_sd_div</description>
<bitRange>[7:0]</bitRange>
</field>
</fields>
</register>
<register> <name>CLK_POSTDIV_CTRL_TEST</name>
<addressOffset>0x01C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xA</resetValue>
<fields>
<field>
<name>postdiv_ctrl_test_div</name>
<description>postdiv_ctrl_test_div</description>
<bitRange>[7:0]</bitRange>
</field>
</fields>
</register>
<register> <name>CTRL_BYPASS_DIV</name>
<addressOffset>0x020</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<fields>
<field>
<name>bypass_div_pll_div_prediv_clk</name>
<description>0: Not bypass 1: bypass</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>bypass_qspi_div_clk</name>
<description>0: Not bypass 1: bypass</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>bypass_rtc_div_clk</name>
<description>0: Not bypass 1: bypass</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>bypass_sd_div_clk</name>
<description>0: Not bypass 1: bypass</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>bypass_test_div_clk</name>
<description>0: Not bypass 1: bypass</description>
<bitRange>[6:6]</bitRange>
</field>
</fields>
</register>
<register> <name>PLL_CTRL_PLL0_CLK</name>
<addressOffset>0x024</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>pd_pll0</name>
<description>Power down PLL0</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>pd_foutpostdiv1pd</name>
<description>Power down FOUTPOSTDIV1PD:</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>pd_foutpostdiv2pd</name>
<description>Power down FOUTPOSTDIV2PD</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>pd_foutvcopd</name>
<description>Power down FOUTVCOPD</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>bypass_pll0</name>
<description>Bypass PLL0</description>
<bitRange>[4:4]</bitRange>
</field>
</fields>
</register>
<register> <name>PLL_POSTDIV_CTRL_PLL0_CLK</name>
<addressOffset>0x028</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1</resetValue>
<fields>
<field>
<name>pll_postdiv_ctrl_pll0_clk</name>
<description>pll_postdiv_ctrl_pll0_clk</description>
<bitRange>[3:0]</bitRange>
</field>
</fields>
</register>
<register> <name>PLL_CTRL_MULT_PLL0_CLK</name>
<addressOffset>0x02C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1388</resetValue>
<fields>
<field>
<name>pll_mult_ctrl_pll0_clk</name>
<description>pll_mult_ctrl_pll0_clk</description>
<bitRange>[13:0]</bitRange>
</field>
</fields>
</register>
<register> <name>CLK_CTRL_ENABLE</name>
<addressOffset>0x030</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFF</resetValue>
<fields>
<field>
<name>ctrl_enable_1hz</name>
<description>0: Disable; 1: Enable</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>ctrl_enable_dapswclk</name>
<description>0: Disable; 1: Enable</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>ctrl_enable_gpiohclk</name>
<description>0: Disable; 1: Enable</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>ctrl_enable_i2sclk0</name>
<description>0: Disable; 1: Enable</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>ctrl_enable_i2sclk1</name>
<description>0: Disable; 1: Enable</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>ctrl_enable_i2sclk2</name>
<description>0: Disable; 1: Enable</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>ctrl_enable_mainclk</name>
<description>0: Disable; 1: Enable</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>ctrl_enable_qspi_phy_clk</name>
<description>0: Disable; 1: Enable</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>ctrl_enable_refclk</name>
<description>0: Disable; 1: Enable</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>ctrl_enable_rm38kclk</name>
<description>0: Disable; 1: Enable</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>ctrl_enable_sccclk</name>
<description>0: Disable; 1: Enable</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>ctrl_enable_sdphyclk</name>
<description>0: Disable; 1: Enable</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>ctrl_enable_testclk</name>
<description>0: Disable; 1: Enable</description>
<bitRange>[15:15]</bitRange>
</field>
</fields>
</register>
<register> <name>CLK_STATUS</name>
<addressOffset>0x034</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x3</resetValue>
<fields>
<field>
<name>status_out_clk_mainclk_ready</name>
<description>Clock ready (active)</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>status_lock_signal_pll0_clk</name>
<description>PLL Lock Status</description>
<bitRange>[1:1]</bitRange>
</field>
</fields>
</register>
<register> <name>RESET_CTRL</name>
<addressOffset>0x040</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>GPTIMER_RESET</name>
<description>Reset Active low</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>I2C0_RESET</name>
<description>Reset Active low</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>I2C1_RESET</name>
<description>Reset Active low</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>I2S_RESET</name>
<description>Reset Active low</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>SPI_RESET</name>
<description>Reset Active low</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>QSPI_RESET</name>
<description>Reset Active low</description>
<bitRange>[6:6]</bitRange>
</field>
<field>
<name>UART0_RESET</name>
<description>Reset Active low</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>UART1_RESET</name>
<description>Reset Active low</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>GPIO_RESET</name>
<description>Reset Active low</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>PVT_RESET</name>
<description>Reset Active low</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>PWM0_RESET</name>
<description>Reset Active low</description>
<bitRange>[11:11]</bitRange>
</field>
<field>
<name>PWM1_RESET</name>
<description>Reset Active low</description>
<bitRange>[12:12]</bitRange>
</field>
<field>
<name>PWM2_RESET</name>
<description>Reset Active low</description>
<bitRange>[13:13]</bitRange>
</field>
<field>
<name>RTC_RESET</name>
<description>Reset Active low</description>
<bitRange>[14:14]</bitRange>
</field>
</fields>
</register>
<register> <name>DBG_CTRL</name>
<addressOffset>0x048</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1F</resetValue>
<fields>
<field>
<name>SSE_200_DBGENIN</name>
<description>0: Not enable 1: Enable</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>SSE_200_NIDENIN</name>
<description>0: Not enable 1: Enable</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>SSE_200_SPIDENIN</name>
<description>0: Not enable 1: Enable</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>SSE_200_SPNIDENIN</name>
<description>0: Not enable 1: Enable</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>TODBGENSEL0</name>
<description>0: Enable 1: Mask or bypass</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>TODBGENSEL1</name>
<description>0: Enable 1: Mask or bypass</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>DBG_DCU_FORCE</name>
<description>SSE-200 debug ports control</description>
<bitRange>[31:30]</bitRange>
</field>
</fields>
</register>
<register> <name>SRAM_CTRL</name>
<addressOffset>0x04C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x48100000</resetValue>
<fields>
<field>
<name>CODE_SRAMx_PGEN</name>
<description>SRAM cell power gate enable</description>
<bitRange>[15:0]</bitRange>
</field>
</fields>
</register>
<register> <name>INTR_CTRL</name>
<addressOffset>0x050</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>QSPI_MPC_CFG_INIT_VALUE</name>
<description>0: Secure mode 1: Non-secure mode</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>SRAM_MPC_CFG_INIT_VALUE</name>
<description>0: Secure mode 1: Non-secure mode</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>AZ_MPC_CFG_INIT_VALUE</name>
<description>0: Secure mode 1: Non-secure mode</description>
<bitRange>[6:6]</bitRange>
</field>
</fields>
</register>
<register> <name>CLK_TEST_CTRL</name>
<addressOffset>0x054</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>CLK_TEST_SEL</name>
<description>Select TESTMUX input</description>
<bitRange>[4:0]</bitRange>
</field>
<field>
<name>CLK_TEST_EN</name>
<description>0: Not enable 1: Enable</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>CLK_MAIN_FORCE_RDY</name>
<description>CLK_MAIN_FORCE_RDY</description>
<bitRange>[6:6]</bitRange>
</field>
</fields>
</register>
<register> <name>CPU0_VTOR</name>
<addressOffset>0x058</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x10000000</resetValue>
<fields>
<field>
<name>CPU0_VTOR_SECURE</name>
<description>Reset vector for CPU0 secure mode</description>
<bitRange>[31:7]</bitRange>
</field>
</fields>
</register>
<register> <name>CPU1_VTOR</name>
<addressOffset>0x060</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1A400000</resetValue>
<fields>
<field>
<name>CPU1_VTOR_SECURE</name>
<description>Reset vector for CPU1 secure mode</description>
<bitRange>[31:7]</bitRange>
</field>
</fields>
</register>
<register> <name>AZ_CPU_VTOR</name>
<addressOffset>0x064</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00A03800</resetValue>
<fields>
<field>
<name>AZ_ROM_REMAP</name>
<description>Remap vector for Alcatraz ROM address space.</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>AZ_CODE_REMAP</name>
<description>Remap vector for Alcatraz Code address space</description>
<bitRange>[15:8]</bitRange>
</field>
<field>
<name>AZ_SYS_REMAP</name>
<description>Remap vector for Alcatraz System address space</description>
<bitRange>[23:16]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_MAIN_INSEL_0</name>
<addressOffset>0x068</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>iomux_main_insel_0</name>
<description>0: Select ATF1 1: Select Main Function</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_MAIN_INSEL_1</name>
<addressOffset>0x06C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>iomux_main_insel_1</name>
<description>0: Select ATF1 1: Select Main Function</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_MAIN_OUTSEL_0</name>
<addressOffset>0x070</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>iomux_main_outsel_0</name>
<description>0: Select ATF1 1: Select Main Function</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_MAIN_OUTSEL_1</name>
<addressOffset>0x074</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>iomux_main_outsel_1</name>
<description>0: Select ATF1 1: Select Main Function</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_MAIN_OENSEL_0</name>
<addressOffset>0x078</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>iomux_main_oensel_0</name>
<description>0: Select ATF1 1: Select Main Function</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_MAIN_OENSEL_1</name>
<addressOffset>0x07C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>iomux_main_oensel_1</name>
<description>0: Select ATF1 1: Select Main Function</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_MAIN_DEFAULT_IN_0</name>
<addressOffset>0x080</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>iomux_main_default_in_0</name>
<description>0: Default to 0 1: Default to 1</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_MAIN_DEFAULT_IN_1</name>
<addressOffset>0x084</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>iomux_main_default_in_1</name>
<description>0: Default to 0 1: Default to 1</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_ALTF1_INSEL_0</name>
<addressOffset>0x088</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>iomux_altf1_insel_0</name>
<description>0: Select ATF2 1: Select ATF1</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_ALTF1_INSEL_1</name>
<addressOffset>0x08C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>iomux_altf1_insel_1</name>
<description>0: Select ATF2 1: Select ATF1</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_ALTF1_OUTSEL_0</name>
<addressOffset>0x090</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>iomux_altf1_outsel_0</name>
<description>0: Select ATF2 1: Select ATF1</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_ALTF1_OUTSEL_1</name>
<addressOffset>0x094</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>iomux_altf1_outsel_1</name>
<description>0: Select ATF2 1: Select ATF1</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_ALTF1_OENSEL_0</name>
<addressOffset>0x098</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>iomux_altf1_oensel_0</name>
<description>0: Select ATF2 1: Select ATF1</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_ALTF1_OENSEL_1</name>
<addressOffset>0x09C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>iomux_altf1_oensel_1</name>
<description>0: Select ATF2 1: Select ATF1</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_ALTF1_DEFAULT_IN_0</name>
<addressOffset>0x0A0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>iomux_altf1_default_in_0</name>
<description>0: Default to 0 1: Default to 1</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_ALTF1_DEFAULT_IN_1</name>
<addressOffset>0x0A4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>iomux_altf1_default_in_1</name>
<description>0: Default to 0 1: Default to 1</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_ALTF2_INSEL_0</name>
<addressOffset>0x0A8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>iomux_altf2_insel_0</name>
<description>0: Select ATF3 1: Select ATF2</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_ALTF2_INSEL_1</name>
<addressOffset>0x0AC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>iomux_altf2_insel_1</name>
<description>0: Select ATF3 1: Select ATF2</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_ALTF2_OUTSEL_0</name>
<addressOffset>0x0B0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>iomux_altf2_outsel_0</name>
<description>0: Select ATF3 1: Select ATF2</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_ALTF2_OUTSEL_1</name>
<addressOffset>0x0B4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>iomux_altf2_outsel_1</name>
<description>0: Select ATF3 1: Select ATF2</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_ALTF2_OENSEL_0</name>
<addressOffset>0x0B8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>iomux_altf2_oensel_0</name>
<description>0: Select ATF3 1: Select ATF2</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_ALTF2_OENSEL_1</name>
<addressOffset>0x0BC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>iomux_altf2_oensel_1</name>
<description>0: Select ATF3 1: Select ATF2</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_ALTF2_DEFAULT_IN_0</name>
<addressOffset>0x0C0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>iomux_altf2_default_in_0</name>
<description>0: Default to 0 1: Default to 1</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOMUX_ALTF2_DEFAULT_IN_1</name>
<addressOffset>0x0C4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>iomux_altf2_default_in_1</name>
<description>0: Default to 0 1: Default to 1</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOPAD_DSO_0</name>
<addressOffset>0x0E8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFF00000</resetValue>
<fields>
<field>
<name>drive_strength0</name>
<description>Least significant bits of the two-bit values that define drive strengths of test chip I/O PA31-PA0</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOPAD_DSO_1</name>
<addressOffset>0x0EC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>drive_strength_0</name>
<description>Least significant bits of the two-bit values that define drive strengths of test chip I/O PA37-PA32</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOPAD_DS1_0</name>
<addressOffset>0x0F0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>drive_strength1</name>
<description>Most significant bits of the two-bit values that define drive strengths of test chip I/O PA31-PA0</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOPAD_DS1_1</name>
<addressOffset>0x0F4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>drive_strength_1</name>
<description>Most significant bits of the two-bit values that define drive strengths of test chip I/O PA37-PA32</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOPAD_PE_0</name>
<addressOffset>0x0F8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>pull_enable</name>
<description>Enables pull resistors of test chip I/O PA31-PA0</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOPAD_PE_1</name>
<addressOffset>0x0FC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>pull_enable</name>
<description>Enables pull resistors of test chip I/O PA37-PA32</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOPAD_PS_0</name>
<addressOffset>0x100</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>pull_select</name>
<description>Enables pull resistors of test chip I/O PA31-PA0</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOPAD_PS_1</name>
<addressOffset>0x104</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>pull_select</name>
<description>Enables pull resistors of test chip I/O PA37-PA32</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOPAD_SR_0</name>
<addressOffset>0x108</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>slew_rate</name>
<description>Selects the slew rate of test chip I/O PA31-PA0</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOPAD_SR_1</name>
<addressOffset>0x10C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>slew_rate</name>
<description>Selects the slew rate of test chip I/O PA37-PA32</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOPAD_IS_0</name>
<addressOffset>0x110</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>input_select</name>
<description>Selects input mode on test chip I/O PA31-PA0</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>IOPAD_IS_1</name>
<addressOffset>0x114</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>input_select</name>
<description>Selects input mode on test chip I/O PA37-PA32</description>
<bitRange>[5:0]</bitRange>
</field>
</fields>
</register>
<register> <name>PVT_CTRL</name>
<addressOffset>0x118</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>TSTSENNUM</name>
<description>Select PVT sensor to write to and read from</description>
<bitRange>[4:0]</bitRange>
</field>
</fields>
</register>
<register> <name>SPARE0</name>
<addressOffset>0x130</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>spare0</name>
<description>Spare read-write register for software</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>STATIC_CONF_SIG1</name>
<addressOffset>0x13C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>TISBYPASSIN</name>
<description>Cross Trigger Interface synchronous bypass on CTITRIGIN</description>
<bitRange>[7:0]</bitRange>
</field>
<field>
<name>TISBYPASSACK</name>
<description>Cross Trigger Interface synchronous bypass on CTITRIGOUTACK</description>
<bitRange>[11:8]</bitRange>
</field>
<field>
<name>TIHSBYPASS</name>
<description>Cross Trigger Interface handshake bypass on CTITRIGOUT</description>
<bitRange>[15:12]</bitRange>
</field>
<field>
<name>TINIDENSEL</name>
<description>NIDEN mask on CTITRIGINT</description>
<bitRange>[23:16]</bitRange>
</field>
<field>
<name>TODBGENSEL</name>
<description>DBGEN mask on CTITRIGOUT</description>
<bitRange>[27:24]</bitRange>
</field>
</fields>
</register>
<register> <name>FLASH_DIN_0</name>
<addressOffset>0x1A0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>scc_flash_din0</name>
<description>eFlash 0 and eFlash 1 data input[31:0]</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>FLASH_DIN_1</name>
<addressOffset>0x1A4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>scc_flash_din1</name>
<description>eFlash 0 and eFlash 1 data input{63:32]</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>FLASH_DIN_2</name>
<addressOffset>0x1A8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>scc_flash_din2</name>
<description>eFlash 0 and eFlash 1 data input[95:64]</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>FLASH_DIN_3</name>
<addressOffset>0x1AC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>scc_flash_din3</name>
<description>eFlash 0 and eFlash 1 data input[127:96]</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>FLASH0_DOUT_0</name>
<addressOffset>0x1C0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>scc_flash0_dout0</name>
<description>eFlash 0 data output[31:0]</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>FLASH0_DOUT_1</name>
<addressOffset>0x1C4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>scc_flash0_dout1</name>
<description>eFlash 0 data output[63:32]</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>FLASH0_DOUT_2</name>
<addressOffset>0x1C8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>scc_flash0_dout2</name>
<description>eFlash 0 data output[95:64]</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>FLASH0_DOUT_3</name>
<addressOffset>0x1CC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>scc_flash0_dout3</name>
<description>eFlash 0 data output[127:96]</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>FLASH1_DOUT_0</name>
<addressOffset>0x1D0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>scc_flash1_dout0</name>
<description>eFlash 1 data output[31:0]</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>FLASH1_DOUT_1</name>
<addressOffset>0x1D4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>scc_flash1_dout1</name>
<description>eFlash 1 data output[63:32]</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>FLASH1_DOUT_2</name>
<addressOffset>0x1D8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>scc_flash1_dout2</name>
<description>eFlash 1 data output[95:64]</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>FLASH1_DOUT_3</name>
<addressOffset>0x1DC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0xFFFFFFFF</resetValue>
<fields>
<field>
<name>scc_flash1_dout3</name>
<description>eFlash 1 data output[127:96]</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>SELECTION_CONTROL_REG</name>
<addressOffset>0x1E0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x01000200</resetValue>
<fields>
<field>
<name>clock_phase_shifter_select</name>
<description>QSPI input clock phase shift control</description>
<bitRange>[1:0]</bitRange>
</field>
<field>
<name>clock_phase_shifter_bypass</name>
<description>QSPI input clock phase shift control</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>sdio_mask_delay</name>
<description>SDIO mask delay</description>
<bitRange>[9:8]</bitRange>
</field>
</fields>
</register>
<register> <name>AZ_ROM_REMAP_MASK</name>
<addressOffset>0x1E4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0001FFFF</resetValue>
<fields>
<field>
<name>az_rom_remap_mask</name>
<description>Alcatraz ROM remap mask</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>AZ_ROM_REMAP_OFFSET</name>
<addressOffset>0x1E8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x1A200000</resetValue>
<fields>
<field>
<name>az_rom_remap_offset</name>
<description>Alcatraz ROM remap offset</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>AZ_CODE_REMAP_MASK</name>
<addressOffset>0x1EC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00FFFFFF</resetValue>
<fields>
<field>
<name>az_code_remap_mask</name>
<description>Alcatraz code remap mask</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>AZ_CODE_REMAP_OFFSET</name>
<addressOffset>0x1F0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>az_code_remap_offset</name>
<description>Alcatraz code remap offset</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>AZ_SYS_REMAP_MASK</name>
<addressOffset>0x1F4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0003FFFF</resetValue>
<fields>
<field>
<name>az_sys_remap_mask</name>
<description>Alcatraz system remap mask</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>AZ_SYS_REMAP_OFFSET</name>
<addressOffset>0x1F8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x40010000</resetValue>
<fields>
<field>
<name>az_sys_remap_offset</name>
<description>Alcatraz system remap offset</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>AZ_CTRL</name>
<addressOffset>0x200</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000600</resetValue>
<fields>
<field>
<name>AZ_BOOT_REMAP</name>
<description>Alcatraz remap at boot</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>CPUWAIT</name>
<description>Alcatraz CPU wait at boot:</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>REMOVE_CHACHA_ENGINE</name>
<description>Alcatraz CryptoCell remove CHACHA engine</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>REMOVE_GHASH_ENGINE</name>
<description>Alcatraz CryptoCell remove Ghash engine</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>CHSEC_ISO_ENB</name>
<description>Alcatraz CryptoCell Secure Frame Isolation enable</description>
<bitRange>[4:4]</bitRange>
</field>
<field>
<name>CHSEC_MISC_7</name>
<description>Alcatraz CryptoCell secure Secure Frame control</description>
<bitRange>[5:5]</bitRange>
</field>
<field>
<name>DBGRESETn</name>
<description>Alcatraz reset DBGRESETn</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>HRESETn</name>
<description>Alcatraz reset HRESETn</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>SCC_nPORESETAON_nPORESET_SEL</name>
<description>Alcatraz reset control</description>
<bitRange>[9:9]</bitRange>
</field>
<field>
<name>SCC_PSI_FEATURE_EN</name>
<description>Value of SCC_PSI_FEATURE_EN from SCC</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>SCC_PSI_FEATURE_EN_SEL</name>
<description>Select PSI_FEATURE_EN source</description>
<bitRange>[11:11]</bitRange>
</field>
</fields>
</register>
<register> <name>SSE_OTP_RD_DATA</name>
<addressOffset>0x208</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>sse_otp_rd_data</name>
<description>SSE-200 OTP read data</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>AZ_OTP_RD_DATA</name>
<addressOffset>0x210</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>az_otp_rd_data</name>
<description>Alcatraz OTP read data</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>SPARE_CTRL0</name>
<addressOffset>0x21C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>spare_ctrl0</name>
<description>Spare control register</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>SPARE_CTRL1</name>
<addressOffset>0x220</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
<fields>
<field>
<name>spare_ctrl1</name>
<description>Spare control register</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
<register> <name>CHIP_ID</name>
<addressOffset>0x400</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x07D00477</resetValue>
<fields>
<field>
<name>chip_id</name>
<description>Component ID information</description>
<bitRange>[31:0]</bitRange>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral> <name>SPCTRL</name>
<description>Secure Privilege Control Block</description>
<baseAddress>0x50080000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register> <name>SPCSECTRL</name>
<description>Secure Privilege Controller Secure Configuration Control register</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>BUSWAIT</name>
<description>Bus Access wait control after reset</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<access>read-write</access>
</register>
<register> <name>SECRESPCFG</name>
<description>Security Violation Response Configuration register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>NSCCFG</name>
<description>Non Secure Callable Configuration for IDAU</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>SECMPCINTSTATUS</name>
<description>Secure MPC Interrupt Status</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>SECPPCINTSTAT</name>
<description>Secure PPC Interrupt Status</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>SECPPCINTCLR</name>
<description>Secure PPC Interrupt Clear</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>SECPPCINTEN</name>
<description>Secure PPC Interrupt Enable</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>SECMSCINTSTAT</name>
<description>Secure MSC Interrupt Status</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>SECMSCINTCLR</name>
<description>Secure MSC Interrupt Clear</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>SECMSCINTEN</name>
<description>Secure MSC Interrupt Enable</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>BRGINTSTAT</name>
<description>Bridge Buffer Error Interrupt Status</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>BRGINTCLR</name>
<description>Bridge Buffer Error Interrupt Clear</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>BRGINTEN</name>
<description>Bridge Buffer Error Interrupt Enable</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>AHBNSPPC0</name>
<description>Non-Secure Access AHB slave Peripheral Protection Control 0</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>AHBNSPPCEXP0</name>
<description>Expansion 0 Non_Secure Access AHB slave Peripheral Protection Control</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>AHBNSPPCEXP1</name>
<description>Expansion 1 Non_Secure Access AHB slave Peripheral Protection Control</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>AHBNSPPCEXP2</name>
<description>Expansion 2 Non_Secure Access AHB slave Peripheral Protection Control</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>AHBNSPPCEXP3</name>
<description>Expansion 3 Non_Secure Access AHB slave Peripheral Protection Control</description>
<addressOffset>0x6C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBNSPPC0</name>
<description>Non-Secure Access APB slave Peripheral Protection Control 0</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBNSPPC1</name>
<description>Non-Secure Access APB slave Peripheral Protection Control 1</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBNSPPCEXP0</name>
<description>Expansion 0 Non_Secure Access APB slave Peripheral Protection Control</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBNSPPCEXP1</name>
<description>Expansion 1 Non_Secure Access APB slave Peripheral Protection Control</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBNSPPCEXP2</name>
<description>Expansion 2 Non_Secure Access APB slave Peripheral Protection Control</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBNSPPCEXP3</name>
<description>Expansion 3 Non_Secure Access APB slave Peripheral Protection Control</description>
<addressOffset>0x8C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>AHBSPPPC0</name>
<description>Secure Unprivileged Access AHB slave Peripheral Protection Control 0</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>AHBSPPPCEXP0</name>
<description>Expansion 0 Secure Unprivileged Access AHB slave Peripheral Protection Control</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>AHBSPPPCEXP1</name>
<description>Expansion 1 Secure Unprivileged Access AHB slave Peripheral Protection Control</description>
<addressOffset>0xA4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>AHBSPPPCEXP2</name>
<description>Expansion 2 Secure Unprivileged Access AHB slave Peripheral Protection Control</description>
<addressOffset>0xA8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>AHBSPPPCEXP3</name>
<description>Expansion 3 Secure Unprivileged Access AHB slave Peripheral Protection Control</description>
<addressOffset>0xAC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBSPPPC0</name>
<description>Secure Unprivileged Access APB slave Peripheral Protection Control 0</description>
<addressOffset>0xB0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBSPPPC1</name>
<description>Secure Unprivileged Access APB slave Peripheral Protection Control 1</description>
<addressOffset>0xB4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBSPPPCEXP0</name>
<description>Expansion 0 Secure Unprivileged Access APB slave Peripheral Protection Control</description>
<addressOffset>0xC0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBSPPPCEXP1</name>
<description>Expansion 1 Secure Unprivileged Access APB slave Peripheral Protection Control</description>
<addressOffset>0xC4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBSPPPCEXP2</name>
<description>Expansion 2 Secure Unprivileged Access APB slave Peripheral Protection Control</description>
<addressOffset>0xC8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBSPPPCEXP3</name>
<description>Expansion 3 Secure Unprivileged Access APB slave Peripheral Protection Control</description>
<addressOffset>0xCC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>NSMSCEXP</name>
<description>Expansion MSC Non-Secure Configuration</description>
<addressOffset>0xD0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>PID4</name>
<description>Peripheral ID 4</description>
<addressOffset>0xFD0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000004</resetValue>
</register>
<register> <name>PID0</name>
<description>Peripheral ID 0</description>
<addressOffset>0xFE0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000052</resetValue>
</register>
<register> <name>PID1</name>
<description>Peripheral ID 1</description>
<addressOffset>0xFE4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x000000B8</resetValue>
</register>
<register> <name>PID2</name>
<description>Peripheral ID 2</description>
<addressOffset>0xFE8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0000000B</resetValue>
</register>
<register> <name>PID3</name>
<description>Peripheral ID 3</description>
<addressOffset>0xFEC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>CIDR0</name>
<description>Component ID 0</description>
<addressOffset>0xFF0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0000000D</resetValue>
</register>
<register> <name>CIDR1</name>
<description>Component ID 1</description>
<addressOffset>0xFF4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x000000F0</resetValue>
</register>
<register> <name>CIDR2</name>
<description>Component ID 2</description>
<addressOffset>0xFF8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000005</resetValue>
</register>
<register> <name>CIDR3</name>
<description>Component ID 3</description>
<addressOffset>0xFFC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x000000B1</resetValue>
</register>
</registers>
</peripheral>
<peripheral> <name>NSPCTRL</name>
<description>Non-secure Privilege Control Block</description>
<baseAddress>0x40080000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register> <name>AHBNSPPPC0</name>
<description>Non-Secure Unprivileged Access AHB slave Peripheral Protection Control #0</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>AHBNSPPPCEXP0</name>
<description>Expansion 0 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control</description>
<addressOffset>0xA0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>AHBNSPPPCEXP1</name>
<description>Expansion 1 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control</description>
<addressOffset>0xA4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>AHBNSPPPCEXP2</name>
<description>Expansion 2 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control</description>
<addressOffset>0xA8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>AHBNSPPPCEXP3</name>
<description>Expansion 3 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control</description>
<addressOffset>0xAC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBNSPPPC0</name>
<description>Non-Secure Unprivileged Access APB slave Peripheral Protection Control 0</description>
<addressOffset>0xB0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBNSPPPC1</name>
<description>Non-Secure Unprivileged Access APB slave Peripheral Protection Control 1</description>
<addressOffset>0xB4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBNSPPPCEXP0</name>
<description>Expansion 0 Non_Secure Unprivileged Access APB slave Peripheral Protection Control</description>
<addressOffset>0xC0</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBNSPPPCEXP1</name>
<description>Expansion 1 Non_Secure Unprivileged Access APB slave Peripheral Protection Control</description>
<addressOffset>0xC4</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBNSPPPCEXP2</name>
<description>Expansion 2 Non_Secure Unprivileged Access APB slave Peripheral Protection Control</description>
<addressOffset>0xC8</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>APBNSPPPCEXP3</name>
<description>Expansion 3 Non_Secure Unprivileged Access APB slave Peripheral Protection Control</description>
<addressOffset>0xCC</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>PIDR4</name>
<description>Peripheral ID 4</description>
<addressOffset>0xFD0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>PIDR0</name>
<description>Peripheral ID 0</description>
<addressOffset>0xFE0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000053</resetValue>
</register>
<register> <name>PIDR1</name>
<description>Peripheral ID 1</description>
<addressOffset>0xFE4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x000000B8</resetValue>
</register>
<register> <name>PIDR2</name>
<description>Peripheral ID 2</description>
<addressOffset>0xFE8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0000000B</resetValue>
</register>
<register> <name>PIDR3</name>
<description>Peripheral ID 3</description>
<addressOffset>0xFEC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>CIDR0</name>
<description>Component ID 0</description>
<addressOffset>0xFF0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0000000D</resetValue>
</register>
<register> <name>CIDR1</name>
<description>Component ID 1</description>
<addressOffset>0xFF4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x000000F0</resetValue>
</register>
<register> <name>CIDR2</name>
<description>Component ID 2</description>
<addressOffset>0xFF8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000005</resetValue>
</register>
<register> <name>CIDR3</name>
<description>Component ID 3</description>
<addressOffset>0xFFC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x000000B1</resetValue>
</register>
</registers>
</peripheral>
<peripheral> <name>SRAM0MPC</name>
<description>Memory Protection Controller 0</description>
<groupName>SRAM_MPC</groupName>
<baseAddress>0x50083000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>MPC</name>
<description>MPC Combined</description>
<value>9</value>
</interrupt>
<registers>
<register> <name>CTRL</name>
<description>MPC Control register</description>
<addressOffset>0x00</addressOffset>
<size>32</size>
<access>read-write</access>
<fields>
<field> <name>bit[4]</name>
<description>Security error response configuration</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<enumeratedValue>
<name>RAZ-WI</name>
<description>Read-As-Zero - Writes ignored</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BUSERROR</name>
<description>Bus Error</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field> <name>bit[6]</name>
<description>Data interface gating request</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>bit[7]</name>
<description>Data interface gating acknowledge (RO)</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>bit[8]</name>
<description>Auto-increment</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>bit[31]</name>
<description>Security lockdown</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
<resetValue>0x0</resetValue>
</register>
<register> <name>BLK_MAX</name>
<description>Maximum value of block based index register</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field> <name>bit[3_0]</name>
<description>Block size</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field> <name>bit[31]</name>
<description>Initialization in progress</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register> <name>BLK_CFG</name>
<description>Block Configuration</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<access>read-only</access>
</register>
<register> <name>BLK_IDX</name>
<description>Index value for accessing block based look up table</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>BLK_LUT</name>
<description>Block based gating Look Up Table</description>
<addressOffset>0x1C</addressOffset>
<size>32</size>
<access>read-write</access>
</register>
<register> <name>INT_STAT</name>
<description>Interrupt state</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field> <name>bit[0]</name>
<description>mpc_irq triggered</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
<resetValue>0x0</resetValue>
</register>
<register> <name>INT_CLEAR</name>
<description>Interrupt clear</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field> <name>bit[0]</name>
<description>mpc_irq clear (cleared automatically)</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
<resetValue>0x0</resetValue>
</register>
<register> <name>INT_EN</name>
<description>Interrupt enable</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<access>read-write</access>
<fields>
<field> <name>bit[0]</name>
<description>mpc_irq enable. Bits are valid when mpc_irq triggered is set</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
<resetValue>0x0</resetValue>
</register>
<register> <name>INT_INFO1</name>
<description>Interrupt information 1</description>
<addressOffset>0x2C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>INT_INFO2</name>
<description>Interrupt information 2</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field> <name>bit[15_0]</name>
<description>hmaster</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field> <name>bit[16]</name>
<description>hnonsec</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field> <name>bit[17]</name>
<description>cfg_ns</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register> <name>INT_SET</name>
<description>Interrupt set. Debug purpose only</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<access>write-only</access>
<fields>
<field> <name>bit[0]</name>
<description>mpc_irq set. Debug purpose only</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
<resetValue>0x0</resetValue>
</register>
<register> <name>PIDR4</name>
<description>Peripheral ID 4</description>
<addressOffset>0xFD0</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field> <name>bit[3_0]</name>
<description>jep106_c_code</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field> <name>bit[7_4]</name>
<description>block count</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
<resetValue>0x00000004</resetValue>
</register>
<register> <name>PIDR5</name>
<description>Peripheral ID 5</description>
<addressOffset>0xFD4</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field> <name>bit[3_0]</name>
<description>Part number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field> <name>bit[7_4]</name>
<description>jep106_id_3_0</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
<resetValue>0x0</resetValue>
</register>
<register> <name>PIDR6</name>
<description>Peripheral ID 6</description>
<addressOffset>0xFD8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>PIDR7</name>
<description>Peripheral ID 7</description>
<addressOffset>0xFDC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
</register>
<register> <name>PIDR0</name>
<description>Peripheral ID 0</description>
<addressOffset>0xFE0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000060</resetValue>
</register>
<register> <name>PIDR1</name>
<description>Peripheral ID 1</description>
<addressOffset>0xFE4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x000000B8</resetValue>
</register>
<register> <name>PIDR2</name>
<description>Peripheral ID 2</description>
<addressOffset>0xFE8</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field> <name>bit[3_0]</name>
<description>Part number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field> <name>bit[7_4]</name>
<description>jep106_id_3_0</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
<resetValue>0x0000000B</resetValue>
</register>
<register> <name>PIDR3</name>
<description>Peripheral ID 3</description>
<addressOffset>0xFEC</addressOffset>
<size>32</size>
<access>read-only</access>
<fields>
<field> <name>bit[3_0]</name>
<description>Customer modification number</description>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field> <name>bit[7_4]</name>
<description>ECO revision number</description>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
<resetValue>0x0</resetValue>
</register>
<register> <name>CIDR0</name>
<description>Component ID 0</description>
<addressOffset>0xFF0</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0000000D</resetValue>
</register>
<register> <name>CIDR1</name>
<description>Component ID 1</description>
<addressOffset>0xFF4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x000000F0</resetValue>
</register>
<register> <name>CIDR2</name>
<description>Component ID 2</description>
<addressOffset>0xFF8</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000005</resetValue>
</register>
<register> <name>CIDR3</name>
<description>Component ID 3</description>
<addressOffset>0xFFC</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x000000B1</resetValue>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="SRAM0MPC"> <name>SRAM1MPC</name>
<description>SRAM 1 Memory Protection Controller</description>
<groupName>SRAM_MPC</groupName>
<baseAddress>0x50084000</baseAddress>
</peripheral>
<peripheral derivedFrom="SRAM0MPC"> <name>SRAM2MPC</name>
<description>SRAM 2 Memory Protection Controller</description>
<groupName>SRAM_MPC</groupName>
<baseAddress>0x50085000</baseAddress>
</peripheral>
<peripheral derivedFrom="SRAM0MPC"> <name>SRAM3MPC</name>
<description>SRAM 3 Memory Protection Controller</description>
<groupName>SRAM_MPC</groupName>
<baseAddress>0x50086000</baseAddress>
</peripheral>
<peripheral derivedFrom="SRAM0MPC"> <name>CODE_SRAM_MPC</name>
<description>Code SRAM Memory Protection Controller</description>
<groupName>SRAM_MPC</groupName>
<baseAddress>0x52100000</baseAddress>
</peripheral>
<peripheral derivedFrom="SRAM0MPC"> <name>QSPI_MPC</name>
<description>QSPI Flash Memory Protection Controller</description>
<groupName>QSPI_MPC</groupName>
<baseAddress>0x52000000</baseAddress>
</peripheral>
<peripheral derivedFrom="SRAM0MPC"> <name>EFLASH0_MPC</name>
<description>EFlash0 Memory Protection Controller</description>
<groupName>EFLASH0_MPC</groupName>
<baseAddress>0x52200000</baseAddress>
</peripheral>
<peripheral derivedFrom="SRAM0MPC"> <name>EFLASH1_MPC</name>
<description>EFlash1 Memory Protection Controller</description>
<groupName>EFLASH1_MPC</groupName>
<baseAddress>0x52300000</baseAddress>
</peripheral>
<peripheral> <name>QSPIFCTRL</name>
<version>1.0</version>
<description>QSPI Flash Controller</description>
<groupName>QSPI</groupName>
<baseAddress>0x42800000</baseAddress>
<size>32</size>
<access>read-write</access>
<addressBlock>
<offset>0</offset>
<size>0xB0</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>QSPIINTR</name>
<description>QSPI interrupt</description>
<value>38</value>
</interrupt>
<registers>
<register>
<name>QSPICFG</name>
<description>QSPI Configuration Register</description>
<addressOffset>0x00</addressOffset>
<resetValue>0x80780081</resetValue>
<access>read-write</access>
<fields>
<field>
<name>PIPLIDLE</name>
<description>Serial Interface and QSPI pipeline is IDLE</description>
<bitRange>[31:31]</bitRange>
</field>
<field>
<name>PIPLPHYEN</name>
<description>Pipeline PHY Mode enable</description>
<bitRange>[25:25]</bitRange>
</field>
<field>
<name>DTREN</name>
<description>Enable DTR Protocol</description>
<bitRange>[24:24]</bitRange>
</field>
<field>
<name>AHBDECEN</name>
<description>Enable AHB Decoder</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>MAMOBRDIV</name>
<description>Master mode baud rate divisor (2 to 32)</description>
<bitRange>[22:19]</bitRange>
</field>
<field>
<name>ENTRXIPMODEIMM</name>
<description>Enter XIP Mode immediately</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>ENTRXIPMODEONR</name>
<description>Enter XIP Mode on next READ</description>
<bitRange>[17:17]</bitRange>
</field>
<field>
<name>ENAHBADDRRM</name>
<description>Enable AHB Address Re-mapping</description>
<bitRange>[16:16]</bitRange>
</field>
<field>
<name>ENDMAPIF</name>
<description>Enable DMA Peripheral Interface</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>WPPINDRV</name>
<description>Set to drive the WP pin of Flash device</description>
<bitRange>[14:14]</bitRange>
</field>
<field>
<name>PERCSLINES</name>
<description>Peripheral chip select lines</description>
<bitRange>[13:10]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>ss0</name>
<description>n_ss_out: 0b1110</description>
<value>0bxxx0</value>
</enumeratedValue>
<enumeratedValue>
<name>ss1</name>
<description>n_ss_out: 0b1101</description>
<value>0bxx01</value>
</enumeratedValue>
<enumeratedValue>
<name>ss2</name>
<description>n_ss_out: 0b1011</description>
<value>0bx011</value>
</enumeratedValue>
<enumeratedValue>
<name>ss3</name>
<description>n_ss_out: 0b0111</description>
<value>0b0111</value>
</enumeratedValue>
<enumeratedValue>
<name>ssinactive</name>
<description>n_ss_out: 0b1111 (no peripheral selected)</description>
<value>0b1111</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PERSELDEC</name>
<description>Peripheral select decode</description>
<bitRange>[9:9]</bitRange>
<enumeratedValues>
<enumeratedValue>
<name>Disabled</name>
<description>Only 1 of 4 selects n_ss_out is active</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enabled</name>
<description>Allow external 4-to-16 decode</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>LEGIPMODEEN</name>
<description>Legacy IP Mode Enable</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>ENDIRACCCTR</name>
<description>Enable Direct Access Controller</description>
<bitRange>[7:7]</bitRange>
</field>
<field>
<name>PHYMODEEN</name>
<description>PHY Mode enable</description>
<bitRange>[3:3]</bitRange>
</field>
<field>
<name>CLKPHASE</name>
<description>Clock phase, this maps to the standard SPI CPHA transfer format</description>
<bitRange>[2:2]</bitRange>
</field>
<field>
<name>CLKPOLARITY</name>
<description>Clock polarity outside SPI word. This maps to the standard SPI CPOL transfer format</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>QSPIEN</name>
<description>QSPI Enable</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>DEVREADINSTR</name>
<description>Device Read Instruction Register</description>
<addressOffset>0x04</addressOffset>
<resetValue>0x00000003</resetValue>
<access>read-write</access>
<fields>
<field>
<name>READDUMCLKCYCNUM</name>
<description>Number of Dummy Clock Cycles required by device for Read Instruction</description>
<bitRange>[28:24]</bitRange>
</field>
<field>
<name>MODEBITEN</name>
<description>Mode Bit Enable</description>
<bitRange>[20:20]</bitRange>
</field>
<field>
<name>DATATRTYPESSPI</name>
<description>Data Transfer Type for Standard SPI modes</description>
<bitRange>[17:16]</bitRange>
</field>
<field>
<name>ADDRTRTYPESSPI</name>
<description>Address Transfer Type for Standard SPI modes</description>
<bitRange>[13:12]</bitRange>
</field>
<field>
<name>DDRBITEN</name>
<description>DDR Bit Enable</description>
<bitRange>[10:10]</bitRange>
</field>
<field>
<name>INSTRTYPE</name>
<description>Instruction Type</description>
<bitRange>[9:8]</bitRange>
</field>
<field>
<name>ROPCODE</name>
<description>Read Opcode to use when not in XIP mode</description>
<bitRange>[7:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>DEVWRITEINSTR</name>
<description>Device Write Instruction Configuration Register</description>
<addressOffset>0x08</addressOffset>
<resetValue>0x00000002</resetValue>
<access>read-write</access>
<fields>
<field>
<name>WRITEDUMCLKCYCNUM</name>
<description>Number of Dummy Clock Cycles required by device for Write Instruction</description>
<bitRange>[28:24]</bitRange>
</field>
<field>
<name>DATATRTYPESSPI</name>
<description>Data Transfer Type for Standard SPI modes</description>
<bitRange>[17:16]</bitRange>
</field>
<field>
<name>ADDRTRTYPESSPI</name>
<description>Address Transfer Type for Standard SPI modes</description>
<bitRange>[13:12]</bitRange>
</field>
<field>
<name>WELDISABLE</name>
<description>WEL Disable</description>
<bitRange>[8:8]</bitRange>
</field>
<field>
<name>WROPCODE</name>
<description>Write Opcode</description>
<bitRange>[7:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>DEVSIZE</name>
<description>Device Size Configuration Register</description>
<addressOffset>0x14</addressOffset>
<resetValue>0X00101002</resetValue>
<access>read-write</access>
<fields>
<field>
<name>FDEVSIZECS3</name>
<description>Size of Flash Device connected to CS[3] pin</description>
<bitRange>[28:27]</bitRange>
</field>
<field>
<name>FDEVSIZECS2</name>
<description>Size of Flash Device connected to CS[2] pin</description>
<bitRange>[26:25]</bitRange>
</field>
<field>
<name>FDEVSIZECS1</name>
<description>Size of Flash Device connected to CS[1] pin</description>
<bitRange>[24:23]</bitRange>
</field>
<field>
<name>FDEVSIZECS0</name>
<description>Size of Flash Device connected to CS[0] pin</description>
<bitRange>[22:21]</bitRange>
</field>
<field>
<name>BYTEPERBLKNUM</name>
<description>Number of bytes per block</description>
<bitRange>[20:16]</bitRange>
</field>
<field>
<name>BYTEPERDEVPGNUM</name>
<description>Number of bytes per device page</description>
<bitRange>[15:4]</bitRange>
</field>
<field>
<name>ADDRBYTENUM</name>
<description>Number of address bytes</description>
<bitRange>[3:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>REMAPADDR</name>
<description>Remap Address Register</description>
<addressOffset>0x24</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-write</access>
</register>
<register>
<name>FLASHCMDCTRL</name>
<description>Flash Command Control Register</description>
<addressOffset>0x90</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-write</access>
<fields>
<field>
<name>CMDOPCODE</name>
<description>Command Opcode</description>
<bitRange>[31:24]</bitRange>
</field>
<field>
<name>RDATAEN</name>
<description>Read Data Enable</description>
<bitRange>[23:23]</bitRange>
</field>
<field>
<name>RDATABYTENUM</name>
<description>Number of Read Data Bytes</description>
<bitRange>[22:20]</bitRange>
</field>
<field>
<name>CMDADDREN</name>
<description>Command Address Enable</description>
<bitRange>[19:19]</bitRange>
</field>
<field>
<name>MODEBITEN</name>
<description>Mode Bit Enable</description>
<bitRange>[18:18]</bitRange>
</field>
<field>
<name>ADDRBYTENUM</name>
<description>Number of Address Bytes</description>
<bitRange>[17:16]</bitRange>
</field>
<field>
<name>WRDATAEN</name>
<description>Write Data Enable</description>
<bitRange>[15:15]</bitRange>
</field>
<field>
<name>WRDATABYTENUM</name>
<description>Number of Write Data Bytes</description>
<bitRange>[14:12]</bitRange>
</field>
<field>
<name>DUMCYCNUM</name>
<description>Number of Dummy Cycles</description>
<bitRange>[11:7]</bitRange>
</field>
<field>
<name>CMDEXINPROG</name>
<description>Command execution in progress</description>
<bitRange>[1:1]</bitRange>
</field>
<field>
<name>CMDEXEC</name>
<description>Execute the command</description>
<bitRange>[0:0]</bitRange>
</field>
</fields>
</register>
<register>
<name>FLASHCMDADDR</name>
<description>Flash Command Address Register</description>
<addressOffset>0x94</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-write</access>
</register>
<register>
<name>FLASHCMDRDATALOW</name>
<description>Flash Command Read Data Register (Lower)</description>
<addressOffset>0xA0</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-only</access>
</register>
<register>
<name>FLASHCMDRDATAUP</name>
<description>Flash Command Read Data Register (Upper)</description>
<addressOffset>0xA4</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-only</access>
</register>
<register>
<name>FLASHCMDWRDATALOW</name>
<description>Flash Command Write Data Register (Lower)</description>
<addressOffset>0xA8</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-write</access>
</register>
<register>
<name>FLASHCMDWRDATAUP</name>
<description>Flash Command Write Data Register (Upper)</description>
<addressOffset>0xAC</addressOffset>
<resetValue>0x00000000</resetValue>
<access>read-write</access>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="QSPIFCTRL"> <name>QSPIFCTRL_Secure</name>
<description>QSPI Flash Controller (Secure)</description>
<groupName>QSPI (Secure)</groupName>
<baseAddress>0x52800000</baseAddress>
</peripheral>
</peripherals>
</device>