Expand description
Peripheral access API for MUSCA_B1 microcontrollers (generated using svd2rust v0.35.0 ( ))
You can find an overview of the generated API here.
API features to be included in the next
svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.
Re-exports§
pub use self::sysinfo as sysinfo_secure;pub use self::timer0 as timer0_secure;pub use self::dualtimer as dualtimer_secure;pub use self::gptimer as gptimer_secure;pub use self::gpio0 as gpio0_secure;pub use self::uart0 as uart0_secure;pub use self::watchdog as watchdog_secure;pub use self::watchdog as s32kwatchdog;pub use self::sram0mpc as sram1mpc;pub use self::sram0mpc as sram2mpc;pub use self::sram0mpc as sram3mpc;pub use self::sram0mpc as code_sram_mpc;pub use self::sram0mpc as qspi_mpc;pub use self::sram0mpc as eflash0_mpc;pub use self::sram0mpc as eflash1_mpc;pub use self::qspifctrl as qspifctrl_secure;pub use self::mhu0 as mhu0_secure;pub use self::mhu0 as mhu1;pub use self::mhu0 as mhu1_secure;
Modules§
- cpu_
identity - CPU Identity
- dualtimer
- Dual Timer
- generic
- Common register and bit access and modify traits
- gpio0
- General-purpose I/O 0
- gptimer
- General-Purpose Timer
- i_cache
- Cache
- mhu0
- Message Handling Unit 0
- nspctrl
- Non-secure Privilege Control Block
- pwm
- PWM_IP6512
- qspifctrl
- QSPI Flash Controller
- sau
- Security Attribution Unit
- scc
- Serial Communication Controller
- spctrl
- Secure Privilege Control Block
- sram0mpc
- Memory Protection Controller 0
- sysinfo
- System Information
- system_
control - System Control
- timer0
- Timer 0
- uart0
- UART 0
- watchdog
- Non-secure Watchdog Timer
Structs§
- Code
Sram Mpc - Code SRAM Memory Protection Controller
- CpuIdentity
- CPU Identity
- Dualtimer
- Dual Timer
- Dualtimer
Secure - Dual Timer (Secure)
- Eflash0
Mpc - EFlash0 Memory Protection Controller
- Eflash1
Mpc - EFlash1 Memory Protection Controller
- Gpio0
- General-purpose I/O 0
- Gpio0
Secure - General-purpose I/O 0 (Secure)
- Gptimer
- General-Purpose Timer
- Gptimer
Secure - General-Purpose Timer (Secure)
- ICache
- Cache
- Mhu0
- Message Handling Unit 0
- Mhu0
Secure - Message Handling Unit 0 (Secure)
- Mhu1
- Message Handling Unit 1
- Mhu1
Secure - Message Handling Unit 1 (Secure)
- Nspctrl
- Non-secure Privilege Control Block
- Peripherals
- All the peripherals.
- Pwm
- PWM_IP6512
- QspiMpc
- QSPI Flash Memory Protection Controller
- Qspifctrl
- QSPI Flash Controller
- Qspifctrl
Secure - QSPI Flash Controller (Secure)
- S32kwatchdog
- S32K Watchdog (Secure)
- Sau
- Security Attribution Unit
- Scc
- Serial Communication Controller
- Spctrl
- Secure Privilege Control Block
- Sram0mpc
- Memory Protection Controller 0
- Sram1mpc
- SRAM 1 Memory Protection Controller
- Sram2mpc
- SRAM 2 Memory Protection Controller
- Sram3mpc
- SRAM 3 Memory Protection Controller
- Sysinfo
- System Information
- Sysinfo
Secure - System Information (Secure)
- System
Control - System Control
- Timer0
- Timer 0
- Timer0
Secure - Timer 0 (Secure)
- Uart0
- UART 0
- Uart0
Secure - UART 0 (Secure)
- Watchdog
- Non-secure Watchdog Timer
- Watchdog
Secure - Watchdog (Secure)
Enums§
- Interrupt
- Enumeration of all the interrupts.
Constants§
- NVIC_
PRIO_ BITS - Number available in the NVIC for configuring priority