mspm0l130x/i2c0/

int_event1_iset.rs

# [doc = "Register `INT_EVENT1_ISET` writer"] pub type W = crate :: W < INT_EVENT1_ISET_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"] pub type INT_EVENT1_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MRXFIFOTRG_AW :: INT_EVENT1_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MRXFIFOTRG_AW :: INT_EVENT1_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"] pub type INT_EVENT1_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MTXFIFOTRG_AW :: INT_EVENT1_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MTXFIFOTRG_AW :: INT_EVENT1_ISET_MTXFIFOTRG_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"] pub type INT_EVENT1_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_SRXFIFOTRG_AW :: INT_EVENT1_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_SRXFIFOTRG_AW :: INT_EVENT1_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum INT_EVENT1_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"] INT_EVENT1_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"] INT_EVENT1_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_STXFIFOTRG_AW > for bool { # [inline (always)] fn from (variant : INT_EVENT1_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"] pub type INT_EVENT1_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"] # [inline (always)] pub fn int_event1_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_STXFIFOTRG_AW :: INT_EVENT1_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"] # [inline (always)] pub fn int_event1_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_STXFIFOTRG_AW :: INT_EVENT1_ISET_STXFIFOTRG_SET) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iset_mrxfifotrg (& mut self) -> INT_EVENT1_ISET_MRXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 0 > { INT_EVENT1_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"] # [inline (always)] # [must_use] pub fn int_event1_iset_mtxfifotrg (& mut self) -> INT_EVENT1_ISET_MTXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 1 > { INT_EVENT1_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iset_srxfifotrg (& mut self) -> INT_EVENT1_ISET_SRXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 2 > { INT_EVENT1_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"] # [inline (always)] # [must_use] pub fn int_event1_iset_stxfifotrg (& mut self) -> INT_EVENT1_ISET_STXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 3 > { INT_EVENT1_ISET_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct INT_EVENT1_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iset::W`](W) writer structure"] impl crate :: Writable for INT_EVENT1_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ISET to value 0"] impl crate :: Resettable for INT_EVENT1_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }