mspm0l130x/timg2/
clksel.rs1# [doc = "Register `CLKSEL` reader"] pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"] pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"] pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"] pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUSCLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUSCLK as clock source if enabled\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"] CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"] CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)] fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"] # [inline (always)] pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUSCLK as clock source if enabled"] pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"] # [inline (always)] pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"] # [inline (always)] pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"] # [inline (always)] pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"] # [inline (always)] # [must_use] pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"] impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"] impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"] impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }