1# [doc = "Register `MSA` reader"] pub type R = crate :: R < MSA_SPEC > ; # [doc = "Register `MSA` writer"] pub type W = crate :: W < MSA_SPEC > ; # [doc = "Field `MSA_DIR` reader - Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive"] pub type MSA_DIR_R = crate :: BitReader < MSA_DIR_A > ; # [doc = "Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MSA_DIR_A { # [doc = "0: TRANSMIT"] MSA_DIR_TRANSMIT = 0 , # [doc = "1: RECEIVE"] MSA_DIR_RECEIVE = 1 , } impl From < MSA_DIR_A > for bool { # [inline (always)] fn from (variant : MSA_DIR_A) -> Self { variant as u8 != 0 } } impl MSA_DIR_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MSA_DIR_A { match self . bits { false => MSA_DIR_A :: MSA_DIR_TRANSMIT , true => MSA_DIR_A :: MSA_DIR_RECEIVE , } } # [doc = "TRANSMIT"] # [inline (always)] pub fn is_msa_dir_transmit (& self) -> bool { * self == MSA_DIR_A :: MSA_DIR_TRANSMIT } # [doc = "RECEIVE"] # [inline (always)] pub fn is_msa_dir_receive (& self) -> bool { * self == MSA_DIR_A :: MSA_DIR_RECEIVE } } # [doc = "Field `MSA_DIR` writer - Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive"] pub type MSA_DIR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MSA_DIR_A > ; impl < 'a , REG , const O : u8 > MSA_DIR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TRANSMIT"] # [inline (always)] pub fn msa_dir_transmit (self) -> & 'a mut crate :: W < REG > { self . variant (MSA_DIR_A :: MSA_DIR_TRANSMIT) } # [doc = "RECEIVE"] # [inline (always)] pub fn msa_dir_receive (self) -> & 'a mut crate :: W < REG > { self . variant (MSA_DIR_A :: MSA_DIR_RECEIVE) } } # [doc = "Field `MSA_SADDR` reader - I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care"] pub type MSA_SADDR_R = crate :: FieldReader < u16 > ; # [doc = "Field `MSA_SADDR` writer - I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care"] pub type MSA_SADDR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 10 , O , u16 > ; # [doc = "Field `MSA_MMODE` reader - This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] pub type MSA_MMODE_R = crate :: BitReader < MSA_MMODE_A > ; # [doc = "This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum MSA_MMODE_A { # [doc = "0: MODE7"] MSA_MMODE_MODE7 = 0 , # [doc = "1: MODE10"] MSA_MMODE_MODE10 = 1 , } impl From < MSA_MMODE_A > for bool { # [inline (always)] fn from (variant : MSA_MMODE_A) -> Self { variant as u8 != 0 } } impl MSA_MMODE_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> MSA_MMODE_A { match self . bits { false => MSA_MMODE_A :: MSA_MMODE_MODE7 , true => MSA_MMODE_A :: MSA_MMODE_MODE10 , } } # [doc = "MODE7"] # [inline (always)] pub fn is_msa_mmode_mode7 (& self) -> bool { * self == MSA_MMODE_A :: MSA_MMODE_MODE7 } # [doc = "MODE10"] # [inline (always)] pub fn is_msa_mmode_mode10 (& self) -> bool { * self == MSA_MMODE_A :: MSA_MMODE_MODE10 } } # [doc = "Field `MSA_MMODE` writer - This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] pub type MSA_MMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MSA_MMODE_A > ; impl < 'a , REG , const O : u8 > MSA_MMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "MODE7"] # [inline (always)] pub fn msa_mmode_mode7 (self) -> & 'a mut crate :: W < REG > { self . variant (MSA_MMODE_A :: MSA_MMODE_MODE7) } # [doc = "MODE10"] # [inline (always)] pub fn msa_mmode_mode10 (self) -> & 'a mut crate :: W < REG > { self . variant (MSA_MMODE_A :: MSA_MMODE_MODE10) } } impl R { # [doc = "Bit 0 - Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive"] # [inline (always)] pub fn msa_dir (& self) -> MSA_DIR_R { MSA_DIR_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:10 - I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care"] # [inline (always)] pub fn msa_saddr (& self) -> MSA_SADDR_R { MSA_SADDR_R :: new (((self . bits >> 1) & 0x03ff) as u16) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] # [inline (always)] pub fn msa_mmode (& self) -> MSA_MMODE_R { MSA_MMODE_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bit 0 - Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive"] # [inline (always)] # [must_use] pub fn msa_dir (& mut self) -> MSA_DIR_W < MSA_SPEC , 0 > { MSA_DIR_W :: new (self) } # [doc = "Bits 1:10 - I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care"] # [inline (always)] # [must_use] pub fn msa_saddr (& mut self) -> MSA_SADDR_W < MSA_SPEC , 1 > { MSA_SADDR_W :: new (self) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."] # [inline (always)] # [must_use] pub fn msa_mmode (& mut self) -> MSA_MMODE_W < MSA_SPEC , 15 > { MSA_MMODE_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Slave Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msa::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msa::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MSA_SPEC ; impl crate :: RegisterSpec for MSA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`msa::R`](R) reader structure"] impl crate :: Readable for MSA_SPEC { } # [doc = "`write(|w| ..)` method takes [`msa::W`](W) writer structure"] impl crate :: Writable for MSA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MSA to value 0"] impl crate :: Resettable for MSA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }