mspm0l130x/timg0/
cclkctl.rs1# [doc = "Register `CCLKCTL` reader"] pub type R = crate :: R < CCLKCTL_SPEC > ; # [doc = "Register `CCLKCTL` writer"] pub type W = crate :: W < CCLKCTL_SPEC > ; # [doc = "Field `CCLKCTL_CLKEN` reader - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."] pub type CCLKCTL_CLKEN_R = crate :: BitReader < CCLKCTL_CLKEN_A > ; # [doc = "Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock.\n\nValue on reset: 0"] # [derive (Clone , Copy , Debug , PartialEq , Eq)] pub enum CCLKCTL_CLKEN_A { # [doc = "0: DISABLED"] CCLKCTL_CLKEN_DISABLED = 0 , # [doc = "1: ENABLED"] CCLKCTL_CLKEN_ENABLED = 1 , } impl From < CCLKCTL_CLKEN_A > for bool { # [inline (always)] fn from (variant : CCLKCTL_CLKEN_A) -> Self { variant as u8 != 0 } } impl CCLKCTL_CLKEN_R { # [doc = "Get enumerated values variant"] # [inline (always)] pub const fn variant (& self) -> CCLKCTL_CLKEN_A { match self . bits { false => CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_DISABLED , true => CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_ENABLED , } } # [doc = "DISABLED"] # [inline (always)] pub fn is_cclkctl_clken_disabled (& self) -> bool { * self == CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_DISABLED } # [doc = "ENABLED"] # [inline (always)] pub fn is_cclkctl_clken_enabled (& self) -> bool { * self == CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_ENABLED } } # [doc = "Field `CCLKCTL_CLKEN` writer - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."] pub type CCLKCTL_CLKEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCLKCTL_CLKEN_A > ; impl < 'a , REG , const O : u8 > CCLKCTL_CLKEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"] # [inline (always)] pub fn cclkctl_clken_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_DISABLED) } # [doc = "ENABLED"] # [inline (always)] pub fn cclkctl_clken_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_ENABLED) } } impl R { # [doc = "Bit 0 - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."] # [inline (always)] pub fn cclkctl_clken (& self) -> CCLKCTL_CLKEN_R { CCLKCTL_CLKEN_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."] # [inline (always)] # [must_use] pub fn cclkctl_clken (& mut self) -> CCLKCTL_CLKEN_W < CCLKCTL_SPEC , 0 > { CCLKCTL_CLKEN_W :: new (self) } # [doc = r" Writes raw bits to the register."] # [doc = r""] # [doc = r" # Safety"] # [doc = r""] # [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] # [inline (always)] pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Counter Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cclkctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cclkctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCLKCTL_SPEC ; impl crate :: RegisterSpec for CCLKCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cclkctl::R`](R) reader structure"] impl crate :: Readable for CCLKCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`cclkctl::W`](W) writer structure"] impl crate :: Writable for CCLKCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCLKCTL to value 0"] impl crate :: Resettable for CCLKCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; }