Enum msp432p401r::dma::dma_enaclr::CLR_AW

#[repr(u32)]pub enum CLR_AW {
    CLR_0,
    CLR_1,
}

Set the appropriate bit to disable the corresponding DMA channel. Note: The controller disables a channel, by setting the appropriate bit, when: a) it completes the DMA cycle b) it reads a channel_cfg memory location which has cycle_ctrl = b000 c) an ERROR occurs on the AHB-Lite bus.

Value on reset: 0

Variants

CLR_0

0: No effect. Use the DMA_ENASET Register to enable DMA channels.

CLR_1

1: Disables channel C. Writing to a bit where a DMA channel is not implemented has no effect.

Trait Implementations

impl Clone for CLR_AW

fn clone(&self) -> CLR_AW

Returns a copy of the value.

pub fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for CLR_AW

impl Debug for CLR_AW

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq<CLR_AW> for CLR_AW

fn eq(&self, other: &CLR_AW) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]pub fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl StructuralPartialEq for CLR_AW