Module msp432p401r::dma::dma_enaclr

Channel Enable Clear Register

Structs

CLR_W	Field CLR writer - Set the appropriate bit to disable the corresponding DMA channel. Note: The controller disables a channel, by setting the appropriate bit, when: a) it completes the DMA cycle b) it reads a channel_cfg memory location which has cycle_ctrl = b000 c) an ERROR occurs on the AHB-Lite bus.
DMA_ENACLR_SPEC	Channel Enable Clear Register
W	Register DMA_ENACLR writer

Enums

CLR_AW

Set the appropriate bit to disable the corresponding DMA channel. Note: The controller disables a channel, by setting the appropriate bit, when: a) it completes the DMA cycle b) it reads a channel_cfg memory location which has cycle_ctrl = b000 c) an ERROR occurs on the AHB-Lite bus.