msp432e4/sysctl/
rcgcadc.rs

1#[doc = r"Value read from the register"]
2pub struct R {
3    bits: u32,
4}
5#[doc = r"Value to write to the register"]
6pub struct W {
7    bits: u32,
8}
9impl super::RCGCADC {
10    #[doc = r"Modifies the contents of the register"]
11    #[inline(always)]
12    pub fn modify<F>(&self, f: F)
13    where
14        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15    {
16        let bits = self.register.get();
17        self.register.set(f(&R { bits }, &mut W { bits }).bits);
18    }
19    #[doc = r"Reads the contents of the register"]
20    #[inline(always)]
21    pub fn read(&self) -> R {
22        R {
23            bits: self.register.get(),
24        }
25    }
26    #[doc = r"Writes to the register"]
27    #[inline(always)]
28    pub fn write<F>(&self, f: F)
29    where
30        F: FnOnce(&mut W) -> &mut W,
31    {
32        self.register.set(
33            f(&mut W {
34                bits: Self::reset_value(),
35            })
36            .bits,
37        );
38    }
39    #[doc = r"Reset value of the register"]
40    #[inline(always)]
41    pub const fn reset_value() -> u32 {
42        0
43    }
44    #[doc = r"Writes the reset value to the register"]
45    #[inline(always)]
46    pub fn reset(&self) {
47        self.register.set(Self::reset_value())
48    }
49}
50#[doc = r"Value of the field"]
51pub struct SYSCTL_RCGCADC_R0R {
52    bits: bool,
53}
54impl SYSCTL_RCGCADC_R0R {
55    #[doc = r"Value of the field as raw bits"]
56    #[inline(always)]
57    pub fn bit(&self) -> bool {
58        self.bits
59    }
60    #[doc = r"Returns `true` if the bit is clear (0)"]
61    #[inline(always)]
62    pub fn bit_is_clear(&self) -> bool {
63        !self.bit()
64    }
65    #[doc = r"Returns `true` if the bit is set (1)"]
66    #[inline(always)]
67    pub fn bit_is_set(&self) -> bool {
68        self.bit()
69    }
70}
71#[doc = r"Proxy"]
72pub struct _SYSCTL_RCGCADC_R0W<'a> {
73    w: &'a mut W,
74}
75impl<'a> _SYSCTL_RCGCADC_R0W<'a> {
76    #[doc = r"Sets the field bit"]
77    #[inline(always)]
78    pub fn set_bit(self) -> &'a mut W {
79        self.bit(true)
80    }
81    #[doc = r"Clears the field bit"]
82    #[inline(always)]
83    pub fn clear_bit(self) -> &'a mut W {
84        self.bit(false)
85    }
86    #[doc = r"Writes raw bits to the field"]
87    #[inline(always)]
88    pub fn bit(self, value: bool) -> &'a mut W {
89        self.w.bits &= !(1 << 0);
90        self.w.bits |= ((value as u32) & 1) << 0;
91        self.w
92    }
93}
94#[doc = r"Value of the field"]
95pub struct SYSCTL_RCGCADC_R1R {
96    bits: bool,
97}
98impl SYSCTL_RCGCADC_R1R {
99    #[doc = r"Value of the field as raw bits"]
100    #[inline(always)]
101    pub fn bit(&self) -> bool {
102        self.bits
103    }
104    #[doc = r"Returns `true` if the bit is clear (0)"]
105    #[inline(always)]
106    pub fn bit_is_clear(&self) -> bool {
107        !self.bit()
108    }
109    #[doc = r"Returns `true` if the bit is set (1)"]
110    #[inline(always)]
111    pub fn bit_is_set(&self) -> bool {
112        self.bit()
113    }
114}
115#[doc = r"Proxy"]
116pub struct _SYSCTL_RCGCADC_R1W<'a> {
117    w: &'a mut W,
118}
119impl<'a> _SYSCTL_RCGCADC_R1W<'a> {
120    #[doc = r"Sets the field bit"]
121    #[inline(always)]
122    pub fn set_bit(self) -> &'a mut W {
123        self.bit(true)
124    }
125    #[doc = r"Clears the field bit"]
126    #[inline(always)]
127    pub fn clear_bit(self) -> &'a mut W {
128        self.bit(false)
129    }
130    #[doc = r"Writes raw bits to the field"]
131    #[inline(always)]
132    pub fn bit(self, value: bool) -> &'a mut W {
133        self.w.bits &= !(1 << 1);
134        self.w.bits |= ((value as u32) & 1) << 1;
135        self.w
136    }
137}
138impl R {
139    #[doc = r"Value of the register as raw bits"]
140    #[inline(always)]
141    pub fn bits(&self) -> u32 {
142        self.bits
143    }
144    #[doc = "Bit 0 - ADC Module 0 Run Mode Clock Gating Control"]
145    #[inline(always)]
146    pub fn sysctl_rcgcadc_r0(&self) -> SYSCTL_RCGCADC_R0R {
147        let bits = ((self.bits >> 0) & 1) != 0;
148        SYSCTL_RCGCADC_R0R { bits }
149    }
150    #[doc = "Bit 1 - ADC Module 1 Run Mode Clock Gating Control"]
151    #[inline(always)]
152    pub fn sysctl_rcgcadc_r1(&self) -> SYSCTL_RCGCADC_R1R {
153        let bits = ((self.bits >> 1) & 1) != 0;
154        SYSCTL_RCGCADC_R1R { bits }
155    }
156}
157impl W {
158    #[doc = r"Writes raw bits to the register"]
159    #[inline(always)]
160    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
161        self.bits = bits;
162        self
163    }
164    #[doc = "Bit 0 - ADC Module 0 Run Mode Clock Gating Control"]
165    #[inline(always)]
166    pub fn sysctl_rcgcadc_r0(&mut self) -> _SYSCTL_RCGCADC_R0W {
167        _SYSCTL_RCGCADC_R0W { w: self }
168    }
169    #[doc = "Bit 1 - ADC Module 1 Run Mode Clock Gating Control"]
170    #[inline(always)]
171    pub fn sysctl_rcgcadc_r1(&mut self) -> _SYSCTL_RCGCADC_R1W {
172        _SYSCTL_RCGCADC_R1W { w: self }
173    }
174}
msp432e4/sysctl/rcgcadc.rs

msp432e4/sysctl/
rcgcadc.rs
