msp430g2231/port_1_2/
p1ifg.rs

1#[doc = "Register `P1IFG` reader"]
2pub type R = crate::R<P1IFG_SPEC>;
3#[doc = "Register `P1IFG` writer"]
4pub type W = crate::W<P1IFG_SPEC>;
5#[doc = "Field `P0` reader - P0"]
6pub type P0_R = crate::BitReader;
7#[doc = "Field `P0` writer - P0"]
8pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
9#[doc = "Field `P1IFG` reader - Port 1 Interrupt Flag register"]
10pub type P1IFG_R = crate::FieldReader;
11#[doc = "Field `P1IFG` writer - Port 1 Interrupt Flag register"]
12pub type P1IFG_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 8, O>;
13#[doc = "Field `P1` reader - P1"]
14pub type P1_R = crate::BitReader;
15#[doc = "Field `P1` writer - P1"]
16pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
17#[doc = "Field `P2` reader - P2"]
18pub type P2_R = crate::BitReader;
19#[doc = "Field `P2` writer - P2"]
20pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
21#[doc = "Field `P3` reader - P3"]
22pub type P3_R = crate::BitReader;
23#[doc = "Field `P3` writer - P3"]
24pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
25#[doc = "Field `P4` reader - P4"]
26pub type P4_R = crate::BitReader;
27#[doc = "Field `P4` writer - P4"]
28pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
29#[doc = "Field `P5` reader - P5"]
30pub type P5_R = crate::BitReader;
31#[doc = "Field `P5` writer - P5"]
32pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
33#[doc = "Field `P6` reader - P6"]
34pub type P6_R = crate::BitReader;
35#[doc = "Field `P6` writer - P6"]
36pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
37#[doc = "Field `P7` reader - P7"]
38pub type P7_R = crate::BitReader;
39#[doc = "Field `P7` writer - P7"]
40pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
41impl R {
42    #[doc = "Bit 0 - P0"]
43    #[inline(always)]
44    pub fn p0(&self) -> P0_R {
45        P0_R::new((self.bits & 1) != 0)
46    }
47    #[doc = "Bits 0:7 - Port 1 Interrupt Flag register"]
48    #[inline(always)]
49    pub fn p1ifg(&self) -> P1IFG_R {
50        P1IFG_R::new(self.bits)
51    }
52    #[doc = "Bit 1 - P1"]
53    #[inline(always)]
54    pub fn p1(&self) -> P1_R {
55        P1_R::new(((self.bits >> 1) & 1) != 0)
56    }
57    #[doc = "Bit 2 - P2"]
58    #[inline(always)]
59    pub fn p2(&self) -> P2_R {
60        P2_R::new(((self.bits >> 2) & 1) != 0)
61    }
62    #[doc = "Bit 3 - P3"]
63    #[inline(always)]
64    pub fn p3(&self) -> P3_R {
65        P3_R::new(((self.bits >> 3) & 1) != 0)
66    }
67    #[doc = "Bit 4 - P4"]
68    #[inline(always)]
69    pub fn p4(&self) -> P4_R {
70        P4_R::new(((self.bits >> 4) & 1) != 0)
71    }
72    #[doc = "Bit 5 - P5"]
73    #[inline(always)]
74    pub fn p5(&self) -> P5_R {
75        P5_R::new(((self.bits >> 5) & 1) != 0)
76    }
77    #[doc = "Bit 6 - P6"]
78    #[inline(always)]
79    pub fn p6(&self) -> P6_R {
80        P6_R::new(((self.bits >> 6) & 1) != 0)
81    }
82    #[doc = "Bit 7 - P7"]
83    #[inline(always)]
84    pub fn p7(&self) -> P7_R {
85        P7_R::new(((self.bits >> 7) & 1) != 0)
86    }
87}
88impl W {
89    #[doc = "Bit 0 - P0"]
90    #[inline(always)]
91    #[must_use]
92    pub fn p0(&mut self) -> P0_W<P1IFG_SPEC, 0> {
93        P0_W::new(self)
94    }
95    #[doc = "Bits 0:7 - Port 1 Interrupt Flag register"]
96    #[inline(always)]
97    #[must_use]
98    pub fn p1ifg(&mut self) -> P1IFG_W<P1IFG_SPEC, 0> {
99        P1IFG_W::new(self)
100    }
101    #[doc = "Bit 1 - P1"]
102    #[inline(always)]
103    #[must_use]
104    pub fn p1(&mut self) -> P1_W<P1IFG_SPEC, 1> {
105        P1_W::new(self)
106    }
107    #[doc = "Bit 2 - P2"]
108    #[inline(always)]
109    #[must_use]
110    pub fn p2(&mut self) -> P2_W<P1IFG_SPEC, 2> {
111        P2_W::new(self)
112    }
113    #[doc = "Bit 3 - P3"]
114    #[inline(always)]
115    #[must_use]
116    pub fn p3(&mut self) -> P3_W<P1IFG_SPEC, 3> {
117        P3_W::new(self)
118    }
119    #[doc = "Bit 4 - P4"]
120    #[inline(always)]
121    #[must_use]
122    pub fn p4(&mut self) -> P4_W<P1IFG_SPEC, 4> {
123        P4_W::new(self)
124    }
125    #[doc = "Bit 5 - P5"]
126    #[inline(always)]
127    #[must_use]
128    pub fn p5(&mut self) -> P5_W<P1IFG_SPEC, 5> {
129        P5_W::new(self)
130    }
131    #[doc = "Bit 6 - P6"]
132    #[inline(always)]
133    #[must_use]
134    pub fn p6(&mut self) -> P6_W<P1IFG_SPEC, 6> {
135        P6_W::new(self)
136    }
137    #[doc = "Bit 7 - P7"]
138    #[inline(always)]
139    #[must_use]
140    pub fn p7(&mut self) -> P7_W<P1IFG_SPEC, 7> {
141        P7_W::new(self)
142    }
143    #[doc = "Writes raw bits to the register."]
144    #[inline(always)]
145    pub fn bits(&mut self, bits: u8) -> &mut Self {
146        self.bits = bits;
147        self
148    }
149}
150#[doc = "Port 1 Interrupt Flag\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`p1ifg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`p1ifg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
151pub struct P1IFG_SPEC;
152impl crate::RegisterSpec for P1IFG_SPEC {
153    type Ux = u8;
154}
155#[doc = "`read()` method returns [`p1ifg::R`](R) reader structure"]
156impl crate::Readable for P1IFG_SPEC {}
157#[doc = "`write(|w| ..)` method takes [`p1ifg::W`](W) writer structure"]
158impl crate::Writable for P1IFG_SPEC {
159    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
160    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
161}
162#[doc = "`reset()` method sets P1IFG to value 0"]
163impl crate::Resettable for P1IFG_SPEC {
164    const RESET_VALUE: Self::Ux = 0;
165}
msp430g2231/port_1_2/p1ifg.rs

msp430g2231/port_1_2/
p1ifg.rs
