#![cfg_attr(feature = "rt", feature(abi_msp430_interrupt))]
#![doc = "Peripheral access API for MSP430FR5969 microcontrollers (generated using svd2rust v0.37.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
#![allow(non_camel_case_types)]
#![allow(non_snake_case)]
#![no_std]
#![cfg_attr(docsrs, feature(doc_cfg))]
#[allow(unused_imports)]
use generic::*;
#[doc = r"Common register and bit access and modify traits"]
pub mod generic {
use core::marker;
#[doc = " Generic peripheral accessor"]
pub struct Periph<RB, const A: usize> {
_marker: marker::PhantomData<RB>,
}
unsafe impl<RB, const A: usize> Send for Periph<RB, A> {}
impl<RB, const A: usize> Periph<RB, A> {
#[doc = "Pointer to the register block"]
pub const PTR: *const RB = A as *const _;
#[doc = "Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const RB {
Self::PTR
}
#[doc = " Steal an instance of this peripheral"]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = " that may race with any existing instances, for example by only"]
#[doc = " accessing read-only or write-only registers, or by consuming the"]
#[doc = " original peripheral and using critical sections to coordinate"]
#[doc = " access between multiple new instances."]
#[doc = ""]
#[doc = " Additionally, other software such as HALs may rely on only one"]
#[doc = " peripheral instance existing to ensure memory safety; ensure"]
#[doc = " no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: marker::PhantomData,
}
}
}
impl<RB, const A: usize> core::ops::Deref for Periph<RB, A> {
type Target = RB;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"]
pub trait RawReg:
Copy
+ From<bool>
+ core::ops::BitOr<Output = Self>
+ core::ops::BitAnd<Output = Self>
+ core::ops::BitOrAssign
+ core::ops::BitAndAssign
+ core::ops::Not<Output = Self>
+ core::ops::Shl<u8, Output = Self>
{
#[doc = " Mask for bits of width `WI`"]
fn mask<const WI: u8>() -> Self;
#[doc = " `0`"]
const ZERO: Self;
#[doc = " `1`"]
const ONE: Self;
}
macro_rules! raw_reg {
($ U : ty , $ size : literal , $ mask : ident) => {
impl RawReg for $U {
#[inline(always)]
fn mask<const WI: u8>() -> Self {
$mask::<WI>()
}
const ZERO: Self = 0;
const ONE: Self = 1;
}
const fn $mask<const WI: u8>() -> $U {
<$U>::MAX >> ($size - WI)
}
impl FieldSpec for $U {
type Ux = $U;
}
};
}
raw_reg!(u8, 8, mask_u8);
raw_reg!(u16, 16, mask_u16);
raw_reg!(u32, 32, mask_u32);
raw_reg!(u64, 64, mask_u64);
#[doc = " Raw register type"]
pub trait RegisterSpec {
#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."]
type Ux: RawReg;
}
#[doc = " Raw field type"]
pub trait FieldSpec: Sized {
#[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
}
#[doc = " Marker for fields with fixed values"]
pub trait IsEnum: FieldSpec {}
#[doc = " Trait implemented by readable registers to enable the `read` method."]
#[doc = ""]
#[doc = " Registers marked with `Writable` can be also be `modify`'ed."]
pub trait Readable: RegisterSpec {}
#[doc = " Trait implemented by writeable registers."]
#[doc = ""]
#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."]
#[doc = ""]
#[doc = " Registers marked with `Readable` can be also be `modify`'ed."]
pub trait Writable: RegisterSpec {
#[doc = " Is it safe to write any bits to register"]
type Safety;
#[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"]
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
#[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"]
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
}
#[doc = " Reset value of the register."]
#[doc = ""]
#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
#[doc = " register by using the `reset` method."]
pub trait Resettable: RegisterSpec {
#[doc = " Reset value of the register."]
const RESET_VALUE: Self::Ux = Self::Ux::ZERO;
#[doc = " Reset value of the register."]
#[inline(always)]
fn reset_value() -> Self::Ux {
Self::RESET_VALUE
}
}
#[doc(hidden)]
pub mod raw {
use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable};
pub struct R<REG: RegisterSpec> {
pub(crate) bits: REG::Ux,
pub(super) _reg: marker::PhantomData<REG>,
}
pub struct W<REG: RegisterSpec> {
#[doc = "Writable bits"]
pub(crate) bits: REG::Ux,
pub(super) _reg: marker::PhantomData<REG>,
}
pub struct FieldReader<FI = u8>
where
FI: FieldSpec,
{
pub(crate) bits: FI::Ux,
_reg: marker::PhantomData<FI>,
}
impl<FI: FieldSpec> FieldReader<FI> {
#[doc = " Creates a new instance of the reader."]
#[allow(unused)]
#[inline(always)]
pub(crate) const fn new(bits: FI::Ux) -> Self {
Self {
bits,
_reg: marker::PhantomData,
}
}
}
pub struct BitReader<FI = bool> {
pub(crate) bits: bool,
_reg: marker::PhantomData<FI>,
}
impl<FI> BitReader<FI> {
#[doc = " Creates a new instance of the reader."]
#[allow(unused)]
#[inline(always)]
pub(crate) const fn new(bits: bool) -> Self {
Self {
bits,
_reg: marker::PhantomData,
}
}
}
#[must_use = "after creating `FieldWriter` you need to call field value setting method"]
pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
{
pub(crate) w: &'a mut W<REG>,
pub(crate) o: u8,
_field: marker::PhantomData<(FI, Safety)>,
}
impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
{
#[doc = " Creates a new instance of the writer"]
#[allow(unused)]
#[inline(always)]
pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
Self {
w,
o,
_field: marker::PhantomData,
}
}
}
#[must_use = "after creating `BitWriter` you need to call bit setting method"]
pub struct BitWriter<'a, REG, FI = bool, M = BitM>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
pub(crate) w: &'a mut W<REG>,
pub(crate) o: u8,
_field: marker::PhantomData<(FI, M)>,
}
impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Creates a new instance of the writer"]
#[allow(unused)]
#[inline(always)]
pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
Self {
w,
o,
_field: marker::PhantomData,
}
}
}
}
#[doc = " Register reader."]
#[doc = ""]
#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
#[doc = " method."]
pub type R<REG> = raw::R<REG>;
impl<REG: RegisterSpec> R<REG> {
#[doc = " Reads raw bits from register."]
#[inline(always)]
pub const fn bits(&self) -> REG::Ux {
self.bits
}
}
impl<REG: RegisterSpec, FI> PartialEq<FI> for R<REG>
where
REG::Ux: PartialEq,
FI: Copy,
REG::Ux: From<FI>,
{
#[inline(always)]
fn eq(&self, other: &FI) -> bool {
self.bits.eq(®::Ux::from(*other))
}
}
#[doc = " Register writer."]
#[doc = ""]
#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."]
pub type W<REG> = raw::W<REG>;
impl<REG: Writable> W<REG> {
#[doc = " Writes raw bits to the register."]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self {
self.bits = bits;
self
}
}
impl<REG> W<REG>
where
REG: Writable<Safety = Safe>,
{
#[doc = " Writes raw bits to the register."]
#[inline(always)]
pub fn set(&mut self, bits: REG::Ux) -> &mut Self {
self.bits = bits;
self
}
}
#[doc = " Field reader."]
#[doc = ""]
#[doc = " Result of the `read` methods of fields."]
pub type FieldReader<FI = u8> = raw::FieldReader<FI>;
#[doc = " Bit-wise field reader"]
pub type BitReader<FI = bool> = raw::BitReader<FI>;
impl<FI: FieldSpec> FieldReader<FI> {
#[doc = " Reads raw bits from field."]
#[inline(always)]
pub const fn bits(&self) -> FI::Ux {
self.bits
}
}
impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.bits, f)
}
}
impl<FI> PartialEq<FI> for FieldReader<FI>
where
FI: FieldSpec + Copy,
{
#[inline(always)]
fn eq(&self, other: &FI) -> bool {
self.bits.eq(&FI::Ux::from(*other))
}
}
impl<FI> PartialEq<FI> for BitReader<FI>
where
FI: Copy,
bool: From<FI>,
{
#[inline(always)]
fn eq(&self, other: &FI) -> bool {
self.bits.eq(&bool::from(*other))
}
}
impl<FI> BitReader<FI> {
#[doc = " Value of the field as raw bits."]
#[inline(always)]
pub const fn bit(&self) -> bool {
self.bits
}
#[doc = " Returns `true` if the bit is clear (0)."]
#[inline(always)]
pub const fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = " Returns `true` if the bit is set (1)."]
#[inline(always)]
pub const fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl<FI> core::fmt::Debug for BitReader<FI> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.bits, f)
}
}
#[doc = " Marker for register/field writers which can take any value of specified width"]
pub struct Safe;
#[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
pub struct Unsafe;
#[doc = " Marker for field writers are safe to write in specified inclusive range"]
pub struct Range<const MIN: u64, const MAX: u64>;
#[doc = " Marker for field writers are safe to write in specified inclusive range"]
pub struct RangeFrom<const MIN: u64>;
#[doc = " Marker for field writers are safe to write in specified inclusive range"]
pub struct RangeTo<const MAX: u64>;
#[doc = " Write field Proxy"]
pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
raw::FieldWriter<'a, REG, WI, FI, Safety>;
impl<REG, const WI: u8, FI, Safety> FieldWriter<'_, REG, WI, FI, Safety>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
{
#[doc = " Field width"]
pub const WIDTH: u8 = WI;
#[doc = " Field width"]
#[inline(always)]
pub const fn width(&self) -> u8 {
WI
}
#[doc = " Field offset"]
#[inline(always)]
pub const fn offset(&self) -> u8 {
self.o
}
}
impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
{
#[doc = " Writes raw bits to the field"]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::mask::<WI>() << self.o);
self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
self.w
}
}
impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
{
#[doc = " Writes raw bits to the field"]
#[inline(always)]
pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
unsafe { self.bits(value) }
}
}
impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
u64: From<FI::Ux>,
{
#[doc = " Writes raw bits to the field"]
#[inline(always)]
pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
{
let value = u64::from(value);
assert!(value >= MIN && value <= MAX);
}
unsafe { self.bits(value) }
}
}
impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
u64: From<FI::Ux>,
{
#[doc = " Writes raw bits to the field"]
#[inline(always)]
pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
{
let value = u64::from(value);
assert!(value >= MIN);
}
unsafe { self.bits(value) }
}
}
impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
u64: From<FI::Ux>,
{
#[doc = " Writes raw bits to the field"]
#[inline(always)]
pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
{
let value = u64::from(value);
assert!(value <= MAX);
}
unsafe { self.bits(value) }
}
}
impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
where
REG: Writable + RegisterSpec,
FI: IsEnum,
REG::Ux: From<FI::Ux>,
{
#[doc = " Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: FI) -> &'a mut W<REG> {
unsafe { self.bits(FI::Ux::from(variant)) }
}
}
macro_rules! bit_proxy {
($ writer : ident , $ mwv : ident) => {
#[doc(hidden)]
pub struct $mwv;
#[doc = " Bit-wise write field proxy"]
pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>;
impl<'a, REG, FI> $writer<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Field width"]
pub const WIDTH: u8 = 1;
#[doc = " Field width"]
#[inline(always)]
pub const fn width(&self) -> u8 {
Self::WIDTH
}
#[doc = " Field offset"]
#[inline(always)]
pub const fn offset(&self) -> u8 {
self.o
}
#[doc = " Writes bit to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o);
self.w.bits |= (REG::Ux::from(value) & REG::Ux::ONE) << self.o;
self.w
}
#[doc = " Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: FI) -> &'a mut W<REG> {
self.bit(bool::from(variant))
}
}
};
}
bit_proxy!(BitWriter, BitM);
bit_proxy!(BitWriter1S, Bit1S);
bit_proxy!(BitWriter0C, Bit0C);
bit_proxy!(BitWriter1C, Bit1C);
bit_proxy!(BitWriter0S, Bit0S);
bit_proxy!(BitWriter1T, Bit1T);
bit_proxy!(BitWriter0T, Bit0T);
impl<'a, REG, FI> BitWriter<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::ONE << self.o;
self.w
}
#[doc = " Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o);
self.w
}
}
impl<'a, REG, FI> BitWriter1S<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::ONE << self.o;
self.w
}
}
impl<'a, REG, FI> BitWriter0C<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o);
self.w
}
}
impl<'a, REG, FI> BitWriter1C<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = "Clears the field bit by passing one"]
#[inline(always)]
pub fn clear_bit_by_one(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::ONE << self.o;
self.w
}
}
impl<'a, REG, FI> BitWriter0S<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = "Sets the field bit by passing zero"]
#[inline(always)]
pub fn set_bit_by_zero(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o);
self.w
}
}
impl<'a, REG, FI> BitWriter1T<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = "Toggle the field bit by passing one"]
#[inline(always)]
pub fn toggle_bit(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::ONE << self.o;
self.w
}
}
impl<'a, REG, FI> BitWriter0T<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = "Toggle the field bit by passing zero"]
#[inline(always)]
pub fn toggle_bit(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o);
self.w
}
}
#[doc = " This structure provides volatile access to registers."]
#[repr(transparent)]
pub struct Reg<REG: RegisterSpec> {
register: vcell::VolatileCell<REG::Ux>,
_marker: marker::PhantomData<REG>,
}
unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
impl<REG: RegisterSpec> Reg<REG> {
#[doc = " Returns the underlying memory address of register."]
#[doc = ""]
#[doc = " ```ignore"]
#[doc = " let reg_ptr = periph.reg.as_ptr();"]
#[doc = " ```"]
#[inline(always)]
pub fn as_ptr(&self) -> *mut REG::Ux {
self.register.as_ptr()
}
}
impl<REG: Readable> Reg<REG> {
#[doc = " Reads the contents of a `Readable` register."]
#[doc = ""]
#[doc = " You can read the raw contents of a register by using `bits`:"]
#[doc = " ```ignore"]
#[doc = " let bits = periph.reg.read().bits();"]
#[doc = " ```"]
#[doc = " or get the content of a particular field of a register:"]
#[doc = " ```ignore"]
#[doc = " let reader = periph.reg.read();"]
#[doc = " let bits = reader.field1().bits();"]
#[doc = " let flag = reader.field2().bit_is_set();"]
#[doc = " ```"]
#[inline(always)]
pub fn read(&self) -> R<REG> {
R {
bits: self.register.get(),
_reg: marker::PhantomData,
}
}
}
impl<REG: Resettable + Writable> Reg<REG> {
#[doc = " Writes the reset value to `Writable` register."]
#[doc = ""]
#[doc = " Resets the register to its initial state."]
#[inline(always)]
pub fn reset(&self) {
self.register.set(REG::RESET_VALUE)
}
#[doc = " Writes bits to a `Writable` register."]
#[doc = ""]
#[doc = " You can write raw bits into a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
#[doc = " ```"]
#[doc = " or write only the fields you need:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| w"]
#[doc = " .field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT)"]
#[doc = " );"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT)"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " In the latter case, other fields will be set to their reset value."]
#[inline(always)]
pub fn write<F>(&self, f: F) -> REG::Ux
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
let value = f(&mut W {
bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
})
.bits;
self.register.set(value);
value
}
#[doc = " Writes bits to a `Writable` register and produce a value."]
#[doc = ""]
#[doc = " You can write raw bits into a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"]
#[doc = " ```"]
#[doc = " or write only the fields you need:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write_and(|w| {"]
#[doc = " w.field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write_and(|w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " In the latter case, other fields will be set to their reset value."]
#[doc = ""]
#[doc = " Values can be returned from the closure:"]
#[doc = " ```ignore"]
#[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"]
#[doc = " ```"]
#[inline(always)]
pub fn from_write<F, T>(&self, f: F) -> T
where
F: FnOnce(&mut W<REG>) -> T,
{
let mut writer = W {
bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
};
let result = f(&mut writer);
self.register.set(writer.bits);
result
}
}
impl<REG: Writable> Reg<REG> {
#[doc = " Writes 0 to a `Writable` register."]
#[doc = ""]
#[doc = " Similar to `write`, but unused bits will contain 0."]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Unsafe to use with registers which don't allow to write 0."]
#[inline(always)]
pub unsafe fn write_with_zero<F>(&self, f: F) -> REG::Ux
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
let value = f(&mut W {
bits: REG::Ux::ZERO,
_reg: marker::PhantomData,
})
.bits;
self.register.set(value);
value
}
#[doc = " Writes 0 to a `Writable` register and produces a value."]
#[doc = ""]
#[doc = " Similar to `write`, but unused bits will contain 0."]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Unsafe to use with registers which don't allow to write 0."]
#[inline(always)]
pub unsafe fn from_write_with_zero<F, T>(&self, f: F) -> T
where
F: FnOnce(&mut W<REG>) -> T,
{
let mut writer = W {
bits: REG::Ux::ZERO,
_reg: marker::PhantomData,
};
let result = f(&mut writer);
self.register.set(writer.bits);
result
}
}
impl<REG: Readable + Writable> Reg<REG> {
#[doc = " Modifies the contents of the register by reading and then writing it."]
#[doc = ""]
#[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
#[doc = " r.bits() | 3"]
#[doc = " ) });"]
#[doc = " ```"]
#[doc = " or"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| w"]
#[doc = " .field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT)"]
#[doc = " );"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT)"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " Other fields will have the value they had before the call to `modify`."]
#[inline(always)]
pub fn modify<F>(&self, f: F) -> REG::Ux
where
for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
{
let bits = self.register.get();
let value = f(
&R {
bits,
_reg: marker::PhantomData,
},
&mut W {
bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
},
)
.bits;
self.register.set(value);
value
}
#[doc = " Modifies the contents of the register by reading and then writing it"]
#[doc = " and produces a value."]
#[doc = ""]
#[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
#[doc = " ```ignore"]
#[doc = " let bits = periph.reg.modify(|r, w| {"]
#[doc = " let new_bits = r.bits() | 3;"]
#[doc = " unsafe {"]
#[doc = " w.bits(new_bits);"]
#[doc = " }"]
#[doc = ""]
#[doc = " new_bits"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " or"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| {"]
#[doc = " w.field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " Other fields will have the value they had before the call to `modify`."]
#[inline(always)]
pub fn from_modify<F, T>(&self, f: F) -> T
where
for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> T,
{
let bits = self.register.get();
let mut writer = W {
bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
};
let result = f(
&R {
bits,
_reg: marker::PhantomData,
},
&mut writer,
);
self.register.set(writer.bits);
result
}
}
impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
where
R<REG>: core::fmt::Debug,
{
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}
}
#[cfg(feature = "rt")]
extern "msp430-interrupt" {
fn AES256();
fn RTC();
fn PORT4();
fn PORT3();
fn TIMER3_A1();
fn TIMER3_A0();
fn PORT2();
fn TIMER2_A1();
fn TIMER2_A0();
fn PORT1();
fn TIMER1_A1();
fn TIMER1_A0();
fn DMA();
fn USCI_A1();
fn TIMER0_A1();
fn TIMER0_A0();
fn ADC12();
fn USCI_B0();
fn USCI_A0();
fn WDT();
fn TIMER0_B1();
fn TIMER0_B0();
fn COMP_E();
fn UNMI();
fn SYSNMI();
}
#[doc(hidden)]
#[cfg(feature = "rt")]
#[repr(C)]
pub union Vector {
_handler: unsafe extern "msp430-interrupt" fn(),
_reserved: u16,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
#[used]
pub static __INTERRUPTS: [Vector; 55] = [
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: AES256 },
Vector { _handler: RTC },
Vector { _handler: PORT4 },
Vector { _handler: PORT3 },
Vector {
_handler: TIMER3_A1,
},
Vector {
_handler: TIMER3_A0,
},
Vector { _handler: PORT2 },
Vector {
_handler: TIMER2_A1,
},
Vector {
_handler: TIMER2_A0,
},
Vector { _handler: PORT1 },
Vector {
_handler: TIMER1_A1,
},
Vector {
_handler: TIMER1_A0,
},
Vector { _handler: DMA },
Vector { _handler: USCI_A1 },
Vector {
_handler: TIMER0_A1,
},
Vector {
_handler: TIMER0_A0,
},
Vector { _handler: ADC12 },
Vector { _handler: USCI_B0 },
Vector { _handler: USCI_A0 },
Vector { _handler: WDT },
Vector {
_handler: TIMER0_B1,
},
Vector {
_handler: TIMER0_B0,
},
Vector { _handler: COMP_E },
Vector { _handler: UNMI },
Vector { _handler: SYSNMI },
];
#[doc = r"Enumeration of all the interrupts. This enum is seldom used in application or library crates. It is present primarily for documenting the device's implemented interrupts."]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
#[doc = "30 - 0xFFCC AES256"]
AES256 = 30,
#[doc = "31 - 0xFFCE RTC"]
RTC = 31,
#[doc = "32 - 0xFFD0 Port 4"]
PORT4 = 32,
#[doc = "33 - 0xFFD2 Port 3"]
PORT3 = 33,
#[doc = "34 - 0xFFD4 Timer3_A2 CC1, TA"]
TIMER3_A1 = 34,
#[doc = "35 - 0xFFD6 Timer3_A2 CC0"]
TIMER3_A0 = 35,
#[doc = "36 - 0xFFD8 Port 2"]
PORT2 = 36,
#[doc = "37 - 0xFFDA Timer2_A2 CC1, TA"]
TIMER2_A1 = 37,
#[doc = "38 - 0xFFDC Timer2_A2 CC0"]
TIMER2_A0 = 38,
#[doc = "39 - 0xFFDE Port 1"]
PORT1 = 39,
#[doc = "40 - 0xFFE0 Timer1_A3 CC1-2, TA"]
TIMER1_A1 = 40,
#[doc = "41 - 0xFFE2 Timer1_A3 CC0"]
TIMER1_A0 = 41,
#[doc = "42 - 0xFFE4 DMA"]
DMA = 42,
#[doc = "43 - 0xFFE6 USCI A1 Receive/Transmit"]
USCI_A1 = 43,
#[doc = "44 - 0xFFE8 Timer0_A3 CC1-2, TA"]
TIMER0_A1 = 44,
#[doc = "45 - 0xFFEA Timer0_A3 CC0"]
TIMER0_A0 = 45,
#[doc = "46 - 0xFFEC ADC"]
ADC12 = 46,
#[doc = "47 - 0xFFEE USCI B0 Receive/Transmit"]
USCI_B0 = 47,
#[doc = "48 - 0xFFF0 USCI A0 Receive/Transmit"]
USCI_A0 = 48,
#[doc = "49 - 0xFFF2 Watchdog Timer"]
WDT = 49,
#[doc = "50 - 0xFFF4 Timer0_B7 CC1-6, TB"]
TIMER0_B1 = 50,
#[doc = "51 - 0xFFF6 Timer0_B7 CC0"]
TIMER0_B0 = 51,
#[doc = "52 - 0xFFF8 Comparator E"]
COMP_E = 52,
#[doc = "53 - 0xFFFA User Non-maskable"]
UNMI = 53,
#[doc = "54 - 0xFFFC System Non-maskable"]
SYSNMI = 54,
}
#[doc = "Port 1/2"]
pub type Port1_2 = crate::Periph<port_1_2::RegisterBlock, 0x0200>;
impl core::fmt::Debug for Port1_2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Port1_2").finish()
}
}
#[doc = "Port 1/2"]
pub mod port_1_2 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
p1in: P1in,
p2in: P2in,
p1out: P1out,
p2out: P2out,
p1dir: P1dir,
p2dir: P2dir,
p1ren: P1ren,
p2ren: P2ren,
_reserved8: [u8; 0x02],
p1sel0: P1sel0,
p2sel0: P2sel0,
p1sel1: P1sel1,
p2sel1: P2sel1,
p1iv: P1iv,
_reserved13: [u8; 0x06],
p1selc: P1selc,
p2selc: P2selc,
p1ies: P1ies,
p2ies: P2ies,
p1ie: P1ie,
p2ie: P2ie,
p1ifg: P1ifg,
p2ifg: P2ifg,
p2iv: P2iv,
}
impl RegisterBlock {
#[doc = "0x00 - Port 1 Input"]
#[inline(always)]
pub const fn p1in(&self) -> &P1in {
&self.p1in
}
#[doc = "0x01 - Port 2 Input"]
#[inline(always)]
pub const fn p2in(&self) -> &P2in {
&self.p2in
}
#[doc = "0x02 - Port 1 Output"]
#[inline(always)]
pub const fn p1out(&self) -> &P1out {
&self.p1out
}
#[doc = "0x03 - Port 2 Output"]
#[inline(always)]
pub const fn p2out(&self) -> &P2out {
&self.p2out
}
#[doc = "0x04 - Port 1 Direction"]
#[inline(always)]
pub const fn p1dir(&self) -> &P1dir {
&self.p1dir
}
#[doc = "0x05 - Port 2 Direction"]
#[inline(always)]
pub const fn p2dir(&self) -> &P2dir {
&self.p2dir
}
#[doc = "0x06 - Port 1 Resistor Enable"]
#[inline(always)]
pub const fn p1ren(&self) -> &P1ren {
&self.p1ren
}
#[doc = "0x07 - Port 2 Resistor Enable"]
#[inline(always)]
pub const fn p2ren(&self) -> &P2ren {
&self.p2ren
}
#[doc = "0x0a - Port 1 Selection 0"]
#[inline(always)]
pub const fn p1sel0(&self) -> &P1sel0 {
&self.p1sel0
}
#[doc = "0x0b - Port 2 Selection 0"]
#[inline(always)]
pub const fn p2sel0(&self) -> &P2sel0 {
&self.p2sel0
}
#[doc = "0x0c - Port 1 Selection 1"]
#[inline(always)]
pub const fn p1sel1(&self) -> &P1sel1 {
&self.p1sel1
}
#[doc = "0x0d - Port 2 Selection 1"]
#[inline(always)]
pub const fn p2sel1(&self) -> &P2sel1 {
&self.p2sel1
}
#[doc = "0x0e - Port 1 Interrupt Vector Word"]
#[inline(always)]
pub const fn p1iv(&self) -> &P1iv {
&self.p1iv
}
#[doc = "0x16 - Port 1 Complement Selection"]
#[inline(always)]
pub const fn p1selc(&self) -> &P1selc {
&self.p1selc
}
#[doc = "0x17 - Port 2 Complement Selection"]
#[inline(always)]
pub const fn p2selc(&self) -> &P2selc {
&self.p2selc
}
#[doc = "0x18 - Port 1 Interrupt Edge Select"]
#[inline(always)]
pub const fn p1ies(&self) -> &P1ies {
&self.p1ies
}
#[doc = "0x19 - Port 2 Interrupt Edge Select"]
#[inline(always)]
pub const fn p2ies(&self) -> &P2ies {
&self.p2ies
}
#[doc = "0x1a - Port 1 Interrupt Enable"]
#[inline(always)]
pub const fn p1ie(&self) -> &P1ie {
&self.p1ie
}
#[doc = "0x1b - Port 2 Interrupt Enable"]
#[inline(always)]
pub const fn p2ie(&self) -> &P2ie {
&self.p2ie
}
#[doc = "0x1c - Port 1 Interrupt Flag"]
#[inline(always)]
pub const fn p1ifg(&self) -> &P1ifg {
&self.p1ifg
}
#[doc = "0x1d - Port 2 Interrupt Flag"]
#[inline(always)]
pub const fn p2ifg(&self) -> &P2ifg {
&self.p2ifg
}
#[doc = "0x1e - Port 2 Interrupt Vector Word"]
#[inline(always)]
pub const fn p2iv(&self) -> &P2iv {
&self.p2iv
}
}
#[doc = "P1IN (rw) register accessor: Port 1 Input\n\nYou can [`read`](crate::Reg::read) this register and get [`p1in::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1in::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p1in`] module"]
#[doc(alias = "P1IN")]
pub type P1in = crate::Reg<p1in::P1inSpec>;
#[doc = "Port 1 Input"]
pub mod p1in {
#[doc = "Register `P1IN` reader"]
pub type R = crate::R<P1inSpec>;
#[doc = "Register `P1IN` writer"]
pub type W = crate::W<P1inSpec>;
#[doc = "Field `P1IN0` reader - P1IN0"]
pub type P1in0R = crate::BitReader;
#[doc = "Field `P1IN0` writer - P1IN0"]
pub type P1in0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IN1` reader - P1IN1"]
pub type P1in1R = crate::BitReader;
#[doc = "Field `P1IN1` writer - P1IN1"]
pub type P1in1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IN2` reader - P1IN2"]
pub type P1in2R = crate::BitReader;
#[doc = "Field `P1IN2` writer - P1IN2"]
pub type P1in2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IN3` reader - P1IN3"]
pub type P1in3R = crate::BitReader;
#[doc = "Field `P1IN3` writer - P1IN3"]
pub type P1in3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IN4` reader - P1IN4"]
pub type P1in4R = crate::BitReader;
#[doc = "Field `P1IN4` writer - P1IN4"]
pub type P1in4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IN5` reader - P1IN5"]
pub type P1in5R = crate::BitReader;
#[doc = "Field `P1IN5` writer - P1IN5"]
pub type P1in5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IN6` reader - P1IN6"]
pub type P1in6R = crate::BitReader;
#[doc = "Field `P1IN6` writer - P1IN6"]
pub type P1in6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IN7` reader - P1IN7"]
pub type P1in7R = crate::BitReader;
#[doc = "Field `P1IN7` writer - P1IN7"]
pub type P1in7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P1IN0"]
#[inline(always)]
pub fn p1in0(&self) -> P1in0R {
P1in0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P1IN1"]
#[inline(always)]
pub fn p1in1(&self) -> P1in1R {
P1in1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P1IN2"]
#[inline(always)]
pub fn p1in2(&self) -> P1in2R {
P1in2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P1IN3"]
#[inline(always)]
pub fn p1in3(&self) -> P1in3R {
P1in3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P1IN4"]
#[inline(always)]
pub fn p1in4(&self) -> P1in4R {
P1in4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P1IN5"]
#[inline(always)]
pub fn p1in5(&self) -> P1in5R {
P1in5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P1IN6"]
#[inline(always)]
pub fn p1in6(&self) -> P1in6R {
P1in6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P1IN7"]
#[inline(always)]
pub fn p1in7(&self) -> P1in7R {
P1in7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P1IN0"]
#[inline(always)]
pub fn p1in0(&mut self) -> P1in0W<'_, P1inSpec> {
P1in0W::new(self, 0)
}
#[doc = "Bit 1 - P1IN1"]
#[inline(always)]
pub fn p1in1(&mut self) -> P1in1W<'_, P1inSpec> {
P1in1W::new(self, 1)
}
#[doc = "Bit 2 - P1IN2"]
#[inline(always)]
pub fn p1in2(&mut self) -> P1in2W<'_, P1inSpec> {
P1in2W::new(self, 2)
}
#[doc = "Bit 3 - P1IN3"]
#[inline(always)]
pub fn p1in3(&mut self) -> P1in3W<'_, P1inSpec> {
P1in3W::new(self, 3)
}
#[doc = "Bit 4 - P1IN4"]
#[inline(always)]
pub fn p1in4(&mut self) -> P1in4W<'_, P1inSpec> {
P1in4W::new(self, 4)
}
#[doc = "Bit 5 - P1IN5"]
#[inline(always)]
pub fn p1in5(&mut self) -> P1in5W<'_, P1inSpec> {
P1in5W::new(self, 5)
}
#[doc = "Bit 6 - P1IN6"]
#[inline(always)]
pub fn p1in6(&mut self) -> P1in6W<'_, P1inSpec> {
P1in6W::new(self, 6)
}
#[doc = "Bit 7 - P1IN7"]
#[inline(always)]
pub fn p1in7(&mut self) -> P1in7W<'_, P1inSpec> {
P1in7W::new(self, 7)
}
}
#[doc = "Port 1 Input\n\nYou can [`read`](crate::Reg::read) this register and get [`p1in::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1in::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P1inSpec;
impl crate::RegisterSpec for P1inSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p1in::R`](R) reader structure"]
impl crate::Readable for P1inSpec {}
#[doc = "`write(|w| ..)` method takes [`p1in::W`](W) writer structure"]
impl crate::Writable for P1inSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P1IN to value 0"]
impl crate::Resettable for P1inSpec {}
}
#[doc = "P2IN (rw) register accessor: Port 2 Input\n\nYou can [`read`](crate::Reg::read) this register and get [`p2in::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2in::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p2in`] module"]
#[doc(alias = "P2IN")]
pub type P2in = crate::Reg<p2in::P2inSpec>;
#[doc = "Port 2 Input"]
pub mod p2in {
#[doc = "Register `P2IN` reader"]
pub type R = crate::R<P2inSpec>;
#[doc = "Register `P2IN` writer"]
pub type W = crate::W<P2inSpec>;
#[doc = "Field `P2IN0` reader - P2IN0"]
pub type P2in0R = crate::BitReader;
#[doc = "Field `P2IN0` writer - P2IN0"]
pub type P2in0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IN1` reader - P2IN1"]
pub type P2in1R = crate::BitReader;
#[doc = "Field `P2IN1` writer - P2IN1"]
pub type P2in1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IN2` reader - P2IN2"]
pub type P2in2R = crate::BitReader;
#[doc = "Field `P2IN2` writer - P2IN2"]
pub type P2in2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IN3` reader - P2IN3"]
pub type P2in3R = crate::BitReader;
#[doc = "Field `P2IN3` writer - P2IN3"]
pub type P2in3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IN4` reader - P2IN4"]
pub type P2in4R = crate::BitReader;
#[doc = "Field `P2IN4` writer - P2IN4"]
pub type P2in4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IN5` reader - P2IN5"]
pub type P2in5R = crate::BitReader;
#[doc = "Field `P2IN5` writer - P2IN5"]
pub type P2in5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IN6` reader - P2IN6"]
pub type P2in6R = crate::BitReader;
#[doc = "Field `P2IN6` writer - P2IN6"]
pub type P2in6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IN7` reader - P2IN7"]
pub type P2in7R = crate::BitReader;
#[doc = "Field `P2IN7` writer - P2IN7"]
pub type P2in7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P2IN0"]
#[inline(always)]
pub fn p2in0(&self) -> P2in0R {
P2in0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P2IN1"]
#[inline(always)]
pub fn p2in1(&self) -> P2in1R {
P2in1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P2IN2"]
#[inline(always)]
pub fn p2in2(&self) -> P2in2R {
P2in2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P2IN3"]
#[inline(always)]
pub fn p2in3(&self) -> P2in3R {
P2in3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P2IN4"]
#[inline(always)]
pub fn p2in4(&self) -> P2in4R {
P2in4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P2IN5"]
#[inline(always)]
pub fn p2in5(&self) -> P2in5R {
P2in5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P2IN6"]
#[inline(always)]
pub fn p2in6(&self) -> P2in6R {
P2in6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P2IN7"]
#[inline(always)]
pub fn p2in7(&self) -> P2in7R {
P2in7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P2IN0"]
#[inline(always)]
pub fn p2in0(&mut self) -> P2in0W<'_, P2inSpec> {
P2in0W::new(self, 0)
}
#[doc = "Bit 1 - P2IN1"]
#[inline(always)]
pub fn p2in1(&mut self) -> P2in1W<'_, P2inSpec> {
P2in1W::new(self, 1)
}
#[doc = "Bit 2 - P2IN2"]
#[inline(always)]
pub fn p2in2(&mut self) -> P2in2W<'_, P2inSpec> {
P2in2W::new(self, 2)
}
#[doc = "Bit 3 - P2IN3"]
#[inline(always)]
pub fn p2in3(&mut self) -> P2in3W<'_, P2inSpec> {
P2in3W::new(self, 3)
}
#[doc = "Bit 4 - P2IN4"]
#[inline(always)]
pub fn p2in4(&mut self) -> P2in4W<'_, P2inSpec> {
P2in4W::new(self, 4)
}
#[doc = "Bit 5 - P2IN5"]
#[inline(always)]
pub fn p2in5(&mut self) -> P2in5W<'_, P2inSpec> {
P2in5W::new(self, 5)
}
#[doc = "Bit 6 - P2IN6"]
#[inline(always)]
pub fn p2in6(&mut self) -> P2in6W<'_, P2inSpec> {
P2in6W::new(self, 6)
}
#[doc = "Bit 7 - P2IN7"]
#[inline(always)]
pub fn p2in7(&mut self) -> P2in7W<'_, P2inSpec> {
P2in7W::new(self, 7)
}
}
#[doc = "Port 2 Input\n\nYou can [`read`](crate::Reg::read) this register and get [`p2in::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2in::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P2inSpec;
impl crate::RegisterSpec for P2inSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p2in::R`](R) reader structure"]
impl crate::Readable for P2inSpec {}
#[doc = "`write(|w| ..)` method takes [`p2in::W`](W) writer structure"]
impl crate::Writable for P2inSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P2IN to value 0"]
impl crate::Resettable for P2inSpec {}
}
#[doc = "P1OUT (rw) register accessor: Port 1 Output\n\nYou can [`read`](crate::Reg::read) this register and get [`p1out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p1out`] module"]
#[doc(alias = "P1OUT")]
pub type P1out = crate::Reg<p1out::P1outSpec>;
#[doc = "Port 1 Output"]
pub mod p1out {
#[doc = "Register `P1OUT` reader"]
pub type R = crate::R<P1outSpec>;
#[doc = "Register `P1OUT` writer"]
pub type W = crate::W<P1outSpec>;
#[doc = "Field `P1OUT0` reader - P1OUT0"]
pub type P1out0R = crate::BitReader;
#[doc = "Field `P1OUT0` writer - P1OUT0"]
pub type P1out0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1OUT1` reader - P1OUT1"]
pub type P1out1R = crate::BitReader;
#[doc = "Field `P1OUT1` writer - P1OUT1"]
pub type P1out1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1OUT2` reader - P1OUT2"]
pub type P1out2R = crate::BitReader;
#[doc = "Field `P1OUT2` writer - P1OUT2"]
pub type P1out2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1OUT3` reader - P1OUT3"]
pub type P1out3R = crate::BitReader;
#[doc = "Field `P1OUT3` writer - P1OUT3"]
pub type P1out3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1OUT4` reader - P1OUT4"]
pub type P1out4R = crate::BitReader;
#[doc = "Field `P1OUT4` writer - P1OUT4"]
pub type P1out4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1OUT5` reader - P1OUT5"]
pub type P1out5R = crate::BitReader;
#[doc = "Field `P1OUT5` writer - P1OUT5"]
pub type P1out5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1OUT6` reader - P1OUT6"]
pub type P1out6R = crate::BitReader;
#[doc = "Field `P1OUT6` writer - P1OUT6"]
pub type P1out6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1OUT7` reader - P1OUT7"]
pub type P1out7R = crate::BitReader;
#[doc = "Field `P1OUT7` writer - P1OUT7"]
pub type P1out7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P1OUT0"]
#[inline(always)]
pub fn p1out0(&self) -> P1out0R {
P1out0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P1OUT1"]
#[inline(always)]
pub fn p1out1(&self) -> P1out1R {
P1out1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P1OUT2"]
#[inline(always)]
pub fn p1out2(&self) -> P1out2R {
P1out2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P1OUT3"]
#[inline(always)]
pub fn p1out3(&self) -> P1out3R {
P1out3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P1OUT4"]
#[inline(always)]
pub fn p1out4(&self) -> P1out4R {
P1out4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P1OUT5"]
#[inline(always)]
pub fn p1out5(&self) -> P1out5R {
P1out5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P1OUT6"]
#[inline(always)]
pub fn p1out6(&self) -> P1out6R {
P1out6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P1OUT7"]
#[inline(always)]
pub fn p1out7(&self) -> P1out7R {
P1out7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P1OUT0"]
#[inline(always)]
pub fn p1out0(&mut self) -> P1out0W<'_, P1outSpec> {
P1out0W::new(self, 0)
}
#[doc = "Bit 1 - P1OUT1"]
#[inline(always)]
pub fn p1out1(&mut self) -> P1out1W<'_, P1outSpec> {
P1out1W::new(self, 1)
}
#[doc = "Bit 2 - P1OUT2"]
#[inline(always)]
pub fn p1out2(&mut self) -> P1out2W<'_, P1outSpec> {
P1out2W::new(self, 2)
}
#[doc = "Bit 3 - P1OUT3"]
#[inline(always)]
pub fn p1out3(&mut self) -> P1out3W<'_, P1outSpec> {
P1out3W::new(self, 3)
}
#[doc = "Bit 4 - P1OUT4"]
#[inline(always)]
pub fn p1out4(&mut self) -> P1out4W<'_, P1outSpec> {
P1out4W::new(self, 4)
}
#[doc = "Bit 5 - P1OUT5"]
#[inline(always)]
pub fn p1out5(&mut self) -> P1out5W<'_, P1outSpec> {
P1out5W::new(self, 5)
}
#[doc = "Bit 6 - P1OUT6"]
#[inline(always)]
pub fn p1out6(&mut self) -> P1out6W<'_, P1outSpec> {
P1out6W::new(self, 6)
}
#[doc = "Bit 7 - P1OUT7"]
#[inline(always)]
pub fn p1out7(&mut self) -> P1out7W<'_, P1outSpec> {
P1out7W::new(self, 7)
}
}
#[doc = "Port 1 Output\n\nYou can [`read`](crate::Reg::read) this register and get [`p1out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P1outSpec;
impl crate::RegisterSpec for P1outSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p1out::R`](R) reader structure"]
impl crate::Readable for P1outSpec {}
#[doc = "`write(|w| ..)` method takes [`p1out::W`](W) writer structure"]
impl crate::Writable for P1outSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P1OUT to value 0"]
impl crate::Resettable for P1outSpec {}
}
#[doc = "P2OUT (rw) register accessor: Port 2 Output\n\nYou can [`read`](crate::Reg::read) this register and get [`p2out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p2out`] module"]
#[doc(alias = "P2OUT")]
pub type P2out = crate::Reg<p2out::P2outSpec>;
#[doc = "Port 2 Output"]
pub mod p2out {
#[doc = "Register `P2OUT` reader"]
pub type R = crate::R<P2outSpec>;
#[doc = "Register `P2OUT` writer"]
pub type W = crate::W<P2outSpec>;
#[doc = "Field `P2OUT0` reader - P2OUT0"]
pub type P2out0R = crate::BitReader;
#[doc = "Field `P2OUT0` writer - P2OUT0"]
pub type P2out0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2OUT1` reader - P2OUT1"]
pub type P2out1R = crate::BitReader;
#[doc = "Field `P2OUT1` writer - P2OUT1"]
pub type P2out1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2OUT2` reader - P2OUT2"]
pub type P2out2R = crate::BitReader;
#[doc = "Field `P2OUT2` writer - P2OUT2"]
pub type P2out2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2OUT3` reader - P2OUT3"]
pub type P2out3R = crate::BitReader;
#[doc = "Field `P2OUT3` writer - P2OUT3"]
pub type P2out3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2OUT4` reader - P2OUT4"]
pub type P2out4R = crate::BitReader;
#[doc = "Field `P2OUT4` writer - P2OUT4"]
pub type P2out4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2OUT5` reader - P2OUT5"]
pub type P2out5R = crate::BitReader;
#[doc = "Field `P2OUT5` writer - P2OUT5"]
pub type P2out5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2OUT6` reader - P2OUT6"]
pub type P2out6R = crate::BitReader;
#[doc = "Field `P2OUT6` writer - P2OUT6"]
pub type P2out6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2OUT7` reader - P2OUT7"]
pub type P2out7R = crate::BitReader;
#[doc = "Field `P2OUT7` writer - P2OUT7"]
pub type P2out7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P2OUT0"]
#[inline(always)]
pub fn p2out0(&self) -> P2out0R {
P2out0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P2OUT1"]
#[inline(always)]
pub fn p2out1(&self) -> P2out1R {
P2out1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P2OUT2"]
#[inline(always)]
pub fn p2out2(&self) -> P2out2R {
P2out2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P2OUT3"]
#[inline(always)]
pub fn p2out3(&self) -> P2out3R {
P2out3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P2OUT4"]
#[inline(always)]
pub fn p2out4(&self) -> P2out4R {
P2out4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P2OUT5"]
#[inline(always)]
pub fn p2out5(&self) -> P2out5R {
P2out5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P2OUT6"]
#[inline(always)]
pub fn p2out6(&self) -> P2out6R {
P2out6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P2OUT7"]
#[inline(always)]
pub fn p2out7(&self) -> P2out7R {
P2out7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P2OUT0"]
#[inline(always)]
pub fn p2out0(&mut self) -> P2out0W<'_, P2outSpec> {
P2out0W::new(self, 0)
}
#[doc = "Bit 1 - P2OUT1"]
#[inline(always)]
pub fn p2out1(&mut self) -> P2out1W<'_, P2outSpec> {
P2out1W::new(self, 1)
}
#[doc = "Bit 2 - P2OUT2"]
#[inline(always)]
pub fn p2out2(&mut self) -> P2out2W<'_, P2outSpec> {
P2out2W::new(self, 2)
}
#[doc = "Bit 3 - P2OUT3"]
#[inline(always)]
pub fn p2out3(&mut self) -> P2out3W<'_, P2outSpec> {
P2out3W::new(self, 3)
}
#[doc = "Bit 4 - P2OUT4"]
#[inline(always)]
pub fn p2out4(&mut self) -> P2out4W<'_, P2outSpec> {
P2out4W::new(self, 4)
}
#[doc = "Bit 5 - P2OUT5"]
#[inline(always)]
pub fn p2out5(&mut self) -> P2out5W<'_, P2outSpec> {
P2out5W::new(self, 5)
}
#[doc = "Bit 6 - P2OUT6"]
#[inline(always)]
pub fn p2out6(&mut self) -> P2out6W<'_, P2outSpec> {
P2out6W::new(self, 6)
}
#[doc = "Bit 7 - P2OUT7"]
#[inline(always)]
pub fn p2out7(&mut self) -> P2out7W<'_, P2outSpec> {
P2out7W::new(self, 7)
}
}
#[doc = "Port 2 Output\n\nYou can [`read`](crate::Reg::read) this register and get [`p2out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P2outSpec;
impl crate::RegisterSpec for P2outSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p2out::R`](R) reader structure"]
impl crate::Readable for P2outSpec {}
#[doc = "`write(|w| ..)` method takes [`p2out::W`](W) writer structure"]
impl crate::Writable for P2outSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P2OUT to value 0"]
impl crate::Resettable for P2outSpec {}
}
#[doc = "P1DIR (rw) register accessor: Port 1 Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`p1dir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1dir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p1dir`] module"]
#[doc(alias = "P1DIR")]
pub type P1dir = crate::Reg<p1dir::P1dirSpec>;
#[doc = "Port 1 Direction"]
pub mod p1dir {
#[doc = "Register `P1DIR` reader"]
pub type R = crate::R<P1dirSpec>;
#[doc = "Register `P1DIR` writer"]
pub type W = crate::W<P1dirSpec>;
#[doc = "Field `P1DIR0` reader - P1DIR0"]
pub type P1dir0R = crate::BitReader;
#[doc = "Field `P1DIR0` writer - P1DIR0"]
pub type P1dir0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1DIR1` reader - P1DIR1"]
pub type P1dir1R = crate::BitReader;
#[doc = "Field `P1DIR1` writer - P1DIR1"]
pub type P1dir1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1DIR2` reader - P1DIR2"]
pub type P1dir2R = crate::BitReader;
#[doc = "Field `P1DIR2` writer - P1DIR2"]
pub type P1dir2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1DIR3` reader - P1DIR3"]
pub type P1dir3R = crate::BitReader;
#[doc = "Field `P1DIR3` writer - P1DIR3"]
pub type P1dir3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1DIR4` reader - P1DIR4"]
pub type P1dir4R = crate::BitReader;
#[doc = "Field `P1DIR4` writer - P1DIR4"]
pub type P1dir4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1DIR5` reader - P1DIR5"]
pub type P1dir5R = crate::BitReader;
#[doc = "Field `P1DIR5` writer - P1DIR5"]
pub type P1dir5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1DIR6` reader - P1DIR6"]
pub type P1dir6R = crate::BitReader;
#[doc = "Field `P1DIR6` writer - P1DIR6"]
pub type P1dir6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1DIR7` reader - P1DIR7"]
pub type P1dir7R = crate::BitReader;
#[doc = "Field `P1DIR7` writer - P1DIR7"]
pub type P1dir7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P1DIR0"]
#[inline(always)]
pub fn p1dir0(&self) -> P1dir0R {
P1dir0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P1DIR1"]
#[inline(always)]
pub fn p1dir1(&self) -> P1dir1R {
P1dir1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P1DIR2"]
#[inline(always)]
pub fn p1dir2(&self) -> P1dir2R {
P1dir2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P1DIR3"]
#[inline(always)]
pub fn p1dir3(&self) -> P1dir3R {
P1dir3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P1DIR4"]
#[inline(always)]
pub fn p1dir4(&self) -> P1dir4R {
P1dir4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P1DIR5"]
#[inline(always)]
pub fn p1dir5(&self) -> P1dir5R {
P1dir5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P1DIR6"]
#[inline(always)]
pub fn p1dir6(&self) -> P1dir6R {
P1dir6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P1DIR7"]
#[inline(always)]
pub fn p1dir7(&self) -> P1dir7R {
P1dir7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P1DIR0"]
#[inline(always)]
pub fn p1dir0(&mut self) -> P1dir0W<'_, P1dirSpec> {
P1dir0W::new(self, 0)
}
#[doc = "Bit 1 - P1DIR1"]
#[inline(always)]
pub fn p1dir1(&mut self) -> P1dir1W<'_, P1dirSpec> {
P1dir1W::new(self, 1)
}
#[doc = "Bit 2 - P1DIR2"]
#[inline(always)]
pub fn p1dir2(&mut self) -> P1dir2W<'_, P1dirSpec> {
P1dir2W::new(self, 2)
}
#[doc = "Bit 3 - P1DIR3"]
#[inline(always)]
pub fn p1dir3(&mut self) -> P1dir3W<'_, P1dirSpec> {
P1dir3W::new(self, 3)
}
#[doc = "Bit 4 - P1DIR4"]
#[inline(always)]
pub fn p1dir4(&mut self) -> P1dir4W<'_, P1dirSpec> {
P1dir4W::new(self, 4)
}
#[doc = "Bit 5 - P1DIR5"]
#[inline(always)]
pub fn p1dir5(&mut self) -> P1dir5W<'_, P1dirSpec> {
P1dir5W::new(self, 5)
}
#[doc = "Bit 6 - P1DIR6"]
#[inline(always)]
pub fn p1dir6(&mut self) -> P1dir6W<'_, P1dirSpec> {
P1dir6W::new(self, 6)
}
#[doc = "Bit 7 - P1DIR7"]
#[inline(always)]
pub fn p1dir7(&mut self) -> P1dir7W<'_, P1dirSpec> {
P1dir7W::new(self, 7)
}
}
#[doc = "Port 1 Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`p1dir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1dir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P1dirSpec;
impl crate::RegisterSpec for P1dirSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p1dir::R`](R) reader structure"]
impl crate::Readable for P1dirSpec {}
#[doc = "`write(|w| ..)` method takes [`p1dir::W`](W) writer structure"]
impl crate::Writable for P1dirSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P1DIR to value 0"]
impl crate::Resettable for P1dirSpec {}
}
#[doc = "P2DIR (rw) register accessor: Port 2 Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`p2dir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2dir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p2dir`] module"]
#[doc(alias = "P2DIR")]
pub type P2dir = crate::Reg<p2dir::P2dirSpec>;
#[doc = "Port 2 Direction"]
pub mod p2dir {
#[doc = "Register `P2DIR` reader"]
pub type R = crate::R<P2dirSpec>;
#[doc = "Register `P2DIR` writer"]
pub type W = crate::W<P2dirSpec>;
#[doc = "Field `P2DIR0` reader - P2DIR0"]
pub type P2dir0R = crate::BitReader;
#[doc = "Field `P2DIR0` writer - P2DIR0"]
pub type P2dir0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2DIR1` reader - P2DIR1"]
pub type P2dir1R = crate::BitReader;
#[doc = "Field `P2DIR1` writer - P2DIR1"]
pub type P2dir1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2DIR2` reader - P2DIR2"]
pub type P2dir2R = crate::BitReader;
#[doc = "Field `P2DIR2` writer - P2DIR2"]
pub type P2dir2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2DIR3` reader - P2DIR3"]
pub type P2dir3R = crate::BitReader;
#[doc = "Field `P2DIR3` writer - P2DIR3"]
pub type P2dir3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2DIR4` reader - P2DIR4"]
pub type P2dir4R = crate::BitReader;
#[doc = "Field `P2DIR4` writer - P2DIR4"]
pub type P2dir4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2DIR5` reader - P2DIR5"]
pub type P2dir5R = crate::BitReader;
#[doc = "Field `P2DIR5` writer - P2DIR5"]
pub type P2dir5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2DIR6` reader - P2DIR6"]
pub type P2dir6R = crate::BitReader;
#[doc = "Field `P2DIR6` writer - P2DIR6"]
pub type P2dir6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2DIR7` reader - P2DIR7"]
pub type P2dir7R = crate::BitReader;
#[doc = "Field `P2DIR7` writer - P2DIR7"]
pub type P2dir7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P2DIR0"]
#[inline(always)]
pub fn p2dir0(&self) -> P2dir0R {
P2dir0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P2DIR1"]
#[inline(always)]
pub fn p2dir1(&self) -> P2dir1R {
P2dir1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P2DIR2"]
#[inline(always)]
pub fn p2dir2(&self) -> P2dir2R {
P2dir2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P2DIR3"]
#[inline(always)]
pub fn p2dir3(&self) -> P2dir3R {
P2dir3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P2DIR4"]
#[inline(always)]
pub fn p2dir4(&self) -> P2dir4R {
P2dir4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P2DIR5"]
#[inline(always)]
pub fn p2dir5(&self) -> P2dir5R {
P2dir5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P2DIR6"]
#[inline(always)]
pub fn p2dir6(&self) -> P2dir6R {
P2dir6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P2DIR7"]
#[inline(always)]
pub fn p2dir7(&self) -> P2dir7R {
P2dir7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P2DIR0"]
#[inline(always)]
pub fn p2dir0(&mut self) -> P2dir0W<'_, P2dirSpec> {
P2dir0W::new(self, 0)
}
#[doc = "Bit 1 - P2DIR1"]
#[inline(always)]
pub fn p2dir1(&mut self) -> P2dir1W<'_, P2dirSpec> {
P2dir1W::new(self, 1)
}
#[doc = "Bit 2 - P2DIR2"]
#[inline(always)]
pub fn p2dir2(&mut self) -> P2dir2W<'_, P2dirSpec> {
P2dir2W::new(self, 2)
}
#[doc = "Bit 3 - P2DIR3"]
#[inline(always)]
pub fn p2dir3(&mut self) -> P2dir3W<'_, P2dirSpec> {
P2dir3W::new(self, 3)
}
#[doc = "Bit 4 - P2DIR4"]
#[inline(always)]
pub fn p2dir4(&mut self) -> P2dir4W<'_, P2dirSpec> {
P2dir4W::new(self, 4)
}
#[doc = "Bit 5 - P2DIR5"]
#[inline(always)]
pub fn p2dir5(&mut self) -> P2dir5W<'_, P2dirSpec> {
P2dir5W::new(self, 5)
}
#[doc = "Bit 6 - P2DIR6"]
#[inline(always)]
pub fn p2dir6(&mut self) -> P2dir6W<'_, P2dirSpec> {
P2dir6W::new(self, 6)
}
#[doc = "Bit 7 - P2DIR7"]
#[inline(always)]
pub fn p2dir7(&mut self) -> P2dir7W<'_, P2dirSpec> {
P2dir7W::new(self, 7)
}
}
#[doc = "Port 2 Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`p2dir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2dir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P2dirSpec;
impl crate::RegisterSpec for P2dirSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p2dir::R`](R) reader structure"]
impl crate::Readable for P2dirSpec {}
#[doc = "`write(|w| ..)` method takes [`p2dir::W`](W) writer structure"]
impl crate::Writable for P2dirSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P2DIR to value 0"]
impl crate::Resettable for P2dirSpec {}
}
#[doc = "P1REN (rw) register accessor: Port 1 Resistor Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p1ren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1ren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p1ren`] module"]
#[doc(alias = "P1REN")]
pub type P1ren = crate::Reg<p1ren::P1renSpec>;
#[doc = "Port 1 Resistor Enable"]
pub mod p1ren {
#[doc = "Register `P1REN` reader"]
pub type R = crate::R<P1renSpec>;
#[doc = "Register `P1REN` writer"]
pub type W = crate::W<P1renSpec>;
#[doc = "Field `P1REN0` reader - P1REN0"]
pub type P1ren0R = crate::BitReader;
#[doc = "Field `P1REN0` writer - P1REN0"]
pub type P1ren0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1REN1` reader - P1REN1"]
pub type P1ren1R = crate::BitReader;
#[doc = "Field `P1REN1` writer - P1REN1"]
pub type P1ren1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1REN2` reader - P1REN2"]
pub type P1ren2R = crate::BitReader;
#[doc = "Field `P1REN2` writer - P1REN2"]
pub type P1ren2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1REN3` reader - P1REN3"]
pub type P1ren3R = crate::BitReader;
#[doc = "Field `P1REN3` writer - P1REN3"]
pub type P1ren3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1REN4` reader - P1REN4"]
pub type P1ren4R = crate::BitReader;
#[doc = "Field `P1REN4` writer - P1REN4"]
pub type P1ren4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1REN5` reader - P1REN5"]
pub type P1ren5R = crate::BitReader;
#[doc = "Field `P1REN5` writer - P1REN5"]
pub type P1ren5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1REN6` reader - P1REN6"]
pub type P1ren6R = crate::BitReader;
#[doc = "Field `P1REN6` writer - P1REN6"]
pub type P1ren6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1REN7` reader - P1REN7"]
pub type P1ren7R = crate::BitReader;
#[doc = "Field `P1REN7` writer - P1REN7"]
pub type P1ren7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P1REN0"]
#[inline(always)]
pub fn p1ren0(&self) -> P1ren0R {
P1ren0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P1REN1"]
#[inline(always)]
pub fn p1ren1(&self) -> P1ren1R {
P1ren1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P1REN2"]
#[inline(always)]
pub fn p1ren2(&self) -> P1ren2R {
P1ren2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P1REN3"]
#[inline(always)]
pub fn p1ren3(&self) -> P1ren3R {
P1ren3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P1REN4"]
#[inline(always)]
pub fn p1ren4(&self) -> P1ren4R {
P1ren4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P1REN5"]
#[inline(always)]
pub fn p1ren5(&self) -> P1ren5R {
P1ren5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P1REN6"]
#[inline(always)]
pub fn p1ren6(&self) -> P1ren6R {
P1ren6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P1REN7"]
#[inline(always)]
pub fn p1ren7(&self) -> P1ren7R {
P1ren7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P1REN0"]
#[inline(always)]
pub fn p1ren0(&mut self) -> P1ren0W<'_, P1renSpec> {
P1ren0W::new(self, 0)
}
#[doc = "Bit 1 - P1REN1"]
#[inline(always)]
pub fn p1ren1(&mut self) -> P1ren1W<'_, P1renSpec> {
P1ren1W::new(self, 1)
}
#[doc = "Bit 2 - P1REN2"]
#[inline(always)]
pub fn p1ren2(&mut self) -> P1ren2W<'_, P1renSpec> {
P1ren2W::new(self, 2)
}
#[doc = "Bit 3 - P1REN3"]
#[inline(always)]
pub fn p1ren3(&mut self) -> P1ren3W<'_, P1renSpec> {
P1ren3W::new(self, 3)
}
#[doc = "Bit 4 - P1REN4"]
#[inline(always)]
pub fn p1ren4(&mut self) -> P1ren4W<'_, P1renSpec> {
P1ren4W::new(self, 4)
}
#[doc = "Bit 5 - P1REN5"]
#[inline(always)]
pub fn p1ren5(&mut self) -> P1ren5W<'_, P1renSpec> {
P1ren5W::new(self, 5)
}
#[doc = "Bit 6 - P1REN6"]
#[inline(always)]
pub fn p1ren6(&mut self) -> P1ren6W<'_, P1renSpec> {
P1ren6W::new(self, 6)
}
#[doc = "Bit 7 - P1REN7"]
#[inline(always)]
pub fn p1ren7(&mut self) -> P1ren7W<'_, P1renSpec> {
P1ren7W::new(self, 7)
}
}
#[doc = "Port 1 Resistor Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p1ren::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1ren::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P1renSpec;
impl crate::RegisterSpec for P1renSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p1ren::R`](R) reader structure"]
impl crate::Readable for P1renSpec {}
#[doc = "`write(|w| ..)` method takes [`p1ren::W`](W) writer structure"]
impl crate::Writable for P1renSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P1REN to value 0"]
impl crate::Resettable for P1renSpec {}
}
#[doc = "P2REN (rw) register accessor: Port 2 Resistor Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p2ren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2ren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p2ren`] module"]
#[doc(alias = "P2REN")]
pub type P2ren = crate::Reg<p2ren::P2renSpec>;
#[doc = "Port 2 Resistor Enable"]
pub mod p2ren {
#[doc = "Register `P2REN` reader"]
pub type R = crate::R<P2renSpec>;
#[doc = "Register `P2REN` writer"]
pub type W = crate::W<P2renSpec>;
#[doc = "Field `P2REN0` reader - P2REN0"]
pub type P2ren0R = crate::BitReader;
#[doc = "Field `P2REN0` writer - P2REN0"]
pub type P2ren0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2REN1` reader - P2REN1"]
pub type P2ren1R = crate::BitReader;
#[doc = "Field `P2REN1` writer - P2REN1"]
pub type P2ren1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2REN2` reader - P2REN2"]
pub type P2ren2R = crate::BitReader;
#[doc = "Field `P2REN2` writer - P2REN2"]
pub type P2ren2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2REN3` reader - P2REN3"]
pub type P2ren3R = crate::BitReader;
#[doc = "Field `P2REN3` writer - P2REN3"]
pub type P2ren3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2REN4` reader - P2REN4"]
pub type P2ren4R = crate::BitReader;
#[doc = "Field `P2REN4` writer - P2REN4"]
pub type P2ren4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2REN5` reader - P2REN5"]
pub type P2ren5R = crate::BitReader;
#[doc = "Field `P2REN5` writer - P2REN5"]
pub type P2ren5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2REN6` reader - P2REN6"]
pub type P2ren6R = crate::BitReader;
#[doc = "Field `P2REN6` writer - P2REN6"]
pub type P2ren6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2REN7` reader - P2REN7"]
pub type P2ren7R = crate::BitReader;
#[doc = "Field `P2REN7` writer - P2REN7"]
pub type P2ren7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P2REN0"]
#[inline(always)]
pub fn p2ren0(&self) -> P2ren0R {
P2ren0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P2REN1"]
#[inline(always)]
pub fn p2ren1(&self) -> P2ren1R {
P2ren1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P2REN2"]
#[inline(always)]
pub fn p2ren2(&self) -> P2ren2R {
P2ren2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P2REN3"]
#[inline(always)]
pub fn p2ren3(&self) -> P2ren3R {
P2ren3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P2REN4"]
#[inline(always)]
pub fn p2ren4(&self) -> P2ren4R {
P2ren4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P2REN5"]
#[inline(always)]
pub fn p2ren5(&self) -> P2ren5R {
P2ren5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P2REN6"]
#[inline(always)]
pub fn p2ren6(&self) -> P2ren6R {
P2ren6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P2REN7"]
#[inline(always)]
pub fn p2ren7(&self) -> P2ren7R {
P2ren7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P2REN0"]
#[inline(always)]
pub fn p2ren0(&mut self) -> P2ren0W<'_, P2renSpec> {
P2ren0W::new(self, 0)
}
#[doc = "Bit 1 - P2REN1"]
#[inline(always)]
pub fn p2ren1(&mut self) -> P2ren1W<'_, P2renSpec> {
P2ren1W::new(self, 1)
}
#[doc = "Bit 2 - P2REN2"]
#[inline(always)]
pub fn p2ren2(&mut self) -> P2ren2W<'_, P2renSpec> {
P2ren2W::new(self, 2)
}
#[doc = "Bit 3 - P2REN3"]
#[inline(always)]
pub fn p2ren3(&mut self) -> P2ren3W<'_, P2renSpec> {
P2ren3W::new(self, 3)
}
#[doc = "Bit 4 - P2REN4"]
#[inline(always)]
pub fn p2ren4(&mut self) -> P2ren4W<'_, P2renSpec> {
P2ren4W::new(self, 4)
}
#[doc = "Bit 5 - P2REN5"]
#[inline(always)]
pub fn p2ren5(&mut self) -> P2ren5W<'_, P2renSpec> {
P2ren5W::new(self, 5)
}
#[doc = "Bit 6 - P2REN6"]
#[inline(always)]
pub fn p2ren6(&mut self) -> P2ren6W<'_, P2renSpec> {
P2ren6W::new(self, 6)
}
#[doc = "Bit 7 - P2REN7"]
#[inline(always)]
pub fn p2ren7(&mut self) -> P2ren7W<'_, P2renSpec> {
P2ren7W::new(self, 7)
}
}
#[doc = "Port 2 Resistor Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p2ren::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2ren::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P2renSpec;
impl crate::RegisterSpec for P2renSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p2ren::R`](R) reader structure"]
impl crate::Readable for P2renSpec {}
#[doc = "`write(|w| ..)` method takes [`p2ren::W`](W) writer structure"]
impl crate::Writable for P2renSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P2REN to value 0"]
impl crate::Resettable for P2renSpec {}
}
#[doc = "P1SEL0 (rw) register accessor: Port 1 Selection 0\n\nYou can [`read`](crate::Reg::read) this register and get [`p1sel0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1sel0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p1sel0`] module"]
#[doc(alias = "P1SEL0")]
pub type P1sel0 = crate::Reg<p1sel0::P1sel0Spec>;
#[doc = "Port 1 Selection 0"]
pub mod p1sel0 {
#[doc = "Register `P1SEL0` reader"]
pub type R = crate::R<P1sel0Spec>;
#[doc = "Register `P1SEL0` writer"]
pub type W = crate::W<P1sel0Spec>;
#[doc = "Field `P1SEL0_0` reader - P1SEL0_0"]
pub type P1sel0_0R = crate::BitReader;
#[doc = "Field `P1SEL0_0` writer - P1SEL0_0"]
pub type P1sel0_0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SEL0_1` reader - P1SEL0_1"]
pub type P1sel0_1R = crate::BitReader;
#[doc = "Field `P1SEL0_1` writer - P1SEL0_1"]
pub type P1sel0_1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SEL0_2` reader - P1SEL0_2"]
pub type P1sel0_2R = crate::BitReader;
#[doc = "Field `P1SEL0_2` writer - P1SEL0_2"]
pub type P1sel0_2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SEL0_3` reader - P1SEL0_3"]
pub type P1sel0_3R = crate::BitReader;
#[doc = "Field `P1SEL0_3` writer - P1SEL0_3"]
pub type P1sel0_3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SEL0_4` reader - P1SEL0_4"]
pub type P1sel0_4R = crate::BitReader;
#[doc = "Field `P1SEL0_4` writer - P1SEL0_4"]
pub type P1sel0_4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SEL0_5` reader - P1SEL0_5"]
pub type P1sel0_5R = crate::BitReader;
#[doc = "Field `P1SEL0_5` writer - P1SEL0_5"]
pub type P1sel0_5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SEL0_6` reader - P1SEL0_6"]
pub type P1sel0_6R = crate::BitReader;
#[doc = "Field `P1SEL0_6` writer - P1SEL0_6"]
pub type P1sel0_6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SEL0_7` reader - P1SEL0_7"]
pub type P1sel0_7R = crate::BitReader;
#[doc = "Field `P1SEL0_7` writer - P1SEL0_7"]
pub type P1sel0_7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P1SEL0_0"]
#[inline(always)]
pub fn p1sel0_0(&self) -> P1sel0_0R {
P1sel0_0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P1SEL0_1"]
#[inline(always)]
pub fn p1sel0_1(&self) -> P1sel0_1R {
P1sel0_1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P1SEL0_2"]
#[inline(always)]
pub fn p1sel0_2(&self) -> P1sel0_2R {
P1sel0_2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P1SEL0_3"]
#[inline(always)]
pub fn p1sel0_3(&self) -> P1sel0_3R {
P1sel0_3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P1SEL0_4"]
#[inline(always)]
pub fn p1sel0_4(&self) -> P1sel0_4R {
P1sel0_4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P1SEL0_5"]
#[inline(always)]
pub fn p1sel0_5(&self) -> P1sel0_5R {
P1sel0_5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P1SEL0_6"]
#[inline(always)]
pub fn p1sel0_6(&self) -> P1sel0_6R {
P1sel0_6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P1SEL0_7"]
#[inline(always)]
pub fn p1sel0_7(&self) -> P1sel0_7R {
P1sel0_7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P1SEL0_0"]
#[inline(always)]
pub fn p1sel0_0(&mut self) -> P1sel0_0W<'_, P1sel0Spec> {
P1sel0_0W::new(self, 0)
}
#[doc = "Bit 1 - P1SEL0_1"]
#[inline(always)]
pub fn p1sel0_1(&mut self) -> P1sel0_1W<'_, P1sel0Spec> {
P1sel0_1W::new(self, 1)
}
#[doc = "Bit 2 - P1SEL0_2"]
#[inline(always)]
pub fn p1sel0_2(&mut self) -> P1sel0_2W<'_, P1sel0Spec> {
P1sel0_2W::new(self, 2)
}
#[doc = "Bit 3 - P1SEL0_3"]
#[inline(always)]
pub fn p1sel0_3(&mut self) -> P1sel0_3W<'_, P1sel0Spec> {
P1sel0_3W::new(self, 3)
}
#[doc = "Bit 4 - P1SEL0_4"]
#[inline(always)]
pub fn p1sel0_4(&mut self) -> P1sel0_4W<'_, P1sel0Spec> {
P1sel0_4W::new(self, 4)
}
#[doc = "Bit 5 - P1SEL0_5"]
#[inline(always)]
pub fn p1sel0_5(&mut self) -> P1sel0_5W<'_, P1sel0Spec> {
P1sel0_5W::new(self, 5)
}
#[doc = "Bit 6 - P1SEL0_6"]
#[inline(always)]
pub fn p1sel0_6(&mut self) -> P1sel0_6W<'_, P1sel0Spec> {
P1sel0_6W::new(self, 6)
}
#[doc = "Bit 7 - P1SEL0_7"]
#[inline(always)]
pub fn p1sel0_7(&mut self) -> P1sel0_7W<'_, P1sel0Spec> {
P1sel0_7W::new(self, 7)
}
}
#[doc = "Port 1 Selection 0\n\nYou can [`read`](crate::Reg::read) this register and get [`p1sel0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1sel0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P1sel0Spec;
impl crate::RegisterSpec for P1sel0Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p1sel0::R`](R) reader structure"]
impl crate::Readable for P1sel0Spec {}
#[doc = "`write(|w| ..)` method takes [`p1sel0::W`](W) writer structure"]
impl crate::Writable for P1sel0Spec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P1SEL0 to value 0"]
impl crate::Resettable for P1sel0Spec {}
}
#[doc = "P2SEL0 (rw) register accessor: Port 2 Selection 0\n\nYou can [`read`](crate::Reg::read) this register and get [`p2sel0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2sel0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p2sel0`] module"]
#[doc(alias = "P2SEL0")]
pub type P2sel0 = crate::Reg<p2sel0::P2sel0Spec>;
#[doc = "Port 2 Selection 0"]
pub mod p2sel0 {
#[doc = "Register `P2SEL0` reader"]
pub type R = crate::R<P2sel0Spec>;
#[doc = "Register `P2SEL0` writer"]
pub type W = crate::W<P2sel0Spec>;
#[doc = "Field `P2SEL0_0` reader - P2SEL0_0"]
pub type P2sel0_0R = crate::BitReader;
#[doc = "Field `P2SEL0_0` writer - P2SEL0_0"]
pub type P2sel0_0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SEL0_1` reader - P2SEL0_1"]
pub type P2sel0_1R = crate::BitReader;
#[doc = "Field `P2SEL0_1` writer - P2SEL0_1"]
pub type P2sel0_1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SEL0_2` reader - P2SEL0_2"]
pub type P2sel0_2R = crate::BitReader;
#[doc = "Field `P2SEL0_2` writer - P2SEL0_2"]
pub type P2sel0_2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SEL0_3` reader - P2SEL0_3"]
pub type P2sel0_3R = crate::BitReader;
#[doc = "Field `P2SEL0_3` writer - P2SEL0_3"]
pub type P2sel0_3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SEL0_4` reader - P2SEL0_4"]
pub type P2sel0_4R = crate::BitReader;
#[doc = "Field `P2SEL0_4` writer - P2SEL0_4"]
pub type P2sel0_4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SEL0_5` reader - P2SEL0_5"]
pub type P2sel0_5R = crate::BitReader;
#[doc = "Field `P2SEL0_5` writer - P2SEL0_5"]
pub type P2sel0_5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SEL0_6` reader - P2SEL0_6"]
pub type P2sel0_6R = crate::BitReader;
#[doc = "Field `P2SEL0_6` writer - P2SEL0_6"]
pub type P2sel0_6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SEL0_7` reader - P2SEL0_7"]
pub type P2sel0_7R = crate::BitReader;
#[doc = "Field `P2SEL0_7` writer - P2SEL0_7"]
pub type P2sel0_7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P2SEL0_0"]
#[inline(always)]
pub fn p2sel0_0(&self) -> P2sel0_0R {
P2sel0_0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P2SEL0_1"]
#[inline(always)]
pub fn p2sel0_1(&self) -> P2sel0_1R {
P2sel0_1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P2SEL0_2"]
#[inline(always)]
pub fn p2sel0_2(&self) -> P2sel0_2R {
P2sel0_2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P2SEL0_3"]
#[inline(always)]
pub fn p2sel0_3(&self) -> P2sel0_3R {
P2sel0_3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P2SEL0_4"]
#[inline(always)]
pub fn p2sel0_4(&self) -> P2sel0_4R {
P2sel0_4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P2SEL0_5"]
#[inline(always)]
pub fn p2sel0_5(&self) -> P2sel0_5R {
P2sel0_5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P2SEL0_6"]
#[inline(always)]
pub fn p2sel0_6(&self) -> P2sel0_6R {
P2sel0_6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P2SEL0_7"]
#[inline(always)]
pub fn p2sel0_7(&self) -> P2sel0_7R {
P2sel0_7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P2SEL0_0"]
#[inline(always)]
pub fn p2sel0_0(&mut self) -> P2sel0_0W<'_, P2sel0Spec> {
P2sel0_0W::new(self, 0)
}
#[doc = "Bit 1 - P2SEL0_1"]
#[inline(always)]
pub fn p2sel0_1(&mut self) -> P2sel0_1W<'_, P2sel0Spec> {
P2sel0_1W::new(self, 1)
}
#[doc = "Bit 2 - P2SEL0_2"]
#[inline(always)]
pub fn p2sel0_2(&mut self) -> P2sel0_2W<'_, P2sel0Spec> {
P2sel0_2W::new(self, 2)
}
#[doc = "Bit 3 - P2SEL0_3"]
#[inline(always)]
pub fn p2sel0_3(&mut self) -> P2sel0_3W<'_, P2sel0Spec> {
P2sel0_3W::new(self, 3)
}
#[doc = "Bit 4 - P2SEL0_4"]
#[inline(always)]
pub fn p2sel0_4(&mut self) -> P2sel0_4W<'_, P2sel0Spec> {
P2sel0_4W::new(self, 4)
}
#[doc = "Bit 5 - P2SEL0_5"]
#[inline(always)]
pub fn p2sel0_5(&mut self) -> P2sel0_5W<'_, P2sel0Spec> {
P2sel0_5W::new(self, 5)
}
#[doc = "Bit 6 - P2SEL0_6"]
#[inline(always)]
pub fn p2sel0_6(&mut self) -> P2sel0_6W<'_, P2sel0Spec> {
P2sel0_6W::new(self, 6)
}
#[doc = "Bit 7 - P2SEL0_7"]
#[inline(always)]
pub fn p2sel0_7(&mut self) -> P2sel0_7W<'_, P2sel0Spec> {
P2sel0_7W::new(self, 7)
}
}
#[doc = "Port 2 Selection 0\n\nYou can [`read`](crate::Reg::read) this register and get [`p2sel0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2sel0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P2sel0Spec;
impl crate::RegisterSpec for P2sel0Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p2sel0::R`](R) reader structure"]
impl crate::Readable for P2sel0Spec {}
#[doc = "`write(|w| ..)` method takes [`p2sel0::W`](W) writer structure"]
impl crate::Writable for P2sel0Spec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P2SEL0 to value 0"]
impl crate::Resettable for P2sel0Spec {}
}
#[doc = "P1SEL1 (rw) register accessor: Port 1 Selection 1\n\nYou can [`read`](crate::Reg::read) this register and get [`p1sel1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1sel1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p1sel1`] module"]
#[doc(alias = "P1SEL1")]
pub type P1sel1 = crate::Reg<p1sel1::P1sel1Spec>;
#[doc = "Port 1 Selection 1"]
pub mod p1sel1 {
#[doc = "Register `P1SEL1` reader"]
pub type R = crate::R<P1sel1Spec>;
#[doc = "Register `P1SEL1` writer"]
pub type W = crate::W<P1sel1Spec>;
#[doc = "Field `P1SEL1_0` reader - P1SEL1_0"]
pub type P1sel1_0R = crate::BitReader;
#[doc = "Field `P1SEL1_0` writer - P1SEL1_0"]
pub type P1sel1_0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SEL1_1` reader - P1SEL1_1"]
pub type P1sel1_1R = crate::BitReader;
#[doc = "Field `P1SEL1_1` writer - P1SEL1_1"]
pub type P1sel1_1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SEL1_2` reader - P1SEL1_2"]
pub type P1sel1_2R = crate::BitReader;
#[doc = "Field `P1SEL1_2` writer - P1SEL1_2"]
pub type P1sel1_2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SEL1_3` reader - P1SEL1_3"]
pub type P1sel1_3R = crate::BitReader;
#[doc = "Field `P1SEL1_3` writer - P1SEL1_3"]
pub type P1sel1_3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SEL1_4` reader - P1SEL1_4"]
pub type P1sel1_4R = crate::BitReader;
#[doc = "Field `P1SEL1_4` writer - P1SEL1_4"]
pub type P1sel1_4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SEL1_5` reader - P1SEL1_5"]
pub type P1sel1_5R = crate::BitReader;
#[doc = "Field `P1SEL1_5` writer - P1SEL1_5"]
pub type P1sel1_5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SEL1_6` reader - P1SEL1_6"]
pub type P1sel1_6R = crate::BitReader;
#[doc = "Field `P1SEL1_6` writer - P1SEL1_6"]
pub type P1sel1_6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SEL1_7` reader - P1SEL1_7"]
pub type P1sel1_7R = crate::BitReader;
#[doc = "Field `P1SEL1_7` writer - P1SEL1_7"]
pub type P1sel1_7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P1SEL1_0"]
#[inline(always)]
pub fn p1sel1_0(&self) -> P1sel1_0R {
P1sel1_0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P1SEL1_1"]
#[inline(always)]
pub fn p1sel1_1(&self) -> P1sel1_1R {
P1sel1_1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P1SEL1_2"]
#[inline(always)]
pub fn p1sel1_2(&self) -> P1sel1_2R {
P1sel1_2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P1SEL1_3"]
#[inline(always)]
pub fn p1sel1_3(&self) -> P1sel1_3R {
P1sel1_3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P1SEL1_4"]
#[inline(always)]
pub fn p1sel1_4(&self) -> P1sel1_4R {
P1sel1_4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P1SEL1_5"]
#[inline(always)]
pub fn p1sel1_5(&self) -> P1sel1_5R {
P1sel1_5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P1SEL1_6"]
#[inline(always)]
pub fn p1sel1_6(&self) -> P1sel1_6R {
P1sel1_6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P1SEL1_7"]
#[inline(always)]
pub fn p1sel1_7(&self) -> P1sel1_7R {
P1sel1_7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P1SEL1_0"]
#[inline(always)]
pub fn p1sel1_0(&mut self) -> P1sel1_0W<'_, P1sel1Spec> {
P1sel1_0W::new(self, 0)
}
#[doc = "Bit 1 - P1SEL1_1"]
#[inline(always)]
pub fn p1sel1_1(&mut self) -> P1sel1_1W<'_, P1sel1Spec> {
P1sel1_1W::new(self, 1)
}
#[doc = "Bit 2 - P1SEL1_2"]
#[inline(always)]
pub fn p1sel1_2(&mut self) -> P1sel1_2W<'_, P1sel1Spec> {
P1sel1_2W::new(self, 2)
}
#[doc = "Bit 3 - P1SEL1_3"]
#[inline(always)]
pub fn p1sel1_3(&mut self) -> P1sel1_3W<'_, P1sel1Spec> {
P1sel1_3W::new(self, 3)
}
#[doc = "Bit 4 - P1SEL1_4"]
#[inline(always)]
pub fn p1sel1_4(&mut self) -> P1sel1_4W<'_, P1sel1Spec> {
P1sel1_4W::new(self, 4)
}
#[doc = "Bit 5 - P1SEL1_5"]
#[inline(always)]
pub fn p1sel1_5(&mut self) -> P1sel1_5W<'_, P1sel1Spec> {
P1sel1_5W::new(self, 5)
}
#[doc = "Bit 6 - P1SEL1_6"]
#[inline(always)]
pub fn p1sel1_6(&mut self) -> P1sel1_6W<'_, P1sel1Spec> {
P1sel1_6W::new(self, 6)
}
#[doc = "Bit 7 - P1SEL1_7"]
#[inline(always)]
pub fn p1sel1_7(&mut self) -> P1sel1_7W<'_, P1sel1Spec> {
P1sel1_7W::new(self, 7)
}
}
#[doc = "Port 1 Selection 1\n\nYou can [`read`](crate::Reg::read) this register and get [`p1sel1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1sel1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P1sel1Spec;
impl crate::RegisterSpec for P1sel1Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p1sel1::R`](R) reader structure"]
impl crate::Readable for P1sel1Spec {}
#[doc = "`write(|w| ..)` method takes [`p1sel1::W`](W) writer structure"]
impl crate::Writable for P1sel1Spec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P1SEL1 to value 0"]
impl crate::Resettable for P1sel1Spec {}
}
#[doc = "P2SEL1 (rw) register accessor: Port 2 Selection 1\n\nYou can [`read`](crate::Reg::read) this register and get [`p2sel1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2sel1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p2sel1`] module"]
#[doc(alias = "P2SEL1")]
pub type P2sel1 = crate::Reg<p2sel1::P2sel1Spec>;
#[doc = "Port 2 Selection 1"]
pub mod p2sel1 {
#[doc = "Register `P2SEL1` reader"]
pub type R = crate::R<P2sel1Spec>;
#[doc = "Register `P2SEL1` writer"]
pub type W = crate::W<P2sel1Spec>;
#[doc = "Field `P2SEL1_0` reader - P2SEL1_0"]
pub type P2sel1_0R = crate::BitReader;
#[doc = "Field `P2SEL1_0` writer - P2SEL1_0"]
pub type P2sel1_0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SEL1_1` reader - P2SEL1_1"]
pub type P2sel1_1R = crate::BitReader;
#[doc = "Field `P2SEL1_1` writer - P2SEL1_1"]
pub type P2sel1_1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SEL1_2` reader - P2SEL1_2"]
pub type P2sel1_2R = crate::BitReader;
#[doc = "Field `P2SEL1_2` writer - P2SEL1_2"]
pub type P2sel1_2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SEL1_3` reader - P2SEL1_3"]
pub type P2sel1_3R = crate::BitReader;
#[doc = "Field `P2SEL1_3` writer - P2SEL1_3"]
pub type P2sel1_3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SEL1_4` reader - P2SEL1_4"]
pub type P2sel1_4R = crate::BitReader;
#[doc = "Field `P2SEL1_4` writer - P2SEL1_4"]
pub type P2sel1_4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SEL1_5` reader - P2SEL1_5"]
pub type P2sel1_5R = crate::BitReader;
#[doc = "Field `P2SEL1_5` writer - P2SEL1_5"]
pub type P2sel1_5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SEL1_6` reader - P2SEL1_6"]
pub type P2sel1_6R = crate::BitReader;
#[doc = "Field `P2SEL1_6` writer - P2SEL1_6"]
pub type P2sel1_6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SEL1_7` reader - P2SEL1_7"]
pub type P2sel1_7R = crate::BitReader;
#[doc = "Field `P2SEL1_7` writer - P2SEL1_7"]
pub type P2sel1_7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P2SEL1_0"]
#[inline(always)]
pub fn p2sel1_0(&self) -> P2sel1_0R {
P2sel1_0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P2SEL1_1"]
#[inline(always)]
pub fn p2sel1_1(&self) -> P2sel1_1R {
P2sel1_1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P2SEL1_2"]
#[inline(always)]
pub fn p2sel1_2(&self) -> P2sel1_2R {
P2sel1_2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P2SEL1_3"]
#[inline(always)]
pub fn p2sel1_3(&self) -> P2sel1_3R {
P2sel1_3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P2SEL1_4"]
#[inline(always)]
pub fn p2sel1_4(&self) -> P2sel1_4R {
P2sel1_4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P2SEL1_5"]
#[inline(always)]
pub fn p2sel1_5(&self) -> P2sel1_5R {
P2sel1_5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P2SEL1_6"]
#[inline(always)]
pub fn p2sel1_6(&self) -> P2sel1_6R {
P2sel1_6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P2SEL1_7"]
#[inline(always)]
pub fn p2sel1_7(&self) -> P2sel1_7R {
P2sel1_7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P2SEL1_0"]
#[inline(always)]
pub fn p2sel1_0(&mut self) -> P2sel1_0W<'_, P2sel1Spec> {
P2sel1_0W::new(self, 0)
}
#[doc = "Bit 1 - P2SEL1_1"]
#[inline(always)]
pub fn p2sel1_1(&mut self) -> P2sel1_1W<'_, P2sel1Spec> {
P2sel1_1W::new(self, 1)
}
#[doc = "Bit 2 - P2SEL1_2"]
#[inline(always)]
pub fn p2sel1_2(&mut self) -> P2sel1_2W<'_, P2sel1Spec> {
P2sel1_2W::new(self, 2)
}
#[doc = "Bit 3 - P2SEL1_3"]
#[inline(always)]
pub fn p2sel1_3(&mut self) -> P2sel1_3W<'_, P2sel1Spec> {
P2sel1_3W::new(self, 3)
}
#[doc = "Bit 4 - P2SEL1_4"]
#[inline(always)]
pub fn p2sel1_4(&mut self) -> P2sel1_4W<'_, P2sel1Spec> {
P2sel1_4W::new(self, 4)
}
#[doc = "Bit 5 - P2SEL1_5"]
#[inline(always)]
pub fn p2sel1_5(&mut self) -> P2sel1_5W<'_, P2sel1Spec> {
P2sel1_5W::new(self, 5)
}
#[doc = "Bit 6 - P2SEL1_6"]
#[inline(always)]
pub fn p2sel1_6(&mut self) -> P2sel1_6W<'_, P2sel1Spec> {
P2sel1_6W::new(self, 6)
}
#[doc = "Bit 7 - P2SEL1_7"]
#[inline(always)]
pub fn p2sel1_7(&mut self) -> P2sel1_7W<'_, P2sel1Spec> {
P2sel1_7W::new(self, 7)
}
}
#[doc = "Port 2 Selection 1\n\nYou can [`read`](crate::Reg::read) this register and get [`p2sel1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2sel1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P2sel1Spec;
impl crate::RegisterSpec for P2sel1Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p2sel1::R`](R) reader structure"]
impl crate::Readable for P2sel1Spec {}
#[doc = "`write(|w| ..)` method takes [`p2sel1::W`](W) writer structure"]
impl crate::Writable for P2sel1Spec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P2SEL1 to value 0"]
impl crate::Resettable for P2sel1Spec {}
}
#[doc = "P1SELC (rw) register accessor: Port 1 Complement Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`p1selc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1selc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p1selc`] module"]
#[doc(alias = "P1SELC")]
pub type P1selc = crate::Reg<p1selc::P1selcSpec>;
#[doc = "Port 1 Complement Selection"]
pub mod p1selc {
#[doc = "Register `P1SELC` reader"]
pub type R = crate::R<P1selcSpec>;
#[doc = "Register `P1SELC` writer"]
pub type W = crate::W<P1selcSpec>;
#[doc = "Field `P1SELC_0` reader - P1SELC_0"]
pub type P1selc0R = crate::BitReader;
#[doc = "Field `P1SELC_0` writer - P1SELC_0"]
pub type P1selc0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SELC_1` reader - P1SELC_1"]
pub type P1selc1R = crate::BitReader;
#[doc = "Field `P1SELC_1` writer - P1SELC_1"]
pub type P1selc1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SELC_2` reader - P1SELC_2"]
pub type P1selc2R = crate::BitReader;
#[doc = "Field `P1SELC_2` writer - P1SELC_2"]
pub type P1selc2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SELC_3` reader - P1SELC_3"]
pub type P1selc3R = crate::BitReader;
#[doc = "Field `P1SELC_3` writer - P1SELC_3"]
pub type P1selc3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SELC_4` reader - P1SELC_4"]
pub type P1selc4R = crate::BitReader;
#[doc = "Field `P1SELC_4` writer - P1SELC_4"]
pub type P1selc4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SELC_5` reader - P1SELC_5"]
pub type P1selc5R = crate::BitReader;
#[doc = "Field `P1SELC_5` writer - P1SELC_5"]
pub type P1selc5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SELC_6` reader - P1SELC_6"]
pub type P1selc6R = crate::BitReader;
#[doc = "Field `P1SELC_6` writer - P1SELC_6"]
pub type P1selc6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1SELC_7` reader - P1SELC_7"]
pub type P1selc7R = crate::BitReader;
#[doc = "Field `P1SELC_7` writer - P1SELC_7"]
pub type P1selc7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P1SELC_0"]
#[inline(always)]
pub fn p1selc_0(&self) -> P1selc0R {
P1selc0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P1SELC_1"]
#[inline(always)]
pub fn p1selc_1(&self) -> P1selc1R {
P1selc1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P1SELC_2"]
#[inline(always)]
pub fn p1selc_2(&self) -> P1selc2R {
P1selc2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P1SELC_3"]
#[inline(always)]
pub fn p1selc_3(&self) -> P1selc3R {
P1selc3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P1SELC_4"]
#[inline(always)]
pub fn p1selc_4(&self) -> P1selc4R {
P1selc4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P1SELC_5"]
#[inline(always)]
pub fn p1selc_5(&self) -> P1selc5R {
P1selc5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P1SELC_6"]
#[inline(always)]
pub fn p1selc_6(&self) -> P1selc6R {
P1selc6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P1SELC_7"]
#[inline(always)]
pub fn p1selc_7(&self) -> P1selc7R {
P1selc7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P1SELC_0"]
#[inline(always)]
pub fn p1selc_0(&mut self) -> P1selc0W<'_, P1selcSpec> {
P1selc0W::new(self, 0)
}
#[doc = "Bit 1 - P1SELC_1"]
#[inline(always)]
pub fn p1selc_1(&mut self) -> P1selc1W<'_, P1selcSpec> {
P1selc1W::new(self, 1)
}
#[doc = "Bit 2 - P1SELC_2"]
#[inline(always)]
pub fn p1selc_2(&mut self) -> P1selc2W<'_, P1selcSpec> {
P1selc2W::new(self, 2)
}
#[doc = "Bit 3 - P1SELC_3"]
#[inline(always)]
pub fn p1selc_3(&mut self) -> P1selc3W<'_, P1selcSpec> {
P1selc3W::new(self, 3)
}
#[doc = "Bit 4 - P1SELC_4"]
#[inline(always)]
pub fn p1selc_4(&mut self) -> P1selc4W<'_, P1selcSpec> {
P1selc4W::new(self, 4)
}
#[doc = "Bit 5 - P1SELC_5"]
#[inline(always)]
pub fn p1selc_5(&mut self) -> P1selc5W<'_, P1selcSpec> {
P1selc5W::new(self, 5)
}
#[doc = "Bit 6 - P1SELC_6"]
#[inline(always)]
pub fn p1selc_6(&mut self) -> P1selc6W<'_, P1selcSpec> {
P1selc6W::new(self, 6)
}
#[doc = "Bit 7 - P1SELC_7"]
#[inline(always)]
pub fn p1selc_7(&mut self) -> P1selc7W<'_, P1selcSpec> {
P1selc7W::new(self, 7)
}
}
#[doc = "Port 1 Complement Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`p1selc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1selc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P1selcSpec;
impl crate::RegisterSpec for P1selcSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p1selc::R`](R) reader structure"]
impl crate::Readable for P1selcSpec {}
#[doc = "`write(|w| ..)` method takes [`p1selc::W`](W) writer structure"]
impl crate::Writable for P1selcSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P1SELC to value 0"]
impl crate::Resettable for P1selcSpec {}
}
#[doc = "P2SELC (rw) register accessor: Port 2 Complement Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`p2selc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2selc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p2selc`] module"]
#[doc(alias = "P2SELC")]
pub type P2selc = crate::Reg<p2selc::P2selcSpec>;
#[doc = "Port 2 Complement Selection"]
pub mod p2selc {
#[doc = "Register `P2SELC` reader"]
pub type R = crate::R<P2selcSpec>;
#[doc = "Register `P2SELC` writer"]
pub type W = crate::W<P2selcSpec>;
#[doc = "Field `P2SELC_0` reader - P2SELC_0"]
pub type P2selc0R = crate::BitReader;
#[doc = "Field `P2SELC_0` writer - P2SELC_0"]
pub type P2selc0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SELC_1` reader - P2SELC_1"]
pub type P2selc1R = crate::BitReader;
#[doc = "Field `P2SELC_1` writer - P2SELC_1"]
pub type P2selc1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SELC_2` reader - P2SELC_2"]
pub type P2selc2R = crate::BitReader;
#[doc = "Field `P2SELC_2` writer - P2SELC_2"]
pub type P2selc2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SELC_3` reader - P2SELC_3"]
pub type P2selc3R = crate::BitReader;
#[doc = "Field `P2SELC_3` writer - P2SELC_3"]
pub type P2selc3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SELC_4` reader - P2SELC_4"]
pub type P2selc4R = crate::BitReader;
#[doc = "Field `P2SELC_4` writer - P2SELC_4"]
pub type P2selc4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SELC_5` reader - P2SELC_5"]
pub type P2selc5R = crate::BitReader;
#[doc = "Field `P2SELC_5` writer - P2SELC_5"]
pub type P2selc5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SELC_6` reader - P2SELC_6"]
pub type P2selc6R = crate::BitReader;
#[doc = "Field `P2SELC_6` writer - P2SELC_6"]
pub type P2selc6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2SELC_7` reader - P2SELC_7"]
pub type P2selc7R = crate::BitReader;
#[doc = "Field `P2SELC_7` writer - P2SELC_7"]
pub type P2selc7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P2SELC_0"]
#[inline(always)]
pub fn p2selc_0(&self) -> P2selc0R {
P2selc0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P2SELC_1"]
#[inline(always)]
pub fn p2selc_1(&self) -> P2selc1R {
P2selc1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P2SELC_2"]
#[inline(always)]
pub fn p2selc_2(&self) -> P2selc2R {
P2selc2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P2SELC_3"]
#[inline(always)]
pub fn p2selc_3(&self) -> P2selc3R {
P2selc3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P2SELC_4"]
#[inline(always)]
pub fn p2selc_4(&self) -> P2selc4R {
P2selc4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P2SELC_5"]
#[inline(always)]
pub fn p2selc_5(&self) -> P2selc5R {
P2selc5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P2SELC_6"]
#[inline(always)]
pub fn p2selc_6(&self) -> P2selc6R {
P2selc6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P2SELC_7"]
#[inline(always)]
pub fn p2selc_7(&self) -> P2selc7R {
P2selc7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P2SELC_0"]
#[inline(always)]
pub fn p2selc_0(&mut self) -> P2selc0W<'_, P2selcSpec> {
P2selc0W::new(self, 0)
}
#[doc = "Bit 1 - P2SELC_1"]
#[inline(always)]
pub fn p2selc_1(&mut self) -> P2selc1W<'_, P2selcSpec> {
P2selc1W::new(self, 1)
}
#[doc = "Bit 2 - P2SELC_2"]
#[inline(always)]
pub fn p2selc_2(&mut self) -> P2selc2W<'_, P2selcSpec> {
P2selc2W::new(self, 2)
}
#[doc = "Bit 3 - P2SELC_3"]
#[inline(always)]
pub fn p2selc_3(&mut self) -> P2selc3W<'_, P2selcSpec> {
P2selc3W::new(self, 3)
}
#[doc = "Bit 4 - P2SELC_4"]
#[inline(always)]
pub fn p2selc_4(&mut self) -> P2selc4W<'_, P2selcSpec> {
P2selc4W::new(self, 4)
}
#[doc = "Bit 5 - P2SELC_5"]
#[inline(always)]
pub fn p2selc_5(&mut self) -> P2selc5W<'_, P2selcSpec> {
P2selc5W::new(self, 5)
}
#[doc = "Bit 6 - P2SELC_6"]
#[inline(always)]
pub fn p2selc_6(&mut self) -> P2selc6W<'_, P2selcSpec> {
P2selc6W::new(self, 6)
}
#[doc = "Bit 7 - P2SELC_7"]
#[inline(always)]
pub fn p2selc_7(&mut self) -> P2selc7W<'_, P2selcSpec> {
P2selc7W::new(self, 7)
}
}
#[doc = "Port 2 Complement Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`p2selc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2selc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P2selcSpec;
impl crate::RegisterSpec for P2selcSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p2selc::R`](R) reader structure"]
impl crate::Readable for P2selcSpec {}
#[doc = "`write(|w| ..)` method takes [`p2selc::W`](W) writer structure"]
impl crate::Writable for P2selcSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P2SELC to value 0"]
impl crate::Resettable for P2selcSpec {}
}
#[doc = "P1IES (rw) register accessor: Port 1 Interrupt Edge Select\n\nYou can [`read`](crate::Reg::read) this register and get [`p1ies::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1ies::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p1ies`] module"]
#[doc(alias = "P1IES")]
pub type P1ies = crate::Reg<p1ies::P1iesSpec>;
#[doc = "Port 1 Interrupt Edge Select"]
pub mod p1ies {
#[doc = "Register `P1IES` reader"]
pub type R = crate::R<P1iesSpec>;
#[doc = "Register `P1IES` writer"]
pub type W = crate::W<P1iesSpec>;
#[doc = "Field `P1IES0` reader - P1IES0"]
pub type P1ies0R = crate::BitReader;
#[doc = "Field `P1IES0` writer - P1IES0"]
pub type P1ies0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IES1` reader - P1IES1"]
pub type P1ies1R = crate::BitReader;
#[doc = "Field `P1IES1` writer - P1IES1"]
pub type P1ies1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IES2` reader - P1IES2"]
pub type P1ies2R = crate::BitReader;
#[doc = "Field `P1IES2` writer - P1IES2"]
pub type P1ies2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IES3` reader - P1IES3"]
pub type P1ies3R = crate::BitReader;
#[doc = "Field `P1IES3` writer - P1IES3"]
pub type P1ies3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IES4` reader - P1IES4"]
pub type P1ies4R = crate::BitReader;
#[doc = "Field `P1IES4` writer - P1IES4"]
pub type P1ies4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IES5` reader - P1IES5"]
pub type P1ies5R = crate::BitReader;
#[doc = "Field `P1IES5` writer - P1IES5"]
pub type P1ies5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IES6` reader - P1IES6"]
pub type P1ies6R = crate::BitReader;
#[doc = "Field `P1IES6` writer - P1IES6"]
pub type P1ies6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IES7` reader - P1IES7"]
pub type P1ies7R = crate::BitReader;
#[doc = "Field `P1IES7` writer - P1IES7"]
pub type P1ies7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P1IES0"]
#[inline(always)]
pub fn p1ies0(&self) -> P1ies0R {
P1ies0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P1IES1"]
#[inline(always)]
pub fn p1ies1(&self) -> P1ies1R {
P1ies1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P1IES2"]
#[inline(always)]
pub fn p1ies2(&self) -> P1ies2R {
P1ies2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P1IES3"]
#[inline(always)]
pub fn p1ies3(&self) -> P1ies3R {
P1ies3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P1IES4"]
#[inline(always)]
pub fn p1ies4(&self) -> P1ies4R {
P1ies4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P1IES5"]
#[inline(always)]
pub fn p1ies5(&self) -> P1ies5R {
P1ies5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P1IES6"]
#[inline(always)]
pub fn p1ies6(&self) -> P1ies6R {
P1ies6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P1IES7"]
#[inline(always)]
pub fn p1ies7(&self) -> P1ies7R {
P1ies7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P1IES0"]
#[inline(always)]
pub fn p1ies0(&mut self) -> P1ies0W<'_, P1iesSpec> {
P1ies0W::new(self, 0)
}
#[doc = "Bit 1 - P1IES1"]
#[inline(always)]
pub fn p1ies1(&mut self) -> P1ies1W<'_, P1iesSpec> {
P1ies1W::new(self, 1)
}
#[doc = "Bit 2 - P1IES2"]
#[inline(always)]
pub fn p1ies2(&mut self) -> P1ies2W<'_, P1iesSpec> {
P1ies2W::new(self, 2)
}
#[doc = "Bit 3 - P1IES3"]
#[inline(always)]
pub fn p1ies3(&mut self) -> P1ies3W<'_, P1iesSpec> {
P1ies3W::new(self, 3)
}
#[doc = "Bit 4 - P1IES4"]
#[inline(always)]
pub fn p1ies4(&mut self) -> P1ies4W<'_, P1iesSpec> {
P1ies4W::new(self, 4)
}
#[doc = "Bit 5 - P1IES5"]
#[inline(always)]
pub fn p1ies5(&mut self) -> P1ies5W<'_, P1iesSpec> {
P1ies5W::new(self, 5)
}
#[doc = "Bit 6 - P1IES6"]
#[inline(always)]
pub fn p1ies6(&mut self) -> P1ies6W<'_, P1iesSpec> {
P1ies6W::new(self, 6)
}
#[doc = "Bit 7 - P1IES7"]
#[inline(always)]
pub fn p1ies7(&mut self) -> P1ies7W<'_, P1iesSpec> {
P1ies7W::new(self, 7)
}
}
#[doc = "Port 1 Interrupt Edge Select\n\nYou can [`read`](crate::Reg::read) this register and get [`p1ies::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1ies::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P1iesSpec;
impl crate::RegisterSpec for P1iesSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p1ies::R`](R) reader structure"]
impl crate::Readable for P1iesSpec {}
#[doc = "`write(|w| ..)` method takes [`p1ies::W`](W) writer structure"]
impl crate::Writable for P1iesSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P1IES to value 0"]
impl crate::Resettable for P1iesSpec {}
}
#[doc = "P2IES (rw) register accessor: Port 2 Interrupt Edge Select\n\nYou can [`read`](crate::Reg::read) this register and get [`p2ies::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2ies::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p2ies`] module"]
#[doc(alias = "P2IES")]
pub type P2ies = crate::Reg<p2ies::P2iesSpec>;
#[doc = "Port 2 Interrupt Edge Select"]
pub mod p2ies {
#[doc = "Register `P2IES` reader"]
pub type R = crate::R<P2iesSpec>;
#[doc = "Register `P2IES` writer"]
pub type W = crate::W<P2iesSpec>;
#[doc = "Field `P2IES0` reader - P2IES0"]
pub type P2ies0R = crate::BitReader;
#[doc = "Field `P2IES0` writer - P2IES0"]
pub type P2ies0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IES1` reader - P2IES1"]
pub type P2ies1R = crate::BitReader;
#[doc = "Field `P2IES1` writer - P2IES1"]
pub type P2ies1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IES2` reader - P2IES2"]
pub type P2ies2R = crate::BitReader;
#[doc = "Field `P2IES2` writer - P2IES2"]
pub type P2ies2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IES3` reader - P2IES3"]
pub type P2ies3R = crate::BitReader;
#[doc = "Field `P2IES3` writer - P2IES3"]
pub type P2ies3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IES4` reader - P2IES4"]
pub type P2ies4R = crate::BitReader;
#[doc = "Field `P2IES4` writer - P2IES4"]
pub type P2ies4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IES5` reader - P2IES5"]
pub type P2ies5R = crate::BitReader;
#[doc = "Field `P2IES5` writer - P2IES5"]
pub type P2ies5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IES6` reader - P2IES6"]
pub type P2ies6R = crate::BitReader;
#[doc = "Field `P2IES6` writer - P2IES6"]
pub type P2ies6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IES7` reader - P2IES7"]
pub type P2ies7R = crate::BitReader;
#[doc = "Field `P2IES7` writer - P2IES7"]
pub type P2ies7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P2IES0"]
#[inline(always)]
pub fn p2ies0(&self) -> P2ies0R {
P2ies0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P2IES1"]
#[inline(always)]
pub fn p2ies1(&self) -> P2ies1R {
P2ies1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P2IES2"]
#[inline(always)]
pub fn p2ies2(&self) -> P2ies2R {
P2ies2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P2IES3"]
#[inline(always)]
pub fn p2ies3(&self) -> P2ies3R {
P2ies3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P2IES4"]
#[inline(always)]
pub fn p2ies4(&self) -> P2ies4R {
P2ies4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P2IES5"]
#[inline(always)]
pub fn p2ies5(&self) -> P2ies5R {
P2ies5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P2IES6"]
#[inline(always)]
pub fn p2ies6(&self) -> P2ies6R {
P2ies6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P2IES7"]
#[inline(always)]
pub fn p2ies7(&self) -> P2ies7R {
P2ies7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P2IES0"]
#[inline(always)]
pub fn p2ies0(&mut self) -> P2ies0W<'_, P2iesSpec> {
P2ies0W::new(self, 0)
}
#[doc = "Bit 1 - P2IES1"]
#[inline(always)]
pub fn p2ies1(&mut self) -> P2ies1W<'_, P2iesSpec> {
P2ies1W::new(self, 1)
}
#[doc = "Bit 2 - P2IES2"]
#[inline(always)]
pub fn p2ies2(&mut self) -> P2ies2W<'_, P2iesSpec> {
P2ies2W::new(self, 2)
}
#[doc = "Bit 3 - P2IES3"]
#[inline(always)]
pub fn p2ies3(&mut self) -> P2ies3W<'_, P2iesSpec> {
P2ies3W::new(self, 3)
}
#[doc = "Bit 4 - P2IES4"]
#[inline(always)]
pub fn p2ies4(&mut self) -> P2ies4W<'_, P2iesSpec> {
P2ies4W::new(self, 4)
}
#[doc = "Bit 5 - P2IES5"]
#[inline(always)]
pub fn p2ies5(&mut self) -> P2ies5W<'_, P2iesSpec> {
P2ies5W::new(self, 5)
}
#[doc = "Bit 6 - P2IES6"]
#[inline(always)]
pub fn p2ies6(&mut self) -> P2ies6W<'_, P2iesSpec> {
P2ies6W::new(self, 6)
}
#[doc = "Bit 7 - P2IES7"]
#[inline(always)]
pub fn p2ies7(&mut self) -> P2ies7W<'_, P2iesSpec> {
P2ies7W::new(self, 7)
}
}
#[doc = "Port 2 Interrupt Edge Select\n\nYou can [`read`](crate::Reg::read) this register and get [`p2ies::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2ies::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P2iesSpec;
impl crate::RegisterSpec for P2iesSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p2ies::R`](R) reader structure"]
impl crate::Readable for P2iesSpec {}
#[doc = "`write(|w| ..)` method takes [`p2ies::W`](W) writer structure"]
impl crate::Writable for P2iesSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P2IES to value 0"]
impl crate::Resettable for P2iesSpec {}
}
#[doc = "P1IE (rw) register accessor: Port 1 Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p1ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p1ie`] module"]
#[doc(alias = "P1IE")]
pub type P1ie = crate::Reg<p1ie::P1ieSpec>;
#[doc = "Port 1 Interrupt Enable"]
pub mod p1ie {
#[doc = "Register `P1IE` reader"]
pub type R = crate::R<P1ieSpec>;
#[doc = "Register `P1IE` writer"]
pub type W = crate::W<P1ieSpec>;
#[doc = "Field `P1IE0` reader - P1IE0"]
pub type P1ie0R = crate::BitReader;
#[doc = "Field `P1IE0` writer - P1IE0"]
pub type P1ie0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IE1` reader - P1IE1"]
pub type P1ie1R = crate::BitReader;
#[doc = "Field `P1IE1` writer - P1IE1"]
pub type P1ie1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IE2` reader - P1IE2"]
pub type P1ie2R = crate::BitReader;
#[doc = "Field `P1IE2` writer - P1IE2"]
pub type P1ie2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IE3` reader - P1IE3"]
pub type P1ie3R = crate::BitReader;
#[doc = "Field `P1IE3` writer - P1IE3"]
pub type P1ie3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IE4` reader - P1IE4"]
pub type P1ie4R = crate::BitReader;
#[doc = "Field `P1IE4` writer - P1IE4"]
pub type P1ie4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IE5` reader - P1IE5"]
pub type P1ie5R = crate::BitReader;
#[doc = "Field `P1IE5` writer - P1IE5"]
pub type P1ie5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IE6` reader - P1IE6"]
pub type P1ie6R = crate::BitReader;
#[doc = "Field `P1IE6` writer - P1IE6"]
pub type P1ie6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IE7` reader - P1IE7"]
pub type P1ie7R = crate::BitReader;
#[doc = "Field `P1IE7` writer - P1IE7"]
pub type P1ie7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P1IE0"]
#[inline(always)]
pub fn p1ie0(&self) -> P1ie0R {
P1ie0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P1IE1"]
#[inline(always)]
pub fn p1ie1(&self) -> P1ie1R {
P1ie1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P1IE2"]
#[inline(always)]
pub fn p1ie2(&self) -> P1ie2R {
P1ie2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P1IE3"]
#[inline(always)]
pub fn p1ie3(&self) -> P1ie3R {
P1ie3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P1IE4"]
#[inline(always)]
pub fn p1ie4(&self) -> P1ie4R {
P1ie4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P1IE5"]
#[inline(always)]
pub fn p1ie5(&self) -> P1ie5R {
P1ie5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P1IE6"]
#[inline(always)]
pub fn p1ie6(&self) -> P1ie6R {
P1ie6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P1IE7"]
#[inline(always)]
pub fn p1ie7(&self) -> P1ie7R {
P1ie7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P1IE0"]
#[inline(always)]
pub fn p1ie0(&mut self) -> P1ie0W<'_, P1ieSpec> {
P1ie0W::new(self, 0)
}
#[doc = "Bit 1 - P1IE1"]
#[inline(always)]
pub fn p1ie1(&mut self) -> P1ie1W<'_, P1ieSpec> {
P1ie1W::new(self, 1)
}
#[doc = "Bit 2 - P1IE2"]
#[inline(always)]
pub fn p1ie2(&mut self) -> P1ie2W<'_, P1ieSpec> {
P1ie2W::new(self, 2)
}
#[doc = "Bit 3 - P1IE3"]
#[inline(always)]
pub fn p1ie3(&mut self) -> P1ie3W<'_, P1ieSpec> {
P1ie3W::new(self, 3)
}
#[doc = "Bit 4 - P1IE4"]
#[inline(always)]
pub fn p1ie4(&mut self) -> P1ie4W<'_, P1ieSpec> {
P1ie4W::new(self, 4)
}
#[doc = "Bit 5 - P1IE5"]
#[inline(always)]
pub fn p1ie5(&mut self) -> P1ie5W<'_, P1ieSpec> {
P1ie5W::new(self, 5)
}
#[doc = "Bit 6 - P1IE6"]
#[inline(always)]
pub fn p1ie6(&mut self) -> P1ie6W<'_, P1ieSpec> {
P1ie6W::new(self, 6)
}
#[doc = "Bit 7 - P1IE7"]
#[inline(always)]
pub fn p1ie7(&mut self) -> P1ie7W<'_, P1ieSpec> {
P1ie7W::new(self, 7)
}
}
#[doc = "Port 1 Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p1ie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1ie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P1ieSpec;
impl crate::RegisterSpec for P1ieSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p1ie::R`](R) reader structure"]
impl crate::Readable for P1ieSpec {}
#[doc = "`write(|w| ..)` method takes [`p1ie::W`](W) writer structure"]
impl crate::Writable for P1ieSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P1IE to value 0"]
impl crate::Resettable for P1ieSpec {}
}
#[doc = "P2IE (rw) register accessor: Port 2 Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p2ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p2ie`] module"]
#[doc(alias = "P2IE")]
pub type P2ie = crate::Reg<p2ie::P2ieSpec>;
#[doc = "Port 2 Interrupt Enable"]
pub mod p2ie {
#[doc = "Register `P2IE` reader"]
pub type R = crate::R<P2ieSpec>;
#[doc = "Register `P2IE` writer"]
pub type W = crate::W<P2ieSpec>;
#[doc = "Field `P2IE0` reader - P2IE0"]
pub type P2ie0R = crate::BitReader;
#[doc = "Field `P2IE0` writer - P2IE0"]
pub type P2ie0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IE1` reader - P2IE1"]
pub type P2ie1R = crate::BitReader;
#[doc = "Field `P2IE1` writer - P2IE1"]
pub type P2ie1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IE2` reader - P2IE2"]
pub type P2ie2R = crate::BitReader;
#[doc = "Field `P2IE2` writer - P2IE2"]
pub type P2ie2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IE3` reader - P2IE3"]
pub type P2ie3R = crate::BitReader;
#[doc = "Field `P2IE3` writer - P2IE3"]
pub type P2ie3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IE4` reader - P2IE4"]
pub type P2ie4R = crate::BitReader;
#[doc = "Field `P2IE4` writer - P2IE4"]
pub type P2ie4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IE5` reader - P2IE5"]
pub type P2ie5R = crate::BitReader;
#[doc = "Field `P2IE5` writer - P2IE5"]
pub type P2ie5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IE6` reader - P2IE6"]
pub type P2ie6R = crate::BitReader;
#[doc = "Field `P2IE6` writer - P2IE6"]
pub type P2ie6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IE7` reader - P2IE7"]
pub type P2ie7R = crate::BitReader;
#[doc = "Field `P2IE7` writer - P2IE7"]
pub type P2ie7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P2IE0"]
#[inline(always)]
pub fn p2ie0(&self) -> P2ie0R {
P2ie0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P2IE1"]
#[inline(always)]
pub fn p2ie1(&self) -> P2ie1R {
P2ie1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P2IE2"]
#[inline(always)]
pub fn p2ie2(&self) -> P2ie2R {
P2ie2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P2IE3"]
#[inline(always)]
pub fn p2ie3(&self) -> P2ie3R {
P2ie3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P2IE4"]
#[inline(always)]
pub fn p2ie4(&self) -> P2ie4R {
P2ie4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P2IE5"]
#[inline(always)]
pub fn p2ie5(&self) -> P2ie5R {
P2ie5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P2IE6"]
#[inline(always)]
pub fn p2ie6(&self) -> P2ie6R {
P2ie6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P2IE7"]
#[inline(always)]
pub fn p2ie7(&self) -> P2ie7R {
P2ie7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P2IE0"]
#[inline(always)]
pub fn p2ie0(&mut self) -> P2ie0W<'_, P2ieSpec> {
P2ie0W::new(self, 0)
}
#[doc = "Bit 1 - P2IE1"]
#[inline(always)]
pub fn p2ie1(&mut self) -> P2ie1W<'_, P2ieSpec> {
P2ie1W::new(self, 1)
}
#[doc = "Bit 2 - P2IE2"]
#[inline(always)]
pub fn p2ie2(&mut self) -> P2ie2W<'_, P2ieSpec> {
P2ie2W::new(self, 2)
}
#[doc = "Bit 3 - P2IE3"]
#[inline(always)]
pub fn p2ie3(&mut self) -> P2ie3W<'_, P2ieSpec> {
P2ie3W::new(self, 3)
}
#[doc = "Bit 4 - P2IE4"]
#[inline(always)]
pub fn p2ie4(&mut self) -> P2ie4W<'_, P2ieSpec> {
P2ie4W::new(self, 4)
}
#[doc = "Bit 5 - P2IE5"]
#[inline(always)]
pub fn p2ie5(&mut self) -> P2ie5W<'_, P2ieSpec> {
P2ie5W::new(self, 5)
}
#[doc = "Bit 6 - P2IE6"]
#[inline(always)]
pub fn p2ie6(&mut self) -> P2ie6W<'_, P2ieSpec> {
P2ie6W::new(self, 6)
}
#[doc = "Bit 7 - P2IE7"]
#[inline(always)]
pub fn p2ie7(&mut self) -> P2ie7W<'_, P2ieSpec> {
P2ie7W::new(self, 7)
}
}
#[doc = "Port 2 Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p2ie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2ie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P2ieSpec;
impl crate::RegisterSpec for P2ieSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p2ie::R`](R) reader structure"]
impl crate::Readable for P2ieSpec {}
#[doc = "`write(|w| ..)` method takes [`p2ie::W`](W) writer structure"]
impl crate::Writable for P2ieSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P2IE to value 0"]
impl crate::Resettable for P2ieSpec {}
}
#[doc = "P1IFG (rw) register accessor: Port 1 Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`p1ifg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1ifg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p1ifg`] module"]
#[doc(alias = "P1IFG")]
pub type P1ifg = crate::Reg<p1ifg::P1ifgSpec>;
#[doc = "Port 1 Interrupt Flag"]
pub mod p1ifg {
#[doc = "Register `P1IFG` reader"]
pub type R = crate::R<P1ifgSpec>;
#[doc = "Register `P1IFG` writer"]
pub type W = crate::W<P1ifgSpec>;
#[doc = "Field `P1IFG0` reader - P1IFG0"]
pub type P1ifg0R = crate::BitReader;
#[doc = "Field `P1IFG0` writer - P1IFG0"]
pub type P1ifg0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IFG1` reader - P1IFG1"]
pub type P1ifg1R = crate::BitReader;
#[doc = "Field `P1IFG1` writer - P1IFG1"]
pub type P1ifg1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IFG2` reader - P1IFG2"]
pub type P1ifg2R = crate::BitReader;
#[doc = "Field `P1IFG2` writer - P1IFG2"]
pub type P1ifg2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IFG3` reader - P1IFG3"]
pub type P1ifg3R = crate::BitReader;
#[doc = "Field `P1IFG3` writer - P1IFG3"]
pub type P1ifg3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IFG4` reader - P1IFG4"]
pub type P1ifg4R = crate::BitReader;
#[doc = "Field `P1IFG4` writer - P1IFG4"]
pub type P1ifg4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IFG5` reader - P1IFG5"]
pub type P1ifg5R = crate::BitReader;
#[doc = "Field `P1IFG5` writer - P1IFG5"]
pub type P1ifg5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IFG6` reader - P1IFG6"]
pub type P1ifg6R = crate::BitReader;
#[doc = "Field `P1IFG6` writer - P1IFG6"]
pub type P1ifg6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P1IFG7` reader - P1IFG7"]
pub type P1ifg7R = crate::BitReader;
#[doc = "Field `P1IFG7` writer - P1IFG7"]
pub type P1ifg7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P1IFG0"]
#[inline(always)]
pub fn p1ifg0(&self) -> P1ifg0R {
P1ifg0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P1IFG1"]
#[inline(always)]
pub fn p1ifg1(&self) -> P1ifg1R {
P1ifg1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P1IFG2"]
#[inline(always)]
pub fn p1ifg2(&self) -> P1ifg2R {
P1ifg2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P1IFG3"]
#[inline(always)]
pub fn p1ifg3(&self) -> P1ifg3R {
P1ifg3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P1IFG4"]
#[inline(always)]
pub fn p1ifg4(&self) -> P1ifg4R {
P1ifg4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P1IFG5"]
#[inline(always)]
pub fn p1ifg5(&self) -> P1ifg5R {
P1ifg5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P1IFG6"]
#[inline(always)]
pub fn p1ifg6(&self) -> P1ifg6R {
P1ifg6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P1IFG7"]
#[inline(always)]
pub fn p1ifg7(&self) -> P1ifg7R {
P1ifg7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P1IFG0"]
#[inline(always)]
pub fn p1ifg0(&mut self) -> P1ifg0W<'_, P1ifgSpec> {
P1ifg0W::new(self, 0)
}
#[doc = "Bit 1 - P1IFG1"]
#[inline(always)]
pub fn p1ifg1(&mut self) -> P1ifg1W<'_, P1ifgSpec> {
P1ifg1W::new(self, 1)
}
#[doc = "Bit 2 - P1IFG2"]
#[inline(always)]
pub fn p1ifg2(&mut self) -> P1ifg2W<'_, P1ifgSpec> {
P1ifg2W::new(self, 2)
}
#[doc = "Bit 3 - P1IFG3"]
#[inline(always)]
pub fn p1ifg3(&mut self) -> P1ifg3W<'_, P1ifgSpec> {
P1ifg3W::new(self, 3)
}
#[doc = "Bit 4 - P1IFG4"]
#[inline(always)]
pub fn p1ifg4(&mut self) -> P1ifg4W<'_, P1ifgSpec> {
P1ifg4W::new(self, 4)
}
#[doc = "Bit 5 - P1IFG5"]
#[inline(always)]
pub fn p1ifg5(&mut self) -> P1ifg5W<'_, P1ifgSpec> {
P1ifg5W::new(self, 5)
}
#[doc = "Bit 6 - P1IFG6"]
#[inline(always)]
pub fn p1ifg6(&mut self) -> P1ifg6W<'_, P1ifgSpec> {
P1ifg6W::new(self, 6)
}
#[doc = "Bit 7 - P1IFG7"]
#[inline(always)]
pub fn p1ifg7(&mut self) -> P1ifg7W<'_, P1ifgSpec> {
P1ifg7W::new(self, 7)
}
}
#[doc = "Port 1 Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`p1ifg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1ifg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P1ifgSpec;
impl crate::RegisterSpec for P1ifgSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p1ifg::R`](R) reader structure"]
impl crate::Readable for P1ifgSpec {}
#[doc = "`write(|w| ..)` method takes [`p1ifg::W`](W) writer structure"]
impl crate::Writable for P1ifgSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P1IFG to value 0"]
impl crate::Resettable for P1ifgSpec {}
}
#[doc = "P2IFG (rw) register accessor: Port 2 Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`p2ifg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2ifg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p2ifg`] module"]
#[doc(alias = "P2IFG")]
pub type P2ifg = crate::Reg<p2ifg::P2ifgSpec>;
#[doc = "Port 2 Interrupt Flag"]
pub mod p2ifg {
#[doc = "Register `P2IFG` reader"]
pub type R = crate::R<P2ifgSpec>;
#[doc = "Register `P2IFG` writer"]
pub type W = crate::W<P2ifgSpec>;
#[doc = "Field `P2IFG0` reader - P2IFG0"]
pub type P2ifg0R = crate::BitReader;
#[doc = "Field `P2IFG0` writer - P2IFG0"]
pub type P2ifg0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IFG1` reader - P2IFG1"]
pub type P2ifg1R = crate::BitReader;
#[doc = "Field `P2IFG1` writer - P2IFG1"]
pub type P2ifg1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IFG2` reader - P2IFG2"]
pub type P2ifg2R = crate::BitReader;
#[doc = "Field `P2IFG2` writer - P2IFG2"]
pub type P2ifg2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IFG3` reader - P2IFG3"]
pub type P2ifg3R = crate::BitReader;
#[doc = "Field `P2IFG3` writer - P2IFG3"]
pub type P2ifg3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IFG4` reader - P2IFG4"]
pub type P2ifg4R = crate::BitReader;
#[doc = "Field `P2IFG4` writer - P2IFG4"]
pub type P2ifg4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IFG5` reader - P2IFG5"]
pub type P2ifg5R = crate::BitReader;
#[doc = "Field `P2IFG5` writer - P2IFG5"]
pub type P2ifg5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IFG6` reader - P2IFG6"]
pub type P2ifg6R = crate::BitReader;
#[doc = "Field `P2IFG6` writer - P2IFG6"]
pub type P2ifg6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P2IFG7` reader - P2IFG7"]
pub type P2ifg7R = crate::BitReader;
#[doc = "Field `P2IFG7` writer - P2IFG7"]
pub type P2ifg7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P2IFG0"]
#[inline(always)]
pub fn p2ifg0(&self) -> P2ifg0R {
P2ifg0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P2IFG1"]
#[inline(always)]
pub fn p2ifg1(&self) -> P2ifg1R {
P2ifg1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P2IFG2"]
#[inline(always)]
pub fn p2ifg2(&self) -> P2ifg2R {
P2ifg2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P2IFG3"]
#[inline(always)]
pub fn p2ifg3(&self) -> P2ifg3R {
P2ifg3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P2IFG4"]
#[inline(always)]
pub fn p2ifg4(&self) -> P2ifg4R {
P2ifg4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P2IFG5"]
#[inline(always)]
pub fn p2ifg5(&self) -> P2ifg5R {
P2ifg5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P2IFG6"]
#[inline(always)]
pub fn p2ifg6(&self) -> P2ifg6R {
P2ifg6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P2IFG7"]
#[inline(always)]
pub fn p2ifg7(&self) -> P2ifg7R {
P2ifg7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P2IFG0"]
#[inline(always)]
pub fn p2ifg0(&mut self) -> P2ifg0W<'_, P2ifgSpec> {
P2ifg0W::new(self, 0)
}
#[doc = "Bit 1 - P2IFG1"]
#[inline(always)]
pub fn p2ifg1(&mut self) -> P2ifg1W<'_, P2ifgSpec> {
P2ifg1W::new(self, 1)
}
#[doc = "Bit 2 - P2IFG2"]
#[inline(always)]
pub fn p2ifg2(&mut self) -> P2ifg2W<'_, P2ifgSpec> {
P2ifg2W::new(self, 2)
}
#[doc = "Bit 3 - P2IFG3"]
#[inline(always)]
pub fn p2ifg3(&mut self) -> P2ifg3W<'_, P2ifgSpec> {
P2ifg3W::new(self, 3)
}
#[doc = "Bit 4 - P2IFG4"]
#[inline(always)]
pub fn p2ifg4(&mut self) -> P2ifg4W<'_, P2ifgSpec> {
P2ifg4W::new(self, 4)
}
#[doc = "Bit 5 - P2IFG5"]
#[inline(always)]
pub fn p2ifg5(&mut self) -> P2ifg5W<'_, P2ifgSpec> {
P2ifg5W::new(self, 5)
}
#[doc = "Bit 6 - P2IFG6"]
#[inline(always)]
pub fn p2ifg6(&mut self) -> P2ifg6W<'_, P2ifgSpec> {
P2ifg6W::new(self, 6)
}
#[doc = "Bit 7 - P2IFG7"]
#[inline(always)]
pub fn p2ifg7(&mut self) -> P2ifg7W<'_, P2ifgSpec> {
P2ifg7W::new(self, 7)
}
}
#[doc = "Port 2 Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`p2ifg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2ifg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P2ifgSpec;
impl crate::RegisterSpec for P2ifgSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p2ifg::R`](R) reader structure"]
impl crate::Readable for P2ifgSpec {}
#[doc = "`write(|w| ..)` method takes [`p2ifg::W`](W) writer structure"]
impl crate::Writable for P2ifgSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P2IFG to value 0"]
impl crate::Resettable for P2ifgSpec {}
}
#[doc = "P1IV (rw) register accessor: Port 1 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`p1iv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1iv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p1iv`] module"]
#[doc(alias = "P1IV")]
pub type P1iv = crate::Reg<p1iv::P1ivSpec>;
#[doc = "Port 1 Interrupt Vector Word"]
pub mod p1iv {
#[doc = "Register `P1IV` reader"]
pub type R = crate::R<P1ivSpec>;
#[doc = "Register `P1IV` writer"]
pub type W = crate::W<P1ivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Port 1 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`p1iv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p1iv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P1ivSpec;
impl crate::RegisterSpec for P1ivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`p1iv::R`](R) reader structure"]
impl crate::Readable for P1ivSpec {}
#[doc = "`write(|w| ..)` method takes [`p1iv::W`](W) writer structure"]
impl crate::Writable for P1ivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets P1IV to value 0"]
impl crate::Resettable for P1ivSpec {}
}
#[doc = "P2IV (rw) register accessor: Port 2 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`p2iv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2iv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p2iv`] module"]
#[doc(alias = "P2IV")]
pub type P2iv = crate::Reg<p2iv::P2ivSpec>;
#[doc = "Port 2 Interrupt Vector Word"]
pub mod p2iv {
#[doc = "Register `P2IV` reader"]
pub type R = crate::R<P2ivSpec>;
#[doc = "Register `P2IV` writer"]
pub type W = crate::W<P2ivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Port 2 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`p2iv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p2iv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P2ivSpec;
impl crate::RegisterSpec for P2ivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`p2iv::R`](R) reader structure"]
impl crate::Readable for P2ivSpec {}
#[doc = "`write(|w| ..)` method takes [`p2iv::W`](W) writer structure"]
impl crate::Writable for P2ivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets P2IV to value 0"]
impl crate::Resettable for P2ivSpec {}
}
}
#[doc = "Port 3/4"]
pub type Port3_4 = crate::Periph<port_3_4::RegisterBlock, 0x0220>;
impl core::fmt::Debug for Port3_4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Port3_4").finish()
}
}
#[doc = "Port 3/4"]
pub mod port_3_4 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
p3in: P3in,
p4in: P4in,
p3out: P3out,
p4out: P4out,
p3dir: P3dir,
p4dir: P4dir,
p3ren: P3ren,
p4ren: P4ren,
_reserved8: [u8; 0x02],
p3sel0: P3sel0,
p4sel0: P4sel0,
p3sel1: P3sel1,
p4sel1: P4sel1,
p3iv: P3iv,
_reserved13: [u8; 0x06],
p3selc: P3selc,
p4selc: P4selc,
p3ies: P3ies,
p4ies: P4ies,
p3ie: P3ie,
p4ie: P4ie,
p3ifg: P3ifg,
p4ifg: P4ifg,
p4iv: P4iv,
}
impl RegisterBlock {
#[doc = "0x00 - Port 3 Input"]
#[inline(always)]
pub const fn p3in(&self) -> &P3in {
&self.p3in
}
#[doc = "0x01 - Port 4 Input"]
#[inline(always)]
pub const fn p4in(&self) -> &P4in {
&self.p4in
}
#[doc = "0x02 - Port 3 Output"]
#[inline(always)]
pub const fn p3out(&self) -> &P3out {
&self.p3out
}
#[doc = "0x03 - Port 4 Output"]
#[inline(always)]
pub const fn p4out(&self) -> &P4out {
&self.p4out
}
#[doc = "0x04 - Port 3 Direction"]
#[inline(always)]
pub const fn p3dir(&self) -> &P3dir {
&self.p3dir
}
#[doc = "0x05 - Port 4 Direction"]
#[inline(always)]
pub const fn p4dir(&self) -> &P4dir {
&self.p4dir
}
#[doc = "0x06 - Port 3 Resistor Enable"]
#[inline(always)]
pub const fn p3ren(&self) -> &P3ren {
&self.p3ren
}
#[doc = "0x07 - Port 4 Resistor Enable"]
#[inline(always)]
pub const fn p4ren(&self) -> &P4ren {
&self.p4ren
}
#[doc = "0x0a - Port 3 Selection 0"]
#[inline(always)]
pub const fn p3sel0(&self) -> &P3sel0 {
&self.p3sel0
}
#[doc = "0x0b - Port 4 Selection 0"]
#[inline(always)]
pub const fn p4sel0(&self) -> &P4sel0 {
&self.p4sel0
}
#[doc = "0x0c - Port 3 Selection 1"]
#[inline(always)]
pub const fn p3sel1(&self) -> &P3sel1 {
&self.p3sel1
}
#[doc = "0x0d - Port 4 Selection 1"]
#[inline(always)]
pub const fn p4sel1(&self) -> &P4sel1 {
&self.p4sel1
}
#[doc = "0x0e - Port 3 Interrupt Vector Word"]
#[inline(always)]
pub const fn p3iv(&self) -> &P3iv {
&self.p3iv
}
#[doc = "0x16 - Port 3 Complement Selection"]
#[inline(always)]
pub const fn p3selc(&self) -> &P3selc {
&self.p3selc
}
#[doc = "0x17 - Port 4 Complement Selection"]
#[inline(always)]
pub const fn p4selc(&self) -> &P4selc {
&self.p4selc
}
#[doc = "0x18 - Port 3 Interrupt Edge Select"]
#[inline(always)]
pub const fn p3ies(&self) -> &P3ies {
&self.p3ies
}
#[doc = "0x19 - Port 4 Interrupt Edge Select"]
#[inline(always)]
pub const fn p4ies(&self) -> &P4ies {
&self.p4ies
}
#[doc = "0x1a - Port 3 Interrupt Enable"]
#[inline(always)]
pub const fn p3ie(&self) -> &P3ie {
&self.p3ie
}
#[doc = "0x1b - Port 4 Interrupt Enable"]
#[inline(always)]
pub const fn p4ie(&self) -> &P4ie {
&self.p4ie
}
#[doc = "0x1c - Port 3 Interrupt Flag"]
#[inline(always)]
pub const fn p3ifg(&self) -> &P3ifg {
&self.p3ifg
}
#[doc = "0x1d - Port 4 Interrupt Flag"]
#[inline(always)]
pub const fn p4ifg(&self) -> &P4ifg {
&self.p4ifg
}
#[doc = "0x1e - Port 4 Interrupt Vector Word"]
#[inline(always)]
pub const fn p4iv(&self) -> &P4iv {
&self.p4iv
}
}
#[doc = "P3IN (rw) register accessor: Port 3 Input\n\nYou can [`read`](crate::Reg::read) this register and get [`p3in::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3in::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3in`] module"]
#[doc(alias = "P3IN")]
pub type P3in = crate::Reg<p3in::P3inSpec>;
#[doc = "Port 3 Input"]
pub mod p3in {
#[doc = "Register `P3IN` reader"]
pub type R = crate::R<P3inSpec>;
#[doc = "Register `P3IN` writer"]
pub type W = crate::W<P3inSpec>;
#[doc = "Field `P3IN0` reader - P3IN0"]
pub type P3in0R = crate::BitReader;
#[doc = "Field `P3IN0` writer - P3IN0"]
pub type P3in0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IN1` reader - P3IN1"]
pub type P3in1R = crate::BitReader;
#[doc = "Field `P3IN1` writer - P3IN1"]
pub type P3in1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IN2` reader - P3IN2"]
pub type P3in2R = crate::BitReader;
#[doc = "Field `P3IN2` writer - P3IN2"]
pub type P3in2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IN3` reader - P3IN3"]
pub type P3in3R = crate::BitReader;
#[doc = "Field `P3IN3` writer - P3IN3"]
pub type P3in3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IN4` reader - P3IN4"]
pub type P3in4R = crate::BitReader;
#[doc = "Field `P3IN4` writer - P3IN4"]
pub type P3in4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IN5` reader - P3IN5"]
pub type P3in5R = crate::BitReader;
#[doc = "Field `P3IN5` writer - P3IN5"]
pub type P3in5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IN6` reader - P3IN6"]
pub type P3in6R = crate::BitReader;
#[doc = "Field `P3IN6` writer - P3IN6"]
pub type P3in6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IN7` reader - P3IN7"]
pub type P3in7R = crate::BitReader;
#[doc = "Field `P3IN7` writer - P3IN7"]
pub type P3in7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P3IN0"]
#[inline(always)]
pub fn p3in0(&self) -> P3in0R {
P3in0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P3IN1"]
#[inline(always)]
pub fn p3in1(&self) -> P3in1R {
P3in1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P3IN2"]
#[inline(always)]
pub fn p3in2(&self) -> P3in2R {
P3in2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P3IN3"]
#[inline(always)]
pub fn p3in3(&self) -> P3in3R {
P3in3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P3IN4"]
#[inline(always)]
pub fn p3in4(&self) -> P3in4R {
P3in4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P3IN5"]
#[inline(always)]
pub fn p3in5(&self) -> P3in5R {
P3in5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P3IN6"]
#[inline(always)]
pub fn p3in6(&self) -> P3in6R {
P3in6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P3IN7"]
#[inline(always)]
pub fn p3in7(&self) -> P3in7R {
P3in7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P3IN0"]
#[inline(always)]
pub fn p3in0(&mut self) -> P3in0W<'_, P3inSpec> {
P3in0W::new(self, 0)
}
#[doc = "Bit 1 - P3IN1"]
#[inline(always)]
pub fn p3in1(&mut self) -> P3in1W<'_, P3inSpec> {
P3in1W::new(self, 1)
}
#[doc = "Bit 2 - P3IN2"]
#[inline(always)]
pub fn p3in2(&mut self) -> P3in2W<'_, P3inSpec> {
P3in2W::new(self, 2)
}
#[doc = "Bit 3 - P3IN3"]
#[inline(always)]
pub fn p3in3(&mut self) -> P3in3W<'_, P3inSpec> {
P3in3W::new(self, 3)
}
#[doc = "Bit 4 - P3IN4"]
#[inline(always)]
pub fn p3in4(&mut self) -> P3in4W<'_, P3inSpec> {
P3in4W::new(self, 4)
}
#[doc = "Bit 5 - P3IN5"]
#[inline(always)]
pub fn p3in5(&mut self) -> P3in5W<'_, P3inSpec> {
P3in5W::new(self, 5)
}
#[doc = "Bit 6 - P3IN6"]
#[inline(always)]
pub fn p3in6(&mut self) -> P3in6W<'_, P3inSpec> {
P3in6W::new(self, 6)
}
#[doc = "Bit 7 - P3IN7"]
#[inline(always)]
pub fn p3in7(&mut self) -> P3in7W<'_, P3inSpec> {
P3in7W::new(self, 7)
}
}
#[doc = "Port 3 Input\n\nYou can [`read`](crate::Reg::read) this register and get [`p3in::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3in::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P3inSpec;
impl crate::RegisterSpec for P3inSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p3in::R`](R) reader structure"]
impl crate::Readable for P3inSpec {}
#[doc = "`write(|w| ..)` method takes [`p3in::W`](W) writer structure"]
impl crate::Writable for P3inSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P3IN to value 0"]
impl crate::Resettable for P3inSpec {}
}
#[doc = "P4IN (rw) register accessor: Port 4 Input\n\nYou can [`read`](crate::Reg::read) this register and get [`p4in::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4in::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p4in`] module"]
#[doc(alias = "P4IN")]
pub type P4in = crate::Reg<p4in::P4inSpec>;
#[doc = "Port 4 Input"]
pub mod p4in {
#[doc = "Register `P4IN` reader"]
pub type R = crate::R<P4inSpec>;
#[doc = "Register `P4IN` writer"]
pub type W = crate::W<P4inSpec>;
#[doc = "Field `P4IN0` reader - P4IN0"]
pub type P4in0R = crate::BitReader;
#[doc = "Field `P4IN0` writer - P4IN0"]
pub type P4in0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IN1` reader - P4IN1"]
pub type P4in1R = crate::BitReader;
#[doc = "Field `P4IN1` writer - P4IN1"]
pub type P4in1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IN2` reader - P4IN2"]
pub type P4in2R = crate::BitReader;
#[doc = "Field `P4IN2` writer - P4IN2"]
pub type P4in2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IN3` reader - P4IN3"]
pub type P4in3R = crate::BitReader;
#[doc = "Field `P4IN3` writer - P4IN3"]
pub type P4in3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IN4` reader - P4IN4"]
pub type P4in4R = crate::BitReader;
#[doc = "Field `P4IN4` writer - P4IN4"]
pub type P4in4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IN5` reader - P4IN5"]
pub type P4in5R = crate::BitReader;
#[doc = "Field `P4IN5` writer - P4IN5"]
pub type P4in5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IN6` reader - P4IN6"]
pub type P4in6R = crate::BitReader;
#[doc = "Field `P4IN6` writer - P4IN6"]
pub type P4in6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IN7` reader - P4IN7"]
pub type P4in7R = crate::BitReader;
#[doc = "Field `P4IN7` writer - P4IN7"]
pub type P4in7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P4IN0"]
#[inline(always)]
pub fn p4in0(&self) -> P4in0R {
P4in0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P4IN1"]
#[inline(always)]
pub fn p4in1(&self) -> P4in1R {
P4in1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P4IN2"]
#[inline(always)]
pub fn p4in2(&self) -> P4in2R {
P4in2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P4IN3"]
#[inline(always)]
pub fn p4in3(&self) -> P4in3R {
P4in3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P4IN4"]
#[inline(always)]
pub fn p4in4(&self) -> P4in4R {
P4in4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P4IN5"]
#[inline(always)]
pub fn p4in5(&self) -> P4in5R {
P4in5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P4IN6"]
#[inline(always)]
pub fn p4in6(&self) -> P4in6R {
P4in6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P4IN7"]
#[inline(always)]
pub fn p4in7(&self) -> P4in7R {
P4in7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P4IN0"]
#[inline(always)]
pub fn p4in0(&mut self) -> P4in0W<'_, P4inSpec> {
P4in0W::new(self, 0)
}
#[doc = "Bit 1 - P4IN1"]
#[inline(always)]
pub fn p4in1(&mut self) -> P4in1W<'_, P4inSpec> {
P4in1W::new(self, 1)
}
#[doc = "Bit 2 - P4IN2"]
#[inline(always)]
pub fn p4in2(&mut self) -> P4in2W<'_, P4inSpec> {
P4in2W::new(self, 2)
}
#[doc = "Bit 3 - P4IN3"]
#[inline(always)]
pub fn p4in3(&mut self) -> P4in3W<'_, P4inSpec> {
P4in3W::new(self, 3)
}
#[doc = "Bit 4 - P4IN4"]
#[inline(always)]
pub fn p4in4(&mut self) -> P4in4W<'_, P4inSpec> {
P4in4W::new(self, 4)
}
#[doc = "Bit 5 - P4IN5"]
#[inline(always)]
pub fn p4in5(&mut self) -> P4in5W<'_, P4inSpec> {
P4in5W::new(self, 5)
}
#[doc = "Bit 6 - P4IN6"]
#[inline(always)]
pub fn p4in6(&mut self) -> P4in6W<'_, P4inSpec> {
P4in6W::new(self, 6)
}
#[doc = "Bit 7 - P4IN7"]
#[inline(always)]
pub fn p4in7(&mut self) -> P4in7W<'_, P4inSpec> {
P4in7W::new(self, 7)
}
}
#[doc = "Port 4 Input\n\nYou can [`read`](crate::Reg::read) this register and get [`p4in::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4in::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P4inSpec;
impl crate::RegisterSpec for P4inSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p4in::R`](R) reader structure"]
impl crate::Readable for P4inSpec {}
#[doc = "`write(|w| ..)` method takes [`p4in::W`](W) writer structure"]
impl crate::Writable for P4inSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P4IN to value 0"]
impl crate::Resettable for P4inSpec {}
}
#[doc = "P3OUT (rw) register accessor: Port 3 Output\n\nYou can [`read`](crate::Reg::read) this register and get [`p3out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3out`] module"]
#[doc(alias = "P3OUT")]
pub type P3out = crate::Reg<p3out::P3outSpec>;
#[doc = "Port 3 Output"]
pub mod p3out {
#[doc = "Register `P3OUT` reader"]
pub type R = crate::R<P3outSpec>;
#[doc = "Register `P3OUT` writer"]
pub type W = crate::W<P3outSpec>;
#[doc = "Field `P3OUT0` reader - P3OUT0"]
pub type P3out0R = crate::BitReader;
#[doc = "Field `P3OUT0` writer - P3OUT0"]
pub type P3out0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3OUT1` reader - P3OUT1"]
pub type P3out1R = crate::BitReader;
#[doc = "Field `P3OUT1` writer - P3OUT1"]
pub type P3out1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3OUT2` reader - P3OUT2"]
pub type P3out2R = crate::BitReader;
#[doc = "Field `P3OUT2` writer - P3OUT2"]
pub type P3out2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3OUT3` reader - P3OUT3"]
pub type P3out3R = crate::BitReader;
#[doc = "Field `P3OUT3` writer - P3OUT3"]
pub type P3out3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3OUT4` reader - P3OUT4"]
pub type P3out4R = crate::BitReader;
#[doc = "Field `P3OUT4` writer - P3OUT4"]
pub type P3out4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3OUT5` reader - P3OUT5"]
pub type P3out5R = crate::BitReader;
#[doc = "Field `P3OUT5` writer - P3OUT5"]
pub type P3out5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3OUT6` reader - P3OUT6"]
pub type P3out6R = crate::BitReader;
#[doc = "Field `P3OUT6` writer - P3OUT6"]
pub type P3out6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3OUT7` reader - P3OUT7"]
pub type P3out7R = crate::BitReader;
#[doc = "Field `P3OUT7` writer - P3OUT7"]
pub type P3out7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P3OUT0"]
#[inline(always)]
pub fn p3out0(&self) -> P3out0R {
P3out0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P3OUT1"]
#[inline(always)]
pub fn p3out1(&self) -> P3out1R {
P3out1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P3OUT2"]
#[inline(always)]
pub fn p3out2(&self) -> P3out2R {
P3out2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P3OUT3"]
#[inline(always)]
pub fn p3out3(&self) -> P3out3R {
P3out3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P3OUT4"]
#[inline(always)]
pub fn p3out4(&self) -> P3out4R {
P3out4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P3OUT5"]
#[inline(always)]
pub fn p3out5(&self) -> P3out5R {
P3out5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P3OUT6"]
#[inline(always)]
pub fn p3out6(&self) -> P3out6R {
P3out6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P3OUT7"]
#[inline(always)]
pub fn p3out7(&self) -> P3out7R {
P3out7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P3OUT0"]
#[inline(always)]
pub fn p3out0(&mut self) -> P3out0W<'_, P3outSpec> {
P3out0W::new(self, 0)
}
#[doc = "Bit 1 - P3OUT1"]
#[inline(always)]
pub fn p3out1(&mut self) -> P3out1W<'_, P3outSpec> {
P3out1W::new(self, 1)
}
#[doc = "Bit 2 - P3OUT2"]
#[inline(always)]
pub fn p3out2(&mut self) -> P3out2W<'_, P3outSpec> {
P3out2W::new(self, 2)
}
#[doc = "Bit 3 - P3OUT3"]
#[inline(always)]
pub fn p3out3(&mut self) -> P3out3W<'_, P3outSpec> {
P3out3W::new(self, 3)
}
#[doc = "Bit 4 - P3OUT4"]
#[inline(always)]
pub fn p3out4(&mut self) -> P3out4W<'_, P3outSpec> {
P3out4W::new(self, 4)
}
#[doc = "Bit 5 - P3OUT5"]
#[inline(always)]
pub fn p3out5(&mut self) -> P3out5W<'_, P3outSpec> {
P3out5W::new(self, 5)
}
#[doc = "Bit 6 - P3OUT6"]
#[inline(always)]
pub fn p3out6(&mut self) -> P3out6W<'_, P3outSpec> {
P3out6W::new(self, 6)
}
#[doc = "Bit 7 - P3OUT7"]
#[inline(always)]
pub fn p3out7(&mut self) -> P3out7W<'_, P3outSpec> {
P3out7W::new(self, 7)
}
}
#[doc = "Port 3 Output\n\nYou can [`read`](crate::Reg::read) this register and get [`p3out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P3outSpec;
impl crate::RegisterSpec for P3outSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p3out::R`](R) reader structure"]
impl crate::Readable for P3outSpec {}
#[doc = "`write(|w| ..)` method takes [`p3out::W`](W) writer structure"]
impl crate::Writable for P3outSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P3OUT to value 0"]
impl crate::Resettable for P3outSpec {}
}
#[doc = "P4OUT (rw) register accessor: Port 4 Output\n\nYou can [`read`](crate::Reg::read) this register and get [`p4out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p4out`] module"]
#[doc(alias = "P4OUT")]
pub type P4out = crate::Reg<p4out::P4outSpec>;
#[doc = "Port 4 Output"]
pub mod p4out {
#[doc = "Register `P4OUT` reader"]
pub type R = crate::R<P4outSpec>;
#[doc = "Register `P4OUT` writer"]
pub type W = crate::W<P4outSpec>;
#[doc = "Field `P4OUT0` reader - P4OUT0"]
pub type P4out0R = crate::BitReader;
#[doc = "Field `P4OUT0` writer - P4OUT0"]
pub type P4out0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4OUT1` reader - P4OUT1"]
pub type P4out1R = crate::BitReader;
#[doc = "Field `P4OUT1` writer - P4OUT1"]
pub type P4out1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4OUT2` reader - P4OUT2"]
pub type P4out2R = crate::BitReader;
#[doc = "Field `P4OUT2` writer - P4OUT2"]
pub type P4out2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4OUT3` reader - P4OUT3"]
pub type P4out3R = crate::BitReader;
#[doc = "Field `P4OUT3` writer - P4OUT3"]
pub type P4out3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4OUT4` reader - P4OUT4"]
pub type P4out4R = crate::BitReader;
#[doc = "Field `P4OUT4` writer - P4OUT4"]
pub type P4out4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4OUT5` reader - P4OUT5"]
pub type P4out5R = crate::BitReader;
#[doc = "Field `P4OUT5` writer - P4OUT5"]
pub type P4out5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4OUT6` reader - P4OUT6"]
pub type P4out6R = crate::BitReader;
#[doc = "Field `P4OUT6` writer - P4OUT6"]
pub type P4out6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4OUT7` reader - P4OUT7"]
pub type P4out7R = crate::BitReader;
#[doc = "Field `P4OUT7` writer - P4OUT7"]
pub type P4out7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P4OUT0"]
#[inline(always)]
pub fn p4out0(&self) -> P4out0R {
P4out0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P4OUT1"]
#[inline(always)]
pub fn p4out1(&self) -> P4out1R {
P4out1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P4OUT2"]
#[inline(always)]
pub fn p4out2(&self) -> P4out2R {
P4out2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P4OUT3"]
#[inline(always)]
pub fn p4out3(&self) -> P4out3R {
P4out3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P4OUT4"]
#[inline(always)]
pub fn p4out4(&self) -> P4out4R {
P4out4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P4OUT5"]
#[inline(always)]
pub fn p4out5(&self) -> P4out5R {
P4out5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P4OUT6"]
#[inline(always)]
pub fn p4out6(&self) -> P4out6R {
P4out6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P4OUT7"]
#[inline(always)]
pub fn p4out7(&self) -> P4out7R {
P4out7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P4OUT0"]
#[inline(always)]
pub fn p4out0(&mut self) -> P4out0W<'_, P4outSpec> {
P4out0W::new(self, 0)
}
#[doc = "Bit 1 - P4OUT1"]
#[inline(always)]
pub fn p4out1(&mut self) -> P4out1W<'_, P4outSpec> {
P4out1W::new(self, 1)
}
#[doc = "Bit 2 - P4OUT2"]
#[inline(always)]
pub fn p4out2(&mut self) -> P4out2W<'_, P4outSpec> {
P4out2W::new(self, 2)
}
#[doc = "Bit 3 - P4OUT3"]
#[inline(always)]
pub fn p4out3(&mut self) -> P4out3W<'_, P4outSpec> {
P4out3W::new(self, 3)
}
#[doc = "Bit 4 - P4OUT4"]
#[inline(always)]
pub fn p4out4(&mut self) -> P4out4W<'_, P4outSpec> {
P4out4W::new(self, 4)
}
#[doc = "Bit 5 - P4OUT5"]
#[inline(always)]
pub fn p4out5(&mut self) -> P4out5W<'_, P4outSpec> {
P4out5W::new(self, 5)
}
#[doc = "Bit 6 - P4OUT6"]
#[inline(always)]
pub fn p4out6(&mut self) -> P4out6W<'_, P4outSpec> {
P4out6W::new(self, 6)
}
#[doc = "Bit 7 - P4OUT7"]
#[inline(always)]
pub fn p4out7(&mut self) -> P4out7W<'_, P4outSpec> {
P4out7W::new(self, 7)
}
}
#[doc = "Port 4 Output\n\nYou can [`read`](crate::Reg::read) this register and get [`p4out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P4outSpec;
impl crate::RegisterSpec for P4outSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p4out::R`](R) reader structure"]
impl crate::Readable for P4outSpec {}
#[doc = "`write(|w| ..)` method takes [`p4out::W`](W) writer structure"]
impl crate::Writable for P4outSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P4OUT to value 0"]
impl crate::Resettable for P4outSpec {}
}
#[doc = "P3DIR (rw) register accessor: Port 3 Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`p3dir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3dir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3dir`] module"]
#[doc(alias = "P3DIR")]
pub type P3dir = crate::Reg<p3dir::P3dirSpec>;
#[doc = "Port 3 Direction"]
pub mod p3dir {
#[doc = "Register `P3DIR` reader"]
pub type R = crate::R<P3dirSpec>;
#[doc = "Register `P3DIR` writer"]
pub type W = crate::W<P3dirSpec>;
#[doc = "Field `P3DIR0` reader - P3DIR0"]
pub type P3dir0R = crate::BitReader;
#[doc = "Field `P3DIR0` writer - P3DIR0"]
pub type P3dir0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3DIR1` reader - P3DIR1"]
pub type P3dir1R = crate::BitReader;
#[doc = "Field `P3DIR1` writer - P3DIR1"]
pub type P3dir1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3DIR2` reader - P3DIR2"]
pub type P3dir2R = crate::BitReader;
#[doc = "Field `P3DIR2` writer - P3DIR2"]
pub type P3dir2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3DIR3` reader - P3DIR3"]
pub type P3dir3R = crate::BitReader;
#[doc = "Field `P3DIR3` writer - P3DIR3"]
pub type P3dir3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3DIR4` reader - P3DIR4"]
pub type P3dir4R = crate::BitReader;
#[doc = "Field `P3DIR4` writer - P3DIR4"]
pub type P3dir4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3DIR5` reader - P3DIR5"]
pub type P3dir5R = crate::BitReader;
#[doc = "Field `P3DIR5` writer - P3DIR5"]
pub type P3dir5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3DIR6` reader - P3DIR6"]
pub type P3dir6R = crate::BitReader;
#[doc = "Field `P3DIR6` writer - P3DIR6"]
pub type P3dir6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3DIR7` reader - P3DIR7"]
pub type P3dir7R = crate::BitReader;
#[doc = "Field `P3DIR7` writer - P3DIR7"]
pub type P3dir7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P3DIR0"]
#[inline(always)]
pub fn p3dir0(&self) -> P3dir0R {
P3dir0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P3DIR1"]
#[inline(always)]
pub fn p3dir1(&self) -> P3dir1R {
P3dir1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P3DIR2"]
#[inline(always)]
pub fn p3dir2(&self) -> P3dir2R {
P3dir2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P3DIR3"]
#[inline(always)]
pub fn p3dir3(&self) -> P3dir3R {
P3dir3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P3DIR4"]
#[inline(always)]
pub fn p3dir4(&self) -> P3dir4R {
P3dir4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P3DIR5"]
#[inline(always)]
pub fn p3dir5(&self) -> P3dir5R {
P3dir5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P3DIR6"]
#[inline(always)]
pub fn p3dir6(&self) -> P3dir6R {
P3dir6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P3DIR7"]
#[inline(always)]
pub fn p3dir7(&self) -> P3dir7R {
P3dir7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P3DIR0"]
#[inline(always)]
pub fn p3dir0(&mut self) -> P3dir0W<'_, P3dirSpec> {
P3dir0W::new(self, 0)
}
#[doc = "Bit 1 - P3DIR1"]
#[inline(always)]
pub fn p3dir1(&mut self) -> P3dir1W<'_, P3dirSpec> {
P3dir1W::new(self, 1)
}
#[doc = "Bit 2 - P3DIR2"]
#[inline(always)]
pub fn p3dir2(&mut self) -> P3dir2W<'_, P3dirSpec> {
P3dir2W::new(self, 2)
}
#[doc = "Bit 3 - P3DIR3"]
#[inline(always)]
pub fn p3dir3(&mut self) -> P3dir3W<'_, P3dirSpec> {
P3dir3W::new(self, 3)
}
#[doc = "Bit 4 - P3DIR4"]
#[inline(always)]
pub fn p3dir4(&mut self) -> P3dir4W<'_, P3dirSpec> {
P3dir4W::new(self, 4)
}
#[doc = "Bit 5 - P3DIR5"]
#[inline(always)]
pub fn p3dir5(&mut self) -> P3dir5W<'_, P3dirSpec> {
P3dir5W::new(self, 5)
}
#[doc = "Bit 6 - P3DIR6"]
#[inline(always)]
pub fn p3dir6(&mut self) -> P3dir6W<'_, P3dirSpec> {
P3dir6W::new(self, 6)
}
#[doc = "Bit 7 - P3DIR7"]
#[inline(always)]
pub fn p3dir7(&mut self) -> P3dir7W<'_, P3dirSpec> {
P3dir7W::new(self, 7)
}
}
#[doc = "Port 3 Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`p3dir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3dir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P3dirSpec;
impl crate::RegisterSpec for P3dirSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p3dir::R`](R) reader structure"]
impl crate::Readable for P3dirSpec {}
#[doc = "`write(|w| ..)` method takes [`p3dir::W`](W) writer structure"]
impl crate::Writable for P3dirSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P3DIR to value 0"]
impl crate::Resettable for P3dirSpec {}
}
#[doc = "P4DIR (rw) register accessor: Port 4 Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`p4dir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4dir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p4dir`] module"]
#[doc(alias = "P4DIR")]
pub type P4dir = crate::Reg<p4dir::P4dirSpec>;
#[doc = "Port 4 Direction"]
pub mod p4dir {
#[doc = "Register `P4DIR` reader"]
pub type R = crate::R<P4dirSpec>;
#[doc = "Register `P4DIR` writer"]
pub type W = crate::W<P4dirSpec>;
#[doc = "Field `P4DIR0` reader - P4DIR0"]
pub type P4dir0R = crate::BitReader;
#[doc = "Field `P4DIR0` writer - P4DIR0"]
pub type P4dir0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4DIR1` reader - P4DIR1"]
pub type P4dir1R = crate::BitReader;
#[doc = "Field `P4DIR1` writer - P4DIR1"]
pub type P4dir1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4DIR2` reader - P4DIR2"]
pub type P4dir2R = crate::BitReader;
#[doc = "Field `P4DIR2` writer - P4DIR2"]
pub type P4dir2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4DIR3` reader - P4DIR3"]
pub type P4dir3R = crate::BitReader;
#[doc = "Field `P4DIR3` writer - P4DIR3"]
pub type P4dir3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4DIR4` reader - P4DIR4"]
pub type P4dir4R = crate::BitReader;
#[doc = "Field `P4DIR4` writer - P4DIR4"]
pub type P4dir4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4DIR5` reader - P4DIR5"]
pub type P4dir5R = crate::BitReader;
#[doc = "Field `P4DIR5` writer - P4DIR5"]
pub type P4dir5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4DIR6` reader - P4DIR6"]
pub type P4dir6R = crate::BitReader;
#[doc = "Field `P4DIR6` writer - P4DIR6"]
pub type P4dir6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4DIR7` reader - P4DIR7"]
pub type P4dir7R = crate::BitReader;
#[doc = "Field `P4DIR7` writer - P4DIR7"]
pub type P4dir7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P4DIR0"]
#[inline(always)]
pub fn p4dir0(&self) -> P4dir0R {
P4dir0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P4DIR1"]
#[inline(always)]
pub fn p4dir1(&self) -> P4dir1R {
P4dir1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P4DIR2"]
#[inline(always)]
pub fn p4dir2(&self) -> P4dir2R {
P4dir2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P4DIR3"]
#[inline(always)]
pub fn p4dir3(&self) -> P4dir3R {
P4dir3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P4DIR4"]
#[inline(always)]
pub fn p4dir4(&self) -> P4dir4R {
P4dir4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P4DIR5"]
#[inline(always)]
pub fn p4dir5(&self) -> P4dir5R {
P4dir5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P4DIR6"]
#[inline(always)]
pub fn p4dir6(&self) -> P4dir6R {
P4dir6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P4DIR7"]
#[inline(always)]
pub fn p4dir7(&self) -> P4dir7R {
P4dir7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P4DIR0"]
#[inline(always)]
pub fn p4dir0(&mut self) -> P4dir0W<'_, P4dirSpec> {
P4dir0W::new(self, 0)
}
#[doc = "Bit 1 - P4DIR1"]
#[inline(always)]
pub fn p4dir1(&mut self) -> P4dir1W<'_, P4dirSpec> {
P4dir1W::new(self, 1)
}
#[doc = "Bit 2 - P4DIR2"]
#[inline(always)]
pub fn p4dir2(&mut self) -> P4dir2W<'_, P4dirSpec> {
P4dir2W::new(self, 2)
}
#[doc = "Bit 3 - P4DIR3"]
#[inline(always)]
pub fn p4dir3(&mut self) -> P4dir3W<'_, P4dirSpec> {
P4dir3W::new(self, 3)
}
#[doc = "Bit 4 - P4DIR4"]
#[inline(always)]
pub fn p4dir4(&mut self) -> P4dir4W<'_, P4dirSpec> {
P4dir4W::new(self, 4)
}
#[doc = "Bit 5 - P4DIR5"]
#[inline(always)]
pub fn p4dir5(&mut self) -> P4dir5W<'_, P4dirSpec> {
P4dir5W::new(self, 5)
}
#[doc = "Bit 6 - P4DIR6"]
#[inline(always)]
pub fn p4dir6(&mut self) -> P4dir6W<'_, P4dirSpec> {
P4dir6W::new(self, 6)
}
#[doc = "Bit 7 - P4DIR7"]
#[inline(always)]
pub fn p4dir7(&mut self) -> P4dir7W<'_, P4dirSpec> {
P4dir7W::new(self, 7)
}
}
#[doc = "Port 4 Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`p4dir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4dir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P4dirSpec;
impl crate::RegisterSpec for P4dirSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p4dir::R`](R) reader structure"]
impl crate::Readable for P4dirSpec {}
#[doc = "`write(|w| ..)` method takes [`p4dir::W`](W) writer structure"]
impl crate::Writable for P4dirSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P4DIR to value 0"]
impl crate::Resettable for P4dirSpec {}
}
#[doc = "P3REN (rw) register accessor: Port 3 Resistor Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p3ren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3ren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3ren`] module"]
#[doc(alias = "P3REN")]
pub type P3ren = crate::Reg<p3ren::P3renSpec>;
#[doc = "Port 3 Resistor Enable"]
pub mod p3ren {
#[doc = "Register `P3REN` reader"]
pub type R = crate::R<P3renSpec>;
#[doc = "Register `P3REN` writer"]
pub type W = crate::W<P3renSpec>;
#[doc = "Field `P3REN0` reader - P3REN0"]
pub type P3ren0R = crate::BitReader;
#[doc = "Field `P3REN0` writer - P3REN0"]
pub type P3ren0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3REN1` reader - P3REN1"]
pub type P3ren1R = crate::BitReader;
#[doc = "Field `P3REN1` writer - P3REN1"]
pub type P3ren1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3REN2` reader - P3REN2"]
pub type P3ren2R = crate::BitReader;
#[doc = "Field `P3REN2` writer - P3REN2"]
pub type P3ren2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3REN3` reader - P3REN3"]
pub type P3ren3R = crate::BitReader;
#[doc = "Field `P3REN3` writer - P3REN3"]
pub type P3ren3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3REN4` reader - P3REN4"]
pub type P3ren4R = crate::BitReader;
#[doc = "Field `P3REN4` writer - P3REN4"]
pub type P3ren4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3REN5` reader - P3REN5"]
pub type P3ren5R = crate::BitReader;
#[doc = "Field `P3REN5` writer - P3REN5"]
pub type P3ren5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3REN6` reader - P3REN6"]
pub type P3ren6R = crate::BitReader;
#[doc = "Field `P3REN6` writer - P3REN6"]
pub type P3ren6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3REN7` reader - P3REN7"]
pub type P3ren7R = crate::BitReader;
#[doc = "Field `P3REN7` writer - P3REN7"]
pub type P3ren7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P3REN0"]
#[inline(always)]
pub fn p3ren0(&self) -> P3ren0R {
P3ren0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P3REN1"]
#[inline(always)]
pub fn p3ren1(&self) -> P3ren1R {
P3ren1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P3REN2"]
#[inline(always)]
pub fn p3ren2(&self) -> P3ren2R {
P3ren2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P3REN3"]
#[inline(always)]
pub fn p3ren3(&self) -> P3ren3R {
P3ren3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P3REN4"]
#[inline(always)]
pub fn p3ren4(&self) -> P3ren4R {
P3ren4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P3REN5"]
#[inline(always)]
pub fn p3ren5(&self) -> P3ren5R {
P3ren5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P3REN6"]
#[inline(always)]
pub fn p3ren6(&self) -> P3ren6R {
P3ren6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P3REN7"]
#[inline(always)]
pub fn p3ren7(&self) -> P3ren7R {
P3ren7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P3REN0"]
#[inline(always)]
pub fn p3ren0(&mut self) -> P3ren0W<'_, P3renSpec> {
P3ren0W::new(self, 0)
}
#[doc = "Bit 1 - P3REN1"]
#[inline(always)]
pub fn p3ren1(&mut self) -> P3ren1W<'_, P3renSpec> {
P3ren1W::new(self, 1)
}
#[doc = "Bit 2 - P3REN2"]
#[inline(always)]
pub fn p3ren2(&mut self) -> P3ren2W<'_, P3renSpec> {
P3ren2W::new(self, 2)
}
#[doc = "Bit 3 - P3REN3"]
#[inline(always)]
pub fn p3ren3(&mut self) -> P3ren3W<'_, P3renSpec> {
P3ren3W::new(self, 3)
}
#[doc = "Bit 4 - P3REN4"]
#[inline(always)]
pub fn p3ren4(&mut self) -> P3ren4W<'_, P3renSpec> {
P3ren4W::new(self, 4)
}
#[doc = "Bit 5 - P3REN5"]
#[inline(always)]
pub fn p3ren5(&mut self) -> P3ren5W<'_, P3renSpec> {
P3ren5W::new(self, 5)
}
#[doc = "Bit 6 - P3REN6"]
#[inline(always)]
pub fn p3ren6(&mut self) -> P3ren6W<'_, P3renSpec> {
P3ren6W::new(self, 6)
}
#[doc = "Bit 7 - P3REN7"]
#[inline(always)]
pub fn p3ren7(&mut self) -> P3ren7W<'_, P3renSpec> {
P3ren7W::new(self, 7)
}
}
#[doc = "Port 3 Resistor Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p3ren::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3ren::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P3renSpec;
impl crate::RegisterSpec for P3renSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p3ren::R`](R) reader structure"]
impl crate::Readable for P3renSpec {}
#[doc = "`write(|w| ..)` method takes [`p3ren::W`](W) writer structure"]
impl crate::Writable for P3renSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P3REN to value 0"]
impl crate::Resettable for P3renSpec {}
}
#[doc = "P4REN (rw) register accessor: Port 4 Resistor Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p4ren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4ren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p4ren`] module"]
#[doc(alias = "P4REN")]
pub type P4ren = crate::Reg<p4ren::P4renSpec>;
#[doc = "Port 4 Resistor Enable"]
pub mod p4ren {
#[doc = "Register `P4REN` reader"]
pub type R = crate::R<P4renSpec>;
#[doc = "Register `P4REN` writer"]
pub type W = crate::W<P4renSpec>;
#[doc = "Field `P4REN0` reader - P4REN0"]
pub type P4ren0R = crate::BitReader;
#[doc = "Field `P4REN0` writer - P4REN0"]
pub type P4ren0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4REN1` reader - P4REN1"]
pub type P4ren1R = crate::BitReader;
#[doc = "Field `P4REN1` writer - P4REN1"]
pub type P4ren1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4REN2` reader - P4REN2"]
pub type P4ren2R = crate::BitReader;
#[doc = "Field `P4REN2` writer - P4REN2"]
pub type P4ren2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4REN3` reader - P4REN3"]
pub type P4ren3R = crate::BitReader;
#[doc = "Field `P4REN3` writer - P4REN3"]
pub type P4ren3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4REN4` reader - P4REN4"]
pub type P4ren4R = crate::BitReader;
#[doc = "Field `P4REN4` writer - P4REN4"]
pub type P4ren4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4REN5` reader - P4REN5"]
pub type P4ren5R = crate::BitReader;
#[doc = "Field `P4REN5` writer - P4REN5"]
pub type P4ren5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4REN6` reader - P4REN6"]
pub type P4ren6R = crate::BitReader;
#[doc = "Field `P4REN6` writer - P4REN6"]
pub type P4ren6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4REN7` reader - P4REN7"]
pub type P4ren7R = crate::BitReader;
#[doc = "Field `P4REN7` writer - P4REN7"]
pub type P4ren7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P4REN0"]
#[inline(always)]
pub fn p4ren0(&self) -> P4ren0R {
P4ren0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P4REN1"]
#[inline(always)]
pub fn p4ren1(&self) -> P4ren1R {
P4ren1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P4REN2"]
#[inline(always)]
pub fn p4ren2(&self) -> P4ren2R {
P4ren2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P4REN3"]
#[inline(always)]
pub fn p4ren3(&self) -> P4ren3R {
P4ren3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P4REN4"]
#[inline(always)]
pub fn p4ren4(&self) -> P4ren4R {
P4ren4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P4REN5"]
#[inline(always)]
pub fn p4ren5(&self) -> P4ren5R {
P4ren5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P4REN6"]
#[inline(always)]
pub fn p4ren6(&self) -> P4ren6R {
P4ren6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P4REN7"]
#[inline(always)]
pub fn p4ren7(&self) -> P4ren7R {
P4ren7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P4REN0"]
#[inline(always)]
pub fn p4ren0(&mut self) -> P4ren0W<'_, P4renSpec> {
P4ren0W::new(self, 0)
}
#[doc = "Bit 1 - P4REN1"]
#[inline(always)]
pub fn p4ren1(&mut self) -> P4ren1W<'_, P4renSpec> {
P4ren1W::new(self, 1)
}
#[doc = "Bit 2 - P4REN2"]
#[inline(always)]
pub fn p4ren2(&mut self) -> P4ren2W<'_, P4renSpec> {
P4ren2W::new(self, 2)
}
#[doc = "Bit 3 - P4REN3"]
#[inline(always)]
pub fn p4ren3(&mut self) -> P4ren3W<'_, P4renSpec> {
P4ren3W::new(self, 3)
}
#[doc = "Bit 4 - P4REN4"]
#[inline(always)]
pub fn p4ren4(&mut self) -> P4ren4W<'_, P4renSpec> {
P4ren4W::new(self, 4)
}
#[doc = "Bit 5 - P4REN5"]
#[inline(always)]
pub fn p4ren5(&mut self) -> P4ren5W<'_, P4renSpec> {
P4ren5W::new(self, 5)
}
#[doc = "Bit 6 - P4REN6"]
#[inline(always)]
pub fn p4ren6(&mut self) -> P4ren6W<'_, P4renSpec> {
P4ren6W::new(self, 6)
}
#[doc = "Bit 7 - P4REN7"]
#[inline(always)]
pub fn p4ren7(&mut self) -> P4ren7W<'_, P4renSpec> {
P4ren7W::new(self, 7)
}
}
#[doc = "Port 4 Resistor Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p4ren::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4ren::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P4renSpec;
impl crate::RegisterSpec for P4renSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p4ren::R`](R) reader structure"]
impl crate::Readable for P4renSpec {}
#[doc = "`write(|w| ..)` method takes [`p4ren::W`](W) writer structure"]
impl crate::Writable for P4renSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P4REN to value 0"]
impl crate::Resettable for P4renSpec {}
}
#[doc = "P3SEL0 (rw) register accessor: Port 3 Selection 0\n\nYou can [`read`](crate::Reg::read) this register and get [`p3sel0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3sel0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3sel0`] module"]
#[doc(alias = "P3SEL0")]
pub type P3sel0 = crate::Reg<p3sel0::P3sel0Spec>;
#[doc = "Port 3 Selection 0"]
pub mod p3sel0 {
#[doc = "Register `P3SEL0` reader"]
pub type R = crate::R<P3sel0Spec>;
#[doc = "Register `P3SEL0` writer"]
pub type W = crate::W<P3sel0Spec>;
#[doc = "Field `P3SEL0_0` reader - P3SEL0_0"]
pub type P3sel0_0R = crate::BitReader;
#[doc = "Field `P3SEL0_0` writer - P3SEL0_0"]
pub type P3sel0_0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SEL0_1` reader - P3SEL0_1"]
pub type P3sel0_1R = crate::BitReader;
#[doc = "Field `P3SEL0_1` writer - P3SEL0_1"]
pub type P3sel0_1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SEL0_2` reader - P3SEL0_2"]
pub type P3sel0_2R = crate::BitReader;
#[doc = "Field `P3SEL0_2` writer - P3SEL0_2"]
pub type P3sel0_2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SEL0_3` reader - P3SEL0_3"]
pub type P3sel0_3R = crate::BitReader;
#[doc = "Field `P3SEL0_3` writer - P3SEL0_3"]
pub type P3sel0_3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SEL0_4` reader - P3SEL0_4"]
pub type P3sel0_4R = crate::BitReader;
#[doc = "Field `P3SEL0_4` writer - P3SEL0_4"]
pub type P3sel0_4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SEL0_5` reader - P3SEL0_5"]
pub type P3sel0_5R = crate::BitReader;
#[doc = "Field `P3SEL0_5` writer - P3SEL0_5"]
pub type P3sel0_5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SEL0_6` reader - P3SEL0_6"]
pub type P3sel0_6R = crate::BitReader;
#[doc = "Field `P3SEL0_6` writer - P3SEL0_6"]
pub type P3sel0_6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SEL0_7` reader - P3SEL0_7"]
pub type P3sel0_7R = crate::BitReader;
#[doc = "Field `P3SEL0_7` writer - P3SEL0_7"]
pub type P3sel0_7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P3SEL0_0"]
#[inline(always)]
pub fn p3sel0_0(&self) -> P3sel0_0R {
P3sel0_0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P3SEL0_1"]
#[inline(always)]
pub fn p3sel0_1(&self) -> P3sel0_1R {
P3sel0_1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P3SEL0_2"]
#[inline(always)]
pub fn p3sel0_2(&self) -> P3sel0_2R {
P3sel0_2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P3SEL0_3"]
#[inline(always)]
pub fn p3sel0_3(&self) -> P3sel0_3R {
P3sel0_3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P3SEL0_4"]
#[inline(always)]
pub fn p3sel0_4(&self) -> P3sel0_4R {
P3sel0_4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P3SEL0_5"]
#[inline(always)]
pub fn p3sel0_5(&self) -> P3sel0_5R {
P3sel0_5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P3SEL0_6"]
#[inline(always)]
pub fn p3sel0_6(&self) -> P3sel0_6R {
P3sel0_6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P3SEL0_7"]
#[inline(always)]
pub fn p3sel0_7(&self) -> P3sel0_7R {
P3sel0_7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P3SEL0_0"]
#[inline(always)]
pub fn p3sel0_0(&mut self) -> P3sel0_0W<'_, P3sel0Spec> {
P3sel0_0W::new(self, 0)
}
#[doc = "Bit 1 - P3SEL0_1"]
#[inline(always)]
pub fn p3sel0_1(&mut self) -> P3sel0_1W<'_, P3sel0Spec> {
P3sel0_1W::new(self, 1)
}
#[doc = "Bit 2 - P3SEL0_2"]
#[inline(always)]
pub fn p3sel0_2(&mut self) -> P3sel0_2W<'_, P3sel0Spec> {
P3sel0_2W::new(self, 2)
}
#[doc = "Bit 3 - P3SEL0_3"]
#[inline(always)]
pub fn p3sel0_3(&mut self) -> P3sel0_3W<'_, P3sel0Spec> {
P3sel0_3W::new(self, 3)
}
#[doc = "Bit 4 - P3SEL0_4"]
#[inline(always)]
pub fn p3sel0_4(&mut self) -> P3sel0_4W<'_, P3sel0Spec> {
P3sel0_4W::new(self, 4)
}
#[doc = "Bit 5 - P3SEL0_5"]
#[inline(always)]
pub fn p3sel0_5(&mut self) -> P3sel0_5W<'_, P3sel0Spec> {
P3sel0_5W::new(self, 5)
}
#[doc = "Bit 6 - P3SEL0_6"]
#[inline(always)]
pub fn p3sel0_6(&mut self) -> P3sel0_6W<'_, P3sel0Spec> {
P3sel0_6W::new(self, 6)
}
#[doc = "Bit 7 - P3SEL0_7"]
#[inline(always)]
pub fn p3sel0_7(&mut self) -> P3sel0_7W<'_, P3sel0Spec> {
P3sel0_7W::new(self, 7)
}
}
#[doc = "Port 3 Selection 0\n\nYou can [`read`](crate::Reg::read) this register and get [`p3sel0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3sel0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P3sel0Spec;
impl crate::RegisterSpec for P3sel0Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p3sel0::R`](R) reader structure"]
impl crate::Readable for P3sel0Spec {}
#[doc = "`write(|w| ..)` method takes [`p3sel0::W`](W) writer structure"]
impl crate::Writable for P3sel0Spec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P3SEL0 to value 0"]
impl crate::Resettable for P3sel0Spec {}
}
#[doc = "P4SEL0 (rw) register accessor: Port 4 Selection 0\n\nYou can [`read`](crate::Reg::read) this register and get [`p4sel0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4sel0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p4sel0`] module"]
#[doc(alias = "P4SEL0")]
pub type P4sel0 = crate::Reg<p4sel0::P4sel0Spec>;
#[doc = "Port 4 Selection 0"]
pub mod p4sel0 {
#[doc = "Register `P4SEL0` reader"]
pub type R = crate::R<P4sel0Spec>;
#[doc = "Register `P4SEL0` writer"]
pub type W = crate::W<P4sel0Spec>;
#[doc = "Field `P4SEL0_0` reader - P4SEL0_0"]
pub type P4sel0_0R = crate::BitReader;
#[doc = "Field `P4SEL0_0` writer - P4SEL0_0"]
pub type P4sel0_0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SEL0_1` reader - P4SEL0_1"]
pub type P4sel0_1R = crate::BitReader;
#[doc = "Field `P4SEL0_1` writer - P4SEL0_1"]
pub type P4sel0_1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SEL0_2` reader - P4SEL0_2"]
pub type P4sel0_2R = crate::BitReader;
#[doc = "Field `P4SEL0_2` writer - P4SEL0_2"]
pub type P4sel0_2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SEL0_3` reader - P4SEL0_3"]
pub type P4sel0_3R = crate::BitReader;
#[doc = "Field `P4SEL0_3` writer - P4SEL0_3"]
pub type P4sel0_3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SEL0_4` reader - P4SEL0_4"]
pub type P4sel0_4R = crate::BitReader;
#[doc = "Field `P4SEL0_4` writer - P4SEL0_4"]
pub type P4sel0_4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SEL0_5` reader - P4SEL0_5"]
pub type P4sel0_5R = crate::BitReader;
#[doc = "Field `P4SEL0_5` writer - P4SEL0_5"]
pub type P4sel0_5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SEL0_6` reader - P4SEL0_6"]
pub type P4sel0_6R = crate::BitReader;
#[doc = "Field `P4SEL0_6` writer - P4SEL0_6"]
pub type P4sel0_6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SEL0_7` reader - P4SEL0_7"]
pub type P4sel0_7R = crate::BitReader;
#[doc = "Field `P4SEL0_7` writer - P4SEL0_7"]
pub type P4sel0_7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P4SEL0_0"]
#[inline(always)]
pub fn p4sel0_0(&self) -> P4sel0_0R {
P4sel0_0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P4SEL0_1"]
#[inline(always)]
pub fn p4sel0_1(&self) -> P4sel0_1R {
P4sel0_1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P4SEL0_2"]
#[inline(always)]
pub fn p4sel0_2(&self) -> P4sel0_2R {
P4sel0_2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P4SEL0_3"]
#[inline(always)]
pub fn p4sel0_3(&self) -> P4sel0_3R {
P4sel0_3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P4SEL0_4"]
#[inline(always)]
pub fn p4sel0_4(&self) -> P4sel0_4R {
P4sel0_4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P4SEL0_5"]
#[inline(always)]
pub fn p4sel0_5(&self) -> P4sel0_5R {
P4sel0_5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P4SEL0_6"]
#[inline(always)]
pub fn p4sel0_6(&self) -> P4sel0_6R {
P4sel0_6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P4SEL0_7"]
#[inline(always)]
pub fn p4sel0_7(&self) -> P4sel0_7R {
P4sel0_7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P4SEL0_0"]
#[inline(always)]
pub fn p4sel0_0(&mut self) -> P4sel0_0W<'_, P4sel0Spec> {
P4sel0_0W::new(self, 0)
}
#[doc = "Bit 1 - P4SEL0_1"]
#[inline(always)]
pub fn p4sel0_1(&mut self) -> P4sel0_1W<'_, P4sel0Spec> {
P4sel0_1W::new(self, 1)
}
#[doc = "Bit 2 - P4SEL0_2"]
#[inline(always)]
pub fn p4sel0_2(&mut self) -> P4sel0_2W<'_, P4sel0Spec> {
P4sel0_2W::new(self, 2)
}
#[doc = "Bit 3 - P4SEL0_3"]
#[inline(always)]
pub fn p4sel0_3(&mut self) -> P4sel0_3W<'_, P4sel0Spec> {
P4sel0_3W::new(self, 3)
}
#[doc = "Bit 4 - P4SEL0_4"]
#[inline(always)]
pub fn p4sel0_4(&mut self) -> P4sel0_4W<'_, P4sel0Spec> {
P4sel0_4W::new(self, 4)
}
#[doc = "Bit 5 - P4SEL0_5"]
#[inline(always)]
pub fn p4sel0_5(&mut self) -> P4sel0_5W<'_, P4sel0Spec> {
P4sel0_5W::new(self, 5)
}
#[doc = "Bit 6 - P4SEL0_6"]
#[inline(always)]
pub fn p4sel0_6(&mut self) -> P4sel0_6W<'_, P4sel0Spec> {
P4sel0_6W::new(self, 6)
}
#[doc = "Bit 7 - P4SEL0_7"]
#[inline(always)]
pub fn p4sel0_7(&mut self) -> P4sel0_7W<'_, P4sel0Spec> {
P4sel0_7W::new(self, 7)
}
}
#[doc = "Port 4 Selection 0\n\nYou can [`read`](crate::Reg::read) this register and get [`p4sel0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4sel0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P4sel0Spec;
impl crate::RegisterSpec for P4sel0Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p4sel0::R`](R) reader structure"]
impl crate::Readable for P4sel0Spec {}
#[doc = "`write(|w| ..)` method takes [`p4sel0::W`](W) writer structure"]
impl crate::Writable for P4sel0Spec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P4SEL0 to value 0"]
impl crate::Resettable for P4sel0Spec {}
}
#[doc = "P3SEL1 (rw) register accessor: Port 3 Selection 1\n\nYou can [`read`](crate::Reg::read) this register and get [`p3sel1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3sel1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3sel1`] module"]
#[doc(alias = "P3SEL1")]
pub type P3sel1 = crate::Reg<p3sel1::P3sel1Spec>;
#[doc = "Port 3 Selection 1"]
pub mod p3sel1 {
#[doc = "Register `P3SEL1` reader"]
pub type R = crate::R<P3sel1Spec>;
#[doc = "Register `P3SEL1` writer"]
pub type W = crate::W<P3sel1Spec>;
#[doc = "Field `P3SEL1_0` reader - P3SEL1_0"]
pub type P3sel1_0R = crate::BitReader;
#[doc = "Field `P3SEL1_0` writer - P3SEL1_0"]
pub type P3sel1_0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SEL1_1` reader - P3SEL1_1"]
pub type P3sel1_1R = crate::BitReader;
#[doc = "Field `P3SEL1_1` writer - P3SEL1_1"]
pub type P3sel1_1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SEL1_2` reader - P3SEL1_2"]
pub type P3sel1_2R = crate::BitReader;
#[doc = "Field `P3SEL1_2` writer - P3SEL1_2"]
pub type P3sel1_2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SEL1_3` reader - P3SEL1_3"]
pub type P3sel1_3R = crate::BitReader;
#[doc = "Field `P3SEL1_3` writer - P3SEL1_3"]
pub type P3sel1_3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SEL1_4` reader - P3SEL1_4"]
pub type P3sel1_4R = crate::BitReader;
#[doc = "Field `P3SEL1_4` writer - P3SEL1_4"]
pub type P3sel1_4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SEL1_5` reader - P3SEL1_5"]
pub type P3sel1_5R = crate::BitReader;
#[doc = "Field `P3SEL1_5` writer - P3SEL1_5"]
pub type P3sel1_5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SEL1_6` reader - P3SEL1_6"]
pub type P3sel1_6R = crate::BitReader;
#[doc = "Field `P3SEL1_6` writer - P3SEL1_6"]
pub type P3sel1_6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SEL1_7` reader - P3SEL1_7"]
pub type P3sel1_7R = crate::BitReader;
#[doc = "Field `P3SEL1_7` writer - P3SEL1_7"]
pub type P3sel1_7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P3SEL1_0"]
#[inline(always)]
pub fn p3sel1_0(&self) -> P3sel1_0R {
P3sel1_0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P3SEL1_1"]
#[inline(always)]
pub fn p3sel1_1(&self) -> P3sel1_1R {
P3sel1_1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P3SEL1_2"]
#[inline(always)]
pub fn p3sel1_2(&self) -> P3sel1_2R {
P3sel1_2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P3SEL1_3"]
#[inline(always)]
pub fn p3sel1_3(&self) -> P3sel1_3R {
P3sel1_3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P3SEL1_4"]
#[inline(always)]
pub fn p3sel1_4(&self) -> P3sel1_4R {
P3sel1_4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P3SEL1_5"]
#[inline(always)]
pub fn p3sel1_5(&self) -> P3sel1_5R {
P3sel1_5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P3SEL1_6"]
#[inline(always)]
pub fn p3sel1_6(&self) -> P3sel1_6R {
P3sel1_6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P3SEL1_7"]
#[inline(always)]
pub fn p3sel1_7(&self) -> P3sel1_7R {
P3sel1_7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P3SEL1_0"]
#[inline(always)]
pub fn p3sel1_0(&mut self) -> P3sel1_0W<'_, P3sel1Spec> {
P3sel1_0W::new(self, 0)
}
#[doc = "Bit 1 - P3SEL1_1"]
#[inline(always)]
pub fn p3sel1_1(&mut self) -> P3sel1_1W<'_, P3sel1Spec> {
P3sel1_1W::new(self, 1)
}
#[doc = "Bit 2 - P3SEL1_2"]
#[inline(always)]
pub fn p3sel1_2(&mut self) -> P3sel1_2W<'_, P3sel1Spec> {
P3sel1_2W::new(self, 2)
}
#[doc = "Bit 3 - P3SEL1_3"]
#[inline(always)]
pub fn p3sel1_3(&mut self) -> P3sel1_3W<'_, P3sel1Spec> {
P3sel1_3W::new(self, 3)
}
#[doc = "Bit 4 - P3SEL1_4"]
#[inline(always)]
pub fn p3sel1_4(&mut self) -> P3sel1_4W<'_, P3sel1Spec> {
P3sel1_4W::new(self, 4)
}
#[doc = "Bit 5 - P3SEL1_5"]
#[inline(always)]
pub fn p3sel1_5(&mut self) -> P3sel1_5W<'_, P3sel1Spec> {
P3sel1_5W::new(self, 5)
}
#[doc = "Bit 6 - P3SEL1_6"]
#[inline(always)]
pub fn p3sel1_6(&mut self) -> P3sel1_6W<'_, P3sel1Spec> {
P3sel1_6W::new(self, 6)
}
#[doc = "Bit 7 - P3SEL1_7"]
#[inline(always)]
pub fn p3sel1_7(&mut self) -> P3sel1_7W<'_, P3sel1Spec> {
P3sel1_7W::new(self, 7)
}
}
#[doc = "Port 3 Selection 1\n\nYou can [`read`](crate::Reg::read) this register and get [`p3sel1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3sel1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P3sel1Spec;
impl crate::RegisterSpec for P3sel1Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p3sel1::R`](R) reader structure"]
impl crate::Readable for P3sel1Spec {}
#[doc = "`write(|w| ..)` method takes [`p3sel1::W`](W) writer structure"]
impl crate::Writable for P3sel1Spec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P3SEL1 to value 0"]
impl crate::Resettable for P3sel1Spec {}
}
#[doc = "P4SEL1 (rw) register accessor: Port 4 Selection 1\n\nYou can [`read`](crate::Reg::read) this register and get [`p4sel1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4sel1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p4sel1`] module"]
#[doc(alias = "P4SEL1")]
pub type P4sel1 = crate::Reg<p4sel1::P4sel1Spec>;
#[doc = "Port 4 Selection 1"]
pub mod p4sel1 {
#[doc = "Register `P4SEL1` reader"]
pub type R = crate::R<P4sel1Spec>;
#[doc = "Register `P4SEL1` writer"]
pub type W = crate::W<P4sel1Spec>;
#[doc = "Field `P4SEL1_0` reader - P4SEL1_0"]
pub type P4sel1_0R = crate::BitReader;
#[doc = "Field `P4SEL1_0` writer - P4SEL1_0"]
pub type P4sel1_0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SEL1_1` reader - P4SEL1_1"]
pub type P4sel1_1R = crate::BitReader;
#[doc = "Field `P4SEL1_1` writer - P4SEL1_1"]
pub type P4sel1_1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SEL1_2` reader - P4SEL1_2"]
pub type P4sel1_2R = crate::BitReader;
#[doc = "Field `P4SEL1_2` writer - P4SEL1_2"]
pub type P4sel1_2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SEL1_3` reader - P4SEL1_3"]
pub type P4sel1_3R = crate::BitReader;
#[doc = "Field `P4SEL1_3` writer - P4SEL1_3"]
pub type P4sel1_3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SEL1_4` reader - P4SEL1_4"]
pub type P4sel1_4R = crate::BitReader;
#[doc = "Field `P4SEL1_4` writer - P4SEL1_4"]
pub type P4sel1_4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SEL1_5` reader - P4SEL1_5"]
pub type P4sel1_5R = crate::BitReader;
#[doc = "Field `P4SEL1_5` writer - P4SEL1_5"]
pub type P4sel1_5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SEL1_6` reader - P4SEL1_6"]
pub type P4sel1_6R = crate::BitReader;
#[doc = "Field `P4SEL1_6` writer - P4SEL1_6"]
pub type P4sel1_6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SEL1_7` reader - P4SEL1_7"]
pub type P4sel1_7R = crate::BitReader;
#[doc = "Field `P4SEL1_7` writer - P4SEL1_7"]
pub type P4sel1_7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P4SEL1_0"]
#[inline(always)]
pub fn p4sel1_0(&self) -> P4sel1_0R {
P4sel1_0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P4SEL1_1"]
#[inline(always)]
pub fn p4sel1_1(&self) -> P4sel1_1R {
P4sel1_1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P4SEL1_2"]
#[inline(always)]
pub fn p4sel1_2(&self) -> P4sel1_2R {
P4sel1_2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P4SEL1_3"]
#[inline(always)]
pub fn p4sel1_3(&self) -> P4sel1_3R {
P4sel1_3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P4SEL1_4"]
#[inline(always)]
pub fn p4sel1_4(&self) -> P4sel1_4R {
P4sel1_4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P4SEL1_5"]
#[inline(always)]
pub fn p4sel1_5(&self) -> P4sel1_5R {
P4sel1_5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P4SEL1_6"]
#[inline(always)]
pub fn p4sel1_6(&self) -> P4sel1_6R {
P4sel1_6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P4SEL1_7"]
#[inline(always)]
pub fn p4sel1_7(&self) -> P4sel1_7R {
P4sel1_7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P4SEL1_0"]
#[inline(always)]
pub fn p4sel1_0(&mut self) -> P4sel1_0W<'_, P4sel1Spec> {
P4sel1_0W::new(self, 0)
}
#[doc = "Bit 1 - P4SEL1_1"]
#[inline(always)]
pub fn p4sel1_1(&mut self) -> P4sel1_1W<'_, P4sel1Spec> {
P4sel1_1W::new(self, 1)
}
#[doc = "Bit 2 - P4SEL1_2"]
#[inline(always)]
pub fn p4sel1_2(&mut self) -> P4sel1_2W<'_, P4sel1Spec> {
P4sel1_2W::new(self, 2)
}
#[doc = "Bit 3 - P4SEL1_3"]
#[inline(always)]
pub fn p4sel1_3(&mut self) -> P4sel1_3W<'_, P4sel1Spec> {
P4sel1_3W::new(self, 3)
}
#[doc = "Bit 4 - P4SEL1_4"]
#[inline(always)]
pub fn p4sel1_4(&mut self) -> P4sel1_4W<'_, P4sel1Spec> {
P4sel1_4W::new(self, 4)
}
#[doc = "Bit 5 - P4SEL1_5"]
#[inline(always)]
pub fn p4sel1_5(&mut self) -> P4sel1_5W<'_, P4sel1Spec> {
P4sel1_5W::new(self, 5)
}
#[doc = "Bit 6 - P4SEL1_6"]
#[inline(always)]
pub fn p4sel1_6(&mut self) -> P4sel1_6W<'_, P4sel1Spec> {
P4sel1_6W::new(self, 6)
}
#[doc = "Bit 7 - P4SEL1_7"]
#[inline(always)]
pub fn p4sel1_7(&mut self) -> P4sel1_7W<'_, P4sel1Spec> {
P4sel1_7W::new(self, 7)
}
}
#[doc = "Port 4 Selection 1\n\nYou can [`read`](crate::Reg::read) this register and get [`p4sel1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4sel1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P4sel1Spec;
impl crate::RegisterSpec for P4sel1Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p4sel1::R`](R) reader structure"]
impl crate::Readable for P4sel1Spec {}
#[doc = "`write(|w| ..)` method takes [`p4sel1::W`](W) writer structure"]
impl crate::Writable for P4sel1Spec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P4SEL1 to value 0"]
impl crate::Resettable for P4sel1Spec {}
}
#[doc = "P3SELC (rw) register accessor: Port 3 Complement Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`p3selc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3selc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3selc`] module"]
#[doc(alias = "P3SELC")]
pub type P3selc = crate::Reg<p3selc::P3selcSpec>;
#[doc = "Port 3 Complement Selection"]
pub mod p3selc {
#[doc = "Register `P3SELC` reader"]
pub type R = crate::R<P3selcSpec>;
#[doc = "Register `P3SELC` writer"]
pub type W = crate::W<P3selcSpec>;
#[doc = "Field `P3SELC_0` reader - P3SELC_0"]
pub type P3selc0R = crate::BitReader;
#[doc = "Field `P3SELC_0` writer - P3SELC_0"]
pub type P3selc0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SELC_1` reader - P3SELC_1"]
pub type P3selc1R = crate::BitReader;
#[doc = "Field `P3SELC_1` writer - P3SELC_1"]
pub type P3selc1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SELC_2` reader - P3SELC_2"]
pub type P3selc2R = crate::BitReader;
#[doc = "Field `P3SELC_2` writer - P3SELC_2"]
pub type P3selc2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SELC_3` reader - P3SELC_3"]
pub type P3selc3R = crate::BitReader;
#[doc = "Field `P3SELC_3` writer - P3SELC_3"]
pub type P3selc3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SELC_4` reader - P3SELC_4"]
pub type P3selc4R = crate::BitReader;
#[doc = "Field `P3SELC_4` writer - P3SELC_4"]
pub type P3selc4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SELC_5` reader - P3SELC_5"]
pub type P3selc5R = crate::BitReader;
#[doc = "Field `P3SELC_5` writer - P3SELC_5"]
pub type P3selc5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SELC_6` reader - P3SELC_6"]
pub type P3selc6R = crate::BitReader;
#[doc = "Field `P3SELC_6` writer - P3SELC_6"]
pub type P3selc6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3SELC_7` reader - P3SELC_7"]
pub type P3selc7R = crate::BitReader;
#[doc = "Field `P3SELC_7` writer - P3SELC_7"]
pub type P3selc7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P3SELC_0"]
#[inline(always)]
pub fn p3selc_0(&self) -> P3selc0R {
P3selc0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P3SELC_1"]
#[inline(always)]
pub fn p3selc_1(&self) -> P3selc1R {
P3selc1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P3SELC_2"]
#[inline(always)]
pub fn p3selc_2(&self) -> P3selc2R {
P3selc2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P3SELC_3"]
#[inline(always)]
pub fn p3selc_3(&self) -> P3selc3R {
P3selc3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P3SELC_4"]
#[inline(always)]
pub fn p3selc_4(&self) -> P3selc4R {
P3selc4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P3SELC_5"]
#[inline(always)]
pub fn p3selc_5(&self) -> P3selc5R {
P3selc5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P3SELC_6"]
#[inline(always)]
pub fn p3selc_6(&self) -> P3selc6R {
P3selc6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P3SELC_7"]
#[inline(always)]
pub fn p3selc_7(&self) -> P3selc7R {
P3selc7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P3SELC_0"]
#[inline(always)]
pub fn p3selc_0(&mut self) -> P3selc0W<'_, P3selcSpec> {
P3selc0W::new(self, 0)
}
#[doc = "Bit 1 - P3SELC_1"]
#[inline(always)]
pub fn p3selc_1(&mut self) -> P3selc1W<'_, P3selcSpec> {
P3selc1W::new(self, 1)
}
#[doc = "Bit 2 - P3SELC_2"]
#[inline(always)]
pub fn p3selc_2(&mut self) -> P3selc2W<'_, P3selcSpec> {
P3selc2W::new(self, 2)
}
#[doc = "Bit 3 - P3SELC_3"]
#[inline(always)]
pub fn p3selc_3(&mut self) -> P3selc3W<'_, P3selcSpec> {
P3selc3W::new(self, 3)
}
#[doc = "Bit 4 - P3SELC_4"]
#[inline(always)]
pub fn p3selc_4(&mut self) -> P3selc4W<'_, P3selcSpec> {
P3selc4W::new(self, 4)
}
#[doc = "Bit 5 - P3SELC_5"]
#[inline(always)]
pub fn p3selc_5(&mut self) -> P3selc5W<'_, P3selcSpec> {
P3selc5W::new(self, 5)
}
#[doc = "Bit 6 - P3SELC_6"]
#[inline(always)]
pub fn p3selc_6(&mut self) -> P3selc6W<'_, P3selcSpec> {
P3selc6W::new(self, 6)
}
#[doc = "Bit 7 - P3SELC_7"]
#[inline(always)]
pub fn p3selc_7(&mut self) -> P3selc7W<'_, P3selcSpec> {
P3selc7W::new(self, 7)
}
}
#[doc = "Port 3 Complement Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`p3selc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3selc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P3selcSpec;
impl crate::RegisterSpec for P3selcSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p3selc::R`](R) reader structure"]
impl crate::Readable for P3selcSpec {}
#[doc = "`write(|w| ..)` method takes [`p3selc::W`](W) writer structure"]
impl crate::Writable for P3selcSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P3SELC to value 0"]
impl crate::Resettable for P3selcSpec {}
}
#[doc = "P4SELC (rw) register accessor: Port 4 Complement Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`p4selc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4selc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p4selc`] module"]
#[doc(alias = "P4SELC")]
pub type P4selc = crate::Reg<p4selc::P4selcSpec>;
#[doc = "Port 4 Complement Selection"]
pub mod p4selc {
#[doc = "Register `P4SELC` reader"]
pub type R = crate::R<P4selcSpec>;
#[doc = "Register `P4SELC` writer"]
pub type W = crate::W<P4selcSpec>;
#[doc = "Field `P4SELC_0` reader - P4SELC_0"]
pub type P4selc0R = crate::BitReader;
#[doc = "Field `P4SELC_0` writer - P4SELC_0"]
pub type P4selc0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SELC_1` reader - P4SELC_1"]
pub type P4selc1R = crate::BitReader;
#[doc = "Field `P4SELC_1` writer - P4SELC_1"]
pub type P4selc1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SELC_2` reader - P4SELC_2"]
pub type P4selc2R = crate::BitReader;
#[doc = "Field `P4SELC_2` writer - P4SELC_2"]
pub type P4selc2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SELC_3` reader - P4SELC_3"]
pub type P4selc3R = crate::BitReader;
#[doc = "Field `P4SELC_3` writer - P4SELC_3"]
pub type P4selc3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SELC_4` reader - P4SELC_4"]
pub type P4selc4R = crate::BitReader;
#[doc = "Field `P4SELC_4` writer - P4SELC_4"]
pub type P4selc4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SELC_5` reader - P4SELC_5"]
pub type P4selc5R = crate::BitReader;
#[doc = "Field `P4SELC_5` writer - P4SELC_5"]
pub type P4selc5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SELC_6` reader - P4SELC_6"]
pub type P4selc6R = crate::BitReader;
#[doc = "Field `P4SELC_6` writer - P4SELC_6"]
pub type P4selc6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4SELC_7` reader - P4SELC_7"]
pub type P4selc7R = crate::BitReader;
#[doc = "Field `P4SELC_7` writer - P4SELC_7"]
pub type P4selc7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P4SELC_0"]
#[inline(always)]
pub fn p4selc_0(&self) -> P4selc0R {
P4selc0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P4SELC_1"]
#[inline(always)]
pub fn p4selc_1(&self) -> P4selc1R {
P4selc1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P4SELC_2"]
#[inline(always)]
pub fn p4selc_2(&self) -> P4selc2R {
P4selc2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P4SELC_3"]
#[inline(always)]
pub fn p4selc_3(&self) -> P4selc3R {
P4selc3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P4SELC_4"]
#[inline(always)]
pub fn p4selc_4(&self) -> P4selc4R {
P4selc4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P4SELC_5"]
#[inline(always)]
pub fn p4selc_5(&self) -> P4selc5R {
P4selc5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P4SELC_6"]
#[inline(always)]
pub fn p4selc_6(&self) -> P4selc6R {
P4selc6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P4SELC_7"]
#[inline(always)]
pub fn p4selc_7(&self) -> P4selc7R {
P4selc7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P4SELC_0"]
#[inline(always)]
pub fn p4selc_0(&mut self) -> P4selc0W<'_, P4selcSpec> {
P4selc0W::new(self, 0)
}
#[doc = "Bit 1 - P4SELC_1"]
#[inline(always)]
pub fn p4selc_1(&mut self) -> P4selc1W<'_, P4selcSpec> {
P4selc1W::new(self, 1)
}
#[doc = "Bit 2 - P4SELC_2"]
#[inline(always)]
pub fn p4selc_2(&mut self) -> P4selc2W<'_, P4selcSpec> {
P4selc2W::new(self, 2)
}
#[doc = "Bit 3 - P4SELC_3"]
#[inline(always)]
pub fn p4selc_3(&mut self) -> P4selc3W<'_, P4selcSpec> {
P4selc3W::new(self, 3)
}
#[doc = "Bit 4 - P4SELC_4"]
#[inline(always)]
pub fn p4selc_4(&mut self) -> P4selc4W<'_, P4selcSpec> {
P4selc4W::new(self, 4)
}
#[doc = "Bit 5 - P4SELC_5"]
#[inline(always)]
pub fn p4selc_5(&mut self) -> P4selc5W<'_, P4selcSpec> {
P4selc5W::new(self, 5)
}
#[doc = "Bit 6 - P4SELC_6"]
#[inline(always)]
pub fn p4selc_6(&mut self) -> P4selc6W<'_, P4selcSpec> {
P4selc6W::new(self, 6)
}
#[doc = "Bit 7 - P4SELC_7"]
#[inline(always)]
pub fn p4selc_7(&mut self) -> P4selc7W<'_, P4selcSpec> {
P4selc7W::new(self, 7)
}
}
#[doc = "Port 4 Complement Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`p4selc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4selc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P4selcSpec;
impl crate::RegisterSpec for P4selcSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p4selc::R`](R) reader structure"]
impl crate::Readable for P4selcSpec {}
#[doc = "`write(|w| ..)` method takes [`p4selc::W`](W) writer structure"]
impl crate::Writable for P4selcSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P4SELC to value 0"]
impl crate::Resettable for P4selcSpec {}
}
#[doc = "P3IES (rw) register accessor: Port 3 Interrupt Edge Select\n\nYou can [`read`](crate::Reg::read) this register and get [`p3ies::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3ies::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3ies`] module"]
#[doc(alias = "P3IES")]
pub type P3ies = crate::Reg<p3ies::P3iesSpec>;
#[doc = "Port 3 Interrupt Edge Select"]
pub mod p3ies {
#[doc = "Register `P3IES` reader"]
pub type R = crate::R<P3iesSpec>;
#[doc = "Register `P3IES` writer"]
pub type W = crate::W<P3iesSpec>;
#[doc = "Field `P3IES0` reader - P3IES0"]
pub type P3ies0R = crate::BitReader;
#[doc = "Field `P3IES0` writer - P3IES0"]
pub type P3ies0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IES1` reader - P3IES1"]
pub type P3ies1R = crate::BitReader;
#[doc = "Field `P3IES1` writer - P3IES1"]
pub type P3ies1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IES2` reader - P3IES2"]
pub type P3ies2R = crate::BitReader;
#[doc = "Field `P3IES2` writer - P3IES2"]
pub type P3ies2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IES3` reader - P3IES3"]
pub type P3ies3R = crate::BitReader;
#[doc = "Field `P3IES3` writer - P3IES3"]
pub type P3ies3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IES4` reader - P3IES4"]
pub type P3ies4R = crate::BitReader;
#[doc = "Field `P3IES4` writer - P3IES4"]
pub type P3ies4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IES5` reader - P3IES5"]
pub type P3ies5R = crate::BitReader;
#[doc = "Field `P3IES5` writer - P3IES5"]
pub type P3ies5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IES6` reader - P3IES6"]
pub type P3ies6R = crate::BitReader;
#[doc = "Field `P3IES6` writer - P3IES6"]
pub type P3ies6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IES7` reader - P3IES7"]
pub type P3ies7R = crate::BitReader;
#[doc = "Field `P3IES7` writer - P3IES7"]
pub type P3ies7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P3IES0"]
#[inline(always)]
pub fn p3ies0(&self) -> P3ies0R {
P3ies0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P3IES1"]
#[inline(always)]
pub fn p3ies1(&self) -> P3ies1R {
P3ies1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P3IES2"]
#[inline(always)]
pub fn p3ies2(&self) -> P3ies2R {
P3ies2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P3IES3"]
#[inline(always)]
pub fn p3ies3(&self) -> P3ies3R {
P3ies3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P3IES4"]
#[inline(always)]
pub fn p3ies4(&self) -> P3ies4R {
P3ies4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P3IES5"]
#[inline(always)]
pub fn p3ies5(&self) -> P3ies5R {
P3ies5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P3IES6"]
#[inline(always)]
pub fn p3ies6(&self) -> P3ies6R {
P3ies6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P3IES7"]
#[inline(always)]
pub fn p3ies7(&self) -> P3ies7R {
P3ies7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P3IES0"]
#[inline(always)]
pub fn p3ies0(&mut self) -> P3ies0W<'_, P3iesSpec> {
P3ies0W::new(self, 0)
}
#[doc = "Bit 1 - P3IES1"]
#[inline(always)]
pub fn p3ies1(&mut self) -> P3ies1W<'_, P3iesSpec> {
P3ies1W::new(self, 1)
}
#[doc = "Bit 2 - P3IES2"]
#[inline(always)]
pub fn p3ies2(&mut self) -> P3ies2W<'_, P3iesSpec> {
P3ies2W::new(self, 2)
}
#[doc = "Bit 3 - P3IES3"]
#[inline(always)]
pub fn p3ies3(&mut self) -> P3ies3W<'_, P3iesSpec> {
P3ies3W::new(self, 3)
}
#[doc = "Bit 4 - P3IES4"]
#[inline(always)]
pub fn p3ies4(&mut self) -> P3ies4W<'_, P3iesSpec> {
P3ies4W::new(self, 4)
}
#[doc = "Bit 5 - P3IES5"]
#[inline(always)]
pub fn p3ies5(&mut self) -> P3ies5W<'_, P3iesSpec> {
P3ies5W::new(self, 5)
}
#[doc = "Bit 6 - P3IES6"]
#[inline(always)]
pub fn p3ies6(&mut self) -> P3ies6W<'_, P3iesSpec> {
P3ies6W::new(self, 6)
}
#[doc = "Bit 7 - P3IES7"]
#[inline(always)]
pub fn p3ies7(&mut self) -> P3ies7W<'_, P3iesSpec> {
P3ies7W::new(self, 7)
}
}
#[doc = "Port 3 Interrupt Edge Select\n\nYou can [`read`](crate::Reg::read) this register and get [`p3ies::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3ies::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P3iesSpec;
impl crate::RegisterSpec for P3iesSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p3ies::R`](R) reader structure"]
impl crate::Readable for P3iesSpec {}
#[doc = "`write(|w| ..)` method takes [`p3ies::W`](W) writer structure"]
impl crate::Writable for P3iesSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P3IES to value 0"]
impl crate::Resettable for P3iesSpec {}
}
#[doc = "P4IES (rw) register accessor: Port 4 Interrupt Edge Select\n\nYou can [`read`](crate::Reg::read) this register and get [`p4ies::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4ies::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p4ies`] module"]
#[doc(alias = "P4IES")]
pub type P4ies = crate::Reg<p4ies::P4iesSpec>;
#[doc = "Port 4 Interrupt Edge Select"]
pub mod p4ies {
#[doc = "Register `P4IES` reader"]
pub type R = crate::R<P4iesSpec>;
#[doc = "Register `P4IES` writer"]
pub type W = crate::W<P4iesSpec>;
#[doc = "Field `P4IES0` reader - P4IES0"]
pub type P4ies0R = crate::BitReader;
#[doc = "Field `P4IES0` writer - P4IES0"]
pub type P4ies0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IES1` reader - P4IES1"]
pub type P4ies1R = crate::BitReader;
#[doc = "Field `P4IES1` writer - P4IES1"]
pub type P4ies1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IES2` reader - P4IES2"]
pub type P4ies2R = crate::BitReader;
#[doc = "Field `P4IES2` writer - P4IES2"]
pub type P4ies2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IES3` reader - P4IES3"]
pub type P4ies3R = crate::BitReader;
#[doc = "Field `P4IES3` writer - P4IES3"]
pub type P4ies3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IES4` reader - P4IES4"]
pub type P4ies4R = crate::BitReader;
#[doc = "Field `P4IES4` writer - P4IES4"]
pub type P4ies4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IES5` reader - P4IES5"]
pub type P4ies5R = crate::BitReader;
#[doc = "Field `P4IES5` writer - P4IES5"]
pub type P4ies5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IES6` reader - P4IES6"]
pub type P4ies6R = crate::BitReader;
#[doc = "Field `P4IES6` writer - P4IES6"]
pub type P4ies6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IES7` reader - P4IES7"]
pub type P4ies7R = crate::BitReader;
#[doc = "Field `P4IES7` writer - P4IES7"]
pub type P4ies7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P4IES0"]
#[inline(always)]
pub fn p4ies0(&self) -> P4ies0R {
P4ies0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P4IES1"]
#[inline(always)]
pub fn p4ies1(&self) -> P4ies1R {
P4ies1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P4IES2"]
#[inline(always)]
pub fn p4ies2(&self) -> P4ies2R {
P4ies2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P4IES3"]
#[inline(always)]
pub fn p4ies3(&self) -> P4ies3R {
P4ies3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P4IES4"]
#[inline(always)]
pub fn p4ies4(&self) -> P4ies4R {
P4ies4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P4IES5"]
#[inline(always)]
pub fn p4ies5(&self) -> P4ies5R {
P4ies5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P4IES6"]
#[inline(always)]
pub fn p4ies6(&self) -> P4ies6R {
P4ies6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P4IES7"]
#[inline(always)]
pub fn p4ies7(&self) -> P4ies7R {
P4ies7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P4IES0"]
#[inline(always)]
pub fn p4ies0(&mut self) -> P4ies0W<'_, P4iesSpec> {
P4ies0W::new(self, 0)
}
#[doc = "Bit 1 - P4IES1"]
#[inline(always)]
pub fn p4ies1(&mut self) -> P4ies1W<'_, P4iesSpec> {
P4ies1W::new(self, 1)
}
#[doc = "Bit 2 - P4IES2"]
#[inline(always)]
pub fn p4ies2(&mut self) -> P4ies2W<'_, P4iesSpec> {
P4ies2W::new(self, 2)
}
#[doc = "Bit 3 - P4IES3"]
#[inline(always)]
pub fn p4ies3(&mut self) -> P4ies3W<'_, P4iesSpec> {
P4ies3W::new(self, 3)
}
#[doc = "Bit 4 - P4IES4"]
#[inline(always)]
pub fn p4ies4(&mut self) -> P4ies4W<'_, P4iesSpec> {
P4ies4W::new(self, 4)
}
#[doc = "Bit 5 - P4IES5"]
#[inline(always)]
pub fn p4ies5(&mut self) -> P4ies5W<'_, P4iesSpec> {
P4ies5W::new(self, 5)
}
#[doc = "Bit 6 - P4IES6"]
#[inline(always)]
pub fn p4ies6(&mut self) -> P4ies6W<'_, P4iesSpec> {
P4ies6W::new(self, 6)
}
#[doc = "Bit 7 - P4IES7"]
#[inline(always)]
pub fn p4ies7(&mut self) -> P4ies7W<'_, P4iesSpec> {
P4ies7W::new(self, 7)
}
}
#[doc = "Port 4 Interrupt Edge Select\n\nYou can [`read`](crate::Reg::read) this register and get [`p4ies::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4ies::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P4iesSpec;
impl crate::RegisterSpec for P4iesSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p4ies::R`](R) reader structure"]
impl crate::Readable for P4iesSpec {}
#[doc = "`write(|w| ..)` method takes [`p4ies::W`](W) writer structure"]
impl crate::Writable for P4iesSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P4IES to value 0"]
impl crate::Resettable for P4iesSpec {}
}
#[doc = "P3IE (rw) register accessor: Port 3 Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p3ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3ie`] module"]
#[doc(alias = "P3IE")]
pub type P3ie = crate::Reg<p3ie::P3ieSpec>;
#[doc = "Port 3 Interrupt Enable"]
pub mod p3ie {
#[doc = "Register `P3IE` reader"]
pub type R = crate::R<P3ieSpec>;
#[doc = "Register `P3IE` writer"]
pub type W = crate::W<P3ieSpec>;
#[doc = "Field `P3IE0` reader - P3IE0"]
pub type P3ie0R = crate::BitReader;
#[doc = "Field `P3IE0` writer - P3IE0"]
pub type P3ie0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IE1` reader - P3IE1"]
pub type P3ie1R = crate::BitReader;
#[doc = "Field `P3IE1` writer - P3IE1"]
pub type P3ie1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IE2` reader - P3IE2"]
pub type P3ie2R = crate::BitReader;
#[doc = "Field `P3IE2` writer - P3IE2"]
pub type P3ie2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IE3` reader - P3IE3"]
pub type P3ie3R = crate::BitReader;
#[doc = "Field `P3IE3` writer - P3IE3"]
pub type P3ie3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IE4` reader - P3IE4"]
pub type P3ie4R = crate::BitReader;
#[doc = "Field `P3IE4` writer - P3IE4"]
pub type P3ie4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IE5` reader - P3IE5"]
pub type P3ie5R = crate::BitReader;
#[doc = "Field `P3IE5` writer - P3IE5"]
pub type P3ie5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IE6` reader - P3IE6"]
pub type P3ie6R = crate::BitReader;
#[doc = "Field `P3IE6` writer - P3IE6"]
pub type P3ie6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IE7` reader - P3IE7"]
pub type P3ie7R = crate::BitReader;
#[doc = "Field `P3IE7` writer - P3IE7"]
pub type P3ie7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P3IE0"]
#[inline(always)]
pub fn p3ie0(&self) -> P3ie0R {
P3ie0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P3IE1"]
#[inline(always)]
pub fn p3ie1(&self) -> P3ie1R {
P3ie1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P3IE2"]
#[inline(always)]
pub fn p3ie2(&self) -> P3ie2R {
P3ie2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P3IE3"]
#[inline(always)]
pub fn p3ie3(&self) -> P3ie3R {
P3ie3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P3IE4"]
#[inline(always)]
pub fn p3ie4(&self) -> P3ie4R {
P3ie4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P3IE5"]
#[inline(always)]
pub fn p3ie5(&self) -> P3ie5R {
P3ie5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P3IE6"]
#[inline(always)]
pub fn p3ie6(&self) -> P3ie6R {
P3ie6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P3IE7"]
#[inline(always)]
pub fn p3ie7(&self) -> P3ie7R {
P3ie7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P3IE0"]
#[inline(always)]
pub fn p3ie0(&mut self) -> P3ie0W<'_, P3ieSpec> {
P3ie0W::new(self, 0)
}
#[doc = "Bit 1 - P3IE1"]
#[inline(always)]
pub fn p3ie1(&mut self) -> P3ie1W<'_, P3ieSpec> {
P3ie1W::new(self, 1)
}
#[doc = "Bit 2 - P3IE2"]
#[inline(always)]
pub fn p3ie2(&mut self) -> P3ie2W<'_, P3ieSpec> {
P3ie2W::new(self, 2)
}
#[doc = "Bit 3 - P3IE3"]
#[inline(always)]
pub fn p3ie3(&mut self) -> P3ie3W<'_, P3ieSpec> {
P3ie3W::new(self, 3)
}
#[doc = "Bit 4 - P3IE4"]
#[inline(always)]
pub fn p3ie4(&mut self) -> P3ie4W<'_, P3ieSpec> {
P3ie4W::new(self, 4)
}
#[doc = "Bit 5 - P3IE5"]
#[inline(always)]
pub fn p3ie5(&mut self) -> P3ie5W<'_, P3ieSpec> {
P3ie5W::new(self, 5)
}
#[doc = "Bit 6 - P3IE6"]
#[inline(always)]
pub fn p3ie6(&mut self) -> P3ie6W<'_, P3ieSpec> {
P3ie6W::new(self, 6)
}
#[doc = "Bit 7 - P3IE7"]
#[inline(always)]
pub fn p3ie7(&mut self) -> P3ie7W<'_, P3ieSpec> {
P3ie7W::new(self, 7)
}
}
#[doc = "Port 3 Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p3ie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3ie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P3ieSpec;
impl crate::RegisterSpec for P3ieSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p3ie::R`](R) reader structure"]
impl crate::Readable for P3ieSpec {}
#[doc = "`write(|w| ..)` method takes [`p3ie::W`](W) writer structure"]
impl crate::Writable for P3ieSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P3IE to value 0"]
impl crate::Resettable for P3ieSpec {}
}
#[doc = "P4IE (rw) register accessor: Port 4 Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p4ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p4ie`] module"]
#[doc(alias = "P4IE")]
pub type P4ie = crate::Reg<p4ie::P4ieSpec>;
#[doc = "Port 4 Interrupt Enable"]
pub mod p4ie {
#[doc = "Register `P4IE` reader"]
pub type R = crate::R<P4ieSpec>;
#[doc = "Register `P4IE` writer"]
pub type W = crate::W<P4ieSpec>;
#[doc = "Field `P4IE0` reader - P4IE0"]
pub type P4ie0R = crate::BitReader;
#[doc = "Field `P4IE0` writer - P4IE0"]
pub type P4ie0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IE1` reader - P4IE1"]
pub type P4ie1R = crate::BitReader;
#[doc = "Field `P4IE1` writer - P4IE1"]
pub type P4ie1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IE2` reader - P4IE2"]
pub type P4ie2R = crate::BitReader;
#[doc = "Field `P4IE2` writer - P4IE2"]
pub type P4ie2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IE3` reader - P4IE3"]
pub type P4ie3R = crate::BitReader;
#[doc = "Field `P4IE3` writer - P4IE3"]
pub type P4ie3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IE4` reader - P4IE4"]
pub type P4ie4R = crate::BitReader;
#[doc = "Field `P4IE4` writer - P4IE4"]
pub type P4ie4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IE5` reader - P4IE5"]
pub type P4ie5R = crate::BitReader;
#[doc = "Field `P4IE5` writer - P4IE5"]
pub type P4ie5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IE6` reader - P4IE6"]
pub type P4ie6R = crate::BitReader;
#[doc = "Field `P4IE6` writer - P4IE6"]
pub type P4ie6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IE7` reader - P4IE7"]
pub type P4ie7R = crate::BitReader;
#[doc = "Field `P4IE7` writer - P4IE7"]
pub type P4ie7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P4IE0"]
#[inline(always)]
pub fn p4ie0(&self) -> P4ie0R {
P4ie0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P4IE1"]
#[inline(always)]
pub fn p4ie1(&self) -> P4ie1R {
P4ie1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P4IE2"]
#[inline(always)]
pub fn p4ie2(&self) -> P4ie2R {
P4ie2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P4IE3"]
#[inline(always)]
pub fn p4ie3(&self) -> P4ie3R {
P4ie3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P4IE4"]
#[inline(always)]
pub fn p4ie4(&self) -> P4ie4R {
P4ie4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P4IE5"]
#[inline(always)]
pub fn p4ie5(&self) -> P4ie5R {
P4ie5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P4IE6"]
#[inline(always)]
pub fn p4ie6(&self) -> P4ie6R {
P4ie6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P4IE7"]
#[inline(always)]
pub fn p4ie7(&self) -> P4ie7R {
P4ie7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P4IE0"]
#[inline(always)]
pub fn p4ie0(&mut self) -> P4ie0W<'_, P4ieSpec> {
P4ie0W::new(self, 0)
}
#[doc = "Bit 1 - P4IE1"]
#[inline(always)]
pub fn p4ie1(&mut self) -> P4ie1W<'_, P4ieSpec> {
P4ie1W::new(self, 1)
}
#[doc = "Bit 2 - P4IE2"]
#[inline(always)]
pub fn p4ie2(&mut self) -> P4ie2W<'_, P4ieSpec> {
P4ie2W::new(self, 2)
}
#[doc = "Bit 3 - P4IE3"]
#[inline(always)]
pub fn p4ie3(&mut self) -> P4ie3W<'_, P4ieSpec> {
P4ie3W::new(self, 3)
}
#[doc = "Bit 4 - P4IE4"]
#[inline(always)]
pub fn p4ie4(&mut self) -> P4ie4W<'_, P4ieSpec> {
P4ie4W::new(self, 4)
}
#[doc = "Bit 5 - P4IE5"]
#[inline(always)]
pub fn p4ie5(&mut self) -> P4ie5W<'_, P4ieSpec> {
P4ie5W::new(self, 5)
}
#[doc = "Bit 6 - P4IE6"]
#[inline(always)]
pub fn p4ie6(&mut self) -> P4ie6W<'_, P4ieSpec> {
P4ie6W::new(self, 6)
}
#[doc = "Bit 7 - P4IE7"]
#[inline(always)]
pub fn p4ie7(&mut self) -> P4ie7W<'_, P4ieSpec> {
P4ie7W::new(self, 7)
}
}
#[doc = "Port 4 Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p4ie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4ie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P4ieSpec;
impl crate::RegisterSpec for P4ieSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p4ie::R`](R) reader structure"]
impl crate::Readable for P4ieSpec {}
#[doc = "`write(|w| ..)` method takes [`p4ie::W`](W) writer structure"]
impl crate::Writable for P4ieSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P4IE to value 0"]
impl crate::Resettable for P4ieSpec {}
}
#[doc = "P3IFG (rw) register accessor: Port 3 Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`p3ifg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3ifg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3ifg`] module"]
#[doc(alias = "P3IFG")]
pub type P3ifg = crate::Reg<p3ifg::P3ifgSpec>;
#[doc = "Port 3 Interrupt Flag"]
pub mod p3ifg {
#[doc = "Register `P3IFG` reader"]
pub type R = crate::R<P3ifgSpec>;
#[doc = "Register `P3IFG` writer"]
pub type W = crate::W<P3ifgSpec>;
#[doc = "Field `P3IFG0` reader - P3IFG0"]
pub type P3ifg0R = crate::BitReader;
#[doc = "Field `P3IFG0` writer - P3IFG0"]
pub type P3ifg0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IFG1` reader - P3IFG1"]
pub type P3ifg1R = crate::BitReader;
#[doc = "Field `P3IFG1` writer - P3IFG1"]
pub type P3ifg1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IFG2` reader - P3IFG2"]
pub type P3ifg2R = crate::BitReader;
#[doc = "Field `P3IFG2` writer - P3IFG2"]
pub type P3ifg2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IFG3` reader - P3IFG3"]
pub type P3ifg3R = crate::BitReader;
#[doc = "Field `P3IFG3` writer - P3IFG3"]
pub type P3ifg3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IFG4` reader - P3IFG4"]
pub type P3ifg4R = crate::BitReader;
#[doc = "Field `P3IFG4` writer - P3IFG4"]
pub type P3ifg4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IFG5` reader - P3IFG5"]
pub type P3ifg5R = crate::BitReader;
#[doc = "Field `P3IFG5` writer - P3IFG5"]
pub type P3ifg5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IFG6` reader - P3IFG6"]
pub type P3ifg6R = crate::BitReader;
#[doc = "Field `P3IFG6` writer - P3IFG6"]
pub type P3ifg6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P3IFG7` reader - P3IFG7"]
pub type P3ifg7R = crate::BitReader;
#[doc = "Field `P3IFG7` writer - P3IFG7"]
pub type P3ifg7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P3IFG0"]
#[inline(always)]
pub fn p3ifg0(&self) -> P3ifg0R {
P3ifg0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P3IFG1"]
#[inline(always)]
pub fn p3ifg1(&self) -> P3ifg1R {
P3ifg1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P3IFG2"]
#[inline(always)]
pub fn p3ifg2(&self) -> P3ifg2R {
P3ifg2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P3IFG3"]
#[inline(always)]
pub fn p3ifg3(&self) -> P3ifg3R {
P3ifg3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P3IFG4"]
#[inline(always)]
pub fn p3ifg4(&self) -> P3ifg4R {
P3ifg4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P3IFG5"]
#[inline(always)]
pub fn p3ifg5(&self) -> P3ifg5R {
P3ifg5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P3IFG6"]
#[inline(always)]
pub fn p3ifg6(&self) -> P3ifg6R {
P3ifg6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P3IFG7"]
#[inline(always)]
pub fn p3ifg7(&self) -> P3ifg7R {
P3ifg7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P3IFG0"]
#[inline(always)]
pub fn p3ifg0(&mut self) -> P3ifg0W<'_, P3ifgSpec> {
P3ifg0W::new(self, 0)
}
#[doc = "Bit 1 - P3IFG1"]
#[inline(always)]
pub fn p3ifg1(&mut self) -> P3ifg1W<'_, P3ifgSpec> {
P3ifg1W::new(self, 1)
}
#[doc = "Bit 2 - P3IFG2"]
#[inline(always)]
pub fn p3ifg2(&mut self) -> P3ifg2W<'_, P3ifgSpec> {
P3ifg2W::new(self, 2)
}
#[doc = "Bit 3 - P3IFG3"]
#[inline(always)]
pub fn p3ifg3(&mut self) -> P3ifg3W<'_, P3ifgSpec> {
P3ifg3W::new(self, 3)
}
#[doc = "Bit 4 - P3IFG4"]
#[inline(always)]
pub fn p3ifg4(&mut self) -> P3ifg4W<'_, P3ifgSpec> {
P3ifg4W::new(self, 4)
}
#[doc = "Bit 5 - P3IFG5"]
#[inline(always)]
pub fn p3ifg5(&mut self) -> P3ifg5W<'_, P3ifgSpec> {
P3ifg5W::new(self, 5)
}
#[doc = "Bit 6 - P3IFG6"]
#[inline(always)]
pub fn p3ifg6(&mut self) -> P3ifg6W<'_, P3ifgSpec> {
P3ifg6W::new(self, 6)
}
#[doc = "Bit 7 - P3IFG7"]
#[inline(always)]
pub fn p3ifg7(&mut self) -> P3ifg7W<'_, P3ifgSpec> {
P3ifg7W::new(self, 7)
}
}
#[doc = "Port 3 Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`p3ifg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3ifg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P3ifgSpec;
impl crate::RegisterSpec for P3ifgSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p3ifg::R`](R) reader structure"]
impl crate::Readable for P3ifgSpec {}
#[doc = "`write(|w| ..)` method takes [`p3ifg::W`](W) writer structure"]
impl crate::Writable for P3ifgSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P3IFG to value 0"]
impl crate::Resettable for P3ifgSpec {}
}
#[doc = "P4IFG (rw) register accessor: Port 4 Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`p4ifg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4ifg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p4ifg`] module"]
#[doc(alias = "P4IFG")]
pub type P4ifg = crate::Reg<p4ifg::P4ifgSpec>;
#[doc = "Port 4 Interrupt Flag"]
pub mod p4ifg {
#[doc = "Register `P4IFG` reader"]
pub type R = crate::R<P4ifgSpec>;
#[doc = "Register `P4IFG` writer"]
pub type W = crate::W<P4ifgSpec>;
#[doc = "Field `P4IFG0` reader - P4IFG0"]
pub type P4ifg0R = crate::BitReader;
#[doc = "Field `P4IFG0` writer - P4IFG0"]
pub type P4ifg0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IFG1` reader - P4IFG1"]
pub type P4ifg1R = crate::BitReader;
#[doc = "Field `P4IFG1` writer - P4IFG1"]
pub type P4ifg1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IFG2` reader - P4IFG2"]
pub type P4ifg2R = crate::BitReader;
#[doc = "Field `P4IFG2` writer - P4IFG2"]
pub type P4ifg2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IFG3` reader - P4IFG3"]
pub type P4ifg3R = crate::BitReader;
#[doc = "Field `P4IFG3` writer - P4IFG3"]
pub type P4ifg3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IFG4` reader - P4IFG4"]
pub type P4ifg4R = crate::BitReader;
#[doc = "Field `P4IFG4` writer - P4IFG4"]
pub type P4ifg4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IFG5` reader - P4IFG5"]
pub type P4ifg5R = crate::BitReader;
#[doc = "Field `P4IFG5` writer - P4IFG5"]
pub type P4ifg5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IFG6` reader - P4IFG6"]
pub type P4ifg6R = crate::BitReader;
#[doc = "Field `P4IFG6` writer - P4IFG6"]
pub type P4ifg6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `P4IFG7` reader - P4IFG7"]
pub type P4ifg7R = crate::BitReader;
#[doc = "Field `P4IFG7` writer - P4IFG7"]
pub type P4ifg7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - P4IFG0"]
#[inline(always)]
pub fn p4ifg0(&self) -> P4ifg0R {
P4ifg0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - P4IFG1"]
#[inline(always)]
pub fn p4ifg1(&self) -> P4ifg1R {
P4ifg1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - P4IFG2"]
#[inline(always)]
pub fn p4ifg2(&self) -> P4ifg2R {
P4ifg2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - P4IFG3"]
#[inline(always)]
pub fn p4ifg3(&self) -> P4ifg3R {
P4ifg3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - P4IFG4"]
#[inline(always)]
pub fn p4ifg4(&self) -> P4ifg4R {
P4ifg4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - P4IFG5"]
#[inline(always)]
pub fn p4ifg5(&self) -> P4ifg5R {
P4ifg5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - P4IFG6"]
#[inline(always)]
pub fn p4ifg6(&self) -> P4ifg6R {
P4ifg6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - P4IFG7"]
#[inline(always)]
pub fn p4ifg7(&self) -> P4ifg7R {
P4ifg7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - P4IFG0"]
#[inline(always)]
pub fn p4ifg0(&mut self) -> P4ifg0W<'_, P4ifgSpec> {
P4ifg0W::new(self, 0)
}
#[doc = "Bit 1 - P4IFG1"]
#[inline(always)]
pub fn p4ifg1(&mut self) -> P4ifg1W<'_, P4ifgSpec> {
P4ifg1W::new(self, 1)
}
#[doc = "Bit 2 - P4IFG2"]
#[inline(always)]
pub fn p4ifg2(&mut self) -> P4ifg2W<'_, P4ifgSpec> {
P4ifg2W::new(self, 2)
}
#[doc = "Bit 3 - P4IFG3"]
#[inline(always)]
pub fn p4ifg3(&mut self) -> P4ifg3W<'_, P4ifgSpec> {
P4ifg3W::new(self, 3)
}
#[doc = "Bit 4 - P4IFG4"]
#[inline(always)]
pub fn p4ifg4(&mut self) -> P4ifg4W<'_, P4ifgSpec> {
P4ifg4W::new(self, 4)
}
#[doc = "Bit 5 - P4IFG5"]
#[inline(always)]
pub fn p4ifg5(&mut self) -> P4ifg5W<'_, P4ifgSpec> {
P4ifg5W::new(self, 5)
}
#[doc = "Bit 6 - P4IFG6"]
#[inline(always)]
pub fn p4ifg6(&mut self) -> P4ifg6W<'_, P4ifgSpec> {
P4ifg6W::new(self, 6)
}
#[doc = "Bit 7 - P4IFG7"]
#[inline(always)]
pub fn p4ifg7(&mut self) -> P4ifg7W<'_, P4ifgSpec> {
P4ifg7W::new(self, 7)
}
}
#[doc = "Port 4 Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`p4ifg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4ifg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P4ifgSpec;
impl crate::RegisterSpec for P4ifgSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`p4ifg::R`](R) reader structure"]
impl crate::Readable for P4ifgSpec {}
#[doc = "`write(|w| ..)` method takes [`p4ifg::W`](W) writer structure"]
impl crate::Writable for P4ifgSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets P4IFG to value 0"]
impl crate::Resettable for P4ifgSpec {}
}
#[doc = "P3IV (rw) register accessor: Port 3 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`p3iv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3iv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3iv`] module"]
#[doc(alias = "P3IV")]
pub type P3iv = crate::Reg<p3iv::P3ivSpec>;
#[doc = "Port 3 Interrupt Vector Word"]
pub mod p3iv {
#[doc = "Register `P3IV` reader"]
pub type R = crate::R<P3ivSpec>;
#[doc = "Register `P3IV` writer"]
pub type W = crate::W<P3ivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Port 3 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`p3iv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3iv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P3ivSpec;
impl crate::RegisterSpec for P3ivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`p3iv::R`](R) reader structure"]
impl crate::Readable for P3ivSpec {}
#[doc = "`write(|w| ..)` method takes [`p3iv::W`](W) writer structure"]
impl crate::Writable for P3ivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets P3IV to value 0"]
impl crate::Resettable for P3ivSpec {}
}
#[doc = "P4IV (rw) register accessor: Port 4 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`p4iv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4iv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p4iv`] module"]
#[doc(alias = "P4IV")]
pub type P4iv = crate::Reg<p4iv::P4ivSpec>;
#[doc = "Port 4 Interrupt Vector Word"]
pub mod p4iv {
#[doc = "Register `P4IV` reader"]
pub type R = crate::R<P4ivSpec>;
#[doc = "Register `P4IV` writer"]
pub type W = crate::W<P4ivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Port 4 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`p4iv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p4iv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct P4ivSpec;
impl crate::RegisterSpec for P4ivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`p4iv::R`](R) reader structure"]
impl crate::Readable for P4ivSpec {}
#[doc = "`write(|w| ..)` method takes [`p4iv::W`](W) writer structure"]
impl crate::Writable for P4ivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets P4IV to value 0"]
impl crate::Resettable for P4ivSpec {}
}
}
#[doc = "RTC_B Real Time Clock"]
pub type RtcBRealTimeClock = crate::Periph<rtc_b_real_time_clock::RegisterBlock, 0x04a0>;
impl core::fmt::Debug for RtcBRealTimeClock {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RtcBRealTimeClock").finish()
}
}
#[doc = "RTC_B Real Time Clock"]
pub mod rtc_b_real_time_clock {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
rtcctl01: Rtcctl01,
rtcctl23: Rtcctl23,
_reserved2: [u8; 0x04],
rtcps0ctl: Rtcps0ctl,
rtcps1ctl: Rtcps1ctl,
rtcps: Rtcps,
rtciv: Rtciv,
rtcsec: Rtcsec,
rtcmin: Rtcmin,
rtchour: Rtchour,
rtcdow: Rtcdow,
rtcday: Rtcday,
rtcmon: Rtcmon,
rtcyear: Rtcyear,
rtcamin: Rtcamin,
rtcahour: Rtcahour,
rtcadow: Rtcadow,
rtcaday: Rtcaday,
bin2bcd: Bin2bcd,
bcd2bin: Bcd2bin,
}
impl RegisterBlock {
#[doc = "0x00 - Real Timer Control 0/1"]
#[inline(always)]
pub const fn rtcctl01(&self) -> &Rtcctl01 {
&self.rtcctl01
}
#[doc = "0x02 - Real Timer Control 2/3"]
#[inline(always)]
pub const fn rtcctl23(&self) -> &Rtcctl23 {
&self.rtcctl23
}
#[doc = "0x08 - Real Timer Prescale Timer 0 Control"]
#[inline(always)]
pub const fn rtcps0ctl(&self) -> &Rtcps0ctl {
&self.rtcps0ctl
}
#[doc = "0x0a - Real Timer Prescale Timer 1 Control"]
#[inline(always)]
pub const fn rtcps1ctl(&self) -> &Rtcps1ctl {
&self.rtcps1ctl
}
#[doc = "0x0c - Real Timer Prescale Timer Control"]
#[inline(always)]
pub const fn rtcps(&self) -> &Rtcps {
&self.rtcps
}
#[doc = "0x0e - Real Time Clock Interrupt Vector"]
#[inline(always)]
pub const fn rtciv(&self) -> &Rtciv {
&self.rtciv
}
#[doc = "0x10 - Real Time Clock Seconds"]
#[inline(always)]
pub const fn rtcsec(&self) -> &Rtcsec {
&self.rtcsec
}
#[doc = "0x11 - Real Time Clock Minutes"]
#[inline(always)]
pub const fn rtcmin(&self) -> &Rtcmin {
&self.rtcmin
}
#[doc = "0x12 - Real Time Clock Hour"]
#[inline(always)]
pub const fn rtchour(&self) -> &Rtchour {
&self.rtchour
}
#[doc = "0x13 - Real Time Clock Day of week"]
#[inline(always)]
pub const fn rtcdow(&self) -> &Rtcdow {
&self.rtcdow
}
#[doc = "0x14 - Real Time Clock Day"]
#[inline(always)]
pub const fn rtcday(&self) -> &Rtcday {
&self.rtcday
}
#[doc = "0x15 - Real Time Clock Month"]
#[inline(always)]
pub const fn rtcmon(&self) -> &Rtcmon {
&self.rtcmon
}
#[doc = "0x16 - Real Time Clock Year"]
#[inline(always)]
pub const fn rtcyear(&self) -> &Rtcyear {
&self.rtcyear
}
#[doc = "0x18 - Real Time Clock Alarm Min"]
#[inline(always)]
pub const fn rtcamin(&self) -> &Rtcamin {
&self.rtcamin
}
#[doc = "0x19 - Real Time Clock Alarm Hour"]
#[inline(always)]
pub const fn rtcahour(&self) -> &Rtcahour {
&self.rtcahour
}
#[doc = "0x1a - Real Time Clock Alarm Day of week"]
#[inline(always)]
pub const fn rtcadow(&self) -> &Rtcadow {
&self.rtcadow
}
#[doc = "0x1b - Real Time Clock Alarm Day"]
#[inline(always)]
pub const fn rtcaday(&self) -> &Rtcaday {
&self.rtcaday
}
#[doc = "0x1c - Real Time Binary-to-BCD conversion register"]
#[inline(always)]
pub const fn bin2bcd(&self) -> &Bin2bcd {
&self.bin2bcd
}
#[doc = "0x1e - Real Time BCD-to-binary conversion register"]
#[inline(always)]
pub const fn bcd2bin(&self) -> &Bcd2bin {
&self.bcd2bin
}
}
#[doc = "RTCSEC (rw) register accessor: Real Time Clock Seconds\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcsec::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcsec::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtcsec`] module"]
#[doc(alias = "RTCSEC")]
pub type Rtcsec = crate::Reg<rtcsec::RtcsecSpec>;
#[doc = "Real Time Clock Seconds"]
pub mod rtcsec {
#[doc = "Register `RTCSEC` reader"]
pub type R = crate::R<RtcsecSpec>;
#[doc = "Register `RTCSEC` writer"]
pub type W = crate::W<RtcsecSpec>;
#[doc = "Field `SECONDS0` reader - Real Time Clock Seconds Bit: 0"]
pub type Seconds0R = crate::BitReader;
#[doc = "Field `SECONDS0` writer - Real Time Clock Seconds Bit: 0"]
pub type Seconds0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SECONDS1` reader - Real Time Clock Seconds Bit: 1"]
pub type Seconds1R = crate::BitReader;
#[doc = "Field `SECONDS1` writer - Real Time Clock Seconds Bit: 1"]
pub type Seconds1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SECONDS2` reader - Real Time Clock Seconds Bit: 2"]
pub type Seconds2R = crate::BitReader;
#[doc = "Field `SECONDS2` writer - Real Time Clock Seconds Bit: 2"]
pub type Seconds2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SECONDS3` reader - Real Time Clock Seconds Bit: 3"]
pub type Seconds3R = crate::BitReader;
#[doc = "Field `SECONDS3` writer - Real Time Clock Seconds Bit: 3"]
pub type Seconds3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SECONDS4` reader - Real Time Clock Seconds Bit: 4"]
pub type Seconds4R = crate::BitReader;
#[doc = "Field `SECONDS4` writer - Real Time Clock Seconds Bit: 4"]
pub type Seconds4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SECONDS5` reader - Real Time Clock Seconds Bit: 5"]
pub type Seconds5R = crate::BitReader;
#[doc = "Field `SECONDS5` writer - Real Time Clock Seconds Bit: 5"]
pub type Seconds5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SECONDS6` reader - Real Time Clock Seconds Bit: 6"]
pub type Seconds6R = crate::BitReader;
#[doc = "Field `SECONDS6` writer - Real Time Clock Seconds Bit: 6"]
pub type Seconds6W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Real Time Clock Seconds Bit: 0"]
#[inline(always)]
pub fn seconds0(&self) -> Seconds0R {
Seconds0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Real Time Clock Seconds Bit: 1"]
#[inline(always)]
pub fn seconds1(&self) -> Seconds1R {
Seconds1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Real Time Clock Seconds Bit: 2"]
#[inline(always)]
pub fn seconds2(&self) -> Seconds2R {
Seconds2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Real Time Clock Seconds Bit: 3"]
#[inline(always)]
pub fn seconds3(&self) -> Seconds3R {
Seconds3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Real Time Clock Seconds Bit: 4"]
#[inline(always)]
pub fn seconds4(&self) -> Seconds4R {
Seconds4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Real Time Clock Seconds Bit: 5"]
#[inline(always)]
pub fn seconds5(&self) -> Seconds5R {
Seconds5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Real Time Clock Seconds Bit: 6"]
#[inline(always)]
pub fn seconds6(&self) -> Seconds6R {
Seconds6R::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Real Time Clock Seconds Bit: 0"]
#[inline(always)]
pub fn seconds0(&mut self) -> Seconds0W<'_, RtcsecSpec> {
Seconds0W::new(self, 0)
}
#[doc = "Bit 1 - Real Time Clock Seconds Bit: 1"]
#[inline(always)]
pub fn seconds1(&mut self) -> Seconds1W<'_, RtcsecSpec> {
Seconds1W::new(self, 1)
}
#[doc = "Bit 2 - Real Time Clock Seconds Bit: 2"]
#[inline(always)]
pub fn seconds2(&mut self) -> Seconds2W<'_, RtcsecSpec> {
Seconds2W::new(self, 2)
}
#[doc = "Bit 3 - Real Time Clock Seconds Bit: 3"]
#[inline(always)]
pub fn seconds3(&mut self) -> Seconds3W<'_, RtcsecSpec> {
Seconds3W::new(self, 3)
}
#[doc = "Bit 4 - Real Time Clock Seconds Bit: 4"]
#[inline(always)]
pub fn seconds4(&mut self) -> Seconds4W<'_, RtcsecSpec> {
Seconds4W::new(self, 4)
}
#[doc = "Bit 5 - Real Time Clock Seconds Bit: 5"]
#[inline(always)]
pub fn seconds5(&mut self) -> Seconds5W<'_, RtcsecSpec> {
Seconds5W::new(self, 5)
}
#[doc = "Bit 6 - Real Time Clock Seconds Bit: 6"]
#[inline(always)]
pub fn seconds6(&mut self) -> Seconds6W<'_, RtcsecSpec> {
Seconds6W::new(self, 6)
}
}
#[doc = "Real Time Clock Seconds\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcsec::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcsec::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcsecSpec;
impl crate::RegisterSpec for RtcsecSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`rtcsec::R`](R) reader structure"]
impl crate::Readable for RtcsecSpec {}
#[doc = "`write(|w| ..)` method takes [`rtcsec::W`](W) writer structure"]
impl crate::Writable for RtcsecSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTCSEC to value 0"]
impl crate::Resettable for RtcsecSpec {}
}
#[doc = "RTCMIN (rw) register accessor: Real Time Clock Minutes\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcmin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcmin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtcmin`] module"]
#[doc(alias = "RTCMIN")]
pub type Rtcmin = crate::Reg<rtcmin::RtcminSpec>;
#[doc = "Real Time Clock Minutes"]
pub mod rtcmin {
#[doc = "Register `RTCMIN` reader"]
pub type R = crate::R<RtcminSpec>;
#[doc = "Register `RTCMIN` writer"]
pub type W = crate::W<RtcminSpec>;
#[doc = "Field `MINUTES0` reader - Real Time Clock Minutes Bit: 0"]
pub type Minutes0R = crate::BitReader;
#[doc = "Field `MINUTES0` writer - Real Time Clock Minutes Bit: 0"]
pub type Minutes0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINUTES1` reader - Real Time Clock Minutes Bit: 1"]
pub type Minutes1R = crate::BitReader;
#[doc = "Field `MINUTES1` writer - Real Time Clock Minutes Bit: 1"]
pub type Minutes1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINUTES2` reader - Real Time Clock Minutes Bit: 2"]
pub type Minutes2R = crate::BitReader;
#[doc = "Field `MINUTES2` writer - Real Time Clock Minutes Bit: 2"]
pub type Minutes2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINUTES3` reader - Real Time Clock Minutes Bit: 3"]
pub type Minutes3R = crate::BitReader;
#[doc = "Field `MINUTES3` writer - Real Time Clock Minutes Bit: 3"]
pub type Minutes3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINUTES4` reader - Real Time Clock Minutes Bit: 4"]
pub type Minutes4R = crate::BitReader;
#[doc = "Field `MINUTES4` writer - Real Time Clock Minutes Bit: 4"]
pub type Minutes4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINUTES5` reader - Real Time Clock Minutes Bit: 5"]
pub type Minutes5R = crate::BitReader;
#[doc = "Field `MINUTES5` writer - Real Time Clock Minutes Bit: 5"]
pub type Minutes5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINUTES6` reader - Real Time Clock Minutes Bit: 6"]
pub type Minutes6R = crate::BitReader;
#[doc = "Field `MINUTES6` writer - Real Time Clock Minutes Bit: 6"]
pub type Minutes6W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Real Time Clock Minutes Bit: 0"]
#[inline(always)]
pub fn minutes0(&self) -> Minutes0R {
Minutes0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Real Time Clock Minutes Bit: 1"]
#[inline(always)]
pub fn minutes1(&self) -> Minutes1R {
Minutes1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Real Time Clock Minutes Bit: 2"]
#[inline(always)]
pub fn minutes2(&self) -> Minutes2R {
Minutes2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Real Time Clock Minutes Bit: 3"]
#[inline(always)]
pub fn minutes3(&self) -> Minutes3R {
Minutes3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Real Time Clock Minutes Bit: 4"]
#[inline(always)]
pub fn minutes4(&self) -> Minutes4R {
Minutes4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Real Time Clock Minutes Bit: 5"]
#[inline(always)]
pub fn minutes5(&self) -> Minutes5R {
Minutes5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Real Time Clock Minutes Bit: 6"]
#[inline(always)]
pub fn minutes6(&self) -> Minutes6R {
Minutes6R::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Real Time Clock Minutes Bit: 0"]
#[inline(always)]
pub fn minutes0(&mut self) -> Minutes0W<'_, RtcminSpec> {
Minutes0W::new(self, 0)
}
#[doc = "Bit 1 - Real Time Clock Minutes Bit: 1"]
#[inline(always)]
pub fn minutes1(&mut self) -> Minutes1W<'_, RtcminSpec> {
Minutes1W::new(self, 1)
}
#[doc = "Bit 2 - Real Time Clock Minutes Bit: 2"]
#[inline(always)]
pub fn minutes2(&mut self) -> Minutes2W<'_, RtcminSpec> {
Minutes2W::new(self, 2)
}
#[doc = "Bit 3 - Real Time Clock Minutes Bit: 3"]
#[inline(always)]
pub fn minutes3(&mut self) -> Minutes3W<'_, RtcminSpec> {
Minutes3W::new(self, 3)
}
#[doc = "Bit 4 - Real Time Clock Minutes Bit: 4"]
#[inline(always)]
pub fn minutes4(&mut self) -> Minutes4W<'_, RtcminSpec> {
Minutes4W::new(self, 4)
}
#[doc = "Bit 5 - Real Time Clock Minutes Bit: 5"]
#[inline(always)]
pub fn minutes5(&mut self) -> Minutes5W<'_, RtcminSpec> {
Minutes5W::new(self, 5)
}
#[doc = "Bit 6 - Real Time Clock Minutes Bit: 6"]
#[inline(always)]
pub fn minutes6(&mut self) -> Minutes6W<'_, RtcminSpec> {
Minutes6W::new(self, 6)
}
}
#[doc = "Real Time Clock Minutes\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcmin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcmin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcminSpec;
impl crate::RegisterSpec for RtcminSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`rtcmin::R`](R) reader structure"]
impl crate::Readable for RtcminSpec {}
#[doc = "`write(|w| ..)` method takes [`rtcmin::W`](W) writer structure"]
impl crate::Writable for RtcminSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTCMIN to value 0"]
impl crate::Resettable for RtcminSpec {}
}
#[doc = "RTCHOUR (rw) register accessor: Real Time Clock Hour\n\nYou can [`read`](crate::Reg::read) this register and get [`rtchour::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtchour::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtchour`] module"]
#[doc(alias = "RTCHOUR")]
pub type Rtchour = crate::Reg<rtchour::RtchourSpec>;
#[doc = "Real Time Clock Hour"]
pub mod rtchour {
#[doc = "Register `RTCHOUR` reader"]
pub type R = crate::R<RtchourSpec>;
#[doc = "Register `RTCHOUR` writer"]
pub type W = crate::W<RtchourSpec>;
#[doc = "Field `HOUR0` reader - Real Time Clock Hour Bit: 0"]
pub type Hour0R = crate::BitReader;
#[doc = "Field `HOUR0` writer - Real Time Clock Hour Bit: 0"]
pub type Hour0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HOUR1` reader - Real Time Clock Hour Bit: 1"]
pub type Hour1R = crate::BitReader;
#[doc = "Field `HOUR1` writer - Real Time Clock Hour Bit: 1"]
pub type Hour1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HOUR2` reader - Real Time Clock Hour Bit: 2"]
pub type Hour2R = crate::BitReader;
#[doc = "Field `HOUR2` writer - Real Time Clock Hour Bit: 2"]
pub type Hour2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HOUR3` reader - Real Time Clock Hour Bit: 3"]
pub type Hour3R = crate::BitReader;
#[doc = "Field `HOUR3` writer - Real Time Clock Hour Bit: 3"]
pub type Hour3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HOUR4` reader - Real Time Clock Hour Bit: 4"]
pub type Hour4R = crate::BitReader;
#[doc = "Field `HOUR4` writer - Real Time Clock Hour Bit: 4"]
pub type Hour4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HOUR5` reader - Real Time Clock Hour Bit: 5"]
pub type Hour5R = crate::BitReader;
#[doc = "Field `HOUR5` writer - Real Time Clock Hour Bit: 5"]
pub type Hour5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HOUR6` reader - Real Time Clock Hour Bit: 6"]
pub type Hour6R = crate::BitReader;
#[doc = "Field `HOUR6` writer - Real Time Clock Hour Bit: 6"]
pub type Hour6W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Real Time Clock Hour Bit: 0"]
#[inline(always)]
pub fn hour0(&self) -> Hour0R {
Hour0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Real Time Clock Hour Bit: 1"]
#[inline(always)]
pub fn hour1(&self) -> Hour1R {
Hour1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Real Time Clock Hour Bit: 2"]
#[inline(always)]
pub fn hour2(&self) -> Hour2R {
Hour2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Real Time Clock Hour Bit: 3"]
#[inline(always)]
pub fn hour3(&self) -> Hour3R {
Hour3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Real Time Clock Hour Bit: 4"]
#[inline(always)]
pub fn hour4(&self) -> Hour4R {
Hour4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Real Time Clock Hour Bit: 5"]
#[inline(always)]
pub fn hour5(&self) -> Hour5R {
Hour5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Real Time Clock Hour Bit: 6"]
#[inline(always)]
pub fn hour6(&self) -> Hour6R {
Hour6R::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Real Time Clock Hour Bit: 0"]
#[inline(always)]
pub fn hour0(&mut self) -> Hour0W<'_, RtchourSpec> {
Hour0W::new(self, 0)
}
#[doc = "Bit 1 - Real Time Clock Hour Bit: 1"]
#[inline(always)]
pub fn hour1(&mut self) -> Hour1W<'_, RtchourSpec> {
Hour1W::new(self, 1)
}
#[doc = "Bit 2 - Real Time Clock Hour Bit: 2"]
#[inline(always)]
pub fn hour2(&mut self) -> Hour2W<'_, RtchourSpec> {
Hour2W::new(self, 2)
}
#[doc = "Bit 3 - Real Time Clock Hour Bit: 3"]
#[inline(always)]
pub fn hour3(&mut self) -> Hour3W<'_, RtchourSpec> {
Hour3W::new(self, 3)
}
#[doc = "Bit 4 - Real Time Clock Hour Bit: 4"]
#[inline(always)]
pub fn hour4(&mut self) -> Hour4W<'_, RtchourSpec> {
Hour4W::new(self, 4)
}
#[doc = "Bit 5 - Real Time Clock Hour Bit: 5"]
#[inline(always)]
pub fn hour5(&mut self) -> Hour5W<'_, RtchourSpec> {
Hour5W::new(self, 5)
}
#[doc = "Bit 6 - Real Time Clock Hour Bit: 6"]
#[inline(always)]
pub fn hour6(&mut self) -> Hour6W<'_, RtchourSpec> {
Hour6W::new(self, 6)
}
}
#[doc = "Real Time Clock Hour\n\nYou can [`read`](crate::Reg::read) this register and get [`rtchour::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtchour::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtchourSpec;
impl crate::RegisterSpec for RtchourSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`rtchour::R`](R) reader structure"]
impl crate::Readable for RtchourSpec {}
#[doc = "`write(|w| ..)` method takes [`rtchour::W`](W) writer structure"]
impl crate::Writable for RtchourSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTCHOUR to value 0"]
impl crate::Resettable for RtchourSpec {}
}
#[doc = "RTCDOW (rw) register accessor: Real Time Clock Day of week\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcdow::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcdow::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtcdow`] module"]
#[doc(alias = "RTCDOW")]
pub type Rtcdow = crate::Reg<rtcdow::RtcdowSpec>;
#[doc = "Real Time Clock Day of week"]
pub mod rtcdow {
#[doc = "Register `RTCDOW` reader"]
pub type R = crate::R<RtcdowSpec>;
#[doc = "Register `RTCDOW` writer"]
pub type W = crate::W<RtcdowSpec>;
#[doc = "Field `DOW0` reader - Real Time Clock DOW Bit: 0"]
pub type Dow0R = crate::BitReader;
#[doc = "Field `DOW0` writer - Real Time Clock DOW Bit: 0"]
pub type Dow0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DOW1` reader - Real Time Clock DOW Bit: 1"]
pub type Dow1R = crate::BitReader;
#[doc = "Field `DOW1` writer - Real Time Clock DOW Bit: 1"]
pub type Dow1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DOW2` reader - Real Time Clock DOW Bit: 2"]
pub type Dow2R = crate::BitReader;
#[doc = "Field `DOW2` writer - Real Time Clock DOW Bit: 2"]
pub type Dow2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DOW3` reader - Real Time Clock DOW Bit: 3"]
pub type Dow3R = crate::BitReader;
#[doc = "Field `DOW3` writer - Real Time Clock DOW Bit: 3"]
pub type Dow3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DOW4` reader - Real Time Clock DOW Bit: 4"]
pub type Dow4R = crate::BitReader;
#[doc = "Field `DOW4` writer - Real Time Clock DOW Bit: 4"]
pub type Dow4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DOW5` reader - Real Time Clock DOW Bit: 5"]
pub type Dow5R = crate::BitReader;
#[doc = "Field `DOW5` writer - Real Time Clock DOW Bit: 5"]
pub type Dow5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DOW6` reader - Real Time Clock DOW Bit: 6"]
pub type Dow6R = crate::BitReader;
#[doc = "Field `DOW6` writer - Real Time Clock DOW Bit: 6"]
pub type Dow6W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Real Time Clock DOW Bit: 0"]
#[inline(always)]
pub fn dow0(&self) -> Dow0R {
Dow0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Real Time Clock DOW Bit: 1"]
#[inline(always)]
pub fn dow1(&self) -> Dow1R {
Dow1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Real Time Clock DOW Bit: 2"]
#[inline(always)]
pub fn dow2(&self) -> Dow2R {
Dow2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Real Time Clock DOW Bit: 3"]
#[inline(always)]
pub fn dow3(&self) -> Dow3R {
Dow3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Real Time Clock DOW Bit: 4"]
#[inline(always)]
pub fn dow4(&self) -> Dow4R {
Dow4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Real Time Clock DOW Bit: 5"]
#[inline(always)]
pub fn dow5(&self) -> Dow5R {
Dow5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Real Time Clock DOW Bit: 6"]
#[inline(always)]
pub fn dow6(&self) -> Dow6R {
Dow6R::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Real Time Clock DOW Bit: 0"]
#[inline(always)]
pub fn dow0(&mut self) -> Dow0W<'_, RtcdowSpec> {
Dow0W::new(self, 0)
}
#[doc = "Bit 1 - Real Time Clock DOW Bit: 1"]
#[inline(always)]
pub fn dow1(&mut self) -> Dow1W<'_, RtcdowSpec> {
Dow1W::new(self, 1)
}
#[doc = "Bit 2 - Real Time Clock DOW Bit: 2"]
#[inline(always)]
pub fn dow2(&mut self) -> Dow2W<'_, RtcdowSpec> {
Dow2W::new(self, 2)
}
#[doc = "Bit 3 - Real Time Clock DOW Bit: 3"]
#[inline(always)]
pub fn dow3(&mut self) -> Dow3W<'_, RtcdowSpec> {
Dow3W::new(self, 3)
}
#[doc = "Bit 4 - Real Time Clock DOW Bit: 4"]
#[inline(always)]
pub fn dow4(&mut self) -> Dow4W<'_, RtcdowSpec> {
Dow4W::new(self, 4)
}
#[doc = "Bit 5 - Real Time Clock DOW Bit: 5"]
#[inline(always)]
pub fn dow5(&mut self) -> Dow5W<'_, RtcdowSpec> {
Dow5W::new(self, 5)
}
#[doc = "Bit 6 - Real Time Clock DOW Bit: 6"]
#[inline(always)]
pub fn dow6(&mut self) -> Dow6W<'_, RtcdowSpec> {
Dow6W::new(self, 6)
}
}
#[doc = "Real Time Clock Day of week\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcdow::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcdow::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcdowSpec;
impl crate::RegisterSpec for RtcdowSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`rtcdow::R`](R) reader structure"]
impl crate::Readable for RtcdowSpec {}
#[doc = "`write(|w| ..)` method takes [`rtcdow::W`](W) writer structure"]
impl crate::Writable for RtcdowSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTCDOW to value 0"]
impl crate::Resettable for RtcdowSpec {}
}
#[doc = "RTCDAY (rw) register accessor: Real Time Clock Day\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcday::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcday::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtcday`] module"]
#[doc(alias = "RTCDAY")]
pub type Rtcday = crate::Reg<rtcday::RtcdaySpec>;
#[doc = "Real Time Clock Day"]
pub mod rtcday {
#[doc = "Register `RTCDAY` reader"]
pub type R = crate::R<RtcdaySpec>;
#[doc = "Register `RTCDAY` writer"]
pub type W = crate::W<RtcdaySpec>;
#[doc = "Field `DAY0` reader - Real Time Clock Day Bit: 0"]
pub type Day0R = crate::BitReader;
#[doc = "Field `DAY0` writer - Real Time Clock Day Bit: 0"]
pub type Day0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DAY1` reader - Real Time Clock Day Bit: 1"]
pub type Day1R = crate::BitReader;
#[doc = "Field `DAY1` writer - Real Time Clock Day Bit: 1"]
pub type Day1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DAY2` reader - Real Time Clock Day Bit: 2"]
pub type Day2R = crate::BitReader;
#[doc = "Field `DAY2` writer - Real Time Clock Day Bit: 2"]
pub type Day2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DAY3` reader - Real Time Clock Day Bit: 3"]
pub type Day3R = crate::BitReader;
#[doc = "Field `DAY3` writer - Real Time Clock Day Bit: 3"]
pub type Day3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DAY4` reader - Real Time Clock Day Bit: 4"]
pub type Day4R = crate::BitReader;
#[doc = "Field `DAY4` writer - Real Time Clock Day Bit: 4"]
pub type Day4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DAY5` reader - Real Time Clock Day Bit: 5"]
pub type Day5R = crate::BitReader;
#[doc = "Field `DAY5` writer - Real Time Clock Day Bit: 5"]
pub type Day5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DAY6` reader - Real Time Clock Day Bit: 6"]
pub type Day6R = crate::BitReader;
#[doc = "Field `DAY6` writer - Real Time Clock Day Bit: 6"]
pub type Day6W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Real Time Clock Day Bit: 0"]
#[inline(always)]
pub fn day0(&self) -> Day0R {
Day0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Real Time Clock Day Bit: 1"]
#[inline(always)]
pub fn day1(&self) -> Day1R {
Day1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Real Time Clock Day Bit: 2"]
#[inline(always)]
pub fn day2(&self) -> Day2R {
Day2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Real Time Clock Day Bit: 3"]
#[inline(always)]
pub fn day3(&self) -> Day3R {
Day3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Real Time Clock Day Bit: 4"]
#[inline(always)]
pub fn day4(&self) -> Day4R {
Day4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Real Time Clock Day Bit: 5"]
#[inline(always)]
pub fn day5(&self) -> Day5R {
Day5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Real Time Clock Day Bit: 6"]
#[inline(always)]
pub fn day6(&self) -> Day6R {
Day6R::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Real Time Clock Day Bit: 0"]
#[inline(always)]
pub fn day0(&mut self) -> Day0W<'_, RtcdaySpec> {
Day0W::new(self, 0)
}
#[doc = "Bit 1 - Real Time Clock Day Bit: 1"]
#[inline(always)]
pub fn day1(&mut self) -> Day1W<'_, RtcdaySpec> {
Day1W::new(self, 1)
}
#[doc = "Bit 2 - Real Time Clock Day Bit: 2"]
#[inline(always)]
pub fn day2(&mut self) -> Day2W<'_, RtcdaySpec> {
Day2W::new(self, 2)
}
#[doc = "Bit 3 - Real Time Clock Day Bit: 3"]
#[inline(always)]
pub fn day3(&mut self) -> Day3W<'_, RtcdaySpec> {
Day3W::new(self, 3)
}
#[doc = "Bit 4 - Real Time Clock Day Bit: 4"]
#[inline(always)]
pub fn day4(&mut self) -> Day4W<'_, RtcdaySpec> {
Day4W::new(self, 4)
}
#[doc = "Bit 5 - Real Time Clock Day Bit: 5"]
#[inline(always)]
pub fn day5(&mut self) -> Day5W<'_, RtcdaySpec> {
Day5W::new(self, 5)
}
#[doc = "Bit 6 - Real Time Clock Day Bit: 6"]
#[inline(always)]
pub fn day6(&mut self) -> Day6W<'_, RtcdaySpec> {
Day6W::new(self, 6)
}
}
#[doc = "Real Time Clock Day\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcday::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcday::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcdaySpec;
impl crate::RegisterSpec for RtcdaySpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`rtcday::R`](R) reader structure"]
impl crate::Readable for RtcdaySpec {}
#[doc = "`write(|w| ..)` method takes [`rtcday::W`](W) writer structure"]
impl crate::Writable for RtcdaySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTCDAY to value 0"]
impl crate::Resettable for RtcdaySpec {}
}
#[doc = "RTCMON (rw) register accessor: Real Time Clock Month\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcmon::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcmon::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtcmon`] module"]
#[doc(alias = "RTCMON")]
pub type Rtcmon = crate::Reg<rtcmon::RtcmonSpec>;
#[doc = "Real Time Clock Month"]
pub mod rtcmon {
#[doc = "Register `RTCMON` reader"]
pub type R = crate::R<RtcmonSpec>;
#[doc = "Register `RTCMON` writer"]
pub type W = crate::W<RtcmonSpec>;
#[doc = "Field `MONTH0` reader - Real Time Clock Month Bit: 0"]
pub type Month0R = crate::BitReader;
#[doc = "Field `MONTH0` writer - Real Time Clock Month Bit: 0"]
pub type Month0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MONTH1` reader - Real Time Clock Month Bit: 1"]
pub type Month1R = crate::BitReader;
#[doc = "Field `MONTH1` writer - Real Time Clock Month Bit: 1"]
pub type Month1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MONTH2` reader - Real Time Clock Month Bit: 2"]
pub type Month2R = crate::BitReader;
#[doc = "Field `MONTH2` writer - Real Time Clock Month Bit: 2"]
pub type Month2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MONTH3` reader - Real Time Clock Month Bit: 3"]
pub type Month3R = crate::BitReader;
#[doc = "Field `MONTH3` writer - Real Time Clock Month Bit: 3"]
pub type Month3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MONTH4` reader - Real Time Clock Month Bit: 4"]
pub type Month4R = crate::BitReader;
#[doc = "Field `MONTH4` writer - Real Time Clock Month Bit: 4"]
pub type Month4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MONTH5` reader - Real Time Clock Month Bit: 5"]
pub type Month5R = crate::BitReader;
#[doc = "Field `MONTH5` writer - Real Time Clock Month Bit: 5"]
pub type Month5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MONTH6` reader - Real Time Clock Month Bit: 6"]
pub type Month6R = crate::BitReader;
#[doc = "Field `MONTH6` writer - Real Time Clock Month Bit: 6"]
pub type Month6W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Real Time Clock Month Bit: 0"]
#[inline(always)]
pub fn month0(&self) -> Month0R {
Month0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Real Time Clock Month Bit: 1"]
#[inline(always)]
pub fn month1(&self) -> Month1R {
Month1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Real Time Clock Month Bit: 2"]
#[inline(always)]
pub fn month2(&self) -> Month2R {
Month2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Real Time Clock Month Bit: 3"]
#[inline(always)]
pub fn month3(&self) -> Month3R {
Month3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Real Time Clock Month Bit: 4"]
#[inline(always)]
pub fn month4(&self) -> Month4R {
Month4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Real Time Clock Month Bit: 5"]
#[inline(always)]
pub fn month5(&self) -> Month5R {
Month5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Real Time Clock Month Bit: 6"]
#[inline(always)]
pub fn month6(&self) -> Month6R {
Month6R::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Real Time Clock Month Bit: 0"]
#[inline(always)]
pub fn month0(&mut self) -> Month0W<'_, RtcmonSpec> {
Month0W::new(self, 0)
}
#[doc = "Bit 1 - Real Time Clock Month Bit: 1"]
#[inline(always)]
pub fn month1(&mut self) -> Month1W<'_, RtcmonSpec> {
Month1W::new(self, 1)
}
#[doc = "Bit 2 - Real Time Clock Month Bit: 2"]
#[inline(always)]
pub fn month2(&mut self) -> Month2W<'_, RtcmonSpec> {
Month2W::new(self, 2)
}
#[doc = "Bit 3 - Real Time Clock Month Bit: 3"]
#[inline(always)]
pub fn month3(&mut self) -> Month3W<'_, RtcmonSpec> {
Month3W::new(self, 3)
}
#[doc = "Bit 4 - Real Time Clock Month Bit: 4"]
#[inline(always)]
pub fn month4(&mut self) -> Month4W<'_, RtcmonSpec> {
Month4W::new(self, 4)
}
#[doc = "Bit 5 - Real Time Clock Month Bit: 5"]
#[inline(always)]
pub fn month5(&mut self) -> Month5W<'_, RtcmonSpec> {
Month5W::new(self, 5)
}
#[doc = "Bit 6 - Real Time Clock Month Bit: 6"]
#[inline(always)]
pub fn month6(&mut self) -> Month6W<'_, RtcmonSpec> {
Month6W::new(self, 6)
}
}
#[doc = "Real Time Clock Month\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcmon::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcmon::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcmonSpec;
impl crate::RegisterSpec for RtcmonSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`rtcmon::R`](R) reader structure"]
impl crate::Readable for RtcmonSpec {}
#[doc = "`write(|w| ..)` method takes [`rtcmon::W`](W) writer structure"]
impl crate::Writable for RtcmonSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTCMON to value 0"]
impl crate::Resettable for RtcmonSpec {}
}
#[doc = "RTCAMIN (rw) register accessor: Real Time Clock Alarm Min\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcamin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcamin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtcamin`] module"]
#[doc(alias = "RTCAMIN")]
pub type Rtcamin = crate::Reg<rtcamin::RtcaminSpec>;
#[doc = "Real Time Clock Alarm Min"]
pub mod rtcamin {
#[doc = "Register `RTCAMIN` reader"]
pub type R = crate::R<RtcaminSpec>;
#[doc = "Register `RTCAMIN` writer"]
pub type W = crate::W<RtcaminSpec>;
#[doc = "Field `MINUTES0` reader - Real Time Clock Minutes Bit: 0"]
pub type Minutes0R = crate::BitReader;
#[doc = "Field `MINUTES0` writer - Real Time Clock Minutes Bit: 0"]
pub type Minutes0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINUTES1` reader - Real Time Clock Minutes Bit: 1"]
pub type Minutes1R = crate::BitReader;
#[doc = "Field `MINUTES1` writer - Real Time Clock Minutes Bit: 1"]
pub type Minutes1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINUTES2` reader - Real Time Clock Minutes Bit: 2"]
pub type Minutes2R = crate::BitReader;
#[doc = "Field `MINUTES2` writer - Real Time Clock Minutes Bit: 2"]
pub type Minutes2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINUTES3` reader - Real Time Clock Minutes Bit: 3"]
pub type Minutes3R = crate::BitReader;
#[doc = "Field `MINUTES3` writer - Real Time Clock Minutes Bit: 3"]
pub type Minutes3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINUTES4` reader - Real Time Clock Minutes Bit: 4"]
pub type Minutes4R = crate::BitReader;
#[doc = "Field `MINUTES4` writer - Real Time Clock Minutes Bit: 4"]
pub type Minutes4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINUTES5` reader - Real Time Clock Minutes Bit: 5"]
pub type Minutes5R = crate::BitReader;
#[doc = "Field `MINUTES5` writer - Real Time Clock Minutes Bit: 5"]
pub type Minutes5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MINUTES6` reader - Real Time Clock Minutes Bit: 6"]
pub type Minutes6R = crate::BitReader;
#[doc = "Field `MINUTES6` writer - Real Time Clock Minutes Bit: 6"]
pub type Minutes6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCAE` reader - Real Time Clock Alarm enable"]
pub type RtcaeR = crate::BitReader;
#[doc = "Field `RTCAE` writer - Real Time Clock Alarm enable"]
pub type RtcaeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Real Time Clock Minutes Bit: 0"]
#[inline(always)]
pub fn minutes0(&self) -> Minutes0R {
Minutes0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Real Time Clock Minutes Bit: 1"]
#[inline(always)]
pub fn minutes1(&self) -> Minutes1R {
Minutes1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Real Time Clock Minutes Bit: 2"]
#[inline(always)]
pub fn minutes2(&self) -> Minutes2R {
Minutes2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Real Time Clock Minutes Bit: 3"]
#[inline(always)]
pub fn minutes3(&self) -> Minutes3R {
Minutes3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Real Time Clock Minutes Bit: 4"]
#[inline(always)]
pub fn minutes4(&self) -> Minutes4R {
Minutes4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Real Time Clock Minutes Bit: 5"]
#[inline(always)]
pub fn minutes5(&self) -> Minutes5R {
Minutes5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Real Time Clock Minutes Bit: 6"]
#[inline(always)]
pub fn minutes6(&self) -> Minutes6R {
Minutes6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Real Time Clock Alarm enable"]
#[inline(always)]
pub fn rtcae(&self) -> RtcaeR {
RtcaeR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Real Time Clock Minutes Bit: 0"]
#[inline(always)]
pub fn minutes0(&mut self) -> Minutes0W<'_, RtcaminSpec> {
Minutes0W::new(self, 0)
}
#[doc = "Bit 1 - Real Time Clock Minutes Bit: 1"]
#[inline(always)]
pub fn minutes1(&mut self) -> Minutes1W<'_, RtcaminSpec> {
Minutes1W::new(self, 1)
}
#[doc = "Bit 2 - Real Time Clock Minutes Bit: 2"]
#[inline(always)]
pub fn minutes2(&mut self) -> Minutes2W<'_, RtcaminSpec> {
Minutes2W::new(self, 2)
}
#[doc = "Bit 3 - Real Time Clock Minutes Bit: 3"]
#[inline(always)]
pub fn minutes3(&mut self) -> Minutes3W<'_, RtcaminSpec> {
Minutes3W::new(self, 3)
}
#[doc = "Bit 4 - Real Time Clock Minutes Bit: 4"]
#[inline(always)]
pub fn minutes4(&mut self) -> Minutes4W<'_, RtcaminSpec> {
Minutes4W::new(self, 4)
}
#[doc = "Bit 5 - Real Time Clock Minutes Bit: 5"]
#[inline(always)]
pub fn minutes5(&mut self) -> Minutes5W<'_, RtcaminSpec> {
Minutes5W::new(self, 5)
}
#[doc = "Bit 6 - Real Time Clock Minutes Bit: 6"]
#[inline(always)]
pub fn minutes6(&mut self) -> Minutes6W<'_, RtcaminSpec> {
Minutes6W::new(self, 6)
}
#[doc = "Bit 7 - Real Time Clock Alarm enable"]
#[inline(always)]
pub fn rtcae(&mut self) -> RtcaeW<'_, RtcaminSpec> {
RtcaeW::new(self, 7)
}
}
#[doc = "Real Time Clock Alarm Min\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcamin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcamin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcaminSpec;
impl crate::RegisterSpec for RtcaminSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`rtcamin::R`](R) reader structure"]
impl crate::Readable for RtcaminSpec {}
#[doc = "`write(|w| ..)` method takes [`rtcamin::W`](W) writer structure"]
impl crate::Writable for RtcaminSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets RTCAMIN to value 0"]
impl crate::Resettable for RtcaminSpec {}
}
#[doc = "RTCAHOUR (rw) register accessor: Real Time Clock Alarm Hour\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcahour::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcahour::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtcahour`] module"]
#[doc(alias = "RTCAHOUR")]
pub type Rtcahour = crate::Reg<rtcahour::RtcahourSpec>;
#[doc = "Real Time Clock Alarm Hour"]
pub mod rtcahour {
#[doc = "Register `RTCAHOUR` reader"]
pub type R = crate::R<RtcahourSpec>;
#[doc = "Register `RTCAHOUR` writer"]
pub type W = crate::W<RtcahourSpec>;
#[doc = "Field `HOUR0` reader - Real Time Clock Hour Bit: 0"]
pub type Hour0R = crate::BitReader;
#[doc = "Field `HOUR0` writer - Real Time Clock Hour Bit: 0"]
pub type Hour0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HOUR1` reader - Real Time Clock Hour Bit: 1"]
pub type Hour1R = crate::BitReader;
#[doc = "Field `HOUR1` writer - Real Time Clock Hour Bit: 1"]
pub type Hour1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HOUR2` reader - Real Time Clock Hour Bit: 2"]
pub type Hour2R = crate::BitReader;
#[doc = "Field `HOUR2` writer - Real Time Clock Hour Bit: 2"]
pub type Hour2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HOUR3` reader - Real Time Clock Hour Bit: 3"]
pub type Hour3R = crate::BitReader;
#[doc = "Field `HOUR3` writer - Real Time Clock Hour Bit: 3"]
pub type Hour3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HOUR4` reader - Real Time Clock Hour Bit: 4"]
pub type Hour4R = crate::BitReader;
#[doc = "Field `HOUR4` writer - Real Time Clock Hour Bit: 4"]
pub type Hour4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HOUR5` reader - Real Time Clock Hour Bit: 5"]
pub type Hour5R = crate::BitReader;
#[doc = "Field `HOUR5` writer - Real Time Clock Hour Bit: 5"]
pub type Hour5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HOUR6` reader - Real Time Clock Hour Bit: 6"]
pub type Hour6R = crate::BitReader;
#[doc = "Field `HOUR6` writer - Real Time Clock Hour Bit: 6"]
pub type Hour6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCAE` reader - Real Time Clock Alarm enable"]
pub type RtcaeR = crate::BitReader;
#[doc = "Field `RTCAE` writer - Real Time Clock Alarm enable"]
pub type RtcaeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Real Time Clock Hour Bit: 0"]
#[inline(always)]
pub fn hour0(&self) -> Hour0R {
Hour0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Real Time Clock Hour Bit: 1"]
#[inline(always)]
pub fn hour1(&self) -> Hour1R {
Hour1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Real Time Clock Hour Bit: 2"]
#[inline(always)]
pub fn hour2(&self) -> Hour2R {
Hour2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Real Time Clock Hour Bit: 3"]
#[inline(always)]
pub fn hour3(&self) -> Hour3R {
Hour3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Real Time Clock Hour Bit: 4"]
#[inline(always)]
pub fn hour4(&self) -> Hour4R {
Hour4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Real Time Clock Hour Bit: 5"]
#[inline(always)]
pub fn hour5(&self) -> Hour5R {
Hour5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Real Time Clock Hour Bit: 6"]
#[inline(always)]
pub fn hour6(&self) -> Hour6R {
Hour6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Real Time Clock Alarm enable"]
#[inline(always)]
pub fn rtcae(&self) -> RtcaeR {
RtcaeR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Real Time Clock Hour Bit: 0"]
#[inline(always)]
pub fn hour0(&mut self) -> Hour0W<'_, RtcahourSpec> {
Hour0W::new(self, 0)
}
#[doc = "Bit 1 - Real Time Clock Hour Bit: 1"]
#[inline(always)]
pub fn hour1(&mut self) -> Hour1W<'_, RtcahourSpec> {
Hour1W::new(self, 1)
}
#[doc = "Bit 2 - Real Time Clock Hour Bit: 2"]
#[inline(always)]
pub fn hour2(&mut self) -> Hour2W<'_, RtcahourSpec> {
Hour2W::new(self, 2)
}
#[doc = "Bit 3 - Real Time Clock Hour Bit: 3"]
#[inline(always)]
pub fn hour3(&mut self) -> Hour3W<'_, RtcahourSpec> {
Hour3W::new(self, 3)
}
#[doc = "Bit 4 - Real Time Clock Hour Bit: 4"]
#[inline(always)]
pub fn hour4(&mut self) -> Hour4W<'_, RtcahourSpec> {
Hour4W::new(self, 4)
}
#[doc = "Bit 5 - Real Time Clock Hour Bit: 5"]
#[inline(always)]
pub fn hour5(&mut self) -> Hour5W<'_, RtcahourSpec> {
Hour5W::new(self, 5)
}
#[doc = "Bit 6 - Real Time Clock Hour Bit: 6"]
#[inline(always)]
pub fn hour6(&mut self) -> Hour6W<'_, RtcahourSpec> {
Hour6W::new(self, 6)
}
#[doc = "Bit 7 - Real Time Clock Alarm enable"]
#[inline(always)]
pub fn rtcae(&mut self) -> RtcaeW<'_, RtcahourSpec> {
RtcaeW::new(self, 7)
}
}
#[doc = "Real Time Clock Alarm Hour\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcahour::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcahour::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcahourSpec;
impl crate::RegisterSpec for RtcahourSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`rtcahour::R`](R) reader structure"]
impl crate::Readable for RtcahourSpec {}
#[doc = "`write(|w| ..)` method takes [`rtcahour::W`](W) writer structure"]
impl crate::Writable for RtcahourSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets RTCAHOUR to value 0"]
impl crate::Resettable for RtcahourSpec {}
}
#[doc = "RTCADOW (rw) register accessor: Real Time Clock Alarm Day of week\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcadow::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcadow::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtcadow`] module"]
#[doc(alias = "RTCADOW")]
pub type Rtcadow = crate::Reg<rtcadow::RtcadowSpec>;
#[doc = "Real Time Clock Alarm Day of week"]
pub mod rtcadow {
#[doc = "Register `RTCADOW` reader"]
pub type R = crate::R<RtcadowSpec>;
#[doc = "Register `RTCADOW` writer"]
pub type W = crate::W<RtcadowSpec>;
#[doc = "Field `DOW0` reader - Real Time Clock DOW Bit: 0"]
pub type Dow0R = crate::BitReader;
#[doc = "Field `DOW0` writer - Real Time Clock DOW Bit: 0"]
pub type Dow0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DOW1` reader - Real Time Clock DOW Bit: 1"]
pub type Dow1R = crate::BitReader;
#[doc = "Field `DOW1` writer - Real Time Clock DOW Bit: 1"]
pub type Dow1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DOW2` reader - Real Time Clock DOW Bit: 2"]
pub type Dow2R = crate::BitReader;
#[doc = "Field `DOW2` writer - Real Time Clock DOW Bit: 2"]
pub type Dow2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DOW3` reader - Real Time Clock DOW Bit: 3"]
pub type Dow3R = crate::BitReader;
#[doc = "Field `DOW3` writer - Real Time Clock DOW Bit: 3"]
pub type Dow3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DOW4` reader - Real Time Clock DOW Bit: 4"]
pub type Dow4R = crate::BitReader;
#[doc = "Field `DOW4` writer - Real Time Clock DOW Bit: 4"]
pub type Dow4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DOW5` reader - Real Time Clock DOW Bit: 5"]
pub type Dow5R = crate::BitReader;
#[doc = "Field `DOW5` writer - Real Time Clock DOW Bit: 5"]
pub type Dow5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DOW6` reader - Real Time Clock DOW Bit: 6"]
pub type Dow6R = crate::BitReader;
#[doc = "Field `DOW6` writer - Real Time Clock DOW Bit: 6"]
pub type Dow6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCAE` reader - Real Time Clock Alarm enable"]
pub type RtcaeR = crate::BitReader;
#[doc = "Field `RTCAE` writer - Real Time Clock Alarm enable"]
pub type RtcaeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Real Time Clock DOW Bit: 0"]
#[inline(always)]
pub fn dow0(&self) -> Dow0R {
Dow0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Real Time Clock DOW Bit: 1"]
#[inline(always)]
pub fn dow1(&self) -> Dow1R {
Dow1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Real Time Clock DOW Bit: 2"]
#[inline(always)]
pub fn dow2(&self) -> Dow2R {
Dow2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Real Time Clock DOW Bit: 3"]
#[inline(always)]
pub fn dow3(&self) -> Dow3R {
Dow3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Real Time Clock DOW Bit: 4"]
#[inline(always)]
pub fn dow4(&self) -> Dow4R {
Dow4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Real Time Clock DOW Bit: 5"]
#[inline(always)]
pub fn dow5(&self) -> Dow5R {
Dow5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Real Time Clock DOW Bit: 6"]
#[inline(always)]
pub fn dow6(&self) -> Dow6R {
Dow6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Real Time Clock Alarm enable"]
#[inline(always)]
pub fn rtcae(&self) -> RtcaeR {
RtcaeR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Real Time Clock DOW Bit: 0"]
#[inline(always)]
pub fn dow0(&mut self) -> Dow0W<'_, RtcadowSpec> {
Dow0W::new(self, 0)
}
#[doc = "Bit 1 - Real Time Clock DOW Bit: 1"]
#[inline(always)]
pub fn dow1(&mut self) -> Dow1W<'_, RtcadowSpec> {
Dow1W::new(self, 1)
}
#[doc = "Bit 2 - Real Time Clock DOW Bit: 2"]
#[inline(always)]
pub fn dow2(&mut self) -> Dow2W<'_, RtcadowSpec> {
Dow2W::new(self, 2)
}
#[doc = "Bit 3 - Real Time Clock DOW Bit: 3"]
#[inline(always)]
pub fn dow3(&mut self) -> Dow3W<'_, RtcadowSpec> {
Dow3W::new(self, 3)
}
#[doc = "Bit 4 - Real Time Clock DOW Bit: 4"]
#[inline(always)]
pub fn dow4(&mut self) -> Dow4W<'_, RtcadowSpec> {
Dow4W::new(self, 4)
}
#[doc = "Bit 5 - Real Time Clock DOW Bit: 5"]
#[inline(always)]
pub fn dow5(&mut self) -> Dow5W<'_, RtcadowSpec> {
Dow5W::new(self, 5)
}
#[doc = "Bit 6 - Real Time Clock DOW Bit: 6"]
#[inline(always)]
pub fn dow6(&mut self) -> Dow6W<'_, RtcadowSpec> {
Dow6W::new(self, 6)
}
#[doc = "Bit 7 - Real Time Clock Alarm enable"]
#[inline(always)]
pub fn rtcae(&mut self) -> RtcaeW<'_, RtcadowSpec> {
RtcaeW::new(self, 7)
}
}
#[doc = "Real Time Clock Alarm Day of week\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcadow::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcadow::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcadowSpec;
impl crate::RegisterSpec for RtcadowSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`rtcadow::R`](R) reader structure"]
impl crate::Readable for RtcadowSpec {}
#[doc = "`write(|w| ..)` method takes [`rtcadow::W`](W) writer structure"]
impl crate::Writable for RtcadowSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets RTCADOW to value 0"]
impl crate::Resettable for RtcadowSpec {}
}
#[doc = "RTCADAY (rw) register accessor: Real Time Clock Alarm Day\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcaday::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcaday::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtcaday`] module"]
#[doc(alias = "RTCADAY")]
pub type Rtcaday = crate::Reg<rtcaday::RtcadaySpec>;
#[doc = "Real Time Clock Alarm Day"]
pub mod rtcaday {
#[doc = "Register `RTCADAY` reader"]
pub type R = crate::R<RtcadaySpec>;
#[doc = "Register `RTCADAY` writer"]
pub type W = crate::W<RtcadaySpec>;
#[doc = "Field `DAY0` reader - Real Time Clock Day Bit: 0"]
pub type Day0R = crate::BitReader;
#[doc = "Field `DAY0` writer - Real Time Clock Day Bit: 0"]
pub type Day0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DAY1` reader - Real Time Clock Day Bit: 1"]
pub type Day1R = crate::BitReader;
#[doc = "Field `DAY1` writer - Real Time Clock Day Bit: 1"]
pub type Day1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DAY2` reader - Real Time Clock Day Bit: 2"]
pub type Day2R = crate::BitReader;
#[doc = "Field `DAY2` writer - Real Time Clock Day Bit: 2"]
pub type Day2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DAY3` reader - Real Time Clock Day Bit: 3"]
pub type Day3R = crate::BitReader;
#[doc = "Field `DAY3` writer - Real Time Clock Day Bit: 3"]
pub type Day3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DAY4` reader - Real Time Clock Day Bit: 4"]
pub type Day4R = crate::BitReader;
#[doc = "Field `DAY4` writer - Real Time Clock Day Bit: 4"]
pub type Day4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DAY5` reader - Real Time Clock Day Bit: 5"]
pub type Day5R = crate::BitReader;
#[doc = "Field `DAY5` writer - Real Time Clock Day Bit: 5"]
pub type Day5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DAY6` reader - Real Time Clock Day Bit: 6"]
pub type Day6R = crate::BitReader;
#[doc = "Field `DAY6` writer - Real Time Clock Day Bit: 6"]
pub type Day6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCAE` reader - Real Time Clock Alarm enable"]
pub type RtcaeR = crate::BitReader;
#[doc = "Field `RTCAE` writer - Real Time Clock Alarm enable"]
pub type RtcaeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Real Time Clock Day Bit: 0"]
#[inline(always)]
pub fn day0(&self) -> Day0R {
Day0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Real Time Clock Day Bit: 1"]
#[inline(always)]
pub fn day1(&self) -> Day1R {
Day1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Real Time Clock Day Bit: 2"]
#[inline(always)]
pub fn day2(&self) -> Day2R {
Day2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Real Time Clock Day Bit: 3"]
#[inline(always)]
pub fn day3(&self) -> Day3R {
Day3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Real Time Clock Day Bit: 4"]
#[inline(always)]
pub fn day4(&self) -> Day4R {
Day4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Real Time Clock Day Bit: 5"]
#[inline(always)]
pub fn day5(&self) -> Day5R {
Day5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Real Time Clock Day Bit: 6"]
#[inline(always)]
pub fn day6(&self) -> Day6R {
Day6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Real Time Clock Alarm enable"]
#[inline(always)]
pub fn rtcae(&self) -> RtcaeR {
RtcaeR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Real Time Clock Day Bit: 0"]
#[inline(always)]
pub fn day0(&mut self) -> Day0W<'_, RtcadaySpec> {
Day0W::new(self, 0)
}
#[doc = "Bit 1 - Real Time Clock Day Bit: 1"]
#[inline(always)]
pub fn day1(&mut self) -> Day1W<'_, RtcadaySpec> {
Day1W::new(self, 1)
}
#[doc = "Bit 2 - Real Time Clock Day Bit: 2"]
#[inline(always)]
pub fn day2(&mut self) -> Day2W<'_, RtcadaySpec> {
Day2W::new(self, 2)
}
#[doc = "Bit 3 - Real Time Clock Day Bit: 3"]
#[inline(always)]
pub fn day3(&mut self) -> Day3W<'_, RtcadaySpec> {
Day3W::new(self, 3)
}
#[doc = "Bit 4 - Real Time Clock Day Bit: 4"]
#[inline(always)]
pub fn day4(&mut self) -> Day4W<'_, RtcadaySpec> {
Day4W::new(self, 4)
}
#[doc = "Bit 5 - Real Time Clock Day Bit: 5"]
#[inline(always)]
pub fn day5(&mut self) -> Day5W<'_, RtcadaySpec> {
Day5W::new(self, 5)
}
#[doc = "Bit 6 - Real Time Clock Day Bit: 6"]
#[inline(always)]
pub fn day6(&mut self) -> Day6W<'_, RtcadaySpec> {
Day6W::new(self, 6)
}
#[doc = "Bit 7 - Real Time Clock Alarm enable"]
#[inline(always)]
pub fn rtcae(&mut self) -> RtcaeW<'_, RtcadaySpec> {
RtcaeW::new(self, 7)
}
}
#[doc = "Real Time Clock Alarm Day\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcaday::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcaday::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcadaySpec;
impl crate::RegisterSpec for RtcadaySpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`rtcaday::R`](R) reader structure"]
impl crate::Readable for RtcadaySpec {}
#[doc = "`write(|w| ..)` method takes [`rtcaday::W`](W) writer structure"]
impl crate::Writable for RtcadaySpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets RTCADAY to value 0"]
impl crate::Resettable for RtcadaySpec {}
}
#[doc = "RTCCTL01 (rw) register accessor: Real Timer Control 0/1\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcctl01::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcctl01::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtcctl01`] module"]
#[doc(alias = "RTCCTL01")]
pub type Rtcctl01 = crate::Reg<rtcctl01::Rtcctl01Spec>;
#[doc = "Real Timer Control 0/1"]
pub mod rtcctl01 {
#[doc = "Register `RTCCTL01` reader"]
pub type R = crate::R<Rtcctl01Spec>;
#[doc = "Register `RTCCTL01` writer"]
pub type W = crate::W<Rtcctl01Spec>;
#[doc = "Field `RTCRDYIFG` reader - RTC Ready Interrupt Flag"]
pub type RtcrdyifgR = crate::BitReader;
#[doc = "Field `RTCRDYIFG` writer - RTC Ready Interrupt Flag"]
pub type RtcrdyifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCAIFG` reader - RTC Alarm Interrupt Flag"]
pub type RtcaifgR = crate::BitReader;
#[doc = "Field `RTCAIFG` writer - RTC Alarm Interrupt Flag"]
pub type RtcaifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCTEVIFG` reader - RTC Time Event Interrupt Flag"]
pub type RtctevifgR = crate::BitReader;
#[doc = "Field `RTCTEVIFG` writer - RTC Time Event Interrupt Flag"]
pub type RtctevifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCOFIFG` reader - RTC 32kHz cyrstal oscillator fault interrupt flag"]
pub type RtcofifgR = crate::BitReader;
#[doc = "Field `RTCOFIFG` writer - RTC 32kHz cyrstal oscillator fault interrupt flag"]
pub type RtcofifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCRDYIE` reader - RTC Ready Interrupt Enable Flag"]
pub type RtcrdyieR = crate::BitReader;
#[doc = "Field `RTCRDYIE` writer - RTC Ready Interrupt Enable Flag"]
pub type RtcrdyieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCAIE` reader - RTC Alarm Interrupt Enable Flag"]
pub type RtcaieR = crate::BitReader;
#[doc = "Field `RTCAIE` writer - RTC Alarm Interrupt Enable Flag"]
pub type RtcaieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCTEVIE` reader - RTC Time Event Interrupt Enable Flag"]
pub type RtctevieR = crate::BitReader;
#[doc = "Field `RTCTEVIE` writer - RTC Time Event Interrupt Enable Flag"]
pub type RtctevieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCOFIE` reader - RTC 32kHz cyrstal oscillator fault interrupt enable"]
pub type RtcofieR = crate::BitReader;
#[doc = "Field `RTCOFIE` writer - RTC 32kHz cyrstal oscillator fault interrupt enable"]
pub type RtcofieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "RTC Time Event 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Rtctev {
#[doc = "0: RTC Time Event: 0 (Min. changed)"]
Rtctev0 = 0,
#[doc = "1: RTC Time Event: 1 (Hour changed)"]
Rtctev1 = 1,
#[doc = "2: RTC Time Event: 2 (12:00 changed)"]
Rtctev2 = 2,
#[doc = "3: RTC Time Event: 3 (00:00 changed)"]
Rtctev3 = 3,
}
impl From<Rtctev> for u8 {
#[inline(always)]
fn from(variant: Rtctev) -> Self {
variant as _
}
}
impl crate::FieldSpec for Rtctev {
type Ux = u8;
}
impl crate::IsEnum for Rtctev {}
#[doc = "Field `RTCTEV` reader - RTC Time Event 1"]
pub type RtctevR = crate::FieldReader<Rtctev>;
impl RtctevR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Rtctev {
match self.bits {
0 => Rtctev::Rtctev0,
1 => Rtctev::Rtctev1,
2 => Rtctev::Rtctev2,
3 => Rtctev::Rtctev3,
_ => unreachable!(),
}
}
#[doc = "RTC Time Event: 0 (Min. changed)"]
#[inline(always)]
pub fn is_rtctev_0(&self) -> bool {
*self == Rtctev::Rtctev0
}
#[doc = "RTC Time Event: 1 (Hour changed)"]
#[inline(always)]
pub fn is_rtctev_1(&self) -> bool {
*self == Rtctev::Rtctev1
}
#[doc = "RTC Time Event: 2 (12:00 changed)"]
#[inline(always)]
pub fn is_rtctev_2(&self) -> bool {
*self == Rtctev::Rtctev2
}
#[doc = "RTC Time Event: 3 (00:00 changed)"]
#[inline(always)]
pub fn is_rtctev_3(&self) -> bool {
*self == Rtctev::Rtctev3
}
}
#[doc = "Field `RTCTEV` writer - RTC Time Event 1"]
pub type RtctevW<'a, REG> = crate::FieldWriter<'a, REG, 2, Rtctev, crate::Safe>;
impl<'a, REG> RtctevW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "RTC Time Event: 0 (Min. changed)"]
#[inline(always)]
pub fn rtctev_0(self) -> &'a mut crate::W<REG> {
self.variant(Rtctev::Rtctev0)
}
#[doc = "RTC Time Event: 1 (Hour changed)"]
#[inline(always)]
pub fn rtctev_1(self) -> &'a mut crate::W<REG> {
self.variant(Rtctev::Rtctev1)
}
#[doc = "RTC Time Event: 2 (12:00 changed)"]
#[inline(always)]
pub fn rtctev_2(self) -> &'a mut crate::W<REG> {
self.variant(Rtctev::Rtctev2)
}
#[doc = "RTC Time Event: 3 (00:00 changed)"]
#[inline(always)]
pub fn rtctev_3(self) -> &'a mut crate::W<REG> {
self.variant(Rtctev::Rtctev3)
}
}
#[doc = "Field `RTCRDY` reader - RTC Ready"]
pub type RtcrdyR = crate::BitReader;
#[doc = "Field `RTCRDY` writer - RTC Ready"]
pub type RtcrdyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCHOLD` reader - RTC Hold"]
pub type RtcholdR = crate::BitReader;
#[doc = "Field `RTCHOLD` writer - RTC Hold"]
pub type RtcholdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCBCD` reader - RTC BCD 0:Binary / 1:BCD"]
pub type RtcbcdR = crate::BitReader;
#[doc = "Field `RTCBCD` writer - RTC BCD 0:Binary / 1:BCD"]
pub type RtcbcdW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RTC Ready Interrupt Flag"]
#[inline(always)]
pub fn rtcrdyifg(&self) -> RtcrdyifgR {
RtcrdyifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RTC Alarm Interrupt Flag"]
#[inline(always)]
pub fn rtcaifg(&self) -> RtcaifgR {
RtcaifgR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RTC Time Event Interrupt Flag"]
#[inline(always)]
pub fn rtctevifg(&self) -> RtctevifgR {
RtctevifgR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RTC 32kHz cyrstal oscillator fault interrupt flag"]
#[inline(always)]
pub fn rtcofifg(&self) -> RtcofifgR {
RtcofifgR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RTC Ready Interrupt Enable Flag"]
#[inline(always)]
pub fn rtcrdyie(&self) -> RtcrdyieR {
RtcrdyieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RTC Alarm Interrupt Enable Flag"]
#[inline(always)]
pub fn rtcaie(&self) -> RtcaieR {
RtcaieR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RTC Time Event Interrupt Enable Flag"]
#[inline(always)]
pub fn rtctevie(&self) -> RtctevieR {
RtctevieR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RTC 32kHz cyrstal oscillator fault interrupt enable"]
#[inline(always)]
pub fn rtcofie(&self) -> RtcofieR {
RtcofieR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - RTC Time Event 1"]
#[inline(always)]
pub fn rtctev(&self) -> RtctevR {
RtctevR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 12 - RTC Ready"]
#[inline(always)]
pub fn rtcrdy(&self) -> RtcrdyR {
RtcrdyR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 14 - RTC Hold"]
#[inline(always)]
pub fn rtchold(&self) -> RtcholdR {
RtcholdR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - RTC BCD 0:Binary / 1:BCD"]
#[inline(always)]
pub fn rtcbcd(&self) -> RtcbcdR {
RtcbcdR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RTC Ready Interrupt Flag"]
#[inline(always)]
pub fn rtcrdyifg(&mut self) -> RtcrdyifgW<'_, Rtcctl01Spec> {
RtcrdyifgW::new(self, 0)
}
#[doc = "Bit 1 - RTC Alarm Interrupt Flag"]
#[inline(always)]
pub fn rtcaifg(&mut self) -> RtcaifgW<'_, Rtcctl01Spec> {
RtcaifgW::new(self, 1)
}
#[doc = "Bit 2 - RTC Time Event Interrupt Flag"]
#[inline(always)]
pub fn rtctevifg(&mut self) -> RtctevifgW<'_, Rtcctl01Spec> {
RtctevifgW::new(self, 2)
}
#[doc = "Bit 3 - RTC 32kHz cyrstal oscillator fault interrupt flag"]
#[inline(always)]
pub fn rtcofifg(&mut self) -> RtcofifgW<'_, Rtcctl01Spec> {
RtcofifgW::new(self, 3)
}
#[doc = "Bit 4 - RTC Ready Interrupt Enable Flag"]
#[inline(always)]
pub fn rtcrdyie(&mut self) -> RtcrdyieW<'_, Rtcctl01Spec> {
RtcrdyieW::new(self, 4)
}
#[doc = "Bit 5 - RTC Alarm Interrupt Enable Flag"]
#[inline(always)]
pub fn rtcaie(&mut self) -> RtcaieW<'_, Rtcctl01Spec> {
RtcaieW::new(self, 5)
}
#[doc = "Bit 6 - RTC Time Event Interrupt Enable Flag"]
#[inline(always)]
pub fn rtctevie(&mut self) -> RtctevieW<'_, Rtcctl01Spec> {
RtctevieW::new(self, 6)
}
#[doc = "Bit 7 - RTC 32kHz cyrstal oscillator fault interrupt enable"]
#[inline(always)]
pub fn rtcofie(&mut self) -> RtcofieW<'_, Rtcctl01Spec> {
RtcofieW::new(self, 7)
}
#[doc = "Bits 8:9 - RTC Time Event 1"]
#[inline(always)]
pub fn rtctev(&mut self) -> RtctevW<'_, Rtcctl01Spec> {
RtctevW::new(self, 8)
}
#[doc = "Bit 12 - RTC Ready"]
#[inline(always)]
pub fn rtcrdy(&mut self) -> RtcrdyW<'_, Rtcctl01Spec> {
RtcrdyW::new(self, 12)
}
#[doc = "Bit 14 - RTC Hold"]
#[inline(always)]
pub fn rtchold(&mut self) -> RtcholdW<'_, Rtcctl01Spec> {
RtcholdW::new(self, 14)
}
#[doc = "Bit 15 - RTC BCD 0:Binary / 1:BCD"]
#[inline(always)]
pub fn rtcbcd(&mut self) -> RtcbcdW<'_, Rtcctl01Spec> {
RtcbcdW::new(self, 15)
}
}
#[doc = "Real Timer Control 0/1\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcctl01::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcctl01::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtcctl01Spec;
impl crate::RegisterSpec for Rtcctl01Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`rtcctl01::R`](R) reader structure"]
impl crate::Readable for Rtcctl01Spec {}
#[doc = "`write(|w| ..)` method takes [`rtcctl01::W`](W) writer structure"]
impl crate::Writable for Rtcctl01Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTCCTL01 to value 0"]
impl crate::Resettable for Rtcctl01Spec {}
}
#[doc = "RTCCTL23 (rw) register accessor: Real Timer Control 2/3\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcctl23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcctl23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtcctl23`] module"]
#[doc(alias = "RTCCTL23")]
pub type Rtcctl23 = crate::Reg<rtcctl23::Rtcctl23Spec>;
#[doc = "Real Timer Control 2/3"]
pub mod rtcctl23 {
#[doc = "Register `RTCCTL23` reader"]
pub type R = crate::R<Rtcctl23Spec>;
#[doc = "Register `RTCCTL23` writer"]
pub type W = crate::W<Rtcctl23Spec>;
#[doc = "Field `RTCCAL0` reader - RTC Calibration Bit 0"]
pub type Rtccal0R = crate::BitReader;
#[doc = "Field `RTCCAL0` writer - RTC Calibration Bit 0"]
pub type Rtccal0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCCAL1` reader - RTC Calibration Bit 1"]
pub type Rtccal1R = crate::BitReader;
#[doc = "Field `RTCCAL1` writer - RTC Calibration Bit 1"]
pub type Rtccal1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCCAL2` reader - RTC Calibration Bit 2"]
pub type Rtccal2R = crate::BitReader;
#[doc = "Field `RTCCAL2` writer - RTC Calibration Bit 2"]
pub type Rtccal2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCCAL3` reader - RTC Calibration Bit 3"]
pub type Rtccal3R = crate::BitReader;
#[doc = "Field `RTCCAL3` writer - RTC Calibration Bit 3"]
pub type Rtccal3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCCAL4` reader - RTC Calibration Bit 4"]
pub type Rtccal4R = crate::BitReader;
#[doc = "Field `RTCCAL4` writer - RTC Calibration Bit 4"]
pub type Rtccal4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCCAL5` reader - RTC Calibration Bit 5"]
pub type Rtccal5R = crate::BitReader;
#[doc = "Field `RTCCAL5` writer - RTC Calibration Bit 5"]
pub type Rtccal5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTCCALS` reader - RTC Calibration Sign"]
pub type RtccalsR = crate::BitReader;
#[doc = "Field `RTCCALS` writer - RTC Calibration Sign"]
pub type RtccalsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "RTC Calibration Frequency Bit 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Rtccalf {
#[doc = "0: RTC Calibration Frequency: No Output"]
Rtccalf0 = 0,
#[doc = "1: RTC Calibration Frequency: 512 Hz"]
Rtccalf1 = 1,
#[doc = "2: RTC Calibration Frequency: 256 Hz"]
Rtccalf2 = 2,
#[doc = "3: RTC Calibration Frequency: 1 Hz"]
Rtccalf3 = 3,
}
impl From<Rtccalf> for u8 {
#[inline(always)]
fn from(variant: Rtccalf) -> Self {
variant as _
}
}
impl crate::FieldSpec for Rtccalf {
type Ux = u8;
}
impl crate::IsEnum for Rtccalf {}
#[doc = "Field `RTCCALF` reader - RTC Calibration Frequency Bit 1"]
pub type RtccalfR = crate::FieldReader<Rtccalf>;
impl RtccalfR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Rtccalf {
match self.bits {
0 => Rtccalf::Rtccalf0,
1 => Rtccalf::Rtccalf1,
2 => Rtccalf::Rtccalf2,
3 => Rtccalf::Rtccalf3,
_ => unreachable!(),
}
}
#[doc = "RTC Calibration Frequency: No Output"]
#[inline(always)]
pub fn is_rtccalf_0(&self) -> bool {
*self == Rtccalf::Rtccalf0
}
#[doc = "RTC Calibration Frequency: 512 Hz"]
#[inline(always)]
pub fn is_rtccalf_1(&self) -> bool {
*self == Rtccalf::Rtccalf1
}
#[doc = "RTC Calibration Frequency: 256 Hz"]
#[inline(always)]
pub fn is_rtccalf_2(&self) -> bool {
*self == Rtccalf::Rtccalf2
}
#[doc = "RTC Calibration Frequency: 1 Hz"]
#[inline(always)]
pub fn is_rtccalf_3(&self) -> bool {
*self == Rtccalf::Rtccalf3
}
}
#[doc = "Field `RTCCALF` writer - RTC Calibration Frequency Bit 1"]
pub type RtccalfW<'a, REG> = crate::FieldWriter<'a, REG, 2, Rtccalf, crate::Safe>;
impl<'a, REG> RtccalfW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "RTC Calibration Frequency: No Output"]
#[inline(always)]
pub fn rtccalf_0(self) -> &'a mut crate::W<REG> {
self.variant(Rtccalf::Rtccalf0)
}
#[doc = "RTC Calibration Frequency: 512 Hz"]
#[inline(always)]
pub fn rtccalf_1(self) -> &'a mut crate::W<REG> {
self.variant(Rtccalf::Rtccalf1)
}
#[doc = "RTC Calibration Frequency: 256 Hz"]
#[inline(always)]
pub fn rtccalf_2(self) -> &'a mut crate::W<REG> {
self.variant(Rtccalf::Rtccalf2)
}
#[doc = "RTC Calibration Frequency: 1 Hz"]
#[inline(always)]
pub fn rtccalf_3(self) -> &'a mut crate::W<REG> {
self.variant(Rtccalf::Rtccalf3)
}
}
impl R {
#[doc = "Bit 0 - RTC Calibration Bit 0"]
#[inline(always)]
pub fn rtccal0(&self) -> Rtccal0R {
Rtccal0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RTC Calibration Bit 1"]
#[inline(always)]
pub fn rtccal1(&self) -> Rtccal1R {
Rtccal1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RTC Calibration Bit 2"]
#[inline(always)]
pub fn rtccal2(&self) -> Rtccal2R {
Rtccal2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RTC Calibration Bit 3"]
#[inline(always)]
pub fn rtccal3(&self) -> Rtccal3R {
Rtccal3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - RTC Calibration Bit 4"]
#[inline(always)]
pub fn rtccal4(&self) -> Rtccal4R {
Rtccal4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RTC Calibration Bit 5"]
#[inline(always)]
pub fn rtccal5(&self) -> Rtccal5R {
Rtccal5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 7 - RTC Calibration Sign"]
#[inline(always)]
pub fn rtccals(&self) -> RtccalsR {
RtccalsR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - RTC Calibration Frequency Bit 1"]
#[inline(always)]
pub fn rtccalf(&self) -> RtccalfR {
RtccalfR::new(((self.bits >> 8) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - RTC Calibration Bit 0"]
#[inline(always)]
pub fn rtccal0(&mut self) -> Rtccal0W<'_, Rtcctl23Spec> {
Rtccal0W::new(self, 0)
}
#[doc = "Bit 1 - RTC Calibration Bit 1"]
#[inline(always)]
pub fn rtccal1(&mut self) -> Rtccal1W<'_, Rtcctl23Spec> {
Rtccal1W::new(self, 1)
}
#[doc = "Bit 2 - RTC Calibration Bit 2"]
#[inline(always)]
pub fn rtccal2(&mut self) -> Rtccal2W<'_, Rtcctl23Spec> {
Rtccal2W::new(self, 2)
}
#[doc = "Bit 3 - RTC Calibration Bit 3"]
#[inline(always)]
pub fn rtccal3(&mut self) -> Rtccal3W<'_, Rtcctl23Spec> {
Rtccal3W::new(self, 3)
}
#[doc = "Bit 4 - RTC Calibration Bit 4"]
#[inline(always)]
pub fn rtccal4(&mut self) -> Rtccal4W<'_, Rtcctl23Spec> {
Rtccal4W::new(self, 4)
}
#[doc = "Bit 5 - RTC Calibration Bit 5"]
#[inline(always)]
pub fn rtccal5(&mut self) -> Rtccal5W<'_, Rtcctl23Spec> {
Rtccal5W::new(self, 5)
}
#[doc = "Bit 7 - RTC Calibration Sign"]
#[inline(always)]
pub fn rtccals(&mut self) -> RtccalsW<'_, Rtcctl23Spec> {
RtccalsW::new(self, 7)
}
#[doc = "Bits 8:9 - RTC Calibration Frequency Bit 1"]
#[inline(always)]
pub fn rtccalf(&mut self) -> RtccalfW<'_, Rtcctl23Spec> {
RtccalfW::new(self, 8)
}
}
#[doc = "Real Timer Control 2/3\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcctl23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcctl23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtcctl23Spec;
impl crate::RegisterSpec for Rtcctl23Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`rtcctl23::R`](R) reader structure"]
impl crate::Readable for Rtcctl23Spec {}
#[doc = "`write(|w| ..)` method takes [`rtcctl23::W`](W) writer structure"]
impl crate::Writable for Rtcctl23Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTCCTL23 to value 0"]
impl crate::Resettable for Rtcctl23Spec {}
}
#[doc = "RTCPS0CTL (rw) register accessor: Real Timer Prescale Timer 0 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcps0ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcps0ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtcps0ctl`] module"]
#[doc(alias = "RTCPS0CTL")]
pub type Rtcps0ctl = crate::Reg<rtcps0ctl::Rtcps0ctlSpec>;
#[doc = "Real Timer Prescale Timer 0 Control"]
pub mod rtcps0ctl {
#[doc = "Register `RTCPS0CTL` reader"]
pub type R = crate::R<Rtcps0ctlSpec>;
#[doc = "Register `RTCPS0CTL` writer"]
pub type W = crate::W<Rtcps0ctlSpec>;
#[doc = "Field `RT0PSIFG` reader - RTC Prescale Timer 0 Interrupt Flag"]
pub type Rt0psifgR = crate::BitReader;
#[doc = "Field `RT0PSIFG` writer - RTC Prescale Timer 0 Interrupt Flag"]
pub type Rt0psifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RT0PSIE` reader - RTC Prescale Timer 0 Interrupt Enable Flag"]
pub type Rt0psieR = crate::BitReader;
#[doc = "Field `RT0PSIE` writer - RTC Prescale Timer 0 Interrupt Enable Flag"]
pub type Rt0psieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "RTC Prescale Timer 0 Interrupt Interval Bit: 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Rt0ip {
#[doc = "0: RTC Prescale Timer 0 Interrupt Interval /2"]
Rt0ip0 = 0,
#[doc = "1: RTC Prescale Timer 0 Interrupt Interval /4"]
Rt0ip1 = 1,
#[doc = "2: RTC Prescale Timer 0 Interrupt Interval /8"]
Rt0ip2 = 2,
#[doc = "3: RTC Prescale Timer 0 Interrupt Interval /16"]
Rt0ip3 = 3,
#[doc = "4: RTC Prescale Timer 0 Interrupt Interval /32"]
Rt0ip4 = 4,
#[doc = "5: RTC Prescale Timer 0 Interrupt Interval /64"]
Rt0ip5 = 5,
#[doc = "6: RTC Prescale Timer 0 Interrupt Interval /128"]
Rt0ip6 = 6,
#[doc = "7: RTC Prescale Timer 0 Interrupt Interval /256"]
Rt0ip7 = 7,
}
impl From<Rt0ip> for u8 {
#[inline(always)]
fn from(variant: Rt0ip) -> Self {
variant as _
}
}
impl crate::FieldSpec for Rt0ip {
type Ux = u8;
}
impl crate::IsEnum for Rt0ip {}
#[doc = "Field `RT0IP` reader - RTC Prescale Timer 0 Interrupt Interval Bit: 2"]
pub type Rt0ipR = crate::FieldReader<Rt0ip>;
impl Rt0ipR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Rt0ip {
match self.bits {
0 => Rt0ip::Rt0ip0,
1 => Rt0ip::Rt0ip1,
2 => Rt0ip::Rt0ip2,
3 => Rt0ip::Rt0ip3,
4 => Rt0ip::Rt0ip4,
5 => Rt0ip::Rt0ip5,
6 => Rt0ip::Rt0ip6,
7 => Rt0ip::Rt0ip7,
_ => unreachable!(),
}
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /2"]
#[inline(always)]
pub fn is_rt0ip_0(&self) -> bool {
*self == Rt0ip::Rt0ip0
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /4"]
#[inline(always)]
pub fn is_rt0ip_1(&self) -> bool {
*self == Rt0ip::Rt0ip1
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /8"]
#[inline(always)]
pub fn is_rt0ip_2(&self) -> bool {
*self == Rt0ip::Rt0ip2
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /16"]
#[inline(always)]
pub fn is_rt0ip_3(&self) -> bool {
*self == Rt0ip::Rt0ip3
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /32"]
#[inline(always)]
pub fn is_rt0ip_4(&self) -> bool {
*self == Rt0ip::Rt0ip4
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /64"]
#[inline(always)]
pub fn is_rt0ip_5(&self) -> bool {
*self == Rt0ip::Rt0ip5
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /128"]
#[inline(always)]
pub fn is_rt0ip_6(&self) -> bool {
*self == Rt0ip::Rt0ip6
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /256"]
#[inline(always)]
pub fn is_rt0ip_7(&self) -> bool {
*self == Rt0ip::Rt0ip7
}
}
#[doc = "Field `RT0IP` writer - RTC Prescale Timer 0 Interrupt Interval Bit: 2"]
pub type Rt0ipW<'a, REG> = crate::FieldWriter<'a, REG, 3, Rt0ip, crate::Safe>;
impl<'a, REG> Rt0ipW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "RTC Prescale Timer 0 Interrupt Interval /2"]
#[inline(always)]
pub fn rt0ip_0(self) -> &'a mut crate::W<REG> {
self.variant(Rt0ip::Rt0ip0)
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /4"]
#[inline(always)]
pub fn rt0ip_1(self) -> &'a mut crate::W<REG> {
self.variant(Rt0ip::Rt0ip1)
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /8"]
#[inline(always)]
pub fn rt0ip_2(self) -> &'a mut crate::W<REG> {
self.variant(Rt0ip::Rt0ip2)
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /16"]
#[inline(always)]
pub fn rt0ip_3(self) -> &'a mut crate::W<REG> {
self.variant(Rt0ip::Rt0ip3)
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /32"]
#[inline(always)]
pub fn rt0ip_4(self) -> &'a mut crate::W<REG> {
self.variant(Rt0ip::Rt0ip4)
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /64"]
#[inline(always)]
pub fn rt0ip_5(self) -> &'a mut crate::W<REG> {
self.variant(Rt0ip::Rt0ip5)
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /128"]
#[inline(always)]
pub fn rt0ip_6(self) -> &'a mut crate::W<REG> {
self.variant(Rt0ip::Rt0ip6)
}
#[doc = "RTC Prescale Timer 0 Interrupt Interval /256"]
#[inline(always)]
pub fn rt0ip_7(self) -> &'a mut crate::W<REG> {
self.variant(Rt0ip::Rt0ip7)
}
}
impl R {
#[doc = "Bit 0 - RTC Prescale Timer 0 Interrupt Flag"]
#[inline(always)]
pub fn rt0psifg(&self) -> Rt0psifgR {
Rt0psifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RTC Prescale Timer 0 Interrupt Enable Flag"]
#[inline(always)]
pub fn rt0psie(&self) -> Rt0psieR {
Rt0psieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:4 - RTC Prescale Timer 0 Interrupt Interval Bit: 2"]
#[inline(always)]
pub fn rt0ip(&self) -> Rt0ipR {
Rt0ipR::new(((self.bits >> 2) & 7) as u8)
}
}
impl W {
#[doc = "Bit 0 - RTC Prescale Timer 0 Interrupt Flag"]
#[inline(always)]
pub fn rt0psifg(&mut self) -> Rt0psifgW<'_, Rtcps0ctlSpec> {
Rt0psifgW::new(self, 0)
}
#[doc = "Bit 1 - RTC Prescale Timer 0 Interrupt Enable Flag"]
#[inline(always)]
pub fn rt0psie(&mut self) -> Rt0psieW<'_, Rtcps0ctlSpec> {
Rt0psieW::new(self, 1)
}
#[doc = "Bits 2:4 - RTC Prescale Timer 0 Interrupt Interval Bit: 2"]
#[inline(always)]
pub fn rt0ip(&mut self) -> Rt0ipW<'_, Rtcps0ctlSpec> {
Rt0ipW::new(self, 2)
}
}
#[doc = "Real Timer Prescale Timer 0 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcps0ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcps0ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtcps0ctlSpec;
impl crate::RegisterSpec for Rtcps0ctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`rtcps0ctl::R`](R) reader structure"]
impl crate::Readable for Rtcps0ctlSpec {}
#[doc = "`write(|w| ..)` method takes [`rtcps0ctl::W`](W) writer structure"]
impl crate::Writable for Rtcps0ctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTCPS0CTL to value 0"]
impl crate::Resettable for Rtcps0ctlSpec {}
}
#[doc = "RTCPS1CTL (rw) register accessor: Real Timer Prescale Timer 1 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcps1ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcps1ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtcps1ctl`] module"]
#[doc(alias = "RTCPS1CTL")]
pub type Rtcps1ctl = crate::Reg<rtcps1ctl::Rtcps1ctlSpec>;
#[doc = "Real Timer Prescale Timer 1 Control"]
pub mod rtcps1ctl {
#[doc = "Register `RTCPS1CTL` reader"]
pub type R = crate::R<Rtcps1ctlSpec>;
#[doc = "Register `RTCPS1CTL` writer"]
pub type W = crate::W<Rtcps1ctlSpec>;
#[doc = "Field `RT1PSIFG` reader - RTC Prescale Timer 1 Interrupt Flag"]
pub type Rt1psifgR = crate::BitReader;
#[doc = "Field `RT1PSIFG` writer - RTC Prescale Timer 1 Interrupt Flag"]
pub type Rt1psifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RT1PSIE` reader - RTC Prescale Timer 1 Interrupt Enable Flag"]
pub type Rt1psieR = crate::BitReader;
#[doc = "Field `RT1PSIE` writer - RTC Prescale Timer 1 Interrupt Enable Flag"]
pub type Rt1psieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "RTC Prescale Timer 1 Interrupt Interval Bit: 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Rt1ip {
#[doc = "0: RTC Prescale Timer 1 Interrupt Interval /2"]
Rt1ip0 = 0,
#[doc = "1: RTC Prescale Timer 1 Interrupt Interval /4"]
Rt1ip1 = 1,
#[doc = "2: RTC Prescale Timer 1 Interrupt Interval /8"]
Rt1ip2 = 2,
#[doc = "3: RTC Prescale Timer 1 Interrupt Interval /16"]
Rt1ip3 = 3,
#[doc = "4: RTC Prescale Timer 1 Interrupt Interval /32"]
Rt1ip4 = 4,
#[doc = "5: RTC Prescale Timer 1 Interrupt Interval /64"]
Rt1ip5 = 5,
#[doc = "6: RTC Prescale Timer 1 Interrupt Interval /128"]
Rt1ip6 = 6,
#[doc = "7: RTC Prescale Timer 1 Interrupt Interval /256"]
Rt1ip7 = 7,
}
impl From<Rt1ip> for u8 {
#[inline(always)]
fn from(variant: Rt1ip) -> Self {
variant as _
}
}
impl crate::FieldSpec for Rt1ip {
type Ux = u8;
}
impl crate::IsEnum for Rt1ip {}
#[doc = "Field `RT1IP` reader - RTC Prescale Timer 1 Interrupt Interval Bit: 2"]
pub type Rt1ipR = crate::FieldReader<Rt1ip>;
impl Rt1ipR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Rt1ip {
match self.bits {
0 => Rt1ip::Rt1ip0,
1 => Rt1ip::Rt1ip1,
2 => Rt1ip::Rt1ip2,
3 => Rt1ip::Rt1ip3,
4 => Rt1ip::Rt1ip4,
5 => Rt1ip::Rt1ip5,
6 => Rt1ip::Rt1ip6,
7 => Rt1ip::Rt1ip7,
_ => unreachable!(),
}
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /2"]
#[inline(always)]
pub fn is_rt1ip_0(&self) -> bool {
*self == Rt1ip::Rt1ip0
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /4"]
#[inline(always)]
pub fn is_rt1ip_1(&self) -> bool {
*self == Rt1ip::Rt1ip1
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /8"]
#[inline(always)]
pub fn is_rt1ip_2(&self) -> bool {
*self == Rt1ip::Rt1ip2
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /16"]
#[inline(always)]
pub fn is_rt1ip_3(&self) -> bool {
*self == Rt1ip::Rt1ip3
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /32"]
#[inline(always)]
pub fn is_rt1ip_4(&self) -> bool {
*self == Rt1ip::Rt1ip4
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /64"]
#[inline(always)]
pub fn is_rt1ip_5(&self) -> bool {
*self == Rt1ip::Rt1ip5
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /128"]
#[inline(always)]
pub fn is_rt1ip_6(&self) -> bool {
*self == Rt1ip::Rt1ip6
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /256"]
#[inline(always)]
pub fn is_rt1ip_7(&self) -> bool {
*self == Rt1ip::Rt1ip7
}
}
#[doc = "Field `RT1IP` writer - RTC Prescale Timer 1 Interrupt Interval Bit: 2"]
pub type Rt1ipW<'a, REG> = crate::FieldWriter<'a, REG, 3, Rt1ip, crate::Safe>;
impl<'a, REG> Rt1ipW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "RTC Prescale Timer 1 Interrupt Interval /2"]
#[inline(always)]
pub fn rt1ip_0(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ip::Rt1ip0)
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /4"]
#[inline(always)]
pub fn rt1ip_1(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ip::Rt1ip1)
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /8"]
#[inline(always)]
pub fn rt1ip_2(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ip::Rt1ip2)
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /16"]
#[inline(always)]
pub fn rt1ip_3(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ip::Rt1ip3)
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /32"]
#[inline(always)]
pub fn rt1ip_4(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ip::Rt1ip4)
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /64"]
#[inline(always)]
pub fn rt1ip_5(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ip::Rt1ip5)
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /128"]
#[inline(always)]
pub fn rt1ip_6(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ip::Rt1ip6)
}
#[doc = "RTC Prescale Timer 1 Interrupt Interval /256"]
#[inline(always)]
pub fn rt1ip_7(self) -> &'a mut crate::W<REG> {
self.variant(Rt1ip::Rt1ip7)
}
}
impl R {
#[doc = "Bit 0 - RTC Prescale Timer 1 Interrupt Flag"]
#[inline(always)]
pub fn rt1psifg(&self) -> Rt1psifgR {
Rt1psifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RTC Prescale Timer 1 Interrupt Enable Flag"]
#[inline(always)]
pub fn rt1psie(&self) -> Rt1psieR {
Rt1psieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:4 - RTC Prescale Timer 1 Interrupt Interval Bit: 2"]
#[inline(always)]
pub fn rt1ip(&self) -> Rt1ipR {
Rt1ipR::new(((self.bits >> 2) & 7) as u8)
}
}
impl W {
#[doc = "Bit 0 - RTC Prescale Timer 1 Interrupt Flag"]
#[inline(always)]
pub fn rt1psifg(&mut self) -> Rt1psifgW<'_, Rtcps1ctlSpec> {
Rt1psifgW::new(self, 0)
}
#[doc = "Bit 1 - RTC Prescale Timer 1 Interrupt Enable Flag"]
#[inline(always)]
pub fn rt1psie(&mut self) -> Rt1psieW<'_, Rtcps1ctlSpec> {
Rt1psieW::new(self, 1)
}
#[doc = "Bits 2:4 - RTC Prescale Timer 1 Interrupt Interval Bit: 2"]
#[inline(always)]
pub fn rt1ip(&mut self) -> Rt1ipW<'_, Rtcps1ctlSpec> {
Rt1ipW::new(self, 2)
}
}
#[doc = "Real Timer Prescale Timer 1 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcps1ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcps1ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Rtcps1ctlSpec;
impl crate::RegisterSpec for Rtcps1ctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`rtcps1ctl::R`](R) reader structure"]
impl crate::Readable for Rtcps1ctlSpec {}
#[doc = "`write(|w| ..)` method takes [`rtcps1ctl::W`](W) writer structure"]
impl crate::Writable for Rtcps1ctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTCPS1CTL to value 0"]
impl crate::Resettable for Rtcps1ctlSpec {}
}
#[doc = "RTCPS (rw) register accessor: Real Timer Prescale Timer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcps::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcps::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtcps`] module"]
#[doc(alias = "RTCPS")]
pub type Rtcps = crate::Reg<rtcps::RtcpsSpec>;
#[doc = "Real Timer Prescale Timer Control"]
pub mod rtcps {
#[doc = "Register `RTCPS` reader"]
pub type R = crate::R<RtcpsSpec>;
#[doc = "Register `RTCPS` writer"]
pub type W = crate::W<RtcpsSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Real Timer Prescale Timer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcps::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcps::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcpsSpec;
impl crate::RegisterSpec for RtcpsSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`rtcps::R`](R) reader structure"]
impl crate::Readable for RtcpsSpec {}
#[doc = "`write(|w| ..)` method takes [`rtcps::W`](W) writer structure"]
impl crate::Writable for RtcpsSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTCPS to value 0"]
impl crate::Resettable for RtcpsSpec {}
}
#[doc = "RTCIV (rw) register accessor: Real Time Clock Interrupt Vector\n\nYou can [`read`](crate::Reg::read) this register and get [`rtciv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtciv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtciv`] module"]
#[doc(alias = "RTCIV")]
pub type Rtciv = crate::Reg<rtciv::RtcivSpec>;
#[doc = "Real Time Clock Interrupt Vector"]
pub mod rtciv {
#[doc = "Register `RTCIV` reader"]
pub type R = crate::R<RtcivSpec>;
#[doc = "Register `RTCIV` writer"]
pub type W = crate::W<RtcivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Real Time Clock Interrupt Vector\n\nYou can [`read`](crate::Reg::read) this register and get [`rtciv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtciv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcivSpec;
impl crate::RegisterSpec for RtcivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`rtciv::R`](R) reader structure"]
impl crate::Readable for RtcivSpec {}
#[doc = "`write(|w| ..)` method takes [`rtciv::W`](W) writer structure"]
impl crate::Writable for RtcivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTCIV to value 0"]
impl crate::Resettable for RtcivSpec {}
}
#[doc = "RTCYEAR (rw) register accessor: Real Time Clock Year\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcyear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcyear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtcyear`] module"]
#[doc(alias = "RTCYEAR")]
pub type Rtcyear = crate::Reg<rtcyear::RtcyearSpec>;
#[doc = "Real Time Clock Year"]
pub mod rtcyear {
#[doc = "Register `RTCYEAR` reader"]
pub type R = crate::R<RtcyearSpec>;
#[doc = "Register `RTCYEAR` writer"]
pub type W = crate::W<RtcyearSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Real Time Clock Year\n\nYou can [`read`](crate::Reg::read) this register and get [`rtcyear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtcyear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcyearSpec;
impl crate::RegisterSpec for RtcyearSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`rtcyear::R`](R) reader structure"]
impl crate::Readable for RtcyearSpec {}
#[doc = "`write(|w| ..)` method takes [`rtcyear::W`](W) writer structure"]
impl crate::Writable for RtcyearSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTCYEAR to value 0"]
impl crate::Resettable for RtcyearSpec {}
}
#[doc = "BIN2BCD (rw) register accessor: Real Time Binary-to-BCD conversion register\n\nYou can [`read`](crate::Reg::read) this register and get [`bin2bcd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bin2bcd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bin2bcd`] module"]
#[doc(alias = "BIN2BCD")]
pub type Bin2bcd = crate::Reg<bin2bcd::Bin2bcdSpec>;
#[doc = "Real Time Binary-to-BCD conversion register"]
pub mod bin2bcd {
#[doc = "Register `BIN2BCD` reader"]
pub type R = crate::R<Bin2bcdSpec>;
#[doc = "Register `BIN2BCD` writer"]
pub type W = crate::W<Bin2bcdSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Real Time Binary-to-BCD conversion register\n\nYou can [`read`](crate::Reg::read) this register and get [`bin2bcd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bin2bcd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Bin2bcdSpec;
impl crate::RegisterSpec for Bin2bcdSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`bin2bcd::R`](R) reader structure"]
impl crate::Readable for Bin2bcdSpec {}
#[doc = "`write(|w| ..)` method takes [`bin2bcd::W`](W) writer structure"]
impl crate::Writable for Bin2bcdSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BIN2BCD to value 0"]
impl crate::Resettable for Bin2bcdSpec {}
}
#[doc = "BCD2BIN (rw) register accessor: Real Time BCD-to-binary conversion register\n\nYou can [`read`](crate::Reg::read) this register and get [`bcd2bin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcd2bin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bcd2bin`] module"]
#[doc(alias = "BCD2BIN")]
pub type Bcd2bin = crate::Reg<bcd2bin::Bcd2binSpec>;
#[doc = "Real Time BCD-to-binary conversion register"]
pub mod bcd2bin {
#[doc = "Register `BCD2BIN` reader"]
pub type R = crate::R<Bcd2binSpec>;
#[doc = "Register `BCD2BIN` writer"]
pub type W = crate::W<Bcd2binSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Real Time BCD-to-binary conversion register\n\nYou can [`read`](crate::Reg::read) this register and get [`bcd2bin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcd2bin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Bcd2binSpec;
impl crate::RegisterSpec for Bcd2binSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`bcd2bin::R`](R) reader structure"]
impl crate::Readable for Bcd2binSpec {}
#[doc = "`write(|w| ..)` method takes [`bcd2bin::W`](W) writer structure"]
impl crate::Writable for Bcd2binSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BCD2BIN to value 0"]
impl crate::Resettable for Bcd2binSpec {}
}
}
#[doc = "USCI_A0 UART Mode"]
pub type UsciA0UartMode = crate::Periph<usci_a0_uart_mode::RegisterBlock, 0x05c0>;
impl core::fmt::Debug for UsciA0UartMode {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UsciA0UartMode").finish()
}
}
#[doc = "USCI_A0 UART Mode"]
pub mod usci_a0_uart_mode {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
uca0ctl1: Uca0ctl1,
uca0ctl0: Uca0ctl0,
uca0ctlw1: Uca0ctlw1,
_reserved3: [u8; 0x02],
uca0br0: Uca0br0,
uca0br1: Uca0br1,
uca0mctlw: Uca0mctlw,
uca0statw: Uca0statw,
_reserved7: [u8; 0x01],
uca0rxbuf: Uca0rxbuf,
uca0txbuf: Uca0txbuf,
uca0abctl: Uca0abctl,
_reserved10: [u8; 0x01],
uca0irtctl: Uca0irtctl,
uca0irrctl: Uca0irrctl,
_reserved12: [u8; 0x0a],
uca0iv: Uca0iv,
}
impl RegisterBlock {
#[doc = "0x00 - USCI A0 Control Register 1"]
#[inline(always)]
pub const fn uca0ctl1(&self) -> &Uca0ctl1 {
&self.uca0ctl1
}
#[doc = "0x01 - USCI A0 Control Register 0"]
#[inline(always)]
pub const fn uca0ctl0(&self) -> &Uca0ctl0 {
&self.uca0ctl0
}
#[doc = "0x02 - USCI A0 Control Word Register 1"]
#[inline(always)]
pub const fn uca0ctlw1(&self) -> &Uca0ctlw1 {
&self.uca0ctlw1
}
#[doc = "0x06 - USCI A0 Baud Rate 0"]
#[inline(always)]
pub const fn uca0br0(&self) -> &Uca0br0 {
&self.uca0br0
}
#[doc = "0x07 - USCI A0 Baud Rate 1"]
#[inline(always)]
pub const fn uca0br1(&self) -> &Uca0br1 {
&self.uca0br1
}
#[doc = "0x08 - USCI A0 Modulation Control"]
#[inline(always)]
pub const fn uca0mctlw(&self) -> &Uca0mctlw {
&self.uca0mctlw
}
#[doc = "0x0a - USCI A0 Status Register"]
#[inline(always)]
pub const fn uca0statw(&self) -> &Uca0statw {
&self.uca0statw
}
#[doc = "0x0c - USCI A0 Receive Buffer"]
#[inline(always)]
pub const fn uca0rxbuf(&self) -> &Uca0rxbuf {
&self.uca0rxbuf
}
#[doc = "0x0e - USCI A0 Transmit Buffer"]
#[inline(always)]
pub const fn uca0txbuf(&self) -> &Uca0txbuf {
&self.uca0txbuf
}
#[doc = "0x10 - USCI A0 LIN Control"]
#[inline(always)]
pub const fn uca0abctl(&self) -> &Uca0abctl {
&self.uca0abctl
}
#[doc = "0x12 - USCI A0 IrDA Transmit Control"]
#[inline(always)]
pub const fn uca0irtctl(&self) -> &Uca0irtctl {
&self.uca0irtctl
}
#[doc = "0x13 - USCI A0 IrDA Receive Control"]
#[inline(always)]
pub const fn uca0irrctl(&self) -> &Uca0irrctl {
&self.uca0irrctl
}
#[doc = "0x1e - USCI A0 Interrupt Vector Register"]
#[inline(always)]
pub const fn uca0iv(&self) -> &Uca0iv {
&self.uca0iv
}
}
#[doc = "UCA0CTL1 (rw) register accessor: USCI A0 Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0ctl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0ctl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0ctl1`] module"]
#[doc(alias = "UCA0CTL1")]
pub type Uca0ctl1 = crate::Reg<uca0ctl1::Uca0ctl1Spec>;
#[doc = "USCI A0 Control Register 1"]
pub mod uca0ctl1 {
#[doc = "Register `UCA0CTL1` reader"]
pub type R = crate::R<Uca0ctl1Spec>;
#[doc = "Register `UCA0CTL1` writer"]
pub type W = crate::W<Uca0ctl1Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A0 Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0ctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0ctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0ctl1Spec;
impl crate::RegisterSpec for Uca0ctl1Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca0ctl1::R`](R) reader structure"]
impl crate::Readable for Uca0ctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`uca0ctl1::W`](W) writer structure"]
impl crate::Writable for Uca0ctl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0CTL1 to value 0"]
impl crate::Resettable for Uca0ctl1Spec {}
}
#[doc = "UCA0CTL0 (rw) register accessor: USCI A0 Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0ctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0ctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0ctl0`] module"]
#[doc(alias = "UCA0CTL0")]
pub type Uca0ctl0 = crate::Reg<uca0ctl0::Uca0ctl0Spec>;
#[doc = "USCI A0 Control Register 0"]
pub mod uca0ctl0 {
#[doc = "Register `UCA0CTL0` reader"]
pub type R = crate::R<Uca0ctl0Spec>;
#[doc = "Register `UCA0CTL0` writer"]
pub type W = crate::W<Uca0ctl0Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A0 Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0ctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0ctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0ctl0Spec;
impl crate::RegisterSpec for Uca0ctl0Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca0ctl0::R`](R) reader structure"]
impl crate::Readable for Uca0ctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`uca0ctl0::W`](W) writer structure"]
impl crate::Writable for Uca0ctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0CTL0 to value 0"]
impl crate::Resettable for Uca0ctl0Spec {}
}
#[doc = "UCA0BR0 (rw) register accessor: USCI A0 Baud Rate 0\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0br0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0br0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0br0`] module"]
#[doc(alias = "UCA0BR0")]
pub type Uca0br0 = crate::Reg<uca0br0::Uca0br0Spec>;
#[doc = "USCI A0 Baud Rate 0"]
pub mod uca0br0 {
#[doc = "Register `UCA0BR0` reader"]
pub type R = crate::R<Uca0br0Spec>;
#[doc = "Register `UCA0BR0` writer"]
pub type W = crate::W<Uca0br0Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A0 Baud Rate 0\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0br0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0br0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0br0Spec;
impl crate::RegisterSpec for Uca0br0Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca0br0::R`](R) reader structure"]
impl crate::Readable for Uca0br0Spec {}
#[doc = "`write(|w| ..)` method takes [`uca0br0::W`](W) writer structure"]
impl crate::Writable for Uca0br0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0BR0 to value 0"]
impl crate::Resettable for Uca0br0Spec {}
}
#[doc = "UCA0BR1 (rw) register accessor: USCI A0 Baud Rate 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0br1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0br1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0br1`] module"]
#[doc(alias = "UCA0BR1")]
pub type Uca0br1 = crate::Reg<uca0br1::Uca0br1Spec>;
#[doc = "USCI A0 Baud Rate 1"]
pub mod uca0br1 {
#[doc = "Register `UCA0BR1` reader"]
pub type R = crate::R<Uca0br1Spec>;
#[doc = "Register `UCA0BR1` writer"]
pub type W = crate::W<Uca0br1Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A0 Baud Rate 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0br1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0br1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0br1Spec;
impl crate::RegisterSpec for Uca0br1Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca0br1::R`](R) reader structure"]
impl crate::Readable for Uca0br1Spec {}
#[doc = "`write(|w| ..)` method takes [`uca0br1::W`](W) writer structure"]
impl crate::Writable for Uca0br1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0BR1 to value 0"]
impl crate::Resettable for Uca0br1Spec {}
}
#[doc = "UCA0STATW (rw) register accessor: USCI A0 Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0statw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0statw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0statw`] module"]
#[doc(alias = "UCA0STATW")]
pub type Uca0statw = crate::Reg<uca0statw::Uca0statwSpec>;
#[doc = "USCI A0 Status Register"]
pub mod uca0statw {
#[doc = "Register `UCA0STATW` reader"]
pub type R = crate::R<Uca0statwSpec>;
#[doc = "Register `UCA0STATW` writer"]
pub type W = crate::W<Uca0statwSpec>;
#[doc = "Field `UCBUSY` reader - USCI Busy Flag"]
pub type UcbusyR = crate::BitReader;
#[doc = "Field `UCBUSY` writer - USCI Busy Flag"]
pub type UcbusyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDR` reader - USCI Address received Flag"]
pub type UcaddrR = crate::BitReader;
#[doc = "Field `UCADDR` writer - USCI Address received Flag"]
pub type UcaddrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCRXERR` reader - USCI RX Error Flag"]
pub type UcrxerrR = crate::BitReader;
#[doc = "Field `UCRXERR` writer - USCI RX Error Flag"]
pub type UcrxerrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBRK` reader - USCI Break received"]
pub type UcbrkR = crate::BitReader;
#[doc = "Field `UCBRK` writer - USCI Break received"]
pub type UcbrkW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCPE` reader - USCI Parity Error Flag"]
pub type UcpeR = crate::BitReader;
#[doc = "Field `UCPE` writer - USCI Parity Error Flag"]
pub type UcpeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOE` reader - USCI Overrun Error Flag"]
pub type UcoeR = crate::BitReader;
#[doc = "Field `UCOE` writer - USCI Overrun Error Flag"]
pub type UcoeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCFE` reader - USCI Frame Error Flag"]
pub type UcfeR = crate::BitReader;
#[doc = "Field `UCFE` writer - USCI Frame Error Flag"]
pub type UcfeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCLISTEN` reader - USCI Listen mode"]
pub type UclistenR = crate::BitReader;
#[doc = "Field `UCLISTEN` writer - USCI Listen mode"]
pub type UclistenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - USCI Busy Flag"]
#[inline(always)]
pub fn ucbusy(&self) -> UcbusyR {
UcbusyR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - USCI Address received Flag"]
#[inline(always)]
pub fn ucaddr(&self) -> UcaddrR {
UcaddrR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - USCI RX Error Flag"]
#[inline(always)]
pub fn ucrxerr(&self) -> UcrxerrR {
UcrxerrR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - USCI Break received"]
#[inline(always)]
pub fn ucbrk(&self) -> UcbrkR {
UcbrkR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - USCI Parity Error Flag"]
#[inline(always)]
pub fn ucpe(&self) -> UcpeR {
UcpeR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - USCI Overrun Error Flag"]
#[inline(always)]
pub fn ucoe(&self) -> UcoeR {
UcoeR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - USCI Frame Error Flag"]
#[inline(always)]
pub fn ucfe(&self) -> UcfeR {
UcfeR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - USCI Listen mode"]
#[inline(always)]
pub fn uclisten(&self) -> UclistenR {
UclistenR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - USCI Busy Flag"]
#[inline(always)]
pub fn ucbusy(&mut self) -> UcbusyW<'_, Uca0statwSpec> {
UcbusyW::new(self, 0)
}
#[doc = "Bit 1 - USCI Address received Flag"]
#[inline(always)]
pub fn ucaddr(&mut self) -> UcaddrW<'_, Uca0statwSpec> {
UcaddrW::new(self, 1)
}
#[doc = "Bit 2 - USCI RX Error Flag"]
#[inline(always)]
pub fn ucrxerr(&mut self) -> UcrxerrW<'_, Uca0statwSpec> {
UcrxerrW::new(self, 2)
}
#[doc = "Bit 3 - USCI Break received"]
#[inline(always)]
pub fn ucbrk(&mut self) -> UcbrkW<'_, Uca0statwSpec> {
UcbrkW::new(self, 3)
}
#[doc = "Bit 4 - USCI Parity Error Flag"]
#[inline(always)]
pub fn ucpe(&mut self) -> UcpeW<'_, Uca0statwSpec> {
UcpeW::new(self, 4)
}
#[doc = "Bit 5 - USCI Overrun Error Flag"]
#[inline(always)]
pub fn ucoe(&mut self) -> UcoeW<'_, Uca0statwSpec> {
UcoeW::new(self, 5)
}
#[doc = "Bit 6 - USCI Frame Error Flag"]
#[inline(always)]
pub fn ucfe(&mut self) -> UcfeW<'_, Uca0statwSpec> {
UcfeW::new(self, 6)
}
#[doc = "Bit 7 - USCI Listen mode"]
#[inline(always)]
pub fn uclisten(&mut self) -> UclistenW<'_, Uca0statwSpec> {
UclistenW::new(self, 7)
}
}
#[doc = "USCI A0 Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0statw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0statw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0statwSpec;
impl crate::RegisterSpec for Uca0statwSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca0statw::R`](R) reader structure"]
impl crate::Readable for Uca0statwSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0statw::W`](W) writer structure"]
impl crate::Writable for Uca0statwSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets UCA0STATW to value 0"]
impl crate::Resettable for Uca0statwSpec {}
}
#[doc = "UCA0ABCTL (rw) register accessor: USCI A0 LIN Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0abctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0abctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0abctl`] module"]
#[doc(alias = "UCA0ABCTL")]
pub type Uca0abctl = crate::Reg<uca0abctl::Uca0abctlSpec>;
#[doc = "USCI A0 LIN Control"]
pub mod uca0abctl {
#[doc = "Register `UCA0ABCTL` reader"]
pub type R = crate::R<Uca0abctlSpec>;
#[doc = "Register `UCA0ABCTL` writer"]
pub type W = crate::W<Uca0abctlSpec>;
#[doc = "Field `UCABDEN` reader - Auto Baud Rate detect enable"]
pub type UcabdenR = crate::BitReader;
#[doc = "Field `UCABDEN` writer - Auto Baud Rate detect enable"]
pub type UcabdenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBTOE` reader - Break Timeout error"]
pub type UcbtoeR = crate::BitReader;
#[doc = "Field `UCBTOE` writer - Break Timeout error"]
pub type UcbtoeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCSTOE` reader - Sync-Field Timeout error"]
pub type UcstoeR = crate::BitReader;
#[doc = "Field `UCSTOE` writer - Sync-Field Timeout error"]
pub type UcstoeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCDELIM0` reader - Break Sync Delimiter 0"]
pub type Ucdelim0R = crate::BitReader;
#[doc = "Field `UCDELIM0` writer - Break Sync Delimiter 0"]
pub type Ucdelim0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCDELIM1` reader - Break Sync Delimiter 1"]
pub type Ucdelim1R = crate::BitReader;
#[doc = "Field `UCDELIM1` writer - Break Sync Delimiter 1"]
pub type Ucdelim1W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Auto Baud Rate detect enable"]
#[inline(always)]
pub fn ucabden(&self) -> UcabdenR {
UcabdenR::new((self.bits & 1) != 0)
}
#[doc = "Bit 2 - Break Timeout error"]
#[inline(always)]
pub fn ucbtoe(&self) -> UcbtoeR {
UcbtoeR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Sync-Field Timeout error"]
#[inline(always)]
pub fn ucstoe(&self) -> UcstoeR {
UcstoeR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Break Sync Delimiter 0"]
#[inline(always)]
pub fn ucdelim0(&self) -> Ucdelim0R {
Ucdelim0R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Break Sync Delimiter 1"]
#[inline(always)]
pub fn ucdelim1(&self) -> Ucdelim1R {
Ucdelim1R::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Auto Baud Rate detect enable"]
#[inline(always)]
pub fn ucabden(&mut self) -> UcabdenW<'_, Uca0abctlSpec> {
UcabdenW::new(self, 0)
}
#[doc = "Bit 2 - Break Timeout error"]
#[inline(always)]
pub fn ucbtoe(&mut self) -> UcbtoeW<'_, Uca0abctlSpec> {
UcbtoeW::new(self, 2)
}
#[doc = "Bit 3 - Sync-Field Timeout error"]
#[inline(always)]
pub fn ucstoe(&mut self) -> UcstoeW<'_, Uca0abctlSpec> {
UcstoeW::new(self, 3)
}
#[doc = "Bit 4 - Break Sync Delimiter 0"]
#[inline(always)]
pub fn ucdelim0(&mut self) -> Ucdelim0W<'_, Uca0abctlSpec> {
Ucdelim0W::new(self, 4)
}
#[doc = "Bit 5 - Break Sync Delimiter 1"]
#[inline(always)]
pub fn ucdelim1(&mut self) -> Ucdelim1W<'_, Uca0abctlSpec> {
Ucdelim1W::new(self, 5)
}
}
#[doc = "USCI A0 LIN Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0abctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0abctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0abctlSpec;
impl crate::RegisterSpec for Uca0abctlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca0abctl::R`](R) reader structure"]
impl crate::Readable for Uca0abctlSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0abctl::W`](W) writer structure"]
impl crate::Writable for Uca0abctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0ABCTL to value 0"]
impl crate::Resettable for Uca0abctlSpec {}
}
#[doc = "UCA0IRTCTL (rw) register accessor: USCI A0 IrDA Transmit Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0irtctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0irtctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0irtctl`] module"]
#[doc(alias = "UCA0IRTCTL")]
pub type Uca0irtctl = crate::Reg<uca0irtctl::Uca0irtctlSpec>;
#[doc = "USCI A0 IrDA Transmit Control"]
pub mod uca0irtctl {
#[doc = "Register `UCA0IRTCTL` reader"]
pub type R = crate::R<Uca0irtctlSpec>;
#[doc = "Register `UCA0IRTCTL` writer"]
pub type W = crate::W<Uca0irtctlSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A0 IrDA Transmit Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0irtctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0irtctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0irtctlSpec;
impl crate::RegisterSpec for Uca0irtctlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca0irtctl::R`](R) reader structure"]
impl crate::Readable for Uca0irtctlSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0irtctl::W`](W) writer structure"]
impl crate::Writable for Uca0irtctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0IRTCTL to value 0"]
impl crate::Resettable for Uca0irtctlSpec {}
}
#[doc = "UCA0IRRCTL (rw) register accessor: USCI A0 IrDA Receive Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0irrctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0irrctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0irrctl`] module"]
#[doc(alias = "UCA0IRRCTL")]
pub type Uca0irrctl = crate::Reg<uca0irrctl::Uca0irrctlSpec>;
#[doc = "USCI A0 IrDA Receive Control"]
pub mod uca0irrctl {
#[doc = "Register `UCA0IRRCTL` reader"]
pub type R = crate::R<Uca0irrctlSpec>;
#[doc = "Register `UCA0IRRCTL` writer"]
pub type W = crate::W<Uca0irrctlSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A0 IrDA Receive Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0irrctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0irrctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0irrctlSpec;
impl crate::RegisterSpec for Uca0irrctlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca0irrctl::R`](R) reader structure"]
impl crate::Readable for Uca0irrctlSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0irrctl::W`](W) writer structure"]
impl crate::Writable for Uca0irrctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0IRRCTL to value 0"]
impl crate::Resettable for Uca0irrctlSpec {}
}
#[doc = "UCA0CTLW1 (rw) register accessor: USCI A0 Control Word Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0ctlw1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0ctlw1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0ctlw1`] module"]
#[doc(alias = "UCA0CTLW1")]
pub type Uca0ctlw1 = crate::Reg<uca0ctlw1::Uca0ctlw1Spec>;
#[doc = "USCI A0 Control Word Register 1"]
pub mod uca0ctlw1 {
#[doc = "Register `UCA0CTLW1` reader"]
pub type R = crate::R<Uca0ctlw1Spec>;
#[doc = "Register `UCA0CTLW1` writer"]
pub type W = crate::W<Uca0ctlw1Spec>;
#[doc = "USCI Deglitch Time Bit 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ucglit {
#[doc = "0: USCI Deglitch time: 0"]
Ucglit0 = 0,
#[doc = "1: USCI Deglitch time: 1"]
Ucglit1 = 1,
#[doc = "2: USCI Deglitch time: 2"]
Ucglit2 = 2,
#[doc = "3: USCI Deglitch time: 3"]
Ucglit3 = 3,
}
impl From<Ucglit> for u8 {
#[inline(always)]
fn from(variant: Ucglit) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ucglit {
type Ux = u8;
}
impl crate::IsEnum for Ucglit {}
#[doc = "Field `UCGLIT` reader - USCI Deglitch Time Bit 1"]
pub type UcglitR = crate::FieldReader<Ucglit>;
impl UcglitR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ucglit {
match self.bits {
0 => Ucglit::Ucglit0,
1 => Ucglit::Ucglit1,
2 => Ucglit::Ucglit2,
3 => Ucglit::Ucglit3,
_ => unreachable!(),
}
}
#[doc = "USCI Deglitch time: 0"]
#[inline(always)]
pub fn is_ucglit_0(&self) -> bool {
*self == Ucglit::Ucglit0
}
#[doc = "USCI Deglitch time: 1"]
#[inline(always)]
pub fn is_ucglit_1(&self) -> bool {
*self == Ucglit::Ucglit1
}
#[doc = "USCI Deglitch time: 2"]
#[inline(always)]
pub fn is_ucglit_2(&self) -> bool {
*self == Ucglit::Ucglit2
}
#[doc = "USCI Deglitch time: 3"]
#[inline(always)]
pub fn is_ucglit_3(&self) -> bool {
*self == Ucglit::Ucglit3
}
}
#[doc = "Field `UCGLIT` writer - USCI Deglitch Time Bit 1"]
pub type UcglitW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ucglit, crate::Safe>;
impl<'a, REG> UcglitW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "USCI Deglitch time: 0"]
#[inline(always)]
pub fn ucglit_0(self) -> &'a mut crate::W<REG> {
self.variant(Ucglit::Ucglit0)
}
#[doc = "USCI Deglitch time: 1"]
#[inline(always)]
pub fn ucglit_1(self) -> &'a mut crate::W<REG> {
self.variant(Ucglit::Ucglit1)
}
#[doc = "USCI Deglitch time: 2"]
#[inline(always)]
pub fn ucglit_2(self) -> &'a mut crate::W<REG> {
self.variant(Ucglit::Ucglit2)
}
#[doc = "USCI Deglitch time: 3"]
#[inline(always)]
pub fn ucglit_3(self) -> &'a mut crate::W<REG> {
self.variant(Ucglit::Ucglit3)
}
}
impl R {
#[doc = "Bits 0:1 - USCI Deglitch Time Bit 1"]
#[inline(always)]
pub fn ucglit(&self) -> UcglitR {
UcglitR::new((self.bits & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - USCI Deglitch Time Bit 1"]
#[inline(always)]
pub fn ucglit(&mut self) -> UcglitW<'_, Uca0ctlw1Spec> {
UcglitW::new(self, 0)
}
}
#[doc = "USCI A0 Control Word Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0ctlw1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0ctlw1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0ctlw1Spec;
impl crate::RegisterSpec for Uca0ctlw1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`uca0ctlw1::R`](R) reader structure"]
impl crate::Readable for Uca0ctlw1Spec {}
#[doc = "`write(|w| ..)` method takes [`uca0ctlw1::W`](W) writer structure"]
impl crate::Writable for Uca0ctlw1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0CTLW1 to value 0"]
impl crate::Resettable for Uca0ctlw1Spec {}
}
#[doc = "UCA0MCTLW (rw) register accessor: USCI A0 Modulation Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0mctlw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0mctlw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0mctlw`] module"]
#[doc(alias = "UCA0MCTLW")]
pub type Uca0mctlw = crate::Reg<uca0mctlw::Uca0mctlwSpec>;
#[doc = "USCI A0 Modulation Control"]
pub mod uca0mctlw {
#[doc = "Register `UCA0MCTLW` reader"]
pub type R = crate::R<Uca0mctlwSpec>;
#[doc = "Register `UCA0MCTLW` writer"]
pub type W = crate::W<Uca0mctlwSpec>;
#[doc = "Field `UCOS16` reader - USCI 16-times Oversampling enable"]
pub type Ucos16R = crate::BitReader;
#[doc = "Field `UCOS16` writer - USCI 16-times Oversampling enable"]
pub type Ucos16W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "USCI First Stage Modulation Select 3\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ucbrf {
#[doc = "0: USCI First Stage Modulation: 0"]
Ucbrf0 = 0,
#[doc = "1: USCI First Stage Modulation: 1"]
Ucbrf1 = 1,
#[doc = "2: USCI First Stage Modulation: 2"]
Ucbrf2 = 2,
#[doc = "3: USCI First Stage Modulation: 3"]
Ucbrf3 = 3,
#[doc = "4: USCI First Stage Modulation: 4"]
Ucbrf4 = 4,
#[doc = "5: USCI First Stage Modulation: 5"]
Ucbrf5 = 5,
#[doc = "6: USCI First Stage Modulation: 6"]
Ucbrf6 = 6,
#[doc = "7: USCI First Stage Modulation: 7"]
Ucbrf7 = 7,
#[doc = "8: USCI First Stage Modulation: 8"]
Ucbrf8 = 8,
#[doc = "9: USCI First Stage Modulation: 9"]
Ucbrf9 = 9,
#[doc = "10: USCI First Stage Modulation: A"]
Ucbrf10 = 10,
#[doc = "11: USCI First Stage Modulation: B"]
Ucbrf11 = 11,
#[doc = "12: USCI First Stage Modulation: C"]
Ucbrf12 = 12,
#[doc = "13: USCI First Stage Modulation: D"]
Ucbrf13 = 13,
#[doc = "14: USCI First Stage Modulation: E"]
Ucbrf14 = 14,
#[doc = "15: USCI First Stage Modulation: F"]
Ucbrf15 = 15,
}
impl From<Ucbrf> for u8 {
#[inline(always)]
fn from(variant: Ucbrf) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ucbrf {
type Ux = u8;
}
impl crate::IsEnum for Ucbrf {}
#[doc = "Field `UCBRF` reader - USCI First Stage Modulation Select 3"]
pub type UcbrfR = crate::FieldReader<Ucbrf>;
impl UcbrfR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ucbrf {
match self.bits {
0 => Ucbrf::Ucbrf0,
1 => Ucbrf::Ucbrf1,
2 => Ucbrf::Ucbrf2,
3 => Ucbrf::Ucbrf3,
4 => Ucbrf::Ucbrf4,
5 => Ucbrf::Ucbrf5,
6 => Ucbrf::Ucbrf6,
7 => Ucbrf::Ucbrf7,
8 => Ucbrf::Ucbrf8,
9 => Ucbrf::Ucbrf9,
10 => Ucbrf::Ucbrf10,
11 => Ucbrf::Ucbrf11,
12 => Ucbrf::Ucbrf12,
13 => Ucbrf::Ucbrf13,
14 => Ucbrf::Ucbrf14,
15 => Ucbrf::Ucbrf15,
_ => unreachable!(),
}
}
#[doc = "USCI First Stage Modulation: 0"]
#[inline(always)]
pub fn is_ucbrf_0(&self) -> bool {
*self == Ucbrf::Ucbrf0
}
#[doc = "USCI First Stage Modulation: 1"]
#[inline(always)]
pub fn is_ucbrf_1(&self) -> bool {
*self == Ucbrf::Ucbrf1
}
#[doc = "USCI First Stage Modulation: 2"]
#[inline(always)]
pub fn is_ucbrf_2(&self) -> bool {
*self == Ucbrf::Ucbrf2
}
#[doc = "USCI First Stage Modulation: 3"]
#[inline(always)]
pub fn is_ucbrf_3(&self) -> bool {
*self == Ucbrf::Ucbrf3
}
#[doc = "USCI First Stage Modulation: 4"]
#[inline(always)]
pub fn is_ucbrf_4(&self) -> bool {
*self == Ucbrf::Ucbrf4
}
#[doc = "USCI First Stage Modulation: 5"]
#[inline(always)]
pub fn is_ucbrf_5(&self) -> bool {
*self == Ucbrf::Ucbrf5
}
#[doc = "USCI First Stage Modulation: 6"]
#[inline(always)]
pub fn is_ucbrf_6(&self) -> bool {
*self == Ucbrf::Ucbrf6
}
#[doc = "USCI First Stage Modulation: 7"]
#[inline(always)]
pub fn is_ucbrf_7(&self) -> bool {
*self == Ucbrf::Ucbrf7
}
#[doc = "USCI First Stage Modulation: 8"]
#[inline(always)]
pub fn is_ucbrf_8(&self) -> bool {
*self == Ucbrf::Ucbrf8
}
#[doc = "USCI First Stage Modulation: 9"]
#[inline(always)]
pub fn is_ucbrf_9(&self) -> bool {
*self == Ucbrf::Ucbrf9
}
#[doc = "USCI First Stage Modulation: A"]
#[inline(always)]
pub fn is_ucbrf_10(&self) -> bool {
*self == Ucbrf::Ucbrf10
}
#[doc = "USCI First Stage Modulation: B"]
#[inline(always)]
pub fn is_ucbrf_11(&self) -> bool {
*self == Ucbrf::Ucbrf11
}
#[doc = "USCI First Stage Modulation: C"]
#[inline(always)]
pub fn is_ucbrf_12(&self) -> bool {
*self == Ucbrf::Ucbrf12
}
#[doc = "USCI First Stage Modulation: D"]
#[inline(always)]
pub fn is_ucbrf_13(&self) -> bool {
*self == Ucbrf::Ucbrf13
}
#[doc = "USCI First Stage Modulation: E"]
#[inline(always)]
pub fn is_ucbrf_14(&self) -> bool {
*self == Ucbrf::Ucbrf14
}
#[doc = "USCI First Stage Modulation: F"]
#[inline(always)]
pub fn is_ucbrf_15(&self) -> bool {
*self == Ucbrf::Ucbrf15
}
}
#[doc = "Field `UCBRF` writer - USCI First Stage Modulation Select 3"]
pub type UcbrfW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ucbrf, crate::Safe>;
impl<'a, REG> UcbrfW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "USCI First Stage Modulation: 0"]
#[inline(always)]
pub fn ucbrf_0(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf0)
}
#[doc = "USCI First Stage Modulation: 1"]
#[inline(always)]
pub fn ucbrf_1(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf1)
}
#[doc = "USCI First Stage Modulation: 2"]
#[inline(always)]
pub fn ucbrf_2(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf2)
}
#[doc = "USCI First Stage Modulation: 3"]
#[inline(always)]
pub fn ucbrf_3(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf3)
}
#[doc = "USCI First Stage Modulation: 4"]
#[inline(always)]
pub fn ucbrf_4(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf4)
}
#[doc = "USCI First Stage Modulation: 5"]
#[inline(always)]
pub fn ucbrf_5(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf5)
}
#[doc = "USCI First Stage Modulation: 6"]
#[inline(always)]
pub fn ucbrf_6(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf6)
}
#[doc = "USCI First Stage Modulation: 7"]
#[inline(always)]
pub fn ucbrf_7(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf7)
}
#[doc = "USCI First Stage Modulation: 8"]
#[inline(always)]
pub fn ucbrf_8(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf8)
}
#[doc = "USCI First Stage Modulation: 9"]
#[inline(always)]
pub fn ucbrf_9(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf9)
}
#[doc = "USCI First Stage Modulation: A"]
#[inline(always)]
pub fn ucbrf_10(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf10)
}
#[doc = "USCI First Stage Modulation: B"]
#[inline(always)]
pub fn ucbrf_11(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf11)
}
#[doc = "USCI First Stage Modulation: C"]
#[inline(always)]
pub fn ucbrf_12(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf12)
}
#[doc = "USCI First Stage Modulation: D"]
#[inline(always)]
pub fn ucbrf_13(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf13)
}
#[doc = "USCI First Stage Modulation: E"]
#[inline(always)]
pub fn ucbrf_14(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf14)
}
#[doc = "USCI First Stage Modulation: F"]
#[inline(always)]
pub fn ucbrf_15(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf15)
}
}
#[doc = "Field `UCBRS0` reader - USCI Second Stage Modulation Select 0"]
pub type Ucbrs0R = crate::BitReader;
#[doc = "Field `UCBRS0` writer - USCI Second Stage Modulation Select 0"]
pub type Ucbrs0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBRS1` reader - USCI Second Stage Modulation Select 1"]
pub type Ucbrs1R = crate::BitReader;
#[doc = "Field `UCBRS1` writer - USCI Second Stage Modulation Select 1"]
pub type Ucbrs1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBRS2` reader - USCI Second Stage Modulation Select 2"]
pub type Ucbrs2R = crate::BitReader;
#[doc = "Field `UCBRS2` writer - USCI Second Stage Modulation Select 2"]
pub type Ucbrs2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBRS3` reader - USCI Second Stage Modulation Select 3"]
pub type Ucbrs3R = crate::BitReader;
#[doc = "Field `UCBRS3` writer - USCI Second Stage Modulation Select 3"]
pub type Ucbrs3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBRS4` reader - USCI Second Stage Modulation Select 4"]
pub type Ucbrs4R = crate::BitReader;
#[doc = "Field `UCBRS4` writer - USCI Second Stage Modulation Select 4"]
pub type Ucbrs4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBRS5` reader - USCI Second Stage Modulation Select 5"]
pub type Ucbrs5R = crate::BitReader;
#[doc = "Field `UCBRS5` writer - USCI Second Stage Modulation Select 5"]
pub type Ucbrs5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBRS6` reader - USCI Second Stage Modulation Select 6"]
pub type Ucbrs6R = crate::BitReader;
#[doc = "Field `UCBRS6` writer - USCI Second Stage Modulation Select 6"]
pub type Ucbrs6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBRS7` reader - USCI Second Stage Modulation Select 7"]
pub type Ucbrs7R = crate::BitReader;
#[doc = "Field `UCBRS7` writer - USCI Second Stage Modulation Select 7"]
pub type Ucbrs7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - USCI 16-times Oversampling enable"]
#[inline(always)]
pub fn ucos16(&self) -> Ucos16R {
Ucos16R::new((self.bits & 1) != 0)
}
#[doc = "Bits 4:7 - USCI First Stage Modulation Select 3"]
#[inline(always)]
pub fn ucbrf(&self) -> UcbrfR {
UcbrfR::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bit 8 - USCI Second Stage Modulation Select 0"]
#[inline(always)]
pub fn ucbrs0(&self) -> Ucbrs0R {
Ucbrs0R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - USCI Second Stage Modulation Select 1"]
#[inline(always)]
pub fn ucbrs1(&self) -> Ucbrs1R {
Ucbrs1R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - USCI Second Stage Modulation Select 2"]
#[inline(always)]
pub fn ucbrs2(&self) -> Ucbrs2R {
Ucbrs2R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - USCI Second Stage Modulation Select 3"]
#[inline(always)]
pub fn ucbrs3(&self) -> Ucbrs3R {
Ucbrs3R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - USCI Second Stage Modulation Select 4"]
#[inline(always)]
pub fn ucbrs4(&self) -> Ucbrs4R {
Ucbrs4R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - USCI Second Stage Modulation Select 5"]
#[inline(always)]
pub fn ucbrs5(&self) -> Ucbrs5R {
Ucbrs5R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - USCI Second Stage Modulation Select 6"]
#[inline(always)]
pub fn ucbrs6(&self) -> Ucbrs6R {
Ucbrs6R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - USCI Second Stage Modulation Select 7"]
#[inline(always)]
pub fn ucbrs7(&self) -> Ucbrs7R {
Ucbrs7R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - USCI 16-times Oversampling enable"]
#[inline(always)]
pub fn ucos16(&mut self) -> Ucos16W<'_, Uca0mctlwSpec> {
Ucos16W::new(self, 0)
}
#[doc = "Bits 4:7 - USCI First Stage Modulation Select 3"]
#[inline(always)]
pub fn ucbrf(&mut self) -> UcbrfW<'_, Uca0mctlwSpec> {
UcbrfW::new(self, 4)
}
#[doc = "Bit 8 - USCI Second Stage Modulation Select 0"]
#[inline(always)]
pub fn ucbrs0(&mut self) -> Ucbrs0W<'_, Uca0mctlwSpec> {
Ucbrs0W::new(self, 8)
}
#[doc = "Bit 9 - USCI Second Stage Modulation Select 1"]
#[inline(always)]
pub fn ucbrs1(&mut self) -> Ucbrs1W<'_, Uca0mctlwSpec> {
Ucbrs1W::new(self, 9)
}
#[doc = "Bit 10 - USCI Second Stage Modulation Select 2"]
#[inline(always)]
pub fn ucbrs2(&mut self) -> Ucbrs2W<'_, Uca0mctlwSpec> {
Ucbrs2W::new(self, 10)
}
#[doc = "Bit 11 - USCI Second Stage Modulation Select 3"]
#[inline(always)]
pub fn ucbrs3(&mut self) -> Ucbrs3W<'_, Uca0mctlwSpec> {
Ucbrs3W::new(self, 11)
}
#[doc = "Bit 12 - USCI Second Stage Modulation Select 4"]
#[inline(always)]
pub fn ucbrs4(&mut self) -> Ucbrs4W<'_, Uca0mctlwSpec> {
Ucbrs4W::new(self, 12)
}
#[doc = "Bit 13 - USCI Second Stage Modulation Select 5"]
#[inline(always)]
pub fn ucbrs5(&mut self) -> Ucbrs5W<'_, Uca0mctlwSpec> {
Ucbrs5W::new(self, 13)
}
#[doc = "Bit 14 - USCI Second Stage Modulation Select 6"]
#[inline(always)]
pub fn ucbrs6(&mut self) -> Ucbrs6W<'_, Uca0mctlwSpec> {
Ucbrs6W::new(self, 14)
}
#[doc = "Bit 15 - USCI Second Stage Modulation Select 7"]
#[inline(always)]
pub fn ucbrs7(&mut self) -> Ucbrs7W<'_, Uca0mctlwSpec> {
Ucbrs7W::new(self, 15)
}
}
#[doc = "USCI A0 Modulation Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0mctlw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0mctlw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0mctlwSpec;
impl crate::RegisterSpec for Uca0mctlwSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`uca0mctlw::R`](R) reader structure"]
impl crate::Readable for Uca0mctlwSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0mctlw::W`](W) writer structure"]
impl crate::Writable for Uca0mctlwSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0MCTLW to value 0"]
impl crate::Resettable for Uca0mctlwSpec {}
}
#[doc = "UCA0RXBUF (rw) register accessor: USCI A0 Receive Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0rxbuf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0rxbuf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0rxbuf`] module"]
#[doc(alias = "UCA0RXBUF")]
pub type Uca0rxbuf = crate::Reg<uca0rxbuf::Uca0rxbufSpec>;
#[doc = "USCI A0 Receive Buffer"]
pub mod uca0rxbuf {
#[doc = "Register `UCA0RXBUF` reader"]
pub type R = crate::R<Uca0rxbufSpec>;
#[doc = "Register `UCA0RXBUF` writer"]
pub type W = crate::W<Uca0rxbufSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A0 Receive Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0rxbuf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0rxbuf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0rxbufSpec;
impl crate::RegisterSpec for Uca0rxbufSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`uca0rxbuf::R`](R) reader structure"]
impl crate::Readable for Uca0rxbufSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0rxbuf::W`](W) writer structure"]
impl crate::Writable for Uca0rxbufSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0RXBUF to value 0"]
impl crate::Resettable for Uca0rxbufSpec {}
}
#[doc = "UCA0TXBUF (rw) register accessor: USCI A0 Transmit Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0txbuf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0txbuf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0txbuf`] module"]
#[doc(alias = "UCA0TXBUF")]
pub type Uca0txbuf = crate::Reg<uca0txbuf::Uca0txbufSpec>;
#[doc = "USCI A0 Transmit Buffer"]
pub mod uca0txbuf {
#[doc = "Register `UCA0TXBUF` reader"]
pub type R = crate::R<Uca0txbufSpec>;
#[doc = "Register `UCA0TXBUF` writer"]
pub type W = crate::W<Uca0txbufSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A0 Transmit Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0txbuf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0txbuf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0txbufSpec;
impl crate::RegisterSpec for Uca0txbufSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`uca0txbuf::R`](R) reader structure"]
impl crate::Readable for Uca0txbufSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0txbuf::W`](W) writer structure"]
impl crate::Writable for Uca0txbufSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0TXBUF to value 0"]
impl crate::Resettable for Uca0txbufSpec {}
}
#[doc = "UCA0IV (rw) register accessor: USCI A0 Interrupt Vector Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0iv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0iv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0iv`] module"]
#[doc(alias = "UCA0IV")]
pub type Uca0iv = crate::Reg<uca0iv::Uca0ivSpec>;
#[doc = "USCI A0 Interrupt Vector Register"]
pub mod uca0iv {
#[doc = "Register `UCA0IV` reader"]
pub type R = crate::R<Uca0ivSpec>;
#[doc = "Register `UCA0IV` writer"]
pub type W = crate::W<Uca0ivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A0 Interrupt Vector Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0iv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0iv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0ivSpec;
impl crate::RegisterSpec for Uca0ivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`uca0iv::R`](R) reader structure"]
impl crate::Readable for Uca0ivSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0iv::W`](W) writer structure"]
impl crate::Writable for Uca0ivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0IV to value 0"]
impl crate::Resettable for Uca0ivSpec {}
}
}
#[doc = "USCI_A0 SPI Mode"]
pub type UsciA0SpiMode = crate::Periph<usci_a0_spi_mode::RegisterBlock, 0x05c0>;
impl core::fmt::Debug for UsciA0SpiMode {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UsciA0SpiMode").finish()
}
}
#[doc = "USCI_A0 SPI Mode"]
pub mod usci_a0_spi_mode {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
uca0ctl1_spi: Uca0ctl1Spi,
uca0ctl0_spi: Uca0ctl0Spi,
_reserved2: [u8; 0x04],
uca0br0_spi: Uca0br0Spi,
uca0br1_spi: Uca0br1Spi,
_reserved4: [u8; 0x02],
uca0statw_spi: Uca0statwSpi,
_reserved5: [u8; 0x01],
uca0rxbuf_spi: Uca0rxbufSpi,
uca0txbuf_spi: Uca0txbufSpi,
_reserved7: [u8; 0x0a],
uca0ie_spi: Uca0ieSpi,
_reserved8: [u8; 0x01],
uca0ifg_spi: Uca0ifgSpi,
_reserved9: [u8; 0x01],
uca0iv_spi: Uca0ivSpi,
}
impl RegisterBlock {
#[doc = "0x00 - USCI A0 Control Register 1"]
#[inline(always)]
pub const fn uca0ctl1_spi(&self) -> &Uca0ctl1Spi {
&self.uca0ctl1_spi
}
#[doc = "0x01 - USCI A0 Control Register 0"]
#[inline(always)]
pub const fn uca0ctl0_spi(&self) -> &Uca0ctl0Spi {
&self.uca0ctl0_spi
}
#[doc = "0x06 - USCI A0 Baud Rate 0"]
#[inline(always)]
pub const fn uca0br0_spi(&self) -> &Uca0br0Spi {
&self.uca0br0_spi
}
#[doc = "0x07 - USCI A0 Baud Rate 1"]
#[inline(always)]
pub const fn uca0br1_spi(&self) -> &Uca0br1Spi {
&self.uca0br1_spi
}
#[doc = "0x0a - USCI A0 Status Register"]
#[inline(always)]
pub const fn uca0statw_spi(&self) -> &Uca0statwSpi {
&self.uca0statw_spi
}
#[doc = "0x0c - USCI A0 Receive Buffer"]
#[inline(always)]
pub const fn uca0rxbuf_spi(&self) -> &Uca0rxbufSpi {
&self.uca0rxbuf_spi
}
#[doc = "0x0e - USCI A0 Transmit Buffer"]
#[inline(always)]
pub const fn uca0txbuf_spi(&self) -> &Uca0txbufSpi {
&self.uca0txbuf_spi
}
#[doc = "0x1a - USCI A0 Interrupt Enable Register"]
#[inline(always)]
pub const fn uca0ie_spi(&self) -> &Uca0ieSpi {
&self.uca0ie_spi
}
#[doc = "0x1c - USCI A0 Interrupt Flags Register"]
#[inline(always)]
pub const fn uca0ifg_spi(&self) -> &Uca0ifgSpi {
&self.uca0ifg_spi
}
#[doc = "0x1e - USCI A0 Interrupt Vector Register"]
#[inline(always)]
pub const fn uca0iv_spi(&self) -> &Uca0ivSpi {
&self.uca0iv_spi
}
}
#[doc = "UCA0CTL1_SPI (rw) register accessor: USCI A0 Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0ctl1_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0ctl1_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0ctl1_spi`] module"]
#[doc(alias = "UCA0CTL1_SPI")]
pub type Uca0ctl1Spi = crate::Reg<uca0ctl1_spi::Uca0ctl1SpiSpec>;
#[doc = "USCI A0 Control Register 1"]
pub mod uca0ctl1_spi {
#[doc = "Register `UCA0CTL1_SPI` reader"]
pub type R = crate::R<Uca0ctl1SpiSpec>;
#[doc = "Register `UCA0CTL1_SPI` writer"]
pub type W = crate::W<Uca0ctl1SpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A0 Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0ctl1_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0ctl1_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0ctl1SpiSpec;
impl crate::RegisterSpec for Uca0ctl1SpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca0ctl1_spi::R`](R) reader structure"]
impl crate::Readable for Uca0ctl1SpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0ctl1_spi::W`](W) writer structure"]
impl crate::Writable for Uca0ctl1SpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0CTL1_SPI to value 0"]
impl crate::Resettable for Uca0ctl1SpiSpec {}
}
#[doc = "UCA0CTL0_SPI (rw) register accessor: USCI A0 Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0ctl0_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0ctl0_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0ctl0_spi`] module"]
#[doc(alias = "UCA0CTL0_SPI")]
pub type Uca0ctl0Spi = crate::Reg<uca0ctl0_spi::Uca0ctl0SpiSpec>;
#[doc = "USCI A0 Control Register 0"]
pub mod uca0ctl0_spi {
#[doc = "Register `UCA0CTL0_SPI` reader"]
pub type R = crate::R<Uca0ctl0SpiSpec>;
#[doc = "Register `UCA0CTL0_SPI` writer"]
pub type W = crate::W<Uca0ctl0SpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A0 Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0ctl0_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0ctl0_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0ctl0SpiSpec;
impl crate::RegisterSpec for Uca0ctl0SpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca0ctl0_spi::R`](R) reader structure"]
impl crate::Readable for Uca0ctl0SpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0ctl0_spi::W`](W) writer structure"]
impl crate::Writable for Uca0ctl0SpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0CTL0_SPI to value 0"]
impl crate::Resettable for Uca0ctl0SpiSpec {}
}
#[doc = "UCA0BR0_SPI (rw) register accessor: USCI A0 Baud Rate 0\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0br0_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0br0_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0br0_spi`] module"]
#[doc(alias = "UCA0BR0_SPI")]
pub type Uca0br0Spi = crate::Reg<uca0br0_spi::Uca0br0SpiSpec>;
#[doc = "USCI A0 Baud Rate 0"]
pub mod uca0br0_spi {
#[doc = "Register `UCA0BR0_SPI` reader"]
pub type R = crate::R<Uca0br0SpiSpec>;
#[doc = "Register `UCA0BR0_SPI` writer"]
pub type W = crate::W<Uca0br0SpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A0 Baud Rate 0\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0br0_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0br0_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0br0SpiSpec;
impl crate::RegisterSpec for Uca0br0SpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca0br0_spi::R`](R) reader structure"]
impl crate::Readable for Uca0br0SpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0br0_spi::W`](W) writer structure"]
impl crate::Writable for Uca0br0SpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0BR0_SPI to value 0"]
impl crate::Resettable for Uca0br0SpiSpec {}
}
#[doc = "UCA0BR1_SPI (rw) register accessor: USCI A0 Baud Rate 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0br1_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0br1_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0br1_spi`] module"]
#[doc(alias = "UCA0BR1_SPI")]
pub type Uca0br1Spi = crate::Reg<uca0br1_spi::Uca0br1SpiSpec>;
#[doc = "USCI A0 Baud Rate 1"]
pub mod uca0br1_spi {
#[doc = "Register `UCA0BR1_SPI` reader"]
pub type R = crate::R<Uca0br1SpiSpec>;
#[doc = "Register `UCA0BR1_SPI` writer"]
pub type W = crate::W<Uca0br1SpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A0 Baud Rate 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0br1_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0br1_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0br1SpiSpec;
impl crate::RegisterSpec for Uca0br1SpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca0br1_spi::R`](R) reader structure"]
impl crate::Readable for Uca0br1SpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0br1_spi::W`](W) writer structure"]
impl crate::Writable for Uca0br1SpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0BR1_SPI to value 0"]
impl crate::Resettable for Uca0br1SpiSpec {}
}
#[doc = "UCA0STATW_SPI (rw) register accessor: USCI A0 Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0statw_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0statw_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0statw_spi`] module"]
#[doc(alias = "UCA0STATW_SPI")]
pub type Uca0statwSpi = crate::Reg<uca0statw_spi::Uca0statwSpiSpec>;
#[doc = "USCI A0 Status Register"]
pub mod uca0statw_spi {
#[doc = "Register `UCA0STATW_SPI` reader"]
pub type R = crate::R<Uca0statwSpiSpec>;
#[doc = "Register `UCA0STATW_SPI` writer"]
pub type W = crate::W<Uca0statwSpiSpec>;
#[doc = "Field `UCBUSY` reader - USCI Busy Flag"]
pub type UcbusyR = crate::BitReader;
#[doc = "Field `UCBUSY` writer - USCI Busy Flag"]
pub type UcbusyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOE` reader - USCI Overrun Error Flag"]
pub type UcoeR = crate::BitReader;
#[doc = "Field `UCOE` writer - USCI Overrun Error Flag"]
pub type UcoeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCFE` reader - USCI Frame Error Flag"]
pub type UcfeR = crate::BitReader;
#[doc = "Field `UCFE` writer - USCI Frame Error Flag"]
pub type UcfeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCLISTEN` reader - USCI Listen mode"]
pub type UclistenR = crate::BitReader;
#[doc = "Field `UCLISTEN` writer - USCI Listen mode"]
pub type UclistenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - USCI Busy Flag"]
#[inline(always)]
pub fn ucbusy(&self) -> UcbusyR {
UcbusyR::new((self.bits & 1) != 0)
}
#[doc = "Bit 5 - USCI Overrun Error Flag"]
#[inline(always)]
pub fn ucoe(&self) -> UcoeR {
UcoeR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - USCI Frame Error Flag"]
#[inline(always)]
pub fn ucfe(&self) -> UcfeR {
UcfeR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - USCI Listen mode"]
#[inline(always)]
pub fn uclisten(&self) -> UclistenR {
UclistenR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - USCI Busy Flag"]
#[inline(always)]
pub fn ucbusy(&mut self) -> UcbusyW<'_, Uca0statwSpiSpec> {
UcbusyW::new(self, 0)
}
#[doc = "Bit 5 - USCI Overrun Error Flag"]
#[inline(always)]
pub fn ucoe(&mut self) -> UcoeW<'_, Uca0statwSpiSpec> {
UcoeW::new(self, 5)
}
#[doc = "Bit 6 - USCI Frame Error Flag"]
#[inline(always)]
pub fn ucfe(&mut self) -> UcfeW<'_, Uca0statwSpiSpec> {
UcfeW::new(self, 6)
}
#[doc = "Bit 7 - USCI Listen mode"]
#[inline(always)]
pub fn uclisten(&mut self) -> UclistenW<'_, Uca0statwSpiSpec> {
UclistenW::new(self, 7)
}
}
#[doc = "USCI A0 Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0statw_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0statw_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0statwSpiSpec;
impl crate::RegisterSpec for Uca0statwSpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca0statw_spi::R`](R) reader structure"]
impl crate::Readable for Uca0statwSpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0statw_spi::W`](W) writer structure"]
impl crate::Writable for Uca0statwSpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0STATW_SPI to value 0"]
impl crate::Resettable for Uca0statwSpiSpec {}
}
#[doc = "UCA0IE_SPI (rw) register accessor: USCI A0 Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0ie_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0ie_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0ie_spi`] module"]
#[doc(alias = "UCA0IE_SPI")]
pub type Uca0ieSpi = crate::Reg<uca0ie_spi::Uca0ieSpiSpec>;
#[doc = "USCI A0 Interrupt Enable Register"]
pub mod uca0ie_spi {
#[doc = "Register `UCA0IE_SPI` reader"]
pub type R = crate::R<Uca0ieSpiSpec>;
#[doc = "Register `UCA0IE_SPI` writer"]
pub type W = crate::W<Uca0ieSpiSpec>;
#[doc = "Field `UCRXIE` reader - USCI Receive Interrupt Enable"]
pub type UcrxieR = crate::BitReader;
#[doc = "Field `UCRXIE` writer - USCI Receive Interrupt Enable"]
pub type UcrxieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCTXIE` reader - USCI Transmit Interrupt Enable"]
pub type UctxieR = crate::BitReader;
#[doc = "Field `UCTXIE` writer - USCI Transmit Interrupt Enable"]
pub type UctxieW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - USCI Receive Interrupt Enable"]
#[inline(always)]
pub fn ucrxie(&self) -> UcrxieR {
UcrxieR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - USCI Transmit Interrupt Enable"]
#[inline(always)]
pub fn uctxie(&self) -> UctxieR {
UctxieR::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - USCI Receive Interrupt Enable"]
#[inline(always)]
pub fn ucrxie(&mut self) -> UcrxieW<'_, Uca0ieSpiSpec> {
UcrxieW::new(self, 0)
}
#[doc = "Bit 1 - USCI Transmit Interrupt Enable"]
#[inline(always)]
pub fn uctxie(&mut self) -> UctxieW<'_, Uca0ieSpiSpec> {
UctxieW::new(self, 1)
}
}
#[doc = "USCI A0 Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0ie_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0ie_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0ieSpiSpec;
impl crate::RegisterSpec for Uca0ieSpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca0ie_spi::R`](R) reader structure"]
impl crate::Readable for Uca0ieSpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0ie_spi::W`](W) writer structure"]
impl crate::Writable for Uca0ieSpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0IE_SPI to value 0"]
impl crate::Resettable for Uca0ieSpiSpec {}
}
#[doc = "UCA0IFG_SPI (rw) register accessor: USCI A0 Interrupt Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0ifg_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0ifg_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0ifg_spi`] module"]
#[doc(alias = "UCA0IFG_SPI")]
pub type Uca0ifgSpi = crate::Reg<uca0ifg_spi::Uca0ifgSpiSpec>;
#[doc = "USCI A0 Interrupt Flags Register"]
pub mod uca0ifg_spi {
#[doc = "Register `UCA0IFG_SPI` reader"]
pub type R = crate::R<Uca0ifgSpiSpec>;
#[doc = "Register `UCA0IFG_SPI` writer"]
pub type W = crate::W<Uca0ifgSpiSpec>;
#[doc = "Field `UCRXIFG` reader - SPI Receive Interrupt Flag"]
pub type UcrxifgR = crate::BitReader;
#[doc = "Field `UCRXIFG` writer - SPI Receive Interrupt Flag"]
pub type UcrxifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCTXIFG` reader - SPI Transmit Interrupt Flag"]
pub type UctxifgR = crate::BitReader;
#[doc = "Field `UCTXIFG` writer - SPI Transmit Interrupt Flag"]
pub type UctxifgW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - SPI Receive Interrupt Flag"]
#[inline(always)]
pub fn ucrxifg(&self) -> UcrxifgR {
UcrxifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - SPI Transmit Interrupt Flag"]
#[inline(always)]
pub fn uctxifg(&self) -> UctxifgR {
UctxifgR::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - SPI Receive Interrupt Flag"]
#[inline(always)]
pub fn ucrxifg(&mut self) -> UcrxifgW<'_, Uca0ifgSpiSpec> {
UcrxifgW::new(self, 0)
}
#[doc = "Bit 1 - SPI Transmit Interrupt Flag"]
#[inline(always)]
pub fn uctxifg(&mut self) -> UctxifgW<'_, Uca0ifgSpiSpec> {
UctxifgW::new(self, 1)
}
}
#[doc = "USCI A0 Interrupt Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0ifg_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0ifg_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0ifgSpiSpec;
impl crate::RegisterSpec for Uca0ifgSpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca0ifg_spi::R`](R) reader structure"]
impl crate::Readable for Uca0ifgSpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0ifg_spi::W`](W) writer structure"]
impl crate::Writable for Uca0ifgSpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0IFG_SPI to value 0"]
impl crate::Resettable for Uca0ifgSpiSpec {}
}
#[doc = "UCA0RXBUF_SPI (rw) register accessor: USCI A0 Receive Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0rxbuf_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0rxbuf_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0rxbuf_spi`] module"]
#[doc(alias = "UCA0RXBUF_SPI")]
pub type Uca0rxbufSpi = crate::Reg<uca0rxbuf_spi::Uca0rxbufSpiSpec>;
#[doc = "USCI A0 Receive Buffer"]
pub mod uca0rxbuf_spi {
#[doc = "Register `UCA0RXBUF_SPI` reader"]
pub type R = crate::R<Uca0rxbufSpiSpec>;
#[doc = "Register `UCA0RXBUF_SPI` writer"]
pub type W = crate::W<Uca0rxbufSpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A0 Receive Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0rxbuf_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0rxbuf_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0rxbufSpiSpec;
impl crate::RegisterSpec for Uca0rxbufSpiSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`uca0rxbuf_spi::R`](R) reader structure"]
impl crate::Readable for Uca0rxbufSpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0rxbuf_spi::W`](W) writer structure"]
impl crate::Writable for Uca0rxbufSpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0RXBUF_SPI to value 0"]
impl crate::Resettable for Uca0rxbufSpiSpec {}
}
#[doc = "UCA0TXBUF_SPI (rw) register accessor: USCI A0 Transmit Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0txbuf_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0txbuf_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0txbuf_spi`] module"]
#[doc(alias = "UCA0TXBUF_SPI")]
pub type Uca0txbufSpi = crate::Reg<uca0txbuf_spi::Uca0txbufSpiSpec>;
#[doc = "USCI A0 Transmit Buffer"]
pub mod uca0txbuf_spi {
#[doc = "Register `UCA0TXBUF_SPI` reader"]
pub type R = crate::R<Uca0txbufSpiSpec>;
#[doc = "Register `UCA0TXBUF_SPI` writer"]
pub type W = crate::W<Uca0txbufSpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A0 Transmit Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0txbuf_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0txbuf_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0txbufSpiSpec;
impl crate::RegisterSpec for Uca0txbufSpiSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`uca0txbuf_spi::R`](R) reader structure"]
impl crate::Readable for Uca0txbufSpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0txbuf_spi::W`](W) writer structure"]
impl crate::Writable for Uca0txbufSpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0TXBUF_SPI to value 0"]
impl crate::Resettable for Uca0txbufSpiSpec {}
}
#[doc = "UCA0IV_SPI (rw) register accessor: USCI A0 Interrupt Vector Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0iv_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0iv_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca0iv_spi`] module"]
#[doc(alias = "UCA0IV_SPI")]
pub type Uca0ivSpi = crate::Reg<uca0iv_spi::Uca0ivSpiSpec>;
#[doc = "USCI A0 Interrupt Vector Register"]
pub mod uca0iv_spi {
#[doc = "Register `UCA0IV_SPI` reader"]
pub type R = crate::R<Uca0ivSpiSpec>;
#[doc = "Register `UCA0IV_SPI` writer"]
pub type W = crate::W<Uca0ivSpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A0 Interrupt Vector Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca0iv_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca0iv_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca0ivSpiSpec;
impl crate::RegisterSpec for Uca0ivSpiSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`uca0iv_spi::R`](R) reader structure"]
impl crate::Readable for Uca0ivSpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca0iv_spi::W`](W) writer structure"]
impl crate::Writable for Uca0ivSpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA0IV_SPI to value 0"]
impl crate::Resettable for Uca0ivSpiSpec {}
}
}
#[doc = "USCI_A1 UART Mode"]
pub type UsciA1UartMode = crate::Periph<usci_a1_uart_mode::RegisterBlock, 0x05e0>;
impl core::fmt::Debug for UsciA1UartMode {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UsciA1UartMode").finish()
}
}
#[doc = "USCI_A1 UART Mode"]
pub mod usci_a1_uart_mode {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
uca1ctl1: Uca1ctl1,
uca1ctl0: Uca1ctl0,
uca1ctlw1: Uca1ctlw1,
_reserved3: [u8; 0x02],
uca1br0: Uca1br0,
uca1br1: Uca1br1,
uca1mctlw: Uca1mctlw,
uca1statw: Uca1statw,
_reserved7: [u8; 0x01],
uca1rxbuf: Uca1rxbuf,
uca1txbuf: Uca1txbuf,
uca1abctl: Uca1abctl,
_reserved10: [u8; 0x01],
uca1irtctl: Uca1irtctl,
uca1irrctl: Uca1irrctl,
_reserved12: [u8; 0x0a],
uca1iv: Uca1iv,
}
impl RegisterBlock {
#[doc = "0x00 - USCI A1 Control Register 1"]
#[inline(always)]
pub const fn uca1ctl1(&self) -> &Uca1ctl1 {
&self.uca1ctl1
}
#[doc = "0x01 - USCI A1 Control Register 0"]
#[inline(always)]
pub const fn uca1ctl0(&self) -> &Uca1ctl0 {
&self.uca1ctl0
}
#[doc = "0x02 - USCI A1 Control Word Register 1"]
#[inline(always)]
pub const fn uca1ctlw1(&self) -> &Uca1ctlw1 {
&self.uca1ctlw1
}
#[doc = "0x06 - USCI A1 Baud Rate 0"]
#[inline(always)]
pub const fn uca1br0(&self) -> &Uca1br0 {
&self.uca1br0
}
#[doc = "0x07 - USCI A1 Baud Rate 1"]
#[inline(always)]
pub const fn uca1br1(&self) -> &Uca1br1 {
&self.uca1br1
}
#[doc = "0x08 - USCI A1 Modulation Control"]
#[inline(always)]
pub const fn uca1mctlw(&self) -> &Uca1mctlw {
&self.uca1mctlw
}
#[doc = "0x0a - USCI A1 Status Register"]
#[inline(always)]
pub const fn uca1statw(&self) -> &Uca1statw {
&self.uca1statw
}
#[doc = "0x0c - USCI A1 Receive Buffer"]
#[inline(always)]
pub const fn uca1rxbuf(&self) -> &Uca1rxbuf {
&self.uca1rxbuf
}
#[doc = "0x0e - USCI A1 Transmit Buffer"]
#[inline(always)]
pub const fn uca1txbuf(&self) -> &Uca1txbuf {
&self.uca1txbuf
}
#[doc = "0x10 - USCI A1 LIN Control"]
#[inline(always)]
pub const fn uca1abctl(&self) -> &Uca1abctl {
&self.uca1abctl
}
#[doc = "0x12 - USCI A1 IrDA Transmit Control"]
#[inline(always)]
pub const fn uca1irtctl(&self) -> &Uca1irtctl {
&self.uca1irtctl
}
#[doc = "0x13 - USCI A1 IrDA Receive Control"]
#[inline(always)]
pub const fn uca1irrctl(&self) -> &Uca1irrctl {
&self.uca1irrctl
}
#[doc = "0x1e - USCI A1 Interrupt Vector Register"]
#[inline(always)]
pub const fn uca1iv(&self) -> &Uca1iv {
&self.uca1iv
}
}
#[doc = "UCA1CTL1 (rw) register accessor: USCI A1 Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1ctl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1ctl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1ctl1`] module"]
#[doc(alias = "UCA1CTL1")]
pub type Uca1ctl1 = crate::Reg<uca1ctl1::Uca1ctl1Spec>;
#[doc = "USCI A1 Control Register 1"]
pub mod uca1ctl1 {
#[doc = "Register `UCA1CTL1` reader"]
pub type R = crate::R<Uca1ctl1Spec>;
#[doc = "Register `UCA1CTL1` writer"]
pub type W = crate::W<Uca1ctl1Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A1 Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1ctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1ctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1ctl1Spec;
impl crate::RegisterSpec for Uca1ctl1Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca1ctl1::R`](R) reader structure"]
impl crate::Readable for Uca1ctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`uca1ctl1::W`](W) writer structure"]
impl crate::Writable for Uca1ctl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1CTL1 to value 0"]
impl crate::Resettable for Uca1ctl1Spec {}
}
#[doc = "UCA1CTL0 (rw) register accessor: USCI A1 Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1ctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1ctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1ctl0`] module"]
#[doc(alias = "UCA1CTL0")]
pub type Uca1ctl0 = crate::Reg<uca1ctl0::Uca1ctl0Spec>;
#[doc = "USCI A1 Control Register 0"]
pub mod uca1ctl0 {
#[doc = "Register `UCA1CTL0` reader"]
pub type R = crate::R<Uca1ctl0Spec>;
#[doc = "Register `UCA1CTL0` writer"]
pub type W = crate::W<Uca1ctl0Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A1 Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1ctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1ctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1ctl0Spec;
impl crate::RegisterSpec for Uca1ctl0Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca1ctl0::R`](R) reader structure"]
impl crate::Readable for Uca1ctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`uca1ctl0::W`](W) writer structure"]
impl crate::Writable for Uca1ctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1CTL0 to value 0"]
impl crate::Resettable for Uca1ctl0Spec {}
}
#[doc = "UCA1BR0 (rw) register accessor: USCI A1 Baud Rate 0\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1br0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1br0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1br0`] module"]
#[doc(alias = "UCA1BR0")]
pub type Uca1br0 = crate::Reg<uca1br0::Uca1br0Spec>;
#[doc = "USCI A1 Baud Rate 0"]
pub mod uca1br0 {
#[doc = "Register `UCA1BR0` reader"]
pub type R = crate::R<Uca1br0Spec>;
#[doc = "Register `UCA1BR0` writer"]
pub type W = crate::W<Uca1br0Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A1 Baud Rate 0\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1br0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1br0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1br0Spec;
impl crate::RegisterSpec for Uca1br0Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca1br0::R`](R) reader structure"]
impl crate::Readable for Uca1br0Spec {}
#[doc = "`write(|w| ..)` method takes [`uca1br0::W`](W) writer structure"]
impl crate::Writable for Uca1br0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1BR0 to value 0"]
impl crate::Resettable for Uca1br0Spec {}
}
#[doc = "UCA1BR1 (rw) register accessor: USCI A1 Baud Rate 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1br1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1br1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1br1`] module"]
#[doc(alias = "UCA1BR1")]
pub type Uca1br1 = crate::Reg<uca1br1::Uca1br1Spec>;
#[doc = "USCI A1 Baud Rate 1"]
pub mod uca1br1 {
#[doc = "Register `UCA1BR1` reader"]
pub type R = crate::R<Uca1br1Spec>;
#[doc = "Register `UCA1BR1` writer"]
pub type W = crate::W<Uca1br1Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A1 Baud Rate 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1br1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1br1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1br1Spec;
impl crate::RegisterSpec for Uca1br1Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca1br1::R`](R) reader structure"]
impl crate::Readable for Uca1br1Spec {}
#[doc = "`write(|w| ..)` method takes [`uca1br1::W`](W) writer structure"]
impl crate::Writable for Uca1br1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1BR1 to value 0"]
impl crate::Resettable for Uca1br1Spec {}
}
#[doc = "UCA1STATW (rw) register accessor: USCI A1 Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1statw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1statw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1statw`] module"]
#[doc(alias = "UCA1STATW")]
pub type Uca1statw = crate::Reg<uca1statw::Uca1statwSpec>;
#[doc = "USCI A1 Status Register"]
pub mod uca1statw {
#[doc = "Register `UCA1STATW` reader"]
pub type R = crate::R<Uca1statwSpec>;
#[doc = "Register `UCA1STATW` writer"]
pub type W = crate::W<Uca1statwSpec>;
#[doc = "Field `UCBUSY` reader - USCI Busy Flag"]
pub type UcbusyR = crate::BitReader;
#[doc = "Field `UCBUSY` writer - USCI Busy Flag"]
pub type UcbusyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDR` reader - USCI Address received Flag"]
pub type UcaddrR = crate::BitReader;
#[doc = "Field `UCADDR` writer - USCI Address received Flag"]
pub type UcaddrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCRXERR` reader - USCI RX Error Flag"]
pub type UcrxerrR = crate::BitReader;
#[doc = "Field `UCRXERR` writer - USCI RX Error Flag"]
pub type UcrxerrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBRK` reader - USCI Break received"]
pub type UcbrkR = crate::BitReader;
#[doc = "Field `UCBRK` writer - USCI Break received"]
pub type UcbrkW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCPE` reader - USCI Parity Error Flag"]
pub type UcpeR = crate::BitReader;
#[doc = "Field `UCPE` writer - USCI Parity Error Flag"]
pub type UcpeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOE` reader - USCI Overrun Error Flag"]
pub type UcoeR = crate::BitReader;
#[doc = "Field `UCOE` writer - USCI Overrun Error Flag"]
pub type UcoeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCFE` reader - USCI Frame Error Flag"]
pub type UcfeR = crate::BitReader;
#[doc = "Field `UCFE` writer - USCI Frame Error Flag"]
pub type UcfeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCLISTEN` reader - USCI Listen mode"]
pub type UclistenR = crate::BitReader;
#[doc = "Field `UCLISTEN` writer - USCI Listen mode"]
pub type UclistenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - USCI Busy Flag"]
#[inline(always)]
pub fn ucbusy(&self) -> UcbusyR {
UcbusyR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - USCI Address received Flag"]
#[inline(always)]
pub fn ucaddr(&self) -> UcaddrR {
UcaddrR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - USCI RX Error Flag"]
#[inline(always)]
pub fn ucrxerr(&self) -> UcrxerrR {
UcrxerrR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - USCI Break received"]
#[inline(always)]
pub fn ucbrk(&self) -> UcbrkR {
UcbrkR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - USCI Parity Error Flag"]
#[inline(always)]
pub fn ucpe(&self) -> UcpeR {
UcpeR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - USCI Overrun Error Flag"]
#[inline(always)]
pub fn ucoe(&self) -> UcoeR {
UcoeR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - USCI Frame Error Flag"]
#[inline(always)]
pub fn ucfe(&self) -> UcfeR {
UcfeR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - USCI Listen mode"]
#[inline(always)]
pub fn uclisten(&self) -> UclistenR {
UclistenR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - USCI Busy Flag"]
#[inline(always)]
pub fn ucbusy(&mut self) -> UcbusyW<'_, Uca1statwSpec> {
UcbusyW::new(self, 0)
}
#[doc = "Bit 1 - USCI Address received Flag"]
#[inline(always)]
pub fn ucaddr(&mut self) -> UcaddrW<'_, Uca1statwSpec> {
UcaddrW::new(self, 1)
}
#[doc = "Bit 2 - USCI RX Error Flag"]
#[inline(always)]
pub fn ucrxerr(&mut self) -> UcrxerrW<'_, Uca1statwSpec> {
UcrxerrW::new(self, 2)
}
#[doc = "Bit 3 - USCI Break received"]
#[inline(always)]
pub fn ucbrk(&mut self) -> UcbrkW<'_, Uca1statwSpec> {
UcbrkW::new(self, 3)
}
#[doc = "Bit 4 - USCI Parity Error Flag"]
#[inline(always)]
pub fn ucpe(&mut self) -> UcpeW<'_, Uca1statwSpec> {
UcpeW::new(self, 4)
}
#[doc = "Bit 5 - USCI Overrun Error Flag"]
#[inline(always)]
pub fn ucoe(&mut self) -> UcoeW<'_, Uca1statwSpec> {
UcoeW::new(self, 5)
}
#[doc = "Bit 6 - USCI Frame Error Flag"]
#[inline(always)]
pub fn ucfe(&mut self) -> UcfeW<'_, Uca1statwSpec> {
UcfeW::new(self, 6)
}
#[doc = "Bit 7 - USCI Listen mode"]
#[inline(always)]
pub fn uclisten(&mut self) -> UclistenW<'_, Uca1statwSpec> {
UclistenW::new(self, 7)
}
}
#[doc = "USCI A1 Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1statw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1statw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1statwSpec;
impl crate::RegisterSpec for Uca1statwSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca1statw::R`](R) reader structure"]
impl crate::Readable for Uca1statwSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1statw::W`](W) writer structure"]
impl crate::Writable for Uca1statwSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets UCA1STATW to value 0"]
impl crate::Resettable for Uca1statwSpec {}
}
#[doc = "UCA1ABCTL (rw) register accessor: USCI A1 LIN Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1abctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1abctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1abctl`] module"]
#[doc(alias = "UCA1ABCTL")]
pub type Uca1abctl = crate::Reg<uca1abctl::Uca1abctlSpec>;
#[doc = "USCI A1 LIN Control"]
pub mod uca1abctl {
#[doc = "Register `UCA1ABCTL` reader"]
pub type R = crate::R<Uca1abctlSpec>;
#[doc = "Register `UCA1ABCTL` writer"]
pub type W = crate::W<Uca1abctlSpec>;
#[doc = "Field `UCABDEN` reader - Auto Baud Rate detect enable"]
pub type UcabdenR = crate::BitReader;
#[doc = "Field `UCABDEN` writer - Auto Baud Rate detect enable"]
pub type UcabdenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBTOE` reader - Break Timeout error"]
pub type UcbtoeR = crate::BitReader;
#[doc = "Field `UCBTOE` writer - Break Timeout error"]
pub type UcbtoeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCSTOE` reader - Sync-Field Timeout error"]
pub type UcstoeR = crate::BitReader;
#[doc = "Field `UCSTOE` writer - Sync-Field Timeout error"]
pub type UcstoeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCDELIM0` reader - Break Sync Delimiter 0"]
pub type Ucdelim0R = crate::BitReader;
#[doc = "Field `UCDELIM0` writer - Break Sync Delimiter 0"]
pub type Ucdelim0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCDELIM1` reader - Break Sync Delimiter 1"]
pub type Ucdelim1R = crate::BitReader;
#[doc = "Field `UCDELIM1` writer - Break Sync Delimiter 1"]
pub type Ucdelim1W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Auto Baud Rate detect enable"]
#[inline(always)]
pub fn ucabden(&self) -> UcabdenR {
UcabdenR::new((self.bits & 1) != 0)
}
#[doc = "Bit 2 - Break Timeout error"]
#[inline(always)]
pub fn ucbtoe(&self) -> UcbtoeR {
UcbtoeR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Sync-Field Timeout error"]
#[inline(always)]
pub fn ucstoe(&self) -> UcstoeR {
UcstoeR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Break Sync Delimiter 0"]
#[inline(always)]
pub fn ucdelim0(&self) -> Ucdelim0R {
Ucdelim0R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Break Sync Delimiter 1"]
#[inline(always)]
pub fn ucdelim1(&self) -> Ucdelim1R {
Ucdelim1R::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Auto Baud Rate detect enable"]
#[inline(always)]
pub fn ucabden(&mut self) -> UcabdenW<'_, Uca1abctlSpec> {
UcabdenW::new(self, 0)
}
#[doc = "Bit 2 - Break Timeout error"]
#[inline(always)]
pub fn ucbtoe(&mut self) -> UcbtoeW<'_, Uca1abctlSpec> {
UcbtoeW::new(self, 2)
}
#[doc = "Bit 3 - Sync-Field Timeout error"]
#[inline(always)]
pub fn ucstoe(&mut self) -> UcstoeW<'_, Uca1abctlSpec> {
UcstoeW::new(self, 3)
}
#[doc = "Bit 4 - Break Sync Delimiter 0"]
#[inline(always)]
pub fn ucdelim0(&mut self) -> Ucdelim0W<'_, Uca1abctlSpec> {
Ucdelim0W::new(self, 4)
}
#[doc = "Bit 5 - Break Sync Delimiter 1"]
#[inline(always)]
pub fn ucdelim1(&mut self) -> Ucdelim1W<'_, Uca1abctlSpec> {
Ucdelim1W::new(self, 5)
}
}
#[doc = "USCI A1 LIN Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1abctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1abctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1abctlSpec;
impl crate::RegisterSpec for Uca1abctlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca1abctl::R`](R) reader structure"]
impl crate::Readable for Uca1abctlSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1abctl::W`](W) writer structure"]
impl crate::Writable for Uca1abctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1ABCTL to value 0"]
impl crate::Resettable for Uca1abctlSpec {}
}
#[doc = "UCA1IRTCTL (rw) register accessor: USCI A1 IrDA Transmit Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1irtctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1irtctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1irtctl`] module"]
#[doc(alias = "UCA1IRTCTL")]
pub type Uca1irtctl = crate::Reg<uca1irtctl::Uca1irtctlSpec>;
#[doc = "USCI A1 IrDA Transmit Control"]
pub mod uca1irtctl {
#[doc = "Register `UCA1IRTCTL` reader"]
pub type R = crate::R<Uca1irtctlSpec>;
#[doc = "Register `UCA1IRTCTL` writer"]
pub type W = crate::W<Uca1irtctlSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A1 IrDA Transmit Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1irtctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1irtctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1irtctlSpec;
impl crate::RegisterSpec for Uca1irtctlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca1irtctl::R`](R) reader structure"]
impl crate::Readable for Uca1irtctlSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1irtctl::W`](W) writer structure"]
impl crate::Writable for Uca1irtctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1IRTCTL to value 0"]
impl crate::Resettable for Uca1irtctlSpec {}
}
#[doc = "UCA1IRRCTL (rw) register accessor: USCI A1 IrDA Receive Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1irrctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1irrctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1irrctl`] module"]
#[doc(alias = "UCA1IRRCTL")]
pub type Uca1irrctl = crate::Reg<uca1irrctl::Uca1irrctlSpec>;
#[doc = "USCI A1 IrDA Receive Control"]
pub mod uca1irrctl {
#[doc = "Register `UCA1IRRCTL` reader"]
pub type R = crate::R<Uca1irrctlSpec>;
#[doc = "Register `UCA1IRRCTL` writer"]
pub type W = crate::W<Uca1irrctlSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A1 IrDA Receive Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1irrctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1irrctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1irrctlSpec;
impl crate::RegisterSpec for Uca1irrctlSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca1irrctl::R`](R) reader structure"]
impl crate::Readable for Uca1irrctlSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1irrctl::W`](W) writer structure"]
impl crate::Writable for Uca1irrctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1IRRCTL to value 0"]
impl crate::Resettable for Uca1irrctlSpec {}
}
#[doc = "UCA1CTLW1 (rw) register accessor: USCI A1 Control Word Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1ctlw1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1ctlw1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1ctlw1`] module"]
#[doc(alias = "UCA1CTLW1")]
pub type Uca1ctlw1 = crate::Reg<uca1ctlw1::Uca1ctlw1Spec>;
#[doc = "USCI A1 Control Word Register 1"]
pub mod uca1ctlw1 {
#[doc = "Register `UCA1CTLW1` reader"]
pub type R = crate::R<Uca1ctlw1Spec>;
#[doc = "Register `UCA1CTLW1` writer"]
pub type W = crate::W<Uca1ctlw1Spec>;
#[doc = "USCI Deglitch Time Bit 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ucglit {
#[doc = "0: USCI Deglitch time: 0"]
Ucglit0 = 0,
#[doc = "1: USCI Deglitch time: 1"]
Ucglit1 = 1,
#[doc = "2: USCI Deglitch time: 2"]
Ucglit2 = 2,
#[doc = "3: USCI Deglitch time: 3"]
Ucglit3 = 3,
}
impl From<Ucglit> for u8 {
#[inline(always)]
fn from(variant: Ucglit) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ucglit {
type Ux = u8;
}
impl crate::IsEnum for Ucglit {}
#[doc = "Field `UCGLIT` reader - USCI Deglitch Time Bit 1"]
pub type UcglitR = crate::FieldReader<Ucglit>;
impl UcglitR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ucglit {
match self.bits {
0 => Ucglit::Ucglit0,
1 => Ucglit::Ucglit1,
2 => Ucglit::Ucglit2,
3 => Ucglit::Ucglit3,
_ => unreachable!(),
}
}
#[doc = "USCI Deglitch time: 0"]
#[inline(always)]
pub fn is_ucglit_0(&self) -> bool {
*self == Ucglit::Ucglit0
}
#[doc = "USCI Deglitch time: 1"]
#[inline(always)]
pub fn is_ucglit_1(&self) -> bool {
*self == Ucglit::Ucglit1
}
#[doc = "USCI Deglitch time: 2"]
#[inline(always)]
pub fn is_ucglit_2(&self) -> bool {
*self == Ucglit::Ucglit2
}
#[doc = "USCI Deglitch time: 3"]
#[inline(always)]
pub fn is_ucglit_3(&self) -> bool {
*self == Ucglit::Ucglit3
}
}
#[doc = "Field `UCGLIT` writer - USCI Deglitch Time Bit 1"]
pub type UcglitW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ucglit, crate::Safe>;
impl<'a, REG> UcglitW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "USCI Deglitch time: 0"]
#[inline(always)]
pub fn ucglit_0(self) -> &'a mut crate::W<REG> {
self.variant(Ucglit::Ucglit0)
}
#[doc = "USCI Deglitch time: 1"]
#[inline(always)]
pub fn ucglit_1(self) -> &'a mut crate::W<REG> {
self.variant(Ucglit::Ucglit1)
}
#[doc = "USCI Deglitch time: 2"]
#[inline(always)]
pub fn ucglit_2(self) -> &'a mut crate::W<REG> {
self.variant(Ucglit::Ucglit2)
}
#[doc = "USCI Deglitch time: 3"]
#[inline(always)]
pub fn ucglit_3(self) -> &'a mut crate::W<REG> {
self.variant(Ucglit::Ucglit3)
}
}
impl R {
#[doc = "Bits 0:1 - USCI Deglitch Time Bit 1"]
#[inline(always)]
pub fn ucglit(&self) -> UcglitR {
UcglitR::new((self.bits & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - USCI Deglitch Time Bit 1"]
#[inline(always)]
pub fn ucglit(&mut self) -> UcglitW<'_, Uca1ctlw1Spec> {
UcglitW::new(self, 0)
}
}
#[doc = "USCI A1 Control Word Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1ctlw1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1ctlw1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1ctlw1Spec;
impl crate::RegisterSpec for Uca1ctlw1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`uca1ctlw1::R`](R) reader structure"]
impl crate::Readable for Uca1ctlw1Spec {}
#[doc = "`write(|w| ..)` method takes [`uca1ctlw1::W`](W) writer structure"]
impl crate::Writable for Uca1ctlw1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1CTLW1 to value 0"]
impl crate::Resettable for Uca1ctlw1Spec {}
}
#[doc = "UCA1MCTLW (rw) register accessor: USCI A1 Modulation Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1mctlw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1mctlw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1mctlw`] module"]
#[doc(alias = "UCA1MCTLW")]
pub type Uca1mctlw = crate::Reg<uca1mctlw::Uca1mctlwSpec>;
#[doc = "USCI A1 Modulation Control"]
pub mod uca1mctlw {
#[doc = "Register `UCA1MCTLW` reader"]
pub type R = crate::R<Uca1mctlwSpec>;
#[doc = "Register `UCA1MCTLW` writer"]
pub type W = crate::W<Uca1mctlwSpec>;
#[doc = "Field `UCOS16` reader - USCI 16-times Oversampling enable"]
pub type Ucos16R = crate::BitReader;
#[doc = "Field `UCOS16` writer - USCI 16-times Oversampling enable"]
pub type Ucos16W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "USCI First Stage Modulation Select 3\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ucbrf {
#[doc = "0: USCI First Stage Modulation: 0"]
Ucbrf0 = 0,
#[doc = "1: USCI First Stage Modulation: 1"]
Ucbrf1 = 1,
#[doc = "2: USCI First Stage Modulation: 2"]
Ucbrf2 = 2,
#[doc = "3: USCI First Stage Modulation: 3"]
Ucbrf3 = 3,
#[doc = "4: USCI First Stage Modulation: 4"]
Ucbrf4 = 4,
#[doc = "5: USCI First Stage Modulation: 5"]
Ucbrf5 = 5,
#[doc = "6: USCI First Stage Modulation: 6"]
Ucbrf6 = 6,
#[doc = "7: USCI First Stage Modulation: 7"]
Ucbrf7 = 7,
#[doc = "8: USCI First Stage Modulation: 8"]
Ucbrf8 = 8,
#[doc = "9: USCI First Stage Modulation: 9"]
Ucbrf9 = 9,
#[doc = "10: USCI First Stage Modulation: A"]
Ucbrf10 = 10,
#[doc = "11: USCI First Stage Modulation: B"]
Ucbrf11 = 11,
#[doc = "12: USCI First Stage Modulation: C"]
Ucbrf12 = 12,
#[doc = "13: USCI First Stage Modulation: D"]
Ucbrf13 = 13,
#[doc = "14: USCI First Stage Modulation: E"]
Ucbrf14 = 14,
#[doc = "15: USCI First Stage Modulation: F"]
Ucbrf15 = 15,
}
impl From<Ucbrf> for u8 {
#[inline(always)]
fn from(variant: Ucbrf) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ucbrf {
type Ux = u8;
}
impl crate::IsEnum for Ucbrf {}
#[doc = "Field `UCBRF` reader - USCI First Stage Modulation Select 3"]
pub type UcbrfR = crate::FieldReader<Ucbrf>;
impl UcbrfR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ucbrf {
match self.bits {
0 => Ucbrf::Ucbrf0,
1 => Ucbrf::Ucbrf1,
2 => Ucbrf::Ucbrf2,
3 => Ucbrf::Ucbrf3,
4 => Ucbrf::Ucbrf4,
5 => Ucbrf::Ucbrf5,
6 => Ucbrf::Ucbrf6,
7 => Ucbrf::Ucbrf7,
8 => Ucbrf::Ucbrf8,
9 => Ucbrf::Ucbrf9,
10 => Ucbrf::Ucbrf10,
11 => Ucbrf::Ucbrf11,
12 => Ucbrf::Ucbrf12,
13 => Ucbrf::Ucbrf13,
14 => Ucbrf::Ucbrf14,
15 => Ucbrf::Ucbrf15,
_ => unreachable!(),
}
}
#[doc = "USCI First Stage Modulation: 0"]
#[inline(always)]
pub fn is_ucbrf_0(&self) -> bool {
*self == Ucbrf::Ucbrf0
}
#[doc = "USCI First Stage Modulation: 1"]
#[inline(always)]
pub fn is_ucbrf_1(&self) -> bool {
*self == Ucbrf::Ucbrf1
}
#[doc = "USCI First Stage Modulation: 2"]
#[inline(always)]
pub fn is_ucbrf_2(&self) -> bool {
*self == Ucbrf::Ucbrf2
}
#[doc = "USCI First Stage Modulation: 3"]
#[inline(always)]
pub fn is_ucbrf_3(&self) -> bool {
*self == Ucbrf::Ucbrf3
}
#[doc = "USCI First Stage Modulation: 4"]
#[inline(always)]
pub fn is_ucbrf_4(&self) -> bool {
*self == Ucbrf::Ucbrf4
}
#[doc = "USCI First Stage Modulation: 5"]
#[inline(always)]
pub fn is_ucbrf_5(&self) -> bool {
*self == Ucbrf::Ucbrf5
}
#[doc = "USCI First Stage Modulation: 6"]
#[inline(always)]
pub fn is_ucbrf_6(&self) -> bool {
*self == Ucbrf::Ucbrf6
}
#[doc = "USCI First Stage Modulation: 7"]
#[inline(always)]
pub fn is_ucbrf_7(&self) -> bool {
*self == Ucbrf::Ucbrf7
}
#[doc = "USCI First Stage Modulation: 8"]
#[inline(always)]
pub fn is_ucbrf_8(&self) -> bool {
*self == Ucbrf::Ucbrf8
}
#[doc = "USCI First Stage Modulation: 9"]
#[inline(always)]
pub fn is_ucbrf_9(&self) -> bool {
*self == Ucbrf::Ucbrf9
}
#[doc = "USCI First Stage Modulation: A"]
#[inline(always)]
pub fn is_ucbrf_10(&self) -> bool {
*self == Ucbrf::Ucbrf10
}
#[doc = "USCI First Stage Modulation: B"]
#[inline(always)]
pub fn is_ucbrf_11(&self) -> bool {
*self == Ucbrf::Ucbrf11
}
#[doc = "USCI First Stage Modulation: C"]
#[inline(always)]
pub fn is_ucbrf_12(&self) -> bool {
*self == Ucbrf::Ucbrf12
}
#[doc = "USCI First Stage Modulation: D"]
#[inline(always)]
pub fn is_ucbrf_13(&self) -> bool {
*self == Ucbrf::Ucbrf13
}
#[doc = "USCI First Stage Modulation: E"]
#[inline(always)]
pub fn is_ucbrf_14(&self) -> bool {
*self == Ucbrf::Ucbrf14
}
#[doc = "USCI First Stage Modulation: F"]
#[inline(always)]
pub fn is_ucbrf_15(&self) -> bool {
*self == Ucbrf::Ucbrf15
}
}
#[doc = "Field `UCBRF` writer - USCI First Stage Modulation Select 3"]
pub type UcbrfW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ucbrf, crate::Safe>;
impl<'a, REG> UcbrfW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "USCI First Stage Modulation: 0"]
#[inline(always)]
pub fn ucbrf_0(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf0)
}
#[doc = "USCI First Stage Modulation: 1"]
#[inline(always)]
pub fn ucbrf_1(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf1)
}
#[doc = "USCI First Stage Modulation: 2"]
#[inline(always)]
pub fn ucbrf_2(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf2)
}
#[doc = "USCI First Stage Modulation: 3"]
#[inline(always)]
pub fn ucbrf_3(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf3)
}
#[doc = "USCI First Stage Modulation: 4"]
#[inline(always)]
pub fn ucbrf_4(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf4)
}
#[doc = "USCI First Stage Modulation: 5"]
#[inline(always)]
pub fn ucbrf_5(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf5)
}
#[doc = "USCI First Stage Modulation: 6"]
#[inline(always)]
pub fn ucbrf_6(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf6)
}
#[doc = "USCI First Stage Modulation: 7"]
#[inline(always)]
pub fn ucbrf_7(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf7)
}
#[doc = "USCI First Stage Modulation: 8"]
#[inline(always)]
pub fn ucbrf_8(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf8)
}
#[doc = "USCI First Stage Modulation: 9"]
#[inline(always)]
pub fn ucbrf_9(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf9)
}
#[doc = "USCI First Stage Modulation: A"]
#[inline(always)]
pub fn ucbrf_10(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf10)
}
#[doc = "USCI First Stage Modulation: B"]
#[inline(always)]
pub fn ucbrf_11(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf11)
}
#[doc = "USCI First Stage Modulation: C"]
#[inline(always)]
pub fn ucbrf_12(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf12)
}
#[doc = "USCI First Stage Modulation: D"]
#[inline(always)]
pub fn ucbrf_13(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf13)
}
#[doc = "USCI First Stage Modulation: E"]
#[inline(always)]
pub fn ucbrf_14(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf14)
}
#[doc = "USCI First Stage Modulation: F"]
#[inline(always)]
pub fn ucbrf_15(self) -> &'a mut crate::W<REG> {
self.variant(Ucbrf::Ucbrf15)
}
}
#[doc = "Field `UCBRS0` reader - USCI Second Stage Modulation Select 0"]
pub type Ucbrs0R = crate::BitReader;
#[doc = "Field `UCBRS0` writer - USCI Second Stage Modulation Select 0"]
pub type Ucbrs0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBRS1` reader - USCI Second Stage Modulation Select 1"]
pub type Ucbrs1R = crate::BitReader;
#[doc = "Field `UCBRS1` writer - USCI Second Stage Modulation Select 1"]
pub type Ucbrs1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBRS2` reader - USCI Second Stage Modulation Select 2"]
pub type Ucbrs2R = crate::BitReader;
#[doc = "Field `UCBRS2` writer - USCI Second Stage Modulation Select 2"]
pub type Ucbrs2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBRS3` reader - USCI Second Stage Modulation Select 3"]
pub type Ucbrs3R = crate::BitReader;
#[doc = "Field `UCBRS3` writer - USCI Second Stage Modulation Select 3"]
pub type Ucbrs3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBRS4` reader - USCI Second Stage Modulation Select 4"]
pub type Ucbrs4R = crate::BitReader;
#[doc = "Field `UCBRS4` writer - USCI Second Stage Modulation Select 4"]
pub type Ucbrs4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBRS5` reader - USCI Second Stage Modulation Select 5"]
pub type Ucbrs5R = crate::BitReader;
#[doc = "Field `UCBRS5` writer - USCI Second Stage Modulation Select 5"]
pub type Ucbrs5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBRS6` reader - USCI Second Stage Modulation Select 6"]
pub type Ucbrs6R = crate::BitReader;
#[doc = "Field `UCBRS6` writer - USCI Second Stage Modulation Select 6"]
pub type Ucbrs6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBRS7` reader - USCI Second Stage Modulation Select 7"]
pub type Ucbrs7R = crate::BitReader;
#[doc = "Field `UCBRS7` writer - USCI Second Stage Modulation Select 7"]
pub type Ucbrs7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - USCI 16-times Oversampling enable"]
#[inline(always)]
pub fn ucos16(&self) -> Ucos16R {
Ucos16R::new((self.bits & 1) != 0)
}
#[doc = "Bits 4:7 - USCI First Stage Modulation Select 3"]
#[inline(always)]
pub fn ucbrf(&self) -> UcbrfR {
UcbrfR::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bit 8 - USCI Second Stage Modulation Select 0"]
#[inline(always)]
pub fn ucbrs0(&self) -> Ucbrs0R {
Ucbrs0R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - USCI Second Stage Modulation Select 1"]
#[inline(always)]
pub fn ucbrs1(&self) -> Ucbrs1R {
Ucbrs1R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - USCI Second Stage Modulation Select 2"]
#[inline(always)]
pub fn ucbrs2(&self) -> Ucbrs2R {
Ucbrs2R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - USCI Second Stage Modulation Select 3"]
#[inline(always)]
pub fn ucbrs3(&self) -> Ucbrs3R {
Ucbrs3R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - USCI Second Stage Modulation Select 4"]
#[inline(always)]
pub fn ucbrs4(&self) -> Ucbrs4R {
Ucbrs4R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - USCI Second Stage Modulation Select 5"]
#[inline(always)]
pub fn ucbrs5(&self) -> Ucbrs5R {
Ucbrs5R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - USCI Second Stage Modulation Select 6"]
#[inline(always)]
pub fn ucbrs6(&self) -> Ucbrs6R {
Ucbrs6R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - USCI Second Stage Modulation Select 7"]
#[inline(always)]
pub fn ucbrs7(&self) -> Ucbrs7R {
Ucbrs7R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - USCI 16-times Oversampling enable"]
#[inline(always)]
pub fn ucos16(&mut self) -> Ucos16W<'_, Uca1mctlwSpec> {
Ucos16W::new(self, 0)
}
#[doc = "Bits 4:7 - USCI First Stage Modulation Select 3"]
#[inline(always)]
pub fn ucbrf(&mut self) -> UcbrfW<'_, Uca1mctlwSpec> {
UcbrfW::new(self, 4)
}
#[doc = "Bit 8 - USCI Second Stage Modulation Select 0"]
#[inline(always)]
pub fn ucbrs0(&mut self) -> Ucbrs0W<'_, Uca1mctlwSpec> {
Ucbrs0W::new(self, 8)
}
#[doc = "Bit 9 - USCI Second Stage Modulation Select 1"]
#[inline(always)]
pub fn ucbrs1(&mut self) -> Ucbrs1W<'_, Uca1mctlwSpec> {
Ucbrs1W::new(self, 9)
}
#[doc = "Bit 10 - USCI Second Stage Modulation Select 2"]
#[inline(always)]
pub fn ucbrs2(&mut self) -> Ucbrs2W<'_, Uca1mctlwSpec> {
Ucbrs2W::new(self, 10)
}
#[doc = "Bit 11 - USCI Second Stage Modulation Select 3"]
#[inline(always)]
pub fn ucbrs3(&mut self) -> Ucbrs3W<'_, Uca1mctlwSpec> {
Ucbrs3W::new(self, 11)
}
#[doc = "Bit 12 - USCI Second Stage Modulation Select 4"]
#[inline(always)]
pub fn ucbrs4(&mut self) -> Ucbrs4W<'_, Uca1mctlwSpec> {
Ucbrs4W::new(self, 12)
}
#[doc = "Bit 13 - USCI Second Stage Modulation Select 5"]
#[inline(always)]
pub fn ucbrs5(&mut self) -> Ucbrs5W<'_, Uca1mctlwSpec> {
Ucbrs5W::new(self, 13)
}
#[doc = "Bit 14 - USCI Second Stage Modulation Select 6"]
#[inline(always)]
pub fn ucbrs6(&mut self) -> Ucbrs6W<'_, Uca1mctlwSpec> {
Ucbrs6W::new(self, 14)
}
#[doc = "Bit 15 - USCI Second Stage Modulation Select 7"]
#[inline(always)]
pub fn ucbrs7(&mut self) -> Ucbrs7W<'_, Uca1mctlwSpec> {
Ucbrs7W::new(self, 15)
}
}
#[doc = "USCI A1 Modulation Control\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1mctlw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1mctlw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1mctlwSpec;
impl crate::RegisterSpec for Uca1mctlwSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`uca1mctlw::R`](R) reader structure"]
impl crate::Readable for Uca1mctlwSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1mctlw::W`](W) writer structure"]
impl crate::Writable for Uca1mctlwSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1MCTLW to value 0"]
impl crate::Resettable for Uca1mctlwSpec {}
}
#[doc = "UCA1RXBUF (rw) register accessor: USCI A1 Receive Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1rxbuf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1rxbuf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1rxbuf`] module"]
#[doc(alias = "UCA1RXBUF")]
pub type Uca1rxbuf = crate::Reg<uca1rxbuf::Uca1rxbufSpec>;
#[doc = "USCI A1 Receive Buffer"]
pub mod uca1rxbuf {
#[doc = "Register `UCA1RXBUF` reader"]
pub type R = crate::R<Uca1rxbufSpec>;
#[doc = "Register `UCA1RXBUF` writer"]
pub type W = crate::W<Uca1rxbufSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A1 Receive Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1rxbuf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1rxbuf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1rxbufSpec;
impl crate::RegisterSpec for Uca1rxbufSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`uca1rxbuf::R`](R) reader structure"]
impl crate::Readable for Uca1rxbufSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1rxbuf::W`](W) writer structure"]
impl crate::Writable for Uca1rxbufSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1RXBUF to value 0"]
impl crate::Resettable for Uca1rxbufSpec {}
}
#[doc = "UCA1TXBUF (rw) register accessor: USCI A1 Transmit Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1txbuf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1txbuf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1txbuf`] module"]
#[doc(alias = "UCA1TXBUF")]
pub type Uca1txbuf = crate::Reg<uca1txbuf::Uca1txbufSpec>;
#[doc = "USCI A1 Transmit Buffer"]
pub mod uca1txbuf {
#[doc = "Register `UCA1TXBUF` reader"]
pub type R = crate::R<Uca1txbufSpec>;
#[doc = "Register `UCA1TXBUF` writer"]
pub type W = crate::W<Uca1txbufSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A1 Transmit Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1txbuf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1txbuf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1txbufSpec;
impl crate::RegisterSpec for Uca1txbufSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`uca1txbuf::R`](R) reader structure"]
impl crate::Readable for Uca1txbufSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1txbuf::W`](W) writer structure"]
impl crate::Writable for Uca1txbufSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1TXBUF to value 0"]
impl crate::Resettable for Uca1txbufSpec {}
}
#[doc = "UCA1IV (rw) register accessor: USCI A1 Interrupt Vector Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1iv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1iv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1iv`] module"]
#[doc(alias = "UCA1IV")]
pub type Uca1iv = crate::Reg<uca1iv::Uca1ivSpec>;
#[doc = "USCI A1 Interrupt Vector Register"]
pub mod uca1iv {
#[doc = "Register `UCA1IV` reader"]
pub type R = crate::R<Uca1ivSpec>;
#[doc = "Register `UCA1IV` writer"]
pub type W = crate::W<Uca1ivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A1 Interrupt Vector Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1iv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1iv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1ivSpec;
impl crate::RegisterSpec for Uca1ivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`uca1iv::R`](R) reader structure"]
impl crate::Readable for Uca1ivSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1iv::W`](W) writer structure"]
impl crate::Writable for Uca1ivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1IV to value 0"]
impl crate::Resettable for Uca1ivSpec {}
}
}
#[doc = "USCI_A1 SPI Mode"]
pub type UsciA1SpiMode = crate::Periph<usci_a1_spi_mode::RegisterBlock, 0x05e0>;
impl core::fmt::Debug for UsciA1SpiMode {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UsciA1SpiMode").finish()
}
}
#[doc = "USCI_A1 SPI Mode"]
pub mod usci_a1_spi_mode {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
uca1ctl1_spi: Uca1ctl1Spi,
uca1ctl0_spi: Uca1ctl0Spi,
_reserved2: [u8; 0x04],
uca1br0_spi: Uca1br0Spi,
uca1br1_spi: Uca1br1Spi,
_reserved4: [u8; 0x02],
uca1statw_spi: Uca1statwSpi,
_reserved5: [u8; 0x01],
uca1rxbuf_spi: Uca1rxbufSpi,
uca1txbuf_spi: Uca1txbufSpi,
_reserved7: [u8; 0x0a],
uca1ie_spi: Uca1ieSpi,
_reserved8: [u8; 0x01],
uca1ifg_spi: Uca1ifgSpi,
_reserved9: [u8; 0x01],
uca1iv_spi: Uca1ivSpi,
}
impl RegisterBlock {
#[doc = "0x00 - USCI A1 Control Register 1"]
#[inline(always)]
pub const fn uca1ctl1_spi(&self) -> &Uca1ctl1Spi {
&self.uca1ctl1_spi
}
#[doc = "0x01 - USCI A1 Control Register 0"]
#[inline(always)]
pub const fn uca1ctl0_spi(&self) -> &Uca1ctl0Spi {
&self.uca1ctl0_spi
}
#[doc = "0x06 - USCI A1 Baud Rate 0"]
#[inline(always)]
pub const fn uca1br0_spi(&self) -> &Uca1br0Spi {
&self.uca1br0_spi
}
#[doc = "0x07 - USCI A1 Baud Rate 1"]
#[inline(always)]
pub const fn uca1br1_spi(&self) -> &Uca1br1Spi {
&self.uca1br1_spi
}
#[doc = "0x0a - USCI A1 Status Register"]
#[inline(always)]
pub const fn uca1statw_spi(&self) -> &Uca1statwSpi {
&self.uca1statw_spi
}
#[doc = "0x0c - USCI A1 Receive Buffer"]
#[inline(always)]
pub const fn uca1rxbuf_spi(&self) -> &Uca1rxbufSpi {
&self.uca1rxbuf_spi
}
#[doc = "0x0e - USCI A1 Transmit Buffer"]
#[inline(always)]
pub const fn uca1txbuf_spi(&self) -> &Uca1txbufSpi {
&self.uca1txbuf_spi
}
#[doc = "0x1a - USCI A1 Interrupt Enable Register"]
#[inline(always)]
pub const fn uca1ie_spi(&self) -> &Uca1ieSpi {
&self.uca1ie_spi
}
#[doc = "0x1c - USCI A1 Interrupt Flags Register"]
#[inline(always)]
pub const fn uca1ifg_spi(&self) -> &Uca1ifgSpi {
&self.uca1ifg_spi
}
#[doc = "0x1e - USCI A1 Interrupt Vector Register"]
#[inline(always)]
pub const fn uca1iv_spi(&self) -> &Uca1ivSpi {
&self.uca1iv_spi
}
}
#[doc = "UCA1CTL1_SPI (rw) register accessor: USCI A1 Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1ctl1_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1ctl1_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1ctl1_spi`] module"]
#[doc(alias = "UCA1CTL1_SPI")]
pub type Uca1ctl1Spi = crate::Reg<uca1ctl1_spi::Uca1ctl1SpiSpec>;
#[doc = "USCI A1 Control Register 1"]
pub mod uca1ctl1_spi {
#[doc = "Register `UCA1CTL1_SPI` reader"]
pub type R = crate::R<Uca1ctl1SpiSpec>;
#[doc = "Register `UCA1CTL1_SPI` writer"]
pub type W = crate::W<Uca1ctl1SpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A1 Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1ctl1_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1ctl1_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1ctl1SpiSpec;
impl crate::RegisterSpec for Uca1ctl1SpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca1ctl1_spi::R`](R) reader structure"]
impl crate::Readable for Uca1ctl1SpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1ctl1_spi::W`](W) writer structure"]
impl crate::Writable for Uca1ctl1SpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1CTL1_SPI to value 0"]
impl crate::Resettable for Uca1ctl1SpiSpec {}
}
#[doc = "UCA1CTL0_SPI (rw) register accessor: USCI A1 Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1ctl0_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1ctl0_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1ctl0_spi`] module"]
#[doc(alias = "UCA1CTL0_SPI")]
pub type Uca1ctl0Spi = crate::Reg<uca1ctl0_spi::Uca1ctl0SpiSpec>;
#[doc = "USCI A1 Control Register 0"]
pub mod uca1ctl0_spi {
#[doc = "Register `UCA1CTL0_SPI` reader"]
pub type R = crate::R<Uca1ctl0SpiSpec>;
#[doc = "Register `UCA1CTL0_SPI` writer"]
pub type W = crate::W<Uca1ctl0SpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A1 Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1ctl0_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1ctl0_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1ctl0SpiSpec;
impl crate::RegisterSpec for Uca1ctl0SpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca1ctl0_spi::R`](R) reader structure"]
impl crate::Readable for Uca1ctl0SpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1ctl0_spi::W`](W) writer structure"]
impl crate::Writable for Uca1ctl0SpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1CTL0_SPI to value 0"]
impl crate::Resettable for Uca1ctl0SpiSpec {}
}
#[doc = "UCA1BR0_SPI (rw) register accessor: USCI A1 Baud Rate 0\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1br0_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1br0_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1br0_spi`] module"]
#[doc(alias = "UCA1BR0_SPI")]
pub type Uca1br0Spi = crate::Reg<uca1br0_spi::Uca1br0SpiSpec>;
#[doc = "USCI A1 Baud Rate 0"]
pub mod uca1br0_spi {
#[doc = "Register `UCA1BR0_SPI` reader"]
pub type R = crate::R<Uca1br0SpiSpec>;
#[doc = "Register `UCA1BR0_SPI` writer"]
pub type W = crate::W<Uca1br0SpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A1 Baud Rate 0\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1br0_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1br0_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1br0SpiSpec;
impl crate::RegisterSpec for Uca1br0SpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca1br0_spi::R`](R) reader structure"]
impl crate::Readable for Uca1br0SpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1br0_spi::W`](W) writer structure"]
impl crate::Writable for Uca1br0SpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1BR0_SPI to value 0"]
impl crate::Resettable for Uca1br0SpiSpec {}
}
#[doc = "UCA1BR1_SPI (rw) register accessor: USCI A1 Baud Rate 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1br1_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1br1_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1br1_spi`] module"]
#[doc(alias = "UCA1BR1_SPI")]
pub type Uca1br1Spi = crate::Reg<uca1br1_spi::Uca1br1SpiSpec>;
#[doc = "USCI A1 Baud Rate 1"]
pub mod uca1br1_spi {
#[doc = "Register `UCA1BR1_SPI` reader"]
pub type R = crate::R<Uca1br1SpiSpec>;
#[doc = "Register `UCA1BR1_SPI` writer"]
pub type W = crate::W<Uca1br1SpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A1 Baud Rate 1\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1br1_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1br1_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1br1SpiSpec;
impl crate::RegisterSpec for Uca1br1SpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca1br1_spi::R`](R) reader structure"]
impl crate::Readable for Uca1br1SpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1br1_spi::W`](W) writer structure"]
impl crate::Writable for Uca1br1SpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1BR1_SPI to value 0"]
impl crate::Resettable for Uca1br1SpiSpec {}
}
#[doc = "UCA1STATW_SPI (rw) register accessor: USCI A1 Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1statw_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1statw_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1statw_spi`] module"]
#[doc(alias = "UCA1STATW_SPI")]
pub type Uca1statwSpi = crate::Reg<uca1statw_spi::Uca1statwSpiSpec>;
#[doc = "USCI A1 Status Register"]
pub mod uca1statw_spi {
#[doc = "Register `UCA1STATW_SPI` reader"]
pub type R = crate::R<Uca1statwSpiSpec>;
#[doc = "Register `UCA1STATW_SPI` writer"]
pub type W = crate::W<Uca1statwSpiSpec>;
#[doc = "Field `UCBUSY` reader - USCI Busy Flag"]
pub type UcbusyR = crate::BitReader;
#[doc = "Field `UCBUSY` writer - USCI Busy Flag"]
pub type UcbusyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOE` reader - USCI Overrun Error Flag"]
pub type UcoeR = crate::BitReader;
#[doc = "Field `UCOE` writer - USCI Overrun Error Flag"]
pub type UcoeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCFE` reader - USCI Frame Error Flag"]
pub type UcfeR = crate::BitReader;
#[doc = "Field `UCFE` writer - USCI Frame Error Flag"]
pub type UcfeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCLISTEN` reader - USCI Listen mode"]
pub type UclistenR = crate::BitReader;
#[doc = "Field `UCLISTEN` writer - USCI Listen mode"]
pub type UclistenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - USCI Busy Flag"]
#[inline(always)]
pub fn ucbusy(&self) -> UcbusyR {
UcbusyR::new((self.bits & 1) != 0)
}
#[doc = "Bit 5 - USCI Overrun Error Flag"]
#[inline(always)]
pub fn ucoe(&self) -> UcoeR {
UcoeR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - USCI Frame Error Flag"]
#[inline(always)]
pub fn ucfe(&self) -> UcfeR {
UcfeR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - USCI Listen mode"]
#[inline(always)]
pub fn uclisten(&self) -> UclistenR {
UclistenR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - USCI Busy Flag"]
#[inline(always)]
pub fn ucbusy(&mut self) -> UcbusyW<'_, Uca1statwSpiSpec> {
UcbusyW::new(self, 0)
}
#[doc = "Bit 5 - USCI Overrun Error Flag"]
#[inline(always)]
pub fn ucoe(&mut self) -> UcoeW<'_, Uca1statwSpiSpec> {
UcoeW::new(self, 5)
}
#[doc = "Bit 6 - USCI Frame Error Flag"]
#[inline(always)]
pub fn ucfe(&mut self) -> UcfeW<'_, Uca1statwSpiSpec> {
UcfeW::new(self, 6)
}
#[doc = "Bit 7 - USCI Listen mode"]
#[inline(always)]
pub fn uclisten(&mut self) -> UclistenW<'_, Uca1statwSpiSpec> {
UclistenW::new(self, 7)
}
}
#[doc = "USCI A1 Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1statw_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1statw_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1statwSpiSpec;
impl crate::RegisterSpec for Uca1statwSpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca1statw_spi::R`](R) reader structure"]
impl crate::Readable for Uca1statwSpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1statw_spi::W`](W) writer structure"]
impl crate::Writable for Uca1statwSpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1STATW_SPI to value 0"]
impl crate::Resettable for Uca1statwSpiSpec {}
}
#[doc = "UCA1IE_SPI (rw) register accessor: USCI A1 Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1ie_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1ie_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1ie_spi`] module"]
#[doc(alias = "UCA1IE_SPI")]
pub type Uca1ieSpi = crate::Reg<uca1ie_spi::Uca1ieSpiSpec>;
#[doc = "USCI A1 Interrupt Enable Register"]
pub mod uca1ie_spi {
#[doc = "Register `UCA1IE_SPI` reader"]
pub type R = crate::R<Uca1ieSpiSpec>;
#[doc = "Register `UCA1IE_SPI` writer"]
pub type W = crate::W<Uca1ieSpiSpec>;
#[doc = "Field `UCRXIE` reader - USCI Receive Interrupt Enable"]
pub type UcrxieR = crate::BitReader;
#[doc = "Field `UCRXIE` writer - USCI Receive Interrupt Enable"]
pub type UcrxieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCTXIE` reader - USCI Transmit Interrupt Enable"]
pub type UctxieR = crate::BitReader;
#[doc = "Field `UCTXIE` writer - USCI Transmit Interrupt Enable"]
pub type UctxieW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - USCI Receive Interrupt Enable"]
#[inline(always)]
pub fn ucrxie(&self) -> UcrxieR {
UcrxieR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - USCI Transmit Interrupt Enable"]
#[inline(always)]
pub fn uctxie(&self) -> UctxieR {
UctxieR::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - USCI Receive Interrupt Enable"]
#[inline(always)]
pub fn ucrxie(&mut self) -> UcrxieW<'_, Uca1ieSpiSpec> {
UcrxieW::new(self, 0)
}
#[doc = "Bit 1 - USCI Transmit Interrupt Enable"]
#[inline(always)]
pub fn uctxie(&mut self) -> UctxieW<'_, Uca1ieSpiSpec> {
UctxieW::new(self, 1)
}
}
#[doc = "USCI A1 Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1ie_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1ie_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1ieSpiSpec;
impl crate::RegisterSpec for Uca1ieSpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca1ie_spi::R`](R) reader structure"]
impl crate::Readable for Uca1ieSpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1ie_spi::W`](W) writer structure"]
impl crate::Writable for Uca1ieSpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1IE_SPI to value 0"]
impl crate::Resettable for Uca1ieSpiSpec {}
}
#[doc = "UCA1IFG_SPI (rw) register accessor: USCI A1 Interrupt Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1ifg_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1ifg_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1ifg_spi`] module"]
#[doc(alias = "UCA1IFG_SPI")]
pub type Uca1ifgSpi = crate::Reg<uca1ifg_spi::Uca1ifgSpiSpec>;
#[doc = "USCI A1 Interrupt Flags Register"]
pub mod uca1ifg_spi {
#[doc = "Register `UCA1IFG_SPI` reader"]
pub type R = crate::R<Uca1ifgSpiSpec>;
#[doc = "Register `UCA1IFG_SPI` writer"]
pub type W = crate::W<Uca1ifgSpiSpec>;
#[doc = "Field `UCRXIFG` reader - SPI Receive Interrupt Flag"]
pub type UcrxifgR = crate::BitReader;
#[doc = "Field `UCRXIFG` writer - SPI Receive Interrupt Flag"]
pub type UcrxifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCTXIFG` reader - SPI Transmit Interrupt Flag"]
pub type UctxifgR = crate::BitReader;
#[doc = "Field `UCTXIFG` writer - SPI Transmit Interrupt Flag"]
pub type UctxifgW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - SPI Receive Interrupt Flag"]
#[inline(always)]
pub fn ucrxifg(&self) -> UcrxifgR {
UcrxifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - SPI Transmit Interrupt Flag"]
#[inline(always)]
pub fn uctxifg(&self) -> UctxifgR {
UctxifgR::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - SPI Receive Interrupt Flag"]
#[inline(always)]
pub fn ucrxifg(&mut self) -> UcrxifgW<'_, Uca1ifgSpiSpec> {
UcrxifgW::new(self, 0)
}
#[doc = "Bit 1 - SPI Transmit Interrupt Flag"]
#[inline(always)]
pub fn uctxifg(&mut self) -> UctxifgW<'_, Uca1ifgSpiSpec> {
UctxifgW::new(self, 1)
}
}
#[doc = "USCI A1 Interrupt Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1ifg_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1ifg_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1ifgSpiSpec;
impl crate::RegisterSpec for Uca1ifgSpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`uca1ifg_spi::R`](R) reader structure"]
impl crate::Readable for Uca1ifgSpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1ifg_spi::W`](W) writer structure"]
impl crate::Writable for Uca1ifgSpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1IFG_SPI to value 0"]
impl crate::Resettable for Uca1ifgSpiSpec {}
}
#[doc = "UCA1RXBUF_SPI (rw) register accessor: USCI A1 Receive Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1rxbuf_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1rxbuf_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1rxbuf_spi`] module"]
#[doc(alias = "UCA1RXBUF_SPI")]
pub type Uca1rxbufSpi = crate::Reg<uca1rxbuf_spi::Uca1rxbufSpiSpec>;
#[doc = "USCI A1 Receive Buffer"]
pub mod uca1rxbuf_spi {
#[doc = "Register `UCA1RXBUF_SPI` reader"]
pub type R = crate::R<Uca1rxbufSpiSpec>;
#[doc = "Register `UCA1RXBUF_SPI` writer"]
pub type W = crate::W<Uca1rxbufSpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A1 Receive Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1rxbuf_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1rxbuf_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1rxbufSpiSpec;
impl crate::RegisterSpec for Uca1rxbufSpiSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`uca1rxbuf_spi::R`](R) reader structure"]
impl crate::Readable for Uca1rxbufSpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1rxbuf_spi::W`](W) writer structure"]
impl crate::Writable for Uca1rxbufSpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1RXBUF_SPI to value 0"]
impl crate::Resettable for Uca1rxbufSpiSpec {}
}
#[doc = "UCA1TXBUF_SPI (rw) register accessor: USCI A1 Transmit Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1txbuf_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1txbuf_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1txbuf_spi`] module"]
#[doc(alias = "UCA1TXBUF_SPI")]
pub type Uca1txbufSpi = crate::Reg<uca1txbuf_spi::Uca1txbufSpiSpec>;
#[doc = "USCI A1 Transmit Buffer"]
pub mod uca1txbuf_spi {
#[doc = "Register `UCA1TXBUF_SPI` reader"]
pub type R = crate::R<Uca1txbufSpiSpec>;
#[doc = "Register `UCA1TXBUF_SPI` writer"]
pub type W = crate::W<Uca1txbufSpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A1 Transmit Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1txbuf_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1txbuf_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1txbufSpiSpec;
impl crate::RegisterSpec for Uca1txbufSpiSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`uca1txbuf_spi::R`](R) reader structure"]
impl crate::Readable for Uca1txbufSpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1txbuf_spi::W`](W) writer structure"]
impl crate::Writable for Uca1txbufSpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1TXBUF_SPI to value 0"]
impl crate::Resettable for Uca1txbufSpiSpec {}
}
#[doc = "UCA1IV_SPI (rw) register accessor: USCI A1 Interrupt Vector Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1iv_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1iv_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uca1iv_spi`] module"]
#[doc(alias = "UCA1IV_SPI")]
pub type Uca1ivSpi = crate::Reg<uca1iv_spi::Uca1ivSpiSpec>;
#[doc = "USCI A1 Interrupt Vector Register"]
pub mod uca1iv_spi {
#[doc = "Register `UCA1IV_SPI` reader"]
pub type R = crate::R<Uca1ivSpiSpec>;
#[doc = "Register `UCA1IV_SPI` writer"]
pub type W = crate::W<Uca1ivSpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI A1 Interrupt Vector Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uca1iv_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uca1iv_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uca1ivSpiSpec;
impl crate::RegisterSpec for Uca1ivSpiSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`uca1iv_spi::R`](R) reader structure"]
impl crate::Readable for Uca1ivSpiSpec {}
#[doc = "`write(|w| ..)` method takes [`uca1iv_spi::W`](W) writer structure"]
impl crate::Writable for Uca1ivSpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCA1IV_SPI to value 0"]
impl crate::Resettable for Uca1ivSpiSpec {}
}
}
#[doc = "USCI_B0 I2C Mode"]
pub type UsciB0I2cMode = crate::Periph<usci_b0_i2c_mode::RegisterBlock, 0x0640>;
impl core::fmt::Debug for UsciB0I2cMode {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UsciB0I2cMode").finish()
}
}
#[doc = "USCI_B0 I2C Mode"]
pub mod usci_b0_i2c_mode {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
ucb0ctl1: Ucb0ctl1,
ucb0ctl0: Ucb0ctl0,
ucb0ctlw1: Ucb0ctlw1,
_reserved3: [u8; 0x02],
ucb0br0: Ucb0br0,
ucb0br1: Ucb0br1,
ucb0stat_i2c: Ucb0statI2c,
ucb0bcnt_i2c: Ucb0bcntI2c,
ucb0tbcnt: Ucb0tbcnt,
ucb0rxbuf: Ucb0rxbuf,
ucb0txbuf: Ucb0txbuf,
_reserved10: [u8; 0x04],
ucb0i2coa0: Ucb0i2coa0,
ucb0i2coa1: Ucb0i2coa1,
ucb0i2coa2: Ucb0i2coa2,
ucb0i2coa3: Ucb0i2coa3,
ucb0addrx: Ucb0addrx,
ucb0addmask: Ucb0addmask,
ucb0i2csa: Ucb0i2csa,
_reserved17: [u8; 0x08],
_reserved_17_ucb0: [u8; 0x02],
_reserved_18_ucb0: [u8; 0x02],
ucb0iv: Ucb0iv,
}
impl RegisterBlock {
#[doc = "0x00 - USCI B0 Control Register 1"]
#[inline(always)]
pub const fn ucb0ctl1(&self) -> &Ucb0ctl1 {
&self.ucb0ctl1
}
#[doc = "0x01 - USCI B0 Control Register 0"]
#[inline(always)]
pub const fn ucb0ctl0(&self) -> &Ucb0ctl0 {
&self.ucb0ctl0
}
#[doc = "0x02 - USCI B0 Control Word Register 1"]
#[inline(always)]
pub const fn ucb0ctlw1(&self) -> &Ucb0ctlw1 {
&self.ucb0ctlw1
}
#[doc = "0x06 - USCI B0 Baud Rate 0"]
#[inline(always)]
pub const fn ucb0br0(&self) -> &Ucb0br0 {
&self.ucb0br0
}
#[doc = "0x07 - USCI B0 Baud Rate 1"]
#[inline(always)]
pub const fn ucb0br1(&self) -> &Ucb0br1 {
&self.ucb0br1
}
#[doc = "0x08 - USCI B0 Status Register"]
#[inline(always)]
pub const fn ucb0stat_i2c(&self) -> &Ucb0statI2c {
&self.ucb0stat_i2c
}
#[doc = "0x09 - USCI B0 Byte Counter Register"]
#[inline(always)]
pub const fn ucb0bcnt_i2c(&self) -> &Ucb0bcntI2c {
&self.ucb0bcnt_i2c
}
#[doc = "0x0a - USCI B0 Byte Counter Threshold Register"]
#[inline(always)]
pub const fn ucb0tbcnt(&self) -> &Ucb0tbcnt {
&self.ucb0tbcnt
}
#[doc = "0x0c - USCI B0 Receive Buffer"]
#[inline(always)]
pub const fn ucb0rxbuf(&self) -> &Ucb0rxbuf {
&self.ucb0rxbuf
}
#[doc = "0x0e - USCI B0 Transmit Buffer"]
#[inline(always)]
pub const fn ucb0txbuf(&self) -> &Ucb0txbuf {
&self.ucb0txbuf
}
#[doc = "0x14 - USCI B0 I2C Own Address 0"]
#[inline(always)]
pub const fn ucb0i2coa0(&self) -> &Ucb0i2coa0 {
&self.ucb0i2coa0
}
#[doc = "0x16 - USCI B0 I2C Own Address 1"]
#[inline(always)]
pub const fn ucb0i2coa1(&self) -> &Ucb0i2coa1 {
&self.ucb0i2coa1
}
#[doc = "0x18 - USCI B0 I2C Own Address 2"]
#[inline(always)]
pub const fn ucb0i2coa2(&self) -> &Ucb0i2coa2 {
&self.ucb0i2coa2
}
#[doc = "0x1a - USCI B0 I2C Own Address 3"]
#[inline(always)]
pub const fn ucb0i2coa3(&self) -> &Ucb0i2coa3 {
&self.ucb0i2coa3
}
#[doc = "0x1c - USCI B0 Received Address Register"]
#[inline(always)]
pub const fn ucb0addrx(&self) -> &Ucb0addrx {
&self.ucb0addrx
}
#[doc = "0x1e - USCI B0 Address Mask Register"]
#[inline(always)]
pub const fn ucb0addmask(&self) -> &Ucb0addmask {
&self.ucb0addmask
}
#[doc = "0x20 - USCI B0 I2C Slave Address"]
#[inline(always)]
pub const fn ucb0i2csa(&self) -> &Ucb0i2csa {
&self.ucb0i2csa
}
#[doc = "0x2a - USCI B0 Interrupt Enable Register"]
#[inline(always)]
pub const fn ucb0ie_i2c(&self) -> &Ucb0ieI2c {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(42).cast() }
}
#[doc = "0x2a - USCI B0 Interrupt Enable Register"]
#[inline(always)]
pub const fn ucb0ie(&self) -> &Ucb0ie {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(42).cast() }
}
#[doc = "0x2c - USCI B0 Interrupt Flags Register"]
#[inline(always)]
pub const fn ucb0ifg_i2c(&self) -> &Ucb0ifgI2c {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).cast() }
}
#[doc = "0x2c - USCI B0 Interrupt Flags Register"]
#[inline(always)]
pub const fn ucb0ifg(&self) -> &Ucb0ifg {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).cast() }
}
#[doc = "0x2e - USCI B0 Interrupt Vector Register"]
#[inline(always)]
pub const fn ucb0iv(&self) -> &Ucb0iv {
&self.ucb0iv
}
}
#[doc = "UCB0CTL1 (rw) register accessor: USCI B0 Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ctl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ctl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0ctl1`] module"]
#[doc(alias = "UCB0CTL1")]
pub type Ucb0ctl1 = crate::Reg<ucb0ctl1::Ucb0ctl1Spec>;
#[doc = "USCI B0 Control Register 1"]
pub mod ucb0ctl1 {
#[doc = "Register `UCB0CTL1` reader"]
pub type R = crate::R<Ucb0ctl1Spec>;
#[doc = "Register `UCB0CTL1` writer"]
pub type W = crate::W<Ucb0ctl1Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI B0 Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0ctl1Spec;
impl crate::RegisterSpec for Ucb0ctl1Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`ucb0ctl1::R`](R) reader structure"]
impl crate::Readable for Ucb0ctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`ucb0ctl1::W`](W) writer structure"]
impl crate::Writable for Ucb0ctl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0CTL1 to value 0"]
impl crate::Resettable for Ucb0ctl1Spec {}
}
#[doc = "UCB0CTL0 (rw) register accessor: USCI B0 Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0ctl0`] module"]
#[doc(alias = "UCB0CTL0")]
pub type Ucb0ctl0 = crate::Reg<ucb0ctl0::Ucb0ctl0Spec>;
#[doc = "USCI B0 Control Register 0"]
pub mod ucb0ctl0 {
#[doc = "Register `UCB0CTL0` reader"]
pub type R = crate::R<Ucb0ctl0Spec>;
#[doc = "Register `UCB0CTL0` writer"]
pub type W = crate::W<Ucb0ctl0Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI B0 Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0ctl0Spec;
impl crate::RegisterSpec for Ucb0ctl0Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`ucb0ctl0::R`](R) reader structure"]
impl crate::Readable for Ucb0ctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`ucb0ctl0::W`](W) writer structure"]
impl crate::Writable for Ucb0ctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0CTL0 to value 0"]
impl crate::Resettable for Ucb0ctl0Spec {}
}
#[doc = "UCB0BR0 (rw) register accessor: USCI B0 Baud Rate 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0br0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0br0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0br0`] module"]
#[doc(alias = "UCB0BR0")]
pub type Ucb0br0 = crate::Reg<ucb0br0::Ucb0br0Spec>;
#[doc = "USCI B0 Baud Rate 0"]
pub mod ucb0br0 {
#[doc = "Register `UCB0BR0` reader"]
pub type R = crate::R<Ucb0br0Spec>;
#[doc = "Register `UCB0BR0` writer"]
pub type W = crate::W<Ucb0br0Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI B0 Baud Rate 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0br0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0br0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0br0Spec;
impl crate::RegisterSpec for Ucb0br0Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`ucb0br0::R`](R) reader structure"]
impl crate::Readable for Ucb0br0Spec {}
#[doc = "`write(|w| ..)` method takes [`ucb0br0::W`](W) writer structure"]
impl crate::Writable for Ucb0br0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0BR0 to value 0"]
impl crate::Resettable for Ucb0br0Spec {}
}
#[doc = "UCB0BR1 (rw) register accessor: USCI B0 Baud Rate 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0br1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0br1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0br1`] module"]
#[doc(alias = "UCB0BR1")]
pub type Ucb0br1 = crate::Reg<ucb0br1::Ucb0br1Spec>;
#[doc = "USCI B0 Baud Rate 1"]
pub mod ucb0br1 {
#[doc = "Register `UCB0BR1` reader"]
pub type R = crate::R<Ucb0br1Spec>;
#[doc = "Register `UCB0BR1` writer"]
pub type W = crate::W<Ucb0br1Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI B0 Baud Rate 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0br1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0br1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0br1Spec;
impl crate::RegisterSpec for Ucb0br1Spec {
type Ux = u8;
}
#[doc = "`read()` method returns [`ucb0br1::R`](R) reader structure"]
impl crate::Readable for Ucb0br1Spec {}
#[doc = "`write(|w| ..)` method takes [`ucb0br1::W`](W) writer structure"]
impl crate::Writable for Ucb0br1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0BR1 to value 0"]
impl crate::Resettable for Ucb0br1Spec {}
}
#[doc = "UCB0STAT_I2C (rw) register accessor: USCI B0 Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0stat_i2c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0stat_i2c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0stat_i2c`] module"]
#[doc(alias = "UCB0STAT_I2C")]
pub type Ucb0statI2c = crate::Reg<ucb0stat_i2c::Ucb0statI2cSpec>;
#[doc = "USCI B0 Status Register"]
pub mod ucb0stat_i2c {
#[doc = "Register `UCB0STAT_I2C` reader"]
pub type R = crate::R<Ucb0statI2cSpec>;
#[doc = "Register `UCB0STAT_I2C` writer"]
pub type W = crate::W<Ucb0statI2cSpec>;
#[doc = "Field `UCBBUSY` reader - Bus Busy Flag"]
pub type UcbbusyR = crate::BitReader;
#[doc = "Field `UCBBUSY` writer - Bus Busy Flag"]
pub type UcbbusyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCGC` reader - General Call address received Flag"]
pub type UcgcR = crate::BitReader;
#[doc = "Field `UCGC` writer - General Call address received Flag"]
pub type UcgcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCSCLLOW` reader - SCL low"]
pub type UcscllowR = crate::BitReader;
#[doc = "Field `UCSCLLOW` writer - SCL low"]
pub type UcscllowW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 4 - Bus Busy Flag"]
#[inline(always)]
pub fn ucbbusy(&self) -> UcbbusyR {
UcbbusyR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - General Call address received Flag"]
#[inline(always)]
pub fn ucgc(&self) -> UcgcR {
UcgcR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - SCL low"]
#[inline(always)]
pub fn ucscllow(&self) -> UcscllowR {
UcscllowR::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 4 - Bus Busy Flag"]
#[inline(always)]
pub fn ucbbusy(&mut self) -> UcbbusyW<'_, Ucb0statI2cSpec> {
UcbbusyW::new(self, 4)
}
#[doc = "Bit 5 - General Call address received Flag"]
#[inline(always)]
pub fn ucgc(&mut self) -> UcgcW<'_, Ucb0statI2cSpec> {
UcgcW::new(self, 5)
}
#[doc = "Bit 6 - SCL low"]
#[inline(always)]
pub fn ucscllow(&mut self) -> UcscllowW<'_, Ucb0statI2cSpec> {
UcscllowW::new(self, 6)
}
}
#[doc = "USCI B0 Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0stat_i2c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0stat_i2c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0statI2cSpec;
impl crate::RegisterSpec for Ucb0statI2cSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`ucb0stat_i2c::R`](R) reader structure"]
impl crate::Readable for Ucb0statI2cSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0stat_i2c::W`](W) writer structure"]
impl crate::Writable for Ucb0statI2cSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0STAT_I2C to value 0"]
impl crate::Resettable for Ucb0statI2cSpec {}
}
#[doc = "UCB0BCNT_I2C (rw) register accessor: USCI B0 Byte Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0bcnt_i2c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0bcnt_i2c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0bcnt_i2c`] module"]
#[doc(alias = "UCB0BCNT_I2C")]
pub type Ucb0bcntI2c = crate::Reg<ucb0bcnt_i2c::Ucb0bcntI2cSpec>;
#[doc = "USCI B0 Byte Counter Register"]
pub mod ucb0bcnt_i2c {
#[doc = "Register `UCB0BCNT_I2C` reader"]
pub type R = crate::R<Ucb0bcntI2cSpec>;
#[doc = "Register `UCB0BCNT_I2C` writer"]
pub type W = crate::W<Ucb0bcntI2cSpec>;
#[doc = "Field `UCBCNT0` reader - USCI Byte Counter Bit 0"]
pub type Ucbcnt0R = crate::BitReader;
#[doc = "Field `UCBCNT0` writer - USCI Byte Counter Bit 0"]
pub type Ucbcnt0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBCNT1` reader - USCI Byte Counter Bit 1"]
pub type Ucbcnt1R = crate::BitReader;
#[doc = "Field `UCBCNT1` writer - USCI Byte Counter Bit 1"]
pub type Ucbcnt1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBCNT2` reader - USCI Byte Counter Bit 2"]
pub type Ucbcnt2R = crate::BitReader;
#[doc = "Field `UCBCNT2` writer - USCI Byte Counter Bit 2"]
pub type Ucbcnt2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBCNT3` reader - USCI Byte Counter Bit 3"]
pub type Ucbcnt3R = crate::BitReader;
#[doc = "Field `UCBCNT3` writer - USCI Byte Counter Bit 3"]
pub type Ucbcnt3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBCNT4` reader - USCI Byte Counter Bit 4"]
pub type Ucbcnt4R = crate::BitReader;
#[doc = "Field `UCBCNT4` writer - USCI Byte Counter Bit 4"]
pub type Ucbcnt4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBCNT5` reader - USCI Byte Counter Bit 5"]
pub type Ucbcnt5R = crate::BitReader;
#[doc = "Field `UCBCNT5` writer - USCI Byte Counter Bit 5"]
pub type Ucbcnt5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBCNT6` reader - USCI Byte Counter Bit 6"]
pub type Ucbcnt6R = crate::BitReader;
#[doc = "Field `UCBCNT6` writer - USCI Byte Counter Bit 6"]
pub type Ucbcnt6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBCNT7` reader - USCI Byte Counter Bit 7"]
pub type Ucbcnt7R = crate::BitReader;
#[doc = "Field `UCBCNT7` writer - USCI Byte Counter Bit 7"]
pub type Ucbcnt7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - USCI Byte Counter Bit 0"]
#[inline(always)]
pub fn ucbcnt0(&self) -> Ucbcnt0R {
Ucbcnt0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - USCI Byte Counter Bit 1"]
#[inline(always)]
pub fn ucbcnt1(&self) -> Ucbcnt1R {
Ucbcnt1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - USCI Byte Counter Bit 2"]
#[inline(always)]
pub fn ucbcnt2(&self) -> Ucbcnt2R {
Ucbcnt2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - USCI Byte Counter Bit 3"]
#[inline(always)]
pub fn ucbcnt3(&self) -> Ucbcnt3R {
Ucbcnt3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - USCI Byte Counter Bit 4"]
#[inline(always)]
pub fn ucbcnt4(&self) -> Ucbcnt4R {
Ucbcnt4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - USCI Byte Counter Bit 5"]
#[inline(always)]
pub fn ucbcnt5(&self) -> Ucbcnt5R {
Ucbcnt5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - USCI Byte Counter Bit 6"]
#[inline(always)]
pub fn ucbcnt6(&self) -> Ucbcnt6R {
Ucbcnt6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - USCI Byte Counter Bit 7"]
#[inline(always)]
pub fn ucbcnt7(&self) -> Ucbcnt7R {
Ucbcnt7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - USCI Byte Counter Bit 0"]
#[inline(always)]
pub fn ucbcnt0(&mut self) -> Ucbcnt0W<'_, Ucb0bcntI2cSpec> {
Ucbcnt0W::new(self, 0)
}
#[doc = "Bit 1 - USCI Byte Counter Bit 1"]
#[inline(always)]
pub fn ucbcnt1(&mut self) -> Ucbcnt1W<'_, Ucb0bcntI2cSpec> {
Ucbcnt1W::new(self, 1)
}
#[doc = "Bit 2 - USCI Byte Counter Bit 2"]
#[inline(always)]
pub fn ucbcnt2(&mut self) -> Ucbcnt2W<'_, Ucb0bcntI2cSpec> {
Ucbcnt2W::new(self, 2)
}
#[doc = "Bit 3 - USCI Byte Counter Bit 3"]
#[inline(always)]
pub fn ucbcnt3(&mut self) -> Ucbcnt3W<'_, Ucb0bcntI2cSpec> {
Ucbcnt3W::new(self, 3)
}
#[doc = "Bit 4 - USCI Byte Counter Bit 4"]
#[inline(always)]
pub fn ucbcnt4(&mut self) -> Ucbcnt4W<'_, Ucb0bcntI2cSpec> {
Ucbcnt4W::new(self, 4)
}
#[doc = "Bit 5 - USCI Byte Counter Bit 5"]
#[inline(always)]
pub fn ucbcnt5(&mut self) -> Ucbcnt5W<'_, Ucb0bcntI2cSpec> {
Ucbcnt5W::new(self, 5)
}
#[doc = "Bit 6 - USCI Byte Counter Bit 6"]
#[inline(always)]
pub fn ucbcnt6(&mut self) -> Ucbcnt6W<'_, Ucb0bcntI2cSpec> {
Ucbcnt6W::new(self, 6)
}
#[doc = "Bit 7 - USCI Byte Counter Bit 7"]
#[inline(always)]
pub fn ucbcnt7(&mut self) -> Ucbcnt7W<'_, Ucb0bcntI2cSpec> {
Ucbcnt7W::new(self, 7)
}
}
#[doc = "USCI B0 Byte Counter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0bcnt_i2c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0bcnt_i2c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0bcntI2cSpec;
impl crate::RegisterSpec for Ucb0bcntI2cSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`ucb0bcnt_i2c::R`](R) reader structure"]
impl crate::Readable for Ucb0bcntI2cSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0bcnt_i2c::W`](W) writer structure"]
impl crate::Writable for Ucb0bcntI2cSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets UCB0BCNT_I2C to value 0"]
impl crate::Resettable for Ucb0bcntI2cSpec {}
}
#[doc = "UCB0CTLW1 (rw) register accessor: USCI B0 Control Word Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ctlw1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ctlw1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0ctlw1`] module"]
#[doc(alias = "UCB0CTLW1")]
pub type Ucb0ctlw1 = crate::Reg<ucb0ctlw1::Ucb0ctlw1Spec>;
#[doc = "USCI B0 Control Word Register 1"]
pub mod ucb0ctlw1 {
#[doc = "Register `UCB0CTLW1` reader"]
pub type R = crate::R<Ucb0ctlw1Spec>;
#[doc = "Register `UCB0CTLW1` writer"]
pub type W = crate::W<Ucb0ctlw1Spec>;
#[doc = "USCI Deglitch time Bit: 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ucglit {
#[doc = "0: USCI Deglitch time: 0"]
Ucglit0 = 0,
#[doc = "1: USCI Deglitch time: 1"]
Ucglit1 = 1,
#[doc = "2: USCI Deglitch time: 2"]
Ucglit2 = 2,
#[doc = "3: USCI Deglitch time: 3"]
Ucglit3 = 3,
}
impl From<Ucglit> for u8 {
#[inline(always)]
fn from(variant: Ucglit) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ucglit {
type Ux = u8;
}
impl crate::IsEnum for Ucglit {}
#[doc = "Field `UCGLIT` reader - USCI Deglitch time Bit: 1"]
pub type UcglitR = crate::FieldReader<Ucglit>;
impl UcglitR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ucglit {
match self.bits {
0 => Ucglit::Ucglit0,
1 => Ucglit::Ucglit1,
2 => Ucglit::Ucglit2,
3 => Ucglit::Ucglit3,
_ => unreachable!(),
}
}
#[doc = "USCI Deglitch time: 0"]
#[inline(always)]
pub fn is_ucglit_0(&self) -> bool {
*self == Ucglit::Ucglit0
}
#[doc = "USCI Deglitch time: 1"]
#[inline(always)]
pub fn is_ucglit_1(&self) -> bool {
*self == Ucglit::Ucglit1
}
#[doc = "USCI Deglitch time: 2"]
#[inline(always)]
pub fn is_ucglit_2(&self) -> bool {
*self == Ucglit::Ucglit2
}
#[doc = "USCI Deglitch time: 3"]
#[inline(always)]
pub fn is_ucglit_3(&self) -> bool {
*self == Ucglit::Ucglit3
}
}
#[doc = "Field `UCGLIT` writer - USCI Deglitch time Bit: 1"]
pub type UcglitW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ucglit, crate::Safe>;
impl<'a, REG> UcglitW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "USCI Deglitch time: 0"]
#[inline(always)]
pub fn ucglit_0(self) -> &'a mut crate::W<REG> {
self.variant(Ucglit::Ucglit0)
}
#[doc = "USCI Deglitch time: 1"]
#[inline(always)]
pub fn ucglit_1(self) -> &'a mut crate::W<REG> {
self.variant(Ucglit::Ucglit1)
}
#[doc = "USCI Deglitch time: 2"]
#[inline(always)]
pub fn ucglit_2(self) -> &'a mut crate::W<REG> {
self.variant(Ucglit::Ucglit2)
}
#[doc = "USCI Deglitch time: 3"]
#[inline(always)]
pub fn ucglit_3(self) -> &'a mut crate::W<REG> {
self.variant(Ucglit::Ucglit3)
}
}
#[doc = "USCI Automatic Stop condition generation Bit: 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ucastp {
#[doc = "0: USCI Automatic Stop condition generation: 0"]
Ucastp0 = 0,
#[doc = "1: USCI Automatic Stop condition generation: 1"]
Ucastp1 = 1,
#[doc = "2: USCI Automatic Stop condition generation: 2"]
Ucastp2 = 2,
#[doc = "3: USCI Automatic Stop condition generation: 3"]
Ucastp3 = 3,
}
impl From<Ucastp> for u8 {
#[inline(always)]
fn from(variant: Ucastp) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ucastp {
type Ux = u8;
}
impl crate::IsEnum for Ucastp {}
#[doc = "Field `UCASTP` reader - USCI Automatic Stop condition generation Bit: 1"]
pub type UcastpR = crate::FieldReader<Ucastp>;
impl UcastpR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ucastp {
match self.bits {
0 => Ucastp::Ucastp0,
1 => Ucastp::Ucastp1,
2 => Ucastp::Ucastp2,
3 => Ucastp::Ucastp3,
_ => unreachable!(),
}
}
#[doc = "USCI Automatic Stop condition generation: 0"]
#[inline(always)]
pub fn is_ucastp_0(&self) -> bool {
*self == Ucastp::Ucastp0
}
#[doc = "USCI Automatic Stop condition generation: 1"]
#[inline(always)]
pub fn is_ucastp_1(&self) -> bool {
*self == Ucastp::Ucastp1
}
#[doc = "USCI Automatic Stop condition generation: 2"]
#[inline(always)]
pub fn is_ucastp_2(&self) -> bool {
*self == Ucastp::Ucastp2
}
#[doc = "USCI Automatic Stop condition generation: 3"]
#[inline(always)]
pub fn is_ucastp_3(&self) -> bool {
*self == Ucastp::Ucastp3
}
}
#[doc = "Field `UCASTP` writer - USCI Automatic Stop condition generation Bit: 1"]
pub type UcastpW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ucastp, crate::Safe>;
impl<'a, REG> UcastpW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "USCI Automatic Stop condition generation: 0"]
#[inline(always)]
pub fn ucastp_0(self) -> &'a mut crate::W<REG> {
self.variant(Ucastp::Ucastp0)
}
#[doc = "USCI Automatic Stop condition generation: 1"]
#[inline(always)]
pub fn ucastp_1(self) -> &'a mut crate::W<REG> {
self.variant(Ucastp::Ucastp1)
}
#[doc = "USCI Automatic Stop condition generation: 2"]
#[inline(always)]
pub fn ucastp_2(self) -> &'a mut crate::W<REG> {
self.variant(Ucastp::Ucastp2)
}
#[doc = "USCI Automatic Stop condition generation: 3"]
#[inline(always)]
pub fn ucastp_3(self) -> &'a mut crate::W<REG> {
self.variant(Ucastp::Ucastp3)
}
}
#[doc = "Field `UCSWACK` reader - USCI Software controlled ACK"]
pub type UcswackR = crate::BitReader;
#[doc = "Field `UCSWACK` writer - USCI Software controlled ACK"]
pub type UcswackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCSTPNACK` reader - USCI Acknowledge Stop last byte"]
pub type UcstpnackR = crate::BitReader;
#[doc = "Field `UCSTPNACK` writer - USCI Acknowledge Stop last byte"]
pub type UcstpnackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "USCI Clock low timeout Bit: 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ucclto {
#[doc = "0: USCI Clock low timeout: 0"]
Ucclto0 = 0,
#[doc = "1: USCI Clock low timeout: 1"]
Ucclto1 = 1,
#[doc = "2: USCI Clock low timeout: 2"]
Ucclto2 = 2,
#[doc = "3: USCI Clock low timeout: 3"]
Ucclto3 = 3,
}
impl From<Ucclto> for u8 {
#[inline(always)]
fn from(variant: Ucclto) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ucclto {
type Ux = u8;
}
impl crate::IsEnum for Ucclto {}
#[doc = "Field `UCCLTO` reader - USCI Clock low timeout Bit: 1"]
pub type UccltoR = crate::FieldReader<Ucclto>;
impl UccltoR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ucclto {
match self.bits {
0 => Ucclto::Ucclto0,
1 => Ucclto::Ucclto1,
2 => Ucclto::Ucclto2,
3 => Ucclto::Ucclto3,
_ => unreachable!(),
}
}
#[doc = "USCI Clock low timeout: 0"]
#[inline(always)]
pub fn is_ucclto_0(&self) -> bool {
*self == Ucclto::Ucclto0
}
#[doc = "USCI Clock low timeout: 1"]
#[inline(always)]
pub fn is_ucclto_1(&self) -> bool {
*self == Ucclto::Ucclto1
}
#[doc = "USCI Clock low timeout: 2"]
#[inline(always)]
pub fn is_ucclto_2(&self) -> bool {
*self == Ucclto::Ucclto2
}
#[doc = "USCI Clock low timeout: 3"]
#[inline(always)]
pub fn is_ucclto_3(&self) -> bool {
*self == Ucclto::Ucclto3
}
}
#[doc = "Field `UCCLTO` writer - USCI Clock low timeout Bit: 1"]
pub type UccltoW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ucclto, crate::Safe>;
impl<'a, REG> UccltoW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "USCI Clock low timeout: 0"]
#[inline(always)]
pub fn ucclto_0(self) -> &'a mut crate::W<REG> {
self.variant(Ucclto::Ucclto0)
}
#[doc = "USCI Clock low timeout: 1"]
#[inline(always)]
pub fn ucclto_1(self) -> &'a mut crate::W<REG> {
self.variant(Ucclto::Ucclto1)
}
#[doc = "USCI Clock low timeout: 2"]
#[inline(always)]
pub fn ucclto_2(self) -> &'a mut crate::W<REG> {
self.variant(Ucclto::Ucclto2)
}
#[doc = "USCI Clock low timeout: 3"]
#[inline(always)]
pub fn ucclto_3(self) -> &'a mut crate::W<REG> {
self.variant(Ucclto::Ucclto3)
}
}
#[doc = "Field `UCETXINT` reader - USCI Early UCTXIFG0"]
pub type UcetxintR = crate::BitReader;
#[doc = "Field `UCETXINT` writer - USCI Early UCTXIFG0"]
pub type UcetxintW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - USCI Deglitch time Bit: 1"]
#[inline(always)]
pub fn ucglit(&self) -> UcglitR {
UcglitR::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3 - USCI Automatic Stop condition generation Bit: 1"]
#[inline(always)]
pub fn ucastp(&self) -> UcastpR {
UcastpR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bit 4 - USCI Software controlled ACK"]
#[inline(always)]
pub fn ucswack(&self) -> UcswackR {
UcswackR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - USCI Acknowledge Stop last byte"]
#[inline(always)]
pub fn ucstpnack(&self) -> UcstpnackR {
UcstpnackR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:7 - USCI Clock low timeout Bit: 1"]
#[inline(always)]
pub fn ucclto(&self) -> UccltoR {
UccltoR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bit 8 - USCI Early UCTXIFG0"]
#[inline(always)]
pub fn ucetxint(&self) -> UcetxintR {
UcetxintR::new(((self.bits >> 8) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - USCI Deglitch time Bit: 1"]
#[inline(always)]
pub fn ucglit(&mut self) -> UcglitW<'_, Ucb0ctlw1Spec> {
UcglitW::new(self, 0)
}
#[doc = "Bits 2:3 - USCI Automatic Stop condition generation Bit: 1"]
#[inline(always)]
pub fn ucastp(&mut self) -> UcastpW<'_, Ucb0ctlw1Spec> {
UcastpW::new(self, 2)
}
#[doc = "Bit 4 - USCI Software controlled ACK"]
#[inline(always)]
pub fn ucswack(&mut self) -> UcswackW<'_, Ucb0ctlw1Spec> {
UcswackW::new(self, 4)
}
#[doc = "Bit 5 - USCI Acknowledge Stop last byte"]
#[inline(always)]
pub fn ucstpnack(&mut self) -> UcstpnackW<'_, Ucb0ctlw1Spec> {
UcstpnackW::new(self, 5)
}
#[doc = "Bits 6:7 - USCI Clock low timeout Bit: 1"]
#[inline(always)]
pub fn ucclto(&mut self) -> UccltoW<'_, Ucb0ctlw1Spec> {
UccltoW::new(self, 6)
}
#[doc = "Bit 8 - USCI Early UCTXIFG0"]
#[inline(always)]
pub fn ucetxint(&mut self) -> UcetxintW<'_, Ucb0ctlw1Spec> {
UcetxintW::new(self, 8)
}
}
#[doc = "USCI B0 Control Word Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ctlw1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ctlw1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0ctlw1Spec;
impl crate::RegisterSpec for Ucb0ctlw1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0ctlw1::R`](R) reader structure"]
impl crate::Readable for Ucb0ctlw1Spec {}
#[doc = "`write(|w| ..)` method takes [`ucb0ctlw1::W`](W) writer structure"]
impl crate::Writable for Ucb0ctlw1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0CTLW1 to value 0"]
impl crate::Resettable for Ucb0ctlw1Spec {}
}
#[doc = "UCB0TBCNT (rw) register accessor: USCI B0 Byte Counter Threshold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0tbcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0tbcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0tbcnt`] module"]
#[doc(alias = "UCB0TBCNT")]
pub type Ucb0tbcnt = crate::Reg<ucb0tbcnt::Ucb0tbcntSpec>;
#[doc = "USCI B0 Byte Counter Threshold Register"]
pub mod ucb0tbcnt {
#[doc = "Register `UCB0TBCNT` reader"]
pub type R = crate::R<Ucb0tbcntSpec>;
#[doc = "Register `UCB0TBCNT` writer"]
pub type W = crate::W<Ucb0tbcntSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI B0 Byte Counter Threshold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0tbcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0tbcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0tbcntSpec;
impl crate::RegisterSpec for Ucb0tbcntSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0tbcnt::R`](R) reader structure"]
impl crate::Readable for Ucb0tbcntSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0tbcnt::W`](W) writer structure"]
impl crate::Writable for Ucb0tbcntSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0TBCNT to value 0"]
impl crate::Resettable for Ucb0tbcntSpec {}
}
#[doc = "UCB0RXBUF (rw) register accessor: USCI B0 Receive Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0rxbuf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0rxbuf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0rxbuf`] module"]
#[doc(alias = "UCB0RXBUF")]
pub type Ucb0rxbuf = crate::Reg<ucb0rxbuf::Ucb0rxbufSpec>;
#[doc = "USCI B0 Receive Buffer"]
pub mod ucb0rxbuf {
#[doc = "Register `UCB0RXBUF` reader"]
pub type R = crate::R<Ucb0rxbufSpec>;
#[doc = "Register `UCB0RXBUF` writer"]
pub type W = crate::W<Ucb0rxbufSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI B0 Receive Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0rxbuf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0rxbuf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0rxbufSpec;
impl crate::RegisterSpec for Ucb0rxbufSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0rxbuf::R`](R) reader structure"]
impl crate::Readable for Ucb0rxbufSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0rxbuf::W`](W) writer structure"]
impl crate::Writable for Ucb0rxbufSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0RXBUF to value 0"]
impl crate::Resettable for Ucb0rxbufSpec {}
}
#[doc = "UCB0TXBUF (rw) register accessor: USCI B0 Transmit Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0txbuf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0txbuf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0txbuf`] module"]
#[doc(alias = "UCB0TXBUF")]
pub type Ucb0txbuf = crate::Reg<ucb0txbuf::Ucb0txbufSpec>;
#[doc = "USCI B0 Transmit Buffer"]
pub mod ucb0txbuf {
#[doc = "Register `UCB0TXBUF` reader"]
pub type R = crate::R<Ucb0txbufSpec>;
#[doc = "Register `UCB0TXBUF` writer"]
pub type W = crate::W<Ucb0txbufSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI B0 Transmit Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0txbuf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0txbuf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0txbufSpec;
impl crate::RegisterSpec for Ucb0txbufSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0txbuf::R`](R) reader structure"]
impl crate::Readable for Ucb0txbufSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0txbuf::W`](W) writer structure"]
impl crate::Writable for Ucb0txbufSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0TXBUF to value 0"]
impl crate::Resettable for Ucb0txbufSpec {}
}
#[doc = "UCB0I2COA0 (rw) register accessor: USCI B0 I2C Own Address 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0i2coa0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0i2coa0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0i2coa0`] module"]
#[doc(alias = "UCB0I2COA0")]
pub type Ucb0i2coa0 = crate::Reg<ucb0i2coa0::Ucb0i2coa0Spec>;
#[doc = "USCI B0 I2C Own Address 0"]
pub mod ucb0i2coa0 {
#[doc = "Register `UCB0I2COA0` reader"]
pub type R = crate::R<Ucb0i2coa0Spec>;
#[doc = "Register `UCB0I2COA0` writer"]
pub type W = crate::W<Ucb0i2coa0Spec>;
#[doc = "Field `UCOA0` reader - I2C Own Address Bit 0"]
pub type Ucoa0R = crate::BitReader;
#[doc = "Field `UCOA0` writer - I2C Own Address Bit 0"]
pub type Ucoa0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA1` reader - I2C Own Address Bit 1"]
pub type Ucoa1R = crate::BitReader;
#[doc = "Field `UCOA1` writer - I2C Own Address Bit 1"]
pub type Ucoa1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA2` reader - I2C Own Address Bit 2"]
pub type Ucoa2R = crate::BitReader;
#[doc = "Field `UCOA2` writer - I2C Own Address Bit 2"]
pub type Ucoa2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA3` reader - I2C Own Address Bit 3"]
pub type Ucoa3R = crate::BitReader;
#[doc = "Field `UCOA3` writer - I2C Own Address Bit 3"]
pub type Ucoa3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA4` reader - I2C Own Address Bit 4"]
pub type Ucoa4R = crate::BitReader;
#[doc = "Field `UCOA4` writer - I2C Own Address Bit 4"]
pub type Ucoa4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA5` reader - I2C Own Address Bit 5"]
pub type Ucoa5R = crate::BitReader;
#[doc = "Field `UCOA5` writer - I2C Own Address Bit 5"]
pub type Ucoa5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA6` reader - I2C Own Address Bit 6"]
pub type Ucoa6R = crate::BitReader;
#[doc = "Field `UCOA6` writer - I2C Own Address Bit 6"]
pub type Ucoa6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA7` reader - I2C Own Address Bit 7"]
pub type Ucoa7R = crate::BitReader;
#[doc = "Field `UCOA7` writer - I2C Own Address Bit 7"]
pub type Ucoa7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA8` reader - I2C Own Address Bit 8"]
pub type Ucoa8R = crate::BitReader;
#[doc = "Field `UCOA8` writer - I2C Own Address Bit 8"]
pub type Ucoa8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA9` reader - I2C Own Address Bit 9"]
pub type Ucoa9R = crate::BitReader;
#[doc = "Field `UCOA9` writer - I2C Own Address Bit 9"]
pub type Ucoa9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOAEN` reader - I2C Own Address enable"]
pub type UcoaenR = crate::BitReader;
#[doc = "Field `UCOAEN` writer - I2C Own Address enable"]
pub type UcoaenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCGCEN` reader - I2C General Call enable"]
pub type UcgcenR = crate::BitReader;
#[doc = "Field `UCGCEN` writer - I2C General Call enable"]
pub type UcgcenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - I2C Own Address Bit 0"]
#[inline(always)]
pub fn ucoa0(&self) -> Ucoa0R {
Ucoa0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - I2C Own Address Bit 1"]
#[inline(always)]
pub fn ucoa1(&self) -> Ucoa1R {
Ucoa1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - I2C Own Address Bit 2"]
#[inline(always)]
pub fn ucoa2(&self) -> Ucoa2R {
Ucoa2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - I2C Own Address Bit 3"]
#[inline(always)]
pub fn ucoa3(&self) -> Ucoa3R {
Ucoa3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - I2C Own Address Bit 4"]
#[inline(always)]
pub fn ucoa4(&self) -> Ucoa4R {
Ucoa4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - I2C Own Address Bit 5"]
#[inline(always)]
pub fn ucoa5(&self) -> Ucoa5R {
Ucoa5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - I2C Own Address Bit 6"]
#[inline(always)]
pub fn ucoa6(&self) -> Ucoa6R {
Ucoa6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - I2C Own Address Bit 7"]
#[inline(always)]
pub fn ucoa7(&self) -> Ucoa7R {
Ucoa7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - I2C Own Address Bit 8"]
#[inline(always)]
pub fn ucoa8(&self) -> Ucoa8R {
Ucoa8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - I2C Own Address Bit 9"]
#[inline(always)]
pub fn ucoa9(&self) -> Ucoa9R {
Ucoa9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - I2C Own Address enable"]
#[inline(always)]
pub fn ucoaen(&self) -> UcoaenR {
UcoaenR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 15 - I2C General Call enable"]
#[inline(always)]
pub fn ucgcen(&self) -> UcgcenR {
UcgcenR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - I2C Own Address Bit 0"]
#[inline(always)]
pub fn ucoa0(&mut self) -> Ucoa0W<'_, Ucb0i2coa0Spec> {
Ucoa0W::new(self, 0)
}
#[doc = "Bit 1 - I2C Own Address Bit 1"]
#[inline(always)]
pub fn ucoa1(&mut self) -> Ucoa1W<'_, Ucb0i2coa0Spec> {
Ucoa1W::new(self, 1)
}
#[doc = "Bit 2 - I2C Own Address Bit 2"]
#[inline(always)]
pub fn ucoa2(&mut self) -> Ucoa2W<'_, Ucb0i2coa0Spec> {
Ucoa2W::new(self, 2)
}
#[doc = "Bit 3 - I2C Own Address Bit 3"]
#[inline(always)]
pub fn ucoa3(&mut self) -> Ucoa3W<'_, Ucb0i2coa0Spec> {
Ucoa3W::new(self, 3)
}
#[doc = "Bit 4 - I2C Own Address Bit 4"]
#[inline(always)]
pub fn ucoa4(&mut self) -> Ucoa4W<'_, Ucb0i2coa0Spec> {
Ucoa4W::new(self, 4)
}
#[doc = "Bit 5 - I2C Own Address Bit 5"]
#[inline(always)]
pub fn ucoa5(&mut self) -> Ucoa5W<'_, Ucb0i2coa0Spec> {
Ucoa5W::new(self, 5)
}
#[doc = "Bit 6 - I2C Own Address Bit 6"]
#[inline(always)]
pub fn ucoa6(&mut self) -> Ucoa6W<'_, Ucb0i2coa0Spec> {
Ucoa6W::new(self, 6)
}
#[doc = "Bit 7 - I2C Own Address Bit 7"]
#[inline(always)]
pub fn ucoa7(&mut self) -> Ucoa7W<'_, Ucb0i2coa0Spec> {
Ucoa7W::new(self, 7)
}
#[doc = "Bit 8 - I2C Own Address Bit 8"]
#[inline(always)]
pub fn ucoa8(&mut self) -> Ucoa8W<'_, Ucb0i2coa0Spec> {
Ucoa8W::new(self, 8)
}
#[doc = "Bit 9 - I2C Own Address Bit 9"]
#[inline(always)]
pub fn ucoa9(&mut self) -> Ucoa9W<'_, Ucb0i2coa0Spec> {
Ucoa9W::new(self, 9)
}
#[doc = "Bit 10 - I2C Own Address enable"]
#[inline(always)]
pub fn ucoaen(&mut self) -> UcoaenW<'_, Ucb0i2coa0Spec> {
UcoaenW::new(self, 10)
}
#[doc = "Bit 15 - I2C General Call enable"]
#[inline(always)]
pub fn ucgcen(&mut self) -> UcgcenW<'_, Ucb0i2coa0Spec> {
UcgcenW::new(self, 15)
}
}
#[doc = "USCI B0 I2C Own Address 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0i2coa0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0i2coa0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0i2coa0Spec;
impl crate::RegisterSpec for Ucb0i2coa0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0i2coa0::R`](R) reader structure"]
impl crate::Readable for Ucb0i2coa0Spec {}
#[doc = "`write(|w| ..)` method takes [`ucb0i2coa0::W`](W) writer structure"]
impl crate::Writable for Ucb0i2coa0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0I2COA0 to value 0"]
impl crate::Resettable for Ucb0i2coa0Spec {}
}
#[doc = "UCB0I2COA1 (rw) register accessor: USCI B0 I2C Own Address 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0i2coa1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0i2coa1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0i2coa1`] module"]
#[doc(alias = "UCB0I2COA1")]
pub type Ucb0i2coa1 = crate::Reg<ucb0i2coa1::Ucb0i2coa1Spec>;
#[doc = "USCI B0 I2C Own Address 1"]
pub mod ucb0i2coa1 {
#[doc = "Register `UCB0I2COA1` reader"]
pub type R = crate::R<Ucb0i2coa1Spec>;
#[doc = "Register `UCB0I2COA1` writer"]
pub type W = crate::W<Ucb0i2coa1Spec>;
#[doc = "Field `UCOA0` reader - I2C Own Address Bit 0"]
pub type Ucoa0R = crate::BitReader;
#[doc = "Field `UCOA0` writer - I2C Own Address Bit 0"]
pub type Ucoa0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA1` reader - I2C Own Address Bit 1"]
pub type Ucoa1R = crate::BitReader;
#[doc = "Field `UCOA1` writer - I2C Own Address Bit 1"]
pub type Ucoa1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA2` reader - I2C Own Address Bit 2"]
pub type Ucoa2R = crate::BitReader;
#[doc = "Field `UCOA2` writer - I2C Own Address Bit 2"]
pub type Ucoa2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA3` reader - I2C Own Address Bit 3"]
pub type Ucoa3R = crate::BitReader;
#[doc = "Field `UCOA3` writer - I2C Own Address Bit 3"]
pub type Ucoa3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA4` reader - I2C Own Address Bit 4"]
pub type Ucoa4R = crate::BitReader;
#[doc = "Field `UCOA4` writer - I2C Own Address Bit 4"]
pub type Ucoa4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA5` reader - I2C Own Address Bit 5"]
pub type Ucoa5R = crate::BitReader;
#[doc = "Field `UCOA5` writer - I2C Own Address Bit 5"]
pub type Ucoa5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA6` reader - I2C Own Address Bit 6"]
pub type Ucoa6R = crate::BitReader;
#[doc = "Field `UCOA6` writer - I2C Own Address Bit 6"]
pub type Ucoa6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA7` reader - I2C Own Address Bit 7"]
pub type Ucoa7R = crate::BitReader;
#[doc = "Field `UCOA7` writer - I2C Own Address Bit 7"]
pub type Ucoa7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA8` reader - I2C Own Address Bit 8"]
pub type Ucoa8R = crate::BitReader;
#[doc = "Field `UCOA8` writer - I2C Own Address Bit 8"]
pub type Ucoa8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA9` reader - I2C Own Address Bit 9"]
pub type Ucoa9R = crate::BitReader;
#[doc = "Field `UCOA9` writer - I2C Own Address Bit 9"]
pub type Ucoa9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOAEN` reader - I2C Own Address enable"]
pub type UcoaenR = crate::BitReader;
#[doc = "Field `UCOAEN` writer - I2C Own Address enable"]
pub type UcoaenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - I2C Own Address Bit 0"]
#[inline(always)]
pub fn ucoa0(&self) -> Ucoa0R {
Ucoa0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - I2C Own Address Bit 1"]
#[inline(always)]
pub fn ucoa1(&self) -> Ucoa1R {
Ucoa1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - I2C Own Address Bit 2"]
#[inline(always)]
pub fn ucoa2(&self) -> Ucoa2R {
Ucoa2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - I2C Own Address Bit 3"]
#[inline(always)]
pub fn ucoa3(&self) -> Ucoa3R {
Ucoa3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - I2C Own Address Bit 4"]
#[inline(always)]
pub fn ucoa4(&self) -> Ucoa4R {
Ucoa4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - I2C Own Address Bit 5"]
#[inline(always)]
pub fn ucoa5(&self) -> Ucoa5R {
Ucoa5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - I2C Own Address Bit 6"]
#[inline(always)]
pub fn ucoa6(&self) -> Ucoa6R {
Ucoa6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - I2C Own Address Bit 7"]
#[inline(always)]
pub fn ucoa7(&self) -> Ucoa7R {
Ucoa7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - I2C Own Address Bit 8"]
#[inline(always)]
pub fn ucoa8(&self) -> Ucoa8R {
Ucoa8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - I2C Own Address Bit 9"]
#[inline(always)]
pub fn ucoa9(&self) -> Ucoa9R {
Ucoa9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - I2C Own Address enable"]
#[inline(always)]
pub fn ucoaen(&self) -> UcoaenR {
UcoaenR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - I2C Own Address Bit 0"]
#[inline(always)]
pub fn ucoa0(&mut self) -> Ucoa0W<'_, Ucb0i2coa1Spec> {
Ucoa0W::new(self, 0)
}
#[doc = "Bit 1 - I2C Own Address Bit 1"]
#[inline(always)]
pub fn ucoa1(&mut self) -> Ucoa1W<'_, Ucb0i2coa1Spec> {
Ucoa1W::new(self, 1)
}
#[doc = "Bit 2 - I2C Own Address Bit 2"]
#[inline(always)]
pub fn ucoa2(&mut self) -> Ucoa2W<'_, Ucb0i2coa1Spec> {
Ucoa2W::new(self, 2)
}
#[doc = "Bit 3 - I2C Own Address Bit 3"]
#[inline(always)]
pub fn ucoa3(&mut self) -> Ucoa3W<'_, Ucb0i2coa1Spec> {
Ucoa3W::new(self, 3)
}
#[doc = "Bit 4 - I2C Own Address Bit 4"]
#[inline(always)]
pub fn ucoa4(&mut self) -> Ucoa4W<'_, Ucb0i2coa1Spec> {
Ucoa4W::new(self, 4)
}
#[doc = "Bit 5 - I2C Own Address Bit 5"]
#[inline(always)]
pub fn ucoa5(&mut self) -> Ucoa5W<'_, Ucb0i2coa1Spec> {
Ucoa5W::new(self, 5)
}
#[doc = "Bit 6 - I2C Own Address Bit 6"]
#[inline(always)]
pub fn ucoa6(&mut self) -> Ucoa6W<'_, Ucb0i2coa1Spec> {
Ucoa6W::new(self, 6)
}
#[doc = "Bit 7 - I2C Own Address Bit 7"]
#[inline(always)]
pub fn ucoa7(&mut self) -> Ucoa7W<'_, Ucb0i2coa1Spec> {
Ucoa7W::new(self, 7)
}
#[doc = "Bit 8 - I2C Own Address Bit 8"]
#[inline(always)]
pub fn ucoa8(&mut self) -> Ucoa8W<'_, Ucb0i2coa1Spec> {
Ucoa8W::new(self, 8)
}
#[doc = "Bit 9 - I2C Own Address Bit 9"]
#[inline(always)]
pub fn ucoa9(&mut self) -> Ucoa9W<'_, Ucb0i2coa1Spec> {
Ucoa9W::new(self, 9)
}
#[doc = "Bit 10 - I2C Own Address enable"]
#[inline(always)]
pub fn ucoaen(&mut self) -> UcoaenW<'_, Ucb0i2coa1Spec> {
UcoaenW::new(self, 10)
}
}
#[doc = "USCI B0 I2C Own Address 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0i2coa1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0i2coa1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0i2coa1Spec;
impl crate::RegisterSpec for Ucb0i2coa1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0i2coa1::R`](R) reader structure"]
impl crate::Readable for Ucb0i2coa1Spec {}
#[doc = "`write(|w| ..)` method takes [`ucb0i2coa1::W`](W) writer structure"]
impl crate::Writable for Ucb0i2coa1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0I2COA1 to value 0"]
impl crate::Resettable for Ucb0i2coa1Spec {}
}
#[doc = "UCB0I2COA2 (rw) register accessor: USCI B0 I2C Own Address 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0i2coa2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0i2coa2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0i2coa2`] module"]
#[doc(alias = "UCB0I2COA2")]
pub type Ucb0i2coa2 = crate::Reg<ucb0i2coa2::Ucb0i2coa2Spec>;
#[doc = "USCI B0 I2C Own Address 2"]
pub mod ucb0i2coa2 {
#[doc = "Register `UCB0I2COA2` reader"]
pub type R = crate::R<Ucb0i2coa2Spec>;
#[doc = "Register `UCB0I2COA2` writer"]
pub type W = crate::W<Ucb0i2coa2Spec>;
#[doc = "Field `UCOA0` reader - I2C Own Address Bit 0"]
pub type Ucoa0R = crate::BitReader;
#[doc = "Field `UCOA0` writer - I2C Own Address Bit 0"]
pub type Ucoa0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA1` reader - I2C Own Address Bit 1"]
pub type Ucoa1R = crate::BitReader;
#[doc = "Field `UCOA1` writer - I2C Own Address Bit 1"]
pub type Ucoa1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA2` reader - I2C Own Address Bit 2"]
pub type Ucoa2R = crate::BitReader;
#[doc = "Field `UCOA2` writer - I2C Own Address Bit 2"]
pub type Ucoa2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA3` reader - I2C Own Address Bit 3"]
pub type Ucoa3R = crate::BitReader;
#[doc = "Field `UCOA3` writer - I2C Own Address Bit 3"]
pub type Ucoa3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA4` reader - I2C Own Address Bit 4"]
pub type Ucoa4R = crate::BitReader;
#[doc = "Field `UCOA4` writer - I2C Own Address Bit 4"]
pub type Ucoa4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA5` reader - I2C Own Address Bit 5"]
pub type Ucoa5R = crate::BitReader;
#[doc = "Field `UCOA5` writer - I2C Own Address Bit 5"]
pub type Ucoa5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA6` reader - I2C Own Address Bit 6"]
pub type Ucoa6R = crate::BitReader;
#[doc = "Field `UCOA6` writer - I2C Own Address Bit 6"]
pub type Ucoa6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA7` reader - I2C Own Address Bit 7"]
pub type Ucoa7R = crate::BitReader;
#[doc = "Field `UCOA7` writer - I2C Own Address Bit 7"]
pub type Ucoa7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA8` reader - I2C Own Address Bit 8"]
pub type Ucoa8R = crate::BitReader;
#[doc = "Field `UCOA8` writer - I2C Own Address Bit 8"]
pub type Ucoa8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA9` reader - I2C Own Address Bit 9"]
pub type Ucoa9R = crate::BitReader;
#[doc = "Field `UCOA9` writer - I2C Own Address Bit 9"]
pub type Ucoa9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOAEN` reader - I2C Own Address enable"]
pub type UcoaenR = crate::BitReader;
#[doc = "Field `UCOAEN` writer - I2C Own Address enable"]
pub type UcoaenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - I2C Own Address Bit 0"]
#[inline(always)]
pub fn ucoa0(&self) -> Ucoa0R {
Ucoa0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - I2C Own Address Bit 1"]
#[inline(always)]
pub fn ucoa1(&self) -> Ucoa1R {
Ucoa1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - I2C Own Address Bit 2"]
#[inline(always)]
pub fn ucoa2(&self) -> Ucoa2R {
Ucoa2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - I2C Own Address Bit 3"]
#[inline(always)]
pub fn ucoa3(&self) -> Ucoa3R {
Ucoa3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - I2C Own Address Bit 4"]
#[inline(always)]
pub fn ucoa4(&self) -> Ucoa4R {
Ucoa4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - I2C Own Address Bit 5"]
#[inline(always)]
pub fn ucoa5(&self) -> Ucoa5R {
Ucoa5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - I2C Own Address Bit 6"]
#[inline(always)]
pub fn ucoa6(&self) -> Ucoa6R {
Ucoa6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - I2C Own Address Bit 7"]
#[inline(always)]
pub fn ucoa7(&self) -> Ucoa7R {
Ucoa7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - I2C Own Address Bit 8"]
#[inline(always)]
pub fn ucoa8(&self) -> Ucoa8R {
Ucoa8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - I2C Own Address Bit 9"]
#[inline(always)]
pub fn ucoa9(&self) -> Ucoa9R {
Ucoa9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - I2C Own Address enable"]
#[inline(always)]
pub fn ucoaen(&self) -> UcoaenR {
UcoaenR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - I2C Own Address Bit 0"]
#[inline(always)]
pub fn ucoa0(&mut self) -> Ucoa0W<'_, Ucb0i2coa2Spec> {
Ucoa0W::new(self, 0)
}
#[doc = "Bit 1 - I2C Own Address Bit 1"]
#[inline(always)]
pub fn ucoa1(&mut self) -> Ucoa1W<'_, Ucb0i2coa2Spec> {
Ucoa1W::new(self, 1)
}
#[doc = "Bit 2 - I2C Own Address Bit 2"]
#[inline(always)]
pub fn ucoa2(&mut self) -> Ucoa2W<'_, Ucb0i2coa2Spec> {
Ucoa2W::new(self, 2)
}
#[doc = "Bit 3 - I2C Own Address Bit 3"]
#[inline(always)]
pub fn ucoa3(&mut self) -> Ucoa3W<'_, Ucb0i2coa2Spec> {
Ucoa3W::new(self, 3)
}
#[doc = "Bit 4 - I2C Own Address Bit 4"]
#[inline(always)]
pub fn ucoa4(&mut self) -> Ucoa4W<'_, Ucb0i2coa2Spec> {
Ucoa4W::new(self, 4)
}
#[doc = "Bit 5 - I2C Own Address Bit 5"]
#[inline(always)]
pub fn ucoa5(&mut self) -> Ucoa5W<'_, Ucb0i2coa2Spec> {
Ucoa5W::new(self, 5)
}
#[doc = "Bit 6 - I2C Own Address Bit 6"]
#[inline(always)]
pub fn ucoa6(&mut self) -> Ucoa6W<'_, Ucb0i2coa2Spec> {
Ucoa6W::new(self, 6)
}
#[doc = "Bit 7 - I2C Own Address Bit 7"]
#[inline(always)]
pub fn ucoa7(&mut self) -> Ucoa7W<'_, Ucb0i2coa2Spec> {
Ucoa7W::new(self, 7)
}
#[doc = "Bit 8 - I2C Own Address Bit 8"]
#[inline(always)]
pub fn ucoa8(&mut self) -> Ucoa8W<'_, Ucb0i2coa2Spec> {
Ucoa8W::new(self, 8)
}
#[doc = "Bit 9 - I2C Own Address Bit 9"]
#[inline(always)]
pub fn ucoa9(&mut self) -> Ucoa9W<'_, Ucb0i2coa2Spec> {
Ucoa9W::new(self, 9)
}
#[doc = "Bit 10 - I2C Own Address enable"]
#[inline(always)]
pub fn ucoaen(&mut self) -> UcoaenW<'_, Ucb0i2coa2Spec> {
UcoaenW::new(self, 10)
}
}
#[doc = "USCI B0 I2C Own Address 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0i2coa2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0i2coa2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0i2coa2Spec;
impl crate::RegisterSpec for Ucb0i2coa2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0i2coa2::R`](R) reader structure"]
impl crate::Readable for Ucb0i2coa2Spec {}
#[doc = "`write(|w| ..)` method takes [`ucb0i2coa2::W`](W) writer structure"]
impl crate::Writable for Ucb0i2coa2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0I2COA2 to value 0"]
impl crate::Resettable for Ucb0i2coa2Spec {}
}
#[doc = "UCB0I2COA3 (rw) register accessor: USCI B0 I2C Own Address 3\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0i2coa3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0i2coa3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0i2coa3`] module"]
#[doc(alias = "UCB0I2COA3")]
pub type Ucb0i2coa3 = crate::Reg<ucb0i2coa3::Ucb0i2coa3Spec>;
#[doc = "USCI B0 I2C Own Address 3"]
pub mod ucb0i2coa3 {
#[doc = "Register `UCB0I2COA3` reader"]
pub type R = crate::R<Ucb0i2coa3Spec>;
#[doc = "Register `UCB0I2COA3` writer"]
pub type W = crate::W<Ucb0i2coa3Spec>;
#[doc = "Field `UCOA0` reader - I2C Own Address Bit 0"]
pub type Ucoa0R = crate::BitReader;
#[doc = "Field `UCOA0` writer - I2C Own Address Bit 0"]
pub type Ucoa0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA1` reader - I2C Own Address Bit 1"]
pub type Ucoa1R = crate::BitReader;
#[doc = "Field `UCOA1` writer - I2C Own Address Bit 1"]
pub type Ucoa1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA2` reader - I2C Own Address Bit 2"]
pub type Ucoa2R = crate::BitReader;
#[doc = "Field `UCOA2` writer - I2C Own Address Bit 2"]
pub type Ucoa2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA3` reader - I2C Own Address Bit 3"]
pub type Ucoa3R = crate::BitReader;
#[doc = "Field `UCOA3` writer - I2C Own Address Bit 3"]
pub type Ucoa3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA4` reader - I2C Own Address Bit 4"]
pub type Ucoa4R = crate::BitReader;
#[doc = "Field `UCOA4` writer - I2C Own Address Bit 4"]
pub type Ucoa4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA5` reader - I2C Own Address Bit 5"]
pub type Ucoa5R = crate::BitReader;
#[doc = "Field `UCOA5` writer - I2C Own Address Bit 5"]
pub type Ucoa5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA6` reader - I2C Own Address Bit 6"]
pub type Ucoa6R = crate::BitReader;
#[doc = "Field `UCOA6` writer - I2C Own Address Bit 6"]
pub type Ucoa6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA7` reader - I2C Own Address Bit 7"]
pub type Ucoa7R = crate::BitReader;
#[doc = "Field `UCOA7` writer - I2C Own Address Bit 7"]
pub type Ucoa7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA8` reader - I2C Own Address Bit 8"]
pub type Ucoa8R = crate::BitReader;
#[doc = "Field `UCOA8` writer - I2C Own Address Bit 8"]
pub type Ucoa8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOA9` reader - I2C Own Address Bit 9"]
pub type Ucoa9R = crate::BitReader;
#[doc = "Field `UCOA9` writer - I2C Own Address Bit 9"]
pub type Ucoa9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCOAEN` reader - I2C Own Address enable"]
pub type UcoaenR = crate::BitReader;
#[doc = "Field `UCOAEN` writer - I2C Own Address enable"]
pub type UcoaenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - I2C Own Address Bit 0"]
#[inline(always)]
pub fn ucoa0(&self) -> Ucoa0R {
Ucoa0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - I2C Own Address Bit 1"]
#[inline(always)]
pub fn ucoa1(&self) -> Ucoa1R {
Ucoa1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - I2C Own Address Bit 2"]
#[inline(always)]
pub fn ucoa2(&self) -> Ucoa2R {
Ucoa2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - I2C Own Address Bit 3"]
#[inline(always)]
pub fn ucoa3(&self) -> Ucoa3R {
Ucoa3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - I2C Own Address Bit 4"]
#[inline(always)]
pub fn ucoa4(&self) -> Ucoa4R {
Ucoa4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - I2C Own Address Bit 5"]
#[inline(always)]
pub fn ucoa5(&self) -> Ucoa5R {
Ucoa5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - I2C Own Address Bit 6"]
#[inline(always)]
pub fn ucoa6(&self) -> Ucoa6R {
Ucoa6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - I2C Own Address Bit 7"]
#[inline(always)]
pub fn ucoa7(&self) -> Ucoa7R {
Ucoa7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - I2C Own Address Bit 8"]
#[inline(always)]
pub fn ucoa8(&self) -> Ucoa8R {
Ucoa8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - I2C Own Address Bit 9"]
#[inline(always)]
pub fn ucoa9(&self) -> Ucoa9R {
Ucoa9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - I2C Own Address enable"]
#[inline(always)]
pub fn ucoaen(&self) -> UcoaenR {
UcoaenR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - I2C Own Address Bit 0"]
#[inline(always)]
pub fn ucoa0(&mut self) -> Ucoa0W<'_, Ucb0i2coa3Spec> {
Ucoa0W::new(self, 0)
}
#[doc = "Bit 1 - I2C Own Address Bit 1"]
#[inline(always)]
pub fn ucoa1(&mut self) -> Ucoa1W<'_, Ucb0i2coa3Spec> {
Ucoa1W::new(self, 1)
}
#[doc = "Bit 2 - I2C Own Address Bit 2"]
#[inline(always)]
pub fn ucoa2(&mut self) -> Ucoa2W<'_, Ucb0i2coa3Spec> {
Ucoa2W::new(self, 2)
}
#[doc = "Bit 3 - I2C Own Address Bit 3"]
#[inline(always)]
pub fn ucoa3(&mut self) -> Ucoa3W<'_, Ucb0i2coa3Spec> {
Ucoa3W::new(self, 3)
}
#[doc = "Bit 4 - I2C Own Address Bit 4"]
#[inline(always)]
pub fn ucoa4(&mut self) -> Ucoa4W<'_, Ucb0i2coa3Spec> {
Ucoa4W::new(self, 4)
}
#[doc = "Bit 5 - I2C Own Address Bit 5"]
#[inline(always)]
pub fn ucoa5(&mut self) -> Ucoa5W<'_, Ucb0i2coa3Spec> {
Ucoa5W::new(self, 5)
}
#[doc = "Bit 6 - I2C Own Address Bit 6"]
#[inline(always)]
pub fn ucoa6(&mut self) -> Ucoa6W<'_, Ucb0i2coa3Spec> {
Ucoa6W::new(self, 6)
}
#[doc = "Bit 7 - I2C Own Address Bit 7"]
#[inline(always)]
pub fn ucoa7(&mut self) -> Ucoa7W<'_, Ucb0i2coa3Spec> {
Ucoa7W::new(self, 7)
}
#[doc = "Bit 8 - I2C Own Address Bit 8"]
#[inline(always)]
pub fn ucoa8(&mut self) -> Ucoa8W<'_, Ucb0i2coa3Spec> {
Ucoa8W::new(self, 8)
}
#[doc = "Bit 9 - I2C Own Address Bit 9"]
#[inline(always)]
pub fn ucoa9(&mut self) -> Ucoa9W<'_, Ucb0i2coa3Spec> {
Ucoa9W::new(self, 9)
}
#[doc = "Bit 10 - I2C Own Address enable"]
#[inline(always)]
pub fn ucoaen(&mut self) -> UcoaenW<'_, Ucb0i2coa3Spec> {
UcoaenW::new(self, 10)
}
}
#[doc = "USCI B0 I2C Own Address 3\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0i2coa3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0i2coa3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0i2coa3Spec;
impl crate::RegisterSpec for Ucb0i2coa3Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0i2coa3::R`](R) reader structure"]
impl crate::Readable for Ucb0i2coa3Spec {}
#[doc = "`write(|w| ..)` method takes [`ucb0i2coa3::W`](W) writer structure"]
impl crate::Writable for Ucb0i2coa3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0I2COA3 to value 0"]
impl crate::Resettable for Ucb0i2coa3Spec {}
}
#[doc = "UCB0ADDRX (rw) register accessor: USCI B0 Received Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0addrx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0addrx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0addrx`] module"]
#[doc(alias = "UCB0ADDRX")]
pub type Ucb0addrx = crate::Reg<ucb0addrx::Ucb0addrxSpec>;
#[doc = "USCI B0 Received Address Register"]
pub mod ucb0addrx {
#[doc = "Register `UCB0ADDRX` reader"]
pub type R = crate::R<Ucb0addrxSpec>;
#[doc = "Register `UCB0ADDRX` writer"]
pub type W = crate::W<Ucb0addrxSpec>;
#[doc = "Field `UCADDRX0` reader - I2C Receive Address Bit 0"]
pub type Ucaddrx0R = crate::BitReader;
#[doc = "Field `UCADDRX0` writer - I2C Receive Address Bit 0"]
pub type Ucaddrx0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDRX1` reader - I2C Receive Address Bit 1"]
pub type Ucaddrx1R = crate::BitReader;
#[doc = "Field `UCADDRX1` writer - I2C Receive Address Bit 1"]
pub type Ucaddrx1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDRX2` reader - I2C Receive Address Bit 2"]
pub type Ucaddrx2R = crate::BitReader;
#[doc = "Field `UCADDRX2` writer - I2C Receive Address Bit 2"]
pub type Ucaddrx2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDRX3` reader - I2C Receive Address Bit 3"]
pub type Ucaddrx3R = crate::BitReader;
#[doc = "Field `UCADDRX3` writer - I2C Receive Address Bit 3"]
pub type Ucaddrx3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDRX4` reader - I2C Receive Address Bit 4"]
pub type Ucaddrx4R = crate::BitReader;
#[doc = "Field `UCADDRX4` writer - I2C Receive Address Bit 4"]
pub type Ucaddrx4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDRX5` reader - I2C Receive Address Bit 5"]
pub type Ucaddrx5R = crate::BitReader;
#[doc = "Field `UCADDRX5` writer - I2C Receive Address Bit 5"]
pub type Ucaddrx5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDRX6` reader - I2C Receive Address Bit 6"]
pub type Ucaddrx6R = crate::BitReader;
#[doc = "Field `UCADDRX6` writer - I2C Receive Address Bit 6"]
pub type Ucaddrx6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDRX7` reader - I2C Receive Address Bit 7"]
pub type Ucaddrx7R = crate::BitReader;
#[doc = "Field `UCADDRX7` writer - I2C Receive Address Bit 7"]
pub type Ucaddrx7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDRX8` reader - I2C Receive Address Bit 8"]
pub type Ucaddrx8R = crate::BitReader;
#[doc = "Field `UCADDRX8` writer - I2C Receive Address Bit 8"]
pub type Ucaddrx8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDRX9` reader - I2C Receive Address Bit 9"]
pub type Ucaddrx9R = crate::BitReader;
#[doc = "Field `UCADDRX9` writer - I2C Receive Address Bit 9"]
pub type Ucaddrx9W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - I2C Receive Address Bit 0"]
#[inline(always)]
pub fn ucaddrx0(&self) -> Ucaddrx0R {
Ucaddrx0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - I2C Receive Address Bit 1"]
#[inline(always)]
pub fn ucaddrx1(&self) -> Ucaddrx1R {
Ucaddrx1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - I2C Receive Address Bit 2"]
#[inline(always)]
pub fn ucaddrx2(&self) -> Ucaddrx2R {
Ucaddrx2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - I2C Receive Address Bit 3"]
#[inline(always)]
pub fn ucaddrx3(&self) -> Ucaddrx3R {
Ucaddrx3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - I2C Receive Address Bit 4"]
#[inline(always)]
pub fn ucaddrx4(&self) -> Ucaddrx4R {
Ucaddrx4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - I2C Receive Address Bit 5"]
#[inline(always)]
pub fn ucaddrx5(&self) -> Ucaddrx5R {
Ucaddrx5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - I2C Receive Address Bit 6"]
#[inline(always)]
pub fn ucaddrx6(&self) -> Ucaddrx6R {
Ucaddrx6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - I2C Receive Address Bit 7"]
#[inline(always)]
pub fn ucaddrx7(&self) -> Ucaddrx7R {
Ucaddrx7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - I2C Receive Address Bit 8"]
#[inline(always)]
pub fn ucaddrx8(&self) -> Ucaddrx8R {
Ucaddrx8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - I2C Receive Address Bit 9"]
#[inline(always)]
pub fn ucaddrx9(&self) -> Ucaddrx9R {
Ucaddrx9R::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - I2C Receive Address Bit 0"]
#[inline(always)]
pub fn ucaddrx0(&mut self) -> Ucaddrx0W<'_, Ucb0addrxSpec> {
Ucaddrx0W::new(self, 0)
}
#[doc = "Bit 1 - I2C Receive Address Bit 1"]
#[inline(always)]
pub fn ucaddrx1(&mut self) -> Ucaddrx1W<'_, Ucb0addrxSpec> {
Ucaddrx1W::new(self, 1)
}
#[doc = "Bit 2 - I2C Receive Address Bit 2"]
#[inline(always)]
pub fn ucaddrx2(&mut self) -> Ucaddrx2W<'_, Ucb0addrxSpec> {
Ucaddrx2W::new(self, 2)
}
#[doc = "Bit 3 - I2C Receive Address Bit 3"]
#[inline(always)]
pub fn ucaddrx3(&mut self) -> Ucaddrx3W<'_, Ucb0addrxSpec> {
Ucaddrx3W::new(self, 3)
}
#[doc = "Bit 4 - I2C Receive Address Bit 4"]
#[inline(always)]
pub fn ucaddrx4(&mut self) -> Ucaddrx4W<'_, Ucb0addrxSpec> {
Ucaddrx4W::new(self, 4)
}
#[doc = "Bit 5 - I2C Receive Address Bit 5"]
#[inline(always)]
pub fn ucaddrx5(&mut self) -> Ucaddrx5W<'_, Ucb0addrxSpec> {
Ucaddrx5W::new(self, 5)
}
#[doc = "Bit 6 - I2C Receive Address Bit 6"]
#[inline(always)]
pub fn ucaddrx6(&mut self) -> Ucaddrx6W<'_, Ucb0addrxSpec> {
Ucaddrx6W::new(self, 6)
}
#[doc = "Bit 7 - I2C Receive Address Bit 7"]
#[inline(always)]
pub fn ucaddrx7(&mut self) -> Ucaddrx7W<'_, Ucb0addrxSpec> {
Ucaddrx7W::new(self, 7)
}
#[doc = "Bit 8 - I2C Receive Address Bit 8"]
#[inline(always)]
pub fn ucaddrx8(&mut self) -> Ucaddrx8W<'_, Ucb0addrxSpec> {
Ucaddrx8W::new(self, 8)
}
#[doc = "Bit 9 - I2C Receive Address Bit 9"]
#[inline(always)]
pub fn ucaddrx9(&mut self) -> Ucaddrx9W<'_, Ucb0addrxSpec> {
Ucaddrx9W::new(self, 9)
}
}
#[doc = "USCI B0 Received Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0addrx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0addrx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0addrxSpec;
impl crate::RegisterSpec for Ucb0addrxSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0addrx::R`](R) reader structure"]
impl crate::Readable for Ucb0addrxSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0addrx::W`](W) writer structure"]
impl crate::Writable for Ucb0addrxSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0ADDRX to value 0"]
impl crate::Resettable for Ucb0addrxSpec {}
}
#[doc = "UCB0ADDMASK (rw) register accessor: USCI B0 Address Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0addmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0addmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0addmask`] module"]
#[doc(alias = "UCB0ADDMASK")]
pub type Ucb0addmask = crate::Reg<ucb0addmask::Ucb0addmaskSpec>;
#[doc = "USCI B0 Address Mask Register"]
pub mod ucb0addmask {
#[doc = "Register `UCB0ADDMASK` reader"]
pub type R = crate::R<Ucb0addmaskSpec>;
#[doc = "Register `UCB0ADDMASK` writer"]
pub type W = crate::W<Ucb0addmaskSpec>;
#[doc = "Field `UCADDMASK0` reader - I2C Address Mask Bit 0"]
pub type Ucaddmask0R = crate::BitReader;
#[doc = "Field `UCADDMASK0` writer - I2C Address Mask Bit 0"]
pub type Ucaddmask0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDMASK1` reader - I2C Address Mask Bit 1"]
pub type Ucaddmask1R = crate::BitReader;
#[doc = "Field `UCADDMASK1` writer - I2C Address Mask Bit 1"]
pub type Ucaddmask1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDMASK2` reader - I2C Address Mask Bit 2"]
pub type Ucaddmask2R = crate::BitReader;
#[doc = "Field `UCADDMASK2` writer - I2C Address Mask Bit 2"]
pub type Ucaddmask2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDMASK3` reader - I2C Address Mask Bit 3"]
pub type Ucaddmask3R = crate::BitReader;
#[doc = "Field `UCADDMASK3` writer - I2C Address Mask Bit 3"]
pub type Ucaddmask3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDMASK4` reader - I2C Address Mask Bit 4"]
pub type Ucaddmask4R = crate::BitReader;
#[doc = "Field `UCADDMASK4` writer - I2C Address Mask Bit 4"]
pub type Ucaddmask4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDMASK5` reader - I2C Address Mask Bit 5"]
pub type Ucaddmask5R = crate::BitReader;
#[doc = "Field `UCADDMASK5` writer - I2C Address Mask Bit 5"]
pub type Ucaddmask5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDMASK6` reader - I2C Address Mask Bit 6"]
pub type Ucaddmask6R = crate::BitReader;
#[doc = "Field `UCADDMASK6` writer - I2C Address Mask Bit 6"]
pub type Ucaddmask6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDMASK7` reader - I2C Address Mask Bit 7"]
pub type Ucaddmask7R = crate::BitReader;
#[doc = "Field `UCADDMASK7` writer - I2C Address Mask Bit 7"]
pub type Ucaddmask7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDMASK8` reader - I2C Address Mask Bit 8"]
pub type Ucaddmask8R = crate::BitReader;
#[doc = "Field `UCADDMASK8` writer - I2C Address Mask Bit 8"]
pub type Ucaddmask8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCADDMASK9` reader - I2C Address Mask Bit 9"]
pub type Ucaddmask9R = crate::BitReader;
#[doc = "Field `UCADDMASK9` writer - I2C Address Mask Bit 9"]
pub type Ucaddmask9W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - I2C Address Mask Bit 0"]
#[inline(always)]
pub fn ucaddmask0(&self) -> Ucaddmask0R {
Ucaddmask0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - I2C Address Mask Bit 1"]
#[inline(always)]
pub fn ucaddmask1(&self) -> Ucaddmask1R {
Ucaddmask1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - I2C Address Mask Bit 2"]
#[inline(always)]
pub fn ucaddmask2(&self) -> Ucaddmask2R {
Ucaddmask2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - I2C Address Mask Bit 3"]
#[inline(always)]
pub fn ucaddmask3(&self) -> Ucaddmask3R {
Ucaddmask3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - I2C Address Mask Bit 4"]
#[inline(always)]
pub fn ucaddmask4(&self) -> Ucaddmask4R {
Ucaddmask4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - I2C Address Mask Bit 5"]
#[inline(always)]
pub fn ucaddmask5(&self) -> Ucaddmask5R {
Ucaddmask5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - I2C Address Mask Bit 6"]
#[inline(always)]
pub fn ucaddmask6(&self) -> Ucaddmask6R {
Ucaddmask6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - I2C Address Mask Bit 7"]
#[inline(always)]
pub fn ucaddmask7(&self) -> Ucaddmask7R {
Ucaddmask7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - I2C Address Mask Bit 8"]
#[inline(always)]
pub fn ucaddmask8(&self) -> Ucaddmask8R {
Ucaddmask8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - I2C Address Mask Bit 9"]
#[inline(always)]
pub fn ucaddmask9(&self) -> Ucaddmask9R {
Ucaddmask9R::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - I2C Address Mask Bit 0"]
#[inline(always)]
pub fn ucaddmask0(&mut self) -> Ucaddmask0W<'_, Ucb0addmaskSpec> {
Ucaddmask0W::new(self, 0)
}
#[doc = "Bit 1 - I2C Address Mask Bit 1"]
#[inline(always)]
pub fn ucaddmask1(&mut self) -> Ucaddmask1W<'_, Ucb0addmaskSpec> {
Ucaddmask1W::new(self, 1)
}
#[doc = "Bit 2 - I2C Address Mask Bit 2"]
#[inline(always)]
pub fn ucaddmask2(&mut self) -> Ucaddmask2W<'_, Ucb0addmaskSpec> {
Ucaddmask2W::new(self, 2)
}
#[doc = "Bit 3 - I2C Address Mask Bit 3"]
#[inline(always)]
pub fn ucaddmask3(&mut self) -> Ucaddmask3W<'_, Ucb0addmaskSpec> {
Ucaddmask3W::new(self, 3)
}
#[doc = "Bit 4 - I2C Address Mask Bit 4"]
#[inline(always)]
pub fn ucaddmask4(&mut self) -> Ucaddmask4W<'_, Ucb0addmaskSpec> {
Ucaddmask4W::new(self, 4)
}
#[doc = "Bit 5 - I2C Address Mask Bit 5"]
#[inline(always)]
pub fn ucaddmask5(&mut self) -> Ucaddmask5W<'_, Ucb0addmaskSpec> {
Ucaddmask5W::new(self, 5)
}
#[doc = "Bit 6 - I2C Address Mask Bit 6"]
#[inline(always)]
pub fn ucaddmask6(&mut self) -> Ucaddmask6W<'_, Ucb0addmaskSpec> {
Ucaddmask6W::new(self, 6)
}
#[doc = "Bit 7 - I2C Address Mask Bit 7"]
#[inline(always)]
pub fn ucaddmask7(&mut self) -> Ucaddmask7W<'_, Ucb0addmaskSpec> {
Ucaddmask7W::new(self, 7)
}
#[doc = "Bit 8 - I2C Address Mask Bit 8"]
#[inline(always)]
pub fn ucaddmask8(&mut self) -> Ucaddmask8W<'_, Ucb0addmaskSpec> {
Ucaddmask8W::new(self, 8)
}
#[doc = "Bit 9 - I2C Address Mask Bit 9"]
#[inline(always)]
pub fn ucaddmask9(&mut self) -> Ucaddmask9W<'_, Ucb0addmaskSpec> {
Ucaddmask9W::new(self, 9)
}
}
#[doc = "USCI B0 Address Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0addmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0addmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0addmaskSpec;
impl crate::RegisterSpec for Ucb0addmaskSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0addmask::R`](R) reader structure"]
impl crate::Readable for Ucb0addmaskSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0addmask::W`](W) writer structure"]
impl crate::Writable for Ucb0addmaskSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0ADDMASK to value 0"]
impl crate::Resettable for Ucb0addmaskSpec {}
}
#[doc = "UCB0I2CSA (rw) register accessor: USCI B0 I2C Slave Address\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0i2csa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0i2csa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0i2csa`] module"]
#[doc(alias = "UCB0I2CSA")]
pub type Ucb0i2csa = crate::Reg<ucb0i2csa::Ucb0i2csaSpec>;
#[doc = "USCI B0 I2C Slave Address"]
pub mod ucb0i2csa {
#[doc = "Register `UCB0I2CSA` reader"]
pub type R = crate::R<Ucb0i2csaSpec>;
#[doc = "Register `UCB0I2CSA` writer"]
pub type W = crate::W<Ucb0i2csaSpec>;
#[doc = "Field `UCSA0` reader - I2C Slave Address Bit 0"]
pub type Ucsa0R = crate::BitReader;
#[doc = "Field `UCSA0` writer - I2C Slave Address Bit 0"]
pub type Ucsa0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCSA1` reader - I2C Slave Address Bit 1"]
pub type Ucsa1R = crate::BitReader;
#[doc = "Field `UCSA1` writer - I2C Slave Address Bit 1"]
pub type Ucsa1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCSA2` reader - I2C Slave Address Bit 2"]
pub type Ucsa2R = crate::BitReader;
#[doc = "Field `UCSA2` writer - I2C Slave Address Bit 2"]
pub type Ucsa2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCSA3` reader - I2C Slave Address Bit 3"]
pub type Ucsa3R = crate::BitReader;
#[doc = "Field `UCSA3` writer - I2C Slave Address Bit 3"]
pub type Ucsa3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCSA4` reader - I2C Slave Address Bit 4"]
pub type Ucsa4R = crate::BitReader;
#[doc = "Field `UCSA4` writer - I2C Slave Address Bit 4"]
pub type Ucsa4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCSA5` reader - I2C Slave Address Bit 5"]
pub type Ucsa5R = crate::BitReader;
#[doc = "Field `UCSA5` writer - I2C Slave Address Bit 5"]
pub type Ucsa5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCSA6` reader - I2C Slave Address Bit 6"]
pub type Ucsa6R = crate::BitReader;
#[doc = "Field `UCSA6` writer - I2C Slave Address Bit 6"]
pub type Ucsa6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCSA7` reader - I2C Slave Address Bit 7"]
pub type Ucsa7R = crate::BitReader;
#[doc = "Field `UCSA7` writer - I2C Slave Address Bit 7"]
pub type Ucsa7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCSA8` reader - I2C Slave Address Bit 8"]
pub type Ucsa8R = crate::BitReader;
#[doc = "Field `UCSA8` writer - I2C Slave Address Bit 8"]
pub type Ucsa8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCSA9` reader - I2C Slave Address Bit 9"]
pub type Ucsa9R = crate::BitReader;
#[doc = "Field `UCSA9` writer - I2C Slave Address Bit 9"]
pub type Ucsa9W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - I2C Slave Address Bit 0"]
#[inline(always)]
pub fn ucsa0(&self) -> Ucsa0R {
Ucsa0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - I2C Slave Address Bit 1"]
#[inline(always)]
pub fn ucsa1(&self) -> Ucsa1R {
Ucsa1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - I2C Slave Address Bit 2"]
#[inline(always)]
pub fn ucsa2(&self) -> Ucsa2R {
Ucsa2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - I2C Slave Address Bit 3"]
#[inline(always)]
pub fn ucsa3(&self) -> Ucsa3R {
Ucsa3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - I2C Slave Address Bit 4"]
#[inline(always)]
pub fn ucsa4(&self) -> Ucsa4R {
Ucsa4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - I2C Slave Address Bit 5"]
#[inline(always)]
pub fn ucsa5(&self) -> Ucsa5R {
Ucsa5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - I2C Slave Address Bit 6"]
#[inline(always)]
pub fn ucsa6(&self) -> Ucsa6R {
Ucsa6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - I2C Slave Address Bit 7"]
#[inline(always)]
pub fn ucsa7(&self) -> Ucsa7R {
Ucsa7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - I2C Slave Address Bit 8"]
#[inline(always)]
pub fn ucsa8(&self) -> Ucsa8R {
Ucsa8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - I2C Slave Address Bit 9"]
#[inline(always)]
pub fn ucsa9(&self) -> Ucsa9R {
Ucsa9R::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - I2C Slave Address Bit 0"]
#[inline(always)]
pub fn ucsa0(&mut self) -> Ucsa0W<'_, Ucb0i2csaSpec> {
Ucsa0W::new(self, 0)
}
#[doc = "Bit 1 - I2C Slave Address Bit 1"]
#[inline(always)]
pub fn ucsa1(&mut self) -> Ucsa1W<'_, Ucb0i2csaSpec> {
Ucsa1W::new(self, 1)
}
#[doc = "Bit 2 - I2C Slave Address Bit 2"]
#[inline(always)]
pub fn ucsa2(&mut self) -> Ucsa2W<'_, Ucb0i2csaSpec> {
Ucsa2W::new(self, 2)
}
#[doc = "Bit 3 - I2C Slave Address Bit 3"]
#[inline(always)]
pub fn ucsa3(&mut self) -> Ucsa3W<'_, Ucb0i2csaSpec> {
Ucsa3W::new(self, 3)
}
#[doc = "Bit 4 - I2C Slave Address Bit 4"]
#[inline(always)]
pub fn ucsa4(&mut self) -> Ucsa4W<'_, Ucb0i2csaSpec> {
Ucsa4W::new(self, 4)
}
#[doc = "Bit 5 - I2C Slave Address Bit 5"]
#[inline(always)]
pub fn ucsa5(&mut self) -> Ucsa5W<'_, Ucb0i2csaSpec> {
Ucsa5W::new(self, 5)
}
#[doc = "Bit 6 - I2C Slave Address Bit 6"]
#[inline(always)]
pub fn ucsa6(&mut self) -> Ucsa6W<'_, Ucb0i2csaSpec> {
Ucsa6W::new(self, 6)
}
#[doc = "Bit 7 - I2C Slave Address Bit 7"]
#[inline(always)]
pub fn ucsa7(&mut self) -> Ucsa7W<'_, Ucb0i2csaSpec> {
Ucsa7W::new(self, 7)
}
#[doc = "Bit 8 - I2C Slave Address Bit 8"]
#[inline(always)]
pub fn ucsa8(&mut self) -> Ucsa8W<'_, Ucb0i2csaSpec> {
Ucsa8W::new(self, 8)
}
#[doc = "Bit 9 - I2C Slave Address Bit 9"]
#[inline(always)]
pub fn ucsa9(&mut self) -> Ucsa9W<'_, Ucb0i2csaSpec> {
Ucsa9W::new(self, 9)
}
}
#[doc = "USCI B0 I2C Slave Address\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0i2csa::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0i2csa::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0i2csaSpec;
impl crate::RegisterSpec for Ucb0i2csaSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0i2csa::R`](R) reader structure"]
impl crate::Readable for Ucb0i2csaSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0i2csa::W`](W) writer structure"]
impl crate::Writable for Ucb0i2csaSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0I2CSA to value 0"]
impl crate::Resettable for Ucb0i2csaSpec {}
}
#[doc = "UCB0IE (rw) register accessor: USCI B0 Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0ie`] module"]
#[doc(alias = "UCB0IE")]
pub type Ucb0ie = crate::Reg<ucb0ie::Ucb0ieSpec>;
#[doc = "USCI B0 Interrupt Enable Register"]
pub mod ucb0ie {
#[doc = "Register `UCB0IE` reader"]
pub type R = crate::R<Ucb0ieSpec>;
#[doc = "Register `UCB0IE` writer"]
pub type W = crate::W<Ucb0ieSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI B0 Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0ieSpec;
impl crate::RegisterSpec for Ucb0ieSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0ie::R`](R) reader structure"]
impl crate::Readable for Ucb0ieSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0ie::W`](W) writer structure"]
impl crate::Writable for Ucb0ieSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0IE to value 0"]
impl crate::Resettable for Ucb0ieSpec {}
}
#[doc = "UCB0IE_I2C (rw) register accessor: USCI B0 Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ie_i2c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ie_i2c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0ie_i2c`] module"]
#[doc(alias = "UCB0IE_I2C")]
pub type Ucb0ieI2c = crate::Reg<ucb0ie_i2c::Ucb0ieI2cSpec>;
#[doc = "USCI B0 Interrupt Enable Register"]
pub mod ucb0ie_i2c {
#[doc = "Register `UCB0IE_I2C` reader"]
pub type R = crate::R<Ucb0ieI2cSpec>;
#[doc = "Register `UCB0IE_I2C` writer"]
pub type W = crate::W<Ucb0ieI2cSpec>;
#[doc = "Field `UCRXIE0` reader - I2C Receive Interrupt Enable 0"]
pub type Ucrxie0R = crate::BitReader;
#[doc = "Field `UCRXIE0` writer - I2C Receive Interrupt Enable 0"]
pub type Ucrxie0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCTXIE0` reader - I2C Transmit Interrupt Enable 0"]
pub type Uctxie0R = crate::BitReader;
#[doc = "Field `UCTXIE0` writer - I2C Transmit Interrupt Enable 0"]
pub type Uctxie0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCSTTIE` reader - I2C START Condition interrupt enable"]
pub type UcsttieR = crate::BitReader;
#[doc = "Field `UCSTTIE` writer - I2C START Condition interrupt enable"]
pub type UcsttieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCSTPIE` reader - I2C STOP Condition interrupt enable"]
pub type UcstpieR = crate::BitReader;
#[doc = "Field `UCSTPIE` writer - I2C STOP Condition interrupt enable"]
pub type UcstpieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCALIE` reader - I2C Arbitration Lost interrupt enable"]
pub type UcalieR = crate::BitReader;
#[doc = "Field `UCALIE` writer - I2C Arbitration Lost interrupt enable"]
pub type UcalieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCNACKIE` reader - I2C NACK Condition interrupt enable"]
pub type UcnackieR = crate::BitReader;
#[doc = "Field `UCNACKIE` writer - I2C NACK Condition interrupt enable"]
pub type UcnackieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBCNTIE` reader - I2C Automatic stop assertion interrupt enable"]
pub type UcbcntieR = crate::BitReader;
#[doc = "Field `UCBCNTIE` writer - I2C Automatic stop assertion interrupt enable"]
pub type UcbcntieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCCLTOIE` reader - I2C Clock Low Timeout interrupt enable"]
pub type UccltoieR = crate::BitReader;
#[doc = "Field `UCCLTOIE` writer - I2C Clock Low Timeout interrupt enable"]
pub type UccltoieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCRXIE1` reader - I2C Receive Interrupt Enable 1"]
pub type Ucrxie1R = crate::BitReader;
#[doc = "Field `UCRXIE1` writer - I2C Receive Interrupt Enable 1"]
pub type Ucrxie1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCTXIE1` reader - I2C Transmit Interrupt Enable 1"]
pub type Uctxie1R = crate::BitReader;
#[doc = "Field `UCTXIE1` writer - I2C Transmit Interrupt Enable 1"]
pub type Uctxie1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCRXIE2` reader - I2C Receive Interrupt Enable 2"]
pub type Ucrxie2R = crate::BitReader;
#[doc = "Field `UCRXIE2` writer - I2C Receive Interrupt Enable 2"]
pub type Ucrxie2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCTXIE2` reader - I2C Transmit Interrupt Enable 2"]
pub type Uctxie2R = crate::BitReader;
#[doc = "Field `UCTXIE2` writer - I2C Transmit Interrupt Enable 2"]
pub type Uctxie2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCRXIE3` reader - I2C Receive Interrupt Enable 3"]
pub type Ucrxie3R = crate::BitReader;
#[doc = "Field `UCRXIE3` writer - I2C Receive Interrupt Enable 3"]
pub type Ucrxie3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCTXIE3` reader - I2C Transmit Interrupt Enable 3"]
pub type Uctxie3R = crate::BitReader;
#[doc = "Field `UCTXIE3` writer - I2C Transmit Interrupt Enable 3"]
pub type Uctxie3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBIT9IE` reader - I2C Bit 9 Position Interrupt Enable 3"]
pub type Ucbit9ieR = crate::BitReader;
#[doc = "Field `UCBIT9IE` writer - I2C Bit 9 Position Interrupt Enable 3"]
pub type Ucbit9ieW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - I2C Receive Interrupt Enable 0"]
#[inline(always)]
pub fn ucrxie0(&self) -> Ucrxie0R {
Ucrxie0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - I2C Transmit Interrupt Enable 0"]
#[inline(always)]
pub fn uctxie0(&self) -> Uctxie0R {
Uctxie0R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - I2C START Condition interrupt enable"]
#[inline(always)]
pub fn ucsttie(&self) -> UcsttieR {
UcsttieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - I2C STOP Condition interrupt enable"]
#[inline(always)]
pub fn ucstpie(&self) -> UcstpieR {
UcstpieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - I2C Arbitration Lost interrupt enable"]
#[inline(always)]
pub fn ucalie(&self) -> UcalieR {
UcalieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - I2C NACK Condition interrupt enable"]
#[inline(always)]
pub fn ucnackie(&self) -> UcnackieR {
UcnackieR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - I2C Automatic stop assertion interrupt enable"]
#[inline(always)]
pub fn ucbcntie(&self) -> UcbcntieR {
UcbcntieR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - I2C Clock Low Timeout interrupt enable"]
#[inline(always)]
pub fn uccltoie(&self) -> UccltoieR {
UccltoieR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - I2C Receive Interrupt Enable 1"]
#[inline(always)]
pub fn ucrxie1(&self) -> Ucrxie1R {
Ucrxie1R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - I2C Transmit Interrupt Enable 1"]
#[inline(always)]
pub fn uctxie1(&self) -> Uctxie1R {
Uctxie1R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - I2C Receive Interrupt Enable 2"]
#[inline(always)]
pub fn ucrxie2(&self) -> Ucrxie2R {
Ucrxie2R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - I2C Transmit Interrupt Enable 2"]
#[inline(always)]
pub fn uctxie2(&self) -> Uctxie2R {
Uctxie2R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - I2C Receive Interrupt Enable 3"]
#[inline(always)]
pub fn ucrxie3(&self) -> Ucrxie3R {
Ucrxie3R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - I2C Transmit Interrupt Enable 3"]
#[inline(always)]
pub fn uctxie3(&self) -> Uctxie3R {
Uctxie3R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - I2C Bit 9 Position Interrupt Enable 3"]
#[inline(always)]
pub fn ucbit9ie(&self) -> Ucbit9ieR {
Ucbit9ieR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - I2C Receive Interrupt Enable 0"]
#[inline(always)]
pub fn ucrxie0(&mut self) -> Ucrxie0W<'_, Ucb0ieI2cSpec> {
Ucrxie0W::new(self, 0)
}
#[doc = "Bit 1 - I2C Transmit Interrupt Enable 0"]
#[inline(always)]
pub fn uctxie0(&mut self) -> Uctxie0W<'_, Ucb0ieI2cSpec> {
Uctxie0W::new(self, 1)
}
#[doc = "Bit 2 - I2C START Condition interrupt enable"]
#[inline(always)]
pub fn ucsttie(&mut self) -> UcsttieW<'_, Ucb0ieI2cSpec> {
UcsttieW::new(self, 2)
}
#[doc = "Bit 3 - I2C STOP Condition interrupt enable"]
#[inline(always)]
pub fn ucstpie(&mut self) -> UcstpieW<'_, Ucb0ieI2cSpec> {
UcstpieW::new(self, 3)
}
#[doc = "Bit 4 - I2C Arbitration Lost interrupt enable"]
#[inline(always)]
pub fn ucalie(&mut self) -> UcalieW<'_, Ucb0ieI2cSpec> {
UcalieW::new(self, 4)
}
#[doc = "Bit 5 - I2C NACK Condition interrupt enable"]
#[inline(always)]
pub fn ucnackie(&mut self) -> UcnackieW<'_, Ucb0ieI2cSpec> {
UcnackieW::new(self, 5)
}
#[doc = "Bit 6 - I2C Automatic stop assertion interrupt enable"]
#[inline(always)]
pub fn ucbcntie(&mut self) -> UcbcntieW<'_, Ucb0ieI2cSpec> {
UcbcntieW::new(self, 6)
}
#[doc = "Bit 7 - I2C Clock Low Timeout interrupt enable"]
#[inline(always)]
pub fn uccltoie(&mut self) -> UccltoieW<'_, Ucb0ieI2cSpec> {
UccltoieW::new(self, 7)
}
#[doc = "Bit 8 - I2C Receive Interrupt Enable 1"]
#[inline(always)]
pub fn ucrxie1(&mut self) -> Ucrxie1W<'_, Ucb0ieI2cSpec> {
Ucrxie1W::new(self, 8)
}
#[doc = "Bit 9 - I2C Transmit Interrupt Enable 1"]
#[inline(always)]
pub fn uctxie1(&mut self) -> Uctxie1W<'_, Ucb0ieI2cSpec> {
Uctxie1W::new(self, 9)
}
#[doc = "Bit 10 - I2C Receive Interrupt Enable 2"]
#[inline(always)]
pub fn ucrxie2(&mut self) -> Ucrxie2W<'_, Ucb0ieI2cSpec> {
Ucrxie2W::new(self, 10)
}
#[doc = "Bit 11 - I2C Transmit Interrupt Enable 2"]
#[inline(always)]
pub fn uctxie2(&mut self) -> Uctxie2W<'_, Ucb0ieI2cSpec> {
Uctxie2W::new(self, 11)
}
#[doc = "Bit 12 - I2C Receive Interrupt Enable 3"]
#[inline(always)]
pub fn ucrxie3(&mut self) -> Ucrxie3W<'_, Ucb0ieI2cSpec> {
Ucrxie3W::new(self, 12)
}
#[doc = "Bit 13 - I2C Transmit Interrupt Enable 3"]
#[inline(always)]
pub fn uctxie3(&mut self) -> Uctxie3W<'_, Ucb0ieI2cSpec> {
Uctxie3W::new(self, 13)
}
#[doc = "Bit 14 - I2C Bit 9 Position Interrupt Enable 3"]
#[inline(always)]
pub fn ucbit9ie(&mut self) -> Ucbit9ieW<'_, Ucb0ieI2cSpec> {
Ucbit9ieW::new(self, 14)
}
}
#[doc = "USCI B0 Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ie_i2c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ie_i2c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0ieI2cSpec;
impl crate::RegisterSpec for Ucb0ieI2cSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0ie_i2c::R`](R) reader structure"]
impl crate::Readable for Ucb0ieI2cSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0ie_i2c::W`](W) writer structure"]
impl crate::Writable for Ucb0ieI2cSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0IE_I2C to value 0"]
impl crate::Resettable for Ucb0ieI2cSpec {}
}
#[doc = "UCB0IFG (rw) register accessor: USCI B0 Interrupt Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ifg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ifg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0ifg`] module"]
#[doc(alias = "UCB0IFG")]
pub type Ucb0ifg = crate::Reg<ucb0ifg::Ucb0ifgSpec>;
#[doc = "USCI B0 Interrupt Flags Register"]
pub mod ucb0ifg {
#[doc = "Register `UCB0IFG` reader"]
pub type R = crate::R<Ucb0ifgSpec>;
#[doc = "Register `UCB0IFG` writer"]
pub type W = crate::W<Ucb0ifgSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI B0 Interrupt Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ifg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ifg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0ifgSpec;
impl crate::RegisterSpec for Ucb0ifgSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0ifg::R`](R) reader structure"]
impl crate::Readable for Ucb0ifgSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0ifg::W`](W) writer structure"]
impl crate::Writable for Ucb0ifgSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0IFG to value 0"]
impl crate::Resettable for Ucb0ifgSpec {}
}
#[doc = "UCB0IFG_I2C (rw) register accessor: USCI B0 Interrupt Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ifg_i2c::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ifg_i2c::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0ifg_i2c`] module"]
#[doc(alias = "UCB0IFG_I2C")]
pub type Ucb0ifgI2c = crate::Reg<ucb0ifg_i2c::Ucb0ifgI2cSpec>;
#[doc = "USCI B0 Interrupt Flags Register"]
pub mod ucb0ifg_i2c {
#[doc = "Register `UCB0IFG_I2C` reader"]
pub type R = crate::R<Ucb0ifgI2cSpec>;
#[doc = "Register `UCB0IFG_I2C` writer"]
pub type W = crate::W<Ucb0ifgI2cSpec>;
#[doc = "Field `UCRXIFG0` reader - I2C Receive Interrupt Flag 0"]
pub type Ucrxifg0R = crate::BitReader;
#[doc = "Field `UCRXIFG0` writer - I2C Receive Interrupt Flag 0"]
pub type Ucrxifg0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCTXIFG0` reader - I2C Transmit Interrupt Flag 0"]
pub type Uctxifg0R = crate::BitReader;
#[doc = "Field `UCTXIFG0` writer - I2C Transmit Interrupt Flag 0"]
pub type Uctxifg0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCSTTIFG` reader - I2C START Condition interrupt Flag"]
pub type UcsttifgR = crate::BitReader;
#[doc = "Field `UCSTTIFG` writer - I2C START Condition interrupt Flag"]
pub type UcsttifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCSTPIFG` reader - I2C STOP Condition interrupt Flag"]
pub type UcstpifgR = crate::BitReader;
#[doc = "Field `UCSTPIFG` writer - I2C STOP Condition interrupt Flag"]
pub type UcstpifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCALIFG` reader - I2C Arbitration Lost interrupt Flag"]
pub type UcalifgR = crate::BitReader;
#[doc = "Field `UCALIFG` writer - I2C Arbitration Lost interrupt Flag"]
pub type UcalifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCNACKIFG` reader - I2C NACK Condition interrupt Flag"]
pub type UcnackifgR = crate::BitReader;
#[doc = "Field `UCNACKIFG` writer - I2C NACK Condition interrupt Flag"]
pub type UcnackifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBCNTIFG` reader - I2C Byte counter interrupt flag"]
pub type UcbcntifgR = crate::BitReader;
#[doc = "Field `UCBCNTIFG` writer - I2C Byte counter interrupt flag"]
pub type UcbcntifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCCLTOIFG` reader - I2C Clock low Timeout interrupt Flag"]
pub type UccltoifgR = crate::BitReader;
#[doc = "Field `UCCLTOIFG` writer - I2C Clock low Timeout interrupt Flag"]
pub type UccltoifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCRXIFG1` reader - I2C Receive Interrupt Flag 1"]
pub type Ucrxifg1R = crate::BitReader;
#[doc = "Field `UCRXIFG1` writer - I2C Receive Interrupt Flag 1"]
pub type Ucrxifg1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCTXIFG1` reader - I2C Transmit Interrupt Flag 1"]
pub type Uctxifg1R = crate::BitReader;
#[doc = "Field `UCTXIFG1` writer - I2C Transmit Interrupt Flag 1"]
pub type Uctxifg1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCRXIFG2` reader - I2C Receive Interrupt Flag 2"]
pub type Ucrxifg2R = crate::BitReader;
#[doc = "Field `UCRXIFG2` writer - I2C Receive Interrupt Flag 2"]
pub type Ucrxifg2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCTXIFG2` reader - I2C Transmit Interrupt Flag 2"]
pub type Uctxifg2R = crate::BitReader;
#[doc = "Field `UCTXIFG2` writer - I2C Transmit Interrupt Flag 2"]
pub type Uctxifg2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCRXIFG3` reader - I2C Receive Interrupt Flag 3"]
pub type Ucrxifg3R = crate::BitReader;
#[doc = "Field `UCRXIFG3` writer - I2C Receive Interrupt Flag 3"]
pub type Ucrxifg3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCTXIFG3` reader - I2C Transmit Interrupt Flag 3"]
pub type Uctxifg3R = crate::BitReader;
#[doc = "Field `UCTXIFG3` writer - I2C Transmit Interrupt Flag 3"]
pub type Uctxifg3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCBIT9IFG` reader - I2C Bit 9 Possition Interrupt Flag 3"]
pub type Ucbit9ifgR = crate::BitReader;
#[doc = "Field `UCBIT9IFG` writer - I2C Bit 9 Possition Interrupt Flag 3"]
pub type Ucbit9ifgW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - I2C Receive Interrupt Flag 0"]
#[inline(always)]
pub fn ucrxifg0(&self) -> Ucrxifg0R {
Ucrxifg0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - I2C Transmit Interrupt Flag 0"]
#[inline(always)]
pub fn uctxifg0(&self) -> Uctxifg0R {
Uctxifg0R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - I2C START Condition interrupt Flag"]
#[inline(always)]
pub fn ucsttifg(&self) -> UcsttifgR {
UcsttifgR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - I2C STOP Condition interrupt Flag"]
#[inline(always)]
pub fn ucstpifg(&self) -> UcstpifgR {
UcstpifgR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - I2C Arbitration Lost interrupt Flag"]
#[inline(always)]
pub fn ucalifg(&self) -> UcalifgR {
UcalifgR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - I2C NACK Condition interrupt Flag"]
#[inline(always)]
pub fn ucnackifg(&self) -> UcnackifgR {
UcnackifgR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - I2C Byte counter interrupt flag"]
#[inline(always)]
pub fn ucbcntifg(&self) -> UcbcntifgR {
UcbcntifgR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - I2C Clock low Timeout interrupt Flag"]
#[inline(always)]
pub fn uccltoifg(&self) -> UccltoifgR {
UccltoifgR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - I2C Receive Interrupt Flag 1"]
#[inline(always)]
pub fn ucrxifg1(&self) -> Ucrxifg1R {
Ucrxifg1R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - I2C Transmit Interrupt Flag 1"]
#[inline(always)]
pub fn uctxifg1(&self) -> Uctxifg1R {
Uctxifg1R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - I2C Receive Interrupt Flag 2"]
#[inline(always)]
pub fn ucrxifg2(&self) -> Ucrxifg2R {
Ucrxifg2R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - I2C Transmit Interrupt Flag 2"]
#[inline(always)]
pub fn uctxifg2(&self) -> Uctxifg2R {
Uctxifg2R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - I2C Receive Interrupt Flag 3"]
#[inline(always)]
pub fn ucrxifg3(&self) -> Ucrxifg3R {
Ucrxifg3R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - I2C Transmit Interrupt Flag 3"]
#[inline(always)]
pub fn uctxifg3(&self) -> Uctxifg3R {
Uctxifg3R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - I2C Bit 9 Possition Interrupt Flag 3"]
#[inline(always)]
pub fn ucbit9ifg(&self) -> Ucbit9ifgR {
Ucbit9ifgR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - I2C Receive Interrupt Flag 0"]
#[inline(always)]
pub fn ucrxifg0(&mut self) -> Ucrxifg0W<'_, Ucb0ifgI2cSpec> {
Ucrxifg0W::new(self, 0)
}
#[doc = "Bit 1 - I2C Transmit Interrupt Flag 0"]
#[inline(always)]
pub fn uctxifg0(&mut self) -> Uctxifg0W<'_, Ucb0ifgI2cSpec> {
Uctxifg0W::new(self, 1)
}
#[doc = "Bit 2 - I2C START Condition interrupt Flag"]
#[inline(always)]
pub fn ucsttifg(&mut self) -> UcsttifgW<'_, Ucb0ifgI2cSpec> {
UcsttifgW::new(self, 2)
}
#[doc = "Bit 3 - I2C STOP Condition interrupt Flag"]
#[inline(always)]
pub fn ucstpifg(&mut self) -> UcstpifgW<'_, Ucb0ifgI2cSpec> {
UcstpifgW::new(self, 3)
}
#[doc = "Bit 4 - I2C Arbitration Lost interrupt Flag"]
#[inline(always)]
pub fn ucalifg(&mut self) -> UcalifgW<'_, Ucb0ifgI2cSpec> {
UcalifgW::new(self, 4)
}
#[doc = "Bit 5 - I2C NACK Condition interrupt Flag"]
#[inline(always)]
pub fn ucnackifg(&mut self) -> UcnackifgW<'_, Ucb0ifgI2cSpec> {
UcnackifgW::new(self, 5)
}
#[doc = "Bit 6 - I2C Byte counter interrupt flag"]
#[inline(always)]
pub fn ucbcntifg(&mut self) -> UcbcntifgW<'_, Ucb0ifgI2cSpec> {
UcbcntifgW::new(self, 6)
}
#[doc = "Bit 7 - I2C Clock low Timeout interrupt Flag"]
#[inline(always)]
pub fn uccltoifg(&mut self) -> UccltoifgW<'_, Ucb0ifgI2cSpec> {
UccltoifgW::new(self, 7)
}
#[doc = "Bit 8 - I2C Receive Interrupt Flag 1"]
#[inline(always)]
pub fn ucrxifg1(&mut self) -> Ucrxifg1W<'_, Ucb0ifgI2cSpec> {
Ucrxifg1W::new(self, 8)
}
#[doc = "Bit 9 - I2C Transmit Interrupt Flag 1"]
#[inline(always)]
pub fn uctxifg1(&mut self) -> Uctxifg1W<'_, Ucb0ifgI2cSpec> {
Uctxifg1W::new(self, 9)
}
#[doc = "Bit 10 - I2C Receive Interrupt Flag 2"]
#[inline(always)]
pub fn ucrxifg2(&mut self) -> Ucrxifg2W<'_, Ucb0ifgI2cSpec> {
Ucrxifg2W::new(self, 10)
}
#[doc = "Bit 11 - I2C Transmit Interrupt Flag 2"]
#[inline(always)]
pub fn uctxifg2(&mut self) -> Uctxifg2W<'_, Ucb0ifgI2cSpec> {
Uctxifg2W::new(self, 11)
}
#[doc = "Bit 12 - I2C Receive Interrupt Flag 3"]
#[inline(always)]
pub fn ucrxifg3(&mut self) -> Ucrxifg3W<'_, Ucb0ifgI2cSpec> {
Ucrxifg3W::new(self, 12)
}
#[doc = "Bit 13 - I2C Transmit Interrupt Flag 3"]
#[inline(always)]
pub fn uctxifg3(&mut self) -> Uctxifg3W<'_, Ucb0ifgI2cSpec> {
Uctxifg3W::new(self, 13)
}
#[doc = "Bit 14 - I2C Bit 9 Possition Interrupt Flag 3"]
#[inline(always)]
pub fn ucbit9ifg(&mut self) -> Ucbit9ifgW<'_, Ucb0ifgI2cSpec> {
Ucbit9ifgW::new(self, 14)
}
}
#[doc = "USCI B0 Interrupt Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ifg_i2c::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ifg_i2c::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0ifgI2cSpec;
impl crate::RegisterSpec for Ucb0ifgI2cSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0ifg_i2c::R`](R) reader structure"]
impl crate::Readable for Ucb0ifgI2cSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0ifg_i2c::W`](W) writer structure"]
impl crate::Writable for Ucb0ifgI2cSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0IFG_I2C to value 0"]
impl crate::Resettable for Ucb0ifgI2cSpec {}
}
#[doc = "UCB0IV (rw) register accessor: USCI B0 Interrupt Vector Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0iv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0iv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0iv`] module"]
#[doc(alias = "UCB0IV")]
pub type Ucb0iv = crate::Reg<ucb0iv::Ucb0ivSpec>;
#[doc = "USCI B0 Interrupt Vector Register"]
pub mod ucb0iv {
#[doc = "Register `UCB0IV` reader"]
pub type R = crate::R<Ucb0ivSpec>;
#[doc = "Register `UCB0IV` writer"]
pub type W = crate::W<Ucb0ivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI B0 Interrupt Vector Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0iv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0iv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0ivSpec;
impl crate::RegisterSpec for Ucb0ivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0iv::R`](R) reader structure"]
impl crate::Readable for Ucb0ivSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0iv::W`](W) writer structure"]
impl crate::Writable for Ucb0ivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0IV to value 0"]
impl crate::Resettable for Ucb0ivSpec {}
}
}
#[doc = "USCI_B0 SPI Mode"]
pub type UsciB0SpiMode = crate::Periph<usci_b0_spi_mode::RegisterBlock, 0x0640>;
impl core::fmt::Debug for UsciB0SpiMode {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UsciB0SpiMode").finish()
}
}
#[doc = "USCI_B0 SPI Mode"]
pub mod usci_b0_spi_mode {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
ucb0ctl1_spi: Ucb0ctl1Spi,
ucb0ctl0_spi: Ucb0ctl0Spi,
_reserved2: [u8; 0x04],
ucb0br0_spi: Ucb0br0Spi,
ucb0br1_spi: Ucb0br1Spi,
_reserved4: [u8; 0x04],
ucb0rxbuf_spi: Ucb0rxbufSpi,
ucb0txbuf_spi: Ucb0txbufSpi,
_reserved6: [u8; 0x1a],
ucb0ie_spi: Ucb0ieSpi,
ucb0ifg_spi: Ucb0ifgSpi,
ucb0iv_spi: Ucb0ivSpi,
}
impl RegisterBlock {
#[doc = "0x00 - USCI B0 Control Register 1"]
#[inline(always)]
pub const fn ucb0ctl1_spi(&self) -> &Ucb0ctl1Spi {
&self.ucb0ctl1_spi
}
#[doc = "0x01 - USCI B0 Control Register 0"]
#[inline(always)]
pub const fn ucb0ctl0_spi(&self) -> &Ucb0ctl0Spi {
&self.ucb0ctl0_spi
}
#[doc = "0x06 - USCI B0 Baud Rate 0"]
#[inline(always)]
pub const fn ucb0br0_spi(&self) -> &Ucb0br0Spi {
&self.ucb0br0_spi
}
#[doc = "0x07 - USCI B0 Baud Rate 1"]
#[inline(always)]
pub const fn ucb0br1_spi(&self) -> &Ucb0br1Spi {
&self.ucb0br1_spi
}
#[doc = "0x0c - USCI B0 Receive Buffer"]
#[inline(always)]
pub const fn ucb0rxbuf_spi(&self) -> &Ucb0rxbufSpi {
&self.ucb0rxbuf_spi
}
#[doc = "0x0e - USCI B0 Transmit Buffer"]
#[inline(always)]
pub const fn ucb0txbuf_spi(&self) -> &Ucb0txbufSpi {
&self.ucb0txbuf_spi
}
#[doc = "0x2a - USCI B0 Interrupt Enable Register"]
#[inline(always)]
pub const fn ucb0ie_spi(&self) -> &Ucb0ieSpi {
&self.ucb0ie_spi
}
#[doc = "0x2c - USCI B0 Interrupt Flags Register"]
#[inline(always)]
pub const fn ucb0ifg_spi(&self) -> &Ucb0ifgSpi {
&self.ucb0ifg_spi
}
#[doc = "0x2e - USCI B0 Interrupt Vector Register"]
#[inline(always)]
pub const fn ucb0iv_spi(&self) -> &Ucb0ivSpi {
&self.ucb0iv_spi
}
}
#[doc = "UCB0CTL1_SPI (rw) register accessor: USCI B0 Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ctl1_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ctl1_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0ctl1_spi`] module"]
#[doc(alias = "UCB0CTL1_SPI")]
pub type Ucb0ctl1Spi = crate::Reg<ucb0ctl1_spi::Ucb0ctl1SpiSpec>;
#[doc = "USCI B0 Control Register 1"]
pub mod ucb0ctl1_spi {
#[doc = "Register `UCB0CTL1_SPI` reader"]
pub type R = crate::R<Ucb0ctl1SpiSpec>;
#[doc = "Register `UCB0CTL1_SPI` writer"]
pub type W = crate::W<Ucb0ctl1SpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI B0 Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ctl1_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ctl1_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0ctl1SpiSpec;
impl crate::RegisterSpec for Ucb0ctl1SpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`ucb0ctl1_spi::R`](R) reader structure"]
impl crate::Readable for Ucb0ctl1SpiSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0ctl1_spi::W`](W) writer structure"]
impl crate::Writable for Ucb0ctl1SpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0CTL1_SPI to value 0"]
impl crate::Resettable for Ucb0ctl1SpiSpec {}
}
#[doc = "UCB0CTL0_SPI (rw) register accessor: USCI B0 Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ctl0_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ctl0_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0ctl0_spi`] module"]
#[doc(alias = "UCB0CTL0_SPI")]
pub type Ucb0ctl0Spi = crate::Reg<ucb0ctl0_spi::Ucb0ctl0SpiSpec>;
#[doc = "USCI B0 Control Register 0"]
pub mod ucb0ctl0_spi {
#[doc = "Register `UCB0CTL0_SPI` reader"]
pub type R = crate::R<Ucb0ctl0SpiSpec>;
#[doc = "Register `UCB0CTL0_SPI` writer"]
pub type W = crate::W<Ucb0ctl0SpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI B0 Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ctl0_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ctl0_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0ctl0SpiSpec;
impl crate::RegisterSpec for Ucb0ctl0SpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`ucb0ctl0_spi::R`](R) reader structure"]
impl crate::Readable for Ucb0ctl0SpiSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0ctl0_spi::W`](W) writer structure"]
impl crate::Writable for Ucb0ctl0SpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0CTL0_SPI to value 0"]
impl crate::Resettable for Ucb0ctl0SpiSpec {}
}
#[doc = "UCB0BR0_SPI (rw) register accessor: USCI B0 Baud Rate 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0br0_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0br0_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0br0_spi`] module"]
#[doc(alias = "UCB0BR0_SPI")]
pub type Ucb0br0Spi = crate::Reg<ucb0br0_spi::Ucb0br0SpiSpec>;
#[doc = "USCI B0 Baud Rate 0"]
pub mod ucb0br0_spi {
#[doc = "Register `UCB0BR0_SPI` reader"]
pub type R = crate::R<Ucb0br0SpiSpec>;
#[doc = "Register `UCB0BR0_SPI` writer"]
pub type W = crate::W<Ucb0br0SpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI B0 Baud Rate 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0br0_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0br0_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0br0SpiSpec;
impl crate::RegisterSpec for Ucb0br0SpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`ucb0br0_spi::R`](R) reader structure"]
impl crate::Readable for Ucb0br0SpiSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0br0_spi::W`](W) writer structure"]
impl crate::Writable for Ucb0br0SpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0BR0_SPI to value 0"]
impl crate::Resettable for Ucb0br0SpiSpec {}
}
#[doc = "UCB0BR1_SPI (rw) register accessor: USCI B0 Baud Rate 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0br1_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0br1_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0br1_spi`] module"]
#[doc(alias = "UCB0BR1_SPI")]
pub type Ucb0br1Spi = crate::Reg<ucb0br1_spi::Ucb0br1SpiSpec>;
#[doc = "USCI B0 Baud Rate 1"]
pub mod ucb0br1_spi {
#[doc = "Register `UCB0BR1_SPI` reader"]
pub type R = crate::R<Ucb0br1SpiSpec>;
#[doc = "Register `UCB0BR1_SPI` writer"]
pub type W = crate::W<Ucb0br1SpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI B0 Baud Rate 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0br1_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0br1_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0br1SpiSpec;
impl crate::RegisterSpec for Ucb0br1SpiSpec {
type Ux = u8;
}
#[doc = "`read()` method returns [`ucb0br1_spi::R`](R) reader structure"]
impl crate::Readable for Ucb0br1SpiSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0br1_spi::W`](W) writer structure"]
impl crate::Writable for Ucb0br1SpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0BR1_SPI to value 0"]
impl crate::Resettable for Ucb0br1SpiSpec {}
}
#[doc = "UCB0RXBUF_SPI (rw) register accessor: USCI B0 Receive Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0rxbuf_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0rxbuf_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0rxbuf_spi`] module"]
#[doc(alias = "UCB0RXBUF_SPI")]
pub type Ucb0rxbufSpi = crate::Reg<ucb0rxbuf_spi::Ucb0rxbufSpiSpec>;
#[doc = "USCI B0 Receive Buffer"]
pub mod ucb0rxbuf_spi {
#[doc = "Register `UCB0RXBUF_SPI` reader"]
pub type R = crate::R<Ucb0rxbufSpiSpec>;
#[doc = "Register `UCB0RXBUF_SPI` writer"]
pub type W = crate::W<Ucb0rxbufSpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI B0 Receive Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0rxbuf_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0rxbuf_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0rxbufSpiSpec;
impl crate::RegisterSpec for Ucb0rxbufSpiSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0rxbuf_spi::R`](R) reader structure"]
impl crate::Readable for Ucb0rxbufSpiSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0rxbuf_spi::W`](W) writer structure"]
impl crate::Writable for Ucb0rxbufSpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0RXBUF_SPI to value 0"]
impl crate::Resettable for Ucb0rxbufSpiSpec {}
}
#[doc = "UCB0TXBUF_SPI (rw) register accessor: USCI B0 Transmit Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0txbuf_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0txbuf_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0txbuf_spi`] module"]
#[doc(alias = "UCB0TXBUF_SPI")]
pub type Ucb0txbufSpi = crate::Reg<ucb0txbuf_spi::Ucb0txbufSpiSpec>;
#[doc = "USCI B0 Transmit Buffer"]
pub mod ucb0txbuf_spi {
#[doc = "Register `UCB0TXBUF_SPI` reader"]
pub type R = crate::R<Ucb0txbufSpiSpec>;
#[doc = "Register `UCB0TXBUF_SPI` writer"]
pub type W = crate::W<Ucb0txbufSpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI B0 Transmit Buffer\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0txbuf_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0txbuf_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0txbufSpiSpec;
impl crate::RegisterSpec for Ucb0txbufSpiSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0txbuf_spi::R`](R) reader structure"]
impl crate::Readable for Ucb0txbufSpiSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0txbuf_spi::W`](W) writer structure"]
impl crate::Writable for Ucb0txbufSpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0TXBUF_SPI to value 0"]
impl crate::Resettable for Ucb0txbufSpiSpec {}
}
#[doc = "UCB0IE_SPI (rw) register accessor: USCI B0 Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ie_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ie_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0ie_spi`] module"]
#[doc(alias = "UCB0IE_SPI")]
pub type Ucb0ieSpi = crate::Reg<ucb0ie_spi::Ucb0ieSpiSpec>;
#[doc = "USCI B0 Interrupt Enable Register"]
pub mod ucb0ie_spi {
#[doc = "Register `UCB0IE_SPI` reader"]
pub type R = crate::R<Ucb0ieSpiSpec>;
#[doc = "Register `UCB0IE_SPI` writer"]
pub type W = crate::W<Ucb0ieSpiSpec>;
#[doc = "Field `UCRXIE` reader - USCI Receive Interrupt Enable"]
pub type UcrxieR = crate::BitReader;
#[doc = "Field `UCRXIE` writer - USCI Receive Interrupt Enable"]
pub type UcrxieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCTXIE` reader - USCI Transmit Interrupt Enable"]
pub type UctxieR = crate::BitReader;
#[doc = "Field `UCTXIE` writer - USCI Transmit Interrupt Enable"]
pub type UctxieW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - USCI Receive Interrupt Enable"]
#[inline(always)]
pub fn ucrxie(&self) -> UcrxieR {
UcrxieR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - USCI Transmit Interrupt Enable"]
#[inline(always)]
pub fn uctxie(&self) -> UctxieR {
UctxieR::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - USCI Receive Interrupt Enable"]
#[inline(always)]
pub fn ucrxie(&mut self) -> UcrxieW<'_, Ucb0ieSpiSpec> {
UcrxieW::new(self, 0)
}
#[doc = "Bit 1 - USCI Transmit Interrupt Enable"]
#[inline(always)]
pub fn uctxie(&mut self) -> UctxieW<'_, Ucb0ieSpiSpec> {
UctxieW::new(self, 1)
}
}
#[doc = "USCI B0 Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ie_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ie_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0ieSpiSpec;
impl crate::RegisterSpec for Ucb0ieSpiSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0ie_spi::R`](R) reader structure"]
impl crate::Readable for Ucb0ieSpiSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0ie_spi::W`](W) writer structure"]
impl crate::Writable for Ucb0ieSpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0IE_SPI to value 0"]
impl crate::Resettable for Ucb0ieSpiSpec {}
}
#[doc = "UCB0IFG_SPI (rw) register accessor: USCI B0 Interrupt Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ifg_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ifg_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0ifg_spi`] module"]
#[doc(alias = "UCB0IFG_SPI")]
pub type Ucb0ifgSpi = crate::Reg<ucb0ifg_spi::Ucb0ifgSpiSpec>;
#[doc = "USCI B0 Interrupt Flags Register"]
pub mod ucb0ifg_spi {
#[doc = "Register `UCB0IFG_SPI` reader"]
pub type R = crate::R<Ucb0ifgSpiSpec>;
#[doc = "Register `UCB0IFG_SPI` writer"]
pub type W = crate::W<Ucb0ifgSpiSpec>;
#[doc = "Field `UCRXIFG` reader - SPI Receive Interrupt Flag"]
pub type UcrxifgR = crate::BitReader;
#[doc = "Field `UCRXIFG` writer - SPI Receive Interrupt Flag"]
pub type UcrxifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UCTXIFG` reader - SPI Transmit Interrupt Flag"]
pub type UctxifgR = crate::BitReader;
#[doc = "Field `UCTXIFG` writer - SPI Transmit Interrupt Flag"]
pub type UctxifgW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - SPI Receive Interrupt Flag"]
#[inline(always)]
pub fn ucrxifg(&self) -> UcrxifgR {
UcrxifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - SPI Transmit Interrupt Flag"]
#[inline(always)]
pub fn uctxifg(&self) -> UctxifgR {
UctxifgR::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - SPI Receive Interrupt Flag"]
#[inline(always)]
pub fn ucrxifg(&mut self) -> UcrxifgW<'_, Ucb0ifgSpiSpec> {
UcrxifgW::new(self, 0)
}
#[doc = "Bit 1 - SPI Transmit Interrupt Flag"]
#[inline(always)]
pub fn uctxifg(&mut self) -> UctxifgW<'_, Ucb0ifgSpiSpec> {
UctxifgW::new(self, 1)
}
}
#[doc = "USCI B0 Interrupt Flags Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0ifg_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0ifg_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0ifgSpiSpec;
impl crate::RegisterSpec for Ucb0ifgSpiSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0ifg_spi::R`](R) reader structure"]
impl crate::Readable for Ucb0ifgSpiSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0ifg_spi::W`](W) writer structure"]
impl crate::Writable for Ucb0ifgSpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0IFG_SPI to value 0"]
impl crate::Resettable for Ucb0ifgSpiSpec {}
}
#[doc = "UCB0IV_SPI (rw) register accessor: USCI B0 Interrupt Vector Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0iv_spi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0iv_spi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ucb0iv_spi`] module"]
#[doc(alias = "UCB0IV_SPI")]
pub type Ucb0ivSpi = crate::Reg<ucb0iv_spi::Ucb0ivSpiSpec>;
#[doc = "USCI B0 Interrupt Vector Register"]
pub mod ucb0iv_spi {
#[doc = "Register `UCB0IV_SPI` reader"]
pub type R = crate::R<Ucb0ivSpiSpec>;
#[doc = "Register `UCB0IV_SPI` writer"]
pub type W = crate::W<Ucb0ivSpiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "USCI B0 Interrupt Vector Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ucb0iv_spi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ucb0iv_spi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ucb0ivSpiSpec;
impl crate::RegisterSpec for Ucb0ivSpiSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ucb0iv_spi::R`](R) reader structure"]
impl crate::Readable for Ucb0ivSpiSpec {}
#[doc = "`write(|w| ..)` method takes [`ucb0iv_spi::W`](W) writer structure"]
impl crate::Writable for Ucb0ivSpiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UCB0IV_SPI to value 0"]
impl crate::Resettable for Ucb0ivSpiSpec {}
}
}
#[doc = "SFR Special Function Registers"]
pub type Sfr = crate::Periph<sfr::RegisterBlock, 0x0100>;
impl core::fmt::Debug for Sfr {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Sfr").finish()
}
}
#[doc = "SFR Special Function Registers"]
pub mod sfr {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
sfrie1: Sfrie1,
sfrifg1: Sfrifg1,
sfrrpcr: Sfrrpcr,
}
impl RegisterBlock {
#[doc = "0x00 - Interrupt Enable 1"]
#[inline(always)]
pub const fn sfrie1(&self) -> &Sfrie1 {
&self.sfrie1
}
#[doc = "0x02 - Interrupt Flag 1"]
#[inline(always)]
pub const fn sfrifg1(&self) -> &Sfrifg1 {
&self.sfrifg1
}
#[doc = "0x04 - RESET Pin Control Register"]
#[inline(always)]
pub const fn sfrrpcr(&self) -> &Sfrrpcr {
&self.sfrrpcr
}
}
#[doc = "SFRIE1 (rw) register accessor: Interrupt Enable 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sfrie1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfrie1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfrie1`] module"]
#[doc(alias = "SFRIE1")]
pub type Sfrie1 = crate::Reg<sfrie1::Sfrie1Spec>;
#[doc = "Interrupt Enable 1"]
pub mod sfrie1 {
#[doc = "Register `SFRIE1` reader"]
pub type R = crate::R<Sfrie1Spec>;
#[doc = "Register `SFRIE1` writer"]
pub type W = crate::W<Sfrie1Spec>;
#[doc = "Field `WDTIE` reader - WDT Interrupt Enable"]
pub type WdtieR = crate::BitReader;
#[doc = "Field `WDTIE` writer - WDT Interrupt Enable"]
pub type WdtieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFIE` reader - Osc Fault Enable"]
pub type OfieR = crate::BitReader;
#[doc = "Field `OFIE` writer - Osc Fault Enable"]
pub type OfieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `VMAIE` reader - Vacant Memory Interrupt Enable"]
pub type VmaieR = crate::BitReader;
#[doc = "Field `VMAIE` writer - Vacant Memory Interrupt Enable"]
pub type VmaieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NMIIE` reader - NMI Interrupt Enable"]
pub type NmiieR = crate::BitReader;
#[doc = "Field `NMIIE` writer - NMI Interrupt Enable"]
pub type NmiieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `JMBINIE` reader - JTAG Mail Box input Interrupt Enable"]
pub type JmbinieR = crate::BitReader;
#[doc = "Field `JMBINIE` writer - JTAG Mail Box input Interrupt Enable"]
pub type JmbinieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `JMBOUTIE` reader - JTAG Mail Box output Interrupt Enable"]
pub type JmboutieR = crate::BitReader;
#[doc = "Field `JMBOUTIE` writer - JTAG Mail Box output Interrupt Enable"]
pub type JmboutieW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - WDT Interrupt Enable"]
#[inline(always)]
pub fn wdtie(&self) -> WdtieR {
WdtieR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Osc Fault Enable"]
#[inline(always)]
pub fn ofie(&self) -> OfieR {
OfieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 3 - Vacant Memory Interrupt Enable"]
#[inline(always)]
pub fn vmaie(&self) -> VmaieR {
VmaieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - NMI Interrupt Enable"]
#[inline(always)]
pub fn nmiie(&self) -> NmiieR {
NmiieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - JTAG Mail Box input Interrupt Enable"]
#[inline(always)]
pub fn jmbinie(&self) -> JmbinieR {
JmbinieR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - JTAG Mail Box output Interrupt Enable"]
#[inline(always)]
pub fn jmboutie(&self) -> JmboutieR {
JmboutieR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - WDT Interrupt Enable"]
#[inline(always)]
pub fn wdtie(&mut self) -> WdtieW<'_, Sfrie1Spec> {
WdtieW::new(self, 0)
}
#[doc = "Bit 1 - Osc Fault Enable"]
#[inline(always)]
pub fn ofie(&mut self) -> OfieW<'_, Sfrie1Spec> {
OfieW::new(self, 1)
}
#[doc = "Bit 3 - Vacant Memory Interrupt Enable"]
#[inline(always)]
pub fn vmaie(&mut self) -> VmaieW<'_, Sfrie1Spec> {
VmaieW::new(self, 3)
}
#[doc = "Bit 4 - NMI Interrupt Enable"]
#[inline(always)]
pub fn nmiie(&mut self) -> NmiieW<'_, Sfrie1Spec> {
NmiieW::new(self, 4)
}
#[doc = "Bit 6 - JTAG Mail Box input Interrupt Enable"]
#[inline(always)]
pub fn jmbinie(&mut self) -> JmbinieW<'_, Sfrie1Spec> {
JmbinieW::new(self, 6)
}
#[doc = "Bit 7 - JTAG Mail Box output Interrupt Enable"]
#[inline(always)]
pub fn jmboutie(&mut self) -> JmboutieW<'_, Sfrie1Spec> {
JmboutieW::new(self, 7)
}
}
#[doc = "Interrupt Enable 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sfrie1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfrie1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sfrie1Spec;
impl crate::RegisterSpec for Sfrie1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`sfrie1::R`](R) reader structure"]
impl crate::Readable for Sfrie1Spec {}
#[doc = "`write(|w| ..)` method takes [`sfrie1::W`](W) writer structure"]
impl crate::Writable for Sfrie1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SFRIE1 to value 0"]
impl crate::Resettable for Sfrie1Spec {}
}
#[doc = "SFRIFG1 (rw) register accessor: Interrupt Flag 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sfrifg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfrifg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfrifg1`] module"]
#[doc(alias = "SFRIFG1")]
pub type Sfrifg1 = crate::Reg<sfrifg1::Sfrifg1Spec>;
#[doc = "Interrupt Flag 1"]
pub mod sfrifg1 {
#[doc = "Register `SFRIFG1` reader"]
pub type R = crate::R<Sfrifg1Spec>;
#[doc = "Register `SFRIFG1` writer"]
pub type W = crate::W<Sfrifg1Spec>;
#[doc = "Field `WDTIFG` reader - WDT Interrupt Flag"]
pub type WdtifgR = crate::BitReader;
#[doc = "Field `WDTIFG` writer - WDT Interrupt Flag"]
pub type WdtifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OFIFG` reader - Osc Fault Flag"]
pub type OfifgR = crate::BitReader;
#[doc = "Field `OFIFG` writer - Osc Fault Flag"]
pub type OfifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `VMAIFG` reader - Vacant Memory Interrupt Flag"]
pub type VmaifgR = crate::BitReader;
#[doc = "Field `VMAIFG` writer - Vacant Memory Interrupt Flag"]
pub type VmaifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NMIIFG` reader - NMI Interrupt Flag"]
pub type NmiifgR = crate::BitReader;
#[doc = "Field `NMIIFG` writer - NMI Interrupt Flag"]
pub type NmiifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `JMBINIFG` reader - JTAG Mail Box input Interrupt Flag"]
pub type JmbinifgR = crate::BitReader;
#[doc = "Field `JMBINIFG` writer - JTAG Mail Box input Interrupt Flag"]
pub type JmbinifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `JMBOUTIFG` reader - JTAG Mail Box output Interrupt Flag"]
pub type JmboutifgR = crate::BitReader;
#[doc = "Field `JMBOUTIFG` writer - JTAG Mail Box output Interrupt Flag"]
pub type JmboutifgW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - WDT Interrupt Flag"]
#[inline(always)]
pub fn wdtifg(&self) -> WdtifgR {
WdtifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Osc Fault Flag"]
#[inline(always)]
pub fn ofifg(&self) -> OfifgR {
OfifgR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 3 - Vacant Memory Interrupt Flag"]
#[inline(always)]
pub fn vmaifg(&self) -> VmaifgR {
VmaifgR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - NMI Interrupt Flag"]
#[inline(always)]
pub fn nmiifg(&self) -> NmiifgR {
NmiifgR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - JTAG Mail Box input Interrupt Flag"]
#[inline(always)]
pub fn jmbinifg(&self) -> JmbinifgR {
JmbinifgR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - JTAG Mail Box output Interrupt Flag"]
#[inline(always)]
pub fn jmboutifg(&self) -> JmboutifgR {
JmboutifgR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - WDT Interrupt Flag"]
#[inline(always)]
pub fn wdtifg(&mut self) -> WdtifgW<'_, Sfrifg1Spec> {
WdtifgW::new(self, 0)
}
#[doc = "Bit 1 - Osc Fault Flag"]
#[inline(always)]
pub fn ofifg(&mut self) -> OfifgW<'_, Sfrifg1Spec> {
OfifgW::new(self, 1)
}
#[doc = "Bit 3 - Vacant Memory Interrupt Flag"]
#[inline(always)]
pub fn vmaifg(&mut self) -> VmaifgW<'_, Sfrifg1Spec> {
VmaifgW::new(self, 3)
}
#[doc = "Bit 4 - NMI Interrupt Flag"]
#[inline(always)]
pub fn nmiifg(&mut self) -> NmiifgW<'_, Sfrifg1Spec> {
NmiifgW::new(self, 4)
}
#[doc = "Bit 6 - JTAG Mail Box input Interrupt Flag"]
#[inline(always)]
pub fn jmbinifg(&mut self) -> JmbinifgW<'_, Sfrifg1Spec> {
JmbinifgW::new(self, 6)
}
#[doc = "Bit 7 - JTAG Mail Box output Interrupt Flag"]
#[inline(always)]
pub fn jmboutifg(&mut self) -> JmboutifgW<'_, Sfrifg1Spec> {
JmboutifgW::new(self, 7)
}
}
#[doc = "Interrupt Flag 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sfrifg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfrifg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sfrifg1Spec;
impl crate::RegisterSpec for Sfrifg1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`sfrifg1::R`](R) reader structure"]
impl crate::Readable for Sfrifg1Spec {}
#[doc = "`write(|w| ..)` method takes [`sfrifg1::W`](W) writer structure"]
impl crate::Writable for Sfrifg1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SFRIFG1 to value 0"]
impl crate::Resettable for Sfrifg1Spec {}
}
#[doc = "SFRRPCR (rw) register accessor: RESET Pin Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sfrrpcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfrrpcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfrrpcr`] module"]
#[doc(alias = "SFRRPCR")]
pub type Sfrrpcr = crate::Reg<sfrrpcr::SfrrpcrSpec>;
#[doc = "RESET Pin Control Register"]
pub mod sfrrpcr {
#[doc = "Register `SFRRPCR` reader"]
pub type R = crate::R<SfrrpcrSpec>;
#[doc = "Register `SFRRPCR` writer"]
pub type W = crate::W<SfrrpcrSpec>;
#[doc = "Field `SYSNMI` reader - NMI select"]
pub type SysnmiR = crate::BitReader;
#[doc = "Field `SYSNMI` writer - NMI select"]
pub type SysnmiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SYSNMIIES` reader - NMI edge select"]
pub type SysnmiiesR = crate::BitReader;
#[doc = "Field `SYSNMIIES` writer - NMI edge select"]
pub type SysnmiiesW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SYSRSTUP` reader - RESET Pin pull down/up select"]
pub type SysrstupR = crate::BitReader;
#[doc = "Field `SYSRSTUP` writer - RESET Pin pull down/up select"]
pub type SysrstupW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SYSRSTRE` reader - RESET Pin Resistor enable"]
pub type SysrstreR = crate::BitReader;
#[doc = "Field `SYSRSTRE` writer - RESET Pin Resistor enable"]
pub type SysrstreW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - NMI select"]
#[inline(always)]
pub fn sysnmi(&self) -> SysnmiR {
SysnmiR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - NMI edge select"]
#[inline(always)]
pub fn sysnmiies(&self) -> SysnmiiesR {
SysnmiiesR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RESET Pin pull down/up select"]
#[inline(always)]
pub fn sysrstup(&self) -> SysrstupR {
SysrstupR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RESET Pin Resistor enable"]
#[inline(always)]
pub fn sysrstre(&self) -> SysrstreR {
SysrstreR::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - NMI select"]
#[inline(always)]
pub fn sysnmi(&mut self) -> SysnmiW<'_, SfrrpcrSpec> {
SysnmiW::new(self, 0)
}
#[doc = "Bit 1 - NMI edge select"]
#[inline(always)]
pub fn sysnmiies(&mut self) -> SysnmiiesW<'_, SfrrpcrSpec> {
SysnmiiesW::new(self, 1)
}
#[doc = "Bit 2 - RESET Pin pull down/up select"]
#[inline(always)]
pub fn sysrstup(&mut self) -> SysrstupW<'_, SfrrpcrSpec> {
SysrstupW::new(self, 2)
}
#[doc = "Bit 3 - RESET Pin Resistor enable"]
#[inline(always)]
pub fn sysrstre(&mut self) -> SysrstreW<'_, SfrrpcrSpec> {
SysrstreW::new(self, 3)
}
}
#[doc = "RESET Pin Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sfrrpcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfrrpcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SfrrpcrSpec;
impl crate::RegisterSpec for SfrrpcrSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`sfrrpcr::R`](R) reader structure"]
impl crate::Readable for SfrrpcrSpec {}
#[doc = "`write(|w| ..)` method takes [`sfrrpcr::W`](W) writer structure"]
impl crate::Writable for SfrrpcrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SFRRPCR to value 0"]
impl crate::Resettable for SfrrpcrSpec {}
}
}
#[doc = "PMM Power Management System"]
pub type Pmm = crate::Periph<pmm::RegisterBlock, 0x0120>;
impl core::fmt::Debug for Pmm {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Pmm").finish()
}
}
#[doc = "PMM Power Management System"]
pub mod pmm {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
pmmctl0: Pmmctl0,
_reserved1: [u8; 0x08],
pmmifg: Pmmifg,
_reserved2: [u8; 0x04],
pm5ctl0: Pm5ctl0,
}
impl RegisterBlock {
#[doc = "0x00 - PMM Control 0"]
#[inline(always)]
pub const fn pmmctl0(&self) -> &Pmmctl0 {
&self.pmmctl0
}
#[doc = "0x0a - PMM Interrupt Flag"]
#[inline(always)]
pub const fn pmmifg(&self) -> &Pmmifg {
&self.pmmifg
}
#[doc = "0x10 - PMM Power Mode 5 Control Register 0"]
#[inline(always)]
pub const fn pm5ctl0(&self) -> &Pm5ctl0 {
&self.pm5ctl0
}
}
#[doc = "PMMCTL0 (rw) register accessor: PMM Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pmmctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmmctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmmctl0`] module"]
#[doc(alias = "PMMCTL0")]
pub type Pmmctl0 = crate::Reg<pmmctl0::Pmmctl0Spec>;
#[doc = "PMM Control 0"]
pub mod pmmctl0 {
#[doc = "Register `PMMCTL0` reader"]
pub type R = crate::R<Pmmctl0Spec>;
#[doc = "Register `PMMCTL0` writer"]
pub type W = crate::W<Pmmctl0Spec>;
#[doc = "Field `PMMSWBOR` reader - PMM Software BOR"]
pub type PmmswborR = crate::BitReader;
#[doc = "Field `PMMSWBOR` writer - PMM Software BOR"]
pub type PmmswborW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PMMSWPOR` reader - PMM Software POR"]
pub type PmmswporR = crate::BitReader;
#[doc = "Field `PMMSWPOR` writer - PMM Software POR"]
pub type PmmswporW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PMMREGOFF` reader - PMM Turn Regulator off"]
pub type PmmregoffR = crate::BitReader;
#[doc = "Field `PMMREGOFF` writer - PMM Turn Regulator off"]
pub type PmmregoffW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SVSHE` reader - SVS high side enable"]
pub type SvsheR = crate::BitReader;
#[doc = "Field `SVSHE` writer - SVS high side enable"]
pub type SvsheW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PMMLPRST` reader - PMM Low-Power Reset Enable"]
pub type PmmlprstR = crate::BitReader;
#[doc = "Field `PMMLPRST` writer - PMM Low-Power Reset Enable"]
pub type PmmlprstW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 2 - PMM Software BOR"]
#[inline(always)]
pub fn pmmswbor(&self) -> PmmswborR {
PmmswborR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - PMM Software POR"]
#[inline(always)]
pub fn pmmswpor(&self) -> PmmswporR {
PmmswporR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - PMM Turn Regulator off"]
#[inline(always)]
pub fn pmmregoff(&self) -> PmmregoffR {
PmmregoffR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - SVS high side enable"]
#[inline(always)]
pub fn svshe(&self) -> SvsheR {
SvsheR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - PMM Low-Power Reset Enable"]
#[inline(always)]
pub fn pmmlprst(&self) -> PmmlprstR {
PmmlprstR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 2 - PMM Software BOR"]
#[inline(always)]
pub fn pmmswbor(&mut self) -> PmmswborW<'_, Pmmctl0Spec> {
PmmswborW::new(self, 2)
}
#[doc = "Bit 3 - PMM Software POR"]
#[inline(always)]
pub fn pmmswpor(&mut self) -> PmmswporW<'_, Pmmctl0Spec> {
PmmswporW::new(self, 3)
}
#[doc = "Bit 4 - PMM Turn Regulator off"]
#[inline(always)]
pub fn pmmregoff(&mut self) -> PmmregoffW<'_, Pmmctl0Spec> {
PmmregoffW::new(self, 4)
}
#[doc = "Bit 6 - SVS high side enable"]
#[inline(always)]
pub fn svshe(&mut self) -> SvsheW<'_, Pmmctl0Spec> {
SvsheW::new(self, 6)
}
#[doc = "Bit 7 - PMM Low-Power Reset Enable"]
#[inline(always)]
pub fn pmmlprst(&mut self) -> PmmlprstW<'_, Pmmctl0Spec> {
PmmlprstW::new(self, 7)
}
}
#[doc = "PMM Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pmmctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmmctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pmmctl0Spec;
impl crate::RegisterSpec for Pmmctl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`pmmctl0::R`](R) reader structure"]
impl crate::Readable for Pmmctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`pmmctl0::W`](W) writer structure"]
impl crate::Writable for Pmmctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PMMCTL0 to value 0"]
impl crate::Resettable for Pmmctl0Spec {}
}
#[doc = "PMMIFG (rw) register accessor: PMM Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pmmifg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmmifg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmmifg`] module"]
#[doc(alias = "PMMIFG")]
pub type Pmmifg = crate::Reg<pmmifg::PmmifgSpec>;
#[doc = "PMM Interrupt Flag"]
pub mod pmmifg {
#[doc = "Register `PMMIFG` reader"]
pub type R = crate::R<PmmifgSpec>;
#[doc = "Register `PMMIFG` writer"]
pub type W = crate::W<PmmifgSpec>;
#[doc = "Field `PMMBORIFG` reader - PMM Software BOR interrupt flag"]
pub type PmmborifgR = crate::BitReader;
#[doc = "Field `PMMBORIFG` writer - PMM Software BOR interrupt flag"]
pub type PmmborifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PMMRSTIFG` reader - PMM RESET pin interrupt flag"]
pub type PmmrstifgR = crate::BitReader;
#[doc = "Field `PMMRSTIFG` writer - PMM RESET pin interrupt flag"]
pub type PmmrstifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PMMPORIFG` reader - PMM Software POR interrupt flag"]
pub type PmmporifgR = crate::BitReader;
#[doc = "Field `PMMPORIFG` writer - PMM Software POR interrupt flag"]
pub type PmmporifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SVSHIFG` reader - SVS low side interrupt flag"]
pub type SvshifgR = crate::BitReader;
#[doc = "Field `SVSHIFG` writer - SVS low side interrupt flag"]
pub type SvshifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PMMLPM5IFG` reader - LPM5 indication Flag"]
pub type Pmmlpm5ifgR = crate::BitReader;
#[doc = "Field `PMMLPM5IFG` writer - LPM5 indication Flag"]
pub type Pmmlpm5ifgW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 8 - PMM Software BOR interrupt flag"]
#[inline(always)]
pub fn pmmborifg(&self) -> PmmborifgR {
PmmborifgR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - PMM RESET pin interrupt flag"]
#[inline(always)]
pub fn pmmrstifg(&self) -> PmmrstifgR {
PmmrstifgR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - PMM Software POR interrupt flag"]
#[inline(always)]
pub fn pmmporifg(&self) -> PmmporifgR {
PmmporifgR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 13 - SVS low side interrupt flag"]
#[inline(always)]
pub fn svshifg(&self) -> SvshifgR {
SvshifgR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 15 - LPM5 indication Flag"]
#[inline(always)]
pub fn pmmlpm5ifg(&self) -> Pmmlpm5ifgR {
Pmmlpm5ifgR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 8 - PMM Software BOR interrupt flag"]
#[inline(always)]
pub fn pmmborifg(&mut self) -> PmmborifgW<'_, PmmifgSpec> {
PmmborifgW::new(self, 8)
}
#[doc = "Bit 9 - PMM RESET pin interrupt flag"]
#[inline(always)]
pub fn pmmrstifg(&mut self) -> PmmrstifgW<'_, PmmifgSpec> {
PmmrstifgW::new(self, 9)
}
#[doc = "Bit 10 - PMM Software POR interrupt flag"]
#[inline(always)]
pub fn pmmporifg(&mut self) -> PmmporifgW<'_, PmmifgSpec> {
PmmporifgW::new(self, 10)
}
#[doc = "Bit 13 - SVS low side interrupt flag"]
#[inline(always)]
pub fn svshifg(&mut self) -> SvshifgW<'_, PmmifgSpec> {
SvshifgW::new(self, 13)
}
#[doc = "Bit 15 - LPM5 indication Flag"]
#[inline(always)]
pub fn pmmlpm5ifg(&mut self) -> Pmmlpm5ifgW<'_, PmmifgSpec> {
Pmmlpm5ifgW::new(self, 15)
}
}
#[doc = "PMM Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`pmmifg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmmifg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PmmifgSpec;
impl crate::RegisterSpec for PmmifgSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`pmmifg::R`](R) reader structure"]
impl crate::Readable for PmmifgSpec {}
#[doc = "`write(|w| ..)` method takes [`pmmifg::W`](W) writer structure"]
impl crate::Writable for PmmifgSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PMMIFG to value 0"]
impl crate::Resettable for PmmifgSpec {}
}
#[doc = "PM5CTL0 (rw) register accessor: PMM Power Mode 5 Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pm5ctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pm5ctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pm5ctl0`] module"]
#[doc(alias = "PM5CTL0")]
pub type Pm5ctl0 = crate::Reg<pm5ctl0::Pm5ctl0Spec>;
#[doc = "PMM Power Mode 5 Control Register 0"]
pub mod pm5ctl0 {
#[doc = "Register `PM5CTL0` reader"]
pub type R = crate::R<Pm5ctl0Spec>;
#[doc = "Register `PM5CTL0` writer"]
pub type W = crate::W<Pm5ctl0Spec>;
#[doc = "Field `LOCKLPM5` reader - Lock I/O pin configuration upon entry/exit to/from LPM5"]
pub type Locklpm5R = crate::BitReader;
#[doc = "Field `LOCKLPM5` writer - Lock I/O pin configuration upon entry/exit to/from LPM5"]
pub type Locklpm5W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Lock I/O pin configuration upon entry/exit to/from LPM5"]
#[inline(always)]
pub fn locklpm5(&self) -> Locklpm5R {
Locklpm5R::new((self.bits & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Lock I/O pin configuration upon entry/exit to/from LPM5"]
#[inline(always)]
pub fn locklpm5(&mut self) -> Locklpm5W<'_, Pm5ctl0Spec> {
Locklpm5W::new(self, 0)
}
}
#[doc = "PMM Power Mode 5 Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pm5ctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pm5ctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pm5ctl0Spec;
impl crate::RegisterSpec for Pm5ctl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`pm5ctl0::R`](R) reader structure"]
impl crate::Readable for Pm5ctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`pm5ctl0::W`](W) writer structure"]
impl crate::Writable for Pm5ctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PM5CTL0 to value 0"]
impl crate::Resettable for Pm5ctl0Spec {}
}
}
#[doc = "FRAM"]
pub type Fram = crate::Periph<fram::RegisterBlock, 0x0140>;
impl core::fmt::Debug for Fram {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Fram").finish()
}
}
#[doc = "FRAM"]
pub mod fram {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
frctl0: Frctl0,
_reserved1: [u8; 0x02],
gcctl0: Gcctl0,
gcctl1: Gcctl1,
}
impl RegisterBlock {
#[doc = "0x00 - FRAM Controller Control 0"]
#[inline(always)]
pub const fn frctl0(&self) -> &Frctl0 {
&self.frctl0
}
#[doc = "0x04 - General Control 0"]
#[inline(always)]
pub const fn gcctl0(&self) -> &Gcctl0 {
&self.gcctl0
}
#[doc = "0x06 - General Control 1"]
#[inline(always)]
pub const fn gcctl1(&self) -> &Gcctl1 {
&self.gcctl1
}
}
#[doc = "FRCTL0 (rw) register accessor: FRAM Controller Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`frctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frctl0`] module"]
#[doc(alias = "FRCTL0")]
pub type Frctl0 = crate::Reg<frctl0::Frctl0Spec>;
#[doc = "FRAM Controller Control 0"]
pub mod frctl0 {
#[doc = "Register `FRCTL0` reader"]
pub type R = crate::R<Frctl0Spec>;
#[doc = "Register `FRCTL0` writer"]
pub type W = crate::W<Frctl0Spec>;
#[doc = "FRAM Wait state control Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Nwaits {
#[doc = "0: FRAM Wait state control: 0"]
Nwaits0 = 0,
#[doc = "1: FRAM Wait state control: 1"]
Nwaits1 = 1,
#[doc = "2: FRAM Wait state control: 2"]
Nwaits2 = 2,
#[doc = "3: FRAM Wait state control: 3"]
Nwaits3 = 3,
#[doc = "4: FRAM Wait state control: 4"]
Nwaits4 = 4,
#[doc = "5: FRAM Wait state control: 5"]
Nwaits5 = 5,
#[doc = "6: FRAM Wait state control: 6"]
Nwaits6 = 6,
#[doc = "7: FRAM Wait state control: 7"]
Nwaits7 = 7,
}
impl From<Nwaits> for u8 {
#[inline(always)]
fn from(variant: Nwaits) -> Self {
variant as _
}
}
impl crate::FieldSpec for Nwaits {
type Ux = u8;
}
impl crate::IsEnum for Nwaits {}
#[doc = "Field `NWAITS` reader - FRAM Wait state control Bit: 0"]
pub type NwaitsR = crate::FieldReader<Nwaits>;
impl NwaitsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Nwaits {
match self.bits {
0 => Nwaits::Nwaits0,
1 => Nwaits::Nwaits1,
2 => Nwaits::Nwaits2,
3 => Nwaits::Nwaits3,
4 => Nwaits::Nwaits4,
5 => Nwaits::Nwaits5,
6 => Nwaits::Nwaits6,
7 => Nwaits::Nwaits7,
_ => unreachable!(),
}
}
#[doc = "FRAM Wait state control: 0"]
#[inline(always)]
pub fn is_nwaits_0(&self) -> bool {
*self == Nwaits::Nwaits0
}
#[doc = "FRAM Wait state control: 1"]
#[inline(always)]
pub fn is_nwaits_1(&self) -> bool {
*self == Nwaits::Nwaits1
}
#[doc = "FRAM Wait state control: 2"]
#[inline(always)]
pub fn is_nwaits_2(&self) -> bool {
*self == Nwaits::Nwaits2
}
#[doc = "FRAM Wait state control: 3"]
#[inline(always)]
pub fn is_nwaits_3(&self) -> bool {
*self == Nwaits::Nwaits3
}
#[doc = "FRAM Wait state control: 4"]
#[inline(always)]
pub fn is_nwaits_4(&self) -> bool {
*self == Nwaits::Nwaits4
}
#[doc = "FRAM Wait state control: 5"]
#[inline(always)]
pub fn is_nwaits_5(&self) -> bool {
*self == Nwaits::Nwaits5
}
#[doc = "FRAM Wait state control: 6"]
#[inline(always)]
pub fn is_nwaits_6(&self) -> bool {
*self == Nwaits::Nwaits6
}
#[doc = "FRAM Wait state control: 7"]
#[inline(always)]
pub fn is_nwaits_7(&self) -> bool {
*self == Nwaits::Nwaits7
}
}
#[doc = "Field `NWAITS` writer - FRAM Wait state control Bit: 0"]
pub type NwaitsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Nwaits, crate::Safe>;
impl<'a, REG> NwaitsW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "FRAM Wait state control: 0"]
#[inline(always)]
pub fn nwaits_0(self) -> &'a mut crate::W<REG> {
self.variant(Nwaits::Nwaits0)
}
#[doc = "FRAM Wait state control: 1"]
#[inline(always)]
pub fn nwaits_1(self) -> &'a mut crate::W<REG> {
self.variant(Nwaits::Nwaits1)
}
#[doc = "FRAM Wait state control: 2"]
#[inline(always)]
pub fn nwaits_2(self) -> &'a mut crate::W<REG> {
self.variant(Nwaits::Nwaits2)
}
#[doc = "FRAM Wait state control: 3"]
#[inline(always)]
pub fn nwaits_3(self) -> &'a mut crate::W<REG> {
self.variant(Nwaits::Nwaits3)
}
#[doc = "FRAM Wait state control: 4"]
#[inline(always)]
pub fn nwaits_4(self) -> &'a mut crate::W<REG> {
self.variant(Nwaits::Nwaits4)
}
#[doc = "FRAM Wait state control: 5"]
#[inline(always)]
pub fn nwaits_5(self) -> &'a mut crate::W<REG> {
self.variant(Nwaits::Nwaits5)
}
#[doc = "FRAM Wait state control: 6"]
#[inline(always)]
pub fn nwaits_6(self) -> &'a mut crate::W<REG> {
self.variant(Nwaits::Nwaits6)
}
#[doc = "FRAM Wait state control: 7"]
#[inline(always)]
pub fn nwaits_7(self) -> &'a mut crate::W<REG> {
self.variant(Nwaits::Nwaits7)
}
}
impl R {
#[doc = "Bits 4:6 - FRAM Wait state control Bit: 0"]
#[inline(always)]
pub fn nwaits(&self) -> NwaitsR {
NwaitsR::new(((self.bits >> 4) & 7) as u8)
}
}
impl W {
#[doc = "Bits 4:6 - FRAM Wait state control Bit: 0"]
#[inline(always)]
pub fn nwaits(&mut self) -> NwaitsW<'_, Frctl0Spec> {
NwaitsW::new(self, 4)
}
}
#[doc = "FRAM Controller Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`frctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Frctl0Spec;
impl crate::RegisterSpec for Frctl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`frctl0::R`](R) reader structure"]
impl crate::Readable for Frctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`frctl0::W`](W) writer structure"]
impl crate::Writable for Frctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets FRCTL0 to value 0"]
impl crate::Resettable for Frctl0Spec {}
}
#[doc = "GCCTL0 (rw) register accessor: General Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`gcctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gcctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gcctl0`] module"]
#[doc(alias = "GCCTL0")]
pub type Gcctl0 = crate::Reg<gcctl0::Gcctl0Spec>;
#[doc = "General Control 0"]
pub mod gcctl0 {
#[doc = "Register `GCCTL0` reader"]
pub type R = crate::R<Gcctl0Spec>;
#[doc = "Register `GCCTL0` writer"]
pub type W = crate::W<Gcctl0Spec>;
#[doc = "Field `FRLPMPWR` reader - FRAM Enable FRAM auto power up after LPM"]
pub type FrlpmpwrR = crate::BitReader;
#[doc = "Field `FRLPMPWR` writer - FRAM Enable FRAM auto power up after LPM"]
pub type FrlpmpwrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FRPWR` reader - FRAM Power Control"]
pub type FrpwrR = crate::BitReader;
#[doc = "Field `FRPWR` writer - FRAM Power Control"]
pub type FrpwrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ACCTEIE` reader - RESERVED"]
pub type AccteieR = crate::BitReader;
#[doc = "Field `ACCTEIE` writer - RESERVED"]
pub type AccteieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CBDIE` reader - Enable NMI event if correctable bit error detected"]
pub type CbdieR = crate::BitReader;
#[doc = "Field `CBDIE` writer - Enable NMI event if correctable bit error detected"]
pub type CbdieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UBDIE` reader - Enable NMI event if uncorrectable bit error detected"]
pub type UbdieR = crate::BitReader;
#[doc = "Field `UBDIE` writer - Enable NMI event if uncorrectable bit error detected"]
pub type UbdieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UBDRSTEN` reader - Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected"]
pub type UbdrstenR = crate::BitReader;
#[doc = "Field `UBDRSTEN` writer - Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected"]
pub type UbdrstenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 1 - FRAM Enable FRAM auto power up after LPM"]
#[inline(always)]
pub fn frlpmpwr(&self) -> FrlpmpwrR {
FrlpmpwrR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - FRAM Power Control"]
#[inline(always)]
pub fn frpwr(&self) -> FrpwrR {
FrpwrR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RESERVED"]
#[inline(always)]
pub fn accteie(&self) -> AccteieR {
AccteieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 5 - Enable NMI event if correctable bit error detected"]
#[inline(always)]
pub fn cbdie(&self) -> CbdieR {
CbdieR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Enable NMI event if uncorrectable bit error detected"]
#[inline(always)]
pub fn ubdie(&self) -> UbdieR {
UbdieR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected"]
#[inline(always)]
pub fn ubdrsten(&self) -> UbdrstenR {
UbdrstenR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1 - FRAM Enable FRAM auto power up after LPM"]
#[inline(always)]
pub fn frlpmpwr(&mut self) -> FrlpmpwrW<'_, Gcctl0Spec> {
FrlpmpwrW::new(self, 1)
}
#[doc = "Bit 2 - FRAM Power Control"]
#[inline(always)]
pub fn frpwr(&mut self) -> FrpwrW<'_, Gcctl0Spec> {
FrpwrW::new(self, 2)
}
#[doc = "Bit 3 - RESERVED"]
#[inline(always)]
pub fn accteie(&mut self) -> AccteieW<'_, Gcctl0Spec> {
AccteieW::new(self, 3)
}
#[doc = "Bit 5 - Enable NMI event if correctable bit error detected"]
#[inline(always)]
pub fn cbdie(&mut self) -> CbdieW<'_, Gcctl0Spec> {
CbdieW::new(self, 5)
}
#[doc = "Bit 6 - Enable NMI event if uncorrectable bit error detected"]
#[inline(always)]
pub fn ubdie(&mut self) -> UbdieW<'_, Gcctl0Spec> {
UbdieW::new(self, 6)
}
#[doc = "Bit 7 - Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected"]
#[inline(always)]
pub fn ubdrsten(&mut self) -> UbdrstenW<'_, Gcctl0Spec> {
UbdrstenW::new(self, 7)
}
}
#[doc = "General Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`gcctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gcctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gcctl0Spec;
impl crate::RegisterSpec for Gcctl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`gcctl0::R`](R) reader structure"]
impl crate::Readable for Gcctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`gcctl0::W`](W) writer structure"]
impl crate::Writable for Gcctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GCCTL0 to value 0"]
impl crate::Resettable for Gcctl0Spec {}
}
#[doc = "GCCTL1 (rw) register accessor: General Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`gcctl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gcctl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gcctl1`] module"]
#[doc(alias = "GCCTL1")]
pub type Gcctl1 = crate::Reg<gcctl1::Gcctl1Spec>;
#[doc = "General Control 1"]
pub mod gcctl1 {
#[doc = "Register `GCCTL1` reader"]
pub type R = crate::R<Gcctl1Spec>;
#[doc = "Register `GCCTL1` writer"]
pub type W = crate::W<Gcctl1Spec>;
#[doc = "Field `CBDIFG` reader - FRAM correctable bit error flag"]
pub type CbdifgR = crate::BitReader;
#[doc = "Field `CBDIFG` writer - FRAM correctable bit error flag"]
pub type CbdifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UBDIFG` reader - FRAM uncorrectable bit error flag"]
pub type UbdifgR = crate::BitReader;
#[doc = "Field `UBDIFG` writer - FRAM uncorrectable bit error flag"]
pub type UbdifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ACCTEIFG` reader - Access time error flag"]
pub type AccteifgR = crate::BitReader;
#[doc = "Field `ACCTEIFG` writer - Access time error flag"]
pub type AccteifgW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 1 - FRAM correctable bit error flag"]
#[inline(always)]
pub fn cbdifg(&self) -> CbdifgR {
CbdifgR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - FRAM uncorrectable bit error flag"]
#[inline(always)]
pub fn ubdifg(&self) -> UbdifgR {
UbdifgR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Access time error flag"]
#[inline(always)]
pub fn accteifg(&self) -> AccteifgR {
AccteifgR::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1 - FRAM correctable bit error flag"]
#[inline(always)]
pub fn cbdifg(&mut self) -> CbdifgW<'_, Gcctl1Spec> {
CbdifgW::new(self, 1)
}
#[doc = "Bit 2 - FRAM uncorrectable bit error flag"]
#[inline(always)]
pub fn ubdifg(&mut self) -> UbdifgW<'_, Gcctl1Spec> {
UbdifgW::new(self, 2)
}
#[doc = "Bit 3 - Access time error flag"]
#[inline(always)]
pub fn accteifg(&mut self) -> AccteifgW<'_, Gcctl1Spec> {
AccteifgW::new(self, 3)
}
}
#[doc = "General Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`gcctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gcctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gcctl1Spec;
impl crate::RegisterSpec for Gcctl1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`gcctl1::R`](R) reader structure"]
impl crate::Readable for Gcctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`gcctl1::W`](W) writer structure"]
impl crate::Writable for Gcctl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GCCTL1 to value 0"]
impl crate::Resettable for Gcctl1Spec {}
}
}
#[doc = "CRC16"]
pub type Crc16 = crate::Periph<crc16::RegisterBlock, 0x0150>;
impl core::fmt::Debug for Crc16 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Crc16").finish()
}
}
#[doc = "CRC16"]
pub mod crc16 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
crcdi: Crcdi,
crcdirb: Crcdirb,
crcinires: Crcinires,
crcresr: Crcresr,
}
impl RegisterBlock {
#[doc = "0x00 - CRC Data In Register"]
#[inline(always)]
pub const fn crcdi(&self) -> &Crcdi {
&self.crcdi
}
#[doc = "0x02 - CRC data in reverse byte Register"]
#[inline(always)]
pub const fn crcdirb(&self) -> &Crcdirb {
&self.crcdirb
}
#[doc = "0x04 - CRC Initialisation Register and Result Register"]
#[inline(always)]
pub const fn crcinires(&self) -> &Crcinires {
&self.crcinires
}
#[doc = "0x06 - CRC reverse result Register"]
#[inline(always)]
pub const fn crcresr(&self) -> &Crcresr {
&self.crcresr
}
}
#[doc = "CRCDI (rw) register accessor: CRC Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`crcdi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crcdi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crcdi`] module"]
#[doc(alias = "CRCDI")]
pub type Crcdi = crate::Reg<crcdi::CrcdiSpec>;
#[doc = "CRC Data In Register"]
pub mod crcdi {
#[doc = "Register `CRCDI` reader"]
pub type R = crate::R<CrcdiSpec>;
#[doc = "Register `CRCDI` writer"]
pub type W = crate::W<CrcdiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "CRC Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`crcdi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crcdi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcdiSpec;
impl crate::RegisterSpec for CrcdiSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`crcdi::R`](R) reader structure"]
impl crate::Readable for CrcdiSpec {}
#[doc = "`write(|w| ..)` method takes [`crcdi::W`](W) writer structure"]
impl crate::Writable for CrcdiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CRCDI to value 0"]
impl crate::Resettable for CrcdiSpec {}
}
#[doc = "CRCDIRB (rw) register accessor: CRC data in reverse byte Register\n\nYou can [`read`](crate::Reg::read) this register and get [`crcdirb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crcdirb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crcdirb`] module"]
#[doc(alias = "CRCDIRB")]
pub type Crcdirb = crate::Reg<crcdirb::CrcdirbSpec>;
#[doc = "CRC data in reverse byte Register"]
pub mod crcdirb {
#[doc = "Register `CRCDIRB` reader"]
pub type R = crate::R<CrcdirbSpec>;
#[doc = "Register `CRCDIRB` writer"]
pub type W = crate::W<CrcdirbSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "CRC data in reverse byte Register\n\nYou can [`read`](crate::Reg::read) this register and get [`crcdirb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crcdirb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcdirbSpec;
impl crate::RegisterSpec for CrcdirbSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`crcdirb::R`](R) reader structure"]
impl crate::Readable for CrcdirbSpec {}
#[doc = "`write(|w| ..)` method takes [`crcdirb::W`](W) writer structure"]
impl crate::Writable for CrcdirbSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CRCDIRB to value 0"]
impl crate::Resettable for CrcdirbSpec {}
}
#[doc = "CRCINIRES (rw) register accessor: CRC Initialisation Register and Result Register\n\nYou can [`read`](crate::Reg::read) this register and get [`crcinires::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crcinires::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crcinires`] module"]
#[doc(alias = "CRCINIRES")]
pub type Crcinires = crate::Reg<crcinires::CrciniresSpec>;
#[doc = "CRC Initialisation Register and Result Register"]
pub mod crcinires {
#[doc = "Register `CRCINIRES` reader"]
pub type R = crate::R<CrciniresSpec>;
#[doc = "Register `CRCINIRES` writer"]
pub type W = crate::W<CrciniresSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "CRC Initialisation Register and Result Register\n\nYou can [`read`](crate::Reg::read) this register and get [`crcinires::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crcinires::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrciniresSpec;
impl crate::RegisterSpec for CrciniresSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`crcinires::R`](R) reader structure"]
impl crate::Readable for CrciniresSpec {}
#[doc = "`write(|w| ..)` method takes [`crcinires::W`](W) writer structure"]
impl crate::Writable for CrciniresSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CRCINIRES to value 0"]
impl crate::Resettable for CrciniresSpec {}
}
#[doc = "CRCRESR (rw) register accessor: CRC reverse result Register\n\nYou can [`read`](crate::Reg::read) this register and get [`crcresr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crcresr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crcresr`] module"]
#[doc(alias = "CRCRESR")]
pub type Crcresr = crate::Reg<crcresr::CrcresrSpec>;
#[doc = "CRC reverse result Register"]
pub mod crcresr {
#[doc = "Register `CRCRESR` reader"]
pub type R = crate::R<CrcresrSpec>;
#[doc = "Register `CRCRESR` writer"]
pub type W = crate::W<CrcresrSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "CRC reverse result Register\n\nYou can [`read`](crate::Reg::read) this register and get [`crcresr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crcresr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcresrSpec;
impl crate::RegisterSpec for CrcresrSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`crcresr::R`](R) reader structure"]
impl crate::Readable for CrcresrSpec {}
#[doc = "`write(|w| ..)` method takes [`crcresr::W`](W) writer structure"]
impl crate::Writable for CrcresrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CRCRESR to value 0"]
impl crate::Resettable for CrcresrSpec {}
}
}
#[doc = "Watchdog Timer"]
pub type WatchdogTimer = crate::Periph<watchdog_timer::RegisterBlock, 0x015c>;
impl core::fmt::Debug for WatchdogTimer {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("WatchdogTimer").finish()
}
}
#[doc = "Watchdog Timer"]
pub mod watchdog_timer {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
wdtctl: Wdtctl,
}
impl RegisterBlock {
#[doc = "0x00 - Watchdog Timer Control"]
#[inline(always)]
pub const fn wdtctl(&self) -> &Wdtctl {
&self.wdtctl
}
}
#[doc = "WDTCTL (rw) register accessor: Watchdog Timer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtctl`] module"]
#[doc(alias = "WDTCTL")]
pub type Wdtctl = crate::Reg<wdtctl::WdtctlSpec>;
#[doc = "Watchdog Timer Control"]
pub mod wdtctl {
#[doc = "Register `WDTCTL` reader"]
pub type R = crate::R<WdtctlSpec>;
#[doc = "Register `WDTCTL` writer"]
pub type W = crate::W<WdtctlSpec>;
#[doc = "WDT - Timer Interval Select 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Wdtis {
#[doc = "0: WDT - Timer Interval Select: /2G"]
Wdtis0 = 0,
#[doc = "1: WDT - Timer Interval Select: /128M"]
Wdtis1 = 1,
#[doc = "2: WDT - Timer Interval Select: /8192k"]
Wdtis2 = 2,
#[doc = "3: WDT - Timer Interval Select: /512k"]
Wdtis3 = 3,
#[doc = "4: WDT - Timer Interval Select: /32k"]
Wdtis4 = 4,
#[doc = "5: WDT - Timer Interval Select: /8192"]
Wdtis5 = 5,
#[doc = "6: WDT - Timer Interval Select: /512"]
Wdtis6 = 6,
#[doc = "7: WDT - Timer Interval Select: /64"]
Wdtis7 = 7,
}
impl From<Wdtis> for u8 {
#[inline(always)]
fn from(variant: Wdtis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Wdtis {
type Ux = u8;
}
impl crate::IsEnum for Wdtis {}
#[doc = "Field `WDTIS` reader - WDT - Timer Interval Select 0"]
pub type WdtisR = crate::FieldReader<Wdtis>;
impl WdtisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Wdtis {
match self.bits {
0 => Wdtis::Wdtis0,
1 => Wdtis::Wdtis1,
2 => Wdtis::Wdtis2,
3 => Wdtis::Wdtis3,
4 => Wdtis::Wdtis4,
5 => Wdtis::Wdtis5,
6 => Wdtis::Wdtis6,
7 => Wdtis::Wdtis7,
_ => unreachable!(),
}
}
#[doc = "WDT - Timer Interval Select: /2G"]
#[inline(always)]
pub fn is_wdtis_0(&self) -> bool {
*self == Wdtis::Wdtis0
}
#[doc = "WDT - Timer Interval Select: /128M"]
#[inline(always)]
pub fn is_wdtis_1(&self) -> bool {
*self == Wdtis::Wdtis1
}
#[doc = "WDT - Timer Interval Select: /8192k"]
#[inline(always)]
pub fn is_wdtis_2(&self) -> bool {
*self == Wdtis::Wdtis2
}
#[doc = "WDT - Timer Interval Select: /512k"]
#[inline(always)]
pub fn is_wdtis_3(&self) -> bool {
*self == Wdtis::Wdtis3
}
#[doc = "WDT - Timer Interval Select: /32k"]
#[inline(always)]
pub fn is_wdtis_4(&self) -> bool {
*self == Wdtis::Wdtis4
}
#[doc = "WDT - Timer Interval Select: /8192"]
#[inline(always)]
pub fn is_wdtis_5(&self) -> bool {
*self == Wdtis::Wdtis5
}
#[doc = "WDT - Timer Interval Select: /512"]
#[inline(always)]
pub fn is_wdtis_6(&self) -> bool {
*self == Wdtis::Wdtis6
}
#[doc = "WDT - Timer Interval Select: /64"]
#[inline(always)]
pub fn is_wdtis_7(&self) -> bool {
*self == Wdtis::Wdtis7
}
}
#[doc = "Field `WDTIS` writer - WDT - Timer Interval Select 0"]
pub type WdtisW<'a, REG> = crate::FieldWriter<'a, REG, 3, Wdtis, crate::Safe>;
impl<'a, REG> WdtisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "WDT - Timer Interval Select: /2G"]
#[inline(always)]
pub fn wdtis_0(self) -> &'a mut crate::W<REG> {
self.variant(Wdtis::Wdtis0)
}
#[doc = "WDT - Timer Interval Select: /128M"]
#[inline(always)]
pub fn wdtis_1(self) -> &'a mut crate::W<REG> {
self.variant(Wdtis::Wdtis1)
}
#[doc = "WDT - Timer Interval Select: /8192k"]
#[inline(always)]
pub fn wdtis_2(self) -> &'a mut crate::W<REG> {
self.variant(Wdtis::Wdtis2)
}
#[doc = "WDT - Timer Interval Select: /512k"]
#[inline(always)]
pub fn wdtis_3(self) -> &'a mut crate::W<REG> {
self.variant(Wdtis::Wdtis3)
}
#[doc = "WDT - Timer Interval Select: /32k"]
#[inline(always)]
pub fn wdtis_4(self) -> &'a mut crate::W<REG> {
self.variant(Wdtis::Wdtis4)
}
#[doc = "WDT - Timer Interval Select: /8192"]
#[inline(always)]
pub fn wdtis_5(self) -> &'a mut crate::W<REG> {
self.variant(Wdtis::Wdtis5)
}
#[doc = "WDT - Timer Interval Select: /512"]
#[inline(always)]
pub fn wdtis_6(self) -> &'a mut crate::W<REG> {
self.variant(Wdtis::Wdtis6)
}
#[doc = "WDT - Timer Interval Select: /64"]
#[inline(always)]
pub fn wdtis_7(self) -> &'a mut crate::W<REG> {
self.variant(Wdtis::Wdtis7)
}
}
#[doc = "Field `WDTCNTCL` reader - WDT - Timer Clear"]
pub type WdtcntclR = crate::BitReader;
#[doc = "Field `WDTCNTCL` writer - WDT - Timer Clear"]
pub type WdtcntclW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WDTTMSEL` reader - WDT - Timer Mode Select"]
pub type WdttmselR = crate::BitReader;
#[doc = "Field `WDTTMSEL` writer - WDT - Timer Mode Select"]
pub type WdttmselW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "WDT - Timer Clock Source Select 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Wdtssel {
#[doc = "0: WDT - Timer Clock Source Select: SMCLK"]
Wdtssel0 = 0,
#[doc = "1: WDT - Timer Clock Source Select: ACLK"]
Wdtssel1 = 1,
#[doc = "2: WDT - Timer Clock Source Select: VLO_CLK"]
Wdtssel2 = 2,
#[doc = "3: WDT - Timer Clock Source Select: reserved"]
Wdtssel3 = 3,
}
impl From<Wdtssel> for u8 {
#[inline(always)]
fn from(variant: Wdtssel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Wdtssel {
type Ux = u8;
}
impl crate::IsEnum for Wdtssel {}
#[doc = "Field `WDTSSEL` reader - WDT - Timer Clock Source Select 0"]
pub type WdtsselR = crate::FieldReader<Wdtssel>;
impl WdtsselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Wdtssel {
match self.bits {
0 => Wdtssel::Wdtssel0,
1 => Wdtssel::Wdtssel1,
2 => Wdtssel::Wdtssel2,
3 => Wdtssel::Wdtssel3,
_ => unreachable!(),
}
}
#[doc = "WDT - Timer Clock Source Select: SMCLK"]
#[inline(always)]
pub fn is_wdtssel_0(&self) -> bool {
*self == Wdtssel::Wdtssel0
}
#[doc = "WDT - Timer Clock Source Select: ACLK"]
#[inline(always)]
pub fn is_wdtssel_1(&self) -> bool {
*self == Wdtssel::Wdtssel1
}
#[doc = "WDT - Timer Clock Source Select: VLO_CLK"]
#[inline(always)]
pub fn is_wdtssel_2(&self) -> bool {
*self == Wdtssel::Wdtssel2
}
#[doc = "WDT - Timer Clock Source Select: reserved"]
#[inline(always)]
pub fn is_wdtssel_3(&self) -> bool {
*self == Wdtssel::Wdtssel3
}
}
#[doc = "Field `WDTSSEL` writer - WDT - Timer Clock Source Select 0"]
pub type WdtsselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Wdtssel, crate::Safe>;
impl<'a, REG> WdtsselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "WDT - Timer Clock Source Select: SMCLK"]
#[inline(always)]
pub fn wdtssel_0(self) -> &'a mut crate::W<REG> {
self.variant(Wdtssel::Wdtssel0)
}
#[doc = "WDT - Timer Clock Source Select: ACLK"]
#[inline(always)]
pub fn wdtssel_1(self) -> &'a mut crate::W<REG> {
self.variant(Wdtssel::Wdtssel1)
}
#[doc = "WDT - Timer Clock Source Select: VLO_CLK"]
#[inline(always)]
pub fn wdtssel_2(self) -> &'a mut crate::W<REG> {
self.variant(Wdtssel::Wdtssel2)
}
#[doc = "WDT - Timer Clock Source Select: reserved"]
#[inline(always)]
pub fn wdtssel_3(self) -> &'a mut crate::W<REG> {
self.variant(Wdtssel::Wdtssel3)
}
}
#[doc = "Field `WDTHOLD` reader - WDT - Timer hold"]
pub type WdtholdR = crate::BitReader;
#[doc = "Field `WDTHOLD` writer - WDT - Timer hold"]
pub type WdtholdW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:2 - WDT - Timer Interval Select 0"]
#[inline(always)]
pub fn wdtis(&self) -> WdtisR {
WdtisR::new((self.bits & 7) as u8)
}
#[doc = "Bit 3 - WDT - Timer Clear"]
#[inline(always)]
pub fn wdtcntcl(&self) -> WdtcntclR {
WdtcntclR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - WDT - Timer Mode Select"]
#[inline(always)]
pub fn wdttmsel(&self) -> WdttmselR {
WdttmselR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6 - WDT - Timer Clock Source Select 0"]
#[inline(always)]
pub fn wdtssel(&self) -> WdtsselR {
WdtsselR::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7 - WDT - Timer hold"]
#[inline(always)]
pub fn wdthold(&self) -> WdtholdR {
WdtholdR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - WDT - Timer Interval Select 0"]
#[inline(always)]
pub fn wdtis(&mut self) -> WdtisW<'_, WdtctlSpec> {
WdtisW::new(self, 0)
}
#[doc = "Bit 3 - WDT - Timer Clear"]
#[inline(always)]
pub fn wdtcntcl(&mut self) -> WdtcntclW<'_, WdtctlSpec> {
WdtcntclW::new(self, 3)
}
#[doc = "Bit 4 - WDT - Timer Mode Select"]
#[inline(always)]
pub fn wdttmsel(&mut self) -> WdttmselW<'_, WdtctlSpec> {
WdttmselW::new(self, 4)
}
#[doc = "Bits 5:6 - WDT - Timer Clock Source Select 0"]
#[inline(always)]
pub fn wdtssel(&mut self) -> WdtsselW<'_, WdtctlSpec> {
WdtsselW::new(self, 5)
}
#[doc = "Bit 7 - WDT - Timer hold"]
#[inline(always)]
pub fn wdthold(&mut self) -> WdtholdW<'_, WdtctlSpec> {
WdtholdW::new(self, 7)
}
}
#[doc = "Watchdog Timer Control\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdtctlSpec;
impl crate::RegisterSpec for WdtctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`wdtctl::R`](R) reader structure"]
impl crate::Readable for WdtctlSpec {}
#[doc = "`write(|w| ..)` method takes [`wdtctl::W`](W) writer structure"]
impl crate::Writable for WdtctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets WDTCTL to value 0"]
impl crate::Resettable for WdtctlSpec {}
}
}
#[doc = "CS Clock System"]
pub type Cs = crate::Periph<cs::RegisterBlock, 0x0160>;
impl core::fmt::Debug for Cs {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Cs").finish()
}
}
#[doc = "CS Clock System"]
pub mod cs {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
csctl0: Csctl0,
csctl1: Csctl1,
csctl2: Csctl2,
csctl3: Csctl3,
csctl4: Csctl4,
csctl5: Csctl5,
csctl6: Csctl6,
}
impl RegisterBlock {
#[doc = "0x00 - CS Control Register 0"]
#[inline(always)]
pub const fn csctl0(&self) -> &Csctl0 {
&self.csctl0
}
#[doc = "0x02 - CS Control Register 1"]
#[inline(always)]
pub const fn csctl1(&self) -> &Csctl1 {
&self.csctl1
}
#[doc = "0x04 - CS Control Register 2"]
#[inline(always)]
pub const fn csctl2(&self) -> &Csctl2 {
&self.csctl2
}
#[doc = "0x06 - CS Control Register 3"]
#[inline(always)]
pub const fn csctl3(&self) -> &Csctl3 {
&self.csctl3
}
#[doc = "0x08 - CS Control Register 4"]
#[inline(always)]
pub const fn csctl4(&self) -> &Csctl4 {
&self.csctl4
}
#[doc = "0x0a - CS Control Register 5"]
#[inline(always)]
pub const fn csctl5(&self) -> &Csctl5 {
&self.csctl5
}
#[doc = "0x0c - CS Control Register 6"]
#[inline(always)]
pub const fn csctl6(&self) -> &Csctl6 {
&self.csctl6
}
}
#[doc = "CSCTL0 (rw) register accessor: CS Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`csctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csctl0`] module"]
#[doc(alias = "CSCTL0")]
pub type Csctl0 = crate::Reg<csctl0::Csctl0Spec>;
#[doc = "CS Control Register 0"]
pub mod csctl0 {
#[doc = "Register `CSCTL0` reader"]
pub type R = crate::R<Csctl0Spec>;
#[doc = "Register `CSCTL0` writer"]
pub type W = crate::W<Csctl0Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "CS Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`csctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Csctl0Spec;
impl crate::RegisterSpec for Csctl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`csctl0::R`](R) reader structure"]
impl crate::Readable for Csctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`csctl0::W`](W) writer structure"]
impl crate::Writable for Csctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CSCTL0 to value 0"]
impl crate::Resettable for Csctl0Spec {}
}
#[doc = "CSCTL1 (rw) register accessor: CS Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`csctl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csctl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csctl1`] module"]
#[doc(alias = "CSCTL1")]
pub type Csctl1 = crate::Reg<csctl1::Csctl1Spec>;
#[doc = "CS Control Register 1"]
pub mod csctl1 {
#[doc = "Register `CSCTL1` reader"]
pub type R = crate::R<Csctl1Spec>;
#[doc = "Register `CSCTL1` writer"]
pub type W = crate::W<Csctl1Spec>;
#[doc = "DCO frequency select Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dcofsel {
#[doc = "0: DCO frequency select: 0"]
Dcofsel0 = 0,
#[doc = "1: DCO frequency select: 1"]
Dcofsel1 = 1,
#[doc = "2: DCO frequency select: 2"]
Dcofsel2 = 2,
#[doc = "3: DCO frequency select: 3"]
Dcofsel3 = 3,
#[doc = "4: DCO frequency select: 4"]
Dcofsel4 = 4,
#[doc = "5: DCO frequency select: 5"]
Dcofsel5 = 5,
#[doc = "6: DCO frequency select: 6"]
Dcofsel6 = 6,
#[doc = "7: DCO frequency select: 7"]
Dcofsel7 = 7,
}
impl From<Dcofsel> for u8 {
#[inline(always)]
fn from(variant: Dcofsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dcofsel {
type Ux = u8;
}
impl crate::IsEnum for Dcofsel {}
#[doc = "Field `DCOFSEL` reader - DCO frequency select Bit: 0"]
pub type DcofselR = crate::FieldReader<Dcofsel>;
impl DcofselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dcofsel {
match self.bits {
0 => Dcofsel::Dcofsel0,
1 => Dcofsel::Dcofsel1,
2 => Dcofsel::Dcofsel2,
3 => Dcofsel::Dcofsel3,
4 => Dcofsel::Dcofsel4,
5 => Dcofsel::Dcofsel5,
6 => Dcofsel::Dcofsel6,
7 => Dcofsel::Dcofsel7,
_ => unreachable!(),
}
}
#[doc = "DCO frequency select: 0"]
#[inline(always)]
pub fn is_dcofsel_0(&self) -> bool {
*self == Dcofsel::Dcofsel0
}
#[doc = "DCO frequency select: 1"]
#[inline(always)]
pub fn is_dcofsel_1(&self) -> bool {
*self == Dcofsel::Dcofsel1
}
#[doc = "DCO frequency select: 2"]
#[inline(always)]
pub fn is_dcofsel_2(&self) -> bool {
*self == Dcofsel::Dcofsel2
}
#[doc = "DCO frequency select: 3"]
#[inline(always)]
pub fn is_dcofsel_3(&self) -> bool {
*self == Dcofsel::Dcofsel3
}
#[doc = "DCO frequency select: 4"]
#[inline(always)]
pub fn is_dcofsel_4(&self) -> bool {
*self == Dcofsel::Dcofsel4
}
#[doc = "DCO frequency select: 5"]
#[inline(always)]
pub fn is_dcofsel_5(&self) -> bool {
*self == Dcofsel::Dcofsel5
}
#[doc = "DCO frequency select: 6"]
#[inline(always)]
pub fn is_dcofsel_6(&self) -> bool {
*self == Dcofsel::Dcofsel6
}
#[doc = "DCO frequency select: 7"]
#[inline(always)]
pub fn is_dcofsel_7(&self) -> bool {
*self == Dcofsel::Dcofsel7
}
}
#[doc = "Field `DCOFSEL` writer - DCO frequency select Bit: 0"]
pub type DcofselW<'a, REG> = crate::FieldWriter<'a, REG, 3, Dcofsel, crate::Safe>;
impl<'a, REG> DcofselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "DCO frequency select: 0"]
#[inline(always)]
pub fn dcofsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Dcofsel::Dcofsel0)
}
#[doc = "DCO frequency select: 1"]
#[inline(always)]
pub fn dcofsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Dcofsel::Dcofsel1)
}
#[doc = "DCO frequency select: 2"]
#[inline(always)]
pub fn dcofsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Dcofsel::Dcofsel2)
}
#[doc = "DCO frequency select: 3"]
#[inline(always)]
pub fn dcofsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Dcofsel::Dcofsel3)
}
#[doc = "DCO frequency select: 4"]
#[inline(always)]
pub fn dcofsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Dcofsel::Dcofsel4)
}
#[doc = "DCO frequency select: 5"]
#[inline(always)]
pub fn dcofsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Dcofsel::Dcofsel5)
}
#[doc = "DCO frequency select: 6"]
#[inline(always)]
pub fn dcofsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Dcofsel::Dcofsel6)
}
#[doc = "DCO frequency select: 7"]
#[inline(always)]
pub fn dcofsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Dcofsel::Dcofsel7)
}
}
#[doc = "Field `DCORSEL` reader - DCO range select."]
pub type DcorselR = crate::BitReader;
#[doc = "Field `DCORSEL` writer - DCO range select."]
pub type DcorselW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 1:3 - DCO frequency select Bit: 0"]
#[inline(always)]
pub fn dcofsel(&self) -> DcofselR {
DcofselR::new(((self.bits >> 1) & 7) as u8)
}
#[doc = "Bit 6 - DCO range select."]
#[inline(always)]
pub fn dcorsel(&self) -> DcorselR {
DcorselR::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bits 1:3 - DCO frequency select Bit: 0"]
#[inline(always)]
pub fn dcofsel(&mut self) -> DcofselW<'_, Csctl1Spec> {
DcofselW::new(self, 1)
}
#[doc = "Bit 6 - DCO range select."]
#[inline(always)]
pub fn dcorsel(&mut self) -> DcorselW<'_, Csctl1Spec> {
DcorselW::new(self, 6)
}
}
#[doc = "CS Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`csctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Csctl1Spec;
impl crate::RegisterSpec for Csctl1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`csctl1::R`](R) reader structure"]
impl crate::Readable for Csctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`csctl1::W`](W) writer structure"]
impl crate::Writable for Csctl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CSCTL1 to value 0"]
impl crate::Resettable for Csctl1Spec {}
}
#[doc = "CSCTL2 (rw) register accessor: CS Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`csctl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csctl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csctl2`] module"]
#[doc(alias = "CSCTL2")]
pub type Csctl2 = crate::Reg<csctl2::Csctl2Spec>;
#[doc = "CS Control Register 2"]
pub mod csctl2 {
#[doc = "Register `CSCTL2` reader"]
pub type R = crate::R<Csctl2Spec>;
#[doc = "Register `CSCTL2` writer"]
pub type W = crate::W<Csctl2Spec>;
#[doc = "MCLK Source Select Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Selm {
#[doc = "0: MCLK Source Select 0"]
Selm0 = 0,
#[doc = "1: MCLK Source Select 1"]
Selm1 = 1,
#[doc = "2: MCLK Source Select 2"]
Selm2 = 2,
#[doc = "3: MCLK Source Select 3"]
Selm3 = 3,
#[doc = "4: MCLK Source Select 4"]
Selm4 = 4,
#[doc = "5: MCLK Source Select 5"]
Selm5 = 5,
#[doc = "6: MCLK Source Select 6"]
Selm6 = 6,
#[doc = "7: MCLK Source Select 7"]
Selm7 = 7,
}
impl From<Selm> for u8 {
#[inline(always)]
fn from(variant: Selm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Selm {
type Ux = u8;
}
impl crate::IsEnum for Selm {}
#[doc = "Field `SELM` reader - MCLK Source Select Bit: 0"]
pub type SelmR = crate::FieldReader<Selm>;
impl SelmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Selm {
match self.bits {
0 => Selm::Selm0,
1 => Selm::Selm1,
2 => Selm::Selm2,
3 => Selm::Selm3,
4 => Selm::Selm4,
5 => Selm::Selm5,
6 => Selm::Selm6,
7 => Selm::Selm7,
_ => unreachable!(),
}
}
#[doc = "MCLK Source Select 0"]
#[inline(always)]
pub fn is_selm_0(&self) -> bool {
*self == Selm::Selm0
}
#[doc = "MCLK Source Select 1"]
#[inline(always)]
pub fn is_selm_1(&self) -> bool {
*self == Selm::Selm1
}
#[doc = "MCLK Source Select 2"]
#[inline(always)]
pub fn is_selm_2(&self) -> bool {
*self == Selm::Selm2
}
#[doc = "MCLK Source Select 3"]
#[inline(always)]
pub fn is_selm_3(&self) -> bool {
*self == Selm::Selm3
}
#[doc = "MCLK Source Select 4"]
#[inline(always)]
pub fn is_selm_4(&self) -> bool {
*self == Selm::Selm4
}
#[doc = "MCLK Source Select 5"]
#[inline(always)]
pub fn is_selm_5(&self) -> bool {
*self == Selm::Selm5
}
#[doc = "MCLK Source Select 6"]
#[inline(always)]
pub fn is_selm_6(&self) -> bool {
*self == Selm::Selm6
}
#[doc = "MCLK Source Select 7"]
#[inline(always)]
pub fn is_selm_7(&self) -> bool {
*self == Selm::Selm7
}
}
#[doc = "Field `SELM` writer - MCLK Source Select Bit: 0"]
pub type SelmW<'a, REG> = crate::FieldWriter<'a, REG, 3, Selm, crate::Safe>;
impl<'a, REG> SelmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "MCLK Source Select 0"]
#[inline(always)]
pub fn selm_0(self) -> &'a mut crate::W<REG> {
self.variant(Selm::Selm0)
}
#[doc = "MCLK Source Select 1"]
#[inline(always)]
pub fn selm_1(self) -> &'a mut crate::W<REG> {
self.variant(Selm::Selm1)
}
#[doc = "MCLK Source Select 2"]
#[inline(always)]
pub fn selm_2(self) -> &'a mut crate::W<REG> {
self.variant(Selm::Selm2)
}
#[doc = "MCLK Source Select 3"]
#[inline(always)]
pub fn selm_3(self) -> &'a mut crate::W<REG> {
self.variant(Selm::Selm3)
}
#[doc = "MCLK Source Select 4"]
#[inline(always)]
pub fn selm_4(self) -> &'a mut crate::W<REG> {
self.variant(Selm::Selm4)
}
#[doc = "MCLK Source Select 5"]
#[inline(always)]
pub fn selm_5(self) -> &'a mut crate::W<REG> {
self.variant(Selm::Selm5)
}
#[doc = "MCLK Source Select 6"]
#[inline(always)]
pub fn selm_6(self) -> &'a mut crate::W<REG> {
self.variant(Selm::Selm6)
}
#[doc = "MCLK Source Select 7"]
#[inline(always)]
pub fn selm_7(self) -> &'a mut crate::W<REG> {
self.variant(Selm::Selm7)
}
}
#[doc = "SMCLK Source Select Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Sels {
#[doc = "0: SMCLK Source Select 0"]
Sels0 = 0,
#[doc = "1: SMCLK Source Select 1"]
Sels1 = 1,
#[doc = "2: SMCLK Source Select 2"]
Sels2 = 2,
#[doc = "3: SMCLK Source Select 3"]
Sels3 = 3,
#[doc = "4: SMCLK Source Select 4"]
Sels4 = 4,
#[doc = "5: SMCLK Source Select 5"]
Sels5 = 5,
#[doc = "6: SMCLK Source Select 6"]
Sels6 = 6,
#[doc = "7: SMCLK Source Select 7"]
Sels7 = 7,
}
impl From<Sels> for u8 {
#[inline(always)]
fn from(variant: Sels) -> Self {
variant as _
}
}
impl crate::FieldSpec for Sels {
type Ux = u8;
}
impl crate::IsEnum for Sels {}
#[doc = "Field `SELS` reader - SMCLK Source Select Bit: 0"]
pub type SelsR = crate::FieldReader<Sels>;
impl SelsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Sels {
match self.bits {
0 => Sels::Sels0,
1 => Sels::Sels1,
2 => Sels::Sels2,
3 => Sels::Sels3,
4 => Sels::Sels4,
5 => Sels::Sels5,
6 => Sels::Sels6,
7 => Sels::Sels7,
_ => unreachable!(),
}
}
#[doc = "SMCLK Source Select 0"]
#[inline(always)]
pub fn is_sels_0(&self) -> bool {
*self == Sels::Sels0
}
#[doc = "SMCLK Source Select 1"]
#[inline(always)]
pub fn is_sels_1(&self) -> bool {
*self == Sels::Sels1
}
#[doc = "SMCLK Source Select 2"]
#[inline(always)]
pub fn is_sels_2(&self) -> bool {
*self == Sels::Sels2
}
#[doc = "SMCLK Source Select 3"]
#[inline(always)]
pub fn is_sels_3(&self) -> bool {
*self == Sels::Sels3
}
#[doc = "SMCLK Source Select 4"]
#[inline(always)]
pub fn is_sels_4(&self) -> bool {
*self == Sels::Sels4
}
#[doc = "SMCLK Source Select 5"]
#[inline(always)]
pub fn is_sels_5(&self) -> bool {
*self == Sels::Sels5
}
#[doc = "SMCLK Source Select 6"]
#[inline(always)]
pub fn is_sels_6(&self) -> bool {
*self == Sels::Sels6
}
#[doc = "SMCLK Source Select 7"]
#[inline(always)]
pub fn is_sels_7(&self) -> bool {
*self == Sels::Sels7
}
}
#[doc = "Field `SELS` writer - SMCLK Source Select Bit: 0"]
pub type SelsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sels, crate::Safe>;
impl<'a, REG> SelsW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "SMCLK Source Select 0"]
#[inline(always)]
pub fn sels_0(self) -> &'a mut crate::W<REG> {
self.variant(Sels::Sels0)
}
#[doc = "SMCLK Source Select 1"]
#[inline(always)]
pub fn sels_1(self) -> &'a mut crate::W<REG> {
self.variant(Sels::Sels1)
}
#[doc = "SMCLK Source Select 2"]
#[inline(always)]
pub fn sels_2(self) -> &'a mut crate::W<REG> {
self.variant(Sels::Sels2)
}
#[doc = "SMCLK Source Select 3"]
#[inline(always)]
pub fn sels_3(self) -> &'a mut crate::W<REG> {
self.variant(Sels::Sels3)
}
#[doc = "SMCLK Source Select 4"]
#[inline(always)]
pub fn sels_4(self) -> &'a mut crate::W<REG> {
self.variant(Sels::Sels4)
}
#[doc = "SMCLK Source Select 5"]
#[inline(always)]
pub fn sels_5(self) -> &'a mut crate::W<REG> {
self.variant(Sels::Sels5)
}
#[doc = "SMCLK Source Select 6"]
#[inline(always)]
pub fn sels_6(self) -> &'a mut crate::W<REG> {
self.variant(Sels::Sels6)
}
#[doc = "SMCLK Source Select 7"]
#[inline(always)]
pub fn sels_7(self) -> &'a mut crate::W<REG> {
self.variant(Sels::Sels7)
}
}
#[doc = "ACLK Source Select Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Sela {
#[doc = "0: ACLK Source Select 0"]
Sela0 = 0,
#[doc = "1: ACLK Source Select 1"]
Sela1 = 1,
#[doc = "2: ACLK Source Select 2"]
Sela2 = 2,
#[doc = "3: ACLK Source Select 3"]
Sela3 = 3,
#[doc = "4: ACLK Source Select 4"]
Sela4 = 4,
#[doc = "5: ACLK Source Select 5"]
Sela5 = 5,
#[doc = "6: ACLK Source Select 6"]
Sela6 = 6,
#[doc = "7: ACLK Source Select 7"]
Sela7 = 7,
}
impl From<Sela> for u8 {
#[inline(always)]
fn from(variant: Sela) -> Self {
variant as _
}
}
impl crate::FieldSpec for Sela {
type Ux = u8;
}
impl crate::IsEnum for Sela {}
#[doc = "Field `SELA` reader - ACLK Source Select Bit: 0"]
pub type SelaR = crate::FieldReader<Sela>;
impl SelaR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Sela {
match self.bits {
0 => Sela::Sela0,
1 => Sela::Sela1,
2 => Sela::Sela2,
3 => Sela::Sela3,
4 => Sela::Sela4,
5 => Sela::Sela5,
6 => Sela::Sela6,
7 => Sela::Sela7,
_ => unreachable!(),
}
}
#[doc = "ACLK Source Select 0"]
#[inline(always)]
pub fn is_sela_0(&self) -> bool {
*self == Sela::Sela0
}
#[doc = "ACLK Source Select 1"]
#[inline(always)]
pub fn is_sela_1(&self) -> bool {
*self == Sela::Sela1
}
#[doc = "ACLK Source Select 2"]
#[inline(always)]
pub fn is_sela_2(&self) -> bool {
*self == Sela::Sela2
}
#[doc = "ACLK Source Select 3"]
#[inline(always)]
pub fn is_sela_3(&self) -> bool {
*self == Sela::Sela3
}
#[doc = "ACLK Source Select 4"]
#[inline(always)]
pub fn is_sela_4(&self) -> bool {
*self == Sela::Sela4
}
#[doc = "ACLK Source Select 5"]
#[inline(always)]
pub fn is_sela_5(&self) -> bool {
*self == Sela::Sela5
}
#[doc = "ACLK Source Select 6"]
#[inline(always)]
pub fn is_sela_6(&self) -> bool {
*self == Sela::Sela6
}
#[doc = "ACLK Source Select 7"]
#[inline(always)]
pub fn is_sela_7(&self) -> bool {
*self == Sela::Sela7
}
}
#[doc = "Field `SELA` writer - ACLK Source Select Bit: 0"]
pub type SelaW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sela, crate::Safe>;
impl<'a, REG> SelaW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ACLK Source Select 0"]
#[inline(always)]
pub fn sela_0(self) -> &'a mut crate::W<REG> {
self.variant(Sela::Sela0)
}
#[doc = "ACLK Source Select 1"]
#[inline(always)]
pub fn sela_1(self) -> &'a mut crate::W<REG> {
self.variant(Sela::Sela1)
}
#[doc = "ACLK Source Select 2"]
#[inline(always)]
pub fn sela_2(self) -> &'a mut crate::W<REG> {
self.variant(Sela::Sela2)
}
#[doc = "ACLK Source Select 3"]
#[inline(always)]
pub fn sela_3(self) -> &'a mut crate::W<REG> {
self.variant(Sela::Sela3)
}
#[doc = "ACLK Source Select 4"]
#[inline(always)]
pub fn sela_4(self) -> &'a mut crate::W<REG> {
self.variant(Sela::Sela4)
}
#[doc = "ACLK Source Select 5"]
#[inline(always)]
pub fn sela_5(self) -> &'a mut crate::W<REG> {
self.variant(Sela::Sela5)
}
#[doc = "ACLK Source Select 6"]
#[inline(always)]
pub fn sela_6(self) -> &'a mut crate::W<REG> {
self.variant(Sela::Sela6)
}
#[doc = "ACLK Source Select 7"]
#[inline(always)]
pub fn sela_7(self) -> &'a mut crate::W<REG> {
self.variant(Sela::Sela7)
}
}
impl R {
#[doc = "Bits 0:2 - MCLK Source Select Bit: 0"]
#[inline(always)]
pub fn selm(&self) -> SelmR {
SelmR::new((self.bits & 7) as u8)
}
#[doc = "Bits 4:6 - SMCLK Source Select Bit: 0"]
#[inline(always)]
pub fn sels(&self) -> SelsR {
SelsR::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bits 8:10 - ACLK Source Select Bit: 0"]
#[inline(always)]
pub fn sela(&self) -> SelaR {
SelaR::new(((self.bits >> 8) & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:2 - MCLK Source Select Bit: 0"]
#[inline(always)]
pub fn selm(&mut self) -> SelmW<'_, Csctl2Spec> {
SelmW::new(self, 0)
}
#[doc = "Bits 4:6 - SMCLK Source Select Bit: 0"]
#[inline(always)]
pub fn sels(&mut self) -> SelsW<'_, Csctl2Spec> {
SelsW::new(self, 4)
}
#[doc = "Bits 8:10 - ACLK Source Select Bit: 0"]
#[inline(always)]
pub fn sela(&mut self) -> SelaW<'_, Csctl2Spec> {
SelaW::new(self, 8)
}
}
#[doc = "CS Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`csctl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csctl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Csctl2Spec;
impl crate::RegisterSpec for Csctl2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`csctl2::R`](R) reader structure"]
impl crate::Readable for Csctl2Spec {}
#[doc = "`write(|w| ..)` method takes [`csctl2::W`](W) writer structure"]
impl crate::Writable for Csctl2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CSCTL2 to value 0"]
impl crate::Resettable for Csctl2Spec {}
}
#[doc = "CSCTL3 (rw) register accessor: CS Control Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`csctl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csctl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csctl3`] module"]
#[doc(alias = "CSCTL3")]
pub type Csctl3 = crate::Reg<csctl3::Csctl3Spec>;
#[doc = "CS Control Register 3"]
pub mod csctl3 {
#[doc = "Register `CSCTL3` reader"]
pub type R = crate::R<Csctl3Spec>;
#[doc = "Register `CSCTL3` writer"]
pub type W = crate::W<Csctl3Spec>;
#[doc = "MCLK Divider Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Divm {
#[doc = "0: MCLK Source Divider 0"]
Divm0 = 0,
#[doc = "1: MCLK Source Divider 1"]
Divm1 = 1,
#[doc = "2: MCLK Source Divider 2"]
Divm2 = 2,
#[doc = "3: MCLK Source Divider 3"]
Divm3 = 3,
#[doc = "4: MCLK Source Divider 4"]
Divm4 = 4,
#[doc = "5: MCLK Source Divider 5"]
Divm5 = 5,
}
impl From<Divm> for u8 {
#[inline(always)]
fn from(variant: Divm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Divm {
type Ux = u8;
}
impl crate::IsEnum for Divm {}
#[doc = "Field `DIVM` reader - MCLK Divider Bit: 0"]
pub type DivmR = crate::FieldReader<Divm>;
impl DivmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Divm> {
match self.bits {
0 => Some(Divm::Divm0),
1 => Some(Divm::Divm1),
2 => Some(Divm::Divm2),
3 => Some(Divm::Divm3),
4 => Some(Divm::Divm4),
5 => Some(Divm::Divm5),
_ => None,
}
}
#[doc = "MCLK Source Divider 0"]
#[inline(always)]
pub fn is_divm_0(&self) -> bool {
*self == Divm::Divm0
}
#[doc = "MCLK Source Divider 1"]
#[inline(always)]
pub fn is_divm_1(&self) -> bool {
*self == Divm::Divm1
}
#[doc = "MCLK Source Divider 2"]
#[inline(always)]
pub fn is_divm_2(&self) -> bool {
*self == Divm::Divm2
}
#[doc = "MCLK Source Divider 3"]
#[inline(always)]
pub fn is_divm_3(&self) -> bool {
*self == Divm::Divm3
}
#[doc = "MCLK Source Divider 4"]
#[inline(always)]
pub fn is_divm_4(&self) -> bool {
*self == Divm::Divm4
}
#[doc = "MCLK Source Divider 5"]
#[inline(always)]
pub fn is_divm_5(&self) -> bool {
*self == Divm::Divm5
}
}
#[doc = "Field `DIVM` writer - MCLK Divider Bit: 0"]
pub type DivmW<'a, REG> = crate::FieldWriter<'a, REG, 3, Divm>;
impl<'a, REG> DivmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "MCLK Source Divider 0"]
#[inline(always)]
pub fn divm_0(self) -> &'a mut crate::W<REG> {
self.variant(Divm::Divm0)
}
#[doc = "MCLK Source Divider 1"]
#[inline(always)]
pub fn divm_1(self) -> &'a mut crate::W<REG> {
self.variant(Divm::Divm1)
}
#[doc = "MCLK Source Divider 2"]
#[inline(always)]
pub fn divm_2(self) -> &'a mut crate::W<REG> {
self.variant(Divm::Divm2)
}
#[doc = "MCLK Source Divider 3"]
#[inline(always)]
pub fn divm_3(self) -> &'a mut crate::W<REG> {
self.variant(Divm::Divm3)
}
#[doc = "MCLK Source Divider 4"]
#[inline(always)]
pub fn divm_4(self) -> &'a mut crate::W<REG> {
self.variant(Divm::Divm4)
}
#[doc = "MCLK Source Divider 5"]
#[inline(always)]
pub fn divm_5(self) -> &'a mut crate::W<REG> {
self.variant(Divm::Divm5)
}
}
#[doc = "SMCLK Divider Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Divs {
#[doc = "0: SMCLK Source Divider 0"]
Divs0 = 0,
#[doc = "1: SMCLK Source Divider 1"]
Divs1 = 1,
#[doc = "2: SMCLK Source Divider 2"]
Divs2 = 2,
#[doc = "3: SMCLK Source Divider 3"]
Divs3 = 3,
#[doc = "4: SMCLK Source Divider 4"]
Divs4 = 4,
#[doc = "5: SMCLK Source Divider 5"]
Divs5 = 5,
}
impl From<Divs> for u8 {
#[inline(always)]
fn from(variant: Divs) -> Self {
variant as _
}
}
impl crate::FieldSpec for Divs {
type Ux = u8;
}
impl crate::IsEnum for Divs {}
#[doc = "Field `DIVS` reader - SMCLK Divider Bit: 0"]
pub type DivsR = crate::FieldReader<Divs>;
impl DivsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Divs> {
match self.bits {
0 => Some(Divs::Divs0),
1 => Some(Divs::Divs1),
2 => Some(Divs::Divs2),
3 => Some(Divs::Divs3),
4 => Some(Divs::Divs4),
5 => Some(Divs::Divs5),
_ => None,
}
}
#[doc = "SMCLK Source Divider 0"]
#[inline(always)]
pub fn is_divs_0(&self) -> bool {
*self == Divs::Divs0
}
#[doc = "SMCLK Source Divider 1"]
#[inline(always)]
pub fn is_divs_1(&self) -> bool {
*self == Divs::Divs1
}
#[doc = "SMCLK Source Divider 2"]
#[inline(always)]
pub fn is_divs_2(&self) -> bool {
*self == Divs::Divs2
}
#[doc = "SMCLK Source Divider 3"]
#[inline(always)]
pub fn is_divs_3(&self) -> bool {
*self == Divs::Divs3
}
#[doc = "SMCLK Source Divider 4"]
#[inline(always)]
pub fn is_divs_4(&self) -> bool {
*self == Divs::Divs4
}
#[doc = "SMCLK Source Divider 5"]
#[inline(always)]
pub fn is_divs_5(&self) -> bool {
*self == Divs::Divs5
}
}
#[doc = "Field `DIVS` writer - SMCLK Divider Bit: 0"]
pub type DivsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Divs>;
impl<'a, REG> DivsW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "SMCLK Source Divider 0"]
#[inline(always)]
pub fn divs_0(self) -> &'a mut crate::W<REG> {
self.variant(Divs::Divs0)
}
#[doc = "SMCLK Source Divider 1"]
#[inline(always)]
pub fn divs_1(self) -> &'a mut crate::W<REG> {
self.variant(Divs::Divs1)
}
#[doc = "SMCLK Source Divider 2"]
#[inline(always)]
pub fn divs_2(self) -> &'a mut crate::W<REG> {
self.variant(Divs::Divs2)
}
#[doc = "SMCLK Source Divider 3"]
#[inline(always)]
pub fn divs_3(self) -> &'a mut crate::W<REG> {
self.variant(Divs::Divs3)
}
#[doc = "SMCLK Source Divider 4"]
#[inline(always)]
pub fn divs_4(self) -> &'a mut crate::W<REG> {
self.variant(Divs::Divs4)
}
#[doc = "SMCLK Source Divider 5"]
#[inline(always)]
pub fn divs_5(self) -> &'a mut crate::W<REG> {
self.variant(Divs::Divs5)
}
}
#[doc = "ACLK Divider Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Diva {
#[doc = "0: ACLK Source Divider 0"]
Diva0 = 0,
#[doc = "1: ACLK Source Divider 1"]
Diva1 = 1,
#[doc = "2: ACLK Source Divider 2"]
Diva2 = 2,
#[doc = "3: ACLK Source Divider 3"]
Diva3 = 3,
#[doc = "4: ACLK Source Divider 4"]
Diva4 = 4,
#[doc = "5: ACLK Source Divider 5"]
Diva5 = 5,
}
impl From<Diva> for u8 {
#[inline(always)]
fn from(variant: Diva) -> Self {
variant as _
}
}
impl crate::FieldSpec for Diva {
type Ux = u8;
}
impl crate::IsEnum for Diva {}
#[doc = "Field `DIVA` reader - ACLK Divider Bit: 0"]
pub type DivaR = crate::FieldReader<Diva>;
impl DivaR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Diva> {
match self.bits {
0 => Some(Diva::Diva0),
1 => Some(Diva::Diva1),
2 => Some(Diva::Diva2),
3 => Some(Diva::Diva3),
4 => Some(Diva::Diva4),
5 => Some(Diva::Diva5),
_ => None,
}
}
#[doc = "ACLK Source Divider 0"]
#[inline(always)]
pub fn is_diva_0(&self) -> bool {
*self == Diva::Diva0
}
#[doc = "ACLK Source Divider 1"]
#[inline(always)]
pub fn is_diva_1(&self) -> bool {
*self == Diva::Diva1
}
#[doc = "ACLK Source Divider 2"]
#[inline(always)]
pub fn is_diva_2(&self) -> bool {
*self == Diva::Diva2
}
#[doc = "ACLK Source Divider 3"]
#[inline(always)]
pub fn is_diva_3(&self) -> bool {
*self == Diva::Diva3
}
#[doc = "ACLK Source Divider 4"]
#[inline(always)]
pub fn is_diva_4(&self) -> bool {
*self == Diva::Diva4
}
#[doc = "ACLK Source Divider 5"]
#[inline(always)]
pub fn is_diva_5(&self) -> bool {
*self == Diva::Diva5
}
}
#[doc = "Field `DIVA` writer - ACLK Divider Bit: 0"]
pub type DivaW<'a, REG> = crate::FieldWriter<'a, REG, 3, Diva>;
impl<'a, REG> DivaW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ACLK Source Divider 0"]
#[inline(always)]
pub fn diva_0(self) -> &'a mut crate::W<REG> {
self.variant(Diva::Diva0)
}
#[doc = "ACLK Source Divider 1"]
#[inline(always)]
pub fn diva_1(self) -> &'a mut crate::W<REG> {
self.variant(Diva::Diva1)
}
#[doc = "ACLK Source Divider 2"]
#[inline(always)]
pub fn diva_2(self) -> &'a mut crate::W<REG> {
self.variant(Diva::Diva2)
}
#[doc = "ACLK Source Divider 3"]
#[inline(always)]
pub fn diva_3(self) -> &'a mut crate::W<REG> {
self.variant(Diva::Diva3)
}
#[doc = "ACLK Source Divider 4"]
#[inline(always)]
pub fn diva_4(self) -> &'a mut crate::W<REG> {
self.variant(Diva::Diva4)
}
#[doc = "ACLK Source Divider 5"]
#[inline(always)]
pub fn diva_5(self) -> &'a mut crate::W<REG> {
self.variant(Diva::Diva5)
}
}
impl R {
#[doc = "Bits 0:2 - MCLK Divider Bit: 0"]
#[inline(always)]
pub fn divm(&self) -> DivmR {
DivmR::new((self.bits & 7) as u8)
}
#[doc = "Bits 4:6 - SMCLK Divider Bit: 0"]
#[inline(always)]
pub fn divs(&self) -> DivsR {
DivsR::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bits 8:10 - ACLK Divider Bit: 0"]
#[inline(always)]
pub fn diva(&self) -> DivaR {
DivaR::new(((self.bits >> 8) & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:2 - MCLK Divider Bit: 0"]
#[inline(always)]
pub fn divm(&mut self) -> DivmW<'_, Csctl3Spec> {
DivmW::new(self, 0)
}
#[doc = "Bits 4:6 - SMCLK Divider Bit: 0"]
#[inline(always)]
pub fn divs(&mut self) -> DivsW<'_, Csctl3Spec> {
DivsW::new(self, 4)
}
#[doc = "Bits 8:10 - ACLK Divider Bit: 0"]
#[inline(always)]
pub fn diva(&mut self) -> DivaW<'_, Csctl3Spec> {
DivaW::new(self, 8)
}
}
#[doc = "CS Control Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`csctl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csctl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Csctl3Spec;
impl crate::RegisterSpec for Csctl3Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`csctl3::R`](R) reader structure"]
impl crate::Readable for Csctl3Spec {}
#[doc = "`write(|w| ..)` method takes [`csctl3::W`](W) writer structure"]
impl crate::Writable for Csctl3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CSCTL3 to value 0"]
impl crate::Resettable for Csctl3Spec {}
}
#[doc = "CSCTL4 (rw) register accessor: CS Control Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`csctl4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csctl4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csctl4`] module"]
#[doc(alias = "CSCTL4")]
pub type Csctl4 = crate::Reg<csctl4::Csctl4Spec>;
#[doc = "CS Control Register 4"]
pub mod csctl4 {
#[doc = "Register `CSCTL4` reader"]
pub type R = crate::R<Csctl4Spec>;
#[doc = "Register `CSCTL4` writer"]
pub type W = crate::W<Csctl4Spec>;
#[doc = "Field `LFXTOFF` reader - Low Frequency Oscillator (LFXT) disable"]
pub type LfxtoffR = crate::BitReader;
#[doc = "Field `LFXTOFF` writer - Low Frequency Oscillator (LFXT) disable"]
pub type LfxtoffW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SMCLKOFF` reader - SMCLK Off"]
pub type SmclkoffR = crate::BitReader;
#[doc = "Field `SMCLKOFF` writer - SMCLK Off"]
pub type SmclkoffW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `VLOOFF` reader - VLO Off"]
pub type VlooffR = crate::BitReader;
#[doc = "Field `VLOOFF` writer - VLO Off"]
pub type VlooffW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LFXTBYPASS` reader - LFXT bypass mode : 0: internal 1:sourced from external pin"]
pub type LfxtbypassR = crate::BitReader;
#[doc = "Field `LFXTBYPASS` writer - LFXT bypass mode : 0: internal 1:sourced from external pin"]
pub type LfxtbypassW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "LFXT Drive Level mode Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Lfxtdrive {
#[doc = "0: LFXT Drive Level mode: 0"]
Lfxtdrive0 = 0,
#[doc = "1: LFXT Drive Level mode: 1"]
Lfxtdrive1 = 1,
#[doc = "2: LFXT Drive Level mode: 2"]
Lfxtdrive2 = 2,
#[doc = "3: LFXT Drive Level mode: 3"]
Lfxtdrive3 = 3,
}
impl From<Lfxtdrive> for u8 {
#[inline(always)]
fn from(variant: Lfxtdrive) -> Self {
variant as _
}
}
impl crate::FieldSpec for Lfxtdrive {
type Ux = u8;
}
impl crate::IsEnum for Lfxtdrive {}
#[doc = "Field `LFXTDRIVE` reader - LFXT Drive Level mode Bit 0"]
pub type LfxtdriveR = crate::FieldReader<Lfxtdrive>;
impl LfxtdriveR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Lfxtdrive {
match self.bits {
0 => Lfxtdrive::Lfxtdrive0,
1 => Lfxtdrive::Lfxtdrive1,
2 => Lfxtdrive::Lfxtdrive2,
3 => Lfxtdrive::Lfxtdrive3,
_ => unreachable!(),
}
}
#[doc = "LFXT Drive Level mode: 0"]
#[inline(always)]
pub fn is_lfxtdrive_0(&self) -> bool {
*self == Lfxtdrive::Lfxtdrive0
}
#[doc = "LFXT Drive Level mode: 1"]
#[inline(always)]
pub fn is_lfxtdrive_1(&self) -> bool {
*self == Lfxtdrive::Lfxtdrive1
}
#[doc = "LFXT Drive Level mode: 2"]
#[inline(always)]
pub fn is_lfxtdrive_2(&self) -> bool {
*self == Lfxtdrive::Lfxtdrive2
}
#[doc = "LFXT Drive Level mode: 3"]
#[inline(always)]
pub fn is_lfxtdrive_3(&self) -> bool {
*self == Lfxtdrive::Lfxtdrive3
}
}
#[doc = "Field `LFXTDRIVE` writer - LFXT Drive Level mode Bit 0"]
pub type LfxtdriveW<'a, REG> = crate::FieldWriter<'a, REG, 2, Lfxtdrive, crate::Safe>;
impl<'a, REG> LfxtdriveW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "LFXT Drive Level mode: 0"]
#[inline(always)]
pub fn lfxtdrive_0(self) -> &'a mut crate::W<REG> {
self.variant(Lfxtdrive::Lfxtdrive0)
}
#[doc = "LFXT Drive Level mode: 1"]
#[inline(always)]
pub fn lfxtdrive_1(self) -> &'a mut crate::W<REG> {
self.variant(Lfxtdrive::Lfxtdrive1)
}
#[doc = "LFXT Drive Level mode: 2"]
#[inline(always)]
pub fn lfxtdrive_2(self) -> &'a mut crate::W<REG> {
self.variant(Lfxtdrive::Lfxtdrive2)
}
#[doc = "LFXT Drive Level mode: 3"]
#[inline(always)]
pub fn lfxtdrive_3(self) -> &'a mut crate::W<REG> {
self.variant(Lfxtdrive::Lfxtdrive3)
}
}
#[doc = "Field `HFXTOFF` reader - High Frequency Oscillator disable"]
pub type HfxtoffR = crate::BitReader;
#[doc = "Field `HFXTOFF` writer - High Frequency Oscillator disable"]
pub type HfxtoffW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "HFXT frequency selection Bit 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Hffreq {
#[doc = "0: HFXT frequency selection: 0"]
Hffreq0 = 0,
#[doc = "1: HFXT frequency selection: 1"]
Hffreq1 = 1,
#[doc = "2: HFXT frequency selection: 2"]
Hffreq2 = 2,
#[doc = "3: HFXT frequency selection: 3"]
Hffreq3 = 3,
}
impl From<Hffreq> for u8 {
#[inline(always)]
fn from(variant: Hffreq) -> Self {
variant as _
}
}
impl crate::FieldSpec for Hffreq {
type Ux = u8;
}
impl crate::IsEnum for Hffreq {}
#[doc = "Field `HFFREQ` reader - HFXT frequency selection Bit 1"]
pub type HffreqR = crate::FieldReader<Hffreq>;
impl HffreqR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hffreq {
match self.bits {
0 => Hffreq::Hffreq0,
1 => Hffreq::Hffreq1,
2 => Hffreq::Hffreq2,
3 => Hffreq::Hffreq3,
_ => unreachable!(),
}
}
#[doc = "HFXT frequency selection: 0"]
#[inline(always)]
pub fn is_hffreq_0(&self) -> bool {
*self == Hffreq::Hffreq0
}
#[doc = "HFXT frequency selection: 1"]
#[inline(always)]
pub fn is_hffreq_1(&self) -> bool {
*self == Hffreq::Hffreq1
}
#[doc = "HFXT frequency selection: 2"]
#[inline(always)]
pub fn is_hffreq_2(&self) -> bool {
*self == Hffreq::Hffreq2
}
#[doc = "HFXT frequency selection: 3"]
#[inline(always)]
pub fn is_hffreq_3(&self) -> bool {
*self == Hffreq::Hffreq3
}
}
#[doc = "Field `HFFREQ` writer - HFXT frequency selection Bit 1"]
pub type HffreqW<'a, REG> = crate::FieldWriter<'a, REG, 2, Hffreq, crate::Safe>;
impl<'a, REG> HffreqW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "HFXT frequency selection: 0"]
#[inline(always)]
pub fn hffreq_0(self) -> &'a mut crate::W<REG> {
self.variant(Hffreq::Hffreq0)
}
#[doc = "HFXT frequency selection: 1"]
#[inline(always)]
pub fn hffreq_1(self) -> &'a mut crate::W<REG> {
self.variant(Hffreq::Hffreq1)
}
#[doc = "HFXT frequency selection: 2"]
#[inline(always)]
pub fn hffreq_2(self) -> &'a mut crate::W<REG> {
self.variant(Hffreq::Hffreq2)
}
#[doc = "HFXT frequency selection: 3"]
#[inline(always)]
pub fn hffreq_3(self) -> &'a mut crate::W<REG> {
self.variant(Hffreq::Hffreq3)
}
}
#[doc = "Field `HFXTBYPASS` reader - HFXT bypass mode : 0: internal 1:sourced from external pin"]
pub type HfxtbypassR = crate::BitReader;
#[doc = "Field `HFXTBYPASS` writer - HFXT bypass mode : 0: internal 1:sourced from external pin"]
pub type HfxtbypassW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "HFXT Drive Level mode Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Hfxtdrive {
#[doc = "0: HFXT Drive Level mode: 0"]
Hfxtdrive0 = 0,
#[doc = "1: HFXT Drive Level mode: 1"]
Hfxtdrive1 = 1,
#[doc = "2: HFXT Drive Level mode: 2"]
Hfxtdrive2 = 2,
#[doc = "3: HFXT Drive Level mode: 3"]
Hfxtdrive3 = 3,
}
impl From<Hfxtdrive> for u8 {
#[inline(always)]
fn from(variant: Hfxtdrive) -> Self {
variant as _
}
}
impl crate::FieldSpec for Hfxtdrive {
type Ux = u8;
}
impl crate::IsEnum for Hfxtdrive {}
#[doc = "Field `HFXTDRIVE` reader - HFXT Drive Level mode Bit 0"]
pub type HfxtdriveR = crate::FieldReader<Hfxtdrive>;
impl HfxtdriveR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hfxtdrive {
match self.bits {
0 => Hfxtdrive::Hfxtdrive0,
1 => Hfxtdrive::Hfxtdrive1,
2 => Hfxtdrive::Hfxtdrive2,
3 => Hfxtdrive::Hfxtdrive3,
_ => unreachable!(),
}
}
#[doc = "HFXT Drive Level mode: 0"]
#[inline(always)]
pub fn is_hfxtdrive_0(&self) -> bool {
*self == Hfxtdrive::Hfxtdrive0
}
#[doc = "HFXT Drive Level mode: 1"]
#[inline(always)]
pub fn is_hfxtdrive_1(&self) -> bool {
*self == Hfxtdrive::Hfxtdrive1
}
#[doc = "HFXT Drive Level mode: 2"]
#[inline(always)]
pub fn is_hfxtdrive_2(&self) -> bool {
*self == Hfxtdrive::Hfxtdrive2
}
#[doc = "HFXT Drive Level mode: 3"]
#[inline(always)]
pub fn is_hfxtdrive_3(&self) -> bool {
*self == Hfxtdrive::Hfxtdrive3
}
}
#[doc = "Field `HFXTDRIVE` writer - HFXT Drive Level mode Bit 0"]
pub type HfxtdriveW<'a, REG> = crate::FieldWriter<'a, REG, 2, Hfxtdrive, crate::Safe>;
impl<'a, REG> HfxtdriveW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "HFXT Drive Level mode: 0"]
#[inline(always)]
pub fn hfxtdrive_0(self) -> &'a mut crate::W<REG> {
self.variant(Hfxtdrive::Hfxtdrive0)
}
#[doc = "HFXT Drive Level mode: 1"]
#[inline(always)]
pub fn hfxtdrive_1(self) -> &'a mut crate::W<REG> {
self.variant(Hfxtdrive::Hfxtdrive1)
}
#[doc = "HFXT Drive Level mode: 2"]
#[inline(always)]
pub fn hfxtdrive_2(self) -> &'a mut crate::W<REG> {
self.variant(Hfxtdrive::Hfxtdrive2)
}
#[doc = "HFXT Drive Level mode: 3"]
#[inline(always)]
pub fn hfxtdrive_3(self) -> &'a mut crate::W<REG> {
self.variant(Hfxtdrive::Hfxtdrive3)
}
}
impl R {
#[doc = "Bit 0 - Low Frequency Oscillator (LFXT) disable"]
#[inline(always)]
pub fn lfxtoff(&self) -> LfxtoffR {
LfxtoffR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - SMCLK Off"]
#[inline(always)]
pub fn smclkoff(&self) -> SmclkoffR {
SmclkoffR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 3 - VLO Off"]
#[inline(always)]
pub fn vlooff(&self) -> VlooffR {
VlooffR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - LFXT bypass mode : 0: internal 1:sourced from external pin"]
#[inline(always)]
pub fn lfxtbypass(&self) -> LfxtbypassR {
LfxtbypassR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 6:7 - LFXT Drive Level mode Bit 0"]
#[inline(always)]
pub fn lfxtdrive(&self) -> LfxtdriveR {
LfxtdriveR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bit 8 - High Frequency Oscillator disable"]
#[inline(always)]
pub fn hfxtoff(&self) -> HfxtoffR {
HfxtoffR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 10:11 - HFXT frequency selection Bit 1"]
#[inline(always)]
pub fn hffreq(&self) -> HffreqR {
HffreqR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bit 12 - HFXT bypass mode : 0: internal 1:sourced from external pin"]
#[inline(always)]
pub fn hfxtbypass(&self) -> HfxtbypassR {
HfxtbypassR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bits 14:15 - HFXT Drive Level mode Bit 0"]
#[inline(always)]
pub fn hfxtdrive(&self) -> HfxtdriveR {
HfxtdriveR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Low Frequency Oscillator (LFXT) disable"]
#[inline(always)]
pub fn lfxtoff(&mut self) -> LfxtoffW<'_, Csctl4Spec> {
LfxtoffW::new(self, 0)
}
#[doc = "Bit 1 - SMCLK Off"]
#[inline(always)]
pub fn smclkoff(&mut self) -> SmclkoffW<'_, Csctl4Spec> {
SmclkoffW::new(self, 1)
}
#[doc = "Bit 3 - VLO Off"]
#[inline(always)]
pub fn vlooff(&mut self) -> VlooffW<'_, Csctl4Spec> {
VlooffW::new(self, 3)
}
#[doc = "Bit 4 - LFXT bypass mode : 0: internal 1:sourced from external pin"]
#[inline(always)]
pub fn lfxtbypass(&mut self) -> LfxtbypassW<'_, Csctl4Spec> {
LfxtbypassW::new(self, 4)
}
#[doc = "Bits 6:7 - LFXT Drive Level mode Bit 0"]
#[inline(always)]
pub fn lfxtdrive(&mut self) -> LfxtdriveW<'_, Csctl4Spec> {
LfxtdriveW::new(self, 6)
}
#[doc = "Bit 8 - High Frequency Oscillator disable"]
#[inline(always)]
pub fn hfxtoff(&mut self) -> HfxtoffW<'_, Csctl4Spec> {
HfxtoffW::new(self, 8)
}
#[doc = "Bits 10:11 - HFXT frequency selection Bit 1"]
#[inline(always)]
pub fn hffreq(&mut self) -> HffreqW<'_, Csctl4Spec> {
HffreqW::new(self, 10)
}
#[doc = "Bit 12 - HFXT bypass mode : 0: internal 1:sourced from external pin"]
#[inline(always)]
pub fn hfxtbypass(&mut self) -> HfxtbypassW<'_, Csctl4Spec> {
HfxtbypassW::new(self, 12)
}
#[doc = "Bits 14:15 - HFXT Drive Level mode Bit 0"]
#[inline(always)]
pub fn hfxtdrive(&mut self) -> HfxtdriveW<'_, Csctl4Spec> {
HfxtdriveW::new(self, 14)
}
}
#[doc = "CS Control Register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`csctl4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csctl4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Csctl4Spec;
impl crate::RegisterSpec for Csctl4Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`csctl4::R`](R) reader structure"]
impl crate::Readable for Csctl4Spec {}
#[doc = "`write(|w| ..)` method takes [`csctl4::W`](W) writer structure"]
impl crate::Writable for Csctl4Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CSCTL4 to value 0"]
impl crate::Resettable for Csctl4Spec {}
}
#[doc = "CSCTL5 (rw) register accessor: CS Control Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`csctl5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csctl5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csctl5`] module"]
#[doc(alias = "CSCTL5")]
pub type Csctl5 = crate::Reg<csctl5::Csctl5Spec>;
#[doc = "CS Control Register 5"]
pub mod csctl5 {
#[doc = "Register `CSCTL5` reader"]
pub type R = crate::R<Csctl5Spec>;
#[doc = "Register `CSCTL5` writer"]
pub type W = crate::W<Csctl5Spec>;
#[doc = "Field `LFXTOFFG` reader - LFXT Low Frequency Oscillator Fault Flag"]
pub type LfxtoffgR = crate::BitReader;
#[doc = "Field `LFXTOFFG` writer - LFXT Low Frequency Oscillator Fault Flag"]
pub type LfxtoffgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HFXTOFFG` reader - HFXT High Frequency Oscillator Fault Flag"]
pub type HfxtoffgR = crate::BitReader;
#[doc = "Field `HFXTOFFG` writer - HFXT High Frequency Oscillator Fault Flag"]
pub type HfxtoffgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ENSTFCNT1` reader - Enable start counter for XT1"]
pub type Enstfcnt1R = crate::BitReader;
#[doc = "Field `ENSTFCNT1` writer - Enable start counter for XT1"]
pub type Enstfcnt1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ENSTFCNT2` reader - Enable start counter for XT2"]
pub type Enstfcnt2R = crate::BitReader;
#[doc = "Field `ENSTFCNT2` writer - Enable start counter for XT2"]
pub type Enstfcnt2W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - LFXT Low Frequency Oscillator Fault Flag"]
#[inline(always)]
pub fn lfxtoffg(&self) -> LfxtoffgR {
LfxtoffgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - HFXT High Frequency Oscillator Fault Flag"]
#[inline(always)]
pub fn hfxtoffg(&self) -> HfxtoffgR {
HfxtoffgR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 6 - Enable start counter for XT1"]
#[inline(always)]
pub fn enstfcnt1(&self) -> Enstfcnt1R {
Enstfcnt1R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Enable start counter for XT2"]
#[inline(always)]
pub fn enstfcnt2(&self) -> Enstfcnt2R {
Enstfcnt2R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - LFXT Low Frequency Oscillator Fault Flag"]
#[inline(always)]
pub fn lfxtoffg(&mut self) -> LfxtoffgW<'_, Csctl5Spec> {
LfxtoffgW::new(self, 0)
}
#[doc = "Bit 1 - HFXT High Frequency Oscillator Fault Flag"]
#[inline(always)]
pub fn hfxtoffg(&mut self) -> HfxtoffgW<'_, Csctl5Spec> {
HfxtoffgW::new(self, 1)
}
#[doc = "Bit 6 - Enable start counter for XT1"]
#[inline(always)]
pub fn enstfcnt1(&mut self) -> Enstfcnt1W<'_, Csctl5Spec> {
Enstfcnt1W::new(self, 6)
}
#[doc = "Bit 7 - Enable start counter for XT2"]
#[inline(always)]
pub fn enstfcnt2(&mut self) -> Enstfcnt2W<'_, Csctl5Spec> {
Enstfcnt2W::new(self, 7)
}
}
#[doc = "CS Control Register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`csctl5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csctl5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Csctl5Spec;
impl crate::RegisterSpec for Csctl5Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`csctl5::R`](R) reader structure"]
impl crate::Readable for Csctl5Spec {}
#[doc = "`write(|w| ..)` method takes [`csctl5::W`](W) writer structure"]
impl crate::Writable for Csctl5Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CSCTL5 to value 0"]
impl crate::Resettable for Csctl5Spec {}
}
#[doc = "CSCTL6 (rw) register accessor: CS Control Register 6\n\nYou can [`read`](crate::Reg::read) this register and get [`csctl6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csctl6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csctl6`] module"]
#[doc(alias = "CSCTL6")]
pub type Csctl6 = crate::Reg<csctl6::Csctl6Spec>;
#[doc = "CS Control Register 6"]
pub mod csctl6 {
#[doc = "Register `CSCTL6` reader"]
pub type R = crate::R<Csctl6Spec>;
#[doc = "Register `CSCTL6` writer"]
pub type W = crate::W<Csctl6Spec>;
#[doc = "Field `ACLKREQEN` reader - ACLK Clock Request Enable"]
pub type AclkreqenR = crate::BitReader;
#[doc = "Field `ACLKREQEN` writer - ACLK Clock Request Enable"]
pub type AclkreqenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MCLKREQEN` reader - MCLK Clock Request Enable"]
pub type MclkreqenR = crate::BitReader;
#[doc = "Field `MCLKREQEN` writer - MCLK Clock Request Enable"]
pub type MclkreqenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SMCLKREQEN` reader - SMCLK Clock Request Enable"]
pub type SmclkreqenR = crate::BitReader;
#[doc = "Field `SMCLKREQEN` writer - SMCLK Clock Request Enable"]
pub type SmclkreqenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MODCLKREQEN` reader - MODOSC Clock Request Enable"]
pub type ModclkreqenR = crate::BitReader;
#[doc = "Field `MODCLKREQEN` writer - MODOSC Clock Request Enable"]
pub type ModclkreqenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - ACLK Clock Request Enable"]
#[inline(always)]
pub fn aclkreqen(&self) -> AclkreqenR {
AclkreqenR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - MCLK Clock Request Enable"]
#[inline(always)]
pub fn mclkreqen(&self) -> MclkreqenR {
MclkreqenR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - SMCLK Clock Request Enable"]
#[inline(always)]
pub fn smclkreqen(&self) -> SmclkreqenR {
SmclkreqenR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - MODOSC Clock Request Enable"]
#[inline(always)]
pub fn modclkreqen(&self) -> ModclkreqenR {
ModclkreqenR::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - ACLK Clock Request Enable"]
#[inline(always)]
pub fn aclkreqen(&mut self) -> AclkreqenW<'_, Csctl6Spec> {
AclkreqenW::new(self, 0)
}
#[doc = "Bit 1 - MCLK Clock Request Enable"]
#[inline(always)]
pub fn mclkreqen(&mut self) -> MclkreqenW<'_, Csctl6Spec> {
MclkreqenW::new(self, 1)
}
#[doc = "Bit 2 - SMCLK Clock Request Enable"]
#[inline(always)]
pub fn smclkreqen(&mut self) -> SmclkreqenW<'_, Csctl6Spec> {
SmclkreqenW::new(self, 2)
}
#[doc = "Bit 3 - MODOSC Clock Request Enable"]
#[inline(always)]
pub fn modclkreqen(&mut self) -> ModclkreqenW<'_, Csctl6Spec> {
ModclkreqenW::new(self, 3)
}
}
#[doc = "CS Control Register 6\n\nYou can [`read`](crate::Reg::read) this register and get [`csctl6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csctl6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Csctl6Spec;
impl crate::RegisterSpec for Csctl6Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`csctl6::R`](R) reader structure"]
impl crate::Readable for Csctl6Spec {}
#[doc = "`write(|w| ..)` method takes [`csctl6::W`](W) writer structure"]
impl crate::Writable for Csctl6Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CSCTL6 to value 0"]
impl crate::Resettable for Csctl6Spec {}
}
}
#[doc = "SYS System Module"]
pub type Sys = crate::Periph<sys::RegisterBlock, 0x0180>;
impl core::fmt::Debug for Sys {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Sys").finish()
}
}
#[doc = "SYS System Module"]
pub mod sys {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
sysctl: Sysctl,
_reserved1: [u8; 0x04],
sysjmbc: Sysjmbc,
sysjmbi0: Sysjmbi0,
sysjmbi1: Sysjmbi1,
sysjmbo0: Sysjmbo0,
sysjmbo1: Sysjmbo1,
_reserved6: [u8; 0x0a],
sysuniv: Sysuniv,
syssniv: Syssniv,
sysrstiv: Sysrstiv,
}
impl RegisterBlock {
#[doc = "0x00 - System control"]
#[inline(always)]
pub const fn sysctl(&self) -> &Sysctl {
&self.sysctl
}
#[doc = "0x06 - JTAG mailbox control"]
#[inline(always)]
pub const fn sysjmbc(&self) -> &Sysjmbc {
&self.sysjmbc
}
#[doc = "0x08 - JTAG mailbox input 0"]
#[inline(always)]
pub const fn sysjmbi0(&self) -> &Sysjmbi0 {
&self.sysjmbi0
}
#[doc = "0x0a - JTAG mailbox input 1"]
#[inline(always)]
pub const fn sysjmbi1(&self) -> &Sysjmbi1 {
&self.sysjmbi1
}
#[doc = "0x0c - JTAG mailbox output 0"]
#[inline(always)]
pub const fn sysjmbo0(&self) -> &Sysjmbo0 {
&self.sysjmbo0
}
#[doc = "0x0e - JTAG mailbox output 1"]
#[inline(always)]
pub const fn sysjmbo1(&self) -> &Sysjmbo1 {
&self.sysjmbo1
}
#[doc = "0x1a - User NMI vector generator"]
#[inline(always)]
pub const fn sysuniv(&self) -> &Sysuniv {
&self.sysuniv
}
#[doc = "0x1c - System NMI vector generator"]
#[inline(always)]
pub const fn syssniv(&self) -> &Syssniv {
&self.syssniv
}
#[doc = "0x1e - Reset vector generator"]
#[inline(always)]
pub const fn sysrstiv(&self) -> &Sysrstiv {
&self.sysrstiv
}
}
#[doc = "SYSCTL (rw) register accessor: System control\n\nYou can [`read`](crate::Reg::read) this register and get [`sysctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysctl`] module"]
#[doc(alias = "SYSCTL")]
pub type Sysctl = crate::Reg<sysctl::SysctlSpec>;
#[doc = "System control"]
pub mod sysctl {
#[doc = "Register `SYSCTL` reader"]
pub type R = crate::R<SysctlSpec>;
#[doc = "Register `SYSCTL` writer"]
pub type W = crate::W<SysctlSpec>;
#[doc = "Field `SYSRIVECT` reader - SYS - RAM based interrupt vectors"]
pub type SysrivectR = crate::BitReader;
#[doc = "Field `SYSRIVECT` writer - SYS - RAM based interrupt vectors"]
pub type SysrivectW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SYSPMMPE` reader - SYS - PMM access protect"]
pub type SyspmmpeR = crate::BitReader;
#[doc = "Field `SYSPMMPE` writer - SYS - PMM access protect"]
pub type SyspmmpeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SYSBSLIND` reader - SYS - TCK/RST indication detected"]
pub type SysbslindR = crate::BitReader;
#[doc = "Field `SYSBSLIND` writer - SYS - TCK/RST indication detected"]
pub type SysbslindW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SYSJTAGPIN` reader - SYS - Dedicated JTAG pins enabled"]
pub type SysjtagpinR = crate::BitReader;
#[doc = "Field `SYSJTAGPIN` writer - SYS - Dedicated JTAG pins enabled"]
pub type SysjtagpinW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - SYS - RAM based interrupt vectors"]
#[inline(always)]
pub fn sysrivect(&self) -> SysrivectR {
SysrivectR::new((self.bits & 1) != 0)
}
#[doc = "Bit 2 - SYS - PMM access protect"]
#[inline(always)]
pub fn syspmmpe(&self) -> SyspmmpeR {
SyspmmpeR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 4 - SYS - TCK/RST indication detected"]
#[inline(always)]
pub fn sysbslind(&self) -> SysbslindR {
SysbslindR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - SYS - Dedicated JTAG pins enabled"]
#[inline(always)]
pub fn sysjtagpin(&self) -> SysjtagpinR {
SysjtagpinR::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - SYS - RAM based interrupt vectors"]
#[inline(always)]
pub fn sysrivect(&mut self) -> SysrivectW<'_, SysctlSpec> {
SysrivectW::new(self, 0)
}
#[doc = "Bit 2 - SYS - PMM access protect"]
#[inline(always)]
pub fn syspmmpe(&mut self) -> SyspmmpeW<'_, SysctlSpec> {
SyspmmpeW::new(self, 2)
}
#[doc = "Bit 4 - SYS - TCK/RST indication detected"]
#[inline(always)]
pub fn sysbslind(&mut self) -> SysbslindW<'_, SysctlSpec> {
SysbslindW::new(self, 4)
}
#[doc = "Bit 5 - SYS - Dedicated JTAG pins enabled"]
#[inline(always)]
pub fn sysjtagpin(&mut self) -> SysjtagpinW<'_, SysctlSpec> {
SysjtagpinW::new(self, 5)
}
}
#[doc = "System control\n\nYou can [`read`](crate::Reg::read) this register and get [`sysctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SysctlSpec;
impl crate::RegisterSpec for SysctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`sysctl::R`](R) reader structure"]
impl crate::Readable for SysctlSpec {}
#[doc = "`write(|w| ..)` method takes [`sysctl::W`](W) writer structure"]
impl crate::Writable for SysctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SYSCTL to value 0"]
impl crate::Resettable for SysctlSpec {}
}
#[doc = "SYSJMBC (rw) register accessor: JTAG mailbox control\n\nYou can [`read`](crate::Reg::read) this register and get [`sysjmbc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysjmbc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysjmbc`] module"]
#[doc(alias = "SYSJMBC")]
pub type Sysjmbc = crate::Reg<sysjmbc::SysjmbcSpec>;
#[doc = "JTAG mailbox control"]
pub mod sysjmbc {
#[doc = "Register `SYSJMBC` reader"]
pub type R = crate::R<SysjmbcSpec>;
#[doc = "Register `SYSJMBC` writer"]
pub type W = crate::W<SysjmbcSpec>;
#[doc = "Field `JMBIN0FG` reader - SYS - Incoming JTAG Mailbox 0 Flag"]
pub type Jmbin0fgR = crate::BitReader;
#[doc = "Field `JMBIN0FG` writer - SYS - Incoming JTAG Mailbox 0 Flag"]
pub type Jmbin0fgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `JMBIN1FG` reader - SYS - Incoming JTAG Mailbox 1 Flag"]
pub type Jmbin1fgR = crate::BitReader;
#[doc = "Field `JMBIN1FG` writer - SYS - Incoming JTAG Mailbox 1 Flag"]
pub type Jmbin1fgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `JMBOUT0FG` reader - SYS - Outgoing JTAG Mailbox 0 Flag"]
pub type Jmbout0fgR = crate::BitReader;
#[doc = "Field `JMBOUT0FG` writer - SYS - Outgoing JTAG Mailbox 0 Flag"]
pub type Jmbout0fgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `JMBOUT1FG` reader - SYS - Outgoing JTAG Mailbox 1 Flag"]
pub type Jmbout1fgR = crate::BitReader;
#[doc = "Field `JMBOUT1FG` writer - SYS - Outgoing JTAG Mailbox 1 Flag"]
pub type Jmbout1fgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `JMBMODE` reader - SYS - JMB 16/32 Bit Mode"]
pub type JmbmodeR = crate::BitReader;
#[doc = "Field `JMBMODE` writer - SYS - JMB 16/32 Bit Mode"]
pub type JmbmodeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `JMBCLR0OFF` reader - SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe"]
pub type Jmbclr0offR = crate::BitReader;
#[doc = "Field `JMBCLR0OFF` writer - SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe"]
pub type Jmbclr0offW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `JMBCLR1OFF` reader - SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe"]
pub type Jmbclr1offR = crate::BitReader;
#[doc = "Field `JMBCLR1OFF` writer - SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe"]
pub type Jmbclr1offW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - SYS - Incoming JTAG Mailbox 0 Flag"]
#[inline(always)]
pub fn jmbin0fg(&self) -> Jmbin0fgR {
Jmbin0fgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - SYS - Incoming JTAG Mailbox 1 Flag"]
#[inline(always)]
pub fn jmbin1fg(&self) -> Jmbin1fgR {
Jmbin1fgR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - SYS - Outgoing JTAG Mailbox 0 Flag"]
#[inline(always)]
pub fn jmbout0fg(&self) -> Jmbout0fgR {
Jmbout0fgR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - SYS - Outgoing JTAG Mailbox 1 Flag"]
#[inline(always)]
pub fn jmbout1fg(&self) -> Jmbout1fgR {
Jmbout1fgR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - SYS - JMB 16/32 Bit Mode"]
#[inline(always)]
pub fn jmbmode(&self) -> JmbmodeR {
JmbmodeR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe"]
#[inline(always)]
pub fn jmbclr0off(&self) -> Jmbclr0offR {
Jmbclr0offR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe"]
#[inline(always)]
pub fn jmbclr1off(&self) -> Jmbclr1offR {
Jmbclr1offR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - SYS - Incoming JTAG Mailbox 0 Flag"]
#[inline(always)]
pub fn jmbin0fg(&mut self) -> Jmbin0fgW<'_, SysjmbcSpec> {
Jmbin0fgW::new(self, 0)
}
#[doc = "Bit 1 - SYS - Incoming JTAG Mailbox 1 Flag"]
#[inline(always)]
pub fn jmbin1fg(&mut self) -> Jmbin1fgW<'_, SysjmbcSpec> {
Jmbin1fgW::new(self, 1)
}
#[doc = "Bit 2 - SYS - Outgoing JTAG Mailbox 0 Flag"]
#[inline(always)]
pub fn jmbout0fg(&mut self) -> Jmbout0fgW<'_, SysjmbcSpec> {
Jmbout0fgW::new(self, 2)
}
#[doc = "Bit 3 - SYS - Outgoing JTAG Mailbox 1 Flag"]
#[inline(always)]
pub fn jmbout1fg(&mut self) -> Jmbout1fgW<'_, SysjmbcSpec> {
Jmbout1fgW::new(self, 3)
}
#[doc = "Bit 4 - SYS - JMB 16/32 Bit Mode"]
#[inline(always)]
pub fn jmbmode(&mut self) -> JmbmodeW<'_, SysjmbcSpec> {
JmbmodeW::new(self, 4)
}
#[doc = "Bit 6 - SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe"]
#[inline(always)]
pub fn jmbclr0off(&mut self) -> Jmbclr0offW<'_, SysjmbcSpec> {
Jmbclr0offW::new(self, 6)
}
#[doc = "Bit 7 - SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe"]
#[inline(always)]
pub fn jmbclr1off(&mut self) -> Jmbclr1offW<'_, SysjmbcSpec> {
Jmbclr1offW::new(self, 7)
}
}
#[doc = "JTAG mailbox control\n\nYou can [`read`](crate::Reg::read) this register and get [`sysjmbc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysjmbc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SysjmbcSpec;
impl crate::RegisterSpec for SysjmbcSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`sysjmbc::R`](R) reader structure"]
impl crate::Readable for SysjmbcSpec {}
#[doc = "`write(|w| ..)` method takes [`sysjmbc::W`](W) writer structure"]
impl crate::Writable for SysjmbcSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SYSJMBC to value 0"]
impl crate::Resettable for SysjmbcSpec {}
}
#[doc = "SYSJMBI0 (rw) register accessor: JTAG mailbox input 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sysjmbi0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysjmbi0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysjmbi0`] module"]
#[doc(alias = "SYSJMBI0")]
pub type Sysjmbi0 = crate::Reg<sysjmbi0::Sysjmbi0Spec>;
#[doc = "JTAG mailbox input 0"]
pub mod sysjmbi0 {
#[doc = "Register `SYSJMBI0` reader"]
pub type R = crate::R<Sysjmbi0Spec>;
#[doc = "Register `SYSJMBI0` writer"]
pub type W = crate::W<Sysjmbi0Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "JTAG mailbox input 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sysjmbi0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysjmbi0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sysjmbi0Spec;
impl crate::RegisterSpec for Sysjmbi0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`sysjmbi0::R`](R) reader structure"]
impl crate::Readable for Sysjmbi0Spec {}
#[doc = "`write(|w| ..)` method takes [`sysjmbi0::W`](W) writer structure"]
impl crate::Writable for Sysjmbi0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SYSJMBI0 to value 0"]
impl crate::Resettable for Sysjmbi0Spec {}
}
#[doc = "SYSJMBI1 (rw) register accessor: JTAG mailbox input 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sysjmbi1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysjmbi1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysjmbi1`] module"]
#[doc(alias = "SYSJMBI1")]
pub type Sysjmbi1 = crate::Reg<sysjmbi1::Sysjmbi1Spec>;
#[doc = "JTAG mailbox input 1"]
pub mod sysjmbi1 {
#[doc = "Register `SYSJMBI1` reader"]
pub type R = crate::R<Sysjmbi1Spec>;
#[doc = "Register `SYSJMBI1` writer"]
pub type W = crate::W<Sysjmbi1Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "JTAG mailbox input 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sysjmbi1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysjmbi1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sysjmbi1Spec;
impl crate::RegisterSpec for Sysjmbi1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`sysjmbi1::R`](R) reader structure"]
impl crate::Readable for Sysjmbi1Spec {}
#[doc = "`write(|w| ..)` method takes [`sysjmbi1::W`](W) writer structure"]
impl crate::Writable for Sysjmbi1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SYSJMBI1 to value 0"]
impl crate::Resettable for Sysjmbi1Spec {}
}
#[doc = "SYSJMBO0 (rw) register accessor: JTAG mailbox output 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sysjmbo0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysjmbo0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysjmbo0`] module"]
#[doc(alias = "SYSJMBO0")]
pub type Sysjmbo0 = crate::Reg<sysjmbo0::Sysjmbo0Spec>;
#[doc = "JTAG mailbox output 0"]
pub mod sysjmbo0 {
#[doc = "Register `SYSJMBO0` reader"]
pub type R = crate::R<Sysjmbo0Spec>;
#[doc = "Register `SYSJMBO0` writer"]
pub type W = crate::W<Sysjmbo0Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "JTAG mailbox output 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sysjmbo0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysjmbo0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sysjmbo0Spec;
impl crate::RegisterSpec for Sysjmbo0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`sysjmbo0::R`](R) reader structure"]
impl crate::Readable for Sysjmbo0Spec {}
#[doc = "`write(|w| ..)` method takes [`sysjmbo0::W`](W) writer structure"]
impl crate::Writable for Sysjmbo0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SYSJMBO0 to value 0"]
impl crate::Resettable for Sysjmbo0Spec {}
}
#[doc = "SYSJMBO1 (rw) register accessor: JTAG mailbox output 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sysjmbo1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysjmbo1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysjmbo1`] module"]
#[doc(alias = "SYSJMBO1")]
pub type Sysjmbo1 = crate::Reg<sysjmbo1::Sysjmbo1Spec>;
#[doc = "JTAG mailbox output 1"]
pub mod sysjmbo1 {
#[doc = "Register `SYSJMBO1` reader"]
pub type R = crate::R<Sysjmbo1Spec>;
#[doc = "Register `SYSJMBO1` writer"]
pub type W = crate::W<Sysjmbo1Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "JTAG mailbox output 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sysjmbo1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysjmbo1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Sysjmbo1Spec;
impl crate::RegisterSpec for Sysjmbo1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`sysjmbo1::R`](R) reader structure"]
impl crate::Readable for Sysjmbo1Spec {}
#[doc = "`write(|w| ..)` method takes [`sysjmbo1::W`](W) writer structure"]
impl crate::Writable for Sysjmbo1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SYSJMBO1 to value 0"]
impl crate::Resettable for Sysjmbo1Spec {}
}
#[doc = "SYSUNIV (rw) register accessor: User NMI vector generator\n\nYou can [`read`](crate::Reg::read) this register and get [`sysuniv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysuniv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysuniv`] module"]
#[doc(alias = "SYSUNIV")]
pub type Sysuniv = crate::Reg<sysuniv::SysunivSpec>;
#[doc = "User NMI vector generator"]
pub mod sysuniv {
#[doc = "Register `SYSUNIV` reader"]
pub type R = crate::R<SysunivSpec>;
#[doc = "Register `SYSUNIV` writer"]
pub type W = crate::W<SysunivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "User NMI vector generator\n\nYou can [`read`](crate::Reg::read) this register and get [`sysuniv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysuniv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SysunivSpec;
impl crate::RegisterSpec for SysunivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`sysuniv::R`](R) reader structure"]
impl crate::Readable for SysunivSpec {}
#[doc = "`write(|w| ..)` method takes [`sysuniv::W`](W) writer structure"]
impl crate::Writable for SysunivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SYSUNIV to value 0"]
impl crate::Resettable for SysunivSpec {}
}
#[doc = "SYSSNIV (rw) register accessor: System NMI vector generator\n\nYou can [`read`](crate::Reg::read) this register and get [`syssniv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syssniv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syssniv`] module"]
#[doc(alias = "SYSSNIV")]
pub type Syssniv = crate::Reg<syssniv::SyssnivSpec>;
#[doc = "System NMI vector generator"]
pub mod syssniv {
#[doc = "Register `SYSSNIV` reader"]
pub type R = crate::R<SyssnivSpec>;
#[doc = "Register `SYSSNIV` writer"]
pub type W = crate::W<SyssnivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "System NMI vector generator\n\nYou can [`read`](crate::Reg::read) this register and get [`syssniv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syssniv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SyssnivSpec;
impl crate::RegisterSpec for SyssnivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`syssniv::R`](R) reader structure"]
impl crate::Readable for SyssnivSpec {}
#[doc = "`write(|w| ..)` method takes [`syssniv::W`](W) writer structure"]
impl crate::Writable for SyssnivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SYSSNIV to value 0"]
impl crate::Resettable for SyssnivSpec {}
}
#[doc = "SYSRSTIV (rw) register accessor: Reset vector generator\n\nYou can [`read`](crate::Reg::read) this register and get [`sysrstiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysrstiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysrstiv`] module"]
#[doc(alias = "SYSRSTIV")]
pub type Sysrstiv = crate::Reg<sysrstiv::SysrstivSpec>;
#[doc = "Reset vector generator"]
pub mod sysrstiv {
#[doc = "Register `SYSRSTIV` reader"]
pub type R = crate::R<SysrstivSpec>;
#[doc = "Register `SYSRSTIV` writer"]
pub type W = crate::W<SysrstivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Reset vector generator\n\nYou can [`read`](crate::Reg::read) this register and get [`sysrstiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysrstiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SysrstivSpec;
impl crate::RegisterSpec for SysrstivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`sysrstiv::R`](R) reader structure"]
impl crate::Readable for SysrstivSpec {}
#[doc = "`write(|w| ..)` method takes [`sysrstiv::W`](W) writer structure"]
impl crate::Writable for SysrstivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SYSRSTIV to value 0"]
impl crate::Resettable for SysrstivSpec {}
}
}
#[doc = "Shared Reference"]
pub type SharedReference = crate::Periph<shared_reference::RegisterBlock, 0x01b0>;
impl core::fmt::Debug for SharedReference {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SharedReference").finish()
}
}
#[doc = "Shared Reference"]
pub mod shared_reference {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
refctl0: Refctl0,
}
impl RegisterBlock {
#[doc = "0x00 - REF Shared Reference control register 0"]
#[inline(always)]
pub const fn refctl0(&self) -> &Refctl0 {
&self.refctl0
}
}
#[doc = "REFCTL0 (rw) register accessor: REF Shared Reference control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`refctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@refctl0`] module"]
#[doc(alias = "REFCTL0")]
pub type Refctl0 = crate::Reg<refctl0::Refctl0Spec>;
#[doc = "REF Shared Reference control register 0"]
pub mod refctl0 {
#[doc = "Register `REFCTL0` reader"]
pub type R = crate::R<Refctl0Spec>;
#[doc = "Register `REFCTL0` writer"]
pub type W = crate::W<Refctl0Spec>;
#[doc = "Field `REFON` reader - REF Reference On"]
pub type RefonR = crate::BitReader;
#[doc = "Field `REFON` writer - REF Reference On"]
pub type RefonW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `REFOUT` reader - REF Reference output Buffer On"]
pub type RefoutR = crate::BitReader;
#[doc = "Field `REFOUT` writer - REF Reference output Buffer On"]
pub type RefoutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `REFTCOFF` reader - REF Temp.Sensor off"]
pub type ReftcoffR = crate::BitReader;
#[doc = "Field `REFTCOFF` writer - REF Temp.Sensor off"]
pub type ReftcoffW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "REF Reference Voltage Level Select Bit:0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Refvsel {
#[doc = "0: REF Reference Voltage Level Select 1.2V"]
Refvsel0 = 0,
#[doc = "1: REF Reference Voltage Level Select 2.0V"]
Refvsel1 = 1,
#[doc = "2: REF Reference Voltage Level Select 2.5V"]
Refvsel2 = 2,
#[doc = "3: REF Reference Voltage Level Select 2.5V"]
Refvsel3 = 3,
}
impl From<Refvsel> for u8 {
#[inline(always)]
fn from(variant: Refvsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Refvsel {
type Ux = u8;
}
impl crate::IsEnum for Refvsel {}
#[doc = "Field `REFVSEL` reader - REF Reference Voltage Level Select Bit:0"]
pub type RefvselR = crate::FieldReader<Refvsel>;
impl RefvselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Refvsel {
match self.bits {
0 => Refvsel::Refvsel0,
1 => Refvsel::Refvsel1,
2 => Refvsel::Refvsel2,
3 => Refvsel::Refvsel3,
_ => unreachable!(),
}
}
#[doc = "REF Reference Voltage Level Select 1.2V"]
#[inline(always)]
pub fn is_refvsel_0(&self) -> bool {
*self == Refvsel::Refvsel0
}
#[doc = "REF Reference Voltage Level Select 2.0V"]
#[inline(always)]
pub fn is_refvsel_1(&self) -> bool {
*self == Refvsel::Refvsel1
}
#[doc = "REF Reference Voltage Level Select 2.5V"]
#[inline(always)]
pub fn is_refvsel_2(&self) -> bool {
*self == Refvsel::Refvsel2
}
#[doc = "REF Reference Voltage Level Select 2.5V"]
#[inline(always)]
pub fn is_refvsel_3(&self) -> bool {
*self == Refvsel::Refvsel3
}
}
#[doc = "Field `REFVSEL` writer - REF Reference Voltage Level Select Bit:0"]
pub type RefvselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Refvsel, crate::Safe>;
impl<'a, REG> RefvselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "REF Reference Voltage Level Select 1.2V"]
#[inline(always)]
pub fn refvsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Refvsel::Refvsel0)
}
#[doc = "REF Reference Voltage Level Select 2.0V"]
#[inline(always)]
pub fn refvsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Refvsel::Refvsel1)
}
#[doc = "REF Reference Voltage Level Select 2.5V"]
#[inline(always)]
pub fn refvsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Refvsel::Refvsel2)
}
#[doc = "REF Reference Voltage Level Select 2.5V"]
#[inline(always)]
pub fn refvsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Refvsel::Refvsel3)
}
}
#[doc = "Field `REFGENOT` reader - REF Reference generator one-time trigger"]
pub type RefgenotR = crate::BitReader;
#[doc = "Field `REFGENOT` writer - REF Reference generator one-time trigger"]
pub type RefgenotW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `REFBGOT` reader - REF Bandgap and bandgap buffer one-time trigger"]
pub type RefbgotR = crate::BitReader;
#[doc = "Field `REFBGOT` writer - REF Bandgap and bandgap buffer one-time trigger"]
pub type RefbgotW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `REFGENACT` reader - REF Reference generator active"]
pub type RefgenactR = crate::BitReader;
#[doc = "Field `REFGENACT` writer - REF Reference generator active"]
pub type RefgenactW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `REFBGACT` reader - REF Reference bandgap active"]
pub type RefbgactR = crate::BitReader;
#[doc = "Field `REFBGACT` writer - REF Reference bandgap active"]
pub type RefbgactW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `REFGENBUSY` reader - REF Reference generator busy"]
pub type RefgenbusyR = crate::BitReader;
#[doc = "Field `REFGENBUSY` writer - REF Reference generator busy"]
pub type RefgenbusyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BGMODE` reader - REF Bandgap mode"]
pub type BgmodeR = crate::BitReader;
#[doc = "Field `BGMODE` writer - REF Bandgap mode"]
pub type BgmodeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `REFGENRDY` reader - REF Reference generator ready"]
pub type RefgenrdyR = crate::BitReader;
#[doc = "Field `REFGENRDY` writer - REF Reference generator ready"]
pub type RefgenrdyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `REFBGRDY` reader - REF Reference bandgap ready"]
pub type RefbgrdyR = crate::BitReader;
#[doc = "Field `REFBGRDY` writer - REF Reference bandgap ready"]
pub type RefbgrdyW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - REF Reference On"]
#[inline(always)]
pub fn refon(&self) -> RefonR {
RefonR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - REF Reference output Buffer On"]
#[inline(always)]
pub fn refout(&self) -> RefoutR {
RefoutR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 3 - REF Temp.Sensor off"]
#[inline(always)]
pub fn reftcoff(&self) -> ReftcoffR {
ReftcoffR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:5 - REF Reference Voltage Level Select Bit:0"]
#[inline(always)]
pub fn refvsel(&self) -> RefvselR {
RefvselR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bit 6 - REF Reference generator one-time trigger"]
#[inline(always)]
pub fn refgenot(&self) -> RefgenotR {
RefgenotR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - REF Bandgap and bandgap buffer one-time trigger"]
#[inline(always)]
pub fn refbgot(&self) -> RefbgotR {
RefbgotR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - REF Reference generator active"]
#[inline(always)]
pub fn refgenact(&self) -> RefgenactR {
RefgenactR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - REF Reference bandgap active"]
#[inline(always)]
pub fn refbgact(&self) -> RefbgactR {
RefbgactR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - REF Reference generator busy"]
#[inline(always)]
pub fn refgenbusy(&self) -> RefgenbusyR {
RefgenbusyR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - REF Bandgap mode"]
#[inline(always)]
pub fn bgmode(&self) -> BgmodeR {
BgmodeR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - REF Reference generator ready"]
#[inline(always)]
pub fn refgenrdy(&self) -> RefgenrdyR {
RefgenrdyR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - REF Reference bandgap ready"]
#[inline(always)]
pub fn refbgrdy(&self) -> RefbgrdyR {
RefbgrdyR::new(((self.bits >> 13) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - REF Reference On"]
#[inline(always)]
pub fn refon(&mut self) -> RefonW<'_, Refctl0Spec> {
RefonW::new(self, 0)
}
#[doc = "Bit 1 - REF Reference output Buffer On"]
#[inline(always)]
pub fn refout(&mut self) -> RefoutW<'_, Refctl0Spec> {
RefoutW::new(self, 1)
}
#[doc = "Bit 3 - REF Temp.Sensor off"]
#[inline(always)]
pub fn reftcoff(&mut self) -> ReftcoffW<'_, Refctl0Spec> {
ReftcoffW::new(self, 3)
}
#[doc = "Bits 4:5 - REF Reference Voltage Level Select Bit:0"]
#[inline(always)]
pub fn refvsel(&mut self) -> RefvselW<'_, Refctl0Spec> {
RefvselW::new(self, 4)
}
#[doc = "Bit 6 - REF Reference generator one-time trigger"]
#[inline(always)]
pub fn refgenot(&mut self) -> RefgenotW<'_, Refctl0Spec> {
RefgenotW::new(self, 6)
}
#[doc = "Bit 7 - REF Bandgap and bandgap buffer one-time trigger"]
#[inline(always)]
pub fn refbgot(&mut self) -> RefbgotW<'_, Refctl0Spec> {
RefbgotW::new(self, 7)
}
#[doc = "Bit 8 - REF Reference generator active"]
#[inline(always)]
pub fn refgenact(&mut self) -> RefgenactW<'_, Refctl0Spec> {
RefgenactW::new(self, 8)
}
#[doc = "Bit 9 - REF Reference bandgap active"]
#[inline(always)]
pub fn refbgact(&mut self) -> RefbgactW<'_, Refctl0Spec> {
RefbgactW::new(self, 9)
}
#[doc = "Bit 10 - REF Reference generator busy"]
#[inline(always)]
pub fn refgenbusy(&mut self) -> RefgenbusyW<'_, Refctl0Spec> {
RefgenbusyW::new(self, 10)
}
#[doc = "Bit 11 - REF Bandgap mode"]
#[inline(always)]
pub fn bgmode(&mut self) -> BgmodeW<'_, Refctl0Spec> {
BgmodeW::new(self, 11)
}
#[doc = "Bit 12 - REF Reference generator ready"]
#[inline(always)]
pub fn refgenrdy(&mut self) -> RefgenrdyW<'_, Refctl0Spec> {
RefgenrdyW::new(self, 12)
}
#[doc = "Bit 13 - REF Reference bandgap ready"]
#[inline(always)]
pub fn refbgrdy(&mut self) -> RefbgrdyW<'_, Refctl0Spec> {
RefbgrdyW::new(self, 13)
}
}
#[doc = "REF Shared Reference control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`refctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Refctl0Spec;
impl crate::RegisterSpec for Refctl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`refctl0::R`](R) reader structure"]
impl crate::Readable for Refctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`refctl0::W`](W) writer structure"]
impl crate::Writable for Refctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets REFCTL0 to value 0"]
impl crate::Resettable for Refctl0Spec {}
}
}
#[doc = "Port J"]
pub type PortJ = crate::Periph<port_j::RegisterBlock, 0x0320>;
impl core::fmt::Debug for PortJ {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PortJ").finish()
}
}
#[doc = "Port J"]
pub mod port_j {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
pjin: Pjin,
pjout: Pjout,
pjdir: Pjdir,
pjren: Pjren,
_reserved4: [u8; 0x02],
pjsel0: Pjsel0,
pjsel1: Pjsel1,
_reserved6: [u8; 0x08],
pjselc: Pjselc,
}
impl RegisterBlock {
#[doc = "0x00 - Port J Input"]
#[inline(always)]
pub const fn pjin(&self) -> &Pjin {
&self.pjin
}
#[doc = "0x02 - Port J Output"]
#[inline(always)]
pub const fn pjout(&self) -> &Pjout {
&self.pjout
}
#[doc = "0x04 - Port J Direction"]
#[inline(always)]
pub const fn pjdir(&self) -> &Pjdir {
&self.pjdir
}
#[doc = "0x06 - Port J Resistor Enable"]
#[inline(always)]
pub const fn pjren(&self) -> &Pjren {
&self.pjren
}
#[doc = "0x0a - Port J Selection 0"]
#[inline(always)]
pub const fn pjsel0(&self) -> &Pjsel0 {
&self.pjsel0
}
#[doc = "0x0c - Port J Selection 1"]
#[inline(always)]
pub const fn pjsel1(&self) -> &Pjsel1 {
&self.pjsel1
}
#[doc = "0x16 - Port J Complement Selection"]
#[inline(always)]
pub const fn pjselc(&self) -> &Pjselc {
&self.pjselc
}
}
#[doc = "PJIN (rw) register accessor: Port J Input\n\nYou can [`read`](crate::Reg::read) this register and get [`pjin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pjin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pjin`] module"]
#[doc(alias = "PJIN")]
pub type Pjin = crate::Reg<pjin::PjinSpec>;
#[doc = "Port J Input"]
pub mod pjin {
#[doc = "Register `PJIN` reader"]
pub type R = crate::R<PjinSpec>;
#[doc = "Register `PJIN` writer"]
pub type W = crate::W<PjinSpec>;
#[doc = "Field `PJIN0` reader - PJIN0"]
pub type Pjin0R = crate::BitReader;
#[doc = "Field `PJIN0` writer - PJIN0"]
pub type Pjin0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJIN1` reader - PJIN1"]
pub type Pjin1R = crate::BitReader;
#[doc = "Field `PJIN1` writer - PJIN1"]
pub type Pjin1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJIN2` reader - PJIN2"]
pub type Pjin2R = crate::BitReader;
#[doc = "Field `PJIN2` writer - PJIN2"]
pub type Pjin2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJIN3` reader - PJIN3"]
pub type Pjin3R = crate::BitReader;
#[doc = "Field `PJIN3` writer - PJIN3"]
pub type Pjin3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJIN4` reader - PJIN4"]
pub type Pjin4R = crate::BitReader;
#[doc = "Field `PJIN4` writer - PJIN4"]
pub type Pjin4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJIN5` reader - PJIN5"]
pub type Pjin5R = crate::BitReader;
#[doc = "Field `PJIN5` writer - PJIN5"]
pub type Pjin5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJIN6` reader - PJIN6"]
pub type Pjin6R = crate::BitReader;
#[doc = "Field `PJIN6` writer - PJIN6"]
pub type Pjin6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJIN7` reader - PJIN7"]
pub type Pjin7R = crate::BitReader;
#[doc = "Field `PJIN7` writer - PJIN7"]
pub type Pjin7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - PJIN0"]
#[inline(always)]
pub fn pjin0(&self) -> Pjin0R {
Pjin0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - PJIN1"]
#[inline(always)]
pub fn pjin1(&self) -> Pjin1R {
Pjin1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PJIN2"]
#[inline(always)]
pub fn pjin2(&self) -> Pjin2R {
Pjin2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - PJIN3"]
#[inline(always)]
pub fn pjin3(&self) -> Pjin3R {
Pjin3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - PJIN4"]
#[inline(always)]
pub fn pjin4(&self) -> Pjin4R {
Pjin4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - PJIN5"]
#[inline(always)]
pub fn pjin5(&self) -> Pjin5R {
Pjin5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - PJIN6"]
#[inline(always)]
pub fn pjin6(&self) -> Pjin6R {
Pjin6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - PJIN7"]
#[inline(always)]
pub fn pjin7(&self) -> Pjin7R {
Pjin7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - PJIN0"]
#[inline(always)]
pub fn pjin0(&mut self) -> Pjin0W<'_, PjinSpec> {
Pjin0W::new(self, 0)
}
#[doc = "Bit 1 - PJIN1"]
#[inline(always)]
pub fn pjin1(&mut self) -> Pjin1W<'_, PjinSpec> {
Pjin1W::new(self, 1)
}
#[doc = "Bit 2 - PJIN2"]
#[inline(always)]
pub fn pjin2(&mut self) -> Pjin2W<'_, PjinSpec> {
Pjin2W::new(self, 2)
}
#[doc = "Bit 3 - PJIN3"]
#[inline(always)]
pub fn pjin3(&mut self) -> Pjin3W<'_, PjinSpec> {
Pjin3W::new(self, 3)
}
#[doc = "Bit 4 - PJIN4"]
#[inline(always)]
pub fn pjin4(&mut self) -> Pjin4W<'_, PjinSpec> {
Pjin4W::new(self, 4)
}
#[doc = "Bit 5 - PJIN5"]
#[inline(always)]
pub fn pjin5(&mut self) -> Pjin5W<'_, PjinSpec> {
Pjin5W::new(self, 5)
}
#[doc = "Bit 6 - PJIN6"]
#[inline(always)]
pub fn pjin6(&mut self) -> Pjin6W<'_, PjinSpec> {
Pjin6W::new(self, 6)
}
#[doc = "Bit 7 - PJIN7"]
#[inline(always)]
pub fn pjin7(&mut self) -> Pjin7W<'_, PjinSpec> {
Pjin7W::new(self, 7)
}
}
#[doc = "Port J Input\n\nYou can [`read`](crate::Reg::read) this register and get [`pjin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pjin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PjinSpec;
impl crate::RegisterSpec for PjinSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`pjin::R`](R) reader structure"]
impl crate::Readable for PjinSpec {}
#[doc = "`write(|w| ..)` method takes [`pjin::W`](W) writer structure"]
impl crate::Writable for PjinSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PJIN to value 0"]
impl crate::Resettable for PjinSpec {}
}
#[doc = "PJOUT (rw) register accessor: Port J Output\n\nYou can [`read`](crate::Reg::read) this register and get [`pjout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pjout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pjout`] module"]
#[doc(alias = "PJOUT")]
pub type Pjout = crate::Reg<pjout::PjoutSpec>;
#[doc = "Port J Output"]
pub mod pjout {
#[doc = "Register `PJOUT` reader"]
pub type R = crate::R<PjoutSpec>;
#[doc = "Register `PJOUT` writer"]
pub type W = crate::W<PjoutSpec>;
#[doc = "Field `PJOUT0` reader - PJOUT0"]
pub type Pjout0R = crate::BitReader;
#[doc = "Field `PJOUT0` writer - PJOUT0"]
pub type Pjout0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJOUT1` reader - PJOUT1"]
pub type Pjout1R = crate::BitReader;
#[doc = "Field `PJOUT1` writer - PJOUT1"]
pub type Pjout1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJOUT2` reader - PJOUT2"]
pub type Pjout2R = crate::BitReader;
#[doc = "Field `PJOUT2` writer - PJOUT2"]
pub type Pjout2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJOUT3` reader - PJOUT3"]
pub type Pjout3R = crate::BitReader;
#[doc = "Field `PJOUT3` writer - PJOUT3"]
pub type Pjout3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJOUT4` reader - PJOUT4"]
pub type Pjout4R = crate::BitReader;
#[doc = "Field `PJOUT4` writer - PJOUT4"]
pub type Pjout4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJOUT5` reader - PJOUT5"]
pub type Pjout5R = crate::BitReader;
#[doc = "Field `PJOUT5` writer - PJOUT5"]
pub type Pjout5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJOUT6` reader - PJOUT6"]
pub type Pjout6R = crate::BitReader;
#[doc = "Field `PJOUT6` writer - PJOUT6"]
pub type Pjout6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJOUT7` reader - PJOUT7"]
pub type Pjout7R = crate::BitReader;
#[doc = "Field `PJOUT7` writer - PJOUT7"]
pub type Pjout7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - PJOUT0"]
#[inline(always)]
pub fn pjout0(&self) -> Pjout0R {
Pjout0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - PJOUT1"]
#[inline(always)]
pub fn pjout1(&self) -> Pjout1R {
Pjout1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PJOUT2"]
#[inline(always)]
pub fn pjout2(&self) -> Pjout2R {
Pjout2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - PJOUT3"]
#[inline(always)]
pub fn pjout3(&self) -> Pjout3R {
Pjout3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - PJOUT4"]
#[inline(always)]
pub fn pjout4(&self) -> Pjout4R {
Pjout4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - PJOUT5"]
#[inline(always)]
pub fn pjout5(&self) -> Pjout5R {
Pjout5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - PJOUT6"]
#[inline(always)]
pub fn pjout6(&self) -> Pjout6R {
Pjout6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - PJOUT7"]
#[inline(always)]
pub fn pjout7(&self) -> Pjout7R {
Pjout7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - PJOUT0"]
#[inline(always)]
pub fn pjout0(&mut self) -> Pjout0W<'_, PjoutSpec> {
Pjout0W::new(self, 0)
}
#[doc = "Bit 1 - PJOUT1"]
#[inline(always)]
pub fn pjout1(&mut self) -> Pjout1W<'_, PjoutSpec> {
Pjout1W::new(self, 1)
}
#[doc = "Bit 2 - PJOUT2"]
#[inline(always)]
pub fn pjout2(&mut self) -> Pjout2W<'_, PjoutSpec> {
Pjout2W::new(self, 2)
}
#[doc = "Bit 3 - PJOUT3"]
#[inline(always)]
pub fn pjout3(&mut self) -> Pjout3W<'_, PjoutSpec> {
Pjout3W::new(self, 3)
}
#[doc = "Bit 4 - PJOUT4"]
#[inline(always)]
pub fn pjout4(&mut self) -> Pjout4W<'_, PjoutSpec> {
Pjout4W::new(self, 4)
}
#[doc = "Bit 5 - PJOUT5"]
#[inline(always)]
pub fn pjout5(&mut self) -> Pjout5W<'_, PjoutSpec> {
Pjout5W::new(self, 5)
}
#[doc = "Bit 6 - PJOUT6"]
#[inline(always)]
pub fn pjout6(&mut self) -> Pjout6W<'_, PjoutSpec> {
Pjout6W::new(self, 6)
}
#[doc = "Bit 7 - PJOUT7"]
#[inline(always)]
pub fn pjout7(&mut self) -> Pjout7W<'_, PjoutSpec> {
Pjout7W::new(self, 7)
}
}
#[doc = "Port J Output\n\nYou can [`read`](crate::Reg::read) this register and get [`pjout::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pjout::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PjoutSpec;
impl crate::RegisterSpec for PjoutSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`pjout::R`](R) reader structure"]
impl crate::Readable for PjoutSpec {}
#[doc = "`write(|w| ..)` method takes [`pjout::W`](W) writer structure"]
impl crate::Writable for PjoutSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PJOUT to value 0"]
impl crate::Resettable for PjoutSpec {}
}
#[doc = "PJDIR (rw) register accessor: Port J Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`pjdir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pjdir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pjdir`] module"]
#[doc(alias = "PJDIR")]
pub type Pjdir = crate::Reg<pjdir::PjdirSpec>;
#[doc = "Port J Direction"]
pub mod pjdir {
#[doc = "Register `PJDIR` reader"]
pub type R = crate::R<PjdirSpec>;
#[doc = "Register `PJDIR` writer"]
pub type W = crate::W<PjdirSpec>;
#[doc = "Field `PJDIR0` reader - PJDIR0"]
pub type Pjdir0R = crate::BitReader;
#[doc = "Field `PJDIR0` writer - PJDIR0"]
pub type Pjdir0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJDIR1` reader - PJDIR1"]
pub type Pjdir1R = crate::BitReader;
#[doc = "Field `PJDIR1` writer - PJDIR1"]
pub type Pjdir1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJDIR2` reader - PJDIR2"]
pub type Pjdir2R = crate::BitReader;
#[doc = "Field `PJDIR2` writer - PJDIR2"]
pub type Pjdir2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJDIR3` reader - PJDIR3"]
pub type Pjdir3R = crate::BitReader;
#[doc = "Field `PJDIR3` writer - PJDIR3"]
pub type Pjdir3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJDIR4` reader - PJDIR4"]
pub type Pjdir4R = crate::BitReader;
#[doc = "Field `PJDIR4` writer - PJDIR4"]
pub type Pjdir4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJDIR5` reader - PJDIR5"]
pub type Pjdir5R = crate::BitReader;
#[doc = "Field `PJDIR5` writer - PJDIR5"]
pub type Pjdir5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJDIR6` reader - PJDIR6"]
pub type Pjdir6R = crate::BitReader;
#[doc = "Field `PJDIR6` writer - PJDIR6"]
pub type Pjdir6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJDIR7` reader - PJDIR7"]
pub type Pjdir7R = crate::BitReader;
#[doc = "Field `PJDIR7` writer - PJDIR7"]
pub type Pjdir7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - PJDIR0"]
#[inline(always)]
pub fn pjdir0(&self) -> Pjdir0R {
Pjdir0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - PJDIR1"]
#[inline(always)]
pub fn pjdir1(&self) -> Pjdir1R {
Pjdir1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PJDIR2"]
#[inline(always)]
pub fn pjdir2(&self) -> Pjdir2R {
Pjdir2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - PJDIR3"]
#[inline(always)]
pub fn pjdir3(&self) -> Pjdir3R {
Pjdir3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - PJDIR4"]
#[inline(always)]
pub fn pjdir4(&self) -> Pjdir4R {
Pjdir4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - PJDIR5"]
#[inline(always)]
pub fn pjdir5(&self) -> Pjdir5R {
Pjdir5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - PJDIR6"]
#[inline(always)]
pub fn pjdir6(&self) -> Pjdir6R {
Pjdir6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - PJDIR7"]
#[inline(always)]
pub fn pjdir7(&self) -> Pjdir7R {
Pjdir7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - PJDIR0"]
#[inline(always)]
pub fn pjdir0(&mut self) -> Pjdir0W<'_, PjdirSpec> {
Pjdir0W::new(self, 0)
}
#[doc = "Bit 1 - PJDIR1"]
#[inline(always)]
pub fn pjdir1(&mut self) -> Pjdir1W<'_, PjdirSpec> {
Pjdir1W::new(self, 1)
}
#[doc = "Bit 2 - PJDIR2"]
#[inline(always)]
pub fn pjdir2(&mut self) -> Pjdir2W<'_, PjdirSpec> {
Pjdir2W::new(self, 2)
}
#[doc = "Bit 3 - PJDIR3"]
#[inline(always)]
pub fn pjdir3(&mut self) -> Pjdir3W<'_, PjdirSpec> {
Pjdir3W::new(self, 3)
}
#[doc = "Bit 4 - PJDIR4"]
#[inline(always)]
pub fn pjdir4(&mut self) -> Pjdir4W<'_, PjdirSpec> {
Pjdir4W::new(self, 4)
}
#[doc = "Bit 5 - PJDIR5"]
#[inline(always)]
pub fn pjdir5(&mut self) -> Pjdir5W<'_, PjdirSpec> {
Pjdir5W::new(self, 5)
}
#[doc = "Bit 6 - PJDIR6"]
#[inline(always)]
pub fn pjdir6(&mut self) -> Pjdir6W<'_, PjdirSpec> {
Pjdir6W::new(self, 6)
}
#[doc = "Bit 7 - PJDIR7"]
#[inline(always)]
pub fn pjdir7(&mut self) -> Pjdir7W<'_, PjdirSpec> {
Pjdir7W::new(self, 7)
}
}
#[doc = "Port J Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`pjdir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pjdir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PjdirSpec;
impl crate::RegisterSpec for PjdirSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`pjdir::R`](R) reader structure"]
impl crate::Readable for PjdirSpec {}
#[doc = "`write(|w| ..)` method takes [`pjdir::W`](W) writer structure"]
impl crate::Writable for PjdirSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PJDIR to value 0"]
impl crate::Resettable for PjdirSpec {}
}
#[doc = "PJREN (rw) register accessor: Port J Resistor Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pjren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pjren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pjren`] module"]
#[doc(alias = "PJREN")]
pub type Pjren = crate::Reg<pjren::PjrenSpec>;
#[doc = "Port J Resistor Enable"]
pub mod pjren {
#[doc = "Register `PJREN` reader"]
pub type R = crate::R<PjrenSpec>;
#[doc = "Register `PJREN` writer"]
pub type W = crate::W<PjrenSpec>;
#[doc = "Field `PJREN0` reader - PJREN0"]
pub type Pjren0R = crate::BitReader;
#[doc = "Field `PJREN0` writer - PJREN0"]
pub type Pjren0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJREN1` reader - PJREN1"]
pub type Pjren1R = crate::BitReader;
#[doc = "Field `PJREN1` writer - PJREN1"]
pub type Pjren1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJREN2` reader - PJREN2"]
pub type Pjren2R = crate::BitReader;
#[doc = "Field `PJREN2` writer - PJREN2"]
pub type Pjren2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJREN3` reader - PJREN3"]
pub type Pjren3R = crate::BitReader;
#[doc = "Field `PJREN3` writer - PJREN3"]
pub type Pjren3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJREN4` reader - PJREN4"]
pub type Pjren4R = crate::BitReader;
#[doc = "Field `PJREN4` writer - PJREN4"]
pub type Pjren4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJREN5` reader - PJREN5"]
pub type Pjren5R = crate::BitReader;
#[doc = "Field `PJREN5` writer - PJREN5"]
pub type Pjren5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJREN6` reader - PJREN6"]
pub type Pjren6R = crate::BitReader;
#[doc = "Field `PJREN6` writer - PJREN6"]
pub type Pjren6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJREN7` reader - PJREN7"]
pub type Pjren7R = crate::BitReader;
#[doc = "Field `PJREN7` writer - PJREN7"]
pub type Pjren7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - PJREN0"]
#[inline(always)]
pub fn pjren0(&self) -> Pjren0R {
Pjren0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - PJREN1"]
#[inline(always)]
pub fn pjren1(&self) -> Pjren1R {
Pjren1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PJREN2"]
#[inline(always)]
pub fn pjren2(&self) -> Pjren2R {
Pjren2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - PJREN3"]
#[inline(always)]
pub fn pjren3(&self) -> Pjren3R {
Pjren3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - PJREN4"]
#[inline(always)]
pub fn pjren4(&self) -> Pjren4R {
Pjren4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - PJREN5"]
#[inline(always)]
pub fn pjren5(&self) -> Pjren5R {
Pjren5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - PJREN6"]
#[inline(always)]
pub fn pjren6(&self) -> Pjren6R {
Pjren6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - PJREN7"]
#[inline(always)]
pub fn pjren7(&self) -> Pjren7R {
Pjren7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - PJREN0"]
#[inline(always)]
pub fn pjren0(&mut self) -> Pjren0W<'_, PjrenSpec> {
Pjren0W::new(self, 0)
}
#[doc = "Bit 1 - PJREN1"]
#[inline(always)]
pub fn pjren1(&mut self) -> Pjren1W<'_, PjrenSpec> {
Pjren1W::new(self, 1)
}
#[doc = "Bit 2 - PJREN2"]
#[inline(always)]
pub fn pjren2(&mut self) -> Pjren2W<'_, PjrenSpec> {
Pjren2W::new(self, 2)
}
#[doc = "Bit 3 - PJREN3"]
#[inline(always)]
pub fn pjren3(&mut self) -> Pjren3W<'_, PjrenSpec> {
Pjren3W::new(self, 3)
}
#[doc = "Bit 4 - PJREN4"]
#[inline(always)]
pub fn pjren4(&mut self) -> Pjren4W<'_, PjrenSpec> {
Pjren4W::new(self, 4)
}
#[doc = "Bit 5 - PJREN5"]
#[inline(always)]
pub fn pjren5(&mut self) -> Pjren5W<'_, PjrenSpec> {
Pjren5W::new(self, 5)
}
#[doc = "Bit 6 - PJREN6"]
#[inline(always)]
pub fn pjren6(&mut self) -> Pjren6W<'_, PjrenSpec> {
Pjren6W::new(self, 6)
}
#[doc = "Bit 7 - PJREN7"]
#[inline(always)]
pub fn pjren7(&mut self) -> Pjren7W<'_, PjrenSpec> {
Pjren7W::new(self, 7)
}
}
#[doc = "Port J Resistor Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`pjren::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pjren::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PjrenSpec;
impl crate::RegisterSpec for PjrenSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`pjren::R`](R) reader structure"]
impl crate::Readable for PjrenSpec {}
#[doc = "`write(|w| ..)` method takes [`pjren::W`](W) writer structure"]
impl crate::Writable for PjrenSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PJREN to value 0"]
impl crate::Resettable for PjrenSpec {}
}
#[doc = "PJSEL0 (rw) register accessor: Port J Selection 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pjsel0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pjsel0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pjsel0`] module"]
#[doc(alias = "PJSEL0")]
pub type Pjsel0 = crate::Reg<pjsel0::Pjsel0Spec>;
#[doc = "Port J Selection 0"]
pub mod pjsel0 {
#[doc = "Register `PJSEL0` reader"]
pub type R = crate::R<Pjsel0Spec>;
#[doc = "Register `PJSEL0` writer"]
pub type W = crate::W<Pjsel0Spec>;
#[doc = "Field `PJSEL0_0` reader - PJSEL0_0"]
pub type Pjsel0_0R = crate::BitReader;
#[doc = "Field `PJSEL0_0` writer - PJSEL0_0"]
pub type Pjsel0_0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJSEL0_1` reader - PJSEL0_1"]
pub type Pjsel0_1R = crate::BitReader;
#[doc = "Field `PJSEL0_1` writer - PJSEL0_1"]
pub type Pjsel0_1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJSEL0_2` reader - PJSEL0_2"]
pub type Pjsel0_2R = crate::BitReader;
#[doc = "Field `PJSEL0_2` writer - PJSEL0_2"]
pub type Pjsel0_2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJSEL0_3` reader - PJSEL0_3"]
pub type Pjsel0_3R = crate::BitReader;
#[doc = "Field `PJSEL0_3` writer - PJSEL0_3"]
pub type Pjsel0_3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJSEL0_4` reader - PJSEL0_4"]
pub type Pjsel0_4R = crate::BitReader;
#[doc = "Field `PJSEL0_4` writer - PJSEL0_4"]
pub type Pjsel0_4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJSEL0_5` reader - PJSEL0_5"]
pub type Pjsel0_5R = crate::BitReader;
#[doc = "Field `PJSEL0_5` writer - PJSEL0_5"]
pub type Pjsel0_5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJSEL0_6` reader - PJSEL0_6"]
pub type Pjsel0_6R = crate::BitReader;
#[doc = "Field `PJSEL0_6` writer - PJSEL0_6"]
pub type Pjsel0_6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJSEL0_7` reader - PJSEL0_7"]
pub type Pjsel0_7R = crate::BitReader;
#[doc = "Field `PJSEL0_7` writer - PJSEL0_7"]
pub type Pjsel0_7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - PJSEL0_0"]
#[inline(always)]
pub fn pjsel0_0(&self) -> Pjsel0_0R {
Pjsel0_0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - PJSEL0_1"]
#[inline(always)]
pub fn pjsel0_1(&self) -> Pjsel0_1R {
Pjsel0_1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PJSEL0_2"]
#[inline(always)]
pub fn pjsel0_2(&self) -> Pjsel0_2R {
Pjsel0_2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - PJSEL0_3"]
#[inline(always)]
pub fn pjsel0_3(&self) -> Pjsel0_3R {
Pjsel0_3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - PJSEL0_4"]
#[inline(always)]
pub fn pjsel0_4(&self) -> Pjsel0_4R {
Pjsel0_4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - PJSEL0_5"]
#[inline(always)]
pub fn pjsel0_5(&self) -> Pjsel0_5R {
Pjsel0_5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - PJSEL0_6"]
#[inline(always)]
pub fn pjsel0_6(&self) -> Pjsel0_6R {
Pjsel0_6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - PJSEL0_7"]
#[inline(always)]
pub fn pjsel0_7(&self) -> Pjsel0_7R {
Pjsel0_7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - PJSEL0_0"]
#[inline(always)]
pub fn pjsel0_0(&mut self) -> Pjsel0_0W<'_, Pjsel0Spec> {
Pjsel0_0W::new(self, 0)
}
#[doc = "Bit 1 - PJSEL0_1"]
#[inline(always)]
pub fn pjsel0_1(&mut self) -> Pjsel0_1W<'_, Pjsel0Spec> {
Pjsel0_1W::new(self, 1)
}
#[doc = "Bit 2 - PJSEL0_2"]
#[inline(always)]
pub fn pjsel0_2(&mut self) -> Pjsel0_2W<'_, Pjsel0Spec> {
Pjsel0_2W::new(self, 2)
}
#[doc = "Bit 3 - PJSEL0_3"]
#[inline(always)]
pub fn pjsel0_3(&mut self) -> Pjsel0_3W<'_, Pjsel0Spec> {
Pjsel0_3W::new(self, 3)
}
#[doc = "Bit 4 - PJSEL0_4"]
#[inline(always)]
pub fn pjsel0_4(&mut self) -> Pjsel0_4W<'_, Pjsel0Spec> {
Pjsel0_4W::new(self, 4)
}
#[doc = "Bit 5 - PJSEL0_5"]
#[inline(always)]
pub fn pjsel0_5(&mut self) -> Pjsel0_5W<'_, Pjsel0Spec> {
Pjsel0_5W::new(self, 5)
}
#[doc = "Bit 6 - PJSEL0_6"]
#[inline(always)]
pub fn pjsel0_6(&mut self) -> Pjsel0_6W<'_, Pjsel0Spec> {
Pjsel0_6W::new(self, 6)
}
#[doc = "Bit 7 - PJSEL0_7"]
#[inline(always)]
pub fn pjsel0_7(&mut self) -> Pjsel0_7W<'_, Pjsel0Spec> {
Pjsel0_7W::new(self, 7)
}
}
#[doc = "Port J Selection 0\n\nYou can [`read`](crate::Reg::read) this register and get [`pjsel0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pjsel0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pjsel0Spec;
impl crate::RegisterSpec for Pjsel0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`pjsel0::R`](R) reader structure"]
impl crate::Readable for Pjsel0Spec {}
#[doc = "`write(|w| ..)` method takes [`pjsel0::W`](W) writer structure"]
impl crate::Writable for Pjsel0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PJSEL0 to value 0"]
impl crate::Resettable for Pjsel0Spec {}
}
#[doc = "PJSEL1 (rw) register accessor: Port J Selection 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pjsel1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pjsel1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pjsel1`] module"]
#[doc(alias = "PJSEL1")]
pub type Pjsel1 = crate::Reg<pjsel1::Pjsel1Spec>;
#[doc = "Port J Selection 1"]
pub mod pjsel1 {
#[doc = "Register `PJSEL1` reader"]
pub type R = crate::R<Pjsel1Spec>;
#[doc = "Register `PJSEL1` writer"]
pub type W = crate::W<Pjsel1Spec>;
#[doc = "Field `PJSEL1_0` reader - PJSEL1_0"]
pub type Pjsel1_0R = crate::BitReader;
#[doc = "Field `PJSEL1_0` writer - PJSEL1_0"]
pub type Pjsel1_0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJSEL1_1` reader - PJSEL1_1"]
pub type Pjsel1_1R = crate::BitReader;
#[doc = "Field `PJSEL1_1` writer - PJSEL1_1"]
pub type Pjsel1_1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJSEL1_2` reader - PJSEL1_2"]
pub type Pjsel1_2R = crate::BitReader;
#[doc = "Field `PJSEL1_2` writer - PJSEL1_2"]
pub type Pjsel1_2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJSEL1_3` reader - PJSEL1_3"]
pub type Pjsel1_3R = crate::BitReader;
#[doc = "Field `PJSEL1_3` writer - PJSEL1_3"]
pub type Pjsel1_3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJSEL1_4` reader - PJSEL1_4"]
pub type Pjsel1_4R = crate::BitReader;
#[doc = "Field `PJSEL1_4` writer - PJSEL1_4"]
pub type Pjsel1_4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJSEL1_5` reader - PJSEL1_5"]
pub type Pjsel1_5R = crate::BitReader;
#[doc = "Field `PJSEL1_5` writer - PJSEL1_5"]
pub type Pjsel1_5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJSEL1_6` reader - PJSEL1_6"]
pub type Pjsel1_6R = crate::BitReader;
#[doc = "Field `PJSEL1_6` writer - PJSEL1_6"]
pub type Pjsel1_6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PJSEL1_7` reader - PJSEL1_7"]
pub type Pjsel1_7R = crate::BitReader;
#[doc = "Field `PJSEL1_7` writer - PJSEL1_7"]
pub type Pjsel1_7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - PJSEL1_0"]
#[inline(always)]
pub fn pjsel1_0(&self) -> Pjsel1_0R {
Pjsel1_0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - PJSEL1_1"]
#[inline(always)]
pub fn pjsel1_1(&self) -> Pjsel1_1R {
Pjsel1_1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PJSEL1_2"]
#[inline(always)]
pub fn pjsel1_2(&self) -> Pjsel1_2R {
Pjsel1_2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - PJSEL1_3"]
#[inline(always)]
pub fn pjsel1_3(&self) -> Pjsel1_3R {
Pjsel1_3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - PJSEL1_4"]
#[inline(always)]
pub fn pjsel1_4(&self) -> Pjsel1_4R {
Pjsel1_4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - PJSEL1_5"]
#[inline(always)]
pub fn pjsel1_5(&self) -> Pjsel1_5R {
Pjsel1_5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - PJSEL1_6"]
#[inline(always)]
pub fn pjsel1_6(&self) -> Pjsel1_6R {
Pjsel1_6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - PJSEL1_7"]
#[inline(always)]
pub fn pjsel1_7(&self) -> Pjsel1_7R {
Pjsel1_7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - PJSEL1_0"]
#[inline(always)]
pub fn pjsel1_0(&mut self) -> Pjsel1_0W<'_, Pjsel1Spec> {
Pjsel1_0W::new(self, 0)
}
#[doc = "Bit 1 - PJSEL1_1"]
#[inline(always)]
pub fn pjsel1_1(&mut self) -> Pjsel1_1W<'_, Pjsel1Spec> {
Pjsel1_1W::new(self, 1)
}
#[doc = "Bit 2 - PJSEL1_2"]
#[inline(always)]
pub fn pjsel1_2(&mut self) -> Pjsel1_2W<'_, Pjsel1Spec> {
Pjsel1_2W::new(self, 2)
}
#[doc = "Bit 3 - PJSEL1_3"]
#[inline(always)]
pub fn pjsel1_3(&mut self) -> Pjsel1_3W<'_, Pjsel1Spec> {
Pjsel1_3W::new(self, 3)
}
#[doc = "Bit 4 - PJSEL1_4"]
#[inline(always)]
pub fn pjsel1_4(&mut self) -> Pjsel1_4W<'_, Pjsel1Spec> {
Pjsel1_4W::new(self, 4)
}
#[doc = "Bit 5 - PJSEL1_5"]
#[inline(always)]
pub fn pjsel1_5(&mut self) -> Pjsel1_5W<'_, Pjsel1Spec> {
Pjsel1_5W::new(self, 5)
}
#[doc = "Bit 6 - PJSEL1_6"]
#[inline(always)]
pub fn pjsel1_6(&mut self) -> Pjsel1_6W<'_, Pjsel1Spec> {
Pjsel1_6W::new(self, 6)
}
#[doc = "Bit 7 - PJSEL1_7"]
#[inline(always)]
pub fn pjsel1_7(&mut self) -> Pjsel1_7W<'_, Pjsel1Spec> {
Pjsel1_7W::new(self, 7)
}
}
#[doc = "Port J Selection 1\n\nYou can [`read`](crate::Reg::read) this register and get [`pjsel1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pjsel1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pjsel1Spec;
impl crate::RegisterSpec for Pjsel1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`pjsel1::R`](R) reader structure"]
impl crate::Readable for Pjsel1Spec {}
#[doc = "`write(|w| ..)` method takes [`pjsel1::W`](W) writer structure"]
impl crate::Writable for Pjsel1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PJSEL1 to value 0"]
impl crate::Resettable for Pjsel1Spec {}
}
#[doc = "PJSELC (rw) register accessor: Port J Complement Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`pjselc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pjselc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pjselc`] module"]
#[doc(alias = "PJSELC")]
pub type Pjselc = crate::Reg<pjselc::PjselcSpec>;
#[doc = "Port J Complement Selection"]
pub mod pjselc {
#[doc = "Register `PJSELC` reader"]
pub type R = crate::R<PjselcSpec>;
#[doc = "Register `PJSELC` writer"]
pub type W = crate::W<PjselcSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Port J Complement Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`pjselc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pjselc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PjselcSpec;
impl crate::RegisterSpec for PjselcSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`pjselc::R`](R) reader structure"]
impl crate::Readable for PjselcSpec {}
#[doc = "`write(|w| ..)` method takes [`pjselc::W`](W) writer structure"]
impl crate::Writable for PjselcSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PJSELC to value 0"]
impl crate::Resettable for PjselcSpec {}
}
}
#[doc = "Timer0_A3"]
pub type Timer0A3 = crate::Periph<timer_0_a3::RegisterBlock, 0x0340>;
impl core::fmt::Debug for Timer0A3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Timer0A3").finish()
}
}
#[doc = "Timer0_A3"]
pub mod timer_0_a3 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
ta0ctl: Ta0ctl,
ta0cctl0: Ta0cctl0,
ta0cctl1: Ta0cctl1,
ta0cctl2: Ta0cctl2,
_reserved4: [u8; 0x08],
ta0r: Ta0r,
ta0ccr0: Ta0ccr0,
ta0ccr1: Ta0ccr1,
ta0ccr2: Ta0ccr2,
_reserved8: [u8; 0x08],
ta0ex0: Ta0ex0,
_reserved9: [u8; 0x0c],
ta0iv: Ta0iv,
}
impl RegisterBlock {
#[doc = "0x00 - Timer0_A3 Control"]
#[inline(always)]
pub const fn ta0ctl(&self) -> &Ta0ctl {
&self.ta0ctl
}
#[doc = "0x02 - Timer0_A3 Capture/Compare Control 0"]
#[inline(always)]
pub const fn ta0cctl0(&self) -> &Ta0cctl0 {
&self.ta0cctl0
}
#[doc = "0x04 - Timer0_A3 Capture/Compare Control 1"]
#[inline(always)]
pub const fn ta0cctl1(&self) -> &Ta0cctl1 {
&self.ta0cctl1
}
#[doc = "0x06 - Timer0_A3 Capture/Compare Control 2"]
#[inline(always)]
pub const fn ta0cctl2(&self) -> &Ta0cctl2 {
&self.ta0cctl2
}
#[doc = "0x10 - Timer0_A3"]
#[inline(always)]
pub const fn ta0r(&self) -> &Ta0r {
&self.ta0r
}
#[doc = "0x12 - Timer0_A3 Capture/Compare 0"]
#[inline(always)]
pub const fn ta0ccr0(&self) -> &Ta0ccr0 {
&self.ta0ccr0
}
#[doc = "0x14 - Timer0_A3 Capture/Compare 1"]
#[inline(always)]
pub const fn ta0ccr1(&self) -> &Ta0ccr1 {
&self.ta0ccr1
}
#[doc = "0x16 - Timer0_A3 Capture/Compare 2"]
#[inline(always)]
pub const fn ta0ccr2(&self) -> &Ta0ccr2 {
&self.ta0ccr2
}
#[doc = "0x20 - Timer0_A3 Expansion Register 0"]
#[inline(always)]
pub const fn ta0ex0(&self) -> &Ta0ex0 {
&self.ta0ex0
}
#[doc = "0x2e - Timer0_A3 Interrupt Vector Word"]
#[inline(always)]
pub const fn ta0iv(&self) -> &Ta0iv {
&self.ta0iv
}
}
#[doc = "TA0CTL (rw) register accessor: Timer0_A3 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta0ctl`] module"]
#[doc(alias = "TA0CTL")]
pub type Ta0ctl = crate::Reg<ta0ctl::Ta0ctlSpec>;
#[doc = "Timer0_A3 Control"]
pub mod ta0ctl {
#[doc = "Register `TA0CTL` reader"]
pub type R = crate::R<Ta0ctlSpec>;
#[doc = "Register `TA0CTL` writer"]
pub type W = crate::W<Ta0ctlSpec>;
#[doc = "Field `TAIFG` reader - Timer A counter interrupt flag"]
pub type TaifgR = crate::BitReader;
#[doc = "Field `TAIFG` writer - Timer A counter interrupt flag"]
pub type TaifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TAIE` reader - Timer A counter interrupt enable"]
pub type TaieR = crate::BitReader;
#[doc = "Field `TAIE` writer - Timer A counter interrupt enable"]
pub type TaieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TACLR` reader - Timer A counter clear"]
pub type TaclrR = crate::BitReader;
#[doc = "Field `TACLR` writer - Timer A counter clear"]
pub type TaclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Timer A mode control 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mc {
#[doc = "0: Timer A mode control: 0 - Stop"]
Mc0 = 0,
#[doc = "1: Timer A mode control: 1 - Up to CCR0"]
Mc1 = 1,
#[doc = "2: Timer A mode control: 2 - Continuous up"]
Mc2 = 2,
#[doc = "3: Timer A mode control: 3 - Up/Down"]
Mc3 = 3,
}
impl From<Mc> for u8 {
#[inline(always)]
fn from(variant: Mc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mc {
type Ux = u8;
}
impl crate::IsEnum for Mc {}
#[doc = "Field `MC` reader - Timer A mode control 1"]
pub type McR = crate::FieldReader<Mc>;
impl McR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mc {
match self.bits {
0 => Mc::Mc0,
1 => Mc::Mc1,
2 => Mc::Mc2,
3 => Mc::Mc3,
_ => unreachable!(),
}
}
#[doc = "Timer A mode control: 0 - Stop"]
#[inline(always)]
pub fn is_mc_0(&self) -> bool {
*self == Mc::Mc0
}
#[doc = "Timer A mode control: 1 - Up to CCR0"]
#[inline(always)]
pub fn is_mc_1(&self) -> bool {
*self == Mc::Mc1
}
#[doc = "Timer A mode control: 2 - Continuous up"]
#[inline(always)]
pub fn is_mc_2(&self) -> bool {
*self == Mc::Mc2
}
#[doc = "Timer A mode control: 3 - Up/Down"]
#[inline(always)]
pub fn is_mc_3(&self) -> bool {
*self == Mc::Mc3
}
}
#[doc = "Field `MC` writer - Timer A mode control 1"]
pub type McW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mc, crate::Safe>;
impl<'a, REG> McW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A mode control: 0 - Stop"]
#[inline(always)]
pub fn mc_0(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc0)
}
#[doc = "Timer A mode control: 1 - Up to CCR0"]
#[inline(always)]
pub fn mc_1(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc1)
}
#[doc = "Timer A mode control: 2 - Continuous up"]
#[inline(always)]
pub fn mc_2(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc2)
}
#[doc = "Timer A mode control: 3 - Up/Down"]
#[inline(always)]
pub fn mc_3(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc3)
}
}
#[doc = "Timer A clock input divider 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Id {
#[doc = "0: Timer A input divider: 0 - /1"]
Id0 = 0,
#[doc = "1: Timer A input divider: 1 - /2"]
Id1 = 1,
#[doc = "2: Timer A input divider: 2 - /4"]
Id2 = 2,
#[doc = "3: Timer A input divider: 3 - /8"]
Id3 = 3,
}
impl From<Id> for u8 {
#[inline(always)]
fn from(variant: Id) -> Self {
variant as _
}
}
impl crate::FieldSpec for Id {
type Ux = u8;
}
impl crate::IsEnum for Id {}
#[doc = "Field `ID` reader - Timer A clock input divider 1"]
pub type IdR = crate::FieldReader<Id>;
impl IdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Id {
match self.bits {
0 => Id::Id0,
1 => Id::Id1,
2 => Id::Id2,
3 => Id::Id3,
_ => unreachable!(),
}
}
#[doc = "Timer A input divider: 0 - /1"]
#[inline(always)]
pub fn is_id_0(&self) -> bool {
*self == Id::Id0
}
#[doc = "Timer A input divider: 1 - /2"]
#[inline(always)]
pub fn is_id_1(&self) -> bool {
*self == Id::Id1
}
#[doc = "Timer A input divider: 2 - /4"]
#[inline(always)]
pub fn is_id_2(&self) -> bool {
*self == Id::Id2
}
#[doc = "Timer A input divider: 3 - /8"]
#[inline(always)]
pub fn is_id_3(&self) -> bool {
*self == Id::Id3
}
}
#[doc = "Field `ID` writer - Timer A clock input divider 1"]
pub type IdW<'a, REG> = crate::FieldWriter<'a, REG, 2, Id, crate::Safe>;
impl<'a, REG> IdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A input divider: 0 - /1"]
#[inline(always)]
pub fn id_0(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id0)
}
#[doc = "Timer A input divider: 1 - /2"]
#[inline(always)]
pub fn id_1(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id1)
}
#[doc = "Timer A input divider: 2 - /4"]
#[inline(always)]
pub fn id_2(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id2)
}
#[doc = "Timer A input divider: 3 - /8"]
#[inline(always)]
pub fn id_3(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id3)
}
}
#[doc = "Timer A clock source select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Tassel {
#[doc = "0: Timer A clock source select: 0 - TACLK"]
Tassel0 = 0,
#[doc = "1: Timer A clock source select: 1 - ACLK"]
Tassel1 = 1,
#[doc = "2: Timer A clock source select: 2 - SMCLK"]
Tassel2 = 2,
#[doc = "3: Timer A clock source select: 3 - INCLK"]
Tassel3 = 3,
}
impl From<Tassel> for u8 {
#[inline(always)]
fn from(variant: Tassel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Tassel {
type Ux = u8;
}
impl crate::IsEnum for Tassel {}
#[doc = "Field `TASSEL` reader - Timer A clock source select 1"]
pub type TasselR = crate::FieldReader<Tassel>;
impl TasselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Tassel {
match self.bits {
0 => Tassel::Tassel0,
1 => Tassel::Tassel1,
2 => Tassel::Tassel2,
3 => Tassel::Tassel3,
_ => unreachable!(),
}
}
#[doc = "Timer A clock source select: 0 - TACLK"]
#[inline(always)]
pub fn is_tassel_0(&self) -> bool {
*self == Tassel::Tassel0
}
#[doc = "Timer A clock source select: 1 - ACLK"]
#[inline(always)]
pub fn is_tassel_1(&self) -> bool {
*self == Tassel::Tassel1
}
#[doc = "Timer A clock source select: 2 - SMCLK"]
#[inline(always)]
pub fn is_tassel_2(&self) -> bool {
*self == Tassel::Tassel2
}
#[doc = "Timer A clock source select: 3 - INCLK"]
#[inline(always)]
pub fn is_tassel_3(&self) -> bool {
*self == Tassel::Tassel3
}
}
#[doc = "Field `TASSEL` writer - Timer A clock source select 1"]
pub type TasselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tassel, crate::Safe>;
impl<'a, REG> TasselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A clock source select: 0 - TACLK"]
#[inline(always)]
pub fn tassel_0(self) -> &'a mut crate::W<REG> {
self.variant(Tassel::Tassel0)
}
#[doc = "Timer A clock source select: 1 - ACLK"]
#[inline(always)]
pub fn tassel_1(self) -> &'a mut crate::W<REG> {
self.variant(Tassel::Tassel1)
}
#[doc = "Timer A clock source select: 2 - SMCLK"]
#[inline(always)]
pub fn tassel_2(self) -> &'a mut crate::W<REG> {
self.variant(Tassel::Tassel2)
}
#[doc = "Timer A clock source select: 3 - INCLK"]
#[inline(always)]
pub fn tassel_3(self) -> &'a mut crate::W<REG> {
self.variant(Tassel::Tassel3)
}
}
impl R {
#[doc = "Bit 0 - Timer A counter interrupt flag"]
#[inline(always)]
pub fn taifg(&self) -> TaifgR {
TaifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Timer A counter interrupt enable"]
#[inline(always)]
pub fn taie(&self) -> TaieR {
TaieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Timer A counter clear"]
#[inline(always)]
pub fn taclr(&self) -> TaclrR {
TaclrR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 4:5 - Timer A mode control 1"]
#[inline(always)]
pub fn mc(&self) -> McR {
McR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:7 - Timer A clock input divider 1"]
#[inline(always)]
pub fn id(&self) -> IdR {
IdR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:9 - Timer A clock source select 1"]
#[inline(always)]
pub fn tassel(&self) -> TasselR {
TasselR::new(((self.bits >> 8) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Timer A counter interrupt flag"]
#[inline(always)]
pub fn taifg(&mut self) -> TaifgW<'_, Ta0ctlSpec> {
TaifgW::new(self, 0)
}
#[doc = "Bit 1 - Timer A counter interrupt enable"]
#[inline(always)]
pub fn taie(&mut self) -> TaieW<'_, Ta0ctlSpec> {
TaieW::new(self, 1)
}
#[doc = "Bit 2 - Timer A counter clear"]
#[inline(always)]
pub fn taclr(&mut self) -> TaclrW<'_, Ta0ctlSpec> {
TaclrW::new(self, 2)
}
#[doc = "Bits 4:5 - Timer A mode control 1"]
#[inline(always)]
pub fn mc(&mut self) -> McW<'_, Ta0ctlSpec> {
McW::new(self, 4)
}
#[doc = "Bits 6:7 - Timer A clock input divider 1"]
#[inline(always)]
pub fn id(&mut self) -> IdW<'_, Ta0ctlSpec> {
IdW::new(self, 6)
}
#[doc = "Bits 8:9 - Timer A clock source select 1"]
#[inline(always)]
pub fn tassel(&mut self) -> TasselW<'_, Ta0ctlSpec> {
TasselW::new(self, 8)
}
}
#[doc = "Timer0_A3 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta0ctlSpec;
impl crate::RegisterSpec for Ta0ctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta0ctl::R`](R) reader structure"]
impl crate::Readable for Ta0ctlSpec {}
#[doc = "`write(|w| ..)` method takes [`ta0ctl::W`](W) writer structure"]
impl crate::Writable for Ta0ctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA0CTL to value 0"]
impl crate::Resettable for Ta0ctlSpec {}
}
#[doc = "TA0CCTL0 (rw) register accessor: Timer0_A3 Capture/Compare Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0cctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0cctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta0cctl0`] module"]
#[doc(alias = "TA0CCTL0")]
pub type Ta0cctl0 = crate::Reg<ta0cctl0::Ta0cctl0Spec>;
#[doc = "Timer0_A3 Capture/Compare Control 0"]
pub mod ta0cctl0 {
#[doc = "Register `TA0CCTL0` reader"]
pub type R = crate::R<Ta0cctl0Spec>;
#[doc = "Register `TA0CCTL0` writer"]
pub type W = crate::W<Ta0cctl0Spec>;
#[doc = "Field `CCIFG` reader - Capture/compare interrupt flag"]
pub type CcifgR = crate::BitReader;
#[doc = "Field `CCIFG` writer - Capture/compare interrupt flag"]
pub type CcifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COV` reader - Capture/compare overflow flag"]
pub type CovR = crate::BitReader;
#[doc = "Field `COV` writer - Capture/compare overflow flag"]
pub type CovW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OUT` reader - PWM Output signal if output mode 0"]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - PWM Output signal if output mode 0"]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCI` reader - Capture input signal (read)"]
pub type CciR = crate::BitReader;
#[doc = "Field `CCI` writer - Capture input signal (read)"]
pub type CciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCIE` reader - Capture/compare interrupt enable"]
pub type CcieR = crate::BitReader;
#[doc = "Field `CCIE` writer - Capture/compare interrupt enable"]
pub type CcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output mode 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Outmod {
#[doc = "0: PWM output mode: 0 - output only"]
Outmod0 = 0,
#[doc = "1: PWM output mode: 1 - set"]
Outmod1 = 1,
#[doc = "2: PWM output mode: 2 - PWM toggle/reset"]
Outmod2 = 2,
#[doc = "3: PWM output mode: 3 - PWM set/reset"]
Outmod3 = 3,
#[doc = "4: PWM output mode: 4 - toggle"]
Outmod4 = 4,
#[doc = "5: PWM output mode: 5 - Reset"]
Outmod5 = 5,
#[doc = "6: PWM output mode: 6 - PWM toggle/set"]
Outmod6 = 6,
#[doc = "7: PWM output mode: 7 - PWM reset/set"]
Outmod7 = 7,
}
impl From<Outmod> for u8 {
#[inline(always)]
fn from(variant: Outmod) -> Self {
variant as _
}
}
impl crate::FieldSpec for Outmod {
type Ux = u8;
}
impl crate::IsEnum for Outmod {}
#[doc = "Field `OUTMOD` reader - Output mode 2"]
pub type OutmodR = crate::FieldReader<Outmod>;
impl OutmodR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Outmod {
match self.bits {
0 => Outmod::Outmod0,
1 => Outmod::Outmod1,
2 => Outmod::Outmod2,
3 => Outmod::Outmod3,
4 => Outmod::Outmod4,
5 => Outmod::Outmod5,
6 => Outmod::Outmod6,
7 => Outmod::Outmod7,
_ => unreachable!(),
}
}
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn is_outmod_0(&self) -> bool {
*self == Outmod::Outmod0
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn is_outmod_1(&self) -> bool {
*self == Outmod::Outmod1
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn is_outmod_2(&self) -> bool {
*self == Outmod::Outmod2
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn is_outmod_3(&self) -> bool {
*self == Outmod::Outmod3
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn is_outmod_4(&self) -> bool {
*self == Outmod::Outmod4
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn is_outmod_5(&self) -> bool {
*self == Outmod::Outmod5
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn is_outmod_6(&self) -> bool {
*self == Outmod::Outmod6
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn is_outmod_7(&self) -> bool {
*self == Outmod::Outmod7
}
}
#[doc = "Field `OUTMOD` writer - Output mode 2"]
pub type OutmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Outmod, crate::Safe>;
impl<'a, REG> OutmodW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn outmod_0(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod0)
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn outmod_1(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod1)
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn outmod_2(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod2)
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn outmod_3(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod3)
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn outmod_4(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod4)
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn outmod_5(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod5)
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn outmod_6(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod6)
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn outmod_7(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod7)
}
}
#[doc = "Field `CAP` reader - Capture mode: 1 /Compare mode : 0"]
pub type CapR = crate::BitReader;
#[doc = "Field `CAP` writer - Capture mode: 1 /Compare mode : 0"]
pub type CapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCCI` reader - Latched capture signal (read)"]
pub type ScciR = crate::BitReader;
#[doc = "Field `SCCI` writer - Latched capture signal (read)"]
pub type ScciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCS` reader - Capture sychronize"]
pub type ScsR = crate::BitReader;
#[doc = "Field `SCS` writer - Capture sychronize"]
pub type ScsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture input select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ccis {
#[doc = "0: Capture input select: 0 - CCIxA"]
Ccis0 = 0,
#[doc = "1: Capture input select: 1 - CCIxB"]
Ccis1 = 1,
#[doc = "2: Capture input select: 2 - GND"]
Ccis2 = 2,
#[doc = "3: Capture input select: 3 - Vcc"]
Ccis3 = 3,
}
impl From<Ccis> for u8 {
#[inline(always)]
fn from(variant: Ccis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ccis {
type Ux = u8;
}
impl crate::IsEnum for Ccis {}
#[doc = "Field `CCIS` reader - Capture input select 1"]
pub type CcisR = crate::FieldReader<Ccis>;
impl CcisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccis {
match self.bits {
0 => Ccis::Ccis0,
1 => Ccis::Ccis1,
2 => Ccis::Ccis2,
3 => Ccis::Ccis3,
_ => unreachable!(),
}
}
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn is_ccis_0(&self) -> bool {
*self == Ccis::Ccis0
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn is_ccis_1(&self) -> bool {
*self == Ccis::Ccis1
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn is_ccis_2(&self) -> bool {
*self == Ccis::Ccis2
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn is_ccis_3(&self) -> bool {
*self == Ccis::Ccis3
}
}
#[doc = "Field `CCIS` writer - Capture input select 1"]
pub type CcisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ccis, crate::Safe>;
impl<'a, REG> CcisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn ccis_0(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis0)
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn ccis_1(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis1)
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn ccis_2(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis2)
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn ccis_3(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis3)
}
}
#[doc = "Capture mode 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Capture mode: 0 - disabled"]
Cm0 = 0,
#[doc = "1: Capture mode: 1 - pos. edge"]
Cm1 = 1,
#[doc = "2: Capture mode: 1 - neg. edge"]
Cm2 = 2,
#[doc = "3: Capture mode: 1 - both edges"]
Cm3 = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Capture mode 1"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cm {
match self.bits {
0 => Cm::Cm0,
1 => Cm::Cm1,
2 => Cm::Cm2,
3 => Cm::Cm3,
_ => unreachable!(),
}
}
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn is_cm_0(&self) -> bool {
*self == Cm::Cm0
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn is_cm_1(&self) -> bool {
*self == Cm::Cm1
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn is_cm_2(&self) -> bool {
*self == Cm::Cm2
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn is_cm_3(&self) -> bool {
*self == Cm::Cm3
}
}
#[doc = "Field `CM` writer - Capture mode 1"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm, crate::Safe>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn cm_0(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm0)
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn cm_1(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm1)
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn cm_2(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm2)
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn cm_3(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm3)
}
}
impl R {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&self) -> CcifgR {
CcifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&self) -> CovR {
CovR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&self) -> CciR {
CciR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&self) -> CcieR {
CcieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&self) -> OutmodR {
OutmodR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&self) -> ScciR {
ScciR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&self) -> ScsR {
ScsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&self) -> CcisR {
CcisR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&mut self) -> CcifgW<'_, Ta0cctl0Spec> {
CcifgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&mut self) -> CovW<'_, Ta0cctl0Spec> {
CovW::new(self, 1)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&mut self) -> OutW<'_, Ta0cctl0Spec> {
OutW::new(self, 2)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&mut self) -> CciW<'_, Ta0cctl0Spec> {
CciW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&mut self) -> CcieW<'_, Ta0cctl0Spec> {
CcieW::new(self, 4)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&mut self) -> OutmodW<'_, Ta0cctl0Spec> {
OutmodW::new(self, 5)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&mut self) -> CapW<'_, Ta0cctl0Spec> {
CapW::new(self, 8)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&mut self) -> ScciW<'_, Ta0cctl0Spec> {
ScciW::new(self, 10)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&mut self) -> ScsW<'_, Ta0cctl0Spec> {
ScsW::new(self, 11)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&mut self) -> CcisW<'_, Ta0cctl0Spec> {
CcisW::new(self, 12)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<'_, Ta0cctl0Spec> {
CmW::new(self, 14)
}
}
#[doc = "Timer0_A3 Capture/Compare Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0cctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0cctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta0cctl0Spec;
impl crate::RegisterSpec for Ta0cctl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta0cctl0::R`](R) reader structure"]
impl crate::Readable for Ta0cctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`ta0cctl0::W`](W) writer structure"]
impl crate::Writable for Ta0cctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA0CCTL0 to value 0"]
impl crate::Resettable for Ta0cctl0Spec {}
}
#[doc = "TA0CCTL1 (rw) register accessor: Timer0_A3 Capture/Compare Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0cctl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0cctl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta0cctl1`] module"]
#[doc(alias = "TA0CCTL1")]
pub type Ta0cctl1 = crate::Reg<ta0cctl1::Ta0cctl1Spec>;
#[doc = "Timer0_A3 Capture/Compare Control 1"]
pub mod ta0cctl1 {
#[doc = "Register `TA0CCTL1` reader"]
pub type R = crate::R<Ta0cctl1Spec>;
#[doc = "Register `TA0CCTL1` writer"]
pub type W = crate::W<Ta0cctl1Spec>;
#[doc = "Field `CCIFG` reader - Capture/compare interrupt flag"]
pub type CcifgR = crate::BitReader;
#[doc = "Field `CCIFG` writer - Capture/compare interrupt flag"]
pub type CcifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COV` reader - Capture/compare overflow flag"]
pub type CovR = crate::BitReader;
#[doc = "Field `COV` writer - Capture/compare overflow flag"]
pub type CovW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OUT` reader - PWM Output signal if output mode 0"]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - PWM Output signal if output mode 0"]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCI` reader - Capture input signal (read)"]
pub type CciR = crate::BitReader;
#[doc = "Field `CCI` writer - Capture input signal (read)"]
pub type CciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCIE` reader - Capture/compare interrupt enable"]
pub type CcieR = crate::BitReader;
#[doc = "Field `CCIE` writer - Capture/compare interrupt enable"]
pub type CcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output mode 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Outmod {
#[doc = "0: PWM output mode: 0 - output only"]
Outmod0 = 0,
#[doc = "1: PWM output mode: 1 - set"]
Outmod1 = 1,
#[doc = "2: PWM output mode: 2 - PWM toggle/reset"]
Outmod2 = 2,
#[doc = "3: PWM output mode: 3 - PWM set/reset"]
Outmod3 = 3,
#[doc = "4: PWM output mode: 4 - toggle"]
Outmod4 = 4,
#[doc = "5: PWM output mode: 5 - Reset"]
Outmod5 = 5,
#[doc = "6: PWM output mode: 6 - PWM toggle/set"]
Outmod6 = 6,
#[doc = "7: PWM output mode: 7 - PWM reset/set"]
Outmod7 = 7,
}
impl From<Outmod> for u8 {
#[inline(always)]
fn from(variant: Outmod) -> Self {
variant as _
}
}
impl crate::FieldSpec for Outmod {
type Ux = u8;
}
impl crate::IsEnum for Outmod {}
#[doc = "Field `OUTMOD` reader - Output mode 2"]
pub type OutmodR = crate::FieldReader<Outmod>;
impl OutmodR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Outmod {
match self.bits {
0 => Outmod::Outmod0,
1 => Outmod::Outmod1,
2 => Outmod::Outmod2,
3 => Outmod::Outmod3,
4 => Outmod::Outmod4,
5 => Outmod::Outmod5,
6 => Outmod::Outmod6,
7 => Outmod::Outmod7,
_ => unreachable!(),
}
}
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn is_outmod_0(&self) -> bool {
*self == Outmod::Outmod0
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn is_outmod_1(&self) -> bool {
*self == Outmod::Outmod1
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn is_outmod_2(&self) -> bool {
*self == Outmod::Outmod2
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn is_outmod_3(&self) -> bool {
*self == Outmod::Outmod3
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn is_outmod_4(&self) -> bool {
*self == Outmod::Outmod4
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn is_outmod_5(&self) -> bool {
*self == Outmod::Outmod5
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn is_outmod_6(&self) -> bool {
*self == Outmod::Outmod6
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn is_outmod_7(&self) -> bool {
*self == Outmod::Outmod7
}
}
#[doc = "Field `OUTMOD` writer - Output mode 2"]
pub type OutmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Outmod, crate::Safe>;
impl<'a, REG> OutmodW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn outmod_0(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod0)
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn outmod_1(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod1)
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn outmod_2(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod2)
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn outmod_3(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod3)
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn outmod_4(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod4)
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn outmod_5(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod5)
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn outmod_6(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod6)
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn outmod_7(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod7)
}
}
#[doc = "Field `CAP` reader - Capture mode: 1 /Compare mode : 0"]
pub type CapR = crate::BitReader;
#[doc = "Field `CAP` writer - Capture mode: 1 /Compare mode : 0"]
pub type CapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCCI` reader - Latched capture signal (read)"]
pub type ScciR = crate::BitReader;
#[doc = "Field `SCCI` writer - Latched capture signal (read)"]
pub type ScciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCS` reader - Capture sychronize"]
pub type ScsR = crate::BitReader;
#[doc = "Field `SCS` writer - Capture sychronize"]
pub type ScsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture input select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ccis {
#[doc = "0: Capture input select: 0 - CCIxA"]
Ccis0 = 0,
#[doc = "1: Capture input select: 1 - CCIxB"]
Ccis1 = 1,
#[doc = "2: Capture input select: 2 - GND"]
Ccis2 = 2,
#[doc = "3: Capture input select: 3 - Vcc"]
Ccis3 = 3,
}
impl From<Ccis> for u8 {
#[inline(always)]
fn from(variant: Ccis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ccis {
type Ux = u8;
}
impl crate::IsEnum for Ccis {}
#[doc = "Field `CCIS` reader - Capture input select 1"]
pub type CcisR = crate::FieldReader<Ccis>;
impl CcisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccis {
match self.bits {
0 => Ccis::Ccis0,
1 => Ccis::Ccis1,
2 => Ccis::Ccis2,
3 => Ccis::Ccis3,
_ => unreachable!(),
}
}
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn is_ccis_0(&self) -> bool {
*self == Ccis::Ccis0
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn is_ccis_1(&self) -> bool {
*self == Ccis::Ccis1
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn is_ccis_2(&self) -> bool {
*self == Ccis::Ccis2
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn is_ccis_3(&self) -> bool {
*self == Ccis::Ccis3
}
}
#[doc = "Field `CCIS` writer - Capture input select 1"]
pub type CcisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ccis, crate::Safe>;
impl<'a, REG> CcisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn ccis_0(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis0)
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn ccis_1(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis1)
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn ccis_2(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis2)
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn ccis_3(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis3)
}
}
#[doc = "Capture mode 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Capture mode: 0 - disabled"]
Cm0 = 0,
#[doc = "1: Capture mode: 1 - pos. edge"]
Cm1 = 1,
#[doc = "2: Capture mode: 1 - neg. edge"]
Cm2 = 2,
#[doc = "3: Capture mode: 1 - both edges"]
Cm3 = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Capture mode 1"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cm {
match self.bits {
0 => Cm::Cm0,
1 => Cm::Cm1,
2 => Cm::Cm2,
3 => Cm::Cm3,
_ => unreachable!(),
}
}
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn is_cm_0(&self) -> bool {
*self == Cm::Cm0
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn is_cm_1(&self) -> bool {
*self == Cm::Cm1
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn is_cm_2(&self) -> bool {
*self == Cm::Cm2
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn is_cm_3(&self) -> bool {
*self == Cm::Cm3
}
}
#[doc = "Field `CM` writer - Capture mode 1"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm, crate::Safe>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn cm_0(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm0)
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn cm_1(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm1)
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn cm_2(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm2)
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn cm_3(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm3)
}
}
impl R {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&self) -> CcifgR {
CcifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&self) -> CovR {
CovR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&self) -> CciR {
CciR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&self) -> CcieR {
CcieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&self) -> OutmodR {
OutmodR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&self) -> ScciR {
ScciR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&self) -> ScsR {
ScsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&self) -> CcisR {
CcisR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&mut self) -> CcifgW<'_, Ta0cctl1Spec> {
CcifgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&mut self) -> CovW<'_, Ta0cctl1Spec> {
CovW::new(self, 1)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&mut self) -> OutW<'_, Ta0cctl1Spec> {
OutW::new(self, 2)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&mut self) -> CciW<'_, Ta0cctl1Spec> {
CciW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&mut self) -> CcieW<'_, Ta0cctl1Spec> {
CcieW::new(self, 4)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&mut self) -> OutmodW<'_, Ta0cctl1Spec> {
OutmodW::new(self, 5)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&mut self) -> CapW<'_, Ta0cctl1Spec> {
CapW::new(self, 8)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&mut self) -> ScciW<'_, Ta0cctl1Spec> {
ScciW::new(self, 10)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&mut self) -> ScsW<'_, Ta0cctl1Spec> {
ScsW::new(self, 11)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&mut self) -> CcisW<'_, Ta0cctl1Spec> {
CcisW::new(self, 12)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<'_, Ta0cctl1Spec> {
CmW::new(self, 14)
}
}
#[doc = "Timer0_A3 Capture/Compare Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0cctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0cctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta0cctl1Spec;
impl crate::RegisterSpec for Ta0cctl1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta0cctl1::R`](R) reader structure"]
impl crate::Readable for Ta0cctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`ta0cctl1::W`](W) writer structure"]
impl crate::Writable for Ta0cctl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA0CCTL1 to value 0"]
impl crate::Resettable for Ta0cctl1Spec {}
}
#[doc = "TA0CCTL2 (rw) register accessor: Timer0_A3 Capture/Compare Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0cctl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0cctl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta0cctl2`] module"]
#[doc(alias = "TA0CCTL2")]
pub type Ta0cctl2 = crate::Reg<ta0cctl2::Ta0cctl2Spec>;
#[doc = "Timer0_A3 Capture/Compare Control 2"]
pub mod ta0cctl2 {
#[doc = "Register `TA0CCTL2` reader"]
pub type R = crate::R<Ta0cctl2Spec>;
#[doc = "Register `TA0CCTL2` writer"]
pub type W = crate::W<Ta0cctl2Spec>;
#[doc = "Field `CCIFG` reader - Capture/compare interrupt flag"]
pub type CcifgR = crate::BitReader;
#[doc = "Field `CCIFG` writer - Capture/compare interrupt flag"]
pub type CcifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COV` reader - Capture/compare overflow flag"]
pub type CovR = crate::BitReader;
#[doc = "Field `COV` writer - Capture/compare overflow flag"]
pub type CovW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OUT` reader - PWM Output signal if output mode 0"]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - PWM Output signal if output mode 0"]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCI` reader - Capture input signal (read)"]
pub type CciR = crate::BitReader;
#[doc = "Field `CCI` writer - Capture input signal (read)"]
pub type CciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCIE` reader - Capture/compare interrupt enable"]
pub type CcieR = crate::BitReader;
#[doc = "Field `CCIE` writer - Capture/compare interrupt enable"]
pub type CcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output mode 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Outmod {
#[doc = "0: PWM output mode: 0 - output only"]
Outmod0 = 0,
#[doc = "1: PWM output mode: 1 - set"]
Outmod1 = 1,
#[doc = "2: PWM output mode: 2 - PWM toggle/reset"]
Outmod2 = 2,
#[doc = "3: PWM output mode: 3 - PWM set/reset"]
Outmod3 = 3,
#[doc = "4: PWM output mode: 4 - toggle"]
Outmod4 = 4,
#[doc = "5: PWM output mode: 5 - Reset"]
Outmod5 = 5,
#[doc = "6: PWM output mode: 6 - PWM toggle/set"]
Outmod6 = 6,
#[doc = "7: PWM output mode: 7 - PWM reset/set"]
Outmod7 = 7,
}
impl From<Outmod> for u8 {
#[inline(always)]
fn from(variant: Outmod) -> Self {
variant as _
}
}
impl crate::FieldSpec for Outmod {
type Ux = u8;
}
impl crate::IsEnum for Outmod {}
#[doc = "Field `OUTMOD` reader - Output mode 2"]
pub type OutmodR = crate::FieldReader<Outmod>;
impl OutmodR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Outmod {
match self.bits {
0 => Outmod::Outmod0,
1 => Outmod::Outmod1,
2 => Outmod::Outmod2,
3 => Outmod::Outmod3,
4 => Outmod::Outmod4,
5 => Outmod::Outmod5,
6 => Outmod::Outmod6,
7 => Outmod::Outmod7,
_ => unreachable!(),
}
}
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn is_outmod_0(&self) -> bool {
*self == Outmod::Outmod0
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn is_outmod_1(&self) -> bool {
*self == Outmod::Outmod1
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn is_outmod_2(&self) -> bool {
*self == Outmod::Outmod2
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn is_outmod_3(&self) -> bool {
*self == Outmod::Outmod3
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn is_outmod_4(&self) -> bool {
*self == Outmod::Outmod4
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn is_outmod_5(&self) -> bool {
*self == Outmod::Outmod5
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn is_outmod_6(&self) -> bool {
*self == Outmod::Outmod6
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn is_outmod_7(&self) -> bool {
*self == Outmod::Outmod7
}
}
#[doc = "Field `OUTMOD` writer - Output mode 2"]
pub type OutmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Outmod, crate::Safe>;
impl<'a, REG> OutmodW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn outmod_0(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod0)
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn outmod_1(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod1)
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn outmod_2(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod2)
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn outmod_3(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod3)
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn outmod_4(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod4)
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn outmod_5(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod5)
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn outmod_6(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod6)
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn outmod_7(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod7)
}
}
#[doc = "Field `CAP` reader - Capture mode: 1 /Compare mode : 0"]
pub type CapR = crate::BitReader;
#[doc = "Field `CAP` writer - Capture mode: 1 /Compare mode : 0"]
pub type CapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCCI` reader - Latched capture signal (read)"]
pub type ScciR = crate::BitReader;
#[doc = "Field `SCCI` writer - Latched capture signal (read)"]
pub type ScciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCS` reader - Capture sychronize"]
pub type ScsR = crate::BitReader;
#[doc = "Field `SCS` writer - Capture sychronize"]
pub type ScsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture input select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ccis {
#[doc = "0: Capture input select: 0 - CCIxA"]
Ccis0 = 0,
#[doc = "1: Capture input select: 1 - CCIxB"]
Ccis1 = 1,
#[doc = "2: Capture input select: 2 - GND"]
Ccis2 = 2,
#[doc = "3: Capture input select: 3 - Vcc"]
Ccis3 = 3,
}
impl From<Ccis> for u8 {
#[inline(always)]
fn from(variant: Ccis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ccis {
type Ux = u8;
}
impl crate::IsEnum for Ccis {}
#[doc = "Field `CCIS` reader - Capture input select 1"]
pub type CcisR = crate::FieldReader<Ccis>;
impl CcisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccis {
match self.bits {
0 => Ccis::Ccis0,
1 => Ccis::Ccis1,
2 => Ccis::Ccis2,
3 => Ccis::Ccis3,
_ => unreachable!(),
}
}
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn is_ccis_0(&self) -> bool {
*self == Ccis::Ccis0
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn is_ccis_1(&self) -> bool {
*self == Ccis::Ccis1
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn is_ccis_2(&self) -> bool {
*self == Ccis::Ccis2
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn is_ccis_3(&self) -> bool {
*self == Ccis::Ccis3
}
}
#[doc = "Field `CCIS` writer - Capture input select 1"]
pub type CcisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ccis, crate::Safe>;
impl<'a, REG> CcisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn ccis_0(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis0)
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn ccis_1(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis1)
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn ccis_2(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis2)
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn ccis_3(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis3)
}
}
#[doc = "Capture mode 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Capture mode: 0 - disabled"]
Cm0 = 0,
#[doc = "1: Capture mode: 1 - pos. edge"]
Cm1 = 1,
#[doc = "2: Capture mode: 1 - neg. edge"]
Cm2 = 2,
#[doc = "3: Capture mode: 1 - both edges"]
Cm3 = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Capture mode 1"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cm {
match self.bits {
0 => Cm::Cm0,
1 => Cm::Cm1,
2 => Cm::Cm2,
3 => Cm::Cm3,
_ => unreachable!(),
}
}
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn is_cm_0(&self) -> bool {
*self == Cm::Cm0
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn is_cm_1(&self) -> bool {
*self == Cm::Cm1
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn is_cm_2(&self) -> bool {
*self == Cm::Cm2
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn is_cm_3(&self) -> bool {
*self == Cm::Cm3
}
}
#[doc = "Field `CM` writer - Capture mode 1"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm, crate::Safe>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn cm_0(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm0)
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn cm_1(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm1)
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn cm_2(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm2)
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn cm_3(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm3)
}
}
impl R {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&self) -> CcifgR {
CcifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&self) -> CovR {
CovR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&self) -> CciR {
CciR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&self) -> CcieR {
CcieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&self) -> OutmodR {
OutmodR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&self) -> ScciR {
ScciR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&self) -> ScsR {
ScsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&self) -> CcisR {
CcisR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&mut self) -> CcifgW<'_, Ta0cctl2Spec> {
CcifgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&mut self) -> CovW<'_, Ta0cctl2Spec> {
CovW::new(self, 1)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&mut self) -> OutW<'_, Ta0cctl2Spec> {
OutW::new(self, 2)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&mut self) -> CciW<'_, Ta0cctl2Spec> {
CciW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&mut self) -> CcieW<'_, Ta0cctl2Spec> {
CcieW::new(self, 4)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&mut self) -> OutmodW<'_, Ta0cctl2Spec> {
OutmodW::new(self, 5)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&mut self) -> CapW<'_, Ta0cctl2Spec> {
CapW::new(self, 8)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&mut self) -> ScciW<'_, Ta0cctl2Spec> {
ScciW::new(self, 10)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&mut self) -> ScsW<'_, Ta0cctl2Spec> {
ScsW::new(self, 11)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&mut self) -> CcisW<'_, Ta0cctl2Spec> {
CcisW::new(self, 12)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<'_, Ta0cctl2Spec> {
CmW::new(self, 14)
}
}
#[doc = "Timer0_A3 Capture/Compare Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0cctl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0cctl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta0cctl2Spec;
impl crate::RegisterSpec for Ta0cctl2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta0cctl2::R`](R) reader structure"]
impl crate::Readable for Ta0cctl2Spec {}
#[doc = "`write(|w| ..)` method takes [`ta0cctl2::W`](W) writer structure"]
impl crate::Writable for Ta0cctl2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA0CCTL2 to value 0"]
impl crate::Resettable for Ta0cctl2Spec {}
}
#[doc = "TA0R (rw) register accessor: Timer0_A3\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta0r`] module"]
#[doc(alias = "TA0R")]
pub type Ta0r = crate::Reg<ta0r::Ta0rSpec>;
#[doc = "Timer0_A3"]
pub mod ta0r {
#[doc = "Register `TA0R` reader"]
pub type R = crate::R<Ta0rSpec>;
#[doc = "Register `TA0R` writer"]
pub type W = crate::W<Ta0rSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer0_A3\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0r::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0r::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta0rSpec;
impl crate::RegisterSpec for Ta0rSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta0r::R`](R) reader structure"]
impl crate::Readable for Ta0rSpec {}
#[doc = "`write(|w| ..)` method takes [`ta0r::W`](W) writer structure"]
impl crate::Writable for Ta0rSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA0R to value 0"]
impl crate::Resettable for Ta0rSpec {}
}
#[doc = "TA0CCR0 (rw) register accessor: Timer0_A3 Capture/Compare 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0ccr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0ccr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta0ccr0`] module"]
#[doc(alias = "TA0CCR0")]
pub type Ta0ccr0 = crate::Reg<ta0ccr0::Ta0ccr0Spec>;
#[doc = "Timer0_A3 Capture/Compare 0"]
pub mod ta0ccr0 {
#[doc = "Register `TA0CCR0` reader"]
pub type R = crate::R<Ta0ccr0Spec>;
#[doc = "Register `TA0CCR0` writer"]
pub type W = crate::W<Ta0ccr0Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer0_A3 Capture/Compare 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0ccr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0ccr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta0ccr0Spec;
impl crate::RegisterSpec for Ta0ccr0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta0ccr0::R`](R) reader structure"]
impl crate::Readable for Ta0ccr0Spec {}
#[doc = "`write(|w| ..)` method takes [`ta0ccr0::W`](W) writer structure"]
impl crate::Writable for Ta0ccr0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA0CCR0 to value 0"]
impl crate::Resettable for Ta0ccr0Spec {}
}
#[doc = "TA0CCR1 (rw) register accessor: Timer0_A3 Capture/Compare 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0ccr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0ccr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta0ccr1`] module"]
#[doc(alias = "TA0CCR1")]
pub type Ta0ccr1 = crate::Reg<ta0ccr1::Ta0ccr1Spec>;
#[doc = "Timer0_A3 Capture/Compare 1"]
pub mod ta0ccr1 {
#[doc = "Register `TA0CCR1` reader"]
pub type R = crate::R<Ta0ccr1Spec>;
#[doc = "Register `TA0CCR1` writer"]
pub type W = crate::W<Ta0ccr1Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer0_A3 Capture/Compare 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0ccr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0ccr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta0ccr1Spec;
impl crate::RegisterSpec for Ta0ccr1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta0ccr1::R`](R) reader structure"]
impl crate::Readable for Ta0ccr1Spec {}
#[doc = "`write(|w| ..)` method takes [`ta0ccr1::W`](W) writer structure"]
impl crate::Writable for Ta0ccr1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA0CCR1 to value 0"]
impl crate::Resettable for Ta0ccr1Spec {}
}
#[doc = "TA0CCR2 (rw) register accessor: Timer0_A3 Capture/Compare 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0ccr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0ccr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta0ccr2`] module"]
#[doc(alias = "TA0CCR2")]
pub type Ta0ccr2 = crate::Reg<ta0ccr2::Ta0ccr2Spec>;
#[doc = "Timer0_A3 Capture/Compare 2"]
pub mod ta0ccr2 {
#[doc = "Register `TA0CCR2` reader"]
pub type R = crate::R<Ta0ccr2Spec>;
#[doc = "Register `TA0CCR2` writer"]
pub type W = crate::W<Ta0ccr2Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer0_A3 Capture/Compare 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0ccr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0ccr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta0ccr2Spec;
impl crate::RegisterSpec for Ta0ccr2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta0ccr2::R`](R) reader structure"]
impl crate::Readable for Ta0ccr2Spec {}
#[doc = "`write(|w| ..)` method takes [`ta0ccr2::W`](W) writer structure"]
impl crate::Writable for Ta0ccr2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA0CCR2 to value 0"]
impl crate::Resettable for Ta0ccr2Spec {}
}
#[doc = "TA0EX0 (rw) register accessor: Timer0_A3 Expansion Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0ex0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0ex0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta0ex0`] module"]
#[doc(alias = "TA0EX0")]
pub type Ta0ex0 = crate::Reg<ta0ex0::Ta0ex0Spec>;
#[doc = "Timer0_A3 Expansion Register 0"]
pub mod ta0ex0 {
#[doc = "Register `TA0EX0` reader"]
pub type R = crate::R<Ta0ex0Spec>;
#[doc = "Register `TA0EX0` writer"]
pub type W = crate::W<Ta0ex0Spec>;
#[doc = "Timer A Input divider expansion Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Taidex {
#[doc = "0: Timer A Input divider expansion : /1"]
Taidex0 = 0,
#[doc = "1: Timer A Input divider expansion : /2"]
Taidex1 = 1,
#[doc = "2: Timer A Input divider expansion : /3"]
Taidex2 = 2,
#[doc = "3: Timer A Input divider expansion : /4"]
Taidex3 = 3,
#[doc = "4: Timer A Input divider expansion : /5"]
Taidex4 = 4,
#[doc = "5: Timer A Input divider expansion : /6"]
Taidex5 = 5,
#[doc = "6: Timer A Input divider expansion : /7"]
Taidex6 = 6,
#[doc = "7: Timer A Input divider expansion : /8"]
Taidex7 = 7,
}
impl From<Taidex> for u8 {
#[inline(always)]
fn from(variant: Taidex) -> Self {
variant as _
}
}
impl crate::FieldSpec for Taidex {
type Ux = u8;
}
impl crate::IsEnum for Taidex {}
#[doc = "Field `TAIDEX` reader - Timer A Input divider expansion Bit: 0"]
pub type TaidexR = crate::FieldReader<Taidex>;
impl TaidexR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Taidex {
match self.bits {
0 => Taidex::Taidex0,
1 => Taidex::Taidex1,
2 => Taidex::Taidex2,
3 => Taidex::Taidex3,
4 => Taidex::Taidex4,
5 => Taidex::Taidex5,
6 => Taidex::Taidex6,
7 => Taidex::Taidex7,
_ => unreachable!(),
}
}
#[doc = "Timer A Input divider expansion : /1"]
#[inline(always)]
pub fn is_taidex_0(&self) -> bool {
*self == Taidex::Taidex0
}
#[doc = "Timer A Input divider expansion : /2"]
#[inline(always)]
pub fn is_taidex_1(&self) -> bool {
*self == Taidex::Taidex1
}
#[doc = "Timer A Input divider expansion : /3"]
#[inline(always)]
pub fn is_taidex_2(&self) -> bool {
*self == Taidex::Taidex2
}
#[doc = "Timer A Input divider expansion : /4"]
#[inline(always)]
pub fn is_taidex_3(&self) -> bool {
*self == Taidex::Taidex3
}
#[doc = "Timer A Input divider expansion : /5"]
#[inline(always)]
pub fn is_taidex_4(&self) -> bool {
*self == Taidex::Taidex4
}
#[doc = "Timer A Input divider expansion : /6"]
#[inline(always)]
pub fn is_taidex_5(&self) -> bool {
*self == Taidex::Taidex5
}
#[doc = "Timer A Input divider expansion : /7"]
#[inline(always)]
pub fn is_taidex_6(&self) -> bool {
*self == Taidex::Taidex6
}
#[doc = "Timer A Input divider expansion : /8"]
#[inline(always)]
pub fn is_taidex_7(&self) -> bool {
*self == Taidex::Taidex7
}
}
#[doc = "Field `TAIDEX` writer - Timer A Input divider expansion Bit: 0"]
pub type TaidexW<'a, REG> = crate::FieldWriter<'a, REG, 3, Taidex, crate::Safe>;
impl<'a, REG> TaidexW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A Input divider expansion : /1"]
#[inline(always)]
pub fn taidex_0(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex0)
}
#[doc = "Timer A Input divider expansion : /2"]
#[inline(always)]
pub fn taidex_1(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex1)
}
#[doc = "Timer A Input divider expansion : /3"]
#[inline(always)]
pub fn taidex_2(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex2)
}
#[doc = "Timer A Input divider expansion : /4"]
#[inline(always)]
pub fn taidex_3(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex3)
}
#[doc = "Timer A Input divider expansion : /5"]
#[inline(always)]
pub fn taidex_4(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex4)
}
#[doc = "Timer A Input divider expansion : /6"]
#[inline(always)]
pub fn taidex_5(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex5)
}
#[doc = "Timer A Input divider expansion : /7"]
#[inline(always)]
pub fn taidex_6(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex6)
}
#[doc = "Timer A Input divider expansion : /8"]
#[inline(always)]
pub fn taidex_7(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex7)
}
}
impl R {
#[doc = "Bits 0:2 - Timer A Input divider expansion Bit: 0"]
#[inline(always)]
pub fn taidex(&self) -> TaidexR {
TaidexR::new((self.bits & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:2 - Timer A Input divider expansion Bit: 0"]
#[inline(always)]
pub fn taidex(&mut self) -> TaidexW<'_, Ta0ex0Spec> {
TaidexW::new(self, 0)
}
}
#[doc = "Timer0_A3 Expansion Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0ex0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0ex0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta0ex0Spec;
impl crate::RegisterSpec for Ta0ex0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta0ex0::R`](R) reader structure"]
impl crate::Readable for Ta0ex0Spec {}
#[doc = "`write(|w| ..)` method takes [`ta0ex0::W`](W) writer structure"]
impl crate::Writable for Ta0ex0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA0EX0 to value 0"]
impl crate::Resettable for Ta0ex0Spec {}
}
#[doc = "TA0IV (rw) register accessor: Timer0_A3 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0iv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0iv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta0iv`] module"]
#[doc(alias = "TA0IV")]
pub type Ta0iv = crate::Reg<ta0iv::Ta0ivSpec>;
#[doc = "Timer0_A3 Interrupt Vector Word"]
pub mod ta0iv {
#[doc = "Register `TA0IV` reader"]
pub type R = crate::R<Ta0ivSpec>;
#[doc = "Register `TA0IV` writer"]
pub type W = crate::W<Ta0ivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer0_A3 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`ta0iv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta0iv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta0ivSpec;
impl crate::RegisterSpec for Ta0ivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta0iv::R`](R) reader structure"]
impl crate::Readable for Ta0ivSpec {}
#[doc = "`write(|w| ..)` method takes [`ta0iv::W`](W) writer structure"]
impl crate::Writable for Ta0ivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA0IV to value 0"]
impl crate::Resettable for Ta0ivSpec {}
}
}
#[doc = "Timer1_A3"]
pub type Timer1A3 = crate::Periph<timer_1_a3::RegisterBlock, 0x0380>;
impl core::fmt::Debug for Timer1A3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Timer1A3").finish()
}
}
#[doc = "Timer1_A3"]
pub mod timer_1_a3 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
ta1ctl: Ta1ctl,
ta1cctl0: Ta1cctl0,
ta1cctl1: Ta1cctl1,
ta1cctl2: Ta1cctl2,
_reserved4: [u8; 0x08],
ta1r: Ta1r,
ta1ccr0: Ta1ccr0,
ta1ccr1: Ta1ccr1,
ta1ccr2: Ta1ccr2,
_reserved8: [u8; 0x08],
ta1ex0: Ta1ex0,
_reserved9: [u8; 0x0c],
ta1iv: Ta1iv,
}
impl RegisterBlock {
#[doc = "0x00 - Timer1_A3 Control"]
#[inline(always)]
pub const fn ta1ctl(&self) -> &Ta1ctl {
&self.ta1ctl
}
#[doc = "0x02 - Timer1_A3 Capture/Compare Control 0"]
#[inline(always)]
pub const fn ta1cctl0(&self) -> &Ta1cctl0 {
&self.ta1cctl0
}
#[doc = "0x04 - Timer1_A3 Capture/Compare Control 1"]
#[inline(always)]
pub const fn ta1cctl1(&self) -> &Ta1cctl1 {
&self.ta1cctl1
}
#[doc = "0x06 - Timer1_A3 Capture/Compare Control 2"]
#[inline(always)]
pub const fn ta1cctl2(&self) -> &Ta1cctl2 {
&self.ta1cctl2
}
#[doc = "0x10 - Timer1_A3"]
#[inline(always)]
pub const fn ta1r(&self) -> &Ta1r {
&self.ta1r
}
#[doc = "0x12 - Timer1_A3 Capture/Compare 0"]
#[inline(always)]
pub const fn ta1ccr0(&self) -> &Ta1ccr0 {
&self.ta1ccr0
}
#[doc = "0x14 - Timer1_A3 Capture/Compare 1"]
#[inline(always)]
pub const fn ta1ccr1(&self) -> &Ta1ccr1 {
&self.ta1ccr1
}
#[doc = "0x16 - Timer1_A3 Capture/Compare 2"]
#[inline(always)]
pub const fn ta1ccr2(&self) -> &Ta1ccr2 {
&self.ta1ccr2
}
#[doc = "0x20 - Timer1_A3 Expansion Register 0"]
#[inline(always)]
pub const fn ta1ex0(&self) -> &Ta1ex0 {
&self.ta1ex0
}
#[doc = "0x2e - Timer1_A3 Interrupt Vector Word"]
#[inline(always)]
pub const fn ta1iv(&self) -> &Ta1iv {
&self.ta1iv
}
}
#[doc = "TA1CTL (rw) register accessor: Timer1_A3 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta1ctl`] module"]
#[doc(alias = "TA1CTL")]
pub type Ta1ctl = crate::Reg<ta1ctl::Ta1ctlSpec>;
#[doc = "Timer1_A3 Control"]
pub mod ta1ctl {
#[doc = "Register `TA1CTL` reader"]
pub type R = crate::R<Ta1ctlSpec>;
#[doc = "Register `TA1CTL` writer"]
pub type W = crate::W<Ta1ctlSpec>;
#[doc = "Field `TAIFG` reader - Timer A counter interrupt flag"]
pub type TaifgR = crate::BitReader;
#[doc = "Field `TAIFG` writer - Timer A counter interrupt flag"]
pub type TaifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TAIE` reader - Timer A counter interrupt enable"]
pub type TaieR = crate::BitReader;
#[doc = "Field `TAIE` writer - Timer A counter interrupt enable"]
pub type TaieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TACLR` reader - Timer A counter clear"]
pub type TaclrR = crate::BitReader;
#[doc = "Field `TACLR` writer - Timer A counter clear"]
pub type TaclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Timer A mode control 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mc {
#[doc = "0: Timer A mode control: 0 - Stop"]
Mc0 = 0,
#[doc = "1: Timer A mode control: 1 - Up to CCR0"]
Mc1 = 1,
#[doc = "2: Timer A mode control: 2 - Continuous up"]
Mc2 = 2,
#[doc = "3: Timer A mode control: 3 - Up/Down"]
Mc3 = 3,
}
impl From<Mc> for u8 {
#[inline(always)]
fn from(variant: Mc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mc {
type Ux = u8;
}
impl crate::IsEnum for Mc {}
#[doc = "Field `MC` reader - Timer A mode control 1"]
pub type McR = crate::FieldReader<Mc>;
impl McR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mc {
match self.bits {
0 => Mc::Mc0,
1 => Mc::Mc1,
2 => Mc::Mc2,
3 => Mc::Mc3,
_ => unreachable!(),
}
}
#[doc = "Timer A mode control: 0 - Stop"]
#[inline(always)]
pub fn is_mc_0(&self) -> bool {
*self == Mc::Mc0
}
#[doc = "Timer A mode control: 1 - Up to CCR0"]
#[inline(always)]
pub fn is_mc_1(&self) -> bool {
*self == Mc::Mc1
}
#[doc = "Timer A mode control: 2 - Continuous up"]
#[inline(always)]
pub fn is_mc_2(&self) -> bool {
*self == Mc::Mc2
}
#[doc = "Timer A mode control: 3 - Up/Down"]
#[inline(always)]
pub fn is_mc_3(&self) -> bool {
*self == Mc::Mc3
}
}
#[doc = "Field `MC` writer - Timer A mode control 1"]
pub type McW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mc, crate::Safe>;
impl<'a, REG> McW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A mode control: 0 - Stop"]
#[inline(always)]
pub fn mc_0(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc0)
}
#[doc = "Timer A mode control: 1 - Up to CCR0"]
#[inline(always)]
pub fn mc_1(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc1)
}
#[doc = "Timer A mode control: 2 - Continuous up"]
#[inline(always)]
pub fn mc_2(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc2)
}
#[doc = "Timer A mode control: 3 - Up/Down"]
#[inline(always)]
pub fn mc_3(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc3)
}
}
#[doc = "Timer A clock input divider 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Id {
#[doc = "0: Timer A input divider: 0 - /1"]
Id0 = 0,
#[doc = "1: Timer A input divider: 1 - /2"]
Id1 = 1,
#[doc = "2: Timer A input divider: 2 - /4"]
Id2 = 2,
#[doc = "3: Timer A input divider: 3 - /8"]
Id3 = 3,
}
impl From<Id> for u8 {
#[inline(always)]
fn from(variant: Id) -> Self {
variant as _
}
}
impl crate::FieldSpec for Id {
type Ux = u8;
}
impl crate::IsEnum for Id {}
#[doc = "Field `ID` reader - Timer A clock input divider 1"]
pub type IdR = crate::FieldReader<Id>;
impl IdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Id {
match self.bits {
0 => Id::Id0,
1 => Id::Id1,
2 => Id::Id2,
3 => Id::Id3,
_ => unreachable!(),
}
}
#[doc = "Timer A input divider: 0 - /1"]
#[inline(always)]
pub fn is_id_0(&self) -> bool {
*self == Id::Id0
}
#[doc = "Timer A input divider: 1 - /2"]
#[inline(always)]
pub fn is_id_1(&self) -> bool {
*self == Id::Id1
}
#[doc = "Timer A input divider: 2 - /4"]
#[inline(always)]
pub fn is_id_2(&self) -> bool {
*self == Id::Id2
}
#[doc = "Timer A input divider: 3 - /8"]
#[inline(always)]
pub fn is_id_3(&self) -> bool {
*self == Id::Id3
}
}
#[doc = "Field `ID` writer - Timer A clock input divider 1"]
pub type IdW<'a, REG> = crate::FieldWriter<'a, REG, 2, Id, crate::Safe>;
impl<'a, REG> IdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A input divider: 0 - /1"]
#[inline(always)]
pub fn id_0(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id0)
}
#[doc = "Timer A input divider: 1 - /2"]
#[inline(always)]
pub fn id_1(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id1)
}
#[doc = "Timer A input divider: 2 - /4"]
#[inline(always)]
pub fn id_2(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id2)
}
#[doc = "Timer A input divider: 3 - /8"]
#[inline(always)]
pub fn id_3(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id3)
}
}
#[doc = "Timer A clock source select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Tassel {
#[doc = "0: Timer A clock source select: 0 - TACLK"]
Tassel0 = 0,
#[doc = "1: Timer A clock source select: 1 - ACLK"]
Tassel1 = 1,
#[doc = "2: Timer A clock source select: 2 - SMCLK"]
Tassel2 = 2,
#[doc = "3: Timer A clock source select: 3 - INCLK"]
Tassel3 = 3,
}
impl From<Tassel> for u8 {
#[inline(always)]
fn from(variant: Tassel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Tassel {
type Ux = u8;
}
impl crate::IsEnum for Tassel {}
#[doc = "Field `TASSEL` reader - Timer A clock source select 1"]
pub type TasselR = crate::FieldReader<Tassel>;
impl TasselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Tassel {
match self.bits {
0 => Tassel::Tassel0,
1 => Tassel::Tassel1,
2 => Tassel::Tassel2,
3 => Tassel::Tassel3,
_ => unreachable!(),
}
}
#[doc = "Timer A clock source select: 0 - TACLK"]
#[inline(always)]
pub fn is_tassel_0(&self) -> bool {
*self == Tassel::Tassel0
}
#[doc = "Timer A clock source select: 1 - ACLK"]
#[inline(always)]
pub fn is_tassel_1(&self) -> bool {
*self == Tassel::Tassel1
}
#[doc = "Timer A clock source select: 2 - SMCLK"]
#[inline(always)]
pub fn is_tassel_2(&self) -> bool {
*self == Tassel::Tassel2
}
#[doc = "Timer A clock source select: 3 - INCLK"]
#[inline(always)]
pub fn is_tassel_3(&self) -> bool {
*self == Tassel::Tassel3
}
}
#[doc = "Field `TASSEL` writer - Timer A clock source select 1"]
pub type TasselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tassel, crate::Safe>;
impl<'a, REG> TasselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A clock source select: 0 - TACLK"]
#[inline(always)]
pub fn tassel_0(self) -> &'a mut crate::W<REG> {
self.variant(Tassel::Tassel0)
}
#[doc = "Timer A clock source select: 1 - ACLK"]
#[inline(always)]
pub fn tassel_1(self) -> &'a mut crate::W<REG> {
self.variant(Tassel::Tassel1)
}
#[doc = "Timer A clock source select: 2 - SMCLK"]
#[inline(always)]
pub fn tassel_2(self) -> &'a mut crate::W<REG> {
self.variant(Tassel::Tassel2)
}
#[doc = "Timer A clock source select: 3 - INCLK"]
#[inline(always)]
pub fn tassel_3(self) -> &'a mut crate::W<REG> {
self.variant(Tassel::Tassel3)
}
}
impl R {
#[doc = "Bit 0 - Timer A counter interrupt flag"]
#[inline(always)]
pub fn taifg(&self) -> TaifgR {
TaifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Timer A counter interrupt enable"]
#[inline(always)]
pub fn taie(&self) -> TaieR {
TaieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Timer A counter clear"]
#[inline(always)]
pub fn taclr(&self) -> TaclrR {
TaclrR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 4:5 - Timer A mode control 1"]
#[inline(always)]
pub fn mc(&self) -> McR {
McR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:7 - Timer A clock input divider 1"]
#[inline(always)]
pub fn id(&self) -> IdR {
IdR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:9 - Timer A clock source select 1"]
#[inline(always)]
pub fn tassel(&self) -> TasselR {
TasselR::new(((self.bits >> 8) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Timer A counter interrupt flag"]
#[inline(always)]
pub fn taifg(&mut self) -> TaifgW<'_, Ta1ctlSpec> {
TaifgW::new(self, 0)
}
#[doc = "Bit 1 - Timer A counter interrupt enable"]
#[inline(always)]
pub fn taie(&mut self) -> TaieW<'_, Ta1ctlSpec> {
TaieW::new(self, 1)
}
#[doc = "Bit 2 - Timer A counter clear"]
#[inline(always)]
pub fn taclr(&mut self) -> TaclrW<'_, Ta1ctlSpec> {
TaclrW::new(self, 2)
}
#[doc = "Bits 4:5 - Timer A mode control 1"]
#[inline(always)]
pub fn mc(&mut self) -> McW<'_, Ta1ctlSpec> {
McW::new(self, 4)
}
#[doc = "Bits 6:7 - Timer A clock input divider 1"]
#[inline(always)]
pub fn id(&mut self) -> IdW<'_, Ta1ctlSpec> {
IdW::new(self, 6)
}
#[doc = "Bits 8:9 - Timer A clock source select 1"]
#[inline(always)]
pub fn tassel(&mut self) -> TasselW<'_, Ta1ctlSpec> {
TasselW::new(self, 8)
}
}
#[doc = "Timer1_A3 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta1ctlSpec;
impl crate::RegisterSpec for Ta1ctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta1ctl::R`](R) reader structure"]
impl crate::Readable for Ta1ctlSpec {}
#[doc = "`write(|w| ..)` method takes [`ta1ctl::W`](W) writer structure"]
impl crate::Writable for Ta1ctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA1CTL to value 0"]
impl crate::Resettable for Ta1ctlSpec {}
}
#[doc = "TA1CCTL0 (rw) register accessor: Timer1_A3 Capture/Compare Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1cctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1cctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta1cctl0`] module"]
#[doc(alias = "TA1CCTL0")]
pub type Ta1cctl0 = crate::Reg<ta1cctl0::Ta1cctl0Spec>;
#[doc = "Timer1_A3 Capture/Compare Control 0"]
pub mod ta1cctl0 {
#[doc = "Register `TA1CCTL0` reader"]
pub type R = crate::R<Ta1cctl0Spec>;
#[doc = "Register `TA1CCTL0` writer"]
pub type W = crate::W<Ta1cctl0Spec>;
#[doc = "Field `CCIFG` reader - Capture/compare interrupt flag"]
pub type CcifgR = crate::BitReader;
#[doc = "Field `CCIFG` writer - Capture/compare interrupt flag"]
pub type CcifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COV` reader - Capture/compare overflow flag"]
pub type CovR = crate::BitReader;
#[doc = "Field `COV` writer - Capture/compare overflow flag"]
pub type CovW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OUT` reader - PWM Output signal if output mode 0"]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - PWM Output signal if output mode 0"]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCI` reader - Capture input signal (read)"]
pub type CciR = crate::BitReader;
#[doc = "Field `CCI` writer - Capture input signal (read)"]
pub type CciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCIE` reader - Capture/compare interrupt enable"]
pub type CcieR = crate::BitReader;
#[doc = "Field `CCIE` writer - Capture/compare interrupt enable"]
pub type CcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output mode 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Outmod {
#[doc = "0: PWM output mode: 0 - output only"]
Outmod0 = 0,
#[doc = "1: PWM output mode: 1 - set"]
Outmod1 = 1,
#[doc = "2: PWM output mode: 2 - PWM toggle/reset"]
Outmod2 = 2,
#[doc = "3: PWM output mode: 3 - PWM set/reset"]
Outmod3 = 3,
#[doc = "4: PWM output mode: 4 - toggle"]
Outmod4 = 4,
#[doc = "5: PWM output mode: 5 - Reset"]
Outmod5 = 5,
#[doc = "6: PWM output mode: 6 - PWM toggle/set"]
Outmod6 = 6,
#[doc = "7: PWM output mode: 7 - PWM reset/set"]
Outmod7 = 7,
}
impl From<Outmod> for u8 {
#[inline(always)]
fn from(variant: Outmod) -> Self {
variant as _
}
}
impl crate::FieldSpec for Outmod {
type Ux = u8;
}
impl crate::IsEnum for Outmod {}
#[doc = "Field `OUTMOD` reader - Output mode 2"]
pub type OutmodR = crate::FieldReader<Outmod>;
impl OutmodR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Outmod {
match self.bits {
0 => Outmod::Outmod0,
1 => Outmod::Outmod1,
2 => Outmod::Outmod2,
3 => Outmod::Outmod3,
4 => Outmod::Outmod4,
5 => Outmod::Outmod5,
6 => Outmod::Outmod6,
7 => Outmod::Outmod7,
_ => unreachable!(),
}
}
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn is_outmod_0(&self) -> bool {
*self == Outmod::Outmod0
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn is_outmod_1(&self) -> bool {
*self == Outmod::Outmod1
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn is_outmod_2(&self) -> bool {
*self == Outmod::Outmod2
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn is_outmod_3(&self) -> bool {
*self == Outmod::Outmod3
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn is_outmod_4(&self) -> bool {
*self == Outmod::Outmod4
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn is_outmod_5(&self) -> bool {
*self == Outmod::Outmod5
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn is_outmod_6(&self) -> bool {
*self == Outmod::Outmod6
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn is_outmod_7(&self) -> bool {
*self == Outmod::Outmod7
}
}
#[doc = "Field `OUTMOD` writer - Output mode 2"]
pub type OutmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Outmod, crate::Safe>;
impl<'a, REG> OutmodW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn outmod_0(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod0)
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn outmod_1(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod1)
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn outmod_2(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod2)
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn outmod_3(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod3)
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn outmod_4(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod4)
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn outmod_5(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod5)
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn outmod_6(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod6)
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn outmod_7(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod7)
}
}
#[doc = "Field `CAP` reader - Capture mode: 1 /Compare mode : 0"]
pub type CapR = crate::BitReader;
#[doc = "Field `CAP` writer - Capture mode: 1 /Compare mode : 0"]
pub type CapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCCI` reader - Latched capture signal (read)"]
pub type ScciR = crate::BitReader;
#[doc = "Field `SCCI` writer - Latched capture signal (read)"]
pub type ScciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCS` reader - Capture sychronize"]
pub type ScsR = crate::BitReader;
#[doc = "Field `SCS` writer - Capture sychronize"]
pub type ScsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture input select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ccis {
#[doc = "0: Capture input select: 0 - CCIxA"]
Ccis0 = 0,
#[doc = "1: Capture input select: 1 - CCIxB"]
Ccis1 = 1,
#[doc = "2: Capture input select: 2 - GND"]
Ccis2 = 2,
#[doc = "3: Capture input select: 3 - Vcc"]
Ccis3 = 3,
}
impl From<Ccis> for u8 {
#[inline(always)]
fn from(variant: Ccis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ccis {
type Ux = u8;
}
impl crate::IsEnum for Ccis {}
#[doc = "Field `CCIS` reader - Capture input select 1"]
pub type CcisR = crate::FieldReader<Ccis>;
impl CcisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccis {
match self.bits {
0 => Ccis::Ccis0,
1 => Ccis::Ccis1,
2 => Ccis::Ccis2,
3 => Ccis::Ccis3,
_ => unreachable!(),
}
}
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn is_ccis_0(&self) -> bool {
*self == Ccis::Ccis0
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn is_ccis_1(&self) -> bool {
*self == Ccis::Ccis1
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn is_ccis_2(&self) -> bool {
*self == Ccis::Ccis2
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn is_ccis_3(&self) -> bool {
*self == Ccis::Ccis3
}
}
#[doc = "Field `CCIS` writer - Capture input select 1"]
pub type CcisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ccis, crate::Safe>;
impl<'a, REG> CcisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn ccis_0(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis0)
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn ccis_1(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis1)
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn ccis_2(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis2)
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn ccis_3(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis3)
}
}
#[doc = "Capture mode 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Capture mode: 0 - disabled"]
Cm0 = 0,
#[doc = "1: Capture mode: 1 - pos. edge"]
Cm1 = 1,
#[doc = "2: Capture mode: 1 - neg. edge"]
Cm2 = 2,
#[doc = "3: Capture mode: 1 - both edges"]
Cm3 = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Capture mode 1"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cm {
match self.bits {
0 => Cm::Cm0,
1 => Cm::Cm1,
2 => Cm::Cm2,
3 => Cm::Cm3,
_ => unreachable!(),
}
}
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn is_cm_0(&self) -> bool {
*self == Cm::Cm0
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn is_cm_1(&self) -> bool {
*self == Cm::Cm1
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn is_cm_2(&self) -> bool {
*self == Cm::Cm2
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn is_cm_3(&self) -> bool {
*self == Cm::Cm3
}
}
#[doc = "Field `CM` writer - Capture mode 1"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm, crate::Safe>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn cm_0(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm0)
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn cm_1(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm1)
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn cm_2(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm2)
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn cm_3(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm3)
}
}
impl R {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&self) -> CcifgR {
CcifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&self) -> CovR {
CovR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&self) -> CciR {
CciR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&self) -> CcieR {
CcieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&self) -> OutmodR {
OutmodR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&self) -> ScciR {
ScciR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&self) -> ScsR {
ScsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&self) -> CcisR {
CcisR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&mut self) -> CcifgW<'_, Ta1cctl0Spec> {
CcifgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&mut self) -> CovW<'_, Ta1cctl0Spec> {
CovW::new(self, 1)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&mut self) -> OutW<'_, Ta1cctl0Spec> {
OutW::new(self, 2)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&mut self) -> CciW<'_, Ta1cctl0Spec> {
CciW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&mut self) -> CcieW<'_, Ta1cctl0Spec> {
CcieW::new(self, 4)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&mut self) -> OutmodW<'_, Ta1cctl0Spec> {
OutmodW::new(self, 5)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&mut self) -> CapW<'_, Ta1cctl0Spec> {
CapW::new(self, 8)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&mut self) -> ScciW<'_, Ta1cctl0Spec> {
ScciW::new(self, 10)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&mut self) -> ScsW<'_, Ta1cctl0Spec> {
ScsW::new(self, 11)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&mut self) -> CcisW<'_, Ta1cctl0Spec> {
CcisW::new(self, 12)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<'_, Ta1cctl0Spec> {
CmW::new(self, 14)
}
}
#[doc = "Timer1_A3 Capture/Compare Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1cctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1cctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta1cctl0Spec;
impl crate::RegisterSpec for Ta1cctl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta1cctl0::R`](R) reader structure"]
impl crate::Readable for Ta1cctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`ta1cctl0::W`](W) writer structure"]
impl crate::Writable for Ta1cctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA1CCTL0 to value 0"]
impl crate::Resettable for Ta1cctl0Spec {}
}
#[doc = "TA1CCTL1 (rw) register accessor: Timer1_A3 Capture/Compare Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1cctl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1cctl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta1cctl1`] module"]
#[doc(alias = "TA1CCTL1")]
pub type Ta1cctl1 = crate::Reg<ta1cctl1::Ta1cctl1Spec>;
#[doc = "Timer1_A3 Capture/Compare Control 1"]
pub mod ta1cctl1 {
#[doc = "Register `TA1CCTL1` reader"]
pub type R = crate::R<Ta1cctl1Spec>;
#[doc = "Register `TA1CCTL1` writer"]
pub type W = crate::W<Ta1cctl1Spec>;
#[doc = "Field `CCIFG` reader - Capture/compare interrupt flag"]
pub type CcifgR = crate::BitReader;
#[doc = "Field `CCIFG` writer - Capture/compare interrupt flag"]
pub type CcifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COV` reader - Capture/compare overflow flag"]
pub type CovR = crate::BitReader;
#[doc = "Field `COV` writer - Capture/compare overflow flag"]
pub type CovW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OUT` reader - PWM Output signal if output mode 0"]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - PWM Output signal if output mode 0"]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCI` reader - Capture input signal (read)"]
pub type CciR = crate::BitReader;
#[doc = "Field `CCI` writer - Capture input signal (read)"]
pub type CciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCIE` reader - Capture/compare interrupt enable"]
pub type CcieR = crate::BitReader;
#[doc = "Field `CCIE` writer - Capture/compare interrupt enable"]
pub type CcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output mode 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Outmod {
#[doc = "0: PWM output mode: 0 - output only"]
Outmod0 = 0,
#[doc = "1: PWM output mode: 1 - set"]
Outmod1 = 1,
#[doc = "2: PWM output mode: 2 - PWM toggle/reset"]
Outmod2 = 2,
#[doc = "3: PWM output mode: 3 - PWM set/reset"]
Outmod3 = 3,
#[doc = "4: PWM output mode: 4 - toggle"]
Outmod4 = 4,
#[doc = "5: PWM output mode: 5 - Reset"]
Outmod5 = 5,
#[doc = "6: PWM output mode: 6 - PWM toggle/set"]
Outmod6 = 6,
#[doc = "7: PWM output mode: 7 - PWM reset/set"]
Outmod7 = 7,
}
impl From<Outmod> for u8 {
#[inline(always)]
fn from(variant: Outmod) -> Self {
variant as _
}
}
impl crate::FieldSpec for Outmod {
type Ux = u8;
}
impl crate::IsEnum for Outmod {}
#[doc = "Field `OUTMOD` reader - Output mode 2"]
pub type OutmodR = crate::FieldReader<Outmod>;
impl OutmodR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Outmod {
match self.bits {
0 => Outmod::Outmod0,
1 => Outmod::Outmod1,
2 => Outmod::Outmod2,
3 => Outmod::Outmod3,
4 => Outmod::Outmod4,
5 => Outmod::Outmod5,
6 => Outmod::Outmod6,
7 => Outmod::Outmod7,
_ => unreachable!(),
}
}
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn is_outmod_0(&self) -> bool {
*self == Outmod::Outmod0
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn is_outmod_1(&self) -> bool {
*self == Outmod::Outmod1
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn is_outmod_2(&self) -> bool {
*self == Outmod::Outmod2
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn is_outmod_3(&self) -> bool {
*self == Outmod::Outmod3
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn is_outmod_4(&self) -> bool {
*self == Outmod::Outmod4
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn is_outmod_5(&self) -> bool {
*self == Outmod::Outmod5
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn is_outmod_6(&self) -> bool {
*self == Outmod::Outmod6
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn is_outmod_7(&self) -> bool {
*self == Outmod::Outmod7
}
}
#[doc = "Field `OUTMOD` writer - Output mode 2"]
pub type OutmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Outmod, crate::Safe>;
impl<'a, REG> OutmodW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn outmod_0(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod0)
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn outmod_1(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod1)
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn outmod_2(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod2)
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn outmod_3(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod3)
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn outmod_4(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod4)
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn outmod_5(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod5)
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn outmod_6(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod6)
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn outmod_7(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod7)
}
}
#[doc = "Field `CAP` reader - Capture mode: 1 /Compare mode : 0"]
pub type CapR = crate::BitReader;
#[doc = "Field `CAP` writer - Capture mode: 1 /Compare mode : 0"]
pub type CapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCCI` reader - Latched capture signal (read)"]
pub type ScciR = crate::BitReader;
#[doc = "Field `SCCI` writer - Latched capture signal (read)"]
pub type ScciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCS` reader - Capture sychronize"]
pub type ScsR = crate::BitReader;
#[doc = "Field `SCS` writer - Capture sychronize"]
pub type ScsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture input select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ccis {
#[doc = "0: Capture input select: 0 - CCIxA"]
Ccis0 = 0,
#[doc = "1: Capture input select: 1 - CCIxB"]
Ccis1 = 1,
#[doc = "2: Capture input select: 2 - GND"]
Ccis2 = 2,
#[doc = "3: Capture input select: 3 - Vcc"]
Ccis3 = 3,
}
impl From<Ccis> for u8 {
#[inline(always)]
fn from(variant: Ccis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ccis {
type Ux = u8;
}
impl crate::IsEnum for Ccis {}
#[doc = "Field `CCIS` reader - Capture input select 1"]
pub type CcisR = crate::FieldReader<Ccis>;
impl CcisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccis {
match self.bits {
0 => Ccis::Ccis0,
1 => Ccis::Ccis1,
2 => Ccis::Ccis2,
3 => Ccis::Ccis3,
_ => unreachable!(),
}
}
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn is_ccis_0(&self) -> bool {
*self == Ccis::Ccis0
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn is_ccis_1(&self) -> bool {
*self == Ccis::Ccis1
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn is_ccis_2(&self) -> bool {
*self == Ccis::Ccis2
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn is_ccis_3(&self) -> bool {
*self == Ccis::Ccis3
}
}
#[doc = "Field `CCIS` writer - Capture input select 1"]
pub type CcisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ccis, crate::Safe>;
impl<'a, REG> CcisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn ccis_0(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis0)
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn ccis_1(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis1)
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn ccis_2(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis2)
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn ccis_3(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis3)
}
}
#[doc = "Capture mode 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Capture mode: 0 - disabled"]
Cm0 = 0,
#[doc = "1: Capture mode: 1 - pos. edge"]
Cm1 = 1,
#[doc = "2: Capture mode: 1 - neg. edge"]
Cm2 = 2,
#[doc = "3: Capture mode: 1 - both edges"]
Cm3 = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Capture mode 1"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cm {
match self.bits {
0 => Cm::Cm0,
1 => Cm::Cm1,
2 => Cm::Cm2,
3 => Cm::Cm3,
_ => unreachable!(),
}
}
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn is_cm_0(&self) -> bool {
*self == Cm::Cm0
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn is_cm_1(&self) -> bool {
*self == Cm::Cm1
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn is_cm_2(&self) -> bool {
*self == Cm::Cm2
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn is_cm_3(&self) -> bool {
*self == Cm::Cm3
}
}
#[doc = "Field `CM` writer - Capture mode 1"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm, crate::Safe>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn cm_0(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm0)
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn cm_1(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm1)
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn cm_2(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm2)
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn cm_3(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm3)
}
}
impl R {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&self) -> CcifgR {
CcifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&self) -> CovR {
CovR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&self) -> CciR {
CciR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&self) -> CcieR {
CcieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&self) -> OutmodR {
OutmodR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&self) -> ScciR {
ScciR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&self) -> ScsR {
ScsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&self) -> CcisR {
CcisR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&mut self) -> CcifgW<'_, Ta1cctl1Spec> {
CcifgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&mut self) -> CovW<'_, Ta1cctl1Spec> {
CovW::new(self, 1)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&mut self) -> OutW<'_, Ta1cctl1Spec> {
OutW::new(self, 2)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&mut self) -> CciW<'_, Ta1cctl1Spec> {
CciW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&mut self) -> CcieW<'_, Ta1cctl1Spec> {
CcieW::new(self, 4)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&mut self) -> OutmodW<'_, Ta1cctl1Spec> {
OutmodW::new(self, 5)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&mut self) -> CapW<'_, Ta1cctl1Spec> {
CapW::new(self, 8)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&mut self) -> ScciW<'_, Ta1cctl1Spec> {
ScciW::new(self, 10)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&mut self) -> ScsW<'_, Ta1cctl1Spec> {
ScsW::new(self, 11)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&mut self) -> CcisW<'_, Ta1cctl1Spec> {
CcisW::new(self, 12)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<'_, Ta1cctl1Spec> {
CmW::new(self, 14)
}
}
#[doc = "Timer1_A3 Capture/Compare Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1cctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1cctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta1cctl1Spec;
impl crate::RegisterSpec for Ta1cctl1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta1cctl1::R`](R) reader structure"]
impl crate::Readable for Ta1cctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`ta1cctl1::W`](W) writer structure"]
impl crate::Writable for Ta1cctl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA1CCTL1 to value 0"]
impl crate::Resettable for Ta1cctl1Spec {}
}
#[doc = "TA1CCTL2 (rw) register accessor: Timer1_A3 Capture/Compare Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1cctl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1cctl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta1cctl2`] module"]
#[doc(alias = "TA1CCTL2")]
pub type Ta1cctl2 = crate::Reg<ta1cctl2::Ta1cctl2Spec>;
#[doc = "Timer1_A3 Capture/Compare Control 2"]
pub mod ta1cctl2 {
#[doc = "Register `TA1CCTL2` reader"]
pub type R = crate::R<Ta1cctl2Spec>;
#[doc = "Register `TA1CCTL2` writer"]
pub type W = crate::W<Ta1cctl2Spec>;
#[doc = "Field `CCIFG` reader - Capture/compare interrupt flag"]
pub type CcifgR = crate::BitReader;
#[doc = "Field `CCIFG` writer - Capture/compare interrupt flag"]
pub type CcifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COV` reader - Capture/compare overflow flag"]
pub type CovR = crate::BitReader;
#[doc = "Field `COV` writer - Capture/compare overflow flag"]
pub type CovW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OUT` reader - PWM Output signal if output mode 0"]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - PWM Output signal if output mode 0"]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCI` reader - Capture input signal (read)"]
pub type CciR = crate::BitReader;
#[doc = "Field `CCI` writer - Capture input signal (read)"]
pub type CciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCIE` reader - Capture/compare interrupt enable"]
pub type CcieR = crate::BitReader;
#[doc = "Field `CCIE` writer - Capture/compare interrupt enable"]
pub type CcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output mode 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Outmod {
#[doc = "0: PWM output mode: 0 - output only"]
Outmod0 = 0,
#[doc = "1: PWM output mode: 1 - set"]
Outmod1 = 1,
#[doc = "2: PWM output mode: 2 - PWM toggle/reset"]
Outmod2 = 2,
#[doc = "3: PWM output mode: 3 - PWM set/reset"]
Outmod3 = 3,
#[doc = "4: PWM output mode: 4 - toggle"]
Outmod4 = 4,
#[doc = "5: PWM output mode: 5 - Reset"]
Outmod5 = 5,
#[doc = "6: PWM output mode: 6 - PWM toggle/set"]
Outmod6 = 6,
#[doc = "7: PWM output mode: 7 - PWM reset/set"]
Outmod7 = 7,
}
impl From<Outmod> for u8 {
#[inline(always)]
fn from(variant: Outmod) -> Self {
variant as _
}
}
impl crate::FieldSpec for Outmod {
type Ux = u8;
}
impl crate::IsEnum for Outmod {}
#[doc = "Field `OUTMOD` reader - Output mode 2"]
pub type OutmodR = crate::FieldReader<Outmod>;
impl OutmodR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Outmod {
match self.bits {
0 => Outmod::Outmod0,
1 => Outmod::Outmod1,
2 => Outmod::Outmod2,
3 => Outmod::Outmod3,
4 => Outmod::Outmod4,
5 => Outmod::Outmod5,
6 => Outmod::Outmod6,
7 => Outmod::Outmod7,
_ => unreachable!(),
}
}
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn is_outmod_0(&self) -> bool {
*self == Outmod::Outmod0
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn is_outmod_1(&self) -> bool {
*self == Outmod::Outmod1
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn is_outmod_2(&self) -> bool {
*self == Outmod::Outmod2
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn is_outmod_3(&self) -> bool {
*self == Outmod::Outmod3
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn is_outmod_4(&self) -> bool {
*self == Outmod::Outmod4
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn is_outmod_5(&self) -> bool {
*self == Outmod::Outmod5
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn is_outmod_6(&self) -> bool {
*self == Outmod::Outmod6
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn is_outmod_7(&self) -> bool {
*self == Outmod::Outmod7
}
}
#[doc = "Field `OUTMOD` writer - Output mode 2"]
pub type OutmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Outmod, crate::Safe>;
impl<'a, REG> OutmodW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn outmod_0(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod0)
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn outmod_1(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod1)
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn outmod_2(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod2)
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn outmod_3(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod3)
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn outmod_4(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod4)
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn outmod_5(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod5)
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn outmod_6(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod6)
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn outmod_7(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod7)
}
}
#[doc = "Field `CAP` reader - Capture mode: 1 /Compare mode : 0"]
pub type CapR = crate::BitReader;
#[doc = "Field `CAP` writer - Capture mode: 1 /Compare mode : 0"]
pub type CapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCCI` reader - Latched capture signal (read)"]
pub type ScciR = crate::BitReader;
#[doc = "Field `SCCI` writer - Latched capture signal (read)"]
pub type ScciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCS` reader - Capture sychronize"]
pub type ScsR = crate::BitReader;
#[doc = "Field `SCS` writer - Capture sychronize"]
pub type ScsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture input select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ccis {
#[doc = "0: Capture input select: 0 - CCIxA"]
Ccis0 = 0,
#[doc = "1: Capture input select: 1 - CCIxB"]
Ccis1 = 1,
#[doc = "2: Capture input select: 2 - GND"]
Ccis2 = 2,
#[doc = "3: Capture input select: 3 - Vcc"]
Ccis3 = 3,
}
impl From<Ccis> for u8 {
#[inline(always)]
fn from(variant: Ccis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ccis {
type Ux = u8;
}
impl crate::IsEnum for Ccis {}
#[doc = "Field `CCIS` reader - Capture input select 1"]
pub type CcisR = crate::FieldReader<Ccis>;
impl CcisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccis {
match self.bits {
0 => Ccis::Ccis0,
1 => Ccis::Ccis1,
2 => Ccis::Ccis2,
3 => Ccis::Ccis3,
_ => unreachable!(),
}
}
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn is_ccis_0(&self) -> bool {
*self == Ccis::Ccis0
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn is_ccis_1(&self) -> bool {
*self == Ccis::Ccis1
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn is_ccis_2(&self) -> bool {
*self == Ccis::Ccis2
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn is_ccis_3(&self) -> bool {
*self == Ccis::Ccis3
}
}
#[doc = "Field `CCIS` writer - Capture input select 1"]
pub type CcisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ccis, crate::Safe>;
impl<'a, REG> CcisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn ccis_0(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis0)
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn ccis_1(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis1)
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn ccis_2(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis2)
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn ccis_3(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis3)
}
}
#[doc = "Capture mode 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Capture mode: 0 - disabled"]
Cm0 = 0,
#[doc = "1: Capture mode: 1 - pos. edge"]
Cm1 = 1,
#[doc = "2: Capture mode: 1 - neg. edge"]
Cm2 = 2,
#[doc = "3: Capture mode: 1 - both edges"]
Cm3 = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Capture mode 1"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cm {
match self.bits {
0 => Cm::Cm0,
1 => Cm::Cm1,
2 => Cm::Cm2,
3 => Cm::Cm3,
_ => unreachable!(),
}
}
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn is_cm_0(&self) -> bool {
*self == Cm::Cm0
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn is_cm_1(&self) -> bool {
*self == Cm::Cm1
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn is_cm_2(&self) -> bool {
*self == Cm::Cm2
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn is_cm_3(&self) -> bool {
*self == Cm::Cm3
}
}
#[doc = "Field `CM` writer - Capture mode 1"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm, crate::Safe>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn cm_0(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm0)
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn cm_1(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm1)
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn cm_2(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm2)
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn cm_3(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm3)
}
}
impl R {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&self) -> CcifgR {
CcifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&self) -> CovR {
CovR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&self) -> CciR {
CciR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&self) -> CcieR {
CcieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&self) -> OutmodR {
OutmodR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&self) -> ScciR {
ScciR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&self) -> ScsR {
ScsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&self) -> CcisR {
CcisR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&mut self) -> CcifgW<'_, Ta1cctl2Spec> {
CcifgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&mut self) -> CovW<'_, Ta1cctl2Spec> {
CovW::new(self, 1)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&mut self) -> OutW<'_, Ta1cctl2Spec> {
OutW::new(self, 2)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&mut self) -> CciW<'_, Ta1cctl2Spec> {
CciW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&mut self) -> CcieW<'_, Ta1cctl2Spec> {
CcieW::new(self, 4)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&mut self) -> OutmodW<'_, Ta1cctl2Spec> {
OutmodW::new(self, 5)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&mut self) -> CapW<'_, Ta1cctl2Spec> {
CapW::new(self, 8)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&mut self) -> ScciW<'_, Ta1cctl2Spec> {
ScciW::new(self, 10)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&mut self) -> ScsW<'_, Ta1cctl2Spec> {
ScsW::new(self, 11)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&mut self) -> CcisW<'_, Ta1cctl2Spec> {
CcisW::new(self, 12)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<'_, Ta1cctl2Spec> {
CmW::new(self, 14)
}
}
#[doc = "Timer1_A3 Capture/Compare Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1cctl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1cctl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta1cctl2Spec;
impl crate::RegisterSpec for Ta1cctl2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta1cctl2::R`](R) reader structure"]
impl crate::Readable for Ta1cctl2Spec {}
#[doc = "`write(|w| ..)` method takes [`ta1cctl2::W`](W) writer structure"]
impl crate::Writable for Ta1cctl2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA1CCTL2 to value 0"]
impl crate::Resettable for Ta1cctl2Spec {}
}
#[doc = "TA1R (rw) register accessor: Timer1_A3\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta1r`] module"]
#[doc(alias = "TA1R")]
pub type Ta1r = crate::Reg<ta1r::Ta1rSpec>;
#[doc = "Timer1_A3"]
pub mod ta1r {
#[doc = "Register `TA1R` reader"]
pub type R = crate::R<Ta1rSpec>;
#[doc = "Register `TA1R` writer"]
pub type W = crate::W<Ta1rSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer1_A3\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1r::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1r::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta1rSpec;
impl crate::RegisterSpec for Ta1rSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta1r::R`](R) reader structure"]
impl crate::Readable for Ta1rSpec {}
#[doc = "`write(|w| ..)` method takes [`ta1r::W`](W) writer structure"]
impl crate::Writable for Ta1rSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA1R to value 0"]
impl crate::Resettable for Ta1rSpec {}
}
#[doc = "TA1CCR0 (rw) register accessor: Timer1_A3 Capture/Compare 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1ccr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1ccr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta1ccr0`] module"]
#[doc(alias = "TA1CCR0")]
pub type Ta1ccr0 = crate::Reg<ta1ccr0::Ta1ccr0Spec>;
#[doc = "Timer1_A3 Capture/Compare 0"]
pub mod ta1ccr0 {
#[doc = "Register `TA1CCR0` reader"]
pub type R = crate::R<Ta1ccr0Spec>;
#[doc = "Register `TA1CCR0` writer"]
pub type W = crate::W<Ta1ccr0Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer1_A3 Capture/Compare 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1ccr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1ccr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta1ccr0Spec;
impl crate::RegisterSpec for Ta1ccr0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta1ccr0::R`](R) reader structure"]
impl crate::Readable for Ta1ccr0Spec {}
#[doc = "`write(|w| ..)` method takes [`ta1ccr0::W`](W) writer structure"]
impl crate::Writable for Ta1ccr0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA1CCR0 to value 0"]
impl crate::Resettable for Ta1ccr0Spec {}
}
#[doc = "TA1CCR1 (rw) register accessor: Timer1_A3 Capture/Compare 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1ccr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1ccr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta1ccr1`] module"]
#[doc(alias = "TA1CCR1")]
pub type Ta1ccr1 = crate::Reg<ta1ccr1::Ta1ccr1Spec>;
#[doc = "Timer1_A3 Capture/Compare 1"]
pub mod ta1ccr1 {
#[doc = "Register `TA1CCR1` reader"]
pub type R = crate::R<Ta1ccr1Spec>;
#[doc = "Register `TA1CCR1` writer"]
pub type W = crate::W<Ta1ccr1Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer1_A3 Capture/Compare 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1ccr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1ccr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta1ccr1Spec;
impl crate::RegisterSpec for Ta1ccr1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta1ccr1::R`](R) reader structure"]
impl crate::Readable for Ta1ccr1Spec {}
#[doc = "`write(|w| ..)` method takes [`ta1ccr1::W`](W) writer structure"]
impl crate::Writable for Ta1ccr1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA1CCR1 to value 0"]
impl crate::Resettable for Ta1ccr1Spec {}
}
#[doc = "TA1CCR2 (rw) register accessor: Timer1_A3 Capture/Compare 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1ccr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1ccr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta1ccr2`] module"]
#[doc(alias = "TA1CCR2")]
pub type Ta1ccr2 = crate::Reg<ta1ccr2::Ta1ccr2Spec>;
#[doc = "Timer1_A3 Capture/Compare 2"]
pub mod ta1ccr2 {
#[doc = "Register `TA1CCR2` reader"]
pub type R = crate::R<Ta1ccr2Spec>;
#[doc = "Register `TA1CCR2` writer"]
pub type W = crate::W<Ta1ccr2Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer1_A3 Capture/Compare 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1ccr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1ccr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta1ccr2Spec;
impl crate::RegisterSpec for Ta1ccr2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta1ccr2::R`](R) reader structure"]
impl crate::Readable for Ta1ccr2Spec {}
#[doc = "`write(|w| ..)` method takes [`ta1ccr2::W`](W) writer structure"]
impl crate::Writable for Ta1ccr2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA1CCR2 to value 0"]
impl crate::Resettable for Ta1ccr2Spec {}
}
#[doc = "TA1EX0 (rw) register accessor: Timer1_A3 Expansion Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1ex0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1ex0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta1ex0`] module"]
#[doc(alias = "TA1EX0")]
pub type Ta1ex0 = crate::Reg<ta1ex0::Ta1ex0Spec>;
#[doc = "Timer1_A3 Expansion Register 0"]
pub mod ta1ex0 {
#[doc = "Register `TA1EX0` reader"]
pub type R = crate::R<Ta1ex0Spec>;
#[doc = "Register `TA1EX0` writer"]
pub type W = crate::W<Ta1ex0Spec>;
#[doc = "Timer A Input divider expansion Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Taidex {
#[doc = "0: Timer A Input divider expansion : /1"]
Taidex0 = 0,
#[doc = "1: Timer A Input divider expansion : /2"]
Taidex1 = 1,
#[doc = "2: Timer A Input divider expansion : /3"]
Taidex2 = 2,
#[doc = "3: Timer A Input divider expansion : /4"]
Taidex3 = 3,
#[doc = "4: Timer A Input divider expansion : /5"]
Taidex4 = 4,
#[doc = "5: Timer A Input divider expansion : /6"]
Taidex5 = 5,
#[doc = "6: Timer A Input divider expansion : /7"]
Taidex6 = 6,
#[doc = "7: Timer A Input divider expansion : /8"]
Taidex7 = 7,
}
impl From<Taidex> for u8 {
#[inline(always)]
fn from(variant: Taidex) -> Self {
variant as _
}
}
impl crate::FieldSpec for Taidex {
type Ux = u8;
}
impl crate::IsEnum for Taidex {}
#[doc = "Field `TAIDEX` reader - Timer A Input divider expansion Bit: 0"]
pub type TaidexR = crate::FieldReader<Taidex>;
impl TaidexR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Taidex {
match self.bits {
0 => Taidex::Taidex0,
1 => Taidex::Taidex1,
2 => Taidex::Taidex2,
3 => Taidex::Taidex3,
4 => Taidex::Taidex4,
5 => Taidex::Taidex5,
6 => Taidex::Taidex6,
7 => Taidex::Taidex7,
_ => unreachable!(),
}
}
#[doc = "Timer A Input divider expansion : /1"]
#[inline(always)]
pub fn is_taidex_0(&self) -> bool {
*self == Taidex::Taidex0
}
#[doc = "Timer A Input divider expansion : /2"]
#[inline(always)]
pub fn is_taidex_1(&self) -> bool {
*self == Taidex::Taidex1
}
#[doc = "Timer A Input divider expansion : /3"]
#[inline(always)]
pub fn is_taidex_2(&self) -> bool {
*self == Taidex::Taidex2
}
#[doc = "Timer A Input divider expansion : /4"]
#[inline(always)]
pub fn is_taidex_3(&self) -> bool {
*self == Taidex::Taidex3
}
#[doc = "Timer A Input divider expansion : /5"]
#[inline(always)]
pub fn is_taidex_4(&self) -> bool {
*self == Taidex::Taidex4
}
#[doc = "Timer A Input divider expansion : /6"]
#[inline(always)]
pub fn is_taidex_5(&self) -> bool {
*self == Taidex::Taidex5
}
#[doc = "Timer A Input divider expansion : /7"]
#[inline(always)]
pub fn is_taidex_6(&self) -> bool {
*self == Taidex::Taidex6
}
#[doc = "Timer A Input divider expansion : /8"]
#[inline(always)]
pub fn is_taidex_7(&self) -> bool {
*self == Taidex::Taidex7
}
}
#[doc = "Field `TAIDEX` writer - Timer A Input divider expansion Bit: 0"]
pub type TaidexW<'a, REG> = crate::FieldWriter<'a, REG, 3, Taidex, crate::Safe>;
impl<'a, REG> TaidexW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A Input divider expansion : /1"]
#[inline(always)]
pub fn taidex_0(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex0)
}
#[doc = "Timer A Input divider expansion : /2"]
#[inline(always)]
pub fn taidex_1(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex1)
}
#[doc = "Timer A Input divider expansion : /3"]
#[inline(always)]
pub fn taidex_2(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex2)
}
#[doc = "Timer A Input divider expansion : /4"]
#[inline(always)]
pub fn taidex_3(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex3)
}
#[doc = "Timer A Input divider expansion : /5"]
#[inline(always)]
pub fn taidex_4(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex4)
}
#[doc = "Timer A Input divider expansion : /6"]
#[inline(always)]
pub fn taidex_5(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex5)
}
#[doc = "Timer A Input divider expansion : /7"]
#[inline(always)]
pub fn taidex_6(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex6)
}
#[doc = "Timer A Input divider expansion : /8"]
#[inline(always)]
pub fn taidex_7(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex7)
}
}
impl R {
#[doc = "Bits 0:2 - Timer A Input divider expansion Bit: 0"]
#[inline(always)]
pub fn taidex(&self) -> TaidexR {
TaidexR::new((self.bits & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:2 - Timer A Input divider expansion Bit: 0"]
#[inline(always)]
pub fn taidex(&mut self) -> TaidexW<'_, Ta1ex0Spec> {
TaidexW::new(self, 0)
}
}
#[doc = "Timer1_A3 Expansion Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1ex0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1ex0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta1ex0Spec;
impl crate::RegisterSpec for Ta1ex0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta1ex0::R`](R) reader structure"]
impl crate::Readable for Ta1ex0Spec {}
#[doc = "`write(|w| ..)` method takes [`ta1ex0::W`](W) writer structure"]
impl crate::Writable for Ta1ex0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA1EX0 to value 0"]
impl crate::Resettable for Ta1ex0Spec {}
}
#[doc = "TA1IV (rw) register accessor: Timer1_A3 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1iv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1iv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta1iv`] module"]
#[doc(alias = "TA1IV")]
pub type Ta1iv = crate::Reg<ta1iv::Ta1ivSpec>;
#[doc = "Timer1_A3 Interrupt Vector Word"]
pub mod ta1iv {
#[doc = "Register `TA1IV` reader"]
pub type R = crate::R<Ta1ivSpec>;
#[doc = "Register `TA1IV` writer"]
pub type W = crate::W<Ta1ivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer1_A3 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`ta1iv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta1iv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta1ivSpec;
impl crate::RegisterSpec for Ta1ivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta1iv::R`](R) reader structure"]
impl crate::Readable for Ta1ivSpec {}
#[doc = "`write(|w| ..)` method takes [`ta1iv::W`](W) writer structure"]
impl crate::Writable for Ta1ivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA1IV to value 0"]
impl crate::Resettable for Ta1ivSpec {}
}
}
#[doc = "Timer0_B7"]
pub type Timer0B7 = crate::Periph<timer_0_b7::RegisterBlock, 0x03c0>;
impl core::fmt::Debug for Timer0B7 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Timer0B7").finish()
}
}
#[doc = "Timer0_B7"]
pub mod timer_0_b7 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
tb0ctl: Tb0ctl,
tb0cctl0: Tb0cctl0,
tb0cctl1: Tb0cctl1,
tb0cctl2: Tb0cctl2,
tb0cctl3: Tb0cctl3,
tb0cctl4: Tb0cctl4,
tb0cctl5: Tb0cctl5,
tb0cctl6: Tb0cctl6,
tb0r: Tb0r,
tb0ccr0: Tb0ccr0,
tb0ccr1: Tb0ccr1,
tb0ccr2: Tb0ccr2,
tb0ccr3: Tb0ccr3,
tb0ccr4: Tb0ccr4,
tb0ccr5: Tb0ccr5,
tb0ccr6: Tb0ccr6,
tb0ex0: Tb0ex0,
_reserved17: [u8; 0x0c],
tb0iv: Tb0iv,
}
impl RegisterBlock {
#[doc = "0x00 - Timer0_B7 Control"]
#[inline(always)]
pub const fn tb0ctl(&self) -> &Tb0ctl {
&self.tb0ctl
}
#[doc = "0x02 - Timer0_B7 Capture/Compare Control 0"]
#[inline(always)]
pub const fn tb0cctl0(&self) -> &Tb0cctl0 {
&self.tb0cctl0
}
#[doc = "0x04 - Timer0_B7 Capture/Compare Control 1"]
#[inline(always)]
pub const fn tb0cctl1(&self) -> &Tb0cctl1 {
&self.tb0cctl1
}
#[doc = "0x06 - Timer0_B7 Capture/Compare Control 2"]
#[inline(always)]
pub const fn tb0cctl2(&self) -> &Tb0cctl2 {
&self.tb0cctl2
}
#[doc = "0x08 - Timer0_B7 Capture/Compare Control 3"]
#[inline(always)]
pub const fn tb0cctl3(&self) -> &Tb0cctl3 {
&self.tb0cctl3
}
#[doc = "0x0a - Timer0_B7 Capture/Compare Control 4"]
#[inline(always)]
pub const fn tb0cctl4(&self) -> &Tb0cctl4 {
&self.tb0cctl4
}
#[doc = "0x0c - Timer0_B7 Capture/Compare Control 5"]
#[inline(always)]
pub const fn tb0cctl5(&self) -> &Tb0cctl5 {
&self.tb0cctl5
}
#[doc = "0x0e - Timer0_B7 Capture/Compare Control 6"]
#[inline(always)]
pub const fn tb0cctl6(&self) -> &Tb0cctl6 {
&self.tb0cctl6
}
#[doc = "0x10 - Timer0_B7"]
#[inline(always)]
pub const fn tb0r(&self) -> &Tb0r {
&self.tb0r
}
#[doc = "0x12 - Timer0_B7 Capture/Compare 0"]
#[inline(always)]
pub const fn tb0ccr0(&self) -> &Tb0ccr0 {
&self.tb0ccr0
}
#[doc = "0x14 - Timer0_B7 Capture/Compare 1"]
#[inline(always)]
pub const fn tb0ccr1(&self) -> &Tb0ccr1 {
&self.tb0ccr1
}
#[doc = "0x16 - Timer0_B7 Capture/Compare 2"]
#[inline(always)]
pub const fn tb0ccr2(&self) -> &Tb0ccr2 {
&self.tb0ccr2
}
#[doc = "0x18 - Timer0_B7 Capture/Compare 3"]
#[inline(always)]
pub const fn tb0ccr3(&self) -> &Tb0ccr3 {
&self.tb0ccr3
}
#[doc = "0x1a - Timer0_B7 Capture/Compare 4"]
#[inline(always)]
pub const fn tb0ccr4(&self) -> &Tb0ccr4 {
&self.tb0ccr4
}
#[doc = "0x1c - Timer0_B7 Capture/Compare 5"]
#[inline(always)]
pub const fn tb0ccr5(&self) -> &Tb0ccr5 {
&self.tb0ccr5
}
#[doc = "0x1e - Timer0_B7 Capture/Compare 6"]
#[inline(always)]
pub const fn tb0ccr6(&self) -> &Tb0ccr6 {
&self.tb0ccr6
}
#[doc = "0x20 - Timer0_B7 Expansion Register 0"]
#[inline(always)]
pub const fn tb0ex0(&self) -> &Tb0ex0 {
&self.tb0ex0
}
#[doc = "0x2e - Timer0_B7 Interrupt Vector Word"]
#[inline(always)]
pub const fn tb0iv(&self) -> &Tb0iv {
&self.tb0iv
}
}
#[doc = "TB0CTL (rw) register accessor: Timer0_B7 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0ctl`] module"]
#[doc(alias = "TB0CTL")]
pub type Tb0ctl = crate::Reg<tb0ctl::Tb0ctlSpec>;
#[doc = "Timer0_B7 Control"]
pub mod tb0ctl {
#[doc = "Register `TB0CTL` reader"]
pub type R = crate::R<Tb0ctlSpec>;
#[doc = "Register `TB0CTL` writer"]
pub type W = crate::W<Tb0ctlSpec>;
#[doc = "Field `TBIFG` reader - Timer0_B7 interrupt flag"]
pub type TbifgR = crate::BitReader;
#[doc = "Field `TBIFG` writer - Timer0_B7 interrupt flag"]
pub type TbifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TBIE` reader - Timer0_B7 interrupt enable"]
pub type TbieR = crate::BitReader;
#[doc = "Field `TBIE` writer - Timer0_B7 interrupt enable"]
pub type TbieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TBCLR` reader - Timer0_B7 counter clear"]
pub type TbclrR = crate::BitReader;
#[doc = "Field `TBCLR` writer - Timer0_B7 counter clear"]
pub type TbclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Timer0_B7 mode control 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mc {
#[doc = "0: Timer A mode control: 0 - Stop"]
Mc0 = 0,
#[doc = "1: Timer A mode control: 1 - Up to CCR0"]
Mc1 = 1,
#[doc = "2: Timer A mode control: 2 - Continuous up"]
Mc2 = 2,
#[doc = "3: Timer A mode control: 3 - Up/Down"]
Mc3 = 3,
}
impl From<Mc> for u8 {
#[inline(always)]
fn from(variant: Mc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mc {
type Ux = u8;
}
impl crate::IsEnum for Mc {}
#[doc = "Field `MC` reader - Timer0_B7 mode control 1"]
pub type McR = crate::FieldReader<Mc>;
impl McR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mc {
match self.bits {
0 => Mc::Mc0,
1 => Mc::Mc1,
2 => Mc::Mc2,
3 => Mc::Mc3,
_ => unreachable!(),
}
}
#[doc = "Timer A mode control: 0 - Stop"]
#[inline(always)]
pub fn is_mc_0(&self) -> bool {
*self == Mc::Mc0
}
#[doc = "Timer A mode control: 1 - Up to CCR0"]
#[inline(always)]
pub fn is_mc_1(&self) -> bool {
*self == Mc::Mc1
}
#[doc = "Timer A mode control: 2 - Continuous up"]
#[inline(always)]
pub fn is_mc_2(&self) -> bool {
*self == Mc::Mc2
}
#[doc = "Timer A mode control: 3 - Up/Down"]
#[inline(always)]
pub fn is_mc_3(&self) -> bool {
*self == Mc::Mc3
}
}
#[doc = "Field `MC` writer - Timer0_B7 mode control 1"]
pub type McW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mc, crate::Safe>;
impl<'a, REG> McW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A mode control: 0 - Stop"]
#[inline(always)]
pub fn mc_0(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc0)
}
#[doc = "Timer A mode control: 1 - Up to CCR0"]
#[inline(always)]
pub fn mc_1(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc1)
}
#[doc = "Timer A mode control: 2 - Continuous up"]
#[inline(always)]
pub fn mc_2(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc2)
}
#[doc = "Timer A mode control: 3 - Up/Down"]
#[inline(always)]
pub fn mc_3(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc3)
}
}
#[doc = "Timer0_B7 clock input divider 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Id {
#[doc = "0: Timer A input divider: 0 - /1"]
Id0 = 0,
#[doc = "1: Timer A input divider: 1 - /2"]
Id1 = 1,
#[doc = "2: Timer A input divider: 2 - /4"]
Id2 = 2,
#[doc = "3: Timer A input divider: 3 - /8"]
Id3 = 3,
}
impl From<Id> for u8 {
#[inline(always)]
fn from(variant: Id) -> Self {
variant as _
}
}
impl crate::FieldSpec for Id {
type Ux = u8;
}
impl crate::IsEnum for Id {}
#[doc = "Field `ID` reader - Timer0_B7 clock input divider 1"]
pub type IdR = crate::FieldReader<Id>;
impl IdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Id {
match self.bits {
0 => Id::Id0,
1 => Id::Id1,
2 => Id::Id2,
3 => Id::Id3,
_ => unreachable!(),
}
}
#[doc = "Timer A input divider: 0 - /1"]
#[inline(always)]
pub fn is_id_0(&self) -> bool {
*self == Id::Id0
}
#[doc = "Timer A input divider: 1 - /2"]
#[inline(always)]
pub fn is_id_1(&self) -> bool {
*self == Id::Id1
}
#[doc = "Timer A input divider: 2 - /4"]
#[inline(always)]
pub fn is_id_2(&self) -> bool {
*self == Id::Id2
}
#[doc = "Timer A input divider: 3 - /8"]
#[inline(always)]
pub fn is_id_3(&self) -> bool {
*self == Id::Id3
}
}
#[doc = "Field `ID` writer - Timer0_B7 clock input divider 1"]
pub type IdW<'a, REG> = crate::FieldWriter<'a, REG, 2, Id, crate::Safe>;
impl<'a, REG> IdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A input divider: 0 - /1"]
#[inline(always)]
pub fn id_0(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id0)
}
#[doc = "Timer A input divider: 1 - /2"]
#[inline(always)]
pub fn id_1(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id1)
}
#[doc = "Timer A input divider: 2 - /4"]
#[inline(always)]
pub fn id_2(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id2)
}
#[doc = "Timer A input divider: 3 - /8"]
#[inline(always)]
pub fn id_3(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id3)
}
}
#[doc = "Clock source 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Tbssel {
#[doc = "0: Clock Source: TBCLK"]
Tbssel0 = 0,
#[doc = "1: Clock Source: ACLK"]
Tbssel1 = 1,
#[doc = "2: Clock Source: SMCLK"]
Tbssel2 = 2,
#[doc = "3: Clock Source: INCLK"]
Tbssel3 = 3,
}
impl From<Tbssel> for u8 {
#[inline(always)]
fn from(variant: Tbssel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Tbssel {
type Ux = u8;
}
impl crate::IsEnum for Tbssel {}
#[doc = "Field `TBSSEL` reader - Clock source 1"]
pub type TbsselR = crate::FieldReader<Tbssel>;
impl TbsselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Tbssel {
match self.bits {
0 => Tbssel::Tbssel0,
1 => Tbssel::Tbssel1,
2 => Tbssel::Tbssel2,
3 => Tbssel::Tbssel3,
_ => unreachable!(),
}
}
#[doc = "Clock Source: TBCLK"]
#[inline(always)]
pub fn is_tbssel_0(&self) -> bool {
*self == Tbssel::Tbssel0
}
#[doc = "Clock Source: ACLK"]
#[inline(always)]
pub fn is_tbssel_1(&self) -> bool {
*self == Tbssel::Tbssel1
}
#[doc = "Clock Source: SMCLK"]
#[inline(always)]
pub fn is_tbssel_2(&self) -> bool {
*self == Tbssel::Tbssel2
}
#[doc = "Clock Source: INCLK"]
#[inline(always)]
pub fn is_tbssel_3(&self) -> bool {
*self == Tbssel::Tbssel3
}
}
#[doc = "Field `TBSSEL` writer - Clock source 1"]
pub type TbsselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tbssel, crate::Safe>;
impl<'a, REG> TbsselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Clock Source: TBCLK"]
#[inline(always)]
pub fn tbssel_0(self) -> &'a mut crate::W<REG> {
self.variant(Tbssel::Tbssel0)
}
#[doc = "Clock Source: ACLK"]
#[inline(always)]
pub fn tbssel_1(self) -> &'a mut crate::W<REG> {
self.variant(Tbssel::Tbssel1)
}
#[doc = "Clock Source: SMCLK"]
#[inline(always)]
pub fn tbssel_2(self) -> &'a mut crate::W<REG> {
self.variant(Tbssel::Tbssel2)
}
#[doc = "Clock Source: INCLK"]
#[inline(always)]
pub fn tbssel_3(self) -> &'a mut crate::W<REG> {
self.variant(Tbssel::Tbssel3)
}
}
#[doc = "Counter lenght 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cntl {
#[doc = "0: Counter lenght: 16 bit"]
Cntl0 = 0,
#[doc = "1: Counter lenght: 12 bit"]
Cntl1 = 1,
#[doc = "2: Counter lenght: 10 bit"]
Cntl2 = 2,
#[doc = "3: Counter lenght: 8 bit"]
Cntl3 = 3,
}
impl From<Cntl> for u8 {
#[inline(always)]
fn from(variant: Cntl) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cntl {
type Ux = u8;
}
impl crate::IsEnum for Cntl {}
#[doc = "Field `CNTL` reader - Counter lenght 1"]
pub type CntlR = crate::FieldReader<Cntl>;
impl CntlR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cntl {
match self.bits {
0 => Cntl::Cntl0,
1 => Cntl::Cntl1,
2 => Cntl::Cntl2,
3 => Cntl::Cntl3,
_ => unreachable!(),
}
}
#[doc = "Counter lenght: 16 bit"]
#[inline(always)]
pub fn is_cntl_0(&self) -> bool {
*self == Cntl::Cntl0
}
#[doc = "Counter lenght: 12 bit"]
#[inline(always)]
pub fn is_cntl_1(&self) -> bool {
*self == Cntl::Cntl1
}
#[doc = "Counter lenght: 10 bit"]
#[inline(always)]
pub fn is_cntl_2(&self) -> bool {
*self == Cntl::Cntl2
}
#[doc = "Counter lenght: 8 bit"]
#[inline(always)]
pub fn is_cntl_3(&self) -> bool {
*self == Cntl::Cntl3
}
}
#[doc = "Field `CNTL` writer - Counter lenght 1"]
pub type CntlW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cntl, crate::Safe>;
impl<'a, REG> CntlW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Counter lenght: 16 bit"]
#[inline(always)]
pub fn cntl_0(self) -> &'a mut crate::W<REG> {
self.variant(Cntl::Cntl0)
}
#[doc = "Counter lenght: 12 bit"]
#[inline(always)]
pub fn cntl_1(self) -> &'a mut crate::W<REG> {
self.variant(Cntl::Cntl1)
}
#[doc = "Counter lenght: 10 bit"]
#[inline(always)]
pub fn cntl_2(self) -> &'a mut crate::W<REG> {
self.variant(Cntl::Cntl2)
}
#[doc = "Counter lenght: 8 bit"]
#[inline(always)]
pub fn cntl_3(self) -> &'a mut crate::W<REG> {
self.variant(Cntl::Cntl3)
}
}
#[doc = "Timer0_B7 Compare latch load group 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Tbclgrp {
#[doc = "0: Timer0_B7 Group: 0 - individually"]
Tbclgrp0 = 0,
#[doc = "1: Timer0_B7 Group: 1 - 3 groups (1-2"]
Tbclgrp1 = 1,
#[doc = "2: Timer0_B7 Group: 2 - 2 groups (1-3"]
Tbclgrp2 = 2,
#[doc = "3: Timer0_B7 Group: 3 - 1 group (all)"]
Tbclgrp3 = 3,
}
impl From<Tbclgrp> for u8 {
#[inline(always)]
fn from(variant: Tbclgrp) -> Self {
variant as _
}
}
impl crate::FieldSpec for Tbclgrp {
type Ux = u8;
}
impl crate::IsEnum for Tbclgrp {}
#[doc = "Field `TBCLGRP` reader - Timer0_B7 Compare latch load group 1"]
pub type TbclgrpR = crate::FieldReader<Tbclgrp>;
impl TbclgrpR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Tbclgrp {
match self.bits {
0 => Tbclgrp::Tbclgrp0,
1 => Tbclgrp::Tbclgrp1,
2 => Tbclgrp::Tbclgrp2,
3 => Tbclgrp::Tbclgrp3,
_ => unreachable!(),
}
}
#[doc = "Timer0_B7 Group: 0 - individually"]
#[inline(always)]
pub fn is_tbclgrp_0(&self) -> bool {
*self == Tbclgrp::Tbclgrp0
}
#[doc = "Timer0_B7 Group: 1 - 3 groups (1-2"]
#[inline(always)]
pub fn is_tbclgrp_1(&self) -> bool {
*self == Tbclgrp::Tbclgrp1
}
#[doc = "Timer0_B7 Group: 2 - 2 groups (1-3"]
#[inline(always)]
pub fn is_tbclgrp_2(&self) -> bool {
*self == Tbclgrp::Tbclgrp2
}
#[doc = "Timer0_B7 Group: 3 - 1 group (all)"]
#[inline(always)]
pub fn is_tbclgrp_3(&self) -> bool {
*self == Tbclgrp::Tbclgrp3
}
}
#[doc = "Field `TBCLGRP` writer - Timer0_B7 Compare latch load group 1"]
pub type TbclgrpW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tbclgrp, crate::Safe>;
impl<'a, REG> TbclgrpW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer0_B7 Group: 0 - individually"]
#[inline(always)]
pub fn tbclgrp_0(self) -> &'a mut crate::W<REG> {
self.variant(Tbclgrp::Tbclgrp0)
}
#[doc = "Timer0_B7 Group: 1 - 3 groups (1-2"]
#[inline(always)]
pub fn tbclgrp_1(self) -> &'a mut crate::W<REG> {
self.variant(Tbclgrp::Tbclgrp1)
}
#[doc = "Timer0_B7 Group: 2 - 2 groups (1-3"]
#[inline(always)]
pub fn tbclgrp_2(self) -> &'a mut crate::W<REG> {
self.variant(Tbclgrp::Tbclgrp2)
}
#[doc = "Timer0_B7 Group: 3 - 1 group (all)"]
#[inline(always)]
pub fn tbclgrp_3(self) -> &'a mut crate::W<REG> {
self.variant(Tbclgrp::Tbclgrp3)
}
}
impl R {
#[doc = "Bit 0 - Timer0_B7 interrupt flag"]
#[inline(always)]
pub fn tbifg(&self) -> TbifgR {
TbifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Timer0_B7 interrupt enable"]
#[inline(always)]
pub fn tbie(&self) -> TbieR {
TbieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Timer0_B7 counter clear"]
#[inline(always)]
pub fn tbclr(&self) -> TbclrR {
TbclrR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 4:5 - Timer0_B7 mode control 1"]
#[inline(always)]
pub fn mc(&self) -> McR {
McR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:7 - Timer0_B7 clock input divider 1"]
#[inline(always)]
pub fn id(&self) -> IdR {
IdR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:9 - Clock source 1"]
#[inline(always)]
pub fn tbssel(&self) -> TbsselR {
TbsselR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 11:12 - Counter lenght 1"]
#[inline(always)]
pub fn cntl(&self) -> CntlR {
CntlR::new(((self.bits >> 11) & 3) as u8)
}
#[doc = "Bits 13:14 - Timer0_B7 Compare latch load group 1"]
#[inline(always)]
pub fn tbclgrp(&self) -> TbclgrpR {
TbclgrpR::new(((self.bits >> 13) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Timer0_B7 interrupt flag"]
#[inline(always)]
pub fn tbifg(&mut self) -> TbifgW<'_, Tb0ctlSpec> {
TbifgW::new(self, 0)
}
#[doc = "Bit 1 - Timer0_B7 interrupt enable"]
#[inline(always)]
pub fn tbie(&mut self) -> TbieW<'_, Tb0ctlSpec> {
TbieW::new(self, 1)
}
#[doc = "Bit 2 - Timer0_B7 counter clear"]
#[inline(always)]
pub fn tbclr(&mut self) -> TbclrW<'_, Tb0ctlSpec> {
TbclrW::new(self, 2)
}
#[doc = "Bits 4:5 - Timer0_B7 mode control 1"]
#[inline(always)]
pub fn mc(&mut self) -> McW<'_, Tb0ctlSpec> {
McW::new(self, 4)
}
#[doc = "Bits 6:7 - Timer0_B7 clock input divider 1"]
#[inline(always)]
pub fn id(&mut self) -> IdW<'_, Tb0ctlSpec> {
IdW::new(self, 6)
}
#[doc = "Bits 8:9 - Clock source 1"]
#[inline(always)]
pub fn tbssel(&mut self) -> TbsselW<'_, Tb0ctlSpec> {
TbsselW::new(self, 8)
}
#[doc = "Bits 11:12 - Counter lenght 1"]
#[inline(always)]
pub fn cntl(&mut self) -> CntlW<'_, Tb0ctlSpec> {
CntlW::new(self, 11)
}
#[doc = "Bits 13:14 - Timer0_B7 Compare latch load group 1"]
#[inline(always)]
pub fn tbclgrp(&mut self) -> TbclgrpW<'_, Tb0ctlSpec> {
TbclgrpW::new(self, 13)
}
}
#[doc = "Timer0_B7 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0ctlSpec;
impl crate::RegisterSpec for Tb0ctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0ctl::R`](R) reader structure"]
impl crate::Readable for Tb0ctlSpec {}
#[doc = "`write(|w| ..)` method takes [`tb0ctl::W`](W) writer structure"]
impl crate::Writable for Tb0ctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0CTL to value 0"]
impl crate::Resettable for Tb0ctlSpec {}
}
#[doc = "TB0CCTL0 (rw) register accessor: Timer0_B7 Capture/Compare Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0cctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0cctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0cctl0`] module"]
#[doc(alias = "TB0CCTL0")]
pub type Tb0cctl0 = crate::Reg<tb0cctl0::Tb0cctl0Spec>;
#[doc = "Timer0_B7 Capture/Compare Control 0"]
pub mod tb0cctl0 {
#[doc = "Register `TB0CCTL0` reader"]
pub type R = crate::R<Tb0cctl0Spec>;
#[doc = "Register `TB0CCTL0` writer"]
pub type W = crate::W<Tb0cctl0Spec>;
#[doc = "Field `CCIFG` reader - Capture/compare interrupt flag"]
pub type CcifgR = crate::BitReader;
#[doc = "Field `CCIFG` writer - Capture/compare interrupt flag"]
pub type CcifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COV` reader - Capture/compare overflow flag"]
pub type CovR = crate::BitReader;
#[doc = "Field `COV` writer - Capture/compare overflow flag"]
pub type CovW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OUT` reader - PWM Output signal if output mode 0"]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - PWM Output signal if output mode 0"]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCI` reader - Capture input signal (read)"]
pub type CciR = crate::BitReader;
#[doc = "Field `CCI` writer - Capture input signal (read)"]
pub type CciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCIE` reader - Capture/compare interrupt enable"]
pub type CcieR = crate::BitReader;
#[doc = "Field `CCIE` writer - Capture/compare interrupt enable"]
pub type CcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output mode 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Outmod {
#[doc = "0: PWM output mode: 0 - output only"]
Outmod0 = 0,
#[doc = "1: PWM output mode: 1 - set"]
Outmod1 = 1,
#[doc = "2: PWM output mode: 2 - PWM toggle/reset"]
Outmod2 = 2,
#[doc = "3: PWM output mode: 3 - PWM set/reset"]
Outmod3 = 3,
#[doc = "4: PWM output mode: 4 - toggle"]
Outmod4 = 4,
#[doc = "5: PWM output mode: 5 - Reset"]
Outmod5 = 5,
#[doc = "6: PWM output mode: 6 - PWM toggle/set"]
Outmod6 = 6,
#[doc = "7: PWM output mode: 7 - PWM reset/set"]
Outmod7 = 7,
}
impl From<Outmod> for u8 {
#[inline(always)]
fn from(variant: Outmod) -> Self {
variant as _
}
}
impl crate::FieldSpec for Outmod {
type Ux = u8;
}
impl crate::IsEnum for Outmod {}
#[doc = "Field `OUTMOD` reader - Output mode 2"]
pub type OutmodR = crate::FieldReader<Outmod>;
impl OutmodR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Outmod {
match self.bits {
0 => Outmod::Outmod0,
1 => Outmod::Outmod1,
2 => Outmod::Outmod2,
3 => Outmod::Outmod3,
4 => Outmod::Outmod4,
5 => Outmod::Outmod5,
6 => Outmod::Outmod6,
7 => Outmod::Outmod7,
_ => unreachable!(),
}
}
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn is_outmod_0(&self) -> bool {
*self == Outmod::Outmod0
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn is_outmod_1(&self) -> bool {
*self == Outmod::Outmod1
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn is_outmod_2(&self) -> bool {
*self == Outmod::Outmod2
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn is_outmod_3(&self) -> bool {
*self == Outmod::Outmod3
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn is_outmod_4(&self) -> bool {
*self == Outmod::Outmod4
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn is_outmod_5(&self) -> bool {
*self == Outmod::Outmod5
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn is_outmod_6(&self) -> bool {
*self == Outmod::Outmod6
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn is_outmod_7(&self) -> bool {
*self == Outmod::Outmod7
}
}
#[doc = "Field `OUTMOD` writer - Output mode 2"]
pub type OutmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Outmod, crate::Safe>;
impl<'a, REG> OutmodW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn outmod_0(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod0)
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn outmod_1(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod1)
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn outmod_2(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod2)
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn outmod_3(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod3)
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn outmod_4(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod4)
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn outmod_5(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod5)
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn outmod_6(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod6)
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn outmod_7(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod7)
}
}
#[doc = "Field `CAP` reader - Capture mode: 1 /Compare mode : 0"]
pub type CapR = crate::BitReader;
#[doc = "Field `CAP` writer - Capture mode: 1 /Compare mode : 0"]
pub type CapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Compare latch load source 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Clld {
#[doc = "0: Compare latch load sourec : 0 - immediate"]
Clld0 = 0,
#[doc = "1: Compare latch load sourec : 1 - TBR counts to 0"]
Clld1 = 1,
#[doc = "2: Compare latch load sourec : 2 - up/down"]
Clld2 = 2,
#[doc = "3: Compare latch load sourec : 3 - TBR counts to TBCTL0"]
Clld3 = 3,
}
impl From<Clld> for u8 {
#[inline(always)]
fn from(variant: Clld) -> Self {
variant as _
}
}
impl crate::FieldSpec for Clld {
type Ux = u8;
}
impl crate::IsEnum for Clld {}
#[doc = "Field `CLLD` reader - Compare latch load source 1"]
pub type ClldR = crate::FieldReader<Clld>;
impl ClldR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Clld {
match self.bits {
0 => Clld::Clld0,
1 => Clld::Clld1,
2 => Clld::Clld2,
3 => Clld::Clld3,
_ => unreachable!(),
}
}
#[doc = "Compare latch load sourec : 0 - immediate"]
#[inline(always)]
pub fn is_clld_0(&self) -> bool {
*self == Clld::Clld0
}
#[doc = "Compare latch load sourec : 1 - TBR counts to 0"]
#[inline(always)]
pub fn is_clld_1(&self) -> bool {
*self == Clld::Clld1
}
#[doc = "Compare latch load sourec : 2 - up/down"]
#[inline(always)]
pub fn is_clld_2(&self) -> bool {
*self == Clld::Clld2
}
#[doc = "Compare latch load sourec : 3 - TBR counts to TBCTL0"]
#[inline(always)]
pub fn is_clld_3(&self) -> bool {
*self == Clld::Clld3
}
}
#[doc = "Field `CLLD` writer - Compare latch load source 1"]
pub type ClldW<'a, REG> = crate::FieldWriter<'a, REG, 2, Clld, crate::Safe>;
impl<'a, REG> ClldW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Compare latch load sourec : 0 - immediate"]
#[inline(always)]
pub fn clld_0(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld0)
}
#[doc = "Compare latch load sourec : 1 - TBR counts to 0"]
#[inline(always)]
pub fn clld_1(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld1)
}
#[doc = "Compare latch load sourec : 2 - up/down"]
#[inline(always)]
pub fn clld_2(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld2)
}
#[doc = "Compare latch load sourec : 3 - TBR counts to TBCTL0"]
#[inline(always)]
pub fn clld_3(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld3)
}
}
#[doc = "Field `SCS` reader - Capture sychronize"]
pub type ScsR = crate::BitReader;
#[doc = "Field `SCS` writer - Capture sychronize"]
pub type ScsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture input select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ccis {
#[doc = "0: Capture input select: 0 - CCIxA"]
Ccis0 = 0,
#[doc = "1: Capture input select: 1 - CCIxB"]
Ccis1 = 1,
#[doc = "2: Capture input select: 2 - GND"]
Ccis2 = 2,
#[doc = "3: Capture input select: 3 - Vcc"]
Ccis3 = 3,
}
impl From<Ccis> for u8 {
#[inline(always)]
fn from(variant: Ccis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ccis {
type Ux = u8;
}
impl crate::IsEnum for Ccis {}
#[doc = "Field `CCIS` reader - Capture input select 1"]
pub type CcisR = crate::FieldReader<Ccis>;
impl CcisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccis {
match self.bits {
0 => Ccis::Ccis0,
1 => Ccis::Ccis1,
2 => Ccis::Ccis2,
3 => Ccis::Ccis3,
_ => unreachable!(),
}
}
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn is_ccis_0(&self) -> bool {
*self == Ccis::Ccis0
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn is_ccis_1(&self) -> bool {
*self == Ccis::Ccis1
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn is_ccis_2(&self) -> bool {
*self == Ccis::Ccis2
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn is_ccis_3(&self) -> bool {
*self == Ccis::Ccis3
}
}
#[doc = "Field `CCIS` writer - Capture input select 1"]
pub type CcisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ccis, crate::Safe>;
impl<'a, REG> CcisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn ccis_0(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis0)
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn ccis_1(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis1)
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn ccis_2(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis2)
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn ccis_3(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis3)
}
}
#[doc = "Capture mode 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Capture mode: 0 - disabled"]
Cm0 = 0,
#[doc = "1: Capture mode: 1 - pos. edge"]
Cm1 = 1,
#[doc = "2: Capture mode: 1 - neg. edge"]
Cm2 = 2,
#[doc = "3: Capture mode: 1 - both edges"]
Cm3 = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Capture mode 1"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cm {
match self.bits {
0 => Cm::Cm0,
1 => Cm::Cm1,
2 => Cm::Cm2,
3 => Cm::Cm3,
_ => unreachable!(),
}
}
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn is_cm_0(&self) -> bool {
*self == Cm::Cm0
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn is_cm_1(&self) -> bool {
*self == Cm::Cm1
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn is_cm_2(&self) -> bool {
*self == Cm::Cm2
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn is_cm_3(&self) -> bool {
*self == Cm::Cm3
}
}
#[doc = "Field `CM` writer - Capture mode 1"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm, crate::Safe>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn cm_0(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm0)
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn cm_1(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm1)
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn cm_2(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm2)
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn cm_3(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm3)
}
}
impl R {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&self) -> CcifgR {
CcifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&self) -> CovR {
CovR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&self) -> CciR {
CciR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&self) -> CcieR {
CcieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&self) -> OutmodR {
OutmodR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:10 - Compare latch load source 1"]
#[inline(always)]
pub fn clld(&self) -> ClldR {
ClldR::new(((self.bits >> 9) & 3) as u8)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&self) -> ScsR {
ScsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&self) -> CcisR {
CcisR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&mut self) -> CcifgW<'_, Tb0cctl0Spec> {
CcifgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&mut self) -> CovW<'_, Tb0cctl0Spec> {
CovW::new(self, 1)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&mut self) -> OutW<'_, Tb0cctl0Spec> {
OutW::new(self, 2)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&mut self) -> CciW<'_, Tb0cctl0Spec> {
CciW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&mut self) -> CcieW<'_, Tb0cctl0Spec> {
CcieW::new(self, 4)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&mut self) -> OutmodW<'_, Tb0cctl0Spec> {
OutmodW::new(self, 5)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&mut self) -> CapW<'_, Tb0cctl0Spec> {
CapW::new(self, 8)
}
#[doc = "Bits 9:10 - Compare latch load source 1"]
#[inline(always)]
pub fn clld(&mut self) -> ClldW<'_, Tb0cctl0Spec> {
ClldW::new(self, 9)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&mut self) -> ScsW<'_, Tb0cctl0Spec> {
ScsW::new(self, 11)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&mut self) -> CcisW<'_, Tb0cctl0Spec> {
CcisW::new(self, 12)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<'_, Tb0cctl0Spec> {
CmW::new(self, 14)
}
}
#[doc = "Timer0_B7 Capture/Compare Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0cctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0cctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0cctl0Spec;
impl crate::RegisterSpec for Tb0cctl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0cctl0::R`](R) reader structure"]
impl crate::Readable for Tb0cctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`tb0cctl0::W`](W) writer structure"]
impl crate::Writable for Tb0cctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0CCTL0 to value 0"]
impl crate::Resettable for Tb0cctl0Spec {}
}
#[doc = "TB0CCTL1 (rw) register accessor: Timer0_B7 Capture/Compare Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0cctl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0cctl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0cctl1`] module"]
#[doc(alias = "TB0CCTL1")]
pub type Tb0cctl1 = crate::Reg<tb0cctl1::Tb0cctl1Spec>;
#[doc = "Timer0_B7 Capture/Compare Control 1"]
pub mod tb0cctl1 {
#[doc = "Register `TB0CCTL1` reader"]
pub type R = crate::R<Tb0cctl1Spec>;
#[doc = "Register `TB0CCTL1` writer"]
pub type W = crate::W<Tb0cctl1Spec>;
#[doc = "Field `CCIFG` reader - Capture/compare interrupt flag"]
pub type CcifgR = crate::BitReader;
#[doc = "Field `CCIFG` writer - Capture/compare interrupt flag"]
pub type CcifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COV` reader - Capture/compare overflow flag"]
pub type CovR = crate::BitReader;
#[doc = "Field `COV` writer - Capture/compare overflow flag"]
pub type CovW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OUT` reader - PWM Output signal if output mode 0"]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - PWM Output signal if output mode 0"]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCI` reader - Capture input signal (read)"]
pub type CciR = crate::BitReader;
#[doc = "Field `CCI` writer - Capture input signal (read)"]
pub type CciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCIE` reader - Capture/compare interrupt enable"]
pub type CcieR = crate::BitReader;
#[doc = "Field `CCIE` writer - Capture/compare interrupt enable"]
pub type CcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output mode 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Outmod {
#[doc = "0: PWM output mode: 0 - output only"]
Outmod0 = 0,
#[doc = "1: PWM output mode: 1 - set"]
Outmod1 = 1,
#[doc = "2: PWM output mode: 2 - PWM toggle/reset"]
Outmod2 = 2,
#[doc = "3: PWM output mode: 3 - PWM set/reset"]
Outmod3 = 3,
#[doc = "4: PWM output mode: 4 - toggle"]
Outmod4 = 4,
#[doc = "5: PWM output mode: 5 - Reset"]
Outmod5 = 5,
#[doc = "6: PWM output mode: 6 - PWM toggle/set"]
Outmod6 = 6,
#[doc = "7: PWM output mode: 7 - PWM reset/set"]
Outmod7 = 7,
}
impl From<Outmod> for u8 {
#[inline(always)]
fn from(variant: Outmod) -> Self {
variant as _
}
}
impl crate::FieldSpec for Outmod {
type Ux = u8;
}
impl crate::IsEnum for Outmod {}
#[doc = "Field `OUTMOD` reader - Output mode 2"]
pub type OutmodR = crate::FieldReader<Outmod>;
impl OutmodR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Outmod {
match self.bits {
0 => Outmod::Outmod0,
1 => Outmod::Outmod1,
2 => Outmod::Outmod2,
3 => Outmod::Outmod3,
4 => Outmod::Outmod4,
5 => Outmod::Outmod5,
6 => Outmod::Outmod6,
7 => Outmod::Outmod7,
_ => unreachable!(),
}
}
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn is_outmod_0(&self) -> bool {
*self == Outmod::Outmod0
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn is_outmod_1(&self) -> bool {
*self == Outmod::Outmod1
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn is_outmod_2(&self) -> bool {
*self == Outmod::Outmod2
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn is_outmod_3(&self) -> bool {
*self == Outmod::Outmod3
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn is_outmod_4(&self) -> bool {
*self == Outmod::Outmod4
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn is_outmod_5(&self) -> bool {
*self == Outmod::Outmod5
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn is_outmod_6(&self) -> bool {
*self == Outmod::Outmod6
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn is_outmod_7(&self) -> bool {
*self == Outmod::Outmod7
}
}
#[doc = "Field `OUTMOD` writer - Output mode 2"]
pub type OutmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Outmod, crate::Safe>;
impl<'a, REG> OutmodW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn outmod_0(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod0)
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn outmod_1(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod1)
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn outmod_2(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod2)
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn outmod_3(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod3)
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn outmod_4(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod4)
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn outmod_5(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod5)
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn outmod_6(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod6)
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn outmod_7(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod7)
}
}
#[doc = "Field `CAP` reader - Capture mode: 1 /Compare mode : 0"]
pub type CapR = crate::BitReader;
#[doc = "Field `CAP` writer - Capture mode: 1 /Compare mode : 0"]
pub type CapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Compare latch load source 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Clld {
#[doc = "0: Compare latch load sourec : 0 - immediate"]
Clld0 = 0,
#[doc = "1: Compare latch load sourec : 1 - TBR counts to 0"]
Clld1 = 1,
#[doc = "2: Compare latch load sourec : 2 - up/down"]
Clld2 = 2,
#[doc = "3: Compare latch load sourec : 3 - TBR counts to TBCTL0"]
Clld3 = 3,
}
impl From<Clld> for u8 {
#[inline(always)]
fn from(variant: Clld) -> Self {
variant as _
}
}
impl crate::FieldSpec for Clld {
type Ux = u8;
}
impl crate::IsEnum for Clld {}
#[doc = "Field `CLLD` reader - Compare latch load source 1"]
pub type ClldR = crate::FieldReader<Clld>;
impl ClldR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Clld {
match self.bits {
0 => Clld::Clld0,
1 => Clld::Clld1,
2 => Clld::Clld2,
3 => Clld::Clld3,
_ => unreachable!(),
}
}
#[doc = "Compare latch load sourec : 0 - immediate"]
#[inline(always)]
pub fn is_clld_0(&self) -> bool {
*self == Clld::Clld0
}
#[doc = "Compare latch load sourec : 1 - TBR counts to 0"]
#[inline(always)]
pub fn is_clld_1(&self) -> bool {
*self == Clld::Clld1
}
#[doc = "Compare latch load sourec : 2 - up/down"]
#[inline(always)]
pub fn is_clld_2(&self) -> bool {
*self == Clld::Clld2
}
#[doc = "Compare latch load sourec : 3 - TBR counts to TBCTL0"]
#[inline(always)]
pub fn is_clld_3(&self) -> bool {
*self == Clld::Clld3
}
}
#[doc = "Field `CLLD` writer - Compare latch load source 1"]
pub type ClldW<'a, REG> = crate::FieldWriter<'a, REG, 2, Clld, crate::Safe>;
impl<'a, REG> ClldW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Compare latch load sourec : 0 - immediate"]
#[inline(always)]
pub fn clld_0(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld0)
}
#[doc = "Compare latch load sourec : 1 - TBR counts to 0"]
#[inline(always)]
pub fn clld_1(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld1)
}
#[doc = "Compare latch load sourec : 2 - up/down"]
#[inline(always)]
pub fn clld_2(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld2)
}
#[doc = "Compare latch load sourec : 3 - TBR counts to TBCTL0"]
#[inline(always)]
pub fn clld_3(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld3)
}
}
#[doc = "Field `SCS` reader - Capture sychronize"]
pub type ScsR = crate::BitReader;
#[doc = "Field `SCS` writer - Capture sychronize"]
pub type ScsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture input select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ccis {
#[doc = "0: Capture input select: 0 - CCIxA"]
Ccis0 = 0,
#[doc = "1: Capture input select: 1 - CCIxB"]
Ccis1 = 1,
#[doc = "2: Capture input select: 2 - GND"]
Ccis2 = 2,
#[doc = "3: Capture input select: 3 - Vcc"]
Ccis3 = 3,
}
impl From<Ccis> for u8 {
#[inline(always)]
fn from(variant: Ccis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ccis {
type Ux = u8;
}
impl crate::IsEnum for Ccis {}
#[doc = "Field `CCIS` reader - Capture input select 1"]
pub type CcisR = crate::FieldReader<Ccis>;
impl CcisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccis {
match self.bits {
0 => Ccis::Ccis0,
1 => Ccis::Ccis1,
2 => Ccis::Ccis2,
3 => Ccis::Ccis3,
_ => unreachable!(),
}
}
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn is_ccis_0(&self) -> bool {
*self == Ccis::Ccis0
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn is_ccis_1(&self) -> bool {
*self == Ccis::Ccis1
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn is_ccis_2(&self) -> bool {
*self == Ccis::Ccis2
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn is_ccis_3(&self) -> bool {
*self == Ccis::Ccis3
}
}
#[doc = "Field `CCIS` writer - Capture input select 1"]
pub type CcisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ccis, crate::Safe>;
impl<'a, REG> CcisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn ccis_0(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis0)
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn ccis_1(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis1)
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn ccis_2(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis2)
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn ccis_3(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis3)
}
}
#[doc = "Capture mode 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Capture mode: 0 - disabled"]
Cm0 = 0,
#[doc = "1: Capture mode: 1 - pos. edge"]
Cm1 = 1,
#[doc = "2: Capture mode: 1 - neg. edge"]
Cm2 = 2,
#[doc = "3: Capture mode: 1 - both edges"]
Cm3 = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Capture mode 1"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cm {
match self.bits {
0 => Cm::Cm0,
1 => Cm::Cm1,
2 => Cm::Cm2,
3 => Cm::Cm3,
_ => unreachable!(),
}
}
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn is_cm_0(&self) -> bool {
*self == Cm::Cm0
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn is_cm_1(&self) -> bool {
*self == Cm::Cm1
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn is_cm_2(&self) -> bool {
*self == Cm::Cm2
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn is_cm_3(&self) -> bool {
*self == Cm::Cm3
}
}
#[doc = "Field `CM` writer - Capture mode 1"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm, crate::Safe>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn cm_0(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm0)
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn cm_1(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm1)
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn cm_2(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm2)
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn cm_3(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm3)
}
}
impl R {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&self) -> CcifgR {
CcifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&self) -> CovR {
CovR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&self) -> CciR {
CciR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&self) -> CcieR {
CcieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&self) -> OutmodR {
OutmodR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:10 - Compare latch load source 1"]
#[inline(always)]
pub fn clld(&self) -> ClldR {
ClldR::new(((self.bits >> 9) & 3) as u8)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&self) -> ScsR {
ScsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&self) -> CcisR {
CcisR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&mut self) -> CcifgW<'_, Tb0cctl1Spec> {
CcifgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&mut self) -> CovW<'_, Tb0cctl1Spec> {
CovW::new(self, 1)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&mut self) -> OutW<'_, Tb0cctl1Spec> {
OutW::new(self, 2)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&mut self) -> CciW<'_, Tb0cctl1Spec> {
CciW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&mut self) -> CcieW<'_, Tb0cctl1Spec> {
CcieW::new(self, 4)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&mut self) -> OutmodW<'_, Tb0cctl1Spec> {
OutmodW::new(self, 5)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&mut self) -> CapW<'_, Tb0cctl1Spec> {
CapW::new(self, 8)
}
#[doc = "Bits 9:10 - Compare latch load source 1"]
#[inline(always)]
pub fn clld(&mut self) -> ClldW<'_, Tb0cctl1Spec> {
ClldW::new(self, 9)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&mut self) -> ScsW<'_, Tb0cctl1Spec> {
ScsW::new(self, 11)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&mut self) -> CcisW<'_, Tb0cctl1Spec> {
CcisW::new(self, 12)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<'_, Tb0cctl1Spec> {
CmW::new(self, 14)
}
}
#[doc = "Timer0_B7 Capture/Compare Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0cctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0cctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0cctl1Spec;
impl crate::RegisterSpec for Tb0cctl1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0cctl1::R`](R) reader structure"]
impl crate::Readable for Tb0cctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`tb0cctl1::W`](W) writer structure"]
impl crate::Writable for Tb0cctl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0CCTL1 to value 0"]
impl crate::Resettable for Tb0cctl1Spec {}
}
#[doc = "TB0CCTL2 (rw) register accessor: Timer0_B7 Capture/Compare Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0cctl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0cctl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0cctl2`] module"]
#[doc(alias = "TB0CCTL2")]
pub type Tb0cctl2 = crate::Reg<tb0cctl2::Tb0cctl2Spec>;
#[doc = "Timer0_B7 Capture/Compare Control 2"]
pub mod tb0cctl2 {
#[doc = "Register `TB0CCTL2` reader"]
pub type R = crate::R<Tb0cctl2Spec>;
#[doc = "Register `TB0CCTL2` writer"]
pub type W = crate::W<Tb0cctl2Spec>;
#[doc = "Field `CCIFG` reader - Capture/compare interrupt flag"]
pub type CcifgR = crate::BitReader;
#[doc = "Field `CCIFG` writer - Capture/compare interrupt flag"]
pub type CcifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COV` reader - Capture/compare overflow flag"]
pub type CovR = crate::BitReader;
#[doc = "Field `COV` writer - Capture/compare overflow flag"]
pub type CovW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OUT` reader - PWM Output signal if output mode 0"]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - PWM Output signal if output mode 0"]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCI` reader - Capture input signal (read)"]
pub type CciR = crate::BitReader;
#[doc = "Field `CCI` writer - Capture input signal (read)"]
pub type CciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCIE` reader - Capture/compare interrupt enable"]
pub type CcieR = crate::BitReader;
#[doc = "Field `CCIE` writer - Capture/compare interrupt enable"]
pub type CcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output mode 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Outmod {
#[doc = "0: PWM output mode: 0 - output only"]
Outmod0 = 0,
#[doc = "1: PWM output mode: 1 - set"]
Outmod1 = 1,
#[doc = "2: PWM output mode: 2 - PWM toggle/reset"]
Outmod2 = 2,
#[doc = "3: PWM output mode: 3 - PWM set/reset"]
Outmod3 = 3,
#[doc = "4: PWM output mode: 4 - toggle"]
Outmod4 = 4,
#[doc = "5: PWM output mode: 5 - Reset"]
Outmod5 = 5,
#[doc = "6: PWM output mode: 6 - PWM toggle/set"]
Outmod6 = 6,
#[doc = "7: PWM output mode: 7 - PWM reset/set"]
Outmod7 = 7,
}
impl From<Outmod> for u8 {
#[inline(always)]
fn from(variant: Outmod) -> Self {
variant as _
}
}
impl crate::FieldSpec for Outmod {
type Ux = u8;
}
impl crate::IsEnum for Outmod {}
#[doc = "Field `OUTMOD` reader - Output mode 2"]
pub type OutmodR = crate::FieldReader<Outmod>;
impl OutmodR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Outmod {
match self.bits {
0 => Outmod::Outmod0,
1 => Outmod::Outmod1,
2 => Outmod::Outmod2,
3 => Outmod::Outmod3,
4 => Outmod::Outmod4,
5 => Outmod::Outmod5,
6 => Outmod::Outmod6,
7 => Outmod::Outmod7,
_ => unreachable!(),
}
}
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn is_outmod_0(&self) -> bool {
*self == Outmod::Outmod0
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn is_outmod_1(&self) -> bool {
*self == Outmod::Outmod1
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn is_outmod_2(&self) -> bool {
*self == Outmod::Outmod2
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn is_outmod_3(&self) -> bool {
*self == Outmod::Outmod3
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn is_outmod_4(&self) -> bool {
*self == Outmod::Outmod4
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn is_outmod_5(&self) -> bool {
*self == Outmod::Outmod5
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn is_outmod_6(&self) -> bool {
*self == Outmod::Outmod6
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn is_outmod_7(&self) -> bool {
*self == Outmod::Outmod7
}
}
#[doc = "Field `OUTMOD` writer - Output mode 2"]
pub type OutmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Outmod, crate::Safe>;
impl<'a, REG> OutmodW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn outmod_0(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod0)
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn outmod_1(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod1)
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn outmod_2(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod2)
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn outmod_3(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod3)
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn outmod_4(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod4)
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn outmod_5(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod5)
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn outmod_6(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod6)
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn outmod_7(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod7)
}
}
#[doc = "Field `CAP` reader - Capture mode: 1 /Compare mode : 0"]
pub type CapR = crate::BitReader;
#[doc = "Field `CAP` writer - Capture mode: 1 /Compare mode : 0"]
pub type CapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Compare latch load source 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Clld {
#[doc = "0: Compare latch load sourec : 0 - immediate"]
Clld0 = 0,
#[doc = "1: Compare latch load sourec : 1 - TBR counts to 0"]
Clld1 = 1,
#[doc = "2: Compare latch load sourec : 2 - up/down"]
Clld2 = 2,
#[doc = "3: Compare latch load sourec : 3 - TBR counts to TBCTL0"]
Clld3 = 3,
}
impl From<Clld> for u8 {
#[inline(always)]
fn from(variant: Clld) -> Self {
variant as _
}
}
impl crate::FieldSpec for Clld {
type Ux = u8;
}
impl crate::IsEnum for Clld {}
#[doc = "Field `CLLD` reader - Compare latch load source 1"]
pub type ClldR = crate::FieldReader<Clld>;
impl ClldR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Clld {
match self.bits {
0 => Clld::Clld0,
1 => Clld::Clld1,
2 => Clld::Clld2,
3 => Clld::Clld3,
_ => unreachable!(),
}
}
#[doc = "Compare latch load sourec : 0 - immediate"]
#[inline(always)]
pub fn is_clld_0(&self) -> bool {
*self == Clld::Clld0
}
#[doc = "Compare latch load sourec : 1 - TBR counts to 0"]
#[inline(always)]
pub fn is_clld_1(&self) -> bool {
*self == Clld::Clld1
}
#[doc = "Compare latch load sourec : 2 - up/down"]
#[inline(always)]
pub fn is_clld_2(&self) -> bool {
*self == Clld::Clld2
}
#[doc = "Compare latch load sourec : 3 - TBR counts to TBCTL0"]
#[inline(always)]
pub fn is_clld_3(&self) -> bool {
*self == Clld::Clld3
}
}
#[doc = "Field `CLLD` writer - Compare latch load source 1"]
pub type ClldW<'a, REG> = crate::FieldWriter<'a, REG, 2, Clld, crate::Safe>;
impl<'a, REG> ClldW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Compare latch load sourec : 0 - immediate"]
#[inline(always)]
pub fn clld_0(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld0)
}
#[doc = "Compare latch load sourec : 1 - TBR counts to 0"]
#[inline(always)]
pub fn clld_1(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld1)
}
#[doc = "Compare latch load sourec : 2 - up/down"]
#[inline(always)]
pub fn clld_2(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld2)
}
#[doc = "Compare latch load sourec : 3 - TBR counts to TBCTL0"]
#[inline(always)]
pub fn clld_3(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld3)
}
}
#[doc = "Field `SCS` reader - Capture sychronize"]
pub type ScsR = crate::BitReader;
#[doc = "Field `SCS` writer - Capture sychronize"]
pub type ScsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture input select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ccis {
#[doc = "0: Capture input select: 0 - CCIxA"]
Ccis0 = 0,
#[doc = "1: Capture input select: 1 - CCIxB"]
Ccis1 = 1,
#[doc = "2: Capture input select: 2 - GND"]
Ccis2 = 2,
#[doc = "3: Capture input select: 3 - Vcc"]
Ccis3 = 3,
}
impl From<Ccis> for u8 {
#[inline(always)]
fn from(variant: Ccis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ccis {
type Ux = u8;
}
impl crate::IsEnum for Ccis {}
#[doc = "Field `CCIS` reader - Capture input select 1"]
pub type CcisR = crate::FieldReader<Ccis>;
impl CcisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccis {
match self.bits {
0 => Ccis::Ccis0,
1 => Ccis::Ccis1,
2 => Ccis::Ccis2,
3 => Ccis::Ccis3,
_ => unreachable!(),
}
}
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn is_ccis_0(&self) -> bool {
*self == Ccis::Ccis0
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn is_ccis_1(&self) -> bool {
*self == Ccis::Ccis1
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn is_ccis_2(&self) -> bool {
*self == Ccis::Ccis2
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn is_ccis_3(&self) -> bool {
*self == Ccis::Ccis3
}
}
#[doc = "Field `CCIS` writer - Capture input select 1"]
pub type CcisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ccis, crate::Safe>;
impl<'a, REG> CcisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn ccis_0(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis0)
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn ccis_1(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis1)
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn ccis_2(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis2)
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn ccis_3(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis3)
}
}
#[doc = "Capture mode 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Capture mode: 0 - disabled"]
Cm0 = 0,
#[doc = "1: Capture mode: 1 - pos. edge"]
Cm1 = 1,
#[doc = "2: Capture mode: 1 - neg. edge"]
Cm2 = 2,
#[doc = "3: Capture mode: 1 - both edges"]
Cm3 = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Capture mode 1"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cm {
match self.bits {
0 => Cm::Cm0,
1 => Cm::Cm1,
2 => Cm::Cm2,
3 => Cm::Cm3,
_ => unreachable!(),
}
}
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn is_cm_0(&self) -> bool {
*self == Cm::Cm0
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn is_cm_1(&self) -> bool {
*self == Cm::Cm1
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn is_cm_2(&self) -> bool {
*self == Cm::Cm2
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn is_cm_3(&self) -> bool {
*self == Cm::Cm3
}
}
#[doc = "Field `CM` writer - Capture mode 1"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm, crate::Safe>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn cm_0(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm0)
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn cm_1(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm1)
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn cm_2(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm2)
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn cm_3(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm3)
}
}
impl R {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&self) -> CcifgR {
CcifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&self) -> CovR {
CovR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&self) -> CciR {
CciR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&self) -> CcieR {
CcieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&self) -> OutmodR {
OutmodR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:10 - Compare latch load source 1"]
#[inline(always)]
pub fn clld(&self) -> ClldR {
ClldR::new(((self.bits >> 9) & 3) as u8)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&self) -> ScsR {
ScsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&self) -> CcisR {
CcisR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&mut self) -> CcifgW<'_, Tb0cctl2Spec> {
CcifgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&mut self) -> CovW<'_, Tb0cctl2Spec> {
CovW::new(self, 1)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&mut self) -> OutW<'_, Tb0cctl2Spec> {
OutW::new(self, 2)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&mut self) -> CciW<'_, Tb0cctl2Spec> {
CciW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&mut self) -> CcieW<'_, Tb0cctl2Spec> {
CcieW::new(self, 4)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&mut self) -> OutmodW<'_, Tb0cctl2Spec> {
OutmodW::new(self, 5)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&mut self) -> CapW<'_, Tb0cctl2Spec> {
CapW::new(self, 8)
}
#[doc = "Bits 9:10 - Compare latch load source 1"]
#[inline(always)]
pub fn clld(&mut self) -> ClldW<'_, Tb0cctl2Spec> {
ClldW::new(self, 9)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&mut self) -> ScsW<'_, Tb0cctl2Spec> {
ScsW::new(self, 11)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&mut self) -> CcisW<'_, Tb0cctl2Spec> {
CcisW::new(self, 12)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<'_, Tb0cctl2Spec> {
CmW::new(self, 14)
}
}
#[doc = "Timer0_B7 Capture/Compare Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0cctl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0cctl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0cctl2Spec;
impl crate::RegisterSpec for Tb0cctl2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0cctl2::R`](R) reader structure"]
impl crate::Readable for Tb0cctl2Spec {}
#[doc = "`write(|w| ..)` method takes [`tb0cctl2::W`](W) writer structure"]
impl crate::Writable for Tb0cctl2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0CCTL2 to value 0"]
impl crate::Resettable for Tb0cctl2Spec {}
}
#[doc = "TB0CCTL3 (rw) register accessor: Timer0_B7 Capture/Compare Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0cctl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0cctl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0cctl3`] module"]
#[doc(alias = "TB0CCTL3")]
pub type Tb0cctl3 = crate::Reg<tb0cctl3::Tb0cctl3Spec>;
#[doc = "Timer0_B7 Capture/Compare Control 3"]
pub mod tb0cctl3 {
#[doc = "Register `TB0CCTL3` reader"]
pub type R = crate::R<Tb0cctl3Spec>;
#[doc = "Register `TB0CCTL3` writer"]
pub type W = crate::W<Tb0cctl3Spec>;
#[doc = "Field `CCIFG` reader - Capture/compare interrupt flag"]
pub type CcifgR = crate::BitReader;
#[doc = "Field `CCIFG` writer - Capture/compare interrupt flag"]
pub type CcifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COV` reader - Capture/compare overflow flag"]
pub type CovR = crate::BitReader;
#[doc = "Field `COV` writer - Capture/compare overflow flag"]
pub type CovW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OUT` reader - PWM Output signal if output mode 0"]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - PWM Output signal if output mode 0"]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCI` reader - Capture input signal (read)"]
pub type CciR = crate::BitReader;
#[doc = "Field `CCI` writer - Capture input signal (read)"]
pub type CciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCIE` reader - Capture/compare interrupt enable"]
pub type CcieR = crate::BitReader;
#[doc = "Field `CCIE` writer - Capture/compare interrupt enable"]
pub type CcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output mode 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Outmod {
#[doc = "0: PWM output mode: 0 - output only"]
Outmod0 = 0,
#[doc = "1: PWM output mode: 1 - set"]
Outmod1 = 1,
#[doc = "2: PWM output mode: 2 - PWM toggle/reset"]
Outmod2 = 2,
#[doc = "3: PWM output mode: 3 - PWM set/reset"]
Outmod3 = 3,
#[doc = "4: PWM output mode: 4 - toggle"]
Outmod4 = 4,
#[doc = "5: PWM output mode: 5 - Reset"]
Outmod5 = 5,
#[doc = "6: PWM output mode: 6 - PWM toggle/set"]
Outmod6 = 6,
#[doc = "7: PWM output mode: 7 - PWM reset/set"]
Outmod7 = 7,
}
impl From<Outmod> for u8 {
#[inline(always)]
fn from(variant: Outmod) -> Self {
variant as _
}
}
impl crate::FieldSpec for Outmod {
type Ux = u8;
}
impl crate::IsEnum for Outmod {}
#[doc = "Field `OUTMOD` reader - Output mode 2"]
pub type OutmodR = crate::FieldReader<Outmod>;
impl OutmodR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Outmod {
match self.bits {
0 => Outmod::Outmod0,
1 => Outmod::Outmod1,
2 => Outmod::Outmod2,
3 => Outmod::Outmod3,
4 => Outmod::Outmod4,
5 => Outmod::Outmod5,
6 => Outmod::Outmod6,
7 => Outmod::Outmod7,
_ => unreachable!(),
}
}
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn is_outmod_0(&self) -> bool {
*self == Outmod::Outmod0
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn is_outmod_1(&self) -> bool {
*self == Outmod::Outmod1
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn is_outmod_2(&self) -> bool {
*self == Outmod::Outmod2
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn is_outmod_3(&self) -> bool {
*self == Outmod::Outmod3
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn is_outmod_4(&self) -> bool {
*self == Outmod::Outmod4
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn is_outmod_5(&self) -> bool {
*self == Outmod::Outmod5
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn is_outmod_6(&self) -> bool {
*self == Outmod::Outmod6
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn is_outmod_7(&self) -> bool {
*self == Outmod::Outmod7
}
}
#[doc = "Field `OUTMOD` writer - Output mode 2"]
pub type OutmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Outmod, crate::Safe>;
impl<'a, REG> OutmodW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn outmod_0(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod0)
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn outmod_1(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod1)
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn outmod_2(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod2)
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn outmod_3(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod3)
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn outmod_4(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod4)
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn outmod_5(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod5)
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn outmod_6(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod6)
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn outmod_7(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod7)
}
}
#[doc = "Field `CAP` reader - Capture mode: 1 /Compare mode : 0"]
pub type CapR = crate::BitReader;
#[doc = "Field `CAP` writer - Capture mode: 1 /Compare mode : 0"]
pub type CapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Compare latch load source 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Clld {
#[doc = "0: Compare latch load sourec : 0 - immediate"]
Clld0 = 0,
#[doc = "1: Compare latch load sourec : 1 - TBR counts to 0"]
Clld1 = 1,
#[doc = "2: Compare latch load sourec : 2 - up/down"]
Clld2 = 2,
#[doc = "3: Compare latch load sourec : 3 - TBR counts to TBCTL0"]
Clld3 = 3,
}
impl From<Clld> for u8 {
#[inline(always)]
fn from(variant: Clld) -> Self {
variant as _
}
}
impl crate::FieldSpec for Clld {
type Ux = u8;
}
impl crate::IsEnum for Clld {}
#[doc = "Field `CLLD` reader - Compare latch load source 1"]
pub type ClldR = crate::FieldReader<Clld>;
impl ClldR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Clld {
match self.bits {
0 => Clld::Clld0,
1 => Clld::Clld1,
2 => Clld::Clld2,
3 => Clld::Clld3,
_ => unreachable!(),
}
}
#[doc = "Compare latch load sourec : 0 - immediate"]
#[inline(always)]
pub fn is_clld_0(&self) -> bool {
*self == Clld::Clld0
}
#[doc = "Compare latch load sourec : 1 - TBR counts to 0"]
#[inline(always)]
pub fn is_clld_1(&self) -> bool {
*self == Clld::Clld1
}
#[doc = "Compare latch load sourec : 2 - up/down"]
#[inline(always)]
pub fn is_clld_2(&self) -> bool {
*self == Clld::Clld2
}
#[doc = "Compare latch load sourec : 3 - TBR counts to TBCTL0"]
#[inline(always)]
pub fn is_clld_3(&self) -> bool {
*self == Clld::Clld3
}
}
#[doc = "Field `CLLD` writer - Compare latch load source 1"]
pub type ClldW<'a, REG> = crate::FieldWriter<'a, REG, 2, Clld, crate::Safe>;
impl<'a, REG> ClldW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Compare latch load sourec : 0 - immediate"]
#[inline(always)]
pub fn clld_0(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld0)
}
#[doc = "Compare latch load sourec : 1 - TBR counts to 0"]
#[inline(always)]
pub fn clld_1(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld1)
}
#[doc = "Compare latch load sourec : 2 - up/down"]
#[inline(always)]
pub fn clld_2(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld2)
}
#[doc = "Compare latch load sourec : 3 - TBR counts to TBCTL0"]
#[inline(always)]
pub fn clld_3(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld3)
}
}
#[doc = "Field `SCS` reader - Capture sychronize"]
pub type ScsR = crate::BitReader;
#[doc = "Field `SCS` writer - Capture sychronize"]
pub type ScsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture input select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ccis {
#[doc = "0: Capture input select: 0 - CCIxA"]
Ccis0 = 0,
#[doc = "1: Capture input select: 1 - CCIxB"]
Ccis1 = 1,
#[doc = "2: Capture input select: 2 - GND"]
Ccis2 = 2,
#[doc = "3: Capture input select: 3 - Vcc"]
Ccis3 = 3,
}
impl From<Ccis> for u8 {
#[inline(always)]
fn from(variant: Ccis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ccis {
type Ux = u8;
}
impl crate::IsEnum for Ccis {}
#[doc = "Field `CCIS` reader - Capture input select 1"]
pub type CcisR = crate::FieldReader<Ccis>;
impl CcisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccis {
match self.bits {
0 => Ccis::Ccis0,
1 => Ccis::Ccis1,
2 => Ccis::Ccis2,
3 => Ccis::Ccis3,
_ => unreachable!(),
}
}
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn is_ccis_0(&self) -> bool {
*self == Ccis::Ccis0
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn is_ccis_1(&self) -> bool {
*self == Ccis::Ccis1
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn is_ccis_2(&self) -> bool {
*self == Ccis::Ccis2
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn is_ccis_3(&self) -> bool {
*self == Ccis::Ccis3
}
}
#[doc = "Field `CCIS` writer - Capture input select 1"]
pub type CcisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ccis, crate::Safe>;
impl<'a, REG> CcisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn ccis_0(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis0)
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn ccis_1(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis1)
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn ccis_2(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis2)
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn ccis_3(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis3)
}
}
#[doc = "Capture mode 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Capture mode: 0 - disabled"]
Cm0 = 0,
#[doc = "1: Capture mode: 1 - pos. edge"]
Cm1 = 1,
#[doc = "2: Capture mode: 1 - neg. edge"]
Cm2 = 2,
#[doc = "3: Capture mode: 1 - both edges"]
Cm3 = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Capture mode 1"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cm {
match self.bits {
0 => Cm::Cm0,
1 => Cm::Cm1,
2 => Cm::Cm2,
3 => Cm::Cm3,
_ => unreachable!(),
}
}
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn is_cm_0(&self) -> bool {
*self == Cm::Cm0
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn is_cm_1(&self) -> bool {
*self == Cm::Cm1
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn is_cm_2(&self) -> bool {
*self == Cm::Cm2
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn is_cm_3(&self) -> bool {
*self == Cm::Cm3
}
}
#[doc = "Field `CM` writer - Capture mode 1"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm, crate::Safe>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn cm_0(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm0)
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn cm_1(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm1)
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn cm_2(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm2)
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn cm_3(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm3)
}
}
impl R {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&self) -> CcifgR {
CcifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&self) -> CovR {
CovR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&self) -> CciR {
CciR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&self) -> CcieR {
CcieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&self) -> OutmodR {
OutmodR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:10 - Compare latch load source 1"]
#[inline(always)]
pub fn clld(&self) -> ClldR {
ClldR::new(((self.bits >> 9) & 3) as u8)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&self) -> ScsR {
ScsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&self) -> CcisR {
CcisR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&mut self) -> CcifgW<'_, Tb0cctl3Spec> {
CcifgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&mut self) -> CovW<'_, Tb0cctl3Spec> {
CovW::new(self, 1)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&mut self) -> OutW<'_, Tb0cctl3Spec> {
OutW::new(self, 2)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&mut self) -> CciW<'_, Tb0cctl3Spec> {
CciW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&mut self) -> CcieW<'_, Tb0cctl3Spec> {
CcieW::new(self, 4)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&mut self) -> OutmodW<'_, Tb0cctl3Spec> {
OutmodW::new(self, 5)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&mut self) -> CapW<'_, Tb0cctl3Spec> {
CapW::new(self, 8)
}
#[doc = "Bits 9:10 - Compare latch load source 1"]
#[inline(always)]
pub fn clld(&mut self) -> ClldW<'_, Tb0cctl3Spec> {
ClldW::new(self, 9)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&mut self) -> ScsW<'_, Tb0cctl3Spec> {
ScsW::new(self, 11)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&mut self) -> CcisW<'_, Tb0cctl3Spec> {
CcisW::new(self, 12)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<'_, Tb0cctl3Spec> {
CmW::new(self, 14)
}
}
#[doc = "Timer0_B7 Capture/Compare Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0cctl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0cctl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0cctl3Spec;
impl crate::RegisterSpec for Tb0cctl3Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0cctl3::R`](R) reader structure"]
impl crate::Readable for Tb0cctl3Spec {}
#[doc = "`write(|w| ..)` method takes [`tb0cctl3::W`](W) writer structure"]
impl crate::Writable for Tb0cctl3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0CCTL3 to value 0"]
impl crate::Resettable for Tb0cctl3Spec {}
}
#[doc = "TB0CCTL4 (rw) register accessor: Timer0_B7 Capture/Compare Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0cctl4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0cctl4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0cctl4`] module"]
#[doc(alias = "TB0CCTL4")]
pub type Tb0cctl4 = crate::Reg<tb0cctl4::Tb0cctl4Spec>;
#[doc = "Timer0_B7 Capture/Compare Control 4"]
pub mod tb0cctl4 {
#[doc = "Register `TB0CCTL4` reader"]
pub type R = crate::R<Tb0cctl4Spec>;
#[doc = "Register `TB0CCTL4` writer"]
pub type W = crate::W<Tb0cctl4Spec>;
#[doc = "Field `CCIFG` reader - Capture/compare interrupt flag"]
pub type CcifgR = crate::BitReader;
#[doc = "Field `CCIFG` writer - Capture/compare interrupt flag"]
pub type CcifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COV` reader - Capture/compare overflow flag"]
pub type CovR = crate::BitReader;
#[doc = "Field `COV` writer - Capture/compare overflow flag"]
pub type CovW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OUT` reader - PWM Output signal if output mode 0"]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - PWM Output signal if output mode 0"]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCI` reader - Capture input signal (read)"]
pub type CciR = crate::BitReader;
#[doc = "Field `CCI` writer - Capture input signal (read)"]
pub type CciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCIE` reader - Capture/compare interrupt enable"]
pub type CcieR = crate::BitReader;
#[doc = "Field `CCIE` writer - Capture/compare interrupt enable"]
pub type CcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output mode 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Outmod {
#[doc = "0: PWM output mode: 0 - output only"]
Outmod0 = 0,
#[doc = "1: PWM output mode: 1 - set"]
Outmod1 = 1,
#[doc = "2: PWM output mode: 2 - PWM toggle/reset"]
Outmod2 = 2,
#[doc = "3: PWM output mode: 3 - PWM set/reset"]
Outmod3 = 3,
#[doc = "4: PWM output mode: 4 - toggle"]
Outmod4 = 4,
#[doc = "5: PWM output mode: 5 - Reset"]
Outmod5 = 5,
#[doc = "6: PWM output mode: 6 - PWM toggle/set"]
Outmod6 = 6,
#[doc = "7: PWM output mode: 7 - PWM reset/set"]
Outmod7 = 7,
}
impl From<Outmod> for u8 {
#[inline(always)]
fn from(variant: Outmod) -> Self {
variant as _
}
}
impl crate::FieldSpec for Outmod {
type Ux = u8;
}
impl crate::IsEnum for Outmod {}
#[doc = "Field `OUTMOD` reader - Output mode 2"]
pub type OutmodR = crate::FieldReader<Outmod>;
impl OutmodR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Outmod {
match self.bits {
0 => Outmod::Outmod0,
1 => Outmod::Outmod1,
2 => Outmod::Outmod2,
3 => Outmod::Outmod3,
4 => Outmod::Outmod4,
5 => Outmod::Outmod5,
6 => Outmod::Outmod6,
7 => Outmod::Outmod7,
_ => unreachable!(),
}
}
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn is_outmod_0(&self) -> bool {
*self == Outmod::Outmod0
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn is_outmod_1(&self) -> bool {
*self == Outmod::Outmod1
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn is_outmod_2(&self) -> bool {
*self == Outmod::Outmod2
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn is_outmod_3(&self) -> bool {
*self == Outmod::Outmod3
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn is_outmod_4(&self) -> bool {
*self == Outmod::Outmod4
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn is_outmod_5(&self) -> bool {
*self == Outmod::Outmod5
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn is_outmod_6(&self) -> bool {
*self == Outmod::Outmod6
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn is_outmod_7(&self) -> bool {
*self == Outmod::Outmod7
}
}
#[doc = "Field `OUTMOD` writer - Output mode 2"]
pub type OutmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Outmod, crate::Safe>;
impl<'a, REG> OutmodW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn outmod_0(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod0)
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn outmod_1(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod1)
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn outmod_2(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod2)
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn outmod_3(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod3)
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn outmod_4(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod4)
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn outmod_5(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod5)
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn outmod_6(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod6)
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn outmod_7(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod7)
}
}
#[doc = "Field `CAP` reader - Capture mode: 1 /Compare mode : 0"]
pub type CapR = crate::BitReader;
#[doc = "Field `CAP` writer - Capture mode: 1 /Compare mode : 0"]
pub type CapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Compare latch load source 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Clld {
#[doc = "0: Compare latch load sourec : 0 - immediate"]
Clld0 = 0,
#[doc = "1: Compare latch load sourec : 1 - TBR counts to 0"]
Clld1 = 1,
#[doc = "2: Compare latch load sourec : 2 - up/down"]
Clld2 = 2,
#[doc = "3: Compare latch load sourec : 3 - TBR counts to TBCTL0"]
Clld3 = 3,
}
impl From<Clld> for u8 {
#[inline(always)]
fn from(variant: Clld) -> Self {
variant as _
}
}
impl crate::FieldSpec for Clld {
type Ux = u8;
}
impl crate::IsEnum for Clld {}
#[doc = "Field `CLLD` reader - Compare latch load source 1"]
pub type ClldR = crate::FieldReader<Clld>;
impl ClldR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Clld {
match self.bits {
0 => Clld::Clld0,
1 => Clld::Clld1,
2 => Clld::Clld2,
3 => Clld::Clld3,
_ => unreachable!(),
}
}
#[doc = "Compare latch load sourec : 0 - immediate"]
#[inline(always)]
pub fn is_clld_0(&self) -> bool {
*self == Clld::Clld0
}
#[doc = "Compare latch load sourec : 1 - TBR counts to 0"]
#[inline(always)]
pub fn is_clld_1(&self) -> bool {
*self == Clld::Clld1
}
#[doc = "Compare latch load sourec : 2 - up/down"]
#[inline(always)]
pub fn is_clld_2(&self) -> bool {
*self == Clld::Clld2
}
#[doc = "Compare latch load sourec : 3 - TBR counts to TBCTL0"]
#[inline(always)]
pub fn is_clld_3(&self) -> bool {
*self == Clld::Clld3
}
}
#[doc = "Field `CLLD` writer - Compare latch load source 1"]
pub type ClldW<'a, REG> = crate::FieldWriter<'a, REG, 2, Clld, crate::Safe>;
impl<'a, REG> ClldW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Compare latch load sourec : 0 - immediate"]
#[inline(always)]
pub fn clld_0(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld0)
}
#[doc = "Compare latch load sourec : 1 - TBR counts to 0"]
#[inline(always)]
pub fn clld_1(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld1)
}
#[doc = "Compare latch load sourec : 2 - up/down"]
#[inline(always)]
pub fn clld_2(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld2)
}
#[doc = "Compare latch load sourec : 3 - TBR counts to TBCTL0"]
#[inline(always)]
pub fn clld_3(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld3)
}
}
#[doc = "Field `SCS` reader - Capture sychronize"]
pub type ScsR = crate::BitReader;
#[doc = "Field `SCS` writer - Capture sychronize"]
pub type ScsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture input select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ccis {
#[doc = "0: Capture input select: 0 - CCIxA"]
Ccis0 = 0,
#[doc = "1: Capture input select: 1 - CCIxB"]
Ccis1 = 1,
#[doc = "2: Capture input select: 2 - GND"]
Ccis2 = 2,
#[doc = "3: Capture input select: 3 - Vcc"]
Ccis3 = 3,
}
impl From<Ccis> for u8 {
#[inline(always)]
fn from(variant: Ccis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ccis {
type Ux = u8;
}
impl crate::IsEnum for Ccis {}
#[doc = "Field `CCIS` reader - Capture input select 1"]
pub type CcisR = crate::FieldReader<Ccis>;
impl CcisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccis {
match self.bits {
0 => Ccis::Ccis0,
1 => Ccis::Ccis1,
2 => Ccis::Ccis2,
3 => Ccis::Ccis3,
_ => unreachable!(),
}
}
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn is_ccis_0(&self) -> bool {
*self == Ccis::Ccis0
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn is_ccis_1(&self) -> bool {
*self == Ccis::Ccis1
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn is_ccis_2(&self) -> bool {
*self == Ccis::Ccis2
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn is_ccis_3(&self) -> bool {
*self == Ccis::Ccis3
}
}
#[doc = "Field `CCIS` writer - Capture input select 1"]
pub type CcisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ccis, crate::Safe>;
impl<'a, REG> CcisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn ccis_0(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis0)
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn ccis_1(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis1)
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn ccis_2(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis2)
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn ccis_3(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis3)
}
}
#[doc = "Capture mode 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Capture mode: 0 - disabled"]
Cm0 = 0,
#[doc = "1: Capture mode: 1 - pos. edge"]
Cm1 = 1,
#[doc = "2: Capture mode: 1 - neg. edge"]
Cm2 = 2,
#[doc = "3: Capture mode: 1 - both edges"]
Cm3 = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Capture mode 1"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cm {
match self.bits {
0 => Cm::Cm0,
1 => Cm::Cm1,
2 => Cm::Cm2,
3 => Cm::Cm3,
_ => unreachable!(),
}
}
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn is_cm_0(&self) -> bool {
*self == Cm::Cm0
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn is_cm_1(&self) -> bool {
*self == Cm::Cm1
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn is_cm_2(&self) -> bool {
*self == Cm::Cm2
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn is_cm_3(&self) -> bool {
*self == Cm::Cm3
}
}
#[doc = "Field `CM` writer - Capture mode 1"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm, crate::Safe>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn cm_0(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm0)
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn cm_1(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm1)
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn cm_2(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm2)
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn cm_3(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm3)
}
}
impl R {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&self) -> CcifgR {
CcifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&self) -> CovR {
CovR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&self) -> CciR {
CciR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&self) -> CcieR {
CcieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&self) -> OutmodR {
OutmodR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:10 - Compare latch load source 1"]
#[inline(always)]
pub fn clld(&self) -> ClldR {
ClldR::new(((self.bits >> 9) & 3) as u8)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&self) -> ScsR {
ScsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&self) -> CcisR {
CcisR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&mut self) -> CcifgW<'_, Tb0cctl4Spec> {
CcifgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&mut self) -> CovW<'_, Tb0cctl4Spec> {
CovW::new(self, 1)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&mut self) -> OutW<'_, Tb0cctl4Spec> {
OutW::new(self, 2)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&mut self) -> CciW<'_, Tb0cctl4Spec> {
CciW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&mut self) -> CcieW<'_, Tb0cctl4Spec> {
CcieW::new(self, 4)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&mut self) -> OutmodW<'_, Tb0cctl4Spec> {
OutmodW::new(self, 5)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&mut self) -> CapW<'_, Tb0cctl4Spec> {
CapW::new(self, 8)
}
#[doc = "Bits 9:10 - Compare latch load source 1"]
#[inline(always)]
pub fn clld(&mut self) -> ClldW<'_, Tb0cctl4Spec> {
ClldW::new(self, 9)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&mut self) -> ScsW<'_, Tb0cctl4Spec> {
ScsW::new(self, 11)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&mut self) -> CcisW<'_, Tb0cctl4Spec> {
CcisW::new(self, 12)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<'_, Tb0cctl4Spec> {
CmW::new(self, 14)
}
}
#[doc = "Timer0_B7 Capture/Compare Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0cctl4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0cctl4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0cctl4Spec;
impl crate::RegisterSpec for Tb0cctl4Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0cctl4::R`](R) reader structure"]
impl crate::Readable for Tb0cctl4Spec {}
#[doc = "`write(|w| ..)` method takes [`tb0cctl4::W`](W) writer structure"]
impl crate::Writable for Tb0cctl4Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0CCTL4 to value 0"]
impl crate::Resettable for Tb0cctl4Spec {}
}
#[doc = "TB0CCTL5 (rw) register accessor: Timer0_B7 Capture/Compare Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0cctl5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0cctl5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0cctl5`] module"]
#[doc(alias = "TB0CCTL5")]
pub type Tb0cctl5 = crate::Reg<tb0cctl5::Tb0cctl5Spec>;
#[doc = "Timer0_B7 Capture/Compare Control 5"]
pub mod tb0cctl5 {
#[doc = "Register `TB0CCTL5` reader"]
pub type R = crate::R<Tb0cctl5Spec>;
#[doc = "Register `TB0CCTL5` writer"]
pub type W = crate::W<Tb0cctl5Spec>;
#[doc = "Field `CCIFG` reader - Capture/compare interrupt flag"]
pub type CcifgR = crate::BitReader;
#[doc = "Field `CCIFG` writer - Capture/compare interrupt flag"]
pub type CcifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COV` reader - Capture/compare overflow flag"]
pub type CovR = crate::BitReader;
#[doc = "Field `COV` writer - Capture/compare overflow flag"]
pub type CovW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OUT` reader - PWM Output signal if output mode 0"]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - PWM Output signal if output mode 0"]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCI` reader - Capture input signal (read)"]
pub type CciR = crate::BitReader;
#[doc = "Field `CCI` writer - Capture input signal (read)"]
pub type CciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCIE` reader - Capture/compare interrupt enable"]
pub type CcieR = crate::BitReader;
#[doc = "Field `CCIE` writer - Capture/compare interrupt enable"]
pub type CcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output mode 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Outmod {
#[doc = "0: PWM output mode: 0 - output only"]
Outmod0 = 0,
#[doc = "1: PWM output mode: 1 - set"]
Outmod1 = 1,
#[doc = "2: PWM output mode: 2 - PWM toggle/reset"]
Outmod2 = 2,
#[doc = "3: PWM output mode: 3 - PWM set/reset"]
Outmod3 = 3,
#[doc = "4: PWM output mode: 4 - toggle"]
Outmod4 = 4,
#[doc = "5: PWM output mode: 5 - Reset"]
Outmod5 = 5,
#[doc = "6: PWM output mode: 6 - PWM toggle/set"]
Outmod6 = 6,
#[doc = "7: PWM output mode: 7 - PWM reset/set"]
Outmod7 = 7,
}
impl From<Outmod> for u8 {
#[inline(always)]
fn from(variant: Outmod) -> Self {
variant as _
}
}
impl crate::FieldSpec for Outmod {
type Ux = u8;
}
impl crate::IsEnum for Outmod {}
#[doc = "Field `OUTMOD` reader - Output mode 2"]
pub type OutmodR = crate::FieldReader<Outmod>;
impl OutmodR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Outmod {
match self.bits {
0 => Outmod::Outmod0,
1 => Outmod::Outmod1,
2 => Outmod::Outmod2,
3 => Outmod::Outmod3,
4 => Outmod::Outmod4,
5 => Outmod::Outmod5,
6 => Outmod::Outmod6,
7 => Outmod::Outmod7,
_ => unreachable!(),
}
}
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn is_outmod_0(&self) -> bool {
*self == Outmod::Outmod0
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn is_outmod_1(&self) -> bool {
*self == Outmod::Outmod1
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn is_outmod_2(&self) -> bool {
*self == Outmod::Outmod2
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn is_outmod_3(&self) -> bool {
*self == Outmod::Outmod3
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn is_outmod_4(&self) -> bool {
*self == Outmod::Outmod4
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn is_outmod_5(&self) -> bool {
*self == Outmod::Outmod5
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn is_outmod_6(&self) -> bool {
*self == Outmod::Outmod6
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn is_outmod_7(&self) -> bool {
*self == Outmod::Outmod7
}
}
#[doc = "Field `OUTMOD` writer - Output mode 2"]
pub type OutmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Outmod, crate::Safe>;
impl<'a, REG> OutmodW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn outmod_0(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod0)
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn outmod_1(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod1)
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn outmod_2(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod2)
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn outmod_3(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod3)
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn outmod_4(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod4)
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn outmod_5(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod5)
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn outmod_6(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod6)
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn outmod_7(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod7)
}
}
#[doc = "Field `CAP` reader - Capture mode: 1 /Compare mode : 0"]
pub type CapR = crate::BitReader;
#[doc = "Field `CAP` writer - Capture mode: 1 /Compare mode : 0"]
pub type CapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Compare latch load source 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Clld {
#[doc = "0: Compare latch load sourec : 0 - immediate"]
Clld0 = 0,
#[doc = "1: Compare latch load sourec : 1 - TBR counts to 0"]
Clld1 = 1,
#[doc = "2: Compare latch load sourec : 2 - up/down"]
Clld2 = 2,
#[doc = "3: Compare latch load sourec : 3 - TBR counts to TBCTL0"]
Clld3 = 3,
}
impl From<Clld> for u8 {
#[inline(always)]
fn from(variant: Clld) -> Self {
variant as _
}
}
impl crate::FieldSpec for Clld {
type Ux = u8;
}
impl crate::IsEnum for Clld {}
#[doc = "Field `CLLD` reader - Compare latch load source 1"]
pub type ClldR = crate::FieldReader<Clld>;
impl ClldR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Clld {
match self.bits {
0 => Clld::Clld0,
1 => Clld::Clld1,
2 => Clld::Clld2,
3 => Clld::Clld3,
_ => unreachable!(),
}
}
#[doc = "Compare latch load sourec : 0 - immediate"]
#[inline(always)]
pub fn is_clld_0(&self) -> bool {
*self == Clld::Clld0
}
#[doc = "Compare latch load sourec : 1 - TBR counts to 0"]
#[inline(always)]
pub fn is_clld_1(&self) -> bool {
*self == Clld::Clld1
}
#[doc = "Compare latch load sourec : 2 - up/down"]
#[inline(always)]
pub fn is_clld_2(&self) -> bool {
*self == Clld::Clld2
}
#[doc = "Compare latch load sourec : 3 - TBR counts to TBCTL0"]
#[inline(always)]
pub fn is_clld_3(&self) -> bool {
*self == Clld::Clld3
}
}
#[doc = "Field `CLLD` writer - Compare latch load source 1"]
pub type ClldW<'a, REG> = crate::FieldWriter<'a, REG, 2, Clld, crate::Safe>;
impl<'a, REG> ClldW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Compare latch load sourec : 0 - immediate"]
#[inline(always)]
pub fn clld_0(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld0)
}
#[doc = "Compare latch load sourec : 1 - TBR counts to 0"]
#[inline(always)]
pub fn clld_1(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld1)
}
#[doc = "Compare latch load sourec : 2 - up/down"]
#[inline(always)]
pub fn clld_2(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld2)
}
#[doc = "Compare latch load sourec : 3 - TBR counts to TBCTL0"]
#[inline(always)]
pub fn clld_3(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld3)
}
}
#[doc = "Field `SCS` reader - Capture sychronize"]
pub type ScsR = crate::BitReader;
#[doc = "Field `SCS` writer - Capture sychronize"]
pub type ScsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture input select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ccis {
#[doc = "0: Capture input select: 0 - CCIxA"]
Ccis0 = 0,
#[doc = "1: Capture input select: 1 - CCIxB"]
Ccis1 = 1,
#[doc = "2: Capture input select: 2 - GND"]
Ccis2 = 2,
#[doc = "3: Capture input select: 3 - Vcc"]
Ccis3 = 3,
}
impl From<Ccis> for u8 {
#[inline(always)]
fn from(variant: Ccis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ccis {
type Ux = u8;
}
impl crate::IsEnum for Ccis {}
#[doc = "Field `CCIS` reader - Capture input select 1"]
pub type CcisR = crate::FieldReader<Ccis>;
impl CcisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccis {
match self.bits {
0 => Ccis::Ccis0,
1 => Ccis::Ccis1,
2 => Ccis::Ccis2,
3 => Ccis::Ccis3,
_ => unreachable!(),
}
}
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn is_ccis_0(&self) -> bool {
*self == Ccis::Ccis0
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn is_ccis_1(&self) -> bool {
*self == Ccis::Ccis1
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn is_ccis_2(&self) -> bool {
*self == Ccis::Ccis2
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn is_ccis_3(&self) -> bool {
*self == Ccis::Ccis3
}
}
#[doc = "Field `CCIS` writer - Capture input select 1"]
pub type CcisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ccis, crate::Safe>;
impl<'a, REG> CcisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn ccis_0(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis0)
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn ccis_1(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis1)
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn ccis_2(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis2)
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn ccis_3(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis3)
}
}
#[doc = "Capture mode 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Capture mode: 0 - disabled"]
Cm0 = 0,
#[doc = "1: Capture mode: 1 - pos. edge"]
Cm1 = 1,
#[doc = "2: Capture mode: 1 - neg. edge"]
Cm2 = 2,
#[doc = "3: Capture mode: 1 - both edges"]
Cm3 = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Capture mode 1"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cm {
match self.bits {
0 => Cm::Cm0,
1 => Cm::Cm1,
2 => Cm::Cm2,
3 => Cm::Cm3,
_ => unreachable!(),
}
}
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn is_cm_0(&self) -> bool {
*self == Cm::Cm0
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn is_cm_1(&self) -> bool {
*self == Cm::Cm1
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn is_cm_2(&self) -> bool {
*self == Cm::Cm2
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn is_cm_3(&self) -> bool {
*self == Cm::Cm3
}
}
#[doc = "Field `CM` writer - Capture mode 1"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm, crate::Safe>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn cm_0(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm0)
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn cm_1(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm1)
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn cm_2(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm2)
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn cm_3(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm3)
}
}
impl R {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&self) -> CcifgR {
CcifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&self) -> CovR {
CovR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&self) -> CciR {
CciR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&self) -> CcieR {
CcieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&self) -> OutmodR {
OutmodR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:10 - Compare latch load source 1"]
#[inline(always)]
pub fn clld(&self) -> ClldR {
ClldR::new(((self.bits >> 9) & 3) as u8)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&self) -> ScsR {
ScsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&self) -> CcisR {
CcisR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&mut self) -> CcifgW<'_, Tb0cctl5Spec> {
CcifgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&mut self) -> CovW<'_, Tb0cctl5Spec> {
CovW::new(self, 1)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&mut self) -> OutW<'_, Tb0cctl5Spec> {
OutW::new(self, 2)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&mut self) -> CciW<'_, Tb0cctl5Spec> {
CciW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&mut self) -> CcieW<'_, Tb0cctl5Spec> {
CcieW::new(self, 4)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&mut self) -> OutmodW<'_, Tb0cctl5Spec> {
OutmodW::new(self, 5)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&mut self) -> CapW<'_, Tb0cctl5Spec> {
CapW::new(self, 8)
}
#[doc = "Bits 9:10 - Compare latch load source 1"]
#[inline(always)]
pub fn clld(&mut self) -> ClldW<'_, Tb0cctl5Spec> {
ClldW::new(self, 9)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&mut self) -> ScsW<'_, Tb0cctl5Spec> {
ScsW::new(self, 11)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&mut self) -> CcisW<'_, Tb0cctl5Spec> {
CcisW::new(self, 12)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<'_, Tb0cctl5Spec> {
CmW::new(self, 14)
}
}
#[doc = "Timer0_B7 Capture/Compare Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0cctl5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0cctl5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0cctl5Spec;
impl crate::RegisterSpec for Tb0cctl5Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0cctl5::R`](R) reader structure"]
impl crate::Readable for Tb0cctl5Spec {}
#[doc = "`write(|w| ..)` method takes [`tb0cctl5::W`](W) writer structure"]
impl crate::Writable for Tb0cctl5Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0CCTL5 to value 0"]
impl crate::Resettable for Tb0cctl5Spec {}
}
#[doc = "TB0CCTL6 (rw) register accessor: Timer0_B7 Capture/Compare Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0cctl6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0cctl6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0cctl6`] module"]
#[doc(alias = "TB0CCTL6")]
pub type Tb0cctl6 = crate::Reg<tb0cctl6::Tb0cctl6Spec>;
#[doc = "Timer0_B7 Capture/Compare Control 6"]
pub mod tb0cctl6 {
#[doc = "Register `TB0CCTL6` reader"]
pub type R = crate::R<Tb0cctl6Spec>;
#[doc = "Register `TB0CCTL6` writer"]
pub type W = crate::W<Tb0cctl6Spec>;
#[doc = "Field `CCIFG` reader - Capture/compare interrupt flag"]
pub type CcifgR = crate::BitReader;
#[doc = "Field `CCIFG` writer - Capture/compare interrupt flag"]
pub type CcifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COV` reader - Capture/compare overflow flag"]
pub type CovR = crate::BitReader;
#[doc = "Field `COV` writer - Capture/compare overflow flag"]
pub type CovW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OUT` reader - PWM Output signal if output mode 0"]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - PWM Output signal if output mode 0"]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCI` reader - Capture input signal (read)"]
pub type CciR = crate::BitReader;
#[doc = "Field `CCI` writer - Capture input signal (read)"]
pub type CciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCIE` reader - Capture/compare interrupt enable"]
pub type CcieR = crate::BitReader;
#[doc = "Field `CCIE` writer - Capture/compare interrupt enable"]
pub type CcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output mode 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Outmod {
#[doc = "0: PWM output mode: 0 - output only"]
Outmod0 = 0,
#[doc = "1: PWM output mode: 1 - set"]
Outmod1 = 1,
#[doc = "2: PWM output mode: 2 - PWM toggle/reset"]
Outmod2 = 2,
#[doc = "3: PWM output mode: 3 - PWM set/reset"]
Outmod3 = 3,
#[doc = "4: PWM output mode: 4 - toggle"]
Outmod4 = 4,
#[doc = "5: PWM output mode: 5 - Reset"]
Outmod5 = 5,
#[doc = "6: PWM output mode: 6 - PWM toggle/set"]
Outmod6 = 6,
#[doc = "7: PWM output mode: 7 - PWM reset/set"]
Outmod7 = 7,
}
impl From<Outmod> for u8 {
#[inline(always)]
fn from(variant: Outmod) -> Self {
variant as _
}
}
impl crate::FieldSpec for Outmod {
type Ux = u8;
}
impl crate::IsEnum for Outmod {}
#[doc = "Field `OUTMOD` reader - Output mode 2"]
pub type OutmodR = crate::FieldReader<Outmod>;
impl OutmodR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Outmod {
match self.bits {
0 => Outmod::Outmod0,
1 => Outmod::Outmod1,
2 => Outmod::Outmod2,
3 => Outmod::Outmod3,
4 => Outmod::Outmod4,
5 => Outmod::Outmod5,
6 => Outmod::Outmod6,
7 => Outmod::Outmod7,
_ => unreachable!(),
}
}
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn is_outmod_0(&self) -> bool {
*self == Outmod::Outmod0
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn is_outmod_1(&self) -> bool {
*self == Outmod::Outmod1
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn is_outmod_2(&self) -> bool {
*self == Outmod::Outmod2
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn is_outmod_3(&self) -> bool {
*self == Outmod::Outmod3
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn is_outmod_4(&self) -> bool {
*self == Outmod::Outmod4
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn is_outmod_5(&self) -> bool {
*self == Outmod::Outmod5
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn is_outmod_6(&self) -> bool {
*self == Outmod::Outmod6
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn is_outmod_7(&self) -> bool {
*self == Outmod::Outmod7
}
}
#[doc = "Field `OUTMOD` writer - Output mode 2"]
pub type OutmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Outmod, crate::Safe>;
impl<'a, REG> OutmodW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn outmod_0(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod0)
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn outmod_1(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod1)
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn outmod_2(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod2)
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn outmod_3(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod3)
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn outmod_4(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod4)
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn outmod_5(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod5)
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn outmod_6(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod6)
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn outmod_7(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod7)
}
}
#[doc = "Field `CAP` reader - Capture mode: 1 /Compare mode : 0"]
pub type CapR = crate::BitReader;
#[doc = "Field `CAP` writer - Capture mode: 1 /Compare mode : 0"]
pub type CapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Compare latch load source 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Clld {
#[doc = "0: Compare latch load sourec : 0 - immediate"]
Clld0 = 0,
#[doc = "1: Compare latch load sourec : 1 - TBR counts to 0"]
Clld1 = 1,
#[doc = "2: Compare latch load sourec : 2 - up/down"]
Clld2 = 2,
#[doc = "3: Compare latch load sourec : 3 - TBR counts to TBCTL0"]
Clld3 = 3,
}
impl From<Clld> for u8 {
#[inline(always)]
fn from(variant: Clld) -> Self {
variant as _
}
}
impl crate::FieldSpec for Clld {
type Ux = u8;
}
impl crate::IsEnum for Clld {}
#[doc = "Field `CLLD` reader - Compare latch load source 1"]
pub type ClldR = crate::FieldReader<Clld>;
impl ClldR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Clld {
match self.bits {
0 => Clld::Clld0,
1 => Clld::Clld1,
2 => Clld::Clld2,
3 => Clld::Clld3,
_ => unreachable!(),
}
}
#[doc = "Compare latch load sourec : 0 - immediate"]
#[inline(always)]
pub fn is_clld_0(&self) -> bool {
*self == Clld::Clld0
}
#[doc = "Compare latch load sourec : 1 - TBR counts to 0"]
#[inline(always)]
pub fn is_clld_1(&self) -> bool {
*self == Clld::Clld1
}
#[doc = "Compare latch load sourec : 2 - up/down"]
#[inline(always)]
pub fn is_clld_2(&self) -> bool {
*self == Clld::Clld2
}
#[doc = "Compare latch load sourec : 3 - TBR counts to TBCTL0"]
#[inline(always)]
pub fn is_clld_3(&self) -> bool {
*self == Clld::Clld3
}
}
#[doc = "Field `CLLD` writer - Compare latch load source 1"]
pub type ClldW<'a, REG> = crate::FieldWriter<'a, REG, 2, Clld, crate::Safe>;
impl<'a, REG> ClldW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Compare latch load sourec : 0 - immediate"]
#[inline(always)]
pub fn clld_0(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld0)
}
#[doc = "Compare latch load sourec : 1 - TBR counts to 0"]
#[inline(always)]
pub fn clld_1(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld1)
}
#[doc = "Compare latch load sourec : 2 - up/down"]
#[inline(always)]
pub fn clld_2(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld2)
}
#[doc = "Compare latch load sourec : 3 - TBR counts to TBCTL0"]
#[inline(always)]
pub fn clld_3(self) -> &'a mut crate::W<REG> {
self.variant(Clld::Clld3)
}
}
#[doc = "Field `SCS` reader - Capture sychronize"]
pub type ScsR = crate::BitReader;
#[doc = "Field `SCS` writer - Capture sychronize"]
pub type ScsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture input select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ccis {
#[doc = "0: Capture input select: 0 - CCIxA"]
Ccis0 = 0,
#[doc = "1: Capture input select: 1 - CCIxB"]
Ccis1 = 1,
#[doc = "2: Capture input select: 2 - GND"]
Ccis2 = 2,
#[doc = "3: Capture input select: 3 - Vcc"]
Ccis3 = 3,
}
impl From<Ccis> for u8 {
#[inline(always)]
fn from(variant: Ccis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ccis {
type Ux = u8;
}
impl crate::IsEnum for Ccis {}
#[doc = "Field `CCIS` reader - Capture input select 1"]
pub type CcisR = crate::FieldReader<Ccis>;
impl CcisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccis {
match self.bits {
0 => Ccis::Ccis0,
1 => Ccis::Ccis1,
2 => Ccis::Ccis2,
3 => Ccis::Ccis3,
_ => unreachable!(),
}
}
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn is_ccis_0(&self) -> bool {
*self == Ccis::Ccis0
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn is_ccis_1(&self) -> bool {
*self == Ccis::Ccis1
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn is_ccis_2(&self) -> bool {
*self == Ccis::Ccis2
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn is_ccis_3(&self) -> bool {
*self == Ccis::Ccis3
}
}
#[doc = "Field `CCIS` writer - Capture input select 1"]
pub type CcisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ccis, crate::Safe>;
impl<'a, REG> CcisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn ccis_0(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis0)
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn ccis_1(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis1)
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn ccis_2(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis2)
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn ccis_3(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis3)
}
}
#[doc = "Capture mode 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Capture mode: 0 - disabled"]
Cm0 = 0,
#[doc = "1: Capture mode: 1 - pos. edge"]
Cm1 = 1,
#[doc = "2: Capture mode: 1 - neg. edge"]
Cm2 = 2,
#[doc = "3: Capture mode: 1 - both edges"]
Cm3 = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Capture mode 1"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cm {
match self.bits {
0 => Cm::Cm0,
1 => Cm::Cm1,
2 => Cm::Cm2,
3 => Cm::Cm3,
_ => unreachable!(),
}
}
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn is_cm_0(&self) -> bool {
*self == Cm::Cm0
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn is_cm_1(&self) -> bool {
*self == Cm::Cm1
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn is_cm_2(&self) -> bool {
*self == Cm::Cm2
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn is_cm_3(&self) -> bool {
*self == Cm::Cm3
}
}
#[doc = "Field `CM` writer - Capture mode 1"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm, crate::Safe>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn cm_0(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm0)
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn cm_1(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm1)
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn cm_2(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm2)
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn cm_3(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm3)
}
}
impl R {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&self) -> CcifgR {
CcifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&self) -> CovR {
CovR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&self) -> CciR {
CciR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&self) -> CcieR {
CcieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&self) -> OutmodR {
OutmodR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:10 - Compare latch load source 1"]
#[inline(always)]
pub fn clld(&self) -> ClldR {
ClldR::new(((self.bits >> 9) & 3) as u8)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&self) -> ScsR {
ScsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&self) -> CcisR {
CcisR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&mut self) -> CcifgW<'_, Tb0cctl6Spec> {
CcifgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&mut self) -> CovW<'_, Tb0cctl6Spec> {
CovW::new(self, 1)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&mut self) -> OutW<'_, Tb0cctl6Spec> {
OutW::new(self, 2)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&mut self) -> CciW<'_, Tb0cctl6Spec> {
CciW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&mut self) -> CcieW<'_, Tb0cctl6Spec> {
CcieW::new(self, 4)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&mut self) -> OutmodW<'_, Tb0cctl6Spec> {
OutmodW::new(self, 5)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&mut self) -> CapW<'_, Tb0cctl6Spec> {
CapW::new(self, 8)
}
#[doc = "Bits 9:10 - Compare latch load source 1"]
#[inline(always)]
pub fn clld(&mut self) -> ClldW<'_, Tb0cctl6Spec> {
ClldW::new(self, 9)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&mut self) -> ScsW<'_, Tb0cctl6Spec> {
ScsW::new(self, 11)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&mut self) -> CcisW<'_, Tb0cctl6Spec> {
CcisW::new(self, 12)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<'_, Tb0cctl6Spec> {
CmW::new(self, 14)
}
}
#[doc = "Timer0_B7 Capture/Compare Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0cctl6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0cctl6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0cctl6Spec;
impl crate::RegisterSpec for Tb0cctl6Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0cctl6::R`](R) reader structure"]
impl crate::Readable for Tb0cctl6Spec {}
#[doc = "`write(|w| ..)` method takes [`tb0cctl6::W`](W) writer structure"]
impl crate::Writable for Tb0cctl6Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0CCTL6 to value 0"]
impl crate::Resettable for Tb0cctl6Spec {}
}
#[doc = "TB0R (rw) register accessor: Timer0_B7\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0r`] module"]
#[doc(alias = "TB0R")]
pub type Tb0r = crate::Reg<tb0r::Tb0rSpec>;
#[doc = "Timer0_B7"]
pub mod tb0r {
#[doc = "Register `TB0R` reader"]
pub type R = crate::R<Tb0rSpec>;
#[doc = "Register `TB0R` writer"]
pub type W = crate::W<Tb0rSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer0_B7\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0r::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0r::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0rSpec;
impl crate::RegisterSpec for Tb0rSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0r::R`](R) reader structure"]
impl crate::Readable for Tb0rSpec {}
#[doc = "`write(|w| ..)` method takes [`tb0r::W`](W) writer structure"]
impl crate::Writable for Tb0rSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0R to value 0"]
impl crate::Resettable for Tb0rSpec {}
}
#[doc = "TB0CCR0 (rw) register accessor: Timer0_B7 Capture/Compare 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ccr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ccr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0ccr0`] module"]
#[doc(alias = "TB0CCR0")]
pub type Tb0ccr0 = crate::Reg<tb0ccr0::Tb0ccr0Spec>;
#[doc = "Timer0_B7 Capture/Compare 0"]
pub mod tb0ccr0 {
#[doc = "Register `TB0CCR0` reader"]
pub type R = crate::R<Tb0ccr0Spec>;
#[doc = "Register `TB0CCR0` writer"]
pub type W = crate::W<Tb0ccr0Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer0_B7 Capture/Compare 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ccr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ccr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0ccr0Spec;
impl crate::RegisterSpec for Tb0ccr0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0ccr0::R`](R) reader structure"]
impl crate::Readable for Tb0ccr0Spec {}
#[doc = "`write(|w| ..)` method takes [`tb0ccr0::W`](W) writer structure"]
impl crate::Writable for Tb0ccr0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0CCR0 to value 0"]
impl crate::Resettable for Tb0ccr0Spec {}
}
#[doc = "TB0CCR1 (rw) register accessor: Timer0_B7 Capture/Compare 1\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ccr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ccr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0ccr1`] module"]
#[doc(alias = "TB0CCR1")]
pub type Tb0ccr1 = crate::Reg<tb0ccr1::Tb0ccr1Spec>;
#[doc = "Timer0_B7 Capture/Compare 1"]
pub mod tb0ccr1 {
#[doc = "Register `TB0CCR1` reader"]
pub type R = crate::R<Tb0ccr1Spec>;
#[doc = "Register `TB0CCR1` writer"]
pub type W = crate::W<Tb0ccr1Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer0_B7 Capture/Compare 1\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ccr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ccr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0ccr1Spec;
impl crate::RegisterSpec for Tb0ccr1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0ccr1::R`](R) reader structure"]
impl crate::Readable for Tb0ccr1Spec {}
#[doc = "`write(|w| ..)` method takes [`tb0ccr1::W`](W) writer structure"]
impl crate::Writable for Tb0ccr1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0CCR1 to value 0"]
impl crate::Resettable for Tb0ccr1Spec {}
}
#[doc = "TB0CCR2 (rw) register accessor: Timer0_B7 Capture/Compare 2\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ccr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ccr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0ccr2`] module"]
#[doc(alias = "TB0CCR2")]
pub type Tb0ccr2 = crate::Reg<tb0ccr2::Tb0ccr2Spec>;
#[doc = "Timer0_B7 Capture/Compare 2"]
pub mod tb0ccr2 {
#[doc = "Register `TB0CCR2` reader"]
pub type R = crate::R<Tb0ccr2Spec>;
#[doc = "Register `TB0CCR2` writer"]
pub type W = crate::W<Tb0ccr2Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer0_B7 Capture/Compare 2\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ccr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ccr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0ccr2Spec;
impl crate::RegisterSpec for Tb0ccr2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0ccr2::R`](R) reader structure"]
impl crate::Readable for Tb0ccr2Spec {}
#[doc = "`write(|w| ..)` method takes [`tb0ccr2::W`](W) writer structure"]
impl crate::Writable for Tb0ccr2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0CCR2 to value 0"]
impl crate::Resettable for Tb0ccr2Spec {}
}
#[doc = "TB0CCR3 (rw) register accessor: Timer0_B7 Capture/Compare 3\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ccr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ccr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0ccr3`] module"]
#[doc(alias = "TB0CCR3")]
pub type Tb0ccr3 = crate::Reg<tb0ccr3::Tb0ccr3Spec>;
#[doc = "Timer0_B7 Capture/Compare 3"]
pub mod tb0ccr3 {
#[doc = "Register `TB0CCR3` reader"]
pub type R = crate::R<Tb0ccr3Spec>;
#[doc = "Register `TB0CCR3` writer"]
pub type W = crate::W<Tb0ccr3Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer0_B7 Capture/Compare 3\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ccr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ccr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0ccr3Spec;
impl crate::RegisterSpec for Tb0ccr3Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0ccr3::R`](R) reader structure"]
impl crate::Readable for Tb0ccr3Spec {}
#[doc = "`write(|w| ..)` method takes [`tb0ccr3::W`](W) writer structure"]
impl crate::Writable for Tb0ccr3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0CCR3 to value 0"]
impl crate::Resettable for Tb0ccr3Spec {}
}
#[doc = "TB0CCR4 (rw) register accessor: Timer0_B7 Capture/Compare 4\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ccr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ccr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0ccr4`] module"]
#[doc(alias = "TB0CCR4")]
pub type Tb0ccr4 = crate::Reg<tb0ccr4::Tb0ccr4Spec>;
#[doc = "Timer0_B7 Capture/Compare 4"]
pub mod tb0ccr4 {
#[doc = "Register `TB0CCR4` reader"]
pub type R = crate::R<Tb0ccr4Spec>;
#[doc = "Register `TB0CCR4` writer"]
pub type W = crate::W<Tb0ccr4Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer0_B7 Capture/Compare 4\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ccr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ccr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0ccr4Spec;
impl crate::RegisterSpec for Tb0ccr4Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0ccr4::R`](R) reader structure"]
impl crate::Readable for Tb0ccr4Spec {}
#[doc = "`write(|w| ..)` method takes [`tb0ccr4::W`](W) writer structure"]
impl crate::Writable for Tb0ccr4Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0CCR4 to value 0"]
impl crate::Resettable for Tb0ccr4Spec {}
}
#[doc = "TB0CCR5 (rw) register accessor: Timer0_B7 Capture/Compare 5\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ccr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ccr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0ccr5`] module"]
#[doc(alias = "TB0CCR5")]
pub type Tb0ccr5 = crate::Reg<tb0ccr5::Tb0ccr5Spec>;
#[doc = "Timer0_B7 Capture/Compare 5"]
pub mod tb0ccr5 {
#[doc = "Register `TB0CCR5` reader"]
pub type R = crate::R<Tb0ccr5Spec>;
#[doc = "Register `TB0CCR5` writer"]
pub type W = crate::W<Tb0ccr5Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer0_B7 Capture/Compare 5\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ccr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ccr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0ccr5Spec;
impl crate::RegisterSpec for Tb0ccr5Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0ccr5::R`](R) reader structure"]
impl crate::Readable for Tb0ccr5Spec {}
#[doc = "`write(|w| ..)` method takes [`tb0ccr5::W`](W) writer structure"]
impl crate::Writable for Tb0ccr5Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0CCR5 to value 0"]
impl crate::Resettable for Tb0ccr5Spec {}
}
#[doc = "TB0CCR6 (rw) register accessor: Timer0_B7 Capture/Compare 6\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ccr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ccr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0ccr6`] module"]
#[doc(alias = "TB0CCR6")]
pub type Tb0ccr6 = crate::Reg<tb0ccr6::Tb0ccr6Spec>;
#[doc = "Timer0_B7 Capture/Compare 6"]
pub mod tb0ccr6 {
#[doc = "Register `TB0CCR6` reader"]
pub type R = crate::R<Tb0ccr6Spec>;
#[doc = "Register `TB0CCR6` writer"]
pub type W = crate::W<Tb0ccr6Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer0_B7 Capture/Compare 6\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ccr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ccr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0ccr6Spec;
impl crate::RegisterSpec for Tb0ccr6Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0ccr6::R`](R) reader structure"]
impl crate::Readable for Tb0ccr6Spec {}
#[doc = "`write(|w| ..)` method takes [`tb0ccr6::W`](W) writer structure"]
impl crate::Writable for Tb0ccr6Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0CCR6 to value 0"]
impl crate::Resettable for Tb0ccr6Spec {}
}
#[doc = "TB0EX0 (rw) register accessor: Timer0_B7 Expansion Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ex0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ex0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0ex0`] module"]
#[doc(alias = "TB0EX0")]
pub type Tb0ex0 = crate::Reg<tb0ex0::Tb0ex0Spec>;
#[doc = "Timer0_B7 Expansion Register 0"]
pub mod tb0ex0 {
#[doc = "Register `TB0EX0` reader"]
pub type R = crate::R<Tb0ex0Spec>;
#[doc = "Register `TB0EX0` writer"]
pub type W = crate::W<Tb0ex0Spec>;
#[doc = "Timer0_B7 Input divider expansion Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Tbidex {
#[doc = "0: Timer0_B7 Input divider expansion : /1"]
Tbidex0 = 0,
#[doc = "1: Timer0_B7 Input divider expansion : /2"]
Tbidex1 = 1,
#[doc = "2: Timer0_B7 Input divider expansion : /3"]
Tbidex2 = 2,
#[doc = "3: Timer0_B7 Input divider expansion : /4"]
Tbidex3 = 3,
#[doc = "4: Timer0_B7 Input divider expansion : /5"]
Tbidex4 = 4,
#[doc = "5: Timer0_B7 Input divider expansion : /6"]
Tbidex5 = 5,
#[doc = "6: Timer0_B7 Input divider expansion : /7"]
Tbidex6 = 6,
#[doc = "7: Timer0_B7 Input divider expansion : /8"]
Tbidex7 = 7,
}
impl From<Tbidex> for u8 {
#[inline(always)]
fn from(variant: Tbidex) -> Self {
variant as _
}
}
impl crate::FieldSpec for Tbidex {
type Ux = u8;
}
impl crate::IsEnum for Tbidex {}
#[doc = "Field `TBIDEX` reader - Timer0_B7 Input divider expansion Bit: 0"]
pub type TbidexR = crate::FieldReader<Tbidex>;
impl TbidexR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Tbidex {
match self.bits {
0 => Tbidex::Tbidex0,
1 => Tbidex::Tbidex1,
2 => Tbidex::Tbidex2,
3 => Tbidex::Tbidex3,
4 => Tbidex::Tbidex4,
5 => Tbidex::Tbidex5,
6 => Tbidex::Tbidex6,
7 => Tbidex::Tbidex7,
_ => unreachable!(),
}
}
#[doc = "Timer0_B7 Input divider expansion : /1"]
#[inline(always)]
pub fn is_tbidex_0(&self) -> bool {
*self == Tbidex::Tbidex0
}
#[doc = "Timer0_B7 Input divider expansion : /2"]
#[inline(always)]
pub fn is_tbidex_1(&self) -> bool {
*self == Tbidex::Tbidex1
}
#[doc = "Timer0_B7 Input divider expansion : /3"]
#[inline(always)]
pub fn is_tbidex_2(&self) -> bool {
*self == Tbidex::Tbidex2
}
#[doc = "Timer0_B7 Input divider expansion : /4"]
#[inline(always)]
pub fn is_tbidex_3(&self) -> bool {
*self == Tbidex::Tbidex3
}
#[doc = "Timer0_B7 Input divider expansion : /5"]
#[inline(always)]
pub fn is_tbidex_4(&self) -> bool {
*self == Tbidex::Tbidex4
}
#[doc = "Timer0_B7 Input divider expansion : /6"]
#[inline(always)]
pub fn is_tbidex_5(&self) -> bool {
*self == Tbidex::Tbidex5
}
#[doc = "Timer0_B7 Input divider expansion : /7"]
#[inline(always)]
pub fn is_tbidex_6(&self) -> bool {
*self == Tbidex::Tbidex6
}
#[doc = "Timer0_B7 Input divider expansion : /8"]
#[inline(always)]
pub fn is_tbidex_7(&self) -> bool {
*self == Tbidex::Tbidex7
}
}
#[doc = "Field `TBIDEX` writer - Timer0_B7 Input divider expansion Bit: 0"]
pub type TbidexW<'a, REG> = crate::FieldWriter<'a, REG, 3, Tbidex, crate::Safe>;
impl<'a, REG> TbidexW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer0_B7 Input divider expansion : /1"]
#[inline(always)]
pub fn tbidex_0(self) -> &'a mut crate::W<REG> {
self.variant(Tbidex::Tbidex0)
}
#[doc = "Timer0_B7 Input divider expansion : /2"]
#[inline(always)]
pub fn tbidex_1(self) -> &'a mut crate::W<REG> {
self.variant(Tbidex::Tbidex1)
}
#[doc = "Timer0_B7 Input divider expansion : /3"]
#[inline(always)]
pub fn tbidex_2(self) -> &'a mut crate::W<REG> {
self.variant(Tbidex::Tbidex2)
}
#[doc = "Timer0_B7 Input divider expansion : /4"]
#[inline(always)]
pub fn tbidex_3(self) -> &'a mut crate::W<REG> {
self.variant(Tbidex::Tbidex3)
}
#[doc = "Timer0_B7 Input divider expansion : /5"]
#[inline(always)]
pub fn tbidex_4(self) -> &'a mut crate::W<REG> {
self.variant(Tbidex::Tbidex4)
}
#[doc = "Timer0_B7 Input divider expansion : /6"]
#[inline(always)]
pub fn tbidex_5(self) -> &'a mut crate::W<REG> {
self.variant(Tbidex::Tbidex5)
}
#[doc = "Timer0_B7 Input divider expansion : /7"]
#[inline(always)]
pub fn tbidex_6(self) -> &'a mut crate::W<REG> {
self.variant(Tbidex::Tbidex6)
}
#[doc = "Timer0_B7 Input divider expansion : /8"]
#[inline(always)]
pub fn tbidex_7(self) -> &'a mut crate::W<REG> {
self.variant(Tbidex::Tbidex7)
}
}
impl R {
#[doc = "Bits 0:2 - Timer0_B7 Input divider expansion Bit: 0"]
#[inline(always)]
pub fn tbidex(&self) -> TbidexR {
TbidexR::new((self.bits & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:2 - Timer0_B7 Input divider expansion Bit: 0"]
#[inline(always)]
pub fn tbidex(&mut self) -> TbidexW<'_, Tb0ex0Spec> {
TbidexW::new(self, 0)
}
}
#[doc = "Timer0_B7 Expansion Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0ex0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0ex0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0ex0Spec;
impl crate::RegisterSpec for Tb0ex0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0ex0::R`](R) reader structure"]
impl crate::Readable for Tb0ex0Spec {}
#[doc = "`write(|w| ..)` method takes [`tb0ex0::W`](W) writer structure"]
impl crate::Writable for Tb0ex0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0EX0 to value 0"]
impl crate::Resettable for Tb0ex0Spec {}
}
#[doc = "TB0IV (rw) register accessor: Timer0_B7 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0iv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0iv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tb0iv`] module"]
#[doc(alias = "TB0IV")]
pub type Tb0iv = crate::Reg<tb0iv::Tb0ivSpec>;
#[doc = "Timer0_B7 Interrupt Vector Word"]
pub mod tb0iv {
#[doc = "Register `TB0IV` reader"]
pub type R = crate::R<Tb0ivSpec>;
#[doc = "Register `TB0IV` writer"]
pub type W = crate::W<Tb0ivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer0_B7 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`tb0iv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tb0iv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Tb0ivSpec;
impl crate::RegisterSpec for Tb0ivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`tb0iv::R`](R) reader structure"]
impl crate::Readable for Tb0ivSpec {}
#[doc = "`write(|w| ..)` method takes [`tb0iv::W`](W) writer structure"]
impl crate::Writable for Tb0ivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TB0IV to value 0"]
impl crate::Resettable for Tb0ivSpec {}
}
}
#[doc = "Timer2_A2"]
pub type Timer2A2 = crate::Periph<timer_2_a2::RegisterBlock, 0x0400>;
impl core::fmt::Debug for Timer2A2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Timer2A2").finish()
}
}
#[doc = "Timer2_A2"]
pub mod timer_2_a2 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
ta2ctl: Ta2ctl,
ta2cctl0: Ta2cctl0,
ta2cctl1: Ta2cctl1,
_reserved3: [u8; 0x0a],
ta2r: Ta2r,
ta2ccr0: Ta2ccr0,
ta2ccr1: Ta2ccr1,
_reserved6: [u8; 0x0a],
ta2ex0: Ta2ex0,
_reserved7: [u8; 0x0c],
ta2iv: Ta2iv,
}
impl RegisterBlock {
#[doc = "0x00 - Timer2_A2 Control"]
#[inline(always)]
pub const fn ta2ctl(&self) -> &Ta2ctl {
&self.ta2ctl
}
#[doc = "0x02 - Timer2_A2 Capture/Compare Control 0"]
#[inline(always)]
pub const fn ta2cctl0(&self) -> &Ta2cctl0 {
&self.ta2cctl0
}
#[doc = "0x04 - Timer2_A2 Capture/Compare Control 1"]
#[inline(always)]
pub const fn ta2cctl1(&self) -> &Ta2cctl1 {
&self.ta2cctl1
}
#[doc = "0x10 - Timer2_A2"]
#[inline(always)]
pub const fn ta2r(&self) -> &Ta2r {
&self.ta2r
}
#[doc = "0x12 - Timer2_A2 Capture/Compare 0"]
#[inline(always)]
pub const fn ta2ccr0(&self) -> &Ta2ccr0 {
&self.ta2ccr0
}
#[doc = "0x14 - Timer2_A2 Capture/Compare 1"]
#[inline(always)]
pub const fn ta2ccr1(&self) -> &Ta2ccr1 {
&self.ta2ccr1
}
#[doc = "0x20 - Timer2_A2 Expansion Register 0"]
#[inline(always)]
pub const fn ta2ex0(&self) -> &Ta2ex0 {
&self.ta2ex0
}
#[doc = "0x2e - Timer2_A2 Interrupt Vector Word"]
#[inline(always)]
pub const fn ta2iv(&self) -> &Ta2iv {
&self.ta2iv
}
}
#[doc = "TA2CTL (rw) register accessor: Timer2_A2 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ta2ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta2ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta2ctl`] module"]
#[doc(alias = "TA2CTL")]
pub type Ta2ctl = crate::Reg<ta2ctl::Ta2ctlSpec>;
#[doc = "Timer2_A2 Control"]
pub mod ta2ctl {
#[doc = "Register `TA2CTL` reader"]
pub type R = crate::R<Ta2ctlSpec>;
#[doc = "Register `TA2CTL` writer"]
pub type W = crate::W<Ta2ctlSpec>;
#[doc = "Field `TAIFG` reader - Timer A counter interrupt flag"]
pub type TaifgR = crate::BitReader;
#[doc = "Field `TAIFG` writer - Timer A counter interrupt flag"]
pub type TaifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TAIE` reader - Timer A counter interrupt enable"]
pub type TaieR = crate::BitReader;
#[doc = "Field `TAIE` writer - Timer A counter interrupt enable"]
pub type TaieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TACLR` reader - Timer A counter clear"]
pub type TaclrR = crate::BitReader;
#[doc = "Field `TACLR` writer - Timer A counter clear"]
pub type TaclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Timer A mode control 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mc {
#[doc = "0: Timer A mode control: 0 - Stop"]
Mc0 = 0,
#[doc = "1: Timer A mode control: 1 - Up to CCR0"]
Mc1 = 1,
#[doc = "2: Timer A mode control: 2 - Continuous up"]
Mc2 = 2,
#[doc = "3: Timer A mode control: 3 - Up/Down"]
Mc3 = 3,
}
impl From<Mc> for u8 {
#[inline(always)]
fn from(variant: Mc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mc {
type Ux = u8;
}
impl crate::IsEnum for Mc {}
#[doc = "Field `MC` reader - Timer A mode control 1"]
pub type McR = crate::FieldReader<Mc>;
impl McR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mc {
match self.bits {
0 => Mc::Mc0,
1 => Mc::Mc1,
2 => Mc::Mc2,
3 => Mc::Mc3,
_ => unreachable!(),
}
}
#[doc = "Timer A mode control: 0 - Stop"]
#[inline(always)]
pub fn is_mc_0(&self) -> bool {
*self == Mc::Mc0
}
#[doc = "Timer A mode control: 1 - Up to CCR0"]
#[inline(always)]
pub fn is_mc_1(&self) -> bool {
*self == Mc::Mc1
}
#[doc = "Timer A mode control: 2 - Continuous up"]
#[inline(always)]
pub fn is_mc_2(&self) -> bool {
*self == Mc::Mc2
}
#[doc = "Timer A mode control: 3 - Up/Down"]
#[inline(always)]
pub fn is_mc_3(&self) -> bool {
*self == Mc::Mc3
}
}
#[doc = "Field `MC` writer - Timer A mode control 1"]
pub type McW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mc, crate::Safe>;
impl<'a, REG> McW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A mode control: 0 - Stop"]
#[inline(always)]
pub fn mc_0(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc0)
}
#[doc = "Timer A mode control: 1 - Up to CCR0"]
#[inline(always)]
pub fn mc_1(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc1)
}
#[doc = "Timer A mode control: 2 - Continuous up"]
#[inline(always)]
pub fn mc_2(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc2)
}
#[doc = "Timer A mode control: 3 - Up/Down"]
#[inline(always)]
pub fn mc_3(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc3)
}
}
#[doc = "Timer A clock input divider 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Id {
#[doc = "0: Timer A input divider: 0 - /1"]
Id0 = 0,
#[doc = "1: Timer A input divider: 1 - /2"]
Id1 = 1,
#[doc = "2: Timer A input divider: 2 - /4"]
Id2 = 2,
#[doc = "3: Timer A input divider: 3 - /8"]
Id3 = 3,
}
impl From<Id> for u8 {
#[inline(always)]
fn from(variant: Id) -> Self {
variant as _
}
}
impl crate::FieldSpec for Id {
type Ux = u8;
}
impl crate::IsEnum for Id {}
#[doc = "Field `ID` reader - Timer A clock input divider 1"]
pub type IdR = crate::FieldReader<Id>;
impl IdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Id {
match self.bits {
0 => Id::Id0,
1 => Id::Id1,
2 => Id::Id2,
3 => Id::Id3,
_ => unreachable!(),
}
}
#[doc = "Timer A input divider: 0 - /1"]
#[inline(always)]
pub fn is_id_0(&self) -> bool {
*self == Id::Id0
}
#[doc = "Timer A input divider: 1 - /2"]
#[inline(always)]
pub fn is_id_1(&self) -> bool {
*self == Id::Id1
}
#[doc = "Timer A input divider: 2 - /4"]
#[inline(always)]
pub fn is_id_2(&self) -> bool {
*self == Id::Id2
}
#[doc = "Timer A input divider: 3 - /8"]
#[inline(always)]
pub fn is_id_3(&self) -> bool {
*self == Id::Id3
}
}
#[doc = "Field `ID` writer - Timer A clock input divider 1"]
pub type IdW<'a, REG> = crate::FieldWriter<'a, REG, 2, Id, crate::Safe>;
impl<'a, REG> IdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A input divider: 0 - /1"]
#[inline(always)]
pub fn id_0(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id0)
}
#[doc = "Timer A input divider: 1 - /2"]
#[inline(always)]
pub fn id_1(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id1)
}
#[doc = "Timer A input divider: 2 - /4"]
#[inline(always)]
pub fn id_2(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id2)
}
#[doc = "Timer A input divider: 3 - /8"]
#[inline(always)]
pub fn id_3(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id3)
}
}
#[doc = "Timer A clock source select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Tassel {
#[doc = "0: Timer A clock source select: 0 - TACLK"]
Tassel0 = 0,
#[doc = "1: Timer A clock source select: 1 - ACLK"]
Tassel1 = 1,
#[doc = "2: Timer A clock source select: 2 - SMCLK"]
Tassel2 = 2,
#[doc = "3: Timer A clock source select: 3 - INCLK"]
Tassel3 = 3,
}
impl From<Tassel> for u8 {
#[inline(always)]
fn from(variant: Tassel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Tassel {
type Ux = u8;
}
impl crate::IsEnum for Tassel {}
#[doc = "Field `TASSEL` reader - Timer A clock source select 1"]
pub type TasselR = crate::FieldReader<Tassel>;
impl TasselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Tassel {
match self.bits {
0 => Tassel::Tassel0,
1 => Tassel::Tassel1,
2 => Tassel::Tassel2,
3 => Tassel::Tassel3,
_ => unreachable!(),
}
}
#[doc = "Timer A clock source select: 0 - TACLK"]
#[inline(always)]
pub fn is_tassel_0(&self) -> bool {
*self == Tassel::Tassel0
}
#[doc = "Timer A clock source select: 1 - ACLK"]
#[inline(always)]
pub fn is_tassel_1(&self) -> bool {
*self == Tassel::Tassel1
}
#[doc = "Timer A clock source select: 2 - SMCLK"]
#[inline(always)]
pub fn is_tassel_2(&self) -> bool {
*self == Tassel::Tassel2
}
#[doc = "Timer A clock source select: 3 - INCLK"]
#[inline(always)]
pub fn is_tassel_3(&self) -> bool {
*self == Tassel::Tassel3
}
}
#[doc = "Field `TASSEL` writer - Timer A clock source select 1"]
pub type TasselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tassel, crate::Safe>;
impl<'a, REG> TasselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A clock source select: 0 - TACLK"]
#[inline(always)]
pub fn tassel_0(self) -> &'a mut crate::W<REG> {
self.variant(Tassel::Tassel0)
}
#[doc = "Timer A clock source select: 1 - ACLK"]
#[inline(always)]
pub fn tassel_1(self) -> &'a mut crate::W<REG> {
self.variant(Tassel::Tassel1)
}
#[doc = "Timer A clock source select: 2 - SMCLK"]
#[inline(always)]
pub fn tassel_2(self) -> &'a mut crate::W<REG> {
self.variant(Tassel::Tassel2)
}
#[doc = "Timer A clock source select: 3 - INCLK"]
#[inline(always)]
pub fn tassel_3(self) -> &'a mut crate::W<REG> {
self.variant(Tassel::Tassel3)
}
}
impl R {
#[doc = "Bit 0 - Timer A counter interrupt flag"]
#[inline(always)]
pub fn taifg(&self) -> TaifgR {
TaifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Timer A counter interrupt enable"]
#[inline(always)]
pub fn taie(&self) -> TaieR {
TaieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Timer A counter clear"]
#[inline(always)]
pub fn taclr(&self) -> TaclrR {
TaclrR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 4:5 - Timer A mode control 1"]
#[inline(always)]
pub fn mc(&self) -> McR {
McR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:7 - Timer A clock input divider 1"]
#[inline(always)]
pub fn id(&self) -> IdR {
IdR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:9 - Timer A clock source select 1"]
#[inline(always)]
pub fn tassel(&self) -> TasselR {
TasselR::new(((self.bits >> 8) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Timer A counter interrupt flag"]
#[inline(always)]
pub fn taifg(&mut self) -> TaifgW<'_, Ta2ctlSpec> {
TaifgW::new(self, 0)
}
#[doc = "Bit 1 - Timer A counter interrupt enable"]
#[inline(always)]
pub fn taie(&mut self) -> TaieW<'_, Ta2ctlSpec> {
TaieW::new(self, 1)
}
#[doc = "Bit 2 - Timer A counter clear"]
#[inline(always)]
pub fn taclr(&mut self) -> TaclrW<'_, Ta2ctlSpec> {
TaclrW::new(self, 2)
}
#[doc = "Bits 4:5 - Timer A mode control 1"]
#[inline(always)]
pub fn mc(&mut self) -> McW<'_, Ta2ctlSpec> {
McW::new(self, 4)
}
#[doc = "Bits 6:7 - Timer A clock input divider 1"]
#[inline(always)]
pub fn id(&mut self) -> IdW<'_, Ta2ctlSpec> {
IdW::new(self, 6)
}
#[doc = "Bits 8:9 - Timer A clock source select 1"]
#[inline(always)]
pub fn tassel(&mut self) -> TasselW<'_, Ta2ctlSpec> {
TasselW::new(self, 8)
}
}
#[doc = "Timer2_A2 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ta2ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta2ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta2ctlSpec;
impl crate::RegisterSpec for Ta2ctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta2ctl::R`](R) reader structure"]
impl crate::Readable for Ta2ctlSpec {}
#[doc = "`write(|w| ..)` method takes [`ta2ctl::W`](W) writer structure"]
impl crate::Writable for Ta2ctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA2CTL to value 0"]
impl crate::Resettable for Ta2ctlSpec {}
}
#[doc = "TA2CCTL0 (rw) register accessor: Timer2_A2 Capture/Compare Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta2cctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta2cctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta2cctl0`] module"]
#[doc(alias = "TA2CCTL0")]
pub type Ta2cctl0 = crate::Reg<ta2cctl0::Ta2cctl0Spec>;
#[doc = "Timer2_A2 Capture/Compare Control 0"]
pub mod ta2cctl0 {
#[doc = "Register `TA2CCTL0` reader"]
pub type R = crate::R<Ta2cctl0Spec>;
#[doc = "Register `TA2CCTL0` writer"]
pub type W = crate::W<Ta2cctl0Spec>;
#[doc = "Field `CCIFG` reader - Capture/compare interrupt flag"]
pub type CcifgR = crate::BitReader;
#[doc = "Field `CCIFG` writer - Capture/compare interrupt flag"]
pub type CcifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COV` reader - Capture/compare overflow flag"]
pub type CovR = crate::BitReader;
#[doc = "Field `COV` writer - Capture/compare overflow flag"]
pub type CovW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OUT` reader - PWM Output signal if output mode 0"]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - PWM Output signal if output mode 0"]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCI` reader - Capture input signal (read)"]
pub type CciR = crate::BitReader;
#[doc = "Field `CCI` writer - Capture input signal (read)"]
pub type CciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCIE` reader - Capture/compare interrupt enable"]
pub type CcieR = crate::BitReader;
#[doc = "Field `CCIE` writer - Capture/compare interrupt enable"]
pub type CcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output mode 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Outmod {
#[doc = "0: PWM output mode: 0 - output only"]
Outmod0 = 0,
#[doc = "1: PWM output mode: 1 - set"]
Outmod1 = 1,
#[doc = "2: PWM output mode: 2 - PWM toggle/reset"]
Outmod2 = 2,
#[doc = "3: PWM output mode: 3 - PWM set/reset"]
Outmod3 = 3,
#[doc = "4: PWM output mode: 4 - toggle"]
Outmod4 = 4,
#[doc = "5: PWM output mode: 5 - Reset"]
Outmod5 = 5,
#[doc = "6: PWM output mode: 6 - PWM toggle/set"]
Outmod6 = 6,
#[doc = "7: PWM output mode: 7 - PWM reset/set"]
Outmod7 = 7,
}
impl From<Outmod> for u8 {
#[inline(always)]
fn from(variant: Outmod) -> Self {
variant as _
}
}
impl crate::FieldSpec for Outmod {
type Ux = u8;
}
impl crate::IsEnum for Outmod {}
#[doc = "Field `OUTMOD` reader - Output mode 2"]
pub type OutmodR = crate::FieldReader<Outmod>;
impl OutmodR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Outmod {
match self.bits {
0 => Outmod::Outmod0,
1 => Outmod::Outmod1,
2 => Outmod::Outmod2,
3 => Outmod::Outmod3,
4 => Outmod::Outmod4,
5 => Outmod::Outmod5,
6 => Outmod::Outmod6,
7 => Outmod::Outmod7,
_ => unreachable!(),
}
}
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn is_outmod_0(&self) -> bool {
*self == Outmod::Outmod0
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn is_outmod_1(&self) -> bool {
*self == Outmod::Outmod1
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn is_outmod_2(&self) -> bool {
*self == Outmod::Outmod2
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn is_outmod_3(&self) -> bool {
*self == Outmod::Outmod3
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn is_outmod_4(&self) -> bool {
*self == Outmod::Outmod4
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn is_outmod_5(&self) -> bool {
*self == Outmod::Outmod5
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn is_outmod_6(&self) -> bool {
*self == Outmod::Outmod6
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn is_outmod_7(&self) -> bool {
*self == Outmod::Outmod7
}
}
#[doc = "Field `OUTMOD` writer - Output mode 2"]
pub type OutmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Outmod, crate::Safe>;
impl<'a, REG> OutmodW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn outmod_0(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod0)
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn outmod_1(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod1)
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn outmod_2(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod2)
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn outmod_3(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod3)
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn outmod_4(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod4)
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn outmod_5(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod5)
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn outmod_6(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod6)
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn outmod_7(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod7)
}
}
#[doc = "Field `CAP` reader - Capture mode: 1 /Compare mode : 0"]
pub type CapR = crate::BitReader;
#[doc = "Field `CAP` writer - Capture mode: 1 /Compare mode : 0"]
pub type CapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCCI` reader - Latched capture signal (read)"]
pub type ScciR = crate::BitReader;
#[doc = "Field `SCCI` writer - Latched capture signal (read)"]
pub type ScciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCS` reader - Capture sychronize"]
pub type ScsR = crate::BitReader;
#[doc = "Field `SCS` writer - Capture sychronize"]
pub type ScsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture input select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ccis {
#[doc = "0: Capture input select: 0 - CCIxA"]
Ccis0 = 0,
#[doc = "1: Capture input select: 1 - CCIxB"]
Ccis1 = 1,
#[doc = "2: Capture input select: 2 - GND"]
Ccis2 = 2,
#[doc = "3: Capture input select: 3 - Vcc"]
Ccis3 = 3,
}
impl From<Ccis> for u8 {
#[inline(always)]
fn from(variant: Ccis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ccis {
type Ux = u8;
}
impl crate::IsEnum for Ccis {}
#[doc = "Field `CCIS` reader - Capture input select 1"]
pub type CcisR = crate::FieldReader<Ccis>;
impl CcisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccis {
match self.bits {
0 => Ccis::Ccis0,
1 => Ccis::Ccis1,
2 => Ccis::Ccis2,
3 => Ccis::Ccis3,
_ => unreachable!(),
}
}
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn is_ccis_0(&self) -> bool {
*self == Ccis::Ccis0
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn is_ccis_1(&self) -> bool {
*self == Ccis::Ccis1
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn is_ccis_2(&self) -> bool {
*self == Ccis::Ccis2
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn is_ccis_3(&self) -> bool {
*self == Ccis::Ccis3
}
}
#[doc = "Field `CCIS` writer - Capture input select 1"]
pub type CcisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ccis, crate::Safe>;
impl<'a, REG> CcisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn ccis_0(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis0)
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn ccis_1(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis1)
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn ccis_2(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis2)
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn ccis_3(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis3)
}
}
#[doc = "Capture mode 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Capture mode: 0 - disabled"]
Cm0 = 0,
#[doc = "1: Capture mode: 1 - pos. edge"]
Cm1 = 1,
#[doc = "2: Capture mode: 1 - neg. edge"]
Cm2 = 2,
#[doc = "3: Capture mode: 1 - both edges"]
Cm3 = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Capture mode 1"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cm {
match self.bits {
0 => Cm::Cm0,
1 => Cm::Cm1,
2 => Cm::Cm2,
3 => Cm::Cm3,
_ => unreachable!(),
}
}
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn is_cm_0(&self) -> bool {
*self == Cm::Cm0
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn is_cm_1(&self) -> bool {
*self == Cm::Cm1
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn is_cm_2(&self) -> bool {
*self == Cm::Cm2
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn is_cm_3(&self) -> bool {
*self == Cm::Cm3
}
}
#[doc = "Field `CM` writer - Capture mode 1"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm, crate::Safe>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn cm_0(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm0)
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn cm_1(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm1)
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn cm_2(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm2)
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn cm_3(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm3)
}
}
impl R {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&self) -> CcifgR {
CcifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&self) -> CovR {
CovR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&self) -> CciR {
CciR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&self) -> CcieR {
CcieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&self) -> OutmodR {
OutmodR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&self) -> ScciR {
ScciR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&self) -> ScsR {
ScsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&self) -> CcisR {
CcisR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&mut self) -> CcifgW<'_, Ta2cctl0Spec> {
CcifgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&mut self) -> CovW<'_, Ta2cctl0Spec> {
CovW::new(self, 1)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&mut self) -> OutW<'_, Ta2cctl0Spec> {
OutW::new(self, 2)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&mut self) -> CciW<'_, Ta2cctl0Spec> {
CciW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&mut self) -> CcieW<'_, Ta2cctl0Spec> {
CcieW::new(self, 4)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&mut self) -> OutmodW<'_, Ta2cctl0Spec> {
OutmodW::new(self, 5)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&mut self) -> CapW<'_, Ta2cctl0Spec> {
CapW::new(self, 8)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&mut self) -> ScciW<'_, Ta2cctl0Spec> {
ScciW::new(self, 10)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&mut self) -> ScsW<'_, Ta2cctl0Spec> {
ScsW::new(self, 11)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&mut self) -> CcisW<'_, Ta2cctl0Spec> {
CcisW::new(self, 12)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<'_, Ta2cctl0Spec> {
CmW::new(self, 14)
}
}
#[doc = "Timer2_A2 Capture/Compare Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta2cctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta2cctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta2cctl0Spec;
impl crate::RegisterSpec for Ta2cctl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta2cctl0::R`](R) reader structure"]
impl crate::Readable for Ta2cctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`ta2cctl0::W`](W) writer structure"]
impl crate::Writable for Ta2cctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA2CCTL0 to value 0"]
impl crate::Resettable for Ta2cctl0Spec {}
}
#[doc = "TA2CCTL1 (rw) register accessor: Timer2_A2 Capture/Compare Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ta2cctl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta2cctl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta2cctl1`] module"]
#[doc(alias = "TA2CCTL1")]
pub type Ta2cctl1 = crate::Reg<ta2cctl1::Ta2cctl1Spec>;
#[doc = "Timer2_A2 Capture/Compare Control 1"]
pub mod ta2cctl1 {
#[doc = "Register `TA2CCTL1` reader"]
pub type R = crate::R<Ta2cctl1Spec>;
#[doc = "Register `TA2CCTL1` writer"]
pub type W = crate::W<Ta2cctl1Spec>;
#[doc = "Field `CCIFG` reader - Capture/compare interrupt flag"]
pub type CcifgR = crate::BitReader;
#[doc = "Field `CCIFG` writer - Capture/compare interrupt flag"]
pub type CcifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COV` reader - Capture/compare overflow flag"]
pub type CovR = crate::BitReader;
#[doc = "Field `COV` writer - Capture/compare overflow flag"]
pub type CovW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OUT` reader - PWM Output signal if output mode 0"]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - PWM Output signal if output mode 0"]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCI` reader - Capture input signal (read)"]
pub type CciR = crate::BitReader;
#[doc = "Field `CCI` writer - Capture input signal (read)"]
pub type CciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCIE` reader - Capture/compare interrupt enable"]
pub type CcieR = crate::BitReader;
#[doc = "Field `CCIE` writer - Capture/compare interrupt enable"]
pub type CcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output mode 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Outmod {
#[doc = "0: PWM output mode: 0 - output only"]
Outmod0 = 0,
#[doc = "1: PWM output mode: 1 - set"]
Outmod1 = 1,
#[doc = "2: PWM output mode: 2 - PWM toggle/reset"]
Outmod2 = 2,
#[doc = "3: PWM output mode: 3 - PWM set/reset"]
Outmod3 = 3,
#[doc = "4: PWM output mode: 4 - toggle"]
Outmod4 = 4,
#[doc = "5: PWM output mode: 5 - Reset"]
Outmod5 = 5,
#[doc = "6: PWM output mode: 6 - PWM toggle/set"]
Outmod6 = 6,
#[doc = "7: PWM output mode: 7 - PWM reset/set"]
Outmod7 = 7,
}
impl From<Outmod> for u8 {
#[inline(always)]
fn from(variant: Outmod) -> Self {
variant as _
}
}
impl crate::FieldSpec for Outmod {
type Ux = u8;
}
impl crate::IsEnum for Outmod {}
#[doc = "Field `OUTMOD` reader - Output mode 2"]
pub type OutmodR = crate::FieldReader<Outmod>;
impl OutmodR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Outmod {
match self.bits {
0 => Outmod::Outmod0,
1 => Outmod::Outmod1,
2 => Outmod::Outmod2,
3 => Outmod::Outmod3,
4 => Outmod::Outmod4,
5 => Outmod::Outmod5,
6 => Outmod::Outmod6,
7 => Outmod::Outmod7,
_ => unreachable!(),
}
}
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn is_outmod_0(&self) -> bool {
*self == Outmod::Outmod0
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn is_outmod_1(&self) -> bool {
*self == Outmod::Outmod1
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn is_outmod_2(&self) -> bool {
*self == Outmod::Outmod2
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn is_outmod_3(&self) -> bool {
*self == Outmod::Outmod3
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn is_outmod_4(&self) -> bool {
*self == Outmod::Outmod4
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn is_outmod_5(&self) -> bool {
*self == Outmod::Outmod5
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn is_outmod_6(&self) -> bool {
*self == Outmod::Outmod6
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn is_outmod_7(&self) -> bool {
*self == Outmod::Outmod7
}
}
#[doc = "Field `OUTMOD` writer - Output mode 2"]
pub type OutmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Outmod, crate::Safe>;
impl<'a, REG> OutmodW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn outmod_0(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod0)
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn outmod_1(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod1)
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn outmod_2(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod2)
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn outmod_3(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod3)
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn outmod_4(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod4)
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn outmod_5(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod5)
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn outmod_6(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod6)
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn outmod_7(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod7)
}
}
#[doc = "Field `CAP` reader - Capture mode: 1 /Compare mode : 0"]
pub type CapR = crate::BitReader;
#[doc = "Field `CAP` writer - Capture mode: 1 /Compare mode : 0"]
pub type CapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCCI` reader - Latched capture signal (read)"]
pub type ScciR = crate::BitReader;
#[doc = "Field `SCCI` writer - Latched capture signal (read)"]
pub type ScciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCS` reader - Capture sychronize"]
pub type ScsR = crate::BitReader;
#[doc = "Field `SCS` writer - Capture sychronize"]
pub type ScsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture input select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ccis {
#[doc = "0: Capture input select: 0 - CCIxA"]
Ccis0 = 0,
#[doc = "1: Capture input select: 1 - CCIxB"]
Ccis1 = 1,
#[doc = "2: Capture input select: 2 - GND"]
Ccis2 = 2,
#[doc = "3: Capture input select: 3 - Vcc"]
Ccis3 = 3,
}
impl From<Ccis> for u8 {
#[inline(always)]
fn from(variant: Ccis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ccis {
type Ux = u8;
}
impl crate::IsEnum for Ccis {}
#[doc = "Field `CCIS` reader - Capture input select 1"]
pub type CcisR = crate::FieldReader<Ccis>;
impl CcisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccis {
match self.bits {
0 => Ccis::Ccis0,
1 => Ccis::Ccis1,
2 => Ccis::Ccis2,
3 => Ccis::Ccis3,
_ => unreachable!(),
}
}
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn is_ccis_0(&self) -> bool {
*self == Ccis::Ccis0
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn is_ccis_1(&self) -> bool {
*self == Ccis::Ccis1
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn is_ccis_2(&self) -> bool {
*self == Ccis::Ccis2
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn is_ccis_3(&self) -> bool {
*self == Ccis::Ccis3
}
}
#[doc = "Field `CCIS` writer - Capture input select 1"]
pub type CcisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ccis, crate::Safe>;
impl<'a, REG> CcisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn ccis_0(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis0)
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn ccis_1(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis1)
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn ccis_2(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis2)
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn ccis_3(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis3)
}
}
#[doc = "Capture mode 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Capture mode: 0 - disabled"]
Cm0 = 0,
#[doc = "1: Capture mode: 1 - pos. edge"]
Cm1 = 1,
#[doc = "2: Capture mode: 1 - neg. edge"]
Cm2 = 2,
#[doc = "3: Capture mode: 1 - both edges"]
Cm3 = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Capture mode 1"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cm {
match self.bits {
0 => Cm::Cm0,
1 => Cm::Cm1,
2 => Cm::Cm2,
3 => Cm::Cm3,
_ => unreachable!(),
}
}
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn is_cm_0(&self) -> bool {
*self == Cm::Cm0
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn is_cm_1(&self) -> bool {
*self == Cm::Cm1
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn is_cm_2(&self) -> bool {
*self == Cm::Cm2
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn is_cm_3(&self) -> bool {
*self == Cm::Cm3
}
}
#[doc = "Field `CM` writer - Capture mode 1"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm, crate::Safe>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn cm_0(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm0)
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn cm_1(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm1)
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn cm_2(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm2)
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn cm_3(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm3)
}
}
impl R {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&self) -> CcifgR {
CcifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&self) -> CovR {
CovR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&self) -> CciR {
CciR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&self) -> CcieR {
CcieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&self) -> OutmodR {
OutmodR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&self) -> ScciR {
ScciR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&self) -> ScsR {
ScsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&self) -> CcisR {
CcisR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&mut self) -> CcifgW<'_, Ta2cctl1Spec> {
CcifgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&mut self) -> CovW<'_, Ta2cctl1Spec> {
CovW::new(self, 1)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&mut self) -> OutW<'_, Ta2cctl1Spec> {
OutW::new(self, 2)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&mut self) -> CciW<'_, Ta2cctl1Spec> {
CciW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&mut self) -> CcieW<'_, Ta2cctl1Spec> {
CcieW::new(self, 4)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&mut self) -> OutmodW<'_, Ta2cctl1Spec> {
OutmodW::new(self, 5)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&mut self) -> CapW<'_, Ta2cctl1Spec> {
CapW::new(self, 8)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&mut self) -> ScciW<'_, Ta2cctl1Spec> {
ScciW::new(self, 10)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&mut self) -> ScsW<'_, Ta2cctl1Spec> {
ScsW::new(self, 11)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&mut self) -> CcisW<'_, Ta2cctl1Spec> {
CcisW::new(self, 12)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<'_, Ta2cctl1Spec> {
CmW::new(self, 14)
}
}
#[doc = "Timer2_A2 Capture/Compare Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ta2cctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta2cctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta2cctl1Spec;
impl crate::RegisterSpec for Ta2cctl1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta2cctl1::R`](R) reader structure"]
impl crate::Readable for Ta2cctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`ta2cctl1::W`](W) writer structure"]
impl crate::Writable for Ta2cctl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA2CCTL1 to value 0"]
impl crate::Resettable for Ta2cctl1Spec {}
}
#[doc = "TA2R (rw) register accessor: Timer2_A2\n\nYou can [`read`](crate::Reg::read) this register and get [`ta2r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta2r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta2r`] module"]
#[doc(alias = "TA2R")]
pub type Ta2r = crate::Reg<ta2r::Ta2rSpec>;
#[doc = "Timer2_A2"]
pub mod ta2r {
#[doc = "Register `TA2R` reader"]
pub type R = crate::R<Ta2rSpec>;
#[doc = "Register `TA2R` writer"]
pub type W = crate::W<Ta2rSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer2_A2\n\nYou can [`read`](crate::Reg::read) this register and get [`ta2r::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta2r::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta2rSpec;
impl crate::RegisterSpec for Ta2rSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta2r::R`](R) reader structure"]
impl crate::Readable for Ta2rSpec {}
#[doc = "`write(|w| ..)` method takes [`ta2r::W`](W) writer structure"]
impl crate::Writable for Ta2rSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA2R to value 0"]
impl crate::Resettable for Ta2rSpec {}
}
#[doc = "TA2CCR0 (rw) register accessor: Timer2_A2 Capture/Compare 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta2ccr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta2ccr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta2ccr0`] module"]
#[doc(alias = "TA2CCR0")]
pub type Ta2ccr0 = crate::Reg<ta2ccr0::Ta2ccr0Spec>;
#[doc = "Timer2_A2 Capture/Compare 0"]
pub mod ta2ccr0 {
#[doc = "Register `TA2CCR0` reader"]
pub type R = crate::R<Ta2ccr0Spec>;
#[doc = "Register `TA2CCR0` writer"]
pub type W = crate::W<Ta2ccr0Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer2_A2 Capture/Compare 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta2ccr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta2ccr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta2ccr0Spec;
impl crate::RegisterSpec for Ta2ccr0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta2ccr0::R`](R) reader structure"]
impl crate::Readable for Ta2ccr0Spec {}
#[doc = "`write(|w| ..)` method takes [`ta2ccr0::W`](W) writer structure"]
impl crate::Writable for Ta2ccr0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA2CCR0 to value 0"]
impl crate::Resettable for Ta2ccr0Spec {}
}
#[doc = "TA2CCR1 (rw) register accessor: Timer2_A2 Capture/Compare 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ta2ccr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta2ccr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta2ccr1`] module"]
#[doc(alias = "TA2CCR1")]
pub type Ta2ccr1 = crate::Reg<ta2ccr1::Ta2ccr1Spec>;
#[doc = "Timer2_A2 Capture/Compare 1"]
pub mod ta2ccr1 {
#[doc = "Register `TA2CCR1` reader"]
pub type R = crate::R<Ta2ccr1Spec>;
#[doc = "Register `TA2CCR1` writer"]
pub type W = crate::W<Ta2ccr1Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer2_A2 Capture/Compare 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ta2ccr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta2ccr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta2ccr1Spec;
impl crate::RegisterSpec for Ta2ccr1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta2ccr1::R`](R) reader structure"]
impl crate::Readable for Ta2ccr1Spec {}
#[doc = "`write(|w| ..)` method takes [`ta2ccr1::W`](W) writer structure"]
impl crate::Writable for Ta2ccr1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA2CCR1 to value 0"]
impl crate::Resettable for Ta2ccr1Spec {}
}
#[doc = "TA2EX0 (rw) register accessor: Timer2_A2 Expansion Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta2ex0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta2ex0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta2ex0`] module"]
#[doc(alias = "TA2EX0")]
pub type Ta2ex0 = crate::Reg<ta2ex0::Ta2ex0Spec>;
#[doc = "Timer2_A2 Expansion Register 0"]
pub mod ta2ex0 {
#[doc = "Register `TA2EX0` reader"]
pub type R = crate::R<Ta2ex0Spec>;
#[doc = "Register `TA2EX0` writer"]
pub type W = crate::W<Ta2ex0Spec>;
#[doc = "Timer A Input divider expansion Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Taidex {
#[doc = "0: Timer A Input divider expansion : /1"]
Taidex0 = 0,
#[doc = "1: Timer A Input divider expansion : /2"]
Taidex1 = 1,
#[doc = "2: Timer A Input divider expansion : /3"]
Taidex2 = 2,
#[doc = "3: Timer A Input divider expansion : /4"]
Taidex3 = 3,
#[doc = "4: Timer A Input divider expansion : /5"]
Taidex4 = 4,
#[doc = "5: Timer A Input divider expansion : /6"]
Taidex5 = 5,
#[doc = "6: Timer A Input divider expansion : /7"]
Taidex6 = 6,
#[doc = "7: Timer A Input divider expansion : /8"]
Taidex7 = 7,
}
impl From<Taidex> for u8 {
#[inline(always)]
fn from(variant: Taidex) -> Self {
variant as _
}
}
impl crate::FieldSpec for Taidex {
type Ux = u8;
}
impl crate::IsEnum for Taidex {}
#[doc = "Field `TAIDEX` reader - Timer A Input divider expansion Bit: 0"]
pub type TaidexR = crate::FieldReader<Taidex>;
impl TaidexR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Taidex {
match self.bits {
0 => Taidex::Taidex0,
1 => Taidex::Taidex1,
2 => Taidex::Taidex2,
3 => Taidex::Taidex3,
4 => Taidex::Taidex4,
5 => Taidex::Taidex5,
6 => Taidex::Taidex6,
7 => Taidex::Taidex7,
_ => unreachable!(),
}
}
#[doc = "Timer A Input divider expansion : /1"]
#[inline(always)]
pub fn is_taidex_0(&self) -> bool {
*self == Taidex::Taidex0
}
#[doc = "Timer A Input divider expansion : /2"]
#[inline(always)]
pub fn is_taidex_1(&self) -> bool {
*self == Taidex::Taidex1
}
#[doc = "Timer A Input divider expansion : /3"]
#[inline(always)]
pub fn is_taidex_2(&self) -> bool {
*self == Taidex::Taidex2
}
#[doc = "Timer A Input divider expansion : /4"]
#[inline(always)]
pub fn is_taidex_3(&self) -> bool {
*self == Taidex::Taidex3
}
#[doc = "Timer A Input divider expansion : /5"]
#[inline(always)]
pub fn is_taidex_4(&self) -> bool {
*self == Taidex::Taidex4
}
#[doc = "Timer A Input divider expansion : /6"]
#[inline(always)]
pub fn is_taidex_5(&self) -> bool {
*self == Taidex::Taidex5
}
#[doc = "Timer A Input divider expansion : /7"]
#[inline(always)]
pub fn is_taidex_6(&self) -> bool {
*self == Taidex::Taidex6
}
#[doc = "Timer A Input divider expansion : /8"]
#[inline(always)]
pub fn is_taidex_7(&self) -> bool {
*self == Taidex::Taidex7
}
}
#[doc = "Field `TAIDEX` writer - Timer A Input divider expansion Bit: 0"]
pub type TaidexW<'a, REG> = crate::FieldWriter<'a, REG, 3, Taidex, crate::Safe>;
impl<'a, REG> TaidexW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A Input divider expansion : /1"]
#[inline(always)]
pub fn taidex_0(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex0)
}
#[doc = "Timer A Input divider expansion : /2"]
#[inline(always)]
pub fn taidex_1(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex1)
}
#[doc = "Timer A Input divider expansion : /3"]
#[inline(always)]
pub fn taidex_2(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex2)
}
#[doc = "Timer A Input divider expansion : /4"]
#[inline(always)]
pub fn taidex_3(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex3)
}
#[doc = "Timer A Input divider expansion : /5"]
#[inline(always)]
pub fn taidex_4(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex4)
}
#[doc = "Timer A Input divider expansion : /6"]
#[inline(always)]
pub fn taidex_5(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex5)
}
#[doc = "Timer A Input divider expansion : /7"]
#[inline(always)]
pub fn taidex_6(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex6)
}
#[doc = "Timer A Input divider expansion : /8"]
#[inline(always)]
pub fn taidex_7(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex7)
}
}
impl R {
#[doc = "Bits 0:2 - Timer A Input divider expansion Bit: 0"]
#[inline(always)]
pub fn taidex(&self) -> TaidexR {
TaidexR::new((self.bits & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:2 - Timer A Input divider expansion Bit: 0"]
#[inline(always)]
pub fn taidex(&mut self) -> TaidexW<'_, Ta2ex0Spec> {
TaidexW::new(self, 0)
}
}
#[doc = "Timer2_A2 Expansion Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta2ex0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta2ex0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta2ex0Spec;
impl crate::RegisterSpec for Ta2ex0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta2ex0::R`](R) reader structure"]
impl crate::Readable for Ta2ex0Spec {}
#[doc = "`write(|w| ..)` method takes [`ta2ex0::W`](W) writer structure"]
impl crate::Writable for Ta2ex0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA2EX0 to value 0"]
impl crate::Resettable for Ta2ex0Spec {}
}
#[doc = "TA2IV (rw) register accessor: Timer2_A2 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`ta2iv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta2iv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta2iv`] module"]
#[doc(alias = "TA2IV")]
pub type Ta2iv = crate::Reg<ta2iv::Ta2ivSpec>;
#[doc = "Timer2_A2 Interrupt Vector Word"]
pub mod ta2iv {
#[doc = "Register `TA2IV` reader"]
pub type R = crate::R<Ta2ivSpec>;
#[doc = "Register `TA2IV` writer"]
pub type W = crate::W<Ta2ivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer2_A2 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`ta2iv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta2iv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta2ivSpec;
impl crate::RegisterSpec for Ta2ivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta2iv::R`](R) reader structure"]
impl crate::Readable for Ta2ivSpec {}
#[doc = "`write(|w| ..)` method takes [`ta2iv::W`](W) writer structure"]
impl crate::Writable for Ta2ivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA2IV to value 0"]
impl crate::Resettable for Ta2ivSpec {}
}
}
#[doc = "Capacitive_Touch_IO 0"]
pub type CapacitiveTouchIo0 = crate::Periph<capacitive_touch_io_0::RegisterBlock, 0x043e>;
impl core::fmt::Debug for CapacitiveTouchIo0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CapacitiveTouchIo0").finish()
}
}
#[doc = "Capacitive_Touch_IO 0"]
pub mod capacitive_touch_io_0 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
captio0ctl: Captio0ctl,
}
impl RegisterBlock {
#[doc = "0x00 - Capacitive_Touch_IO 0 control register"]
#[inline(always)]
pub const fn captio0ctl(&self) -> &Captio0ctl {
&self.captio0ctl
}
}
#[doc = "CAPTIO0CTL (rw) register accessor: Capacitive_Touch_IO 0 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`captio0ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`captio0ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@captio0ctl`] module"]
#[doc(alias = "CAPTIO0CTL")]
pub type Captio0ctl = crate::Reg<captio0ctl::Captio0ctlSpec>;
#[doc = "Capacitive_Touch_IO 0 control register"]
pub mod captio0ctl {
#[doc = "Register `CAPTIO0CTL` reader"]
pub type R = crate::R<Captio0ctlSpec>;
#[doc = "Register `CAPTIO0CTL` writer"]
pub type W = crate::W<Captio0ctlSpec>;
#[doc = "Field `CAPTIOPISEL0` reader - CapTouchIO Pin Select Bit: 0"]
pub type Captiopisel0R = crate::BitReader;
#[doc = "Field `CAPTIOPISEL0` writer - CapTouchIO Pin Select Bit: 0"]
pub type Captiopisel0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAPTIOPISEL1` reader - CapTouchIO Pin Select Bit: 1"]
pub type Captiopisel1R = crate::BitReader;
#[doc = "Field `CAPTIOPISEL1` writer - CapTouchIO Pin Select Bit: 1"]
pub type Captiopisel1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAPTIOPISEL2` reader - CapTouchIO Pin Select Bit: 2"]
pub type Captiopisel2R = crate::BitReader;
#[doc = "Field `CAPTIOPISEL2` writer - CapTouchIO Pin Select Bit: 2"]
pub type Captiopisel2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAPTIOPOSEL0` reader - CapTouchIO Port Select Bit: 0"]
pub type Captioposel0R = crate::BitReader;
#[doc = "Field `CAPTIOPOSEL0` writer - CapTouchIO Port Select Bit: 0"]
pub type Captioposel0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAPTIOPOSEL1` reader - CapTouchIO Port Select Bit: 1"]
pub type Captioposel1R = crate::BitReader;
#[doc = "Field `CAPTIOPOSEL1` writer - CapTouchIO Port Select Bit: 1"]
pub type Captioposel1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAPTIOPOSEL2` reader - CapTouchIO Port Select Bit: 2"]
pub type Captioposel2R = crate::BitReader;
#[doc = "Field `CAPTIOPOSEL2` writer - CapTouchIO Port Select Bit: 2"]
pub type Captioposel2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAPTIOPOSEL3` reader - CapTouchIO Port Select Bit: 3"]
pub type Captioposel3R = crate::BitReader;
#[doc = "Field `CAPTIOPOSEL3` writer - CapTouchIO Port Select Bit: 3"]
pub type Captioposel3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAPTIOEN` reader - CapTouchIO Enable"]
pub type CaptioenR = crate::BitReader;
#[doc = "Field `CAPTIOEN` writer - CapTouchIO Enable"]
pub type CaptioenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAPTIO` reader - CapTouchIO state"]
pub type CaptioR = crate::BitReader;
#[doc = "Field `CAPTIO` writer - CapTouchIO state"]
pub type CaptioW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 1 - CapTouchIO Pin Select Bit: 0"]
#[inline(always)]
pub fn captiopisel0(&self) -> Captiopisel0R {
Captiopisel0R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - CapTouchIO Pin Select Bit: 1"]
#[inline(always)]
pub fn captiopisel1(&self) -> Captiopisel1R {
Captiopisel1R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - CapTouchIO Pin Select Bit: 2"]
#[inline(always)]
pub fn captiopisel2(&self) -> Captiopisel2R {
Captiopisel2R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - CapTouchIO Port Select Bit: 0"]
#[inline(always)]
pub fn captioposel0(&self) -> Captioposel0R {
Captioposel0R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - CapTouchIO Port Select Bit: 1"]
#[inline(always)]
pub fn captioposel1(&self) -> Captioposel1R {
Captioposel1R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - CapTouchIO Port Select Bit: 2"]
#[inline(always)]
pub fn captioposel2(&self) -> Captioposel2R {
Captioposel2R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - CapTouchIO Port Select Bit: 3"]
#[inline(always)]
pub fn captioposel3(&self) -> Captioposel3R {
Captioposel3R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - CapTouchIO Enable"]
#[inline(always)]
pub fn captioen(&self) -> CaptioenR {
CaptioenR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - CapTouchIO state"]
#[inline(always)]
pub fn captio(&self) -> CaptioR {
CaptioR::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1 - CapTouchIO Pin Select Bit: 0"]
#[inline(always)]
pub fn captiopisel0(&mut self) -> Captiopisel0W<'_, Captio0ctlSpec> {
Captiopisel0W::new(self, 1)
}
#[doc = "Bit 2 - CapTouchIO Pin Select Bit: 1"]
#[inline(always)]
pub fn captiopisel1(&mut self) -> Captiopisel1W<'_, Captio0ctlSpec> {
Captiopisel1W::new(self, 2)
}
#[doc = "Bit 3 - CapTouchIO Pin Select Bit: 2"]
#[inline(always)]
pub fn captiopisel2(&mut self) -> Captiopisel2W<'_, Captio0ctlSpec> {
Captiopisel2W::new(self, 3)
}
#[doc = "Bit 4 - CapTouchIO Port Select Bit: 0"]
#[inline(always)]
pub fn captioposel0(&mut self) -> Captioposel0W<'_, Captio0ctlSpec> {
Captioposel0W::new(self, 4)
}
#[doc = "Bit 5 - CapTouchIO Port Select Bit: 1"]
#[inline(always)]
pub fn captioposel1(&mut self) -> Captioposel1W<'_, Captio0ctlSpec> {
Captioposel1W::new(self, 5)
}
#[doc = "Bit 6 - CapTouchIO Port Select Bit: 2"]
#[inline(always)]
pub fn captioposel2(&mut self) -> Captioposel2W<'_, Captio0ctlSpec> {
Captioposel2W::new(self, 6)
}
#[doc = "Bit 7 - CapTouchIO Port Select Bit: 3"]
#[inline(always)]
pub fn captioposel3(&mut self) -> Captioposel3W<'_, Captio0ctlSpec> {
Captioposel3W::new(self, 7)
}
#[doc = "Bit 8 - CapTouchIO Enable"]
#[inline(always)]
pub fn captioen(&mut self) -> CaptioenW<'_, Captio0ctlSpec> {
CaptioenW::new(self, 8)
}
#[doc = "Bit 9 - CapTouchIO state"]
#[inline(always)]
pub fn captio(&mut self) -> CaptioW<'_, Captio0ctlSpec> {
CaptioW::new(self, 9)
}
}
#[doc = "Capacitive_Touch_IO 0 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`captio0ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`captio0ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Captio0ctlSpec;
impl crate::RegisterSpec for Captio0ctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`captio0ctl::R`](R) reader structure"]
impl crate::Readable for Captio0ctlSpec {}
#[doc = "`write(|w| ..)` method takes [`captio0ctl::W`](W) writer structure"]
impl crate::Writable for Captio0ctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CAPTIO0CTL to value 0"]
impl crate::Resettable for Captio0ctlSpec {}
}
}
#[doc = "Timer3_A2"]
pub type Timer3A2 = crate::Periph<timer_3_a2::RegisterBlock, 0x0440>;
impl core::fmt::Debug for Timer3A2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Timer3A2").finish()
}
}
#[doc = "Timer3_A2"]
pub mod timer_3_a2 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
ta3ctl: Ta3ctl,
ta3cctl0: Ta3cctl0,
ta3cctl1: Ta3cctl1,
_reserved3: [u8; 0x0a],
ta3r: Ta3r,
ta3ccr0: Ta3ccr0,
ta3ccr1: Ta3ccr1,
_reserved6: [u8; 0x0a],
ta3ex0: Ta3ex0,
_reserved7: [u8; 0x0c],
ta3iv: Ta3iv,
}
impl RegisterBlock {
#[doc = "0x00 - Timer3_A2 Control"]
#[inline(always)]
pub const fn ta3ctl(&self) -> &Ta3ctl {
&self.ta3ctl
}
#[doc = "0x02 - Timer3_A2 Capture/Compare Control 0"]
#[inline(always)]
pub const fn ta3cctl0(&self) -> &Ta3cctl0 {
&self.ta3cctl0
}
#[doc = "0x04 - Timer3_A2 Capture/Compare Control 1"]
#[inline(always)]
pub const fn ta3cctl1(&self) -> &Ta3cctl1 {
&self.ta3cctl1
}
#[doc = "0x10 - Timer3_A2"]
#[inline(always)]
pub const fn ta3r(&self) -> &Ta3r {
&self.ta3r
}
#[doc = "0x12 - Timer3_A2 Capture/Compare 0"]
#[inline(always)]
pub const fn ta3ccr0(&self) -> &Ta3ccr0 {
&self.ta3ccr0
}
#[doc = "0x14 - Timer3_A2 Capture/Compare 1"]
#[inline(always)]
pub const fn ta3ccr1(&self) -> &Ta3ccr1 {
&self.ta3ccr1
}
#[doc = "0x20 - Timer3_A2 Expansion Register 0"]
#[inline(always)]
pub const fn ta3ex0(&self) -> &Ta3ex0 {
&self.ta3ex0
}
#[doc = "0x2e - Timer3_A2 Interrupt Vector Word"]
#[inline(always)]
pub const fn ta3iv(&self) -> &Ta3iv {
&self.ta3iv
}
}
#[doc = "TA3CTL (rw) register accessor: Timer3_A2 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ta3ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta3ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta3ctl`] module"]
#[doc(alias = "TA3CTL")]
pub type Ta3ctl = crate::Reg<ta3ctl::Ta3ctlSpec>;
#[doc = "Timer3_A2 Control"]
pub mod ta3ctl {
#[doc = "Register `TA3CTL` reader"]
pub type R = crate::R<Ta3ctlSpec>;
#[doc = "Register `TA3CTL` writer"]
pub type W = crate::W<Ta3ctlSpec>;
#[doc = "Field `TAIFG` reader - Timer A counter interrupt flag"]
pub type TaifgR = crate::BitReader;
#[doc = "Field `TAIFG` writer - Timer A counter interrupt flag"]
pub type TaifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TAIE` reader - Timer A counter interrupt enable"]
pub type TaieR = crate::BitReader;
#[doc = "Field `TAIE` writer - Timer A counter interrupt enable"]
pub type TaieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TACLR` reader - Timer A counter clear"]
pub type TaclrR = crate::BitReader;
#[doc = "Field `TACLR` writer - Timer A counter clear"]
pub type TaclrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Timer A mode control 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mc {
#[doc = "0: Timer A mode control: 0 - Stop"]
Mc0 = 0,
#[doc = "1: Timer A mode control: 1 - Up to CCR0"]
Mc1 = 1,
#[doc = "2: Timer A mode control: 2 - Continuous up"]
Mc2 = 2,
#[doc = "3: Timer A mode control: 3 - Up/Down"]
Mc3 = 3,
}
impl From<Mc> for u8 {
#[inline(always)]
fn from(variant: Mc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mc {
type Ux = u8;
}
impl crate::IsEnum for Mc {}
#[doc = "Field `MC` reader - Timer A mode control 1"]
pub type McR = crate::FieldReader<Mc>;
impl McR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mc {
match self.bits {
0 => Mc::Mc0,
1 => Mc::Mc1,
2 => Mc::Mc2,
3 => Mc::Mc3,
_ => unreachable!(),
}
}
#[doc = "Timer A mode control: 0 - Stop"]
#[inline(always)]
pub fn is_mc_0(&self) -> bool {
*self == Mc::Mc0
}
#[doc = "Timer A mode control: 1 - Up to CCR0"]
#[inline(always)]
pub fn is_mc_1(&self) -> bool {
*self == Mc::Mc1
}
#[doc = "Timer A mode control: 2 - Continuous up"]
#[inline(always)]
pub fn is_mc_2(&self) -> bool {
*self == Mc::Mc2
}
#[doc = "Timer A mode control: 3 - Up/Down"]
#[inline(always)]
pub fn is_mc_3(&self) -> bool {
*self == Mc::Mc3
}
}
#[doc = "Field `MC` writer - Timer A mode control 1"]
pub type McW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mc, crate::Safe>;
impl<'a, REG> McW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A mode control: 0 - Stop"]
#[inline(always)]
pub fn mc_0(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc0)
}
#[doc = "Timer A mode control: 1 - Up to CCR0"]
#[inline(always)]
pub fn mc_1(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc1)
}
#[doc = "Timer A mode control: 2 - Continuous up"]
#[inline(always)]
pub fn mc_2(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc2)
}
#[doc = "Timer A mode control: 3 - Up/Down"]
#[inline(always)]
pub fn mc_3(self) -> &'a mut crate::W<REG> {
self.variant(Mc::Mc3)
}
}
#[doc = "Timer A clock input divider 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Id {
#[doc = "0: Timer A input divider: 0 - /1"]
Id0 = 0,
#[doc = "1: Timer A input divider: 1 - /2"]
Id1 = 1,
#[doc = "2: Timer A input divider: 2 - /4"]
Id2 = 2,
#[doc = "3: Timer A input divider: 3 - /8"]
Id3 = 3,
}
impl From<Id> for u8 {
#[inline(always)]
fn from(variant: Id) -> Self {
variant as _
}
}
impl crate::FieldSpec for Id {
type Ux = u8;
}
impl crate::IsEnum for Id {}
#[doc = "Field `ID` reader - Timer A clock input divider 1"]
pub type IdR = crate::FieldReader<Id>;
impl IdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Id {
match self.bits {
0 => Id::Id0,
1 => Id::Id1,
2 => Id::Id2,
3 => Id::Id3,
_ => unreachable!(),
}
}
#[doc = "Timer A input divider: 0 - /1"]
#[inline(always)]
pub fn is_id_0(&self) -> bool {
*self == Id::Id0
}
#[doc = "Timer A input divider: 1 - /2"]
#[inline(always)]
pub fn is_id_1(&self) -> bool {
*self == Id::Id1
}
#[doc = "Timer A input divider: 2 - /4"]
#[inline(always)]
pub fn is_id_2(&self) -> bool {
*self == Id::Id2
}
#[doc = "Timer A input divider: 3 - /8"]
#[inline(always)]
pub fn is_id_3(&self) -> bool {
*self == Id::Id3
}
}
#[doc = "Field `ID` writer - Timer A clock input divider 1"]
pub type IdW<'a, REG> = crate::FieldWriter<'a, REG, 2, Id, crate::Safe>;
impl<'a, REG> IdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A input divider: 0 - /1"]
#[inline(always)]
pub fn id_0(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id0)
}
#[doc = "Timer A input divider: 1 - /2"]
#[inline(always)]
pub fn id_1(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id1)
}
#[doc = "Timer A input divider: 2 - /4"]
#[inline(always)]
pub fn id_2(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id2)
}
#[doc = "Timer A input divider: 3 - /8"]
#[inline(always)]
pub fn id_3(self) -> &'a mut crate::W<REG> {
self.variant(Id::Id3)
}
}
#[doc = "Timer A clock source select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Tassel {
#[doc = "0: Timer A clock source select: 0 - TACLK"]
Tassel0 = 0,
#[doc = "1: Timer A clock source select: 1 - ACLK"]
Tassel1 = 1,
#[doc = "2: Timer A clock source select: 2 - SMCLK"]
Tassel2 = 2,
#[doc = "3: Timer A clock source select: 3 - INCLK"]
Tassel3 = 3,
}
impl From<Tassel> for u8 {
#[inline(always)]
fn from(variant: Tassel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Tassel {
type Ux = u8;
}
impl crate::IsEnum for Tassel {}
#[doc = "Field `TASSEL` reader - Timer A clock source select 1"]
pub type TasselR = crate::FieldReader<Tassel>;
impl TasselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Tassel {
match self.bits {
0 => Tassel::Tassel0,
1 => Tassel::Tassel1,
2 => Tassel::Tassel2,
3 => Tassel::Tassel3,
_ => unreachable!(),
}
}
#[doc = "Timer A clock source select: 0 - TACLK"]
#[inline(always)]
pub fn is_tassel_0(&self) -> bool {
*self == Tassel::Tassel0
}
#[doc = "Timer A clock source select: 1 - ACLK"]
#[inline(always)]
pub fn is_tassel_1(&self) -> bool {
*self == Tassel::Tassel1
}
#[doc = "Timer A clock source select: 2 - SMCLK"]
#[inline(always)]
pub fn is_tassel_2(&self) -> bool {
*self == Tassel::Tassel2
}
#[doc = "Timer A clock source select: 3 - INCLK"]
#[inline(always)]
pub fn is_tassel_3(&self) -> bool {
*self == Tassel::Tassel3
}
}
#[doc = "Field `TASSEL` writer - Timer A clock source select 1"]
pub type TasselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tassel, crate::Safe>;
impl<'a, REG> TasselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A clock source select: 0 - TACLK"]
#[inline(always)]
pub fn tassel_0(self) -> &'a mut crate::W<REG> {
self.variant(Tassel::Tassel0)
}
#[doc = "Timer A clock source select: 1 - ACLK"]
#[inline(always)]
pub fn tassel_1(self) -> &'a mut crate::W<REG> {
self.variant(Tassel::Tassel1)
}
#[doc = "Timer A clock source select: 2 - SMCLK"]
#[inline(always)]
pub fn tassel_2(self) -> &'a mut crate::W<REG> {
self.variant(Tassel::Tassel2)
}
#[doc = "Timer A clock source select: 3 - INCLK"]
#[inline(always)]
pub fn tassel_3(self) -> &'a mut crate::W<REG> {
self.variant(Tassel::Tassel3)
}
}
impl R {
#[doc = "Bit 0 - Timer A counter interrupt flag"]
#[inline(always)]
pub fn taifg(&self) -> TaifgR {
TaifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Timer A counter interrupt enable"]
#[inline(always)]
pub fn taie(&self) -> TaieR {
TaieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Timer A counter clear"]
#[inline(always)]
pub fn taclr(&self) -> TaclrR {
TaclrR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 4:5 - Timer A mode control 1"]
#[inline(always)]
pub fn mc(&self) -> McR {
McR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:7 - Timer A clock input divider 1"]
#[inline(always)]
pub fn id(&self) -> IdR {
IdR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:9 - Timer A clock source select 1"]
#[inline(always)]
pub fn tassel(&self) -> TasselR {
TasselR::new(((self.bits >> 8) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Timer A counter interrupt flag"]
#[inline(always)]
pub fn taifg(&mut self) -> TaifgW<'_, Ta3ctlSpec> {
TaifgW::new(self, 0)
}
#[doc = "Bit 1 - Timer A counter interrupt enable"]
#[inline(always)]
pub fn taie(&mut self) -> TaieW<'_, Ta3ctlSpec> {
TaieW::new(self, 1)
}
#[doc = "Bit 2 - Timer A counter clear"]
#[inline(always)]
pub fn taclr(&mut self) -> TaclrW<'_, Ta3ctlSpec> {
TaclrW::new(self, 2)
}
#[doc = "Bits 4:5 - Timer A mode control 1"]
#[inline(always)]
pub fn mc(&mut self) -> McW<'_, Ta3ctlSpec> {
McW::new(self, 4)
}
#[doc = "Bits 6:7 - Timer A clock input divider 1"]
#[inline(always)]
pub fn id(&mut self) -> IdW<'_, Ta3ctlSpec> {
IdW::new(self, 6)
}
#[doc = "Bits 8:9 - Timer A clock source select 1"]
#[inline(always)]
pub fn tassel(&mut self) -> TasselW<'_, Ta3ctlSpec> {
TasselW::new(self, 8)
}
}
#[doc = "Timer3_A2 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ta3ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta3ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta3ctlSpec;
impl crate::RegisterSpec for Ta3ctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta3ctl::R`](R) reader structure"]
impl crate::Readable for Ta3ctlSpec {}
#[doc = "`write(|w| ..)` method takes [`ta3ctl::W`](W) writer structure"]
impl crate::Writable for Ta3ctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA3CTL to value 0"]
impl crate::Resettable for Ta3ctlSpec {}
}
#[doc = "TA3CCTL0 (rw) register accessor: Timer3_A2 Capture/Compare Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta3cctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta3cctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta3cctl0`] module"]
#[doc(alias = "TA3CCTL0")]
pub type Ta3cctl0 = crate::Reg<ta3cctl0::Ta3cctl0Spec>;
#[doc = "Timer3_A2 Capture/Compare Control 0"]
pub mod ta3cctl0 {
#[doc = "Register `TA3CCTL0` reader"]
pub type R = crate::R<Ta3cctl0Spec>;
#[doc = "Register `TA3CCTL0` writer"]
pub type W = crate::W<Ta3cctl0Spec>;
#[doc = "Field `CCIFG` reader - Capture/compare interrupt flag"]
pub type CcifgR = crate::BitReader;
#[doc = "Field `CCIFG` writer - Capture/compare interrupt flag"]
pub type CcifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COV` reader - Capture/compare overflow flag"]
pub type CovR = crate::BitReader;
#[doc = "Field `COV` writer - Capture/compare overflow flag"]
pub type CovW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OUT` reader - PWM Output signal if output mode 0"]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - PWM Output signal if output mode 0"]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCI` reader - Capture input signal (read)"]
pub type CciR = crate::BitReader;
#[doc = "Field `CCI` writer - Capture input signal (read)"]
pub type CciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCIE` reader - Capture/compare interrupt enable"]
pub type CcieR = crate::BitReader;
#[doc = "Field `CCIE` writer - Capture/compare interrupt enable"]
pub type CcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output mode 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Outmod {
#[doc = "0: PWM output mode: 0 - output only"]
Outmod0 = 0,
#[doc = "1: PWM output mode: 1 - set"]
Outmod1 = 1,
#[doc = "2: PWM output mode: 2 - PWM toggle/reset"]
Outmod2 = 2,
#[doc = "3: PWM output mode: 3 - PWM set/reset"]
Outmod3 = 3,
#[doc = "4: PWM output mode: 4 - toggle"]
Outmod4 = 4,
#[doc = "5: PWM output mode: 5 - Reset"]
Outmod5 = 5,
#[doc = "6: PWM output mode: 6 - PWM toggle/set"]
Outmod6 = 6,
#[doc = "7: PWM output mode: 7 - PWM reset/set"]
Outmod7 = 7,
}
impl From<Outmod> for u8 {
#[inline(always)]
fn from(variant: Outmod) -> Self {
variant as _
}
}
impl crate::FieldSpec for Outmod {
type Ux = u8;
}
impl crate::IsEnum for Outmod {}
#[doc = "Field `OUTMOD` reader - Output mode 2"]
pub type OutmodR = crate::FieldReader<Outmod>;
impl OutmodR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Outmod {
match self.bits {
0 => Outmod::Outmod0,
1 => Outmod::Outmod1,
2 => Outmod::Outmod2,
3 => Outmod::Outmod3,
4 => Outmod::Outmod4,
5 => Outmod::Outmod5,
6 => Outmod::Outmod6,
7 => Outmod::Outmod7,
_ => unreachable!(),
}
}
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn is_outmod_0(&self) -> bool {
*self == Outmod::Outmod0
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn is_outmod_1(&self) -> bool {
*self == Outmod::Outmod1
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn is_outmod_2(&self) -> bool {
*self == Outmod::Outmod2
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn is_outmod_3(&self) -> bool {
*self == Outmod::Outmod3
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn is_outmod_4(&self) -> bool {
*self == Outmod::Outmod4
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn is_outmod_5(&self) -> bool {
*self == Outmod::Outmod5
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn is_outmod_6(&self) -> bool {
*self == Outmod::Outmod6
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn is_outmod_7(&self) -> bool {
*self == Outmod::Outmod7
}
}
#[doc = "Field `OUTMOD` writer - Output mode 2"]
pub type OutmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Outmod, crate::Safe>;
impl<'a, REG> OutmodW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn outmod_0(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod0)
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn outmod_1(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod1)
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn outmod_2(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod2)
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn outmod_3(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod3)
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn outmod_4(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod4)
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn outmod_5(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod5)
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn outmod_6(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod6)
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn outmod_7(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod7)
}
}
#[doc = "Field `CAP` reader - Capture mode: 1 /Compare mode : 0"]
pub type CapR = crate::BitReader;
#[doc = "Field `CAP` writer - Capture mode: 1 /Compare mode : 0"]
pub type CapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCCI` reader - Latched capture signal (read)"]
pub type ScciR = crate::BitReader;
#[doc = "Field `SCCI` writer - Latched capture signal (read)"]
pub type ScciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCS` reader - Capture sychronize"]
pub type ScsR = crate::BitReader;
#[doc = "Field `SCS` writer - Capture sychronize"]
pub type ScsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture input select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ccis {
#[doc = "0: Capture input select: 0 - CCIxA"]
Ccis0 = 0,
#[doc = "1: Capture input select: 1 - CCIxB"]
Ccis1 = 1,
#[doc = "2: Capture input select: 2 - GND"]
Ccis2 = 2,
#[doc = "3: Capture input select: 3 - Vcc"]
Ccis3 = 3,
}
impl From<Ccis> for u8 {
#[inline(always)]
fn from(variant: Ccis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ccis {
type Ux = u8;
}
impl crate::IsEnum for Ccis {}
#[doc = "Field `CCIS` reader - Capture input select 1"]
pub type CcisR = crate::FieldReader<Ccis>;
impl CcisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccis {
match self.bits {
0 => Ccis::Ccis0,
1 => Ccis::Ccis1,
2 => Ccis::Ccis2,
3 => Ccis::Ccis3,
_ => unreachable!(),
}
}
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn is_ccis_0(&self) -> bool {
*self == Ccis::Ccis0
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn is_ccis_1(&self) -> bool {
*self == Ccis::Ccis1
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn is_ccis_2(&self) -> bool {
*self == Ccis::Ccis2
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn is_ccis_3(&self) -> bool {
*self == Ccis::Ccis3
}
}
#[doc = "Field `CCIS` writer - Capture input select 1"]
pub type CcisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ccis, crate::Safe>;
impl<'a, REG> CcisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn ccis_0(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis0)
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn ccis_1(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis1)
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn ccis_2(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis2)
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn ccis_3(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis3)
}
}
#[doc = "Capture mode 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Capture mode: 0 - disabled"]
Cm0 = 0,
#[doc = "1: Capture mode: 1 - pos. edge"]
Cm1 = 1,
#[doc = "2: Capture mode: 1 - neg. edge"]
Cm2 = 2,
#[doc = "3: Capture mode: 1 - both edges"]
Cm3 = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Capture mode 1"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cm {
match self.bits {
0 => Cm::Cm0,
1 => Cm::Cm1,
2 => Cm::Cm2,
3 => Cm::Cm3,
_ => unreachable!(),
}
}
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn is_cm_0(&self) -> bool {
*self == Cm::Cm0
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn is_cm_1(&self) -> bool {
*self == Cm::Cm1
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn is_cm_2(&self) -> bool {
*self == Cm::Cm2
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn is_cm_3(&self) -> bool {
*self == Cm::Cm3
}
}
#[doc = "Field `CM` writer - Capture mode 1"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm, crate::Safe>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn cm_0(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm0)
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn cm_1(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm1)
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn cm_2(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm2)
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn cm_3(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm3)
}
}
impl R {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&self) -> CcifgR {
CcifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&self) -> CovR {
CovR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&self) -> CciR {
CciR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&self) -> CcieR {
CcieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&self) -> OutmodR {
OutmodR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&self) -> ScciR {
ScciR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&self) -> ScsR {
ScsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&self) -> CcisR {
CcisR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&mut self) -> CcifgW<'_, Ta3cctl0Spec> {
CcifgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&mut self) -> CovW<'_, Ta3cctl0Spec> {
CovW::new(self, 1)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&mut self) -> OutW<'_, Ta3cctl0Spec> {
OutW::new(self, 2)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&mut self) -> CciW<'_, Ta3cctl0Spec> {
CciW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&mut self) -> CcieW<'_, Ta3cctl0Spec> {
CcieW::new(self, 4)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&mut self) -> OutmodW<'_, Ta3cctl0Spec> {
OutmodW::new(self, 5)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&mut self) -> CapW<'_, Ta3cctl0Spec> {
CapW::new(self, 8)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&mut self) -> ScciW<'_, Ta3cctl0Spec> {
ScciW::new(self, 10)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&mut self) -> ScsW<'_, Ta3cctl0Spec> {
ScsW::new(self, 11)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&mut self) -> CcisW<'_, Ta3cctl0Spec> {
CcisW::new(self, 12)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<'_, Ta3cctl0Spec> {
CmW::new(self, 14)
}
}
#[doc = "Timer3_A2 Capture/Compare Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta3cctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta3cctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta3cctl0Spec;
impl crate::RegisterSpec for Ta3cctl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta3cctl0::R`](R) reader structure"]
impl crate::Readable for Ta3cctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`ta3cctl0::W`](W) writer structure"]
impl crate::Writable for Ta3cctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA3CCTL0 to value 0"]
impl crate::Resettable for Ta3cctl0Spec {}
}
#[doc = "TA3CCTL1 (rw) register accessor: Timer3_A2 Capture/Compare Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ta3cctl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta3cctl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta3cctl1`] module"]
#[doc(alias = "TA3CCTL1")]
pub type Ta3cctl1 = crate::Reg<ta3cctl1::Ta3cctl1Spec>;
#[doc = "Timer3_A2 Capture/Compare Control 1"]
pub mod ta3cctl1 {
#[doc = "Register `TA3CCTL1` reader"]
pub type R = crate::R<Ta3cctl1Spec>;
#[doc = "Register `TA3CCTL1` writer"]
pub type W = crate::W<Ta3cctl1Spec>;
#[doc = "Field `CCIFG` reader - Capture/compare interrupt flag"]
pub type CcifgR = crate::BitReader;
#[doc = "Field `CCIFG` writer - Capture/compare interrupt flag"]
pub type CcifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COV` reader - Capture/compare overflow flag"]
pub type CovR = crate::BitReader;
#[doc = "Field `COV` writer - Capture/compare overflow flag"]
pub type CovW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OUT` reader - PWM Output signal if output mode 0"]
pub type OutR = crate::BitReader;
#[doc = "Field `OUT` writer - PWM Output signal if output mode 0"]
pub type OutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCI` reader - Capture input signal (read)"]
pub type CciR = crate::BitReader;
#[doc = "Field `CCI` writer - Capture input signal (read)"]
pub type CciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CCIE` reader - Capture/compare interrupt enable"]
pub type CcieR = crate::BitReader;
#[doc = "Field `CCIE` writer - Capture/compare interrupt enable"]
pub type CcieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output mode 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Outmod {
#[doc = "0: PWM output mode: 0 - output only"]
Outmod0 = 0,
#[doc = "1: PWM output mode: 1 - set"]
Outmod1 = 1,
#[doc = "2: PWM output mode: 2 - PWM toggle/reset"]
Outmod2 = 2,
#[doc = "3: PWM output mode: 3 - PWM set/reset"]
Outmod3 = 3,
#[doc = "4: PWM output mode: 4 - toggle"]
Outmod4 = 4,
#[doc = "5: PWM output mode: 5 - Reset"]
Outmod5 = 5,
#[doc = "6: PWM output mode: 6 - PWM toggle/set"]
Outmod6 = 6,
#[doc = "7: PWM output mode: 7 - PWM reset/set"]
Outmod7 = 7,
}
impl From<Outmod> for u8 {
#[inline(always)]
fn from(variant: Outmod) -> Self {
variant as _
}
}
impl crate::FieldSpec for Outmod {
type Ux = u8;
}
impl crate::IsEnum for Outmod {}
#[doc = "Field `OUTMOD` reader - Output mode 2"]
pub type OutmodR = crate::FieldReader<Outmod>;
impl OutmodR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Outmod {
match self.bits {
0 => Outmod::Outmod0,
1 => Outmod::Outmod1,
2 => Outmod::Outmod2,
3 => Outmod::Outmod3,
4 => Outmod::Outmod4,
5 => Outmod::Outmod5,
6 => Outmod::Outmod6,
7 => Outmod::Outmod7,
_ => unreachable!(),
}
}
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn is_outmod_0(&self) -> bool {
*self == Outmod::Outmod0
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn is_outmod_1(&self) -> bool {
*self == Outmod::Outmod1
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn is_outmod_2(&self) -> bool {
*self == Outmod::Outmod2
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn is_outmod_3(&self) -> bool {
*self == Outmod::Outmod3
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn is_outmod_4(&self) -> bool {
*self == Outmod::Outmod4
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn is_outmod_5(&self) -> bool {
*self == Outmod::Outmod5
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn is_outmod_6(&self) -> bool {
*self == Outmod::Outmod6
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn is_outmod_7(&self) -> bool {
*self == Outmod::Outmod7
}
}
#[doc = "Field `OUTMOD` writer - Output mode 2"]
pub type OutmodW<'a, REG> = crate::FieldWriter<'a, REG, 3, Outmod, crate::Safe>;
impl<'a, REG> OutmodW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "PWM output mode: 0 - output only"]
#[inline(always)]
pub fn outmod_0(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod0)
}
#[doc = "PWM output mode: 1 - set"]
#[inline(always)]
pub fn outmod_1(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod1)
}
#[doc = "PWM output mode: 2 - PWM toggle/reset"]
#[inline(always)]
pub fn outmod_2(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod2)
}
#[doc = "PWM output mode: 3 - PWM set/reset"]
#[inline(always)]
pub fn outmod_3(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod3)
}
#[doc = "PWM output mode: 4 - toggle"]
#[inline(always)]
pub fn outmod_4(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod4)
}
#[doc = "PWM output mode: 5 - Reset"]
#[inline(always)]
pub fn outmod_5(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod5)
}
#[doc = "PWM output mode: 6 - PWM toggle/set"]
#[inline(always)]
pub fn outmod_6(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod6)
}
#[doc = "PWM output mode: 7 - PWM reset/set"]
#[inline(always)]
pub fn outmod_7(self) -> &'a mut crate::W<REG> {
self.variant(Outmod::Outmod7)
}
}
#[doc = "Field `CAP` reader - Capture mode: 1 /Compare mode : 0"]
pub type CapR = crate::BitReader;
#[doc = "Field `CAP` writer - Capture mode: 1 /Compare mode : 0"]
pub type CapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCCI` reader - Latched capture signal (read)"]
pub type ScciR = crate::BitReader;
#[doc = "Field `SCCI` writer - Latched capture signal (read)"]
pub type ScciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SCS` reader - Capture sychronize"]
pub type ScsR = crate::BitReader;
#[doc = "Field `SCS` writer - Capture sychronize"]
pub type ScsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture input select 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ccis {
#[doc = "0: Capture input select: 0 - CCIxA"]
Ccis0 = 0,
#[doc = "1: Capture input select: 1 - CCIxB"]
Ccis1 = 1,
#[doc = "2: Capture input select: 2 - GND"]
Ccis2 = 2,
#[doc = "3: Capture input select: 3 - Vcc"]
Ccis3 = 3,
}
impl From<Ccis> for u8 {
#[inline(always)]
fn from(variant: Ccis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ccis {
type Ux = u8;
}
impl crate::IsEnum for Ccis {}
#[doc = "Field `CCIS` reader - Capture input select 1"]
pub type CcisR = crate::FieldReader<Ccis>;
impl CcisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccis {
match self.bits {
0 => Ccis::Ccis0,
1 => Ccis::Ccis1,
2 => Ccis::Ccis2,
3 => Ccis::Ccis3,
_ => unreachable!(),
}
}
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn is_ccis_0(&self) -> bool {
*self == Ccis::Ccis0
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn is_ccis_1(&self) -> bool {
*self == Ccis::Ccis1
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn is_ccis_2(&self) -> bool {
*self == Ccis::Ccis2
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn is_ccis_3(&self) -> bool {
*self == Ccis::Ccis3
}
}
#[doc = "Field `CCIS` writer - Capture input select 1"]
pub type CcisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ccis, crate::Safe>;
impl<'a, REG> CcisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture input select: 0 - CCIxA"]
#[inline(always)]
pub fn ccis_0(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis0)
}
#[doc = "Capture input select: 1 - CCIxB"]
#[inline(always)]
pub fn ccis_1(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis1)
}
#[doc = "Capture input select: 2 - GND"]
#[inline(always)]
pub fn ccis_2(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis2)
}
#[doc = "Capture input select: 3 - Vcc"]
#[inline(always)]
pub fn ccis_3(self) -> &'a mut crate::W<REG> {
self.variant(Ccis::Ccis3)
}
}
#[doc = "Capture mode 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Capture mode: 0 - disabled"]
Cm0 = 0,
#[doc = "1: Capture mode: 1 - pos. edge"]
Cm1 = 1,
#[doc = "2: Capture mode: 1 - neg. edge"]
Cm2 = 2,
#[doc = "3: Capture mode: 1 - both edges"]
Cm3 = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Capture mode 1"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cm {
match self.bits {
0 => Cm::Cm0,
1 => Cm::Cm1,
2 => Cm::Cm2,
3 => Cm::Cm3,
_ => unreachable!(),
}
}
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn is_cm_0(&self) -> bool {
*self == Cm::Cm0
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn is_cm_1(&self) -> bool {
*self == Cm::Cm1
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn is_cm_2(&self) -> bool {
*self == Cm::Cm2
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn is_cm_3(&self) -> bool {
*self == Cm::Cm3
}
}
#[doc = "Field `CM` writer - Capture mode 1"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm, crate::Safe>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Capture mode: 0 - disabled"]
#[inline(always)]
pub fn cm_0(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm0)
}
#[doc = "Capture mode: 1 - pos. edge"]
#[inline(always)]
pub fn cm_1(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm1)
}
#[doc = "Capture mode: 1 - neg. edge"]
#[inline(always)]
pub fn cm_2(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm2)
}
#[doc = "Capture mode: 1 - both edges"]
#[inline(always)]
pub fn cm_3(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Cm3)
}
}
impl R {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&self) -> CcifgR {
CcifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&self) -> CovR {
CovR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&self) -> OutR {
OutR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&self) -> CciR {
CciR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&self) -> CcieR {
CcieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&self) -> OutmodR {
OutmodR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&self) -> ScciR {
ScciR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&self) -> ScsR {
ScsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&self) -> CcisR {
CcisR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Capture/compare interrupt flag"]
#[inline(always)]
pub fn ccifg(&mut self) -> CcifgW<'_, Ta3cctl1Spec> {
CcifgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/compare overflow flag"]
#[inline(always)]
pub fn cov(&mut self) -> CovW<'_, Ta3cctl1Spec> {
CovW::new(self, 1)
}
#[doc = "Bit 2 - PWM Output signal if output mode 0"]
#[inline(always)]
pub fn out(&mut self) -> OutW<'_, Ta3cctl1Spec> {
OutW::new(self, 2)
}
#[doc = "Bit 3 - Capture input signal (read)"]
#[inline(always)]
pub fn cci(&mut self) -> CciW<'_, Ta3cctl1Spec> {
CciW::new(self, 3)
}
#[doc = "Bit 4 - Capture/compare interrupt enable"]
#[inline(always)]
pub fn ccie(&mut self) -> CcieW<'_, Ta3cctl1Spec> {
CcieW::new(self, 4)
}
#[doc = "Bits 5:7 - Output mode 2"]
#[inline(always)]
pub fn outmod(&mut self) -> OutmodW<'_, Ta3cctl1Spec> {
OutmodW::new(self, 5)
}
#[doc = "Bit 8 - Capture mode: 1 /Compare mode : 0"]
#[inline(always)]
pub fn cap(&mut self) -> CapW<'_, Ta3cctl1Spec> {
CapW::new(self, 8)
}
#[doc = "Bit 10 - Latched capture signal (read)"]
#[inline(always)]
pub fn scci(&mut self) -> ScciW<'_, Ta3cctl1Spec> {
ScciW::new(self, 10)
}
#[doc = "Bit 11 - Capture sychronize"]
#[inline(always)]
pub fn scs(&mut self) -> ScsW<'_, Ta3cctl1Spec> {
ScsW::new(self, 11)
}
#[doc = "Bits 12:13 - Capture input select 1"]
#[inline(always)]
pub fn ccis(&mut self) -> CcisW<'_, Ta3cctl1Spec> {
CcisW::new(self, 12)
}
#[doc = "Bits 14:15 - Capture mode 1"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<'_, Ta3cctl1Spec> {
CmW::new(self, 14)
}
}
#[doc = "Timer3_A2 Capture/Compare Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ta3cctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta3cctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta3cctl1Spec;
impl crate::RegisterSpec for Ta3cctl1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta3cctl1::R`](R) reader structure"]
impl crate::Readable for Ta3cctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`ta3cctl1::W`](W) writer structure"]
impl crate::Writable for Ta3cctl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA3CCTL1 to value 0"]
impl crate::Resettable for Ta3cctl1Spec {}
}
#[doc = "TA3R (rw) register accessor: Timer3_A2\n\nYou can [`read`](crate::Reg::read) this register and get [`ta3r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta3r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta3r`] module"]
#[doc(alias = "TA3R")]
pub type Ta3r = crate::Reg<ta3r::Ta3rSpec>;
#[doc = "Timer3_A2"]
pub mod ta3r {
#[doc = "Register `TA3R` reader"]
pub type R = crate::R<Ta3rSpec>;
#[doc = "Register `TA3R` writer"]
pub type W = crate::W<Ta3rSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer3_A2\n\nYou can [`read`](crate::Reg::read) this register and get [`ta3r::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta3r::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta3rSpec;
impl crate::RegisterSpec for Ta3rSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta3r::R`](R) reader structure"]
impl crate::Readable for Ta3rSpec {}
#[doc = "`write(|w| ..)` method takes [`ta3r::W`](W) writer structure"]
impl crate::Writable for Ta3rSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA3R to value 0"]
impl crate::Resettable for Ta3rSpec {}
}
#[doc = "TA3CCR0 (rw) register accessor: Timer3_A2 Capture/Compare 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta3ccr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta3ccr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta3ccr0`] module"]
#[doc(alias = "TA3CCR0")]
pub type Ta3ccr0 = crate::Reg<ta3ccr0::Ta3ccr0Spec>;
#[doc = "Timer3_A2 Capture/Compare 0"]
pub mod ta3ccr0 {
#[doc = "Register `TA3CCR0` reader"]
pub type R = crate::R<Ta3ccr0Spec>;
#[doc = "Register `TA3CCR0` writer"]
pub type W = crate::W<Ta3ccr0Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer3_A2 Capture/Compare 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta3ccr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta3ccr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta3ccr0Spec;
impl crate::RegisterSpec for Ta3ccr0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta3ccr0::R`](R) reader structure"]
impl crate::Readable for Ta3ccr0Spec {}
#[doc = "`write(|w| ..)` method takes [`ta3ccr0::W`](W) writer structure"]
impl crate::Writable for Ta3ccr0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA3CCR0 to value 0"]
impl crate::Resettable for Ta3ccr0Spec {}
}
#[doc = "TA3CCR1 (rw) register accessor: Timer3_A2 Capture/Compare 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ta3ccr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta3ccr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta3ccr1`] module"]
#[doc(alias = "TA3CCR1")]
pub type Ta3ccr1 = crate::Reg<ta3ccr1::Ta3ccr1Spec>;
#[doc = "Timer3_A2 Capture/Compare 1"]
pub mod ta3ccr1 {
#[doc = "Register `TA3CCR1` reader"]
pub type R = crate::R<Ta3ccr1Spec>;
#[doc = "Register `TA3CCR1` writer"]
pub type W = crate::W<Ta3ccr1Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer3_A2 Capture/Compare 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ta3ccr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta3ccr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta3ccr1Spec;
impl crate::RegisterSpec for Ta3ccr1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta3ccr1::R`](R) reader structure"]
impl crate::Readable for Ta3ccr1Spec {}
#[doc = "`write(|w| ..)` method takes [`ta3ccr1::W`](W) writer structure"]
impl crate::Writable for Ta3ccr1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA3CCR1 to value 0"]
impl crate::Resettable for Ta3ccr1Spec {}
}
#[doc = "TA3EX0 (rw) register accessor: Timer3_A2 Expansion Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta3ex0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta3ex0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta3ex0`] module"]
#[doc(alias = "TA3EX0")]
pub type Ta3ex0 = crate::Reg<ta3ex0::Ta3ex0Spec>;
#[doc = "Timer3_A2 Expansion Register 0"]
pub mod ta3ex0 {
#[doc = "Register `TA3EX0` reader"]
pub type R = crate::R<Ta3ex0Spec>;
#[doc = "Register `TA3EX0` writer"]
pub type W = crate::W<Ta3ex0Spec>;
#[doc = "Timer A Input divider expansion Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Taidex {
#[doc = "0: Timer A Input divider expansion : /1"]
Taidex0 = 0,
#[doc = "1: Timer A Input divider expansion : /2"]
Taidex1 = 1,
#[doc = "2: Timer A Input divider expansion : /3"]
Taidex2 = 2,
#[doc = "3: Timer A Input divider expansion : /4"]
Taidex3 = 3,
#[doc = "4: Timer A Input divider expansion : /5"]
Taidex4 = 4,
#[doc = "5: Timer A Input divider expansion : /6"]
Taidex5 = 5,
#[doc = "6: Timer A Input divider expansion : /7"]
Taidex6 = 6,
#[doc = "7: Timer A Input divider expansion : /8"]
Taidex7 = 7,
}
impl From<Taidex> for u8 {
#[inline(always)]
fn from(variant: Taidex) -> Self {
variant as _
}
}
impl crate::FieldSpec for Taidex {
type Ux = u8;
}
impl crate::IsEnum for Taidex {}
#[doc = "Field `TAIDEX` reader - Timer A Input divider expansion Bit: 0"]
pub type TaidexR = crate::FieldReader<Taidex>;
impl TaidexR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Taidex {
match self.bits {
0 => Taidex::Taidex0,
1 => Taidex::Taidex1,
2 => Taidex::Taidex2,
3 => Taidex::Taidex3,
4 => Taidex::Taidex4,
5 => Taidex::Taidex5,
6 => Taidex::Taidex6,
7 => Taidex::Taidex7,
_ => unreachable!(),
}
}
#[doc = "Timer A Input divider expansion : /1"]
#[inline(always)]
pub fn is_taidex_0(&self) -> bool {
*self == Taidex::Taidex0
}
#[doc = "Timer A Input divider expansion : /2"]
#[inline(always)]
pub fn is_taidex_1(&self) -> bool {
*self == Taidex::Taidex1
}
#[doc = "Timer A Input divider expansion : /3"]
#[inline(always)]
pub fn is_taidex_2(&self) -> bool {
*self == Taidex::Taidex2
}
#[doc = "Timer A Input divider expansion : /4"]
#[inline(always)]
pub fn is_taidex_3(&self) -> bool {
*self == Taidex::Taidex3
}
#[doc = "Timer A Input divider expansion : /5"]
#[inline(always)]
pub fn is_taidex_4(&self) -> bool {
*self == Taidex::Taidex4
}
#[doc = "Timer A Input divider expansion : /6"]
#[inline(always)]
pub fn is_taidex_5(&self) -> bool {
*self == Taidex::Taidex5
}
#[doc = "Timer A Input divider expansion : /7"]
#[inline(always)]
pub fn is_taidex_6(&self) -> bool {
*self == Taidex::Taidex6
}
#[doc = "Timer A Input divider expansion : /8"]
#[inline(always)]
pub fn is_taidex_7(&self) -> bool {
*self == Taidex::Taidex7
}
}
#[doc = "Field `TAIDEX` writer - Timer A Input divider expansion Bit: 0"]
pub type TaidexW<'a, REG> = crate::FieldWriter<'a, REG, 3, Taidex, crate::Safe>;
impl<'a, REG> TaidexW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Timer A Input divider expansion : /1"]
#[inline(always)]
pub fn taidex_0(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex0)
}
#[doc = "Timer A Input divider expansion : /2"]
#[inline(always)]
pub fn taidex_1(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex1)
}
#[doc = "Timer A Input divider expansion : /3"]
#[inline(always)]
pub fn taidex_2(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex2)
}
#[doc = "Timer A Input divider expansion : /4"]
#[inline(always)]
pub fn taidex_3(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex3)
}
#[doc = "Timer A Input divider expansion : /5"]
#[inline(always)]
pub fn taidex_4(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex4)
}
#[doc = "Timer A Input divider expansion : /6"]
#[inline(always)]
pub fn taidex_5(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex5)
}
#[doc = "Timer A Input divider expansion : /7"]
#[inline(always)]
pub fn taidex_6(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex6)
}
#[doc = "Timer A Input divider expansion : /8"]
#[inline(always)]
pub fn taidex_7(self) -> &'a mut crate::W<REG> {
self.variant(Taidex::Taidex7)
}
}
impl R {
#[doc = "Bits 0:2 - Timer A Input divider expansion Bit: 0"]
#[inline(always)]
pub fn taidex(&self) -> TaidexR {
TaidexR::new((self.bits & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:2 - Timer A Input divider expansion Bit: 0"]
#[inline(always)]
pub fn taidex(&mut self) -> TaidexW<'_, Ta3ex0Spec> {
TaidexW::new(self, 0)
}
}
#[doc = "Timer3_A2 Expansion Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ta3ex0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta3ex0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta3ex0Spec;
impl crate::RegisterSpec for Ta3ex0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta3ex0::R`](R) reader structure"]
impl crate::Readable for Ta3ex0Spec {}
#[doc = "`write(|w| ..)` method takes [`ta3ex0::W`](W) writer structure"]
impl crate::Writable for Ta3ex0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA3EX0 to value 0"]
impl crate::Resettable for Ta3ex0Spec {}
}
#[doc = "TA3IV (rw) register accessor: Timer3_A2 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`ta3iv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta3iv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ta3iv`] module"]
#[doc(alias = "TA3IV")]
pub type Ta3iv = crate::Reg<ta3iv::Ta3ivSpec>;
#[doc = "Timer3_A2 Interrupt Vector Word"]
pub mod ta3iv {
#[doc = "Register `TA3IV` reader"]
pub type R = crate::R<Ta3ivSpec>;
#[doc = "Register `TA3IV` writer"]
pub type W = crate::W<Ta3ivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Timer3_A2 Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`ta3iv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ta3iv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ta3ivSpec;
impl crate::RegisterSpec for Ta3ivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ta3iv::R`](R) reader structure"]
impl crate::Readable for Ta3ivSpec {}
#[doc = "`write(|w| ..)` method takes [`ta3iv::W`](W) writer structure"]
impl crate::Writable for Ta3ivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TA3IV to value 0"]
impl crate::Resettable for Ta3ivSpec {}
}
}
#[doc = "Capacitive_Touch_IO 1"]
pub type CapacitiveTouchIo1 = crate::Periph<capacitive_touch_io_1::RegisterBlock, 0x047e>;
impl core::fmt::Debug for CapacitiveTouchIo1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CapacitiveTouchIo1").finish()
}
}
#[doc = "Capacitive_Touch_IO 1"]
pub mod capacitive_touch_io_1 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
captio1ctl: Captio1ctl,
}
impl RegisterBlock {
#[doc = "0x00 - Capacitive_Touch_IO 1 control register"]
#[inline(always)]
pub const fn captio1ctl(&self) -> &Captio1ctl {
&self.captio1ctl
}
}
#[doc = "CAPTIO1CTL (rw) register accessor: Capacitive_Touch_IO 1 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`captio1ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`captio1ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@captio1ctl`] module"]
#[doc(alias = "CAPTIO1CTL")]
pub type Captio1ctl = crate::Reg<captio1ctl::Captio1ctlSpec>;
#[doc = "Capacitive_Touch_IO 1 control register"]
pub mod captio1ctl {
#[doc = "Register `CAPTIO1CTL` reader"]
pub type R = crate::R<Captio1ctlSpec>;
#[doc = "Register `CAPTIO1CTL` writer"]
pub type W = crate::W<Captio1ctlSpec>;
#[doc = "Field `CAPTIOPISEL0` reader - CapTouchIO Pin Select Bit: 0"]
pub type Captiopisel0R = crate::BitReader;
#[doc = "Field `CAPTIOPISEL0` writer - CapTouchIO Pin Select Bit: 0"]
pub type Captiopisel0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAPTIOPISEL1` reader - CapTouchIO Pin Select Bit: 1"]
pub type Captiopisel1R = crate::BitReader;
#[doc = "Field `CAPTIOPISEL1` writer - CapTouchIO Pin Select Bit: 1"]
pub type Captiopisel1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAPTIOPISEL2` reader - CapTouchIO Pin Select Bit: 2"]
pub type Captiopisel2R = crate::BitReader;
#[doc = "Field `CAPTIOPISEL2` writer - CapTouchIO Pin Select Bit: 2"]
pub type Captiopisel2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAPTIOPOSEL0` reader - CapTouchIO Port Select Bit: 0"]
pub type Captioposel0R = crate::BitReader;
#[doc = "Field `CAPTIOPOSEL0` writer - CapTouchIO Port Select Bit: 0"]
pub type Captioposel0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAPTIOPOSEL1` reader - CapTouchIO Port Select Bit: 1"]
pub type Captioposel1R = crate::BitReader;
#[doc = "Field `CAPTIOPOSEL1` writer - CapTouchIO Port Select Bit: 1"]
pub type Captioposel1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAPTIOPOSEL2` reader - CapTouchIO Port Select Bit: 2"]
pub type Captioposel2R = crate::BitReader;
#[doc = "Field `CAPTIOPOSEL2` writer - CapTouchIO Port Select Bit: 2"]
pub type Captioposel2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAPTIOPOSEL3` reader - CapTouchIO Port Select Bit: 3"]
pub type Captioposel3R = crate::BitReader;
#[doc = "Field `CAPTIOPOSEL3` writer - CapTouchIO Port Select Bit: 3"]
pub type Captioposel3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAPTIOEN` reader - CapTouchIO Enable"]
pub type CaptioenR = crate::BitReader;
#[doc = "Field `CAPTIOEN` writer - CapTouchIO Enable"]
pub type CaptioenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAPTIO` reader - CapTouchIO state"]
pub type CaptioR = crate::BitReader;
#[doc = "Field `CAPTIO` writer - CapTouchIO state"]
pub type CaptioW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 1 - CapTouchIO Pin Select Bit: 0"]
#[inline(always)]
pub fn captiopisel0(&self) -> Captiopisel0R {
Captiopisel0R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - CapTouchIO Pin Select Bit: 1"]
#[inline(always)]
pub fn captiopisel1(&self) -> Captiopisel1R {
Captiopisel1R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - CapTouchIO Pin Select Bit: 2"]
#[inline(always)]
pub fn captiopisel2(&self) -> Captiopisel2R {
Captiopisel2R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - CapTouchIO Port Select Bit: 0"]
#[inline(always)]
pub fn captioposel0(&self) -> Captioposel0R {
Captioposel0R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - CapTouchIO Port Select Bit: 1"]
#[inline(always)]
pub fn captioposel1(&self) -> Captioposel1R {
Captioposel1R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - CapTouchIO Port Select Bit: 2"]
#[inline(always)]
pub fn captioposel2(&self) -> Captioposel2R {
Captioposel2R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - CapTouchIO Port Select Bit: 3"]
#[inline(always)]
pub fn captioposel3(&self) -> Captioposel3R {
Captioposel3R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - CapTouchIO Enable"]
#[inline(always)]
pub fn captioen(&self) -> CaptioenR {
CaptioenR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - CapTouchIO state"]
#[inline(always)]
pub fn captio(&self) -> CaptioR {
CaptioR::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1 - CapTouchIO Pin Select Bit: 0"]
#[inline(always)]
pub fn captiopisel0(&mut self) -> Captiopisel0W<'_, Captio1ctlSpec> {
Captiopisel0W::new(self, 1)
}
#[doc = "Bit 2 - CapTouchIO Pin Select Bit: 1"]
#[inline(always)]
pub fn captiopisel1(&mut self) -> Captiopisel1W<'_, Captio1ctlSpec> {
Captiopisel1W::new(self, 2)
}
#[doc = "Bit 3 - CapTouchIO Pin Select Bit: 2"]
#[inline(always)]
pub fn captiopisel2(&mut self) -> Captiopisel2W<'_, Captio1ctlSpec> {
Captiopisel2W::new(self, 3)
}
#[doc = "Bit 4 - CapTouchIO Port Select Bit: 0"]
#[inline(always)]
pub fn captioposel0(&mut self) -> Captioposel0W<'_, Captio1ctlSpec> {
Captioposel0W::new(self, 4)
}
#[doc = "Bit 5 - CapTouchIO Port Select Bit: 1"]
#[inline(always)]
pub fn captioposel1(&mut self) -> Captioposel1W<'_, Captio1ctlSpec> {
Captioposel1W::new(self, 5)
}
#[doc = "Bit 6 - CapTouchIO Port Select Bit: 2"]
#[inline(always)]
pub fn captioposel2(&mut self) -> Captioposel2W<'_, Captio1ctlSpec> {
Captioposel2W::new(self, 6)
}
#[doc = "Bit 7 - CapTouchIO Port Select Bit: 3"]
#[inline(always)]
pub fn captioposel3(&mut self) -> Captioposel3W<'_, Captio1ctlSpec> {
Captioposel3W::new(self, 7)
}
#[doc = "Bit 8 - CapTouchIO Enable"]
#[inline(always)]
pub fn captioen(&mut self) -> CaptioenW<'_, Captio1ctlSpec> {
CaptioenW::new(self, 8)
}
#[doc = "Bit 9 - CapTouchIO state"]
#[inline(always)]
pub fn captio(&mut self) -> CaptioW<'_, Captio1ctlSpec> {
CaptioW::new(self, 9)
}
}
#[doc = "Capacitive_Touch_IO 1 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`captio1ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`captio1ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Captio1ctlSpec;
impl crate::RegisterSpec for Captio1ctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`captio1ctl::R`](R) reader structure"]
impl crate::Readable for Captio1ctlSpec {}
#[doc = "`write(|w| ..)` method takes [`captio1ctl::W`](W) writer structure"]
impl crate::Writable for Captio1ctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CAPTIO1CTL to value 0"]
impl crate::Resettable for Captio1ctlSpec {}
}
}
#[doc = "MPY 16 Multiplier 16 Bit Mode"]
pub type Mpy16 = crate::Periph<mpy_16::RegisterBlock, 0x04c0>;
impl core::fmt::Debug for Mpy16 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Mpy16").finish()
}
}
#[doc = "MPY 16 Multiplier 16 Bit Mode"]
pub mod mpy_16 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
mpy: Mpy,
mpys: Mpys,
mac: Mac,
macs: Macs,
op2: Op2,
reslo: Reslo,
reshi: Reshi,
sumext: Sumext,
_reserved8: [u8; 0x1c],
mpy32ctl0: Mpy32ctl0,
}
impl RegisterBlock {
#[doc = "0x00 - Multiply Unsigned/Operand 1"]
#[inline(always)]
pub const fn mpy(&self) -> &Mpy {
&self.mpy
}
#[doc = "0x02 - Multiply Signed/Operand 1"]
#[inline(always)]
pub const fn mpys(&self) -> &Mpys {
&self.mpys
}
#[doc = "0x04 - Multiply Unsigned and Accumulate/Operand 1"]
#[inline(always)]
pub const fn mac(&self) -> &Mac {
&self.mac
}
#[doc = "0x06 - Multiply Signed and Accumulate/Operand 1"]
#[inline(always)]
pub const fn macs(&self) -> &Macs {
&self.macs
}
#[doc = "0x08 - Operand 2"]
#[inline(always)]
pub const fn op2(&self) -> &Op2 {
&self.op2
}
#[doc = "0x0a - Result Low Word"]
#[inline(always)]
pub const fn reslo(&self) -> &Reslo {
&self.reslo
}
#[doc = "0x0c - Result High Word"]
#[inline(always)]
pub const fn reshi(&self) -> &Reshi {
&self.reshi
}
#[doc = "0x0e - Sum Extend"]
#[inline(always)]
pub const fn sumext(&self) -> &Sumext {
&self.sumext
}
#[doc = "0x2c - MPY32 Control Register 0"]
#[inline(always)]
pub const fn mpy32ctl0(&self) -> &Mpy32ctl0 {
&self.mpy32ctl0
}
}
#[doc = "MPY (rw) register accessor: Multiply Unsigned/Operand 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mpy::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpy::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mpy`] module"]
#[doc(alias = "MPY")]
pub type Mpy = crate::Reg<mpy::MpySpec>;
#[doc = "Multiply Unsigned/Operand 1"]
pub mod mpy {
#[doc = "Register `MPY` reader"]
pub type R = crate::R<MpySpec>;
#[doc = "Register `MPY` writer"]
pub type W = crate::W<MpySpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Multiply Unsigned/Operand 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mpy::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpy::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MpySpec;
impl crate::RegisterSpec for MpySpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mpy::R`](R) reader structure"]
impl crate::Readable for MpySpec {}
#[doc = "`write(|w| ..)` method takes [`mpy::W`](W) writer structure"]
impl crate::Writable for MpySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MPY to value 0"]
impl crate::Resettable for MpySpec {}
}
#[doc = "MPYS (rw) register accessor: Multiply Signed/Operand 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mpys::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpys::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mpys`] module"]
#[doc(alias = "MPYS")]
pub type Mpys = crate::Reg<mpys::MpysSpec>;
#[doc = "Multiply Signed/Operand 1"]
pub mod mpys {
#[doc = "Register `MPYS` reader"]
pub type R = crate::R<MpysSpec>;
#[doc = "Register `MPYS` writer"]
pub type W = crate::W<MpysSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Multiply Signed/Operand 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mpys::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpys::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MpysSpec;
impl crate::RegisterSpec for MpysSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mpys::R`](R) reader structure"]
impl crate::Readable for MpysSpec {}
#[doc = "`write(|w| ..)` method takes [`mpys::W`](W) writer structure"]
impl crate::Writable for MpysSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MPYS to value 0"]
impl crate::Resettable for MpysSpec {}
}
#[doc = "MAC (rw) register accessor: Multiply Unsigned and Accumulate/Operand 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mac::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac`] module"]
#[doc(alias = "MAC")]
pub type Mac = crate::Reg<mac::MacSpec>;
#[doc = "Multiply Unsigned and Accumulate/Operand 1"]
pub mod mac {
#[doc = "Register `MAC` reader"]
pub type R = crate::R<MacSpec>;
#[doc = "Register `MAC` writer"]
pub type W = crate::W<MacSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Multiply Unsigned and Accumulate/Operand 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mac::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MacSpec;
impl crate::RegisterSpec for MacSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mac::R`](R) reader structure"]
impl crate::Readable for MacSpec {}
#[doc = "`write(|w| ..)` method takes [`mac::W`](W) writer structure"]
impl crate::Writable for MacSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MAC to value 0"]
impl crate::Resettable for MacSpec {}
}
#[doc = "MACS (rw) register accessor: Multiply Signed and Accumulate/Operand 1\n\nYou can [`read`](crate::Reg::read) this register and get [`macs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`macs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@macs`] module"]
#[doc(alias = "MACS")]
pub type Macs = crate::Reg<macs::MacsSpec>;
#[doc = "Multiply Signed and Accumulate/Operand 1"]
pub mod macs {
#[doc = "Register `MACS` reader"]
pub type R = crate::R<MacsSpec>;
#[doc = "Register `MACS` writer"]
pub type W = crate::W<MacsSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Multiply Signed and Accumulate/Operand 1\n\nYou can [`read`](crate::Reg::read) this register and get [`macs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`macs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MacsSpec;
impl crate::RegisterSpec for MacsSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`macs::R`](R) reader structure"]
impl crate::Readable for MacsSpec {}
#[doc = "`write(|w| ..)` method takes [`macs::W`](W) writer structure"]
impl crate::Writable for MacsSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MACS to value 0"]
impl crate::Resettable for MacsSpec {}
}
#[doc = "OP2 (rw) register accessor: Operand 2\n\nYou can [`read`](crate::Reg::read) this register and get [`op2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`op2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@op2`] module"]
#[doc(alias = "OP2")]
pub type Op2 = crate::Reg<op2::Op2Spec>;
#[doc = "Operand 2"]
pub mod op2 {
#[doc = "Register `OP2` reader"]
pub type R = crate::R<Op2Spec>;
#[doc = "Register `OP2` writer"]
pub type W = crate::W<Op2Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Operand 2\n\nYou can [`read`](crate::Reg::read) this register and get [`op2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`op2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Op2Spec;
impl crate::RegisterSpec for Op2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`op2::R`](R) reader structure"]
impl crate::Readable for Op2Spec {}
#[doc = "`write(|w| ..)` method takes [`op2::W`](W) writer structure"]
impl crate::Writable for Op2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets OP2 to value 0"]
impl crate::Resettable for Op2Spec {}
}
#[doc = "RESLO (rw) register accessor: Result Low Word\n\nYou can [`read`](crate::Reg::read) this register and get [`reslo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reslo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reslo`] module"]
#[doc(alias = "RESLO")]
pub type Reslo = crate::Reg<reslo::ResloSpec>;
#[doc = "Result Low Word"]
pub mod reslo {
#[doc = "Register `RESLO` reader"]
pub type R = crate::R<ResloSpec>;
#[doc = "Register `RESLO` writer"]
pub type W = crate::W<ResloSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Result Low Word\n\nYou can [`read`](crate::Reg::read) this register and get [`reslo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reslo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ResloSpec;
impl crate::RegisterSpec for ResloSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`reslo::R`](R) reader structure"]
impl crate::Readable for ResloSpec {}
#[doc = "`write(|w| ..)` method takes [`reslo::W`](W) writer structure"]
impl crate::Writable for ResloSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RESLO to value 0"]
impl crate::Resettable for ResloSpec {}
}
#[doc = "RESHI (rw) register accessor: Result High Word\n\nYou can [`read`](crate::Reg::read) this register and get [`reshi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reshi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reshi`] module"]
#[doc(alias = "RESHI")]
pub type Reshi = crate::Reg<reshi::ReshiSpec>;
#[doc = "Result High Word"]
pub mod reshi {
#[doc = "Register `RESHI` reader"]
pub type R = crate::R<ReshiSpec>;
#[doc = "Register `RESHI` writer"]
pub type W = crate::W<ReshiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Result High Word\n\nYou can [`read`](crate::Reg::read) this register and get [`reshi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reshi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ReshiSpec;
impl crate::RegisterSpec for ReshiSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`reshi::R`](R) reader structure"]
impl crate::Readable for ReshiSpec {}
#[doc = "`write(|w| ..)` method takes [`reshi::W`](W) writer structure"]
impl crate::Writable for ReshiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RESHI to value 0"]
impl crate::Resettable for ReshiSpec {}
}
#[doc = "SUMEXT (rw) register accessor: Sum Extend\n\nYou can [`read`](crate::Reg::read) this register and get [`sumext::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sumext::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sumext`] module"]
#[doc(alias = "SUMEXT")]
pub type Sumext = crate::Reg<sumext::SumextSpec>;
#[doc = "Sum Extend"]
pub mod sumext {
#[doc = "Register `SUMEXT` reader"]
pub type R = crate::R<SumextSpec>;
#[doc = "Register `SUMEXT` writer"]
pub type W = crate::W<SumextSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Sum Extend\n\nYou can [`read`](crate::Reg::read) this register and get [`sumext::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sumext::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SumextSpec;
impl crate::RegisterSpec for SumextSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`sumext::R`](R) reader structure"]
impl crate::Readable for SumextSpec {}
#[doc = "`write(|w| ..)` method takes [`sumext::W`](W) writer structure"]
impl crate::Writable for SumextSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SUMEXT to value 0"]
impl crate::Resettable for SumextSpec {}
}
#[doc = "MPY32CTL0 (rw) register accessor: MPY32 Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mpy32ctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpy32ctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mpy32ctl0`] module"]
#[doc(alias = "MPY32CTL0")]
pub type Mpy32ctl0 = crate::Reg<mpy32ctl0::Mpy32ctl0Spec>;
#[doc = "MPY32 Control Register 0"]
pub mod mpy32ctl0 {
#[doc = "Register `MPY32CTL0` reader"]
pub type R = crate::R<Mpy32ctl0Spec>;
#[doc = "Register `MPY32CTL0` writer"]
pub type W = crate::W<Mpy32ctl0Spec>;
#[doc = "Field `MPYC` reader - Carry of the multiplier"]
pub type MpycR = crate::BitReader;
#[doc = "Field `MPYC` writer - Carry of the multiplier"]
pub type MpycW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPYFRAC` reader - Fractional mode"]
pub type MpyfracR = crate::BitReader;
#[doc = "Field `MPYFRAC` writer - Fractional mode"]
pub type MpyfracW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPYSAT` reader - Saturation mode"]
pub type MpysatR = crate::BitReader;
#[doc = "Field `MPYSAT` writer - Saturation mode"]
pub type MpysatW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Multiplier mode Bit:0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mpym {
#[doc = "0: Multiplier mode: MPY"]
Mpym0 = 0,
#[doc = "1: Multiplier mode: MPYS"]
Mpym1 = 1,
#[doc = "2: Multiplier mode: MAC"]
Mpym2 = 2,
#[doc = "3: Multiplier mode: MACS"]
Mpym3 = 3,
}
impl From<Mpym> for u8 {
#[inline(always)]
fn from(variant: Mpym) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mpym {
type Ux = u8;
}
impl crate::IsEnum for Mpym {}
#[doc = "Field `MPYM` reader - Multiplier mode Bit:0"]
pub type MpymR = crate::FieldReader<Mpym>;
impl MpymR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mpym {
match self.bits {
0 => Mpym::Mpym0,
1 => Mpym::Mpym1,
2 => Mpym::Mpym2,
3 => Mpym::Mpym3,
_ => unreachable!(),
}
}
#[doc = "Multiplier mode: MPY"]
#[inline(always)]
pub fn is_mpym_0(&self) -> bool {
*self == Mpym::Mpym0
}
#[doc = "Multiplier mode: MPYS"]
#[inline(always)]
pub fn is_mpym_1(&self) -> bool {
*self == Mpym::Mpym1
}
#[doc = "Multiplier mode: MAC"]
#[inline(always)]
pub fn is_mpym_2(&self) -> bool {
*self == Mpym::Mpym2
}
#[doc = "Multiplier mode: MACS"]
#[inline(always)]
pub fn is_mpym_3(&self) -> bool {
*self == Mpym::Mpym3
}
}
#[doc = "Field `MPYM` writer - Multiplier mode Bit:0"]
pub type MpymW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mpym, crate::Safe>;
impl<'a, REG> MpymW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Multiplier mode: MPY"]
#[inline(always)]
pub fn mpym_0(self) -> &'a mut crate::W<REG> {
self.variant(Mpym::Mpym0)
}
#[doc = "Multiplier mode: MPYS"]
#[inline(always)]
pub fn mpym_1(self) -> &'a mut crate::W<REG> {
self.variant(Mpym::Mpym1)
}
#[doc = "Multiplier mode: MAC"]
#[inline(always)]
pub fn mpym_2(self) -> &'a mut crate::W<REG> {
self.variant(Mpym::Mpym2)
}
#[doc = "Multiplier mode: MACS"]
#[inline(always)]
pub fn mpym_3(self) -> &'a mut crate::W<REG> {
self.variant(Mpym::Mpym3)
}
}
#[doc = "Field `OP1_32` reader - Bit-width of operand 1 0:16Bit / 1:32Bit"]
pub type Op1_32R = crate::BitReader;
#[doc = "Field `OP1_32` writer - Bit-width of operand 1 0:16Bit / 1:32Bit"]
pub type Op1_32W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OP2_32` reader - Bit-width of operand 2 0:16Bit / 1:32Bit"]
pub type Op2_32R = crate::BitReader;
#[doc = "Field `OP2_32` writer - Bit-width of operand 2 0:16Bit / 1:32Bit"]
pub type Op2_32W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPYDLYWRTEN` reader - Delayed write enable"]
pub type MpydlywrtenR = crate::BitReader;
#[doc = "Field `MPYDLYWRTEN` writer - Delayed write enable"]
pub type MpydlywrtenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPYDLY32` reader - Delayed write mode"]
pub type Mpydly32R = crate::BitReader;
#[doc = "Field `MPYDLY32` writer - Delayed write mode"]
pub type Mpydly32W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Carry of the multiplier"]
#[inline(always)]
pub fn mpyc(&self) -> MpycR {
MpycR::new((self.bits & 1) != 0)
}
#[doc = "Bit 2 - Fractional mode"]
#[inline(always)]
pub fn mpyfrac(&self) -> MpyfracR {
MpyfracR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Saturation mode"]
#[inline(always)]
pub fn mpysat(&self) -> MpysatR {
MpysatR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:5 - Multiplier mode Bit:0"]
#[inline(always)]
pub fn mpym(&self) -> MpymR {
MpymR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bit 6 - Bit-width of operand 1 0:16Bit / 1:32Bit"]
#[inline(always)]
pub fn op1_32(&self) -> Op1_32R {
Op1_32R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Bit-width of operand 2 0:16Bit / 1:32Bit"]
#[inline(always)]
pub fn op2_32(&self) -> Op2_32R {
Op2_32R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Delayed write enable"]
#[inline(always)]
pub fn mpydlywrten(&self) -> MpydlywrtenR {
MpydlywrtenR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Delayed write mode"]
#[inline(always)]
pub fn mpydly32(&self) -> Mpydly32R {
Mpydly32R::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Carry of the multiplier"]
#[inline(always)]
pub fn mpyc(&mut self) -> MpycW<'_, Mpy32ctl0Spec> {
MpycW::new(self, 0)
}
#[doc = "Bit 2 - Fractional mode"]
#[inline(always)]
pub fn mpyfrac(&mut self) -> MpyfracW<'_, Mpy32ctl0Spec> {
MpyfracW::new(self, 2)
}
#[doc = "Bit 3 - Saturation mode"]
#[inline(always)]
pub fn mpysat(&mut self) -> MpysatW<'_, Mpy32ctl0Spec> {
MpysatW::new(self, 3)
}
#[doc = "Bits 4:5 - Multiplier mode Bit:0"]
#[inline(always)]
pub fn mpym(&mut self) -> MpymW<'_, Mpy32ctl0Spec> {
MpymW::new(self, 4)
}
#[doc = "Bit 6 - Bit-width of operand 1 0:16Bit / 1:32Bit"]
#[inline(always)]
pub fn op1_32(&mut self) -> Op1_32W<'_, Mpy32ctl0Spec> {
Op1_32W::new(self, 6)
}
#[doc = "Bit 7 - Bit-width of operand 2 0:16Bit / 1:32Bit"]
#[inline(always)]
pub fn op2_32(&mut self) -> Op2_32W<'_, Mpy32ctl0Spec> {
Op2_32W::new(self, 7)
}
#[doc = "Bit 8 - Delayed write enable"]
#[inline(always)]
pub fn mpydlywrten(&mut self) -> MpydlywrtenW<'_, Mpy32ctl0Spec> {
MpydlywrtenW::new(self, 8)
}
#[doc = "Bit 9 - Delayed write mode"]
#[inline(always)]
pub fn mpydly32(&mut self) -> Mpydly32W<'_, Mpy32ctl0Spec> {
Mpydly32W::new(self, 9)
}
}
#[doc = "MPY32 Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mpy32ctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpy32ctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mpy32ctl0Spec;
impl crate::RegisterSpec for Mpy32ctl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mpy32ctl0::R`](R) reader structure"]
impl crate::Readable for Mpy32ctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`mpy32ctl0::W`](W) writer structure"]
impl crate::Writable for Mpy32ctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MPY32CTL0 to value 0"]
impl crate::Resettable for Mpy32ctl0Spec {}
}
}
#[doc = "MPY 32 Multiplier 32 Bit Mode"]
pub type Mpy32 = crate::Periph<mpy_32::RegisterBlock, 0x04d0>;
impl core::fmt::Debug for Mpy32 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Mpy32").finish()
}
}
#[doc = "MPY 32 Multiplier 32 Bit Mode"]
pub mod mpy_32 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
mpy32l: Mpy32l,
mpy32h: Mpy32h,
mpys32l: Mpys32l,
mpys32h: Mpys32h,
mac32l: Mac32l,
mac32h: Mac32h,
macs32l: Macs32l,
macs32h: Macs32h,
op2l: Op2l,
op2h: Op2h,
res0: Res0,
res1: Res1,
res2: Res2,
res3: Res3,
}
impl RegisterBlock {
#[doc = "0x00 - 32-bit operand 1 - multiply - low word"]
#[inline(always)]
pub const fn mpy32l(&self) -> &Mpy32l {
&self.mpy32l
}
#[doc = "0x02 - 32-bit operand 1 - multiply - high word"]
#[inline(always)]
pub const fn mpy32h(&self) -> &Mpy32h {
&self.mpy32h
}
#[doc = "0x04 - 32-bit operand 1 - signed multiply - low word"]
#[inline(always)]
pub const fn mpys32l(&self) -> &Mpys32l {
&self.mpys32l
}
#[doc = "0x06 - 32-bit operand 1 - signed multiply - high word"]
#[inline(always)]
pub const fn mpys32h(&self) -> &Mpys32h {
&self.mpys32h
}
#[doc = "0x08 - 32-bit operand 1 - multiply accumulate - low word"]
#[inline(always)]
pub const fn mac32l(&self) -> &Mac32l {
&self.mac32l
}
#[doc = "0x0a - 32-bit operand 1 - multiply accumulate - high word"]
#[inline(always)]
pub const fn mac32h(&self) -> &Mac32h {
&self.mac32h
}
#[doc = "0x0c - 32-bit operand 1 - signed multiply accumulate - low word"]
#[inline(always)]
pub const fn macs32l(&self) -> &Macs32l {
&self.macs32l
}
#[doc = "0x0e - 32-bit operand 1 - signed multiply accumulate - high word"]
#[inline(always)]
pub const fn macs32h(&self) -> &Macs32h {
&self.macs32h
}
#[doc = "0x10 - 32-bit operand 2 - low word"]
#[inline(always)]
pub const fn op2l(&self) -> &Op2l {
&self.op2l
}
#[doc = "0x12 - 32-bit operand 2 - high word"]
#[inline(always)]
pub const fn op2h(&self) -> &Op2h {
&self.op2h
}
#[doc = "0x14 - 32x32-bit result 0 - least significant word"]
#[inline(always)]
pub const fn res0(&self) -> &Res0 {
&self.res0
}
#[doc = "0x16 - 32x32-bit result 1"]
#[inline(always)]
pub const fn res1(&self) -> &Res1 {
&self.res1
}
#[doc = "0x18 - 32x32-bit result 2"]
#[inline(always)]
pub const fn res2(&self) -> &Res2 {
&self.res2
}
#[doc = "0x1a - 32x32-bit result 3 - most significant word"]
#[inline(always)]
pub const fn res3(&self) -> &Res3 {
&self.res3
}
}
#[doc = "MPY32L (rw) register accessor: 32-bit operand 1 - multiply - low word\n\nYou can [`read`](crate::Reg::read) this register and get [`mpy32l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpy32l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mpy32l`] module"]
#[doc(alias = "MPY32L")]
pub type Mpy32l = crate::Reg<mpy32l::Mpy32lSpec>;
#[doc = "32-bit operand 1 - multiply - low word"]
pub mod mpy32l {
#[doc = "Register `MPY32L` reader"]
pub type R = crate::R<Mpy32lSpec>;
#[doc = "Register `MPY32L` writer"]
pub type W = crate::W<Mpy32lSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "32-bit operand 1 - multiply - low word\n\nYou can [`read`](crate::Reg::read) this register and get [`mpy32l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpy32l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mpy32lSpec;
impl crate::RegisterSpec for Mpy32lSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mpy32l::R`](R) reader structure"]
impl crate::Readable for Mpy32lSpec {}
#[doc = "`write(|w| ..)` method takes [`mpy32l::W`](W) writer structure"]
impl crate::Writable for Mpy32lSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MPY32L to value 0"]
impl crate::Resettable for Mpy32lSpec {}
}
#[doc = "MPY32H (rw) register accessor: 32-bit operand 1 - multiply - high word\n\nYou can [`read`](crate::Reg::read) this register and get [`mpy32h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpy32h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mpy32h`] module"]
#[doc(alias = "MPY32H")]
pub type Mpy32h = crate::Reg<mpy32h::Mpy32hSpec>;
#[doc = "32-bit operand 1 - multiply - high word"]
pub mod mpy32h {
#[doc = "Register `MPY32H` reader"]
pub type R = crate::R<Mpy32hSpec>;
#[doc = "Register `MPY32H` writer"]
pub type W = crate::W<Mpy32hSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "32-bit operand 1 - multiply - high word\n\nYou can [`read`](crate::Reg::read) this register and get [`mpy32h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpy32h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mpy32hSpec;
impl crate::RegisterSpec for Mpy32hSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mpy32h::R`](R) reader structure"]
impl crate::Readable for Mpy32hSpec {}
#[doc = "`write(|w| ..)` method takes [`mpy32h::W`](W) writer structure"]
impl crate::Writable for Mpy32hSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MPY32H to value 0"]
impl crate::Resettable for Mpy32hSpec {}
}
#[doc = "MPYS32L (rw) register accessor: 32-bit operand 1 - signed multiply - low word\n\nYou can [`read`](crate::Reg::read) this register and get [`mpys32l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpys32l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mpys32l`] module"]
#[doc(alias = "MPYS32L")]
pub type Mpys32l = crate::Reg<mpys32l::Mpys32lSpec>;
#[doc = "32-bit operand 1 - signed multiply - low word"]
pub mod mpys32l {
#[doc = "Register `MPYS32L` reader"]
pub type R = crate::R<Mpys32lSpec>;
#[doc = "Register `MPYS32L` writer"]
pub type W = crate::W<Mpys32lSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "32-bit operand 1 - signed multiply - low word\n\nYou can [`read`](crate::Reg::read) this register and get [`mpys32l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpys32l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mpys32lSpec;
impl crate::RegisterSpec for Mpys32lSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mpys32l::R`](R) reader structure"]
impl crate::Readable for Mpys32lSpec {}
#[doc = "`write(|w| ..)` method takes [`mpys32l::W`](W) writer structure"]
impl crate::Writable for Mpys32lSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MPYS32L to value 0"]
impl crate::Resettable for Mpys32lSpec {}
}
#[doc = "MPYS32H (rw) register accessor: 32-bit operand 1 - signed multiply - high word\n\nYou can [`read`](crate::Reg::read) this register and get [`mpys32h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpys32h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mpys32h`] module"]
#[doc(alias = "MPYS32H")]
pub type Mpys32h = crate::Reg<mpys32h::Mpys32hSpec>;
#[doc = "32-bit operand 1 - signed multiply - high word"]
pub mod mpys32h {
#[doc = "Register `MPYS32H` reader"]
pub type R = crate::R<Mpys32hSpec>;
#[doc = "Register `MPYS32H` writer"]
pub type W = crate::W<Mpys32hSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "32-bit operand 1 - signed multiply - high word\n\nYou can [`read`](crate::Reg::read) this register and get [`mpys32h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpys32h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mpys32hSpec;
impl crate::RegisterSpec for Mpys32hSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mpys32h::R`](R) reader structure"]
impl crate::Readable for Mpys32hSpec {}
#[doc = "`write(|w| ..)` method takes [`mpys32h::W`](W) writer structure"]
impl crate::Writable for Mpys32hSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MPYS32H to value 0"]
impl crate::Resettable for Mpys32hSpec {}
}
#[doc = "MAC32L (rw) register accessor: 32-bit operand 1 - multiply accumulate - low word\n\nYou can [`read`](crate::Reg::read) this register and get [`mac32l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac32l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac32l`] module"]
#[doc(alias = "MAC32L")]
pub type Mac32l = crate::Reg<mac32l::Mac32lSpec>;
#[doc = "32-bit operand 1 - multiply accumulate - low word"]
pub mod mac32l {
#[doc = "Register `MAC32L` reader"]
pub type R = crate::R<Mac32lSpec>;
#[doc = "Register `MAC32L` writer"]
pub type W = crate::W<Mac32lSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "32-bit operand 1 - multiply accumulate - low word\n\nYou can [`read`](crate::Reg::read) this register and get [`mac32l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac32l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mac32lSpec;
impl crate::RegisterSpec for Mac32lSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mac32l::R`](R) reader structure"]
impl crate::Readable for Mac32lSpec {}
#[doc = "`write(|w| ..)` method takes [`mac32l::W`](W) writer structure"]
impl crate::Writable for Mac32lSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MAC32L to value 0"]
impl crate::Resettable for Mac32lSpec {}
}
#[doc = "MAC32H (rw) register accessor: 32-bit operand 1 - multiply accumulate - high word\n\nYou can [`read`](crate::Reg::read) this register and get [`mac32h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac32h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac32h`] module"]
#[doc(alias = "MAC32H")]
pub type Mac32h = crate::Reg<mac32h::Mac32hSpec>;
#[doc = "32-bit operand 1 - multiply accumulate - high word"]
pub mod mac32h {
#[doc = "Register `MAC32H` reader"]
pub type R = crate::R<Mac32hSpec>;
#[doc = "Register `MAC32H` writer"]
pub type W = crate::W<Mac32hSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "32-bit operand 1 - multiply accumulate - high word\n\nYou can [`read`](crate::Reg::read) this register and get [`mac32h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac32h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mac32hSpec;
impl crate::RegisterSpec for Mac32hSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mac32h::R`](R) reader structure"]
impl crate::Readable for Mac32hSpec {}
#[doc = "`write(|w| ..)` method takes [`mac32h::W`](W) writer structure"]
impl crate::Writable for Mac32hSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MAC32H to value 0"]
impl crate::Resettable for Mac32hSpec {}
}
#[doc = "MACS32L (rw) register accessor: 32-bit operand 1 - signed multiply accumulate - low word\n\nYou can [`read`](crate::Reg::read) this register and get [`macs32l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`macs32l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@macs32l`] module"]
#[doc(alias = "MACS32L")]
pub type Macs32l = crate::Reg<macs32l::Macs32lSpec>;
#[doc = "32-bit operand 1 - signed multiply accumulate - low word"]
pub mod macs32l {
#[doc = "Register `MACS32L` reader"]
pub type R = crate::R<Macs32lSpec>;
#[doc = "Register `MACS32L` writer"]
pub type W = crate::W<Macs32lSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "32-bit operand 1 - signed multiply accumulate - low word\n\nYou can [`read`](crate::Reg::read) this register and get [`macs32l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`macs32l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Macs32lSpec;
impl crate::RegisterSpec for Macs32lSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`macs32l::R`](R) reader structure"]
impl crate::Readable for Macs32lSpec {}
#[doc = "`write(|w| ..)` method takes [`macs32l::W`](W) writer structure"]
impl crate::Writable for Macs32lSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MACS32L to value 0"]
impl crate::Resettable for Macs32lSpec {}
}
#[doc = "MACS32H (rw) register accessor: 32-bit operand 1 - signed multiply accumulate - high word\n\nYou can [`read`](crate::Reg::read) this register and get [`macs32h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`macs32h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@macs32h`] module"]
#[doc(alias = "MACS32H")]
pub type Macs32h = crate::Reg<macs32h::Macs32hSpec>;
#[doc = "32-bit operand 1 - signed multiply accumulate - high word"]
pub mod macs32h {
#[doc = "Register `MACS32H` reader"]
pub type R = crate::R<Macs32hSpec>;
#[doc = "Register `MACS32H` writer"]
pub type W = crate::W<Macs32hSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "32-bit operand 1 - signed multiply accumulate - high word\n\nYou can [`read`](crate::Reg::read) this register and get [`macs32h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`macs32h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Macs32hSpec;
impl crate::RegisterSpec for Macs32hSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`macs32h::R`](R) reader structure"]
impl crate::Readable for Macs32hSpec {}
#[doc = "`write(|w| ..)` method takes [`macs32h::W`](W) writer structure"]
impl crate::Writable for Macs32hSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MACS32H to value 0"]
impl crate::Resettable for Macs32hSpec {}
}
#[doc = "OP2L (rw) register accessor: 32-bit operand 2 - low word\n\nYou can [`read`](crate::Reg::read) this register and get [`op2l::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`op2l::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@op2l`] module"]
#[doc(alias = "OP2L")]
pub type Op2l = crate::Reg<op2l::Op2lSpec>;
#[doc = "32-bit operand 2 - low word"]
pub mod op2l {
#[doc = "Register `OP2L` reader"]
pub type R = crate::R<Op2lSpec>;
#[doc = "Register `OP2L` writer"]
pub type W = crate::W<Op2lSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "32-bit operand 2 - low word\n\nYou can [`read`](crate::Reg::read) this register and get [`op2l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`op2l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Op2lSpec;
impl crate::RegisterSpec for Op2lSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`op2l::R`](R) reader structure"]
impl crate::Readable for Op2lSpec {}
#[doc = "`write(|w| ..)` method takes [`op2l::W`](W) writer structure"]
impl crate::Writable for Op2lSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets OP2L to value 0"]
impl crate::Resettable for Op2lSpec {}
}
#[doc = "OP2H (rw) register accessor: 32-bit operand 2 - high word\n\nYou can [`read`](crate::Reg::read) this register and get [`op2h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`op2h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@op2h`] module"]
#[doc(alias = "OP2H")]
pub type Op2h = crate::Reg<op2h::Op2hSpec>;
#[doc = "32-bit operand 2 - high word"]
pub mod op2h {
#[doc = "Register `OP2H` reader"]
pub type R = crate::R<Op2hSpec>;
#[doc = "Register `OP2H` writer"]
pub type W = crate::W<Op2hSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "32-bit operand 2 - high word\n\nYou can [`read`](crate::Reg::read) this register and get [`op2h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`op2h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Op2hSpec;
impl crate::RegisterSpec for Op2hSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`op2h::R`](R) reader structure"]
impl crate::Readable for Op2hSpec {}
#[doc = "`write(|w| ..)` method takes [`op2h::W`](W) writer structure"]
impl crate::Writable for Op2hSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets OP2H to value 0"]
impl crate::Resettable for Op2hSpec {}
}
#[doc = "RES0 (rw) register accessor: 32x32-bit result 0 - least significant word\n\nYou can [`read`](crate::Reg::read) this register and get [`res0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res0`] module"]
#[doc(alias = "RES0")]
pub type Res0 = crate::Reg<res0::Res0Spec>;
#[doc = "32x32-bit result 0 - least significant word"]
pub mod res0 {
#[doc = "Register `RES0` reader"]
pub type R = crate::R<Res0Spec>;
#[doc = "Register `RES0` writer"]
pub type W = crate::W<Res0Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "32x32-bit result 0 - least significant word\n\nYou can [`read`](crate::Reg::read) this register and get [`res0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res0Spec;
impl crate::RegisterSpec for Res0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`res0::R`](R) reader structure"]
impl crate::Readable for Res0Spec {}
#[doc = "`write(|w| ..)` method takes [`res0::W`](W) writer structure"]
impl crate::Writable for Res0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RES0 to value 0"]
impl crate::Resettable for Res0Spec {}
}
#[doc = "RES1 (rw) register accessor: 32x32-bit result 1\n\nYou can [`read`](crate::Reg::read) this register and get [`res1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res1`] module"]
#[doc(alias = "RES1")]
pub type Res1 = crate::Reg<res1::Res1Spec>;
#[doc = "32x32-bit result 1"]
pub mod res1 {
#[doc = "Register `RES1` reader"]
pub type R = crate::R<Res1Spec>;
#[doc = "Register `RES1` writer"]
pub type W = crate::W<Res1Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "32x32-bit result 1\n\nYou can [`read`](crate::Reg::read) this register and get [`res1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res1Spec;
impl crate::RegisterSpec for Res1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`res1::R`](R) reader structure"]
impl crate::Readable for Res1Spec {}
#[doc = "`write(|w| ..)` method takes [`res1::W`](W) writer structure"]
impl crate::Writable for Res1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RES1 to value 0"]
impl crate::Resettable for Res1Spec {}
}
#[doc = "RES2 (rw) register accessor: 32x32-bit result 2\n\nYou can [`read`](crate::Reg::read) this register and get [`res2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res2`] module"]
#[doc(alias = "RES2")]
pub type Res2 = crate::Reg<res2::Res2Spec>;
#[doc = "32x32-bit result 2"]
pub mod res2 {
#[doc = "Register `RES2` reader"]
pub type R = crate::R<Res2Spec>;
#[doc = "Register `RES2` writer"]
pub type W = crate::W<Res2Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "32x32-bit result 2\n\nYou can [`read`](crate::Reg::read) this register and get [`res2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res2Spec;
impl crate::RegisterSpec for Res2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`res2::R`](R) reader structure"]
impl crate::Readable for Res2Spec {}
#[doc = "`write(|w| ..)` method takes [`res2::W`](W) writer structure"]
impl crate::Writable for Res2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RES2 to value 0"]
impl crate::Resettable for Res2Spec {}
}
#[doc = "RES3 (rw) register accessor: 32x32-bit result 3 - most significant word\n\nYou can [`read`](crate::Reg::read) this register and get [`res3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@res3`] module"]
#[doc(alias = "RES3")]
pub type Res3 = crate::Reg<res3::Res3Spec>;
#[doc = "32x32-bit result 3 - most significant word"]
pub mod res3 {
#[doc = "Register `RES3` reader"]
pub type R = crate::R<Res3Spec>;
#[doc = "Register `RES3` writer"]
pub type W = crate::W<Res3Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "32x32-bit result 3 - most significant word\n\nYou can [`read`](crate::Reg::read) this register and get [`res3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`res3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Res3Spec;
impl crate::RegisterSpec for Res3Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`res3::R`](R) reader structure"]
impl crate::Readable for Res3Spec {}
#[doc = "`write(|w| ..)` method takes [`res3::W`](W) writer structure"]
impl crate::Writable for Res3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RES3 to value 0"]
impl crate::Resettable for Res3Spec {}
}
}
#[doc = "DMA"]
pub type Dma = crate::Periph<dma::RegisterBlock, 0x0500>;
impl core::fmt::Debug for Dma {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Dma").finish()
}
}
#[doc = "DMA"]
pub mod dma {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
dmactl0: Dmactl0,
dmactl1: Dmactl1,
dmactl2: Dmactl2,
dmactl3: Dmactl3,
dmactl4: Dmactl4,
_reserved5: [u8; 0x04],
dmaiv: Dmaiv,
dma0ctl: Dma0ctl,
dma0sa: Dma0sa,
dma0da: Dma0da,
dma0sz: Dma0sz,
_reserved10: [u8; 0x04],
dma1ctl: Dma1ctl,
dma1sa: Dma1sa,
dma1da: Dma1da,
dma1sz: Dma1sz,
_reserved14: [u8; 0x04],
dma2ctl: Dma2ctl,
dma2sa: Dma2sa,
dma2da: Dma2da,
dma2sz: Dma2sz,
}
impl RegisterBlock {
#[doc = "0x00 - DMA Module Control 0"]
#[inline(always)]
pub const fn dmactl0(&self) -> &Dmactl0 {
&self.dmactl0
}
#[doc = "0x02 - DMA Module Control 1"]
#[inline(always)]
pub const fn dmactl1(&self) -> &Dmactl1 {
&self.dmactl1
}
#[doc = "0x04 - DMA Module Control 2"]
#[inline(always)]
pub const fn dmactl2(&self) -> &Dmactl2 {
&self.dmactl2
}
#[doc = "0x06 - DMA Module Control 3"]
#[inline(always)]
pub const fn dmactl3(&self) -> &Dmactl3 {
&self.dmactl3
}
#[doc = "0x08 - DMA Module Control 4"]
#[inline(always)]
pub const fn dmactl4(&self) -> &Dmactl4 {
&self.dmactl4
}
#[doc = "0x0e - DMA Interrupt Vector Word"]
#[inline(always)]
pub const fn dmaiv(&self) -> &Dmaiv {
&self.dmaiv
}
#[doc = "0x10 - DMA Channel 0 Control"]
#[inline(always)]
pub const fn dma0ctl(&self) -> &Dma0ctl {
&self.dma0ctl
}
#[doc = "0x12 - DMA Channel 0 Source Address"]
#[inline(always)]
pub const fn dma0sa(&self) -> &Dma0sa {
&self.dma0sa
}
#[doc = "0x16 - DMA Channel 0 Destination Address"]
#[inline(always)]
pub const fn dma0da(&self) -> &Dma0da {
&self.dma0da
}
#[doc = "0x1a - DMA Channel 0 Transfer Size"]
#[inline(always)]
pub const fn dma0sz(&self) -> &Dma0sz {
&self.dma0sz
}
#[doc = "0x20 - DMA Channel 1 Control"]
#[inline(always)]
pub const fn dma1ctl(&self) -> &Dma1ctl {
&self.dma1ctl
}
#[doc = "0x22 - DMA Channel 1 Source Address"]
#[inline(always)]
pub const fn dma1sa(&self) -> &Dma1sa {
&self.dma1sa
}
#[doc = "0x26 - DMA Channel 1 Destination Address"]
#[inline(always)]
pub const fn dma1da(&self) -> &Dma1da {
&self.dma1da
}
#[doc = "0x2a - DMA Channel 1 Transfer Size"]
#[inline(always)]
pub const fn dma1sz(&self) -> &Dma1sz {
&self.dma1sz
}
#[doc = "0x30 - DMA Channel 2 Control"]
#[inline(always)]
pub const fn dma2ctl(&self) -> &Dma2ctl {
&self.dma2ctl
}
#[doc = "0x32 - DMA Channel 2 Source Address"]
#[inline(always)]
pub const fn dma2sa(&self) -> &Dma2sa {
&self.dma2sa
}
#[doc = "0x36 - DMA Channel 2 Destination Address"]
#[inline(always)]
pub const fn dma2da(&self) -> &Dma2da {
&self.dma2da
}
#[doc = "0x3a - DMA Channel 2 Transfer Size"]
#[inline(always)]
pub const fn dma2sz(&self) -> &Dma2sz {
&self.dma2sz
}
}
#[doc = "DMACTL0 (rw) register accessor: DMA Module Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmactl0`] module"]
#[doc(alias = "DMACTL0")]
pub type Dmactl0 = crate::Reg<dmactl0::Dmactl0Spec>;
#[doc = "DMA Module Control 0"]
pub mod dmactl0 {
#[doc = "Register `DMACTL0` reader"]
pub type R = crate::R<Dmactl0Spec>;
#[doc = "Register `DMACTL0` writer"]
pub type W = crate::W<Dmactl0Spec>;
#[doc = "DMA channel 0 transfer select bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dma0tsel {
#[doc = "0: DMA channel 0 transfer select 0: DMA_REQ (sw)"]
Dma0tsel0 = 0,
#[doc = "1: DMA channel 0 transfer select 1:"]
Dma0tsel1 = 1,
#[doc = "2: DMA channel 0 transfer select 2:"]
Dma0tsel2 = 2,
#[doc = "3: DMA channel 0 transfer select 3:"]
Dma0tsel3 = 3,
#[doc = "4: DMA channel 0 transfer select 4:"]
Dma0tsel4 = 4,
#[doc = "5: DMA channel 0 transfer select 5:"]
Dma0tsel5 = 5,
#[doc = "6: DMA channel 0 transfer select 6:"]
Dma0tsel6 = 6,
#[doc = "7: DMA channel 0 transfer select 7:"]
Dma0tsel7 = 7,
#[doc = "8: DMA channel 0 transfer select 8:"]
Dma0tsel8 = 8,
#[doc = "9: DMA channel 0 transfer select 9:"]
Dma0tsel9 = 9,
#[doc = "10: DMA channel 0 transfer select 10:"]
Dma0tsel10 = 10,
#[doc = "11: DMA channel 0 transfer select 11:"]
Dma0tsel11 = 11,
#[doc = "12: DMA channel 0 transfer select 12:"]
Dma0tsel12 = 12,
#[doc = "13: DMA channel 0 transfer select 13:"]
Dma0tsel13 = 13,
#[doc = "14: DMA channel 0 transfer select 14:"]
Dma0tsel14 = 14,
#[doc = "15: DMA channel 0 transfer select 15:"]
Dma0tsel15 = 15,
#[doc = "16: DMA channel 0 transfer select 16:"]
Dma0tsel16 = 16,
#[doc = "17: DMA channel 0 transfer select 17:"]
Dma0tsel17 = 17,
#[doc = "18: DMA channel 0 transfer select 18:"]
Dma0tsel18 = 18,
#[doc = "19: DMA channel 0 transfer select 19:"]
Dma0tsel19 = 19,
#[doc = "20: DMA channel 0 transfer select 20:"]
Dma0tsel20 = 20,
#[doc = "21: DMA channel 0 transfer select 21:"]
Dma0tsel21 = 21,
#[doc = "22: DMA channel 0 transfer select 22:"]
Dma0tsel22 = 22,
#[doc = "23: DMA channel 0 transfer select 23:"]
Dma0tsel23 = 23,
#[doc = "24: DMA channel 0 transfer select 24:"]
Dma0tsel24 = 24,
#[doc = "25: DMA channel 0 transfer select 25:"]
Dma0tsel25 = 25,
#[doc = "26: DMA channel 0 transfer select 26:"]
Dma0tsel26 = 26,
#[doc = "27: DMA channel 0 transfer select 27:"]
Dma0tsel27 = 27,
#[doc = "28: DMA channel 0 transfer select 28:"]
Dma0tsel28 = 28,
#[doc = "29: DMA channel 0 transfer select 29:"]
Dma0tsel29 = 29,
#[doc = "30: DMA channel 0 transfer select 30: previous DMA channel DMA2IFG"]
Dma0tsel30 = 30,
#[doc = "31: DMA channel 0 transfer select 31: ext. Trigger (DMAE0)"]
Dma0tsel31 = 31,
}
impl From<Dma0tsel> for u8 {
#[inline(always)]
fn from(variant: Dma0tsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dma0tsel {
type Ux = u8;
}
impl crate::IsEnum for Dma0tsel {}
#[doc = "Field `DMA0TSEL` reader - DMA channel 0 transfer select bit 0"]
pub type Dma0tselR = crate::FieldReader<Dma0tsel>;
impl Dma0tselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dma0tsel {
match self.bits {
0 => Dma0tsel::Dma0tsel0,
1 => Dma0tsel::Dma0tsel1,
2 => Dma0tsel::Dma0tsel2,
3 => Dma0tsel::Dma0tsel3,
4 => Dma0tsel::Dma0tsel4,
5 => Dma0tsel::Dma0tsel5,
6 => Dma0tsel::Dma0tsel6,
7 => Dma0tsel::Dma0tsel7,
8 => Dma0tsel::Dma0tsel8,
9 => Dma0tsel::Dma0tsel9,
10 => Dma0tsel::Dma0tsel10,
11 => Dma0tsel::Dma0tsel11,
12 => Dma0tsel::Dma0tsel12,
13 => Dma0tsel::Dma0tsel13,
14 => Dma0tsel::Dma0tsel14,
15 => Dma0tsel::Dma0tsel15,
16 => Dma0tsel::Dma0tsel16,
17 => Dma0tsel::Dma0tsel17,
18 => Dma0tsel::Dma0tsel18,
19 => Dma0tsel::Dma0tsel19,
20 => Dma0tsel::Dma0tsel20,
21 => Dma0tsel::Dma0tsel21,
22 => Dma0tsel::Dma0tsel22,
23 => Dma0tsel::Dma0tsel23,
24 => Dma0tsel::Dma0tsel24,
25 => Dma0tsel::Dma0tsel25,
26 => Dma0tsel::Dma0tsel26,
27 => Dma0tsel::Dma0tsel27,
28 => Dma0tsel::Dma0tsel28,
29 => Dma0tsel::Dma0tsel29,
30 => Dma0tsel::Dma0tsel30,
31 => Dma0tsel::Dma0tsel31,
_ => unreachable!(),
}
}
#[doc = "DMA channel 0 transfer select 0: DMA_REQ (sw)"]
#[inline(always)]
pub fn is_dma0tsel_0(&self) -> bool {
*self == Dma0tsel::Dma0tsel0
}
#[doc = "DMA channel 0 transfer select 1:"]
#[inline(always)]
pub fn is_dma0tsel_1(&self) -> bool {
*self == Dma0tsel::Dma0tsel1
}
#[doc = "DMA channel 0 transfer select 2:"]
#[inline(always)]
pub fn is_dma0tsel_2(&self) -> bool {
*self == Dma0tsel::Dma0tsel2
}
#[doc = "DMA channel 0 transfer select 3:"]
#[inline(always)]
pub fn is_dma0tsel_3(&self) -> bool {
*self == Dma0tsel::Dma0tsel3
}
#[doc = "DMA channel 0 transfer select 4:"]
#[inline(always)]
pub fn is_dma0tsel_4(&self) -> bool {
*self == Dma0tsel::Dma0tsel4
}
#[doc = "DMA channel 0 transfer select 5:"]
#[inline(always)]
pub fn is_dma0tsel_5(&self) -> bool {
*self == Dma0tsel::Dma0tsel5
}
#[doc = "DMA channel 0 transfer select 6:"]
#[inline(always)]
pub fn is_dma0tsel_6(&self) -> bool {
*self == Dma0tsel::Dma0tsel6
}
#[doc = "DMA channel 0 transfer select 7:"]
#[inline(always)]
pub fn is_dma0tsel_7(&self) -> bool {
*self == Dma0tsel::Dma0tsel7
}
#[doc = "DMA channel 0 transfer select 8:"]
#[inline(always)]
pub fn is_dma0tsel_8(&self) -> bool {
*self == Dma0tsel::Dma0tsel8
}
#[doc = "DMA channel 0 transfer select 9:"]
#[inline(always)]
pub fn is_dma0tsel_9(&self) -> bool {
*self == Dma0tsel::Dma0tsel9
}
#[doc = "DMA channel 0 transfer select 10:"]
#[inline(always)]
pub fn is_dma0tsel_10(&self) -> bool {
*self == Dma0tsel::Dma0tsel10
}
#[doc = "DMA channel 0 transfer select 11:"]
#[inline(always)]
pub fn is_dma0tsel_11(&self) -> bool {
*self == Dma0tsel::Dma0tsel11
}
#[doc = "DMA channel 0 transfer select 12:"]
#[inline(always)]
pub fn is_dma0tsel_12(&self) -> bool {
*self == Dma0tsel::Dma0tsel12
}
#[doc = "DMA channel 0 transfer select 13:"]
#[inline(always)]
pub fn is_dma0tsel_13(&self) -> bool {
*self == Dma0tsel::Dma0tsel13
}
#[doc = "DMA channel 0 transfer select 14:"]
#[inline(always)]
pub fn is_dma0tsel_14(&self) -> bool {
*self == Dma0tsel::Dma0tsel14
}
#[doc = "DMA channel 0 transfer select 15:"]
#[inline(always)]
pub fn is_dma0tsel_15(&self) -> bool {
*self == Dma0tsel::Dma0tsel15
}
#[doc = "DMA channel 0 transfer select 16:"]
#[inline(always)]
pub fn is_dma0tsel_16(&self) -> bool {
*self == Dma0tsel::Dma0tsel16
}
#[doc = "DMA channel 0 transfer select 17:"]
#[inline(always)]
pub fn is_dma0tsel_17(&self) -> bool {
*self == Dma0tsel::Dma0tsel17
}
#[doc = "DMA channel 0 transfer select 18:"]
#[inline(always)]
pub fn is_dma0tsel_18(&self) -> bool {
*self == Dma0tsel::Dma0tsel18
}
#[doc = "DMA channel 0 transfer select 19:"]
#[inline(always)]
pub fn is_dma0tsel_19(&self) -> bool {
*self == Dma0tsel::Dma0tsel19
}
#[doc = "DMA channel 0 transfer select 20:"]
#[inline(always)]
pub fn is_dma0tsel_20(&self) -> bool {
*self == Dma0tsel::Dma0tsel20
}
#[doc = "DMA channel 0 transfer select 21:"]
#[inline(always)]
pub fn is_dma0tsel_21(&self) -> bool {
*self == Dma0tsel::Dma0tsel21
}
#[doc = "DMA channel 0 transfer select 22:"]
#[inline(always)]
pub fn is_dma0tsel_22(&self) -> bool {
*self == Dma0tsel::Dma0tsel22
}
#[doc = "DMA channel 0 transfer select 23:"]
#[inline(always)]
pub fn is_dma0tsel_23(&self) -> bool {
*self == Dma0tsel::Dma0tsel23
}
#[doc = "DMA channel 0 transfer select 24:"]
#[inline(always)]
pub fn is_dma0tsel_24(&self) -> bool {
*self == Dma0tsel::Dma0tsel24
}
#[doc = "DMA channel 0 transfer select 25:"]
#[inline(always)]
pub fn is_dma0tsel_25(&self) -> bool {
*self == Dma0tsel::Dma0tsel25
}
#[doc = "DMA channel 0 transfer select 26:"]
#[inline(always)]
pub fn is_dma0tsel_26(&self) -> bool {
*self == Dma0tsel::Dma0tsel26
}
#[doc = "DMA channel 0 transfer select 27:"]
#[inline(always)]
pub fn is_dma0tsel_27(&self) -> bool {
*self == Dma0tsel::Dma0tsel27
}
#[doc = "DMA channel 0 transfer select 28:"]
#[inline(always)]
pub fn is_dma0tsel_28(&self) -> bool {
*self == Dma0tsel::Dma0tsel28
}
#[doc = "DMA channel 0 transfer select 29:"]
#[inline(always)]
pub fn is_dma0tsel_29(&self) -> bool {
*self == Dma0tsel::Dma0tsel29
}
#[doc = "DMA channel 0 transfer select 30: previous DMA channel DMA2IFG"]
#[inline(always)]
pub fn is_dma0tsel_30(&self) -> bool {
*self == Dma0tsel::Dma0tsel30
}
#[doc = "DMA channel 0 transfer select 31: ext. Trigger (DMAE0)"]
#[inline(always)]
pub fn is_dma0tsel_31(&self) -> bool {
*self == Dma0tsel::Dma0tsel31
}
}
#[doc = "Field `DMA0TSEL` writer - DMA channel 0 transfer select bit 0"]
pub type Dma0tselW<'a, REG> = crate::FieldWriter<'a, REG, 5, Dma0tsel, crate::Safe>;
impl<'a, REG> Dma0tselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "DMA channel 0 transfer select 0: DMA_REQ (sw)"]
#[inline(always)]
pub fn dma0tsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel0)
}
#[doc = "DMA channel 0 transfer select 1:"]
#[inline(always)]
pub fn dma0tsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel1)
}
#[doc = "DMA channel 0 transfer select 2:"]
#[inline(always)]
pub fn dma0tsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel2)
}
#[doc = "DMA channel 0 transfer select 3:"]
#[inline(always)]
pub fn dma0tsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel3)
}
#[doc = "DMA channel 0 transfer select 4:"]
#[inline(always)]
pub fn dma0tsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel4)
}
#[doc = "DMA channel 0 transfer select 5:"]
#[inline(always)]
pub fn dma0tsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel5)
}
#[doc = "DMA channel 0 transfer select 6:"]
#[inline(always)]
pub fn dma0tsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel6)
}
#[doc = "DMA channel 0 transfer select 7:"]
#[inline(always)]
pub fn dma0tsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel7)
}
#[doc = "DMA channel 0 transfer select 8:"]
#[inline(always)]
pub fn dma0tsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel8)
}
#[doc = "DMA channel 0 transfer select 9:"]
#[inline(always)]
pub fn dma0tsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel9)
}
#[doc = "DMA channel 0 transfer select 10:"]
#[inline(always)]
pub fn dma0tsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel10)
}
#[doc = "DMA channel 0 transfer select 11:"]
#[inline(always)]
pub fn dma0tsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel11)
}
#[doc = "DMA channel 0 transfer select 12:"]
#[inline(always)]
pub fn dma0tsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel12)
}
#[doc = "DMA channel 0 transfer select 13:"]
#[inline(always)]
pub fn dma0tsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel13)
}
#[doc = "DMA channel 0 transfer select 14:"]
#[inline(always)]
pub fn dma0tsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel14)
}
#[doc = "DMA channel 0 transfer select 15:"]
#[inline(always)]
pub fn dma0tsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel15)
}
#[doc = "DMA channel 0 transfer select 16:"]
#[inline(always)]
pub fn dma0tsel_16(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel16)
}
#[doc = "DMA channel 0 transfer select 17:"]
#[inline(always)]
pub fn dma0tsel_17(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel17)
}
#[doc = "DMA channel 0 transfer select 18:"]
#[inline(always)]
pub fn dma0tsel_18(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel18)
}
#[doc = "DMA channel 0 transfer select 19:"]
#[inline(always)]
pub fn dma0tsel_19(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel19)
}
#[doc = "DMA channel 0 transfer select 20:"]
#[inline(always)]
pub fn dma0tsel_20(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel20)
}
#[doc = "DMA channel 0 transfer select 21:"]
#[inline(always)]
pub fn dma0tsel_21(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel21)
}
#[doc = "DMA channel 0 transfer select 22:"]
#[inline(always)]
pub fn dma0tsel_22(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel22)
}
#[doc = "DMA channel 0 transfer select 23:"]
#[inline(always)]
pub fn dma0tsel_23(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel23)
}
#[doc = "DMA channel 0 transfer select 24:"]
#[inline(always)]
pub fn dma0tsel_24(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel24)
}
#[doc = "DMA channel 0 transfer select 25:"]
#[inline(always)]
pub fn dma0tsel_25(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel25)
}
#[doc = "DMA channel 0 transfer select 26:"]
#[inline(always)]
pub fn dma0tsel_26(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel26)
}
#[doc = "DMA channel 0 transfer select 27:"]
#[inline(always)]
pub fn dma0tsel_27(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel27)
}
#[doc = "DMA channel 0 transfer select 28:"]
#[inline(always)]
pub fn dma0tsel_28(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel28)
}
#[doc = "DMA channel 0 transfer select 29:"]
#[inline(always)]
pub fn dma0tsel_29(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel29)
}
#[doc = "DMA channel 0 transfer select 30: previous DMA channel DMA2IFG"]
#[inline(always)]
pub fn dma0tsel_30(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel30)
}
#[doc = "DMA channel 0 transfer select 31: ext. Trigger (DMAE0)"]
#[inline(always)]
pub fn dma0tsel_31(self) -> &'a mut crate::W<REG> {
self.variant(Dma0tsel::Dma0tsel31)
}
}
#[doc = "DMA channel 1 transfer select bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dma1tsel {
#[doc = "0: DMA channel 1 transfer select 0: DMA_REQ (sw)"]
Dma1tsel0 = 0,
#[doc = "1: DMA channel 1 transfer select 1:"]
Dma1tsel1 = 1,
#[doc = "2: DMA channel 1 transfer select 2:"]
Dma1tsel2 = 2,
#[doc = "3: DMA channel 1 transfer select 3:"]
Dma1tsel3 = 3,
#[doc = "4: DMA channel 1 transfer select 4:"]
Dma1tsel4 = 4,
#[doc = "5: DMA channel 1 transfer select 5:"]
Dma1tsel5 = 5,
#[doc = "6: DMA channel 1 transfer select 6:"]
Dma1tsel6 = 6,
#[doc = "7: DMA channel 1 transfer select 7:"]
Dma1tsel7 = 7,
#[doc = "8: DMA channel 1 transfer select 8:"]
Dma1tsel8 = 8,
#[doc = "9: DMA channel 1 transfer select 9:"]
Dma1tsel9 = 9,
#[doc = "10: DMA channel 1 transfer select 10:"]
Dma1tsel10 = 10,
#[doc = "11: DMA channel 1 transfer select 11:"]
Dma1tsel11 = 11,
#[doc = "12: DMA channel 1 transfer select 12:"]
Dma1tsel12 = 12,
#[doc = "13: DMA channel 1 transfer select 13:"]
Dma1tsel13 = 13,
#[doc = "14: DMA channel 1 transfer select 14:"]
Dma1tsel14 = 14,
#[doc = "15: DMA channel 1 transfer select 15:"]
Dma1tsel15 = 15,
#[doc = "16: DMA channel 1 transfer select 16:"]
Dma1tsel16 = 16,
#[doc = "17: DMA channel 1 transfer select 17:"]
Dma1tsel17 = 17,
#[doc = "18: DMA channel 1 transfer select 18:"]
Dma1tsel18 = 18,
#[doc = "19: DMA channel 1 transfer select 19:"]
Dma1tsel19 = 19,
#[doc = "20: DMA channel 1 transfer select 20:"]
Dma1tsel20 = 20,
#[doc = "21: DMA channel 1 transfer select 21:"]
Dma1tsel21 = 21,
#[doc = "22: DMA channel 1 transfer select 22:"]
Dma1tsel22 = 22,
#[doc = "23: DMA channel 1 transfer select 23:"]
Dma1tsel23 = 23,
#[doc = "24: DMA channel 1 transfer select 24:"]
Dma1tsel24 = 24,
#[doc = "25: DMA channel 1 transfer select 25:"]
Dma1tsel25 = 25,
#[doc = "26: DMA channel 1 transfer select 26:"]
Dma1tsel26 = 26,
#[doc = "27: DMA channel 1 transfer select 27:"]
Dma1tsel27 = 27,
#[doc = "28: DMA channel 1 transfer select 28:"]
Dma1tsel28 = 28,
#[doc = "29: DMA channel 1 transfer select 29:"]
Dma1tsel29 = 29,
#[doc = "30: DMA channel 1 transfer select 30: previous DMA channel DMA0IFG"]
Dma1tsel30 = 30,
#[doc = "31: DMA channel 1 transfer select 31: ext. Trigger (DMAE0)"]
Dma1tsel31 = 31,
}
impl From<Dma1tsel> for u8 {
#[inline(always)]
fn from(variant: Dma1tsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dma1tsel {
type Ux = u8;
}
impl crate::IsEnum for Dma1tsel {}
#[doc = "Field `DMA1TSEL` reader - DMA channel 1 transfer select bit 0"]
pub type Dma1tselR = crate::FieldReader<Dma1tsel>;
impl Dma1tselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dma1tsel {
match self.bits {
0 => Dma1tsel::Dma1tsel0,
1 => Dma1tsel::Dma1tsel1,
2 => Dma1tsel::Dma1tsel2,
3 => Dma1tsel::Dma1tsel3,
4 => Dma1tsel::Dma1tsel4,
5 => Dma1tsel::Dma1tsel5,
6 => Dma1tsel::Dma1tsel6,
7 => Dma1tsel::Dma1tsel7,
8 => Dma1tsel::Dma1tsel8,
9 => Dma1tsel::Dma1tsel9,
10 => Dma1tsel::Dma1tsel10,
11 => Dma1tsel::Dma1tsel11,
12 => Dma1tsel::Dma1tsel12,
13 => Dma1tsel::Dma1tsel13,
14 => Dma1tsel::Dma1tsel14,
15 => Dma1tsel::Dma1tsel15,
16 => Dma1tsel::Dma1tsel16,
17 => Dma1tsel::Dma1tsel17,
18 => Dma1tsel::Dma1tsel18,
19 => Dma1tsel::Dma1tsel19,
20 => Dma1tsel::Dma1tsel20,
21 => Dma1tsel::Dma1tsel21,
22 => Dma1tsel::Dma1tsel22,
23 => Dma1tsel::Dma1tsel23,
24 => Dma1tsel::Dma1tsel24,
25 => Dma1tsel::Dma1tsel25,
26 => Dma1tsel::Dma1tsel26,
27 => Dma1tsel::Dma1tsel27,
28 => Dma1tsel::Dma1tsel28,
29 => Dma1tsel::Dma1tsel29,
30 => Dma1tsel::Dma1tsel30,
31 => Dma1tsel::Dma1tsel31,
_ => unreachable!(),
}
}
#[doc = "DMA channel 1 transfer select 0: DMA_REQ (sw)"]
#[inline(always)]
pub fn is_dma1tsel_0(&self) -> bool {
*self == Dma1tsel::Dma1tsel0
}
#[doc = "DMA channel 1 transfer select 1:"]
#[inline(always)]
pub fn is_dma1tsel_1(&self) -> bool {
*self == Dma1tsel::Dma1tsel1
}
#[doc = "DMA channel 1 transfer select 2:"]
#[inline(always)]
pub fn is_dma1tsel_2(&self) -> bool {
*self == Dma1tsel::Dma1tsel2
}
#[doc = "DMA channel 1 transfer select 3:"]
#[inline(always)]
pub fn is_dma1tsel_3(&self) -> bool {
*self == Dma1tsel::Dma1tsel3
}
#[doc = "DMA channel 1 transfer select 4:"]
#[inline(always)]
pub fn is_dma1tsel_4(&self) -> bool {
*self == Dma1tsel::Dma1tsel4
}
#[doc = "DMA channel 1 transfer select 5:"]
#[inline(always)]
pub fn is_dma1tsel_5(&self) -> bool {
*self == Dma1tsel::Dma1tsel5
}
#[doc = "DMA channel 1 transfer select 6:"]
#[inline(always)]
pub fn is_dma1tsel_6(&self) -> bool {
*self == Dma1tsel::Dma1tsel6
}
#[doc = "DMA channel 1 transfer select 7:"]
#[inline(always)]
pub fn is_dma1tsel_7(&self) -> bool {
*self == Dma1tsel::Dma1tsel7
}
#[doc = "DMA channel 1 transfer select 8:"]
#[inline(always)]
pub fn is_dma1tsel_8(&self) -> bool {
*self == Dma1tsel::Dma1tsel8
}
#[doc = "DMA channel 1 transfer select 9:"]
#[inline(always)]
pub fn is_dma1tsel_9(&self) -> bool {
*self == Dma1tsel::Dma1tsel9
}
#[doc = "DMA channel 1 transfer select 10:"]
#[inline(always)]
pub fn is_dma1tsel_10(&self) -> bool {
*self == Dma1tsel::Dma1tsel10
}
#[doc = "DMA channel 1 transfer select 11:"]
#[inline(always)]
pub fn is_dma1tsel_11(&self) -> bool {
*self == Dma1tsel::Dma1tsel11
}
#[doc = "DMA channel 1 transfer select 12:"]
#[inline(always)]
pub fn is_dma1tsel_12(&self) -> bool {
*self == Dma1tsel::Dma1tsel12
}
#[doc = "DMA channel 1 transfer select 13:"]
#[inline(always)]
pub fn is_dma1tsel_13(&self) -> bool {
*self == Dma1tsel::Dma1tsel13
}
#[doc = "DMA channel 1 transfer select 14:"]
#[inline(always)]
pub fn is_dma1tsel_14(&self) -> bool {
*self == Dma1tsel::Dma1tsel14
}
#[doc = "DMA channel 1 transfer select 15:"]
#[inline(always)]
pub fn is_dma1tsel_15(&self) -> bool {
*self == Dma1tsel::Dma1tsel15
}
#[doc = "DMA channel 1 transfer select 16:"]
#[inline(always)]
pub fn is_dma1tsel_16(&self) -> bool {
*self == Dma1tsel::Dma1tsel16
}
#[doc = "DMA channel 1 transfer select 17:"]
#[inline(always)]
pub fn is_dma1tsel_17(&self) -> bool {
*self == Dma1tsel::Dma1tsel17
}
#[doc = "DMA channel 1 transfer select 18:"]
#[inline(always)]
pub fn is_dma1tsel_18(&self) -> bool {
*self == Dma1tsel::Dma1tsel18
}
#[doc = "DMA channel 1 transfer select 19:"]
#[inline(always)]
pub fn is_dma1tsel_19(&self) -> bool {
*self == Dma1tsel::Dma1tsel19
}
#[doc = "DMA channel 1 transfer select 20:"]
#[inline(always)]
pub fn is_dma1tsel_20(&self) -> bool {
*self == Dma1tsel::Dma1tsel20
}
#[doc = "DMA channel 1 transfer select 21:"]
#[inline(always)]
pub fn is_dma1tsel_21(&self) -> bool {
*self == Dma1tsel::Dma1tsel21
}
#[doc = "DMA channel 1 transfer select 22:"]
#[inline(always)]
pub fn is_dma1tsel_22(&self) -> bool {
*self == Dma1tsel::Dma1tsel22
}
#[doc = "DMA channel 1 transfer select 23:"]
#[inline(always)]
pub fn is_dma1tsel_23(&self) -> bool {
*self == Dma1tsel::Dma1tsel23
}
#[doc = "DMA channel 1 transfer select 24:"]
#[inline(always)]
pub fn is_dma1tsel_24(&self) -> bool {
*self == Dma1tsel::Dma1tsel24
}
#[doc = "DMA channel 1 transfer select 25:"]
#[inline(always)]
pub fn is_dma1tsel_25(&self) -> bool {
*self == Dma1tsel::Dma1tsel25
}
#[doc = "DMA channel 1 transfer select 26:"]
#[inline(always)]
pub fn is_dma1tsel_26(&self) -> bool {
*self == Dma1tsel::Dma1tsel26
}
#[doc = "DMA channel 1 transfer select 27:"]
#[inline(always)]
pub fn is_dma1tsel_27(&self) -> bool {
*self == Dma1tsel::Dma1tsel27
}
#[doc = "DMA channel 1 transfer select 28:"]
#[inline(always)]
pub fn is_dma1tsel_28(&self) -> bool {
*self == Dma1tsel::Dma1tsel28
}
#[doc = "DMA channel 1 transfer select 29:"]
#[inline(always)]
pub fn is_dma1tsel_29(&self) -> bool {
*self == Dma1tsel::Dma1tsel29
}
#[doc = "DMA channel 1 transfer select 30: previous DMA channel DMA0IFG"]
#[inline(always)]
pub fn is_dma1tsel_30(&self) -> bool {
*self == Dma1tsel::Dma1tsel30
}
#[doc = "DMA channel 1 transfer select 31: ext. Trigger (DMAE0)"]
#[inline(always)]
pub fn is_dma1tsel_31(&self) -> bool {
*self == Dma1tsel::Dma1tsel31
}
}
#[doc = "Field `DMA1TSEL` writer - DMA channel 1 transfer select bit 0"]
pub type Dma1tselW<'a, REG> = crate::FieldWriter<'a, REG, 5, Dma1tsel, crate::Safe>;
impl<'a, REG> Dma1tselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "DMA channel 1 transfer select 0: DMA_REQ (sw)"]
#[inline(always)]
pub fn dma1tsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel0)
}
#[doc = "DMA channel 1 transfer select 1:"]
#[inline(always)]
pub fn dma1tsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel1)
}
#[doc = "DMA channel 1 transfer select 2:"]
#[inline(always)]
pub fn dma1tsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel2)
}
#[doc = "DMA channel 1 transfer select 3:"]
#[inline(always)]
pub fn dma1tsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel3)
}
#[doc = "DMA channel 1 transfer select 4:"]
#[inline(always)]
pub fn dma1tsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel4)
}
#[doc = "DMA channel 1 transfer select 5:"]
#[inline(always)]
pub fn dma1tsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel5)
}
#[doc = "DMA channel 1 transfer select 6:"]
#[inline(always)]
pub fn dma1tsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel6)
}
#[doc = "DMA channel 1 transfer select 7:"]
#[inline(always)]
pub fn dma1tsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel7)
}
#[doc = "DMA channel 1 transfer select 8:"]
#[inline(always)]
pub fn dma1tsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel8)
}
#[doc = "DMA channel 1 transfer select 9:"]
#[inline(always)]
pub fn dma1tsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel9)
}
#[doc = "DMA channel 1 transfer select 10:"]
#[inline(always)]
pub fn dma1tsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel10)
}
#[doc = "DMA channel 1 transfer select 11:"]
#[inline(always)]
pub fn dma1tsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel11)
}
#[doc = "DMA channel 1 transfer select 12:"]
#[inline(always)]
pub fn dma1tsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel12)
}
#[doc = "DMA channel 1 transfer select 13:"]
#[inline(always)]
pub fn dma1tsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel13)
}
#[doc = "DMA channel 1 transfer select 14:"]
#[inline(always)]
pub fn dma1tsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel14)
}
#[doc = "DMA channel 1 transfer select 15:"]
#[inline(always)]
pub fn dma1tsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel15)
}
#[doc = "DMA channel 1 transfer select 16:"]
#[inline(always)]
pub fn dma1tsel_16(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel16)
}
#[doc = "DMA channel 1 transfer select 17:"]
#[inline(always)]
pub fn dma1tsel_17(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel17)
}
#[doc = "DMA channel 1 transfer select 18:"]
#[inline(always)]
pub fn dma1tsel_18(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel18)
}
#[doc = "DMA channel 1 transfer select 19:"]
#[inline(always)]
pub fn dma1tsel_19(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel19)
}
#[doc = "DMA channel 1 transfer select 20:"]
#[inline(always)]
pub fn dma1tsel_20(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel20)
}
#[doc = "DMA channel 1 transfer select 21:"]
#[inline(always)]
pub fn dma1tsel_21(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel21)
}
#[doc = "DMA channel 1 transfer select 22:"]
#[inline(always)]
pub fn dma1tsel_22(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel22)
}
#[doc = "DMA channel 1 transfer select 23:"]
#[inline(always)]
pub fn dma1tsel_23(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel23)
}
#[doc = "DMA channel 1 transfer select 24:"]
#[inline(always)]
pub fn dma1tsel_24(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel24)
}
#[doc = "DMA channel 1 transfer select 25:"]
#[inline(always)]
pub fn dma1tsel_25(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel25)
}
#[doc = "DMA channel 1 transfer select 26:"]
#[inline(always)]
pub fn dma1tsel_26(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel26)
}
#[doc = "DMA channel 1 transfer select 27:"]
#[inline(always)]
pub fn dma1tsel_27(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel27)
}
#[doc = "DMA channel 1 transfer select 28:"]
#[inline(always)]
pub fn dma1tsel_28(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel28)
}
#[doc = "DMA channel 1 transfer select 29:"]
#[inline(always)]
pub fn dma1tsel_29(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel29)
}
#[doc = "DMA channel 1 transfer select 30: previous DMA channel DMA0IFG"]
#[inline(always)]
pub fn dma1tsel_30(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel30)
}
#[doc = "DMA channel 1 transfer select 31: ext. Trigger (DMAE0)"]
#[inline(always)]
pub fn dma1tsel_31(self) -> &'a mut crate::W<REG> {
self.variant(Dma1tsel::Dma1tsel31)
}
}
impl R {
#[doc = "Bits 0:4 - DMA channel 0 transfer select bit 0"]
#[inline(always)]
pub fn dma0tsel(&self) -> Dma0tselR {
Dma0tselR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 8:12 - DMA channel 1 transfer select bit 0"]
#[inline(always)]
pub fn dma1tsel(&self) -> Dma1tselR {
Dma1tselR::new(((self.bits >> 8) & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:4 - DMA channel 0 transfer select bit 0"]
#[inline(always)]
pub fn dma0tsel(&mut self) -> Dma0tselW<'_, Dmactl0Spec> {
Dma0tselW::new(self, 0)
}
#[doc = "Bits 8:12 - DMA channel 1 transfer select bit 0"]
#[inline(always)]
pub fn dma1tsel(&mut self) -> Dma1tselW<'_, Dmactl0Spec> {
Dma1tselW::new(self, 8)
}
}
#[doc = "DMA Module Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dmactl0Spec;
impl crate::RegisterSpec for Dmactl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`dmactl0::R`](R) reader structure"]
impl crate::Readable for Dmactl0Spec {}
#[doc = "`write(|w| ..)` method takes [`dmactl0::W`](W) writer structure"]
impl crate::Writable for Dmactl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMACTL0 to value 0"]
impl crate::Resettable for Dmactl0Spec {}
}
#[doc = "DMACTL1 (rw) register accessor: DMA Module Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmactl1`] module"]
#[doc(alias = "DMACTL1")]
pub type Dmactl1 = crate::Reg<dmactl1::Dmactl1Spec>;
#[doc = "DMA Module Control 1"]
pub mod dmactl1 {
#[doc = "Register `DMACTL1` reader"]
pub type R = crate::R<Dmactl1Spec>;
#[doc = "Register `DMACTL1` writer"]
pub type W = crate::W<Dmactl1Spec>;
#[doc = "DMA channel 2 transfer select bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dma2tsel {
#[doc = "0: DMA channel 2 transfer select 0: DMA_REQ (sw)"]
Dma2tsel0 = 0,
#[doc = "1: DMA channel 2 transfer select 1:"]
Dma2tsel1 = 1,
#[doc = "2: DMA channel 2 transfer select 2:"]
Dma2tsel2 = 2,
#[doc = "3: DMA channel 2 transfer select 3:"]
Dma2tsel3 = 3,
#[doc = "4: DMA channel 2 transfer select 4:"]
Dma2tsel4 = 4,
#[doc = "5: DMA channel 2 transfer select 5:"]
Dma2tsel5 = 5,
#[doc = "6: DMA channel 2 transfer select 6:"]
Dma2tsel6 = 6,
#[doc = "7: DMA channel 2 transfer select 7:"]
Dma2tsel7 = 7,
#[doc = "8: DMA channel 2 transfer select 8:"]
Dma2tsel8 = 8,
#[doc = "9: DMA channel 2 transfer select 9:"]
Dma2tsel9 = 9,
#[doc = "10: DMA channel 2 transfer select 10:"]
Dma2tsel10 = 10,
#[doc = "11: DMA channel 2 transfer select 11:"]
Dma2tsel11 = 11,
#[doc = "12: DMA channel 2 transfer select 12:"]
Dma2tsel12 = 12,
#[doc = "13: DMA channel 2 transfer select 13:"]
Dma2tsel13 = 13,
#[doc = "14: DMA channel 2 transfer select 14:"]
Dma2tsel14 = 14,
#[doc = "15: DMA channel 2 transfer select 15:"]
Dma2tsel15 = 15,
#[doc = "16: DMA channel 2 transfer select 16:"]
Dma2tsel16 = 16,
#[doc = "17: DMA channel 2 transfer select 17:"]
Dma2tsel17 = 17,
#[doc = "18: DMA channel 2 transfer select 18:"]
Dma2tsel18 = 18,
#[doc = "19: DMA channel 2 transfer select 19:"]
Dma2tsel19 = 19,
#[doc = "20: DMA channel 2 transfer select 20:"]
Dma2tsel20 = 20,
#[doc = "21: DMA channel 2 transfer select 21:"]
Dma2tsel21 = 21,
#[doc = "22: DMA channel 2 transfer select 22:"]
Dma2tsel22 = 22,
#[doc = "23: DMA channel 2 transfer select 23:"]
Dma2tsel23 = 23,
#[doc = "24: DMA channel 2 transfer select 24:"]
Dma2tsel24 = 24,
#[doc = "25: DMA channel 2 transfer select 25:"]
Dma2tsel25 = 25,
#[doc = "26: DMA channel 2 transfer select 26:"]
Dma2tsel26 = 26,
#[doc = "27: DMA channel 2 transfer select 27:"]
Dma2tsel27 = 27,
#[doc = "28: DMA channel 2 transfer select 28:"]
Dma2tsel28 = 28,
#[doc = "29: DMA channel 2 transfer select 29:"]
Dma2tsel29 = 29,
#[doc = "30: DMA channel 2 transfer select 30: previous DMA channel DMA1IFG"]
Dma2tsel30 = 30,
#[doc = "31: DMA channel 2 transfer select 31: ext. Trigger (DMAE0)"]
Dma2tsel31 = 31,
}
impl From<Dma2tsel> for u8 {
#[inline(always)]
fn from(variant: Dma2tsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dma2tsel {
type Ux = u8;
}
impl crate::IsEnum for Dma2tsel {}
#[doc = "Field `DMA2TSEL` reader - DMA channel 2 transfer select bit 0"]
pub type Dma2tselR = crate::FieldReader<Dma2tsel>;
impl Dma2tselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dma2tsel {
match self.bits {
0 => Dma2tsel::Dma2tsel0,
1 => Dma2tsel::Dma2tsel1,
2 => Dma2tsel::Dma2tsel2,
3 => Dma2tsel::Dma2tsel3,
4 => Dma2tsel::Dma2tsel4,
5 => Dma2tsel::Dma2tsel5,
6 => Dma2tsel::Dma2tsel6,
7 => Dma2tsel::Dma2tsel7,
8 => Dma2tsel::Dma2tsel8,
9 => Dma2tsel::Dma2tsel9,
10 => Dma2tsel::Dma2tsel10,
11 => Dma2tsel::Dma2tsel11,
12 => Dma2tsel::Dma2tsel12,
13 => Dma2tsel::Dma2tsel13,
14 => Dma2tsel::Dma2tsel14,
15 => Dma2tsel::Dma2tsel15,
16 => Dma2tsel::Dma2tsel16,
17 => Dma2tsel::Dma2tsel17,
18 => Dma2tsel::Dma2tsel18,
19 => Dma2tsel::Dma2tsel19,
20 => Dma2tsel::Dma2tsel20,
21 => Dma2tsel::Dma2tsel21,
22 => Dma2tsel::Dma2tsel22,
23 => Dma2tsel::Dma2tsel23,
24 => Dma2tsel::Dma2tsel24,
25 => Dma2tsel::Dma2tsel25,
26 => Dma2tsel::Dma2tsel26,
27 => Dma2tsel::Dma2tsel27,
28 => Dma2tsel::Dma2tsel28,
29 => Dma2tsel::Dma2tsel29,
30 => Dma2tsel::Dma2tsel30,
31 => Dma2tsel::Dma2tsel31,
_ => unreachable!(),
}
}
#[doc = "DMA channel 2 transfer select 0: DMA_REQ (sw)"]
#[inline(always)]
pub fn is_dma2tsel_0(&self) -> bool {
*self == Dma2tsel::Dma2tsel0
}
#[doc = "DMA channel 2 transfer select 1:"]
#[inline(always)]
pub fn is_dma2tsel_1(&self) -> bool {
*self == Dma2tsel::Dma2tsel1
}
#[doc = "DMA channel 2 transfer select 2:"]
#[inline(always)]
pub fn is_dma2tsel_2(&self) -> bool {
*self == Dma2tsel::Dma2tsel2
}
#[doc = "DMA channel 2 transfer select 3:"]
#[inline(always)]
pub fn is_dma2tsel_3(&self) -> bool {
*self == Dma2tsel::Dma2tsel3
}
#[doc = "DMA channel 2 transfer select 4:"]
#[inline(always)]
pub fn is_dma2tsel_4(&self) -> bool {
*self == Dma2tsel::Dma2tsel4
}
#[doc = "DMA channel 2 transfer select 5:"]
#[inline(always)]
pub fn is_dma2tsel_5(&self) -> bool {
*self == Dma2tsel::Dma2tsel5
}
#[doc = "DMA channel 2 transfer select 6:"]
#[inline(always)]
pub fn is_dma2tsel_6(&self) -> bool {
*self == Dma2tsel::Dma2tsel6
}
#[doc = "DMA channel 2 transfer select 7:"]
#[inline(always)]
pub fn is_dma2tsel_7(&self) -> bool {
*self == Dma2tsel::Dma2tsel7
}
#[doc = "DMA channel 2 transfer select 8:"]
#[inline(always)]
pub fn is_dma2tsel_8(&self) -> bool {
*self == Dma2tsel::Dma2tsel8
}
#[doc = "DMA channel 2 transfer select 9:"]
#[inline(always)]
pub fn is_dma2tsel_9(&self) -> bool {
*self == Dma2tsel::Dma2tsel9
}
#[doc = "DMA channel 2 transfer select 10:"]
#[inline(always)]
pub fn is_dma2tsel_10(&self) -> bool {
*self == Dma2tsel::Dma2tsel10
}
#[doc = "DMA channel 2 transfer select 11:"]
#[inline(always)]
pub fn is_dma2tsel_11(&self) -> bool {
*self == Dma2tsel::Dma2tsel11
}
#[doc = "DMA channel 2 transfer select 12:"]
#[inline(always)]
pub fn is_dma2tsel_12(&self) -> bool {
*self == Dma2tsel::Dma2tsel12
}
#[doc = "DMA channel 2 transfer select 13:"]
#[inline(always)]
pub fn is_dma2tsel_13(&self) -> bool {
*self == Dma2tsel::Dma2tsel13
}
#[doc = "DMA channel 2 transfer select 14:"]
#[inline(always)]
pub fn is_dma2tsel_14(&self) -> bool {
*self == Dma2tsel::Dma2tsel14
}
#[doc = "DMA channel 2 transfer select 15:"]
#[inline(always)]
pub fn is_dma2tsel_15(&self) -> bool {
*self == Dma2tsel::Dma2tsel15
}
#[doc = "DMA channel 2 transfer select 16:"]
#[inline(always)]
pub fn is_dma2tsel_16(&self) -> bool {
*self == Dma2tsel::Dma2tsel16
}
#[doc = "DMA channel 2 transfer select 17:"]
#[inline(always)]
pub fn is_dma2tsel_17(&self) -> bool {
*self == Dma2tsel::Dma2tsel17
}
#[doc = "DMA channel 2 transfer select 18:"]
#[inline(always)]
pub fn is_dma2tsel_18(&self) -> bool {
*self == Dma2tsel::Dma2tsel18
}
#[doc = "DMA channel 2 transfer select 19:"]
#[inline(always)]
pub fn is_dma2tsel_19(&self) -> bool {
*self == Dma2tsel::Dma2tsel19
}
#[doc = "DMA channel 2 transfer select 20:"]
#[inline(always)]
pub fn is_dma2tsel_20(&self) -> bool {
*self == Dma2tsel::Dma2tsel20
}
#[doc = "DMA channel 2 transfer select 21:"]
#[inline(always)]
pub fn is_dma2tsel_21(&self) -> bool {
*self == Dma2tsel::Dma2tsel21
}
#[doc = "DMA channel 2 transfer select 22:"]
#[inline(always)]
pub fn is_dma2tsel_22(&self) -> bool {
*self == Dma2tsel::Dma2tsel22
}
#[doc = "DMA channel 2 transfer select 23:"]
#[inline(always)]
pub fn is_dma2tsel_23(&self) -> bool {
*self == Dma2tsel::Dma2tsel23
}
#[doc = "DMA channel 2 transfer select 24:"]
#[inline(always)]
pub fn is_dma2tsel_24(&self) -> bool {
*self == Dma2tsel::Dma2tsel24
}
#[doc = "DMA channel 2 transfer select 25:"]
#[inline(always)]
pub fn is_dma2tsel_25(&self) -> bool {
*self == Dma2tsel::Dma2tsel25
}
#[doc = "DMA channel 2 transfer select 26:"]
#[inline(always)]
pub fn is_dma2tsel_26(&self) -> bool {
*self == Dma2tsel::Dma2tsel26
}
#[doc = "DMA channel 2 transfer select 27:"]
#[inline(always)]
pub fn is_dma2tsel_27(&self) -> bool {
*self == Dma2tsel::Dma2tsel27
}
#[doc = "DMA channel 2 transfer select 28:"]
#[inline(always)]
pub fn is_dma2tsel_28(&self) -> bool {
*self == Dma2tsel::Dma2tsel28
}
#[doc = "DMA channel 2 transfer select 29:"]
#[inline(always)]
pub fn is_dma2tsel_29(&self) -> bool {
*self == Dma2tsel::Dma2tsel29
}
#[doc = "DMA channel 2 transfer select 30: previous DMA channel DMA1IFG"]
#[inline(always)]
pub fn is_dma2tsel_30(&self) -> bool {
*self == Dma2tsel::Dma2tsel30
}
#[doc = "DMA channel 2 transfer select 31: ext. Trigger (DMAE0)"]
#[inline(always)]
pub fn is_dma2tsel_31(&self) -> bool {
*self == Dma2tsel::Dma2tsel31
}
}
#[doc = "Field `DMA2TSEL` writer - DMA channel 2 transfer select bit 0"]
pub type Dma2tselW<'a, REG> = crate::FieldWriter<'a, REG, 5, Dma2tsel, crate::Safe>;
impl<'a, REG> Dma2tselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "DMA channel 2 transfer select 0: DMA_REQ (sw)"]
#[inline(always)]
pub fn dma2tsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel0)
}
#[doc = "DMA channel 2 transfer select 1:"]
#[inline(always)]
pub fn dma2tsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel1)
}
#[doc = "DMA channel 2 transfer select 2:"]
#[inline(always)]
pub fn dma2tsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel2)
}
#[doc = "DMA channel 2 transfer select 3:"]
#[inline(always)]
pub fn dma2tsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel3)
}
#[doc = "DMA channel 2 transfer select 4:"]
#[inline(always)]
pub fn dma2tsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel4)
}
#[doc = "DMA channel 2 transfer select 5:"]
#[inline(always)]
pub fn dma2tsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel5)
}
#[doc = "DMA channel 2 transfer select 6:"]
#[inline(always)]
pub fn dma2tsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel6)
}
#[doc = "DMA channel 2 transfer select 7:"]
#[inline(always)]
pub fn dma2tsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel7)
}
#[doc = "DMA channel 2 transfer select 8:"]
#[inline(always)]
pub fn dma2tsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel8)
}
#[doc = "DMA channel 2 transfer select 9:"]
#[inline(always)]
pub fn dma2tsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel9)
}
#[doc = "DMA channel 2 transfer select 10:"]
#[inline(always)]
pub fn dma2tsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel10)
}
#[doc = "DMA channel 2 transfer select 11:"]
#[inline(always)]
pub fn dma2tsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel11)
}
#[doc = "DMA channel 2 transfer select 12:"]
#[inline(always)]
pub fn dma2tsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel12)
}
#[doc = "DMA channel 2 transfer select 13:"]
#[inline(always)]
pub fn dma2tsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel13)
}
#[doc = "DMA channel 2 transfer select 14:"]
#[inline(always)]
pub fn dma2tsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel14)
}
#[doc = "DMA channel 2 transfer select 15:"]
#[inline(always)]
pub fn dma2tsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel15)
}
#[doc = "DMA channel 2 transfer select 16:"]
#[inline(always)]
pub fn dma2tsel_16(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel16)
}
#[doc = "DMA channel 2 transfer select 17:"]
#[inline(always)]
pub fn dma2tsel_17(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel17)
}
#[doc = "DMA channel 2 transfer select 18:"]
#[inline(always)]
pub fn dma2tsel_18(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel18)
}
#[doc = "DMA channel 2 transfer select 19:"]
#[inline(always)]
pub fn dma2tsel_19(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel19)
}
#[doc = "DMA channel 2 transfer select 20:"]
#[inline(always)]
pub fn dma2tsel_20(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel20)
}
#[doc = "DMA channel 2 transfer select 21:"]
#[inline(always)]
pub fn dma2tsel_21(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel21)
}
#[doc = "DMA channel 2 transfer select 22:"]
#[inline(always)]
pub fn dma2tsel_22(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel22)
}
#[doc = "DMA channel 2 transfer select 23:"]
#[inline(always)]
pub fn dma2tsel_23(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel23)
}
#[doc = "DMA channel 2 transfer select 24:"]
#[inline(always)]
pub fn dma2tsel_24(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel24)
}
#[doc = "DMA channel 2 transfer select 25:"]
#[inline(always)]
pub fn dma2tsel_25(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel25)
}
#[doc = "DMA channel 2 transfer select 26:"]
#[inline(always)]
pub fn dma2tsel_26(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel26)
}
#[doc = "DMA channel 2 transfer select 27:"]
#[inline(always)]
pub fn dma2tsel_27(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel27)
}
#[doc = "DMA channel 2 transfer select 28:"]
#[inline(always)]
pub fn dma2tsel_28(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel28)
}
#[doc = "DMA channel 2 transfer select 29:"]
#[inline(always)]
pub fn dma2tsel_29(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel29)
}
#[doc = "DMA channel 2 transfer select 30: previous DMA channel DMA1IFG"]
#[inline(always)]
pub fn dma2tsel_30(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel30)
}
#[doc = "DMA channel 2 transfer select 31: ext. Trigger (DMAE0)"]
#[inline(always)]
pub fn dma2tsel_31(self) -> &'a mut crate::W<REG> {
self.variant(Dma2tsel::Dma2tsel31)
}
}
impl R {
#[doc = "Bits 0:4 - DMA channel 2 transfer select bit 0"]
#[inline(always)]
pub fn dma2tsel(&self) -> Dma2tselR {
Dma2tselR::new((self.bits & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:4 - DMA channel 2 transfer select bit 0"]
#[inline(always)]
pub fn dma2tsel(&mut self) -> Dma2tselW<'_, Dmactl1Spec> {
Dma2tselW::new(self, 0)
}
}
#[doc = "DMA Module Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dmactl1Spec;
impl crate::RegisterSpec for Dmactl1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`dmactl1::R`](R) reader structure"]
impl crate::Readable for Dmactl1Spec {}
#[doc = "`write(|w| ..)` method takes [`dmactl1::W`](W) writer structure"]
impl crate::Writable for Dmactl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMACTL1 to value 0"]
impl crate::Resettable for Dmactl1Spec {}
}
#[doc = "DMACTL2 (rw) register accessor: DMA Module Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmactl2`] module"]
#[doc(alias = "DMACTL2")]
pub type Dmactl2 = crate::Reg<dmactl2::Dmactl2Spec>;
#[doc = "DMA Module Control 2"]
pub mod dmactl2 {
#[doc = "Register `DMACTL2` reader"]
pub type R = crate::R<Dmactl2Spec>;
#[doc = "Register `DMACTL2` writer"]
pub type W = crate::W<Dmactl2Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "DMA Module Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dmactl2Spec;
impl crate::RegisterSpec for Dmactl2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`dmactl2::R`](R) reader structure"]
impl crate::Readable for Dmactl2Spec {}
#[doc = "`write(|w| ..)` method takes [`dmactl2::W`](W) writer structure"]
impl crate::Writable for Dmactl2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMACTL2 to value 0"]
impl crate::Resettable for Dmactl2Spec {}
}
#[doc = "DMACTL3 (rw) register accessor: DMA Module Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmactl3`] module"]
#[doc(alias = "DMACTL3")]
pub type Dmactl3 = crate::Reg<dmactl3::Dmactl3Spec>;
#[doc = "DMA Module Control 3"]
pub mod dmactl3 {
#[doc = "Register `DMACTL3` reader"]
pub type R = crate::R<Dmactl3Spec>;
#[doc = "Register `DMACTL3` writer"]
pub type W = crate::W<Dmactl3Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "DMA Module Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dmactl3Spec;
impl crate::RegisterSpec for Dmactl3Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`dmactl3::R`](R) reader structure"]
impl crate::Readable for Dmactl3Spec {}
#[doc = "`write(|w| ..)` method takes [`dmactl3::W`](W) writer structure"]
impl crate::Writable for Dmactl3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMACTL3 to value 0"]
impl crate::Resettable for Dmactl3Spec {}
}
#[doc = "DMACTL4 (rw) register accessor: DMA Module Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactl4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactl4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmactl4`] module"]
#[doc(alias = "DMACTL4")]
pub type Dmactl4 = crate::Reg<dmactl4::Dmactl4Spec>;
#[doc = "DMA Module Control 4"]
pub mod dmactl4 {
#[doc = "Register `DMACTL4` reader"]
pub type R = crate::R<Dmactl4Spec>;
#[doc = "Register `DMACTL4` writer"]
pub type W = crate::W<Dmactl4Spec>;
#[doc = "Field `ENNMI` reader - Enable NMI interruption of DMA"]
pub type EnnmiR = crate::BitReader;
#[doc = "Field `ENNMI` writer - Enable NMI interruption of DMA"]
pub type EnnmiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ROUNDROBIN` reader - Round-Robin DMA channel priorities"]
pub type RoundrobinR = crate::BitReader;
#[doc = "Field `ROUNDROBIN` writer - Round-Robin DMA channel priorities"]
pub type RoundrobinW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMARMWDIS` reader - Inhibited DMA transfers during read-modify-write CPU operations"]
pub type DmarmwdisR = crate::BitReader;
#[doc = "Field `DMARMWDIS` writer - Inhibited DMA transfers during read-modify-write CPU operations"]
pub type DmarmwdisW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Enable NMI interruption of DMA"]
#[inline(always)]
pub fn ennmi(&self) -> EnnmiR {
EnnmiR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Round-Robin DMA channel priorities"]
#[inline(always)]
pub fn roundrobin(&self) -> RoundrobinR {
RoundrobinR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Inhibited DMA transfers during read-modify-write CPU operations"]
#[inline(always)]
pub fn dmarmwdis(&self) -> DmarmwdisR {
DmarmwdisR::new(((self.bits >> 2) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Enable NMI interruption of DMA"]
#[inline(always)]
pub fn ennmi(&mut self) -> EnnmiW<'_, Dmactl4Spec> {
EnnmiW::new(self, 0)
}
#[doc = "Bit 1 - Round-Robin DMA channel priorities"]
#[inline(always)]
pub fn roundrobin(&mut self) -> RoundrobinW<'_, Dmactl4Spec> {
RoundrobinW::new(self, 1)
}
#[doc = "Bit 2 - Inhibited DMA transfers during read-modify-write CPU operations"]
#[inline(always)]
pub fn dmarmwdis(&mut self) -> DmarmwdisW<'_, Dmactl4Spec> {
DmarmwdisW::new(self, 2)
}
}
#[doc = "DMA Module Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`dmactl4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmactl4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dmactl4Spec;
impl crate::RegisterSpec for Dmactl4Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`dmactl4::R`](R) reader structure"]
impl crate::Readable for Dmactl4Spec {}
#[doc = "`write(|w| ..)` method takes [`dmactl4::W`](W) writer structure"]
impl crate::Writable for Dmactl4Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMACTL4 to value 0"]
impl crate::Resettable for Dmactl4Spec {}
}
#[doc = "DMAIV (rw) register accessor: DMA Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`dmaiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmaiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmaiv`] module"]
#[doc(alias = "DMAIV")]
pub type Dmaiv = crate::Reg<dmaiv::DmaivSpec>;
#[doc = "DMA Interrupt Vector Word"]
pub mod dmaiv {
#[doc = "Register `DMAIV` reader"]
pub type R = crate::R<DmaivSpec>;
#[doc = "Register `DMAIV` writer"]
pub type W = crate::W<DmaivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "DMA Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`dmaiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmaiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DmaivSpec;
impl crate::RegisterSpec for DmaivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`dmaiv::R`](R) reader structure"]
impl crate::Readable for DmaivSpec {}
#[doc = "`write(|w| ..)` method takes [`dmaiv::W`](W) writer structure"]
impl crate::Writable for DmaivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMAIV to value 0"]
impl crate::Resettable for DmaivSpec {}
}
#[doc = "DMA0CTL (rw) register accessor: DMA Channel 0 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dma0ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma0ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma0ctl`] module"]
#[doc(alias = "DMA0CTL")]
pub type Dma0ctl = crate::Reg<dma0ctl::Dma0ctlSpec>;
#[doc = "DMA Channel 0 Control"]
pub mod dma0ctl {
#[doc = "Register `DMA0CTL` reader"]
pub type R = crate::R<Dma0ctlSpec>;
#[doc = "Register `DMA0CTL` writer"]
pub type W = crate::W<Dma0ctlSpec>;
#[doc = "Field `DMAREQ` reader - Initiate DMA transfer with DMATSEL"]
pub type DmareqR = crate::BitReader;
#[doc = "Field `DMAREQ` writer - Initiate DMA transfer with DMATSEL"]
pub type DmareqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAABORT` reader - DMA transfer aborted by NMI"]
pub type DmaabortR = crate::BitReader;
#[doc = "Field `DMAABORT` writer - DMA transfer aborted by NMI"]
pub type DmaabortW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAIE` reader - DMA interrupt enable"]
pub type DmaieR = crate::BitReader;
#[doc = "Field `DMAIE` writer - DMA interrupt enable"]
pub type DmaieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAIFG` reader - DMA interrupt flag"]
pub type DmaifgR = crate::BitReader;
#[doc = "Field `DMAIFG` writer - DMA interrupt flag"]
pub type DmaifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAEN` reader - DMA enable"]
pub type DmaenR = crate::BitReader;
#[doc = "Field `DMAEN` writer - DMA enable"]
pub type DmaenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMALEVEL` reader - DMA level sensitive trigger select"]
pub type DmalevelR = crate::BitReader;
#[doc = "Field `DMALEVEL` writer - DMA level sensitive trigger select"]
pub type DmalevelW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMASRCBYTE` reader - DMA source byte"]
pub type DmasrcbyteR = crate::BitReader;
#[doc = "Field `DMASRCBYTE` writer - DMA source byte"]
pub type DmasrcbyteW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMADSTBYTE` reader - DMA destination byte"]
pub type DmadstbyteR = crate::BitReader;
#[doc = "Field `DMADSTBYTE` writer - DMA destination byte"]
pub type DmadstbyteW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "DMA source increment bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dmasrcincr {
#[doc = "0: DMA source increment 0: source address unchanged"]
Dmasrcincr0 = 0,
#[doc = "1: DMA source increment 1: source address unchanged"]
Dmasrcincr1 = 1,
#[doc = "2: DMA source increment 2: source address decremented"]
Dmasrcincr2 = 2,
#[doc = "3: DMA source increment 3: source address incremented"]
Dmasrcincr3 = 3,
}
impl From<Dmasrcincr> for u8 {
#[inline(always)]
fn from(variant: Dmasrcincr) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dmasrcincr {
type Ux = u8;
}
impl crate::IsEnum for Dmasrcincr {}
#[doc = "Field `DMASRCINCR` reader - DMA source increment bit 0"]
pub type DmasrcincrR = crate::FieldReader<Dmasrcincr>;
impl DmasrcincrR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dmasrcincr {
match self.bits {
0 => Dmasrcincr::Dmasrcincr0,
1 => Dmasrcincr::Dmasrcincr1,
2 => Dmasrcincr::Dmasrcincr2,
3 => Dmasrcincr::Dmasrcincr3,
_ => unreachable!(),
}
}
#[doc = "DMA source increment 0: source address unchanged"]
#[inline(always)]
pub fn is_dmasrcincr_0(&self) -> bool {
*self == Dmasrcincr::Dmasrcincr0
}
#[doc = "DMA source increment 1: source address unchanged"]
#[inline(always)]
pub fn is_dmasrcincr_1(&self) -> bool {
*self == Dmasrcincr::Dmasrcincr1
}
#[doc = "DMA source increment 2: source address decremented"]
#[inline(always)]
pub fn is_dmasrcincr_2(&self) -> bool {
*self == Dmasrcincr::Dmasrcincr2
}
#[doc = "DMA source increment 3: source address incremented"]
#[inline(always)]
pub fn is_dmasrcincr_3(&self) -> bool {
*self == Dmasrcincr::Dmasrcincr3
}
}
#[doc = "Field `DMASRCINCR` writer - DMA source increment bit 0"]
pub type DmasrcincrW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmasrcincr, crate::Safe>;
impl<'a, REG> DmasrcincrW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "DMA source increment 0: source address unchanged"]
#[inline(always)]
pub fn dmasrcincr_0(self) -> &'a mut crate::W<REG> {
self.variant(Dmasrcincr::Dmasrcincr0)
}
#[doc = "DMA source increment 1: source address unchanged"]
#[inline(always)]
pub fn dmasrcincr_1(self) -> &'a mut crate::W<REG> {
self.variant(Dmasrcincr::Dmasrcincr1)
}
#[doc = "DMA source increment 2: source address decremented"]
#[inline(always)]
pub fn dmasrcincr_2(self) -> &'a mut crate::W<REG> {
self.variant(Dmasrcincr::Dmasrcincr2)
}
#[doc = "DMA source increment 3: source address incremented"]
#[inline(always)]
pub fn dmasrcincr_3(self) -> &'a mut crate::W<REG> {
self.variant(Dmasrcincr::Dmasrcincr3)
}
}
#[doc = "DMA destination increment bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dmadstincr {
#[doc = "0: DMA destination increment 0: destination address unchanged"]
Dmadstincr0 = 0,
#[doc = "1: DMA destination increment 1: destination address unchanged"]
Dmadstincr1 = 1,
#[doc = "2: DMA destination increment 2: destination address decremented"]
Dmadstincr2 = 2,
#[doc = "3: DMA destination increment 3: destination address incremented"]
Dmadstincr3 = 3,
}
impl From<Dmadstincr> for u8 {
#[inline(always)]
fn from(variant: Dmadstincr) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dmadstincr {
type Ux = u8;
}
impl crate::IsEnum for Dmadstincr {}
#[doc = "Field `DMADSTINCR` reader - DMA destination increment bit 0"]
pub type DmadstincrR = crate::FieldReader<Dmadstincr>;
impl DmadstincrR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dmadstincr {
match self.bits {
0 => Dmadstincr::Dmadstincr0,
1 => Dmadstincr::Dmadstincr1,
2 => Dmadstincr::Dmadstincr2,
3 => Dmadstincr::Dmadstincr3,
_ => unreachable!(),
}
}
#[doc = "DMA destination increment 0: destination address unchanged"]
#[inline(always)]
pub fn is_dmadstincr_0(&self) -> bool {
*self == Dmadstincr::Dmadstincr0
}
#[doc = "DMA destination increment 1: destination address unchanged"]
#[inline(always)]
pub fn is_dmadstincr_1(&self) -> bool {
*self == Dmadstincr::Dmadstincr1
}
#[doc = "DMA destination increment 2: destination address decremented"]
#[inline(always)]
pub fn is_dmadstincr_2(&self) -> bool {
*self == Dmadstincr::Dmadstincr2
}
#[doc = "DMA destination increment 3: destination address incremented"]
#[inline(always)]
pub fn is_dmadstincr_3(&self) -> bool {
*self == Dmadstincr::Dmadstincr3
}
}
#[doc = "Field `DMADSTINCR` writer - DMA destination increment bit 0"]
pub type DmadstincrW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmadstincr, crate::Safe>;
impl<'a, REG> DmadstincrW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "DMA destination increment 0: destination address unchanged"]
#[inline(always)]
pub fn dmadstincr_0(self) -> &'a mut crate::W<REG> {
self.variant(Dmadstincr::Dmadstincr0)
}
#[doc = "DMA destination increment 1: destination address unchanged"]
#[inline(always)]
pub fn dmadstincr_1(self) -> &'a mut crate::W<REG> {
self.variant(Dmadstincr::Dmadstincr1)
}
#[doc = "DMA destination increment 2: destination address decremented"]
#[inline(always)]
pub fn dmadstincr_2(self) -> &'a mut crate::W<REG> {
self.variant(Dmadstincr::Dmadstincr2)
}
#[doc = "DMA destination increment 3: destination address incremented"]
#[inline(always)]
pub fn dmadstincr_3(self) -> &'a mut crate::W<REG> {
self.variant(Dmadstincr::Dmadstincr3)
}
}
#[doc = "DMA transfer mode bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dmadt {
#[doc = "0: DMA transfer mode 0: Single transfer"]
Dmadt0 = 0,
#[doc = "1: DMA transfer mode 1: Block transfer"]
Dmadt1 = 1,
#[doc = "2: DMA transfer mode 2: Burst-Block transfer"]
Dmadt2 = 2,
#[doc = "3: DMA transfer mode 3: Burst-Block transfer"]
Dmadt3 = 3,
#[doc = "4: DMA transfer mode 4: Repeated Single transfer"]
Dmadt4 = 4,
#[doc = "5: DMA transfer mode 5: Repeated Block transfer"]
Dmadt5 = 5,
#[doc = "6: DMA transfer mode 6: Repeated Burst-Block transfer"]
Dmadt6 = 6,
#[doc = "7: DMA transfer mode 7: Repeated Burst-Block transfer"]
Dmadt7 = 7,
}
impl From<Dmadt> for u8 {
#[inline(always)]
fn from(variant: Dmadt) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dmadt {
type Ux = u8;
}
impl crate::IsEnum for Dmadt {}
#[doc = "Field `DMADT` reader - DMA transfer mode bit 0"]
pub type DmadtR = crate::FieldReader<Dmadt>;
impl DmadtR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dmadt {
match self.bits {
0 => Dmadt::Dmadt0,
1 => Dmadt::Dmadt1,
2 => Dmadt::Dmadt2,
3 => Dmadt::Dmadt3,
4 => Dmadt::Dmadt4,
5 => Dmadt::Dmadt5,
6 => Dmadt::Dmadt6,
7 => Dmadt::Dmadt7,
_ => unreachable!(),
}
}
#[doc = "DMA transfer mode 0: Single transfer"]
#[inline(always)]
pub fn is_dmadt_0(&self) -> bool {
*self == Dmadt::Dmadt0
}
#[doc = "DMA transfer mode 1: Block transfer"]
#[inline(always)]
pub fn is_dmadt_1(&self) -> bool {
*self == Dmadt::Dmadt1
}
#[doc = "DMA transfer mode 2: Burst-Block transfer"]
#[inline(always)]
pub fn is_dmadt_2(&self) -> bool {
*self == Dmadt::Dmadt2
}
#[doc = "DMA transfer mode 3: Burst-Block transfer"]
#[inline(always)]
pub fn is_dmadt_3(&self) -> bool {
*self == Dmadt::Dmadt3
}
#[doc = "DMA transfer mode 4: Repeated Single transfer"]
#[inline(always)]
pub fn is_dmadt_4(&self) -> bool {
*self == Dmadt::Dmadt4
}
#[doc = "DMA transfer mode 5: Repeated Block transfer"]
#[inline(always)]
pub fn is_dmadt_5(&self) -> bool {
*self == Dmadt::Dmadt5
}
#[doc = "DMA transfer mode 6: Repeated Burst-Block transfer"]
#[inline(always)]
pub fn is_dmadt_6(&self) -> bool {
*self == Dmadt::Dmadt6
}
#[doc = "DMA transfer mode 7: Repeated Burst-Block transfer"]
#[inline(always)]
pub fn is_dmadt_7(&self) -> bool {
*self == Dmadt::Dmadt7
}
}
#[doc = "Field `DMADT` writer - DMA transfer mode bit 0"]
pub type DmadtW<'a, REG> = crate::FieldWriter<'a, REG, 3, Dmadt, crate::Safe>;
impl<'a, REG> DmadtW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "DMA transfer mode 0: Single transfer"]
#[inline(always)]
pub fn dmadt_0(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt0)
}
#[doc = "DMA transfer mode 1: Block transfer"]
#[inline(always)]
pub fn dmadt_1(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt1)
}
#[doc = "DMA transfer mode 2: Burst-Block transfer"]
#[inline(always)]
pub fn dmadt_2(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt2)
}
#[doc = "DMA transfer mode 3: Burst-Block transfer"]
#[inline(always)]
pub fn dmadt_3(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt3)
}
#[doc = "DMA transfer mode 4: Repeated Single transfer"]
#[inline(always)]
pub fn dmadt_4(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt4)
}
#[doc = "DMA transfer mode 5: Repeated Block transfer"]
#[inline(always)]
pub fn dmadt_5(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt5)
}
#[doc = "DMA transfer mode 6: Repeated Burst-Block transfer"]
#[inline(always)]
pub fn dmadt_6(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt6)
}
#[doc = "DMA transfer mode 7: Repeated Burst-Block transfer"]
#[inline(always)]
pub fn dmadt_7(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt7)
}
}
impl R {
#[doc = "Bit 0 - Initiate DMA transfer with DMATSEL"]
#[inline(always)]
pub fn dmareq(&self) -> DmareqR {
DmareqR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - DMA transfer aborted by NMI"]
#[inline(always)]
pub fn dmaabort(&self) -> DmaabortR {
DmaabortR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - DMA interrupt enable"]
#[inline(always)]
pub fn dmaie(&self) -> DmaieR {
DmaieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - DMA interrupt flag"]
#[inline(always)]
pub fn dmaifg(&self) -> DmaifgR {
DmaifgR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - DMA enable"]
#[inline(always)]
pub fn dmaen(&self) -> DmaenR {
DmaenR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - DMA level sensitive trigger select"]
#[inline(always)]
pub fn dmalevel(&self) -> DmalevelR {
DmalevelR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - DMA source byte"]
#[inline(always)]
pub fn dmasrcbyte(&self) -> DmasrcbyteR {
DmasrcbyteR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - DMA destination byte"]
#[inline(always)]
pub fn dmadstbyte(&self) -> DmadstbyteR {
DmadstbyteR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - DMA source increment bit 0"]
#[inline(always)]
pub fn dmasrcincr(&self) -> DmasrcincrR {
DmasrcincrR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - DMA destination increment bit 0"]
#[inline(always)]
pub fn dmadstincr(&self) -> DmadstincrR {
DmadstincrR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:14 - DMA transfer mode bit 0"]
#[inline(always)]
pub fn dmadt(&self) -> DmadtR {
DmadtR::new(((self.bits >> 12) & 7) as u8)
}
}
impl W {
#[doc = "Bit 0 - Initiate DMA transfer with DMATSEL"]
#[inline(always)]
pub fn dmareq(&mut self) -> DmareqW<'_, Dma0ctlSpec> {
DmareqW::new(self, 0)
}
#[doc = "Bit 1 - DMA transfer aborted by NMI"]
#[inline(always)]
pub fn dmaabort(&mut self) -> DmaabortW<'_, Dma0ctlSpec> {
DmaabortW::new(self, 1)
}
#[doc = "Bit 2 - DMA interrupt enable"]
#[inline(always)]
pub fn dmaie(&mut self) -> DmaieW<'_, Dma0ctlSpec> {
DmaieW::new(self, 2)
}
#[doc = "Bit 3 - DMA interrupt flag"]
#[inline(always)]
pub fn dmaifg(&mut self) -> DmaifgW<'_, Dma0ctlSpec> {
DmaifgW::new(self, 3)
}
#[doc = "Bit 4 - DMA enable"]
#[inline(always)]
pub fn dmaen(&mut self) -> DmaenW<'_, Dma0ctlSpec> {
DmaenW::new(self, 4)
}
#[doc = "Bit 5 - DMA level sensitive trigger select"]
#[inline(always)]
pub fn dmalevel(&mut self) -> DmalevelW<'_, Dma0ctlSpec> {
DmalevelW::new(self, 5)
}
#[doc = "Bit 6 - DMA source byte"]
#[inline(always)]
pub fn dmasrcbyte(&mut self) -> DmasrcbyteW<'_, Dma0ctlSpec> {
DmasrcbyteW::new(self, 6)
}
#[doc = "Bit 7 - DMA destination byte"]
#[inline(always)]
pub fn dmadstbyte(&mut self) -> DmadstbyteW<'_, Dma0ctlSpec> {
DmadstbyteW::new(self, 7)
}
#[doc = "Bits 8:9 - DMA source increment bit 0"]
#[inline(always)]
pub fn dmasrcincr(&mut self) -> DmasrcincrW<'_, Dma0ctlSpec> {
DmasrcincrW::new(self, 8)
}
#[doc = "Bits 10:11 - DMA destination increment bit 0"]
#[inline(always)]
pub fn dmadstincr(&mut self) -> DmadstincrW<'_, Dma0ctlSpec> {
DmadstincrW::new(self, 10)
}
#[doc = "Bits 12:14 - DMA transfer mode bit 0"]
#[inline(always)]
pub fn dmadt(&mut self) -> DmadtW<'_, Dma0ctlSpec> {
DmadtW::new(self, 12)
}
}
#[doc = "DMA Channel 0 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dma0ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma0ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dma0ctlSpec;
impl crate::RegisterSpec for Dma0ctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`dma0ctl::R`](R) reader structure"]
impl crate::Readable for Dma0ctlSpec {}
#[doc = "`write(|w| ..)` method takes [`dma0ctl::W`](W) writer structure"]
impl crate::Writable for Dma0ctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMA0CTL to value 0"]
impl crate::Resettable for Dma0ctlSpec {}
}
#[doc = "DMA0SZ (rw) register accessor: DMA Channel 0 Transfer Size\n\nYou can [`read`](crate::Reg::read) this register and get [`dma0sz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma0sz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma0sz`] module"]
#[doc(alias = "DMA0SZ")]
pub type Dma0sz = crate::Reg<dma0sz::Dma0szSpec>;
#[doc = "DMA Channel 0 Transfer Size"]
pub mod dma0sz {
#[doc = "Register `DMA0SZ` reader"]
pub type R = crate::R<Dma0szSpec>;
#[doc = "Register `DMA0SZ` writer"]
pub type W = crate::W<Dma0szSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "DMA Channel 0 Transfer Size\n\nYou can [`read`](crate::Reg::read) this register and get [`dma0sz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma0sz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dma0szSpec;
impl crate::RegisterSpec for Dma0szSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`dma0sz::R`](R) reader structure"]
impl crate::Readable for Dma0szSpec {}
#[doc = "`write(|w| ..)` method takes [`dma0sz::W`](W) writer structure"]
impl crate::Writable for Dma0szSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMA0SZ to value 0"]
impl crate::Resettable for Dma0szSpec {}
}
#[doc = "DMA1CTL (rw) register accessor: DMA Channel 1 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dma1ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma1ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma1ctl`] module"]
#[doc(alias = "DMA1CTL")]
pub type Dma1ctl = crate::Reg<dma1ctl::Dma1ctlSpec>;
#[doc = "DMA Channel 1 Control"]
pub mod dma1ctl {
#[doc = "Register `DMA1CTL` reader"]
pub type R = crate::R<Dma1ctlSpec>;
#[doc = "Register `DMA1CTL` writer"]
pub type W = crate::W<Dma1ctlSpec>;
#[doc = "Field `DMAREQ` reader - Initiate DMA transfer with DMATSEL"]
pub type DmareqR = crate::BitReader;
#[doc = "Field `DMAREQ` writer - Initiate DMA transfer with DMATSEL"]
pub type DmareqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAABORT` reader - DMA transfer aborted by NMI"]
pub type DmaabortR = crate::BitReader;
#[doc = "Field `DMAABORT` writer - DMA transfer aborted by NMI"]
pub type DmaabortW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAIE` reader - DMA interrupt enable"]
pub type DmaieR = crate::BitReader;
#[doc = "Field `DMAIE` writer - DMA interrupt enable"]
pub type DmaieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAIFG` reader - DMA interrupt flag"]
pub type DmaifgR = crate::BitReader;
#[doc = "Field `DMAIFG` writer - DMA interrupt flag"]
pub type DmaifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAEN` reader - DMA enable"]
pub type DmaenR = crate::BitReader;
#[doc = "Field `DMAEN` writer - DMA enable"]
pub type DmaenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMALEVEL` reader - DMA level sensitive trigger select"]
pub type DmalevelR = crate::BitReader;
#[doc = "Field `DMALEVEL` writer - DMA level sensitive trigger select"]
pub type DmalevelW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMASRCBYTE` reader - DMA source byte"]
pub type DmasrcbyteR = crate::BitReader;
#[doc = "Field `DMASRCBYTE` writer - DMA source byte"]
pub type DmasrcbyteW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMADSTBYTE` reader - DMA destination byte"]
pub type DmadstbyteR = crate::BitReader;
#[doc = "Field `DMADSTBYTE` writer - DMA destination byte"]
pub type DmadstbyteW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "DMA source increment bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dmasrcincr {
#[doc = "0: DMA source increment 0: source address unchanged"]
Dmasrcincr0 = 0,
#[doc = "1: DMA source increment 1: source address unchanged"]
Dmasrcincr1 = 1,
#[doc = "2: DMA source increment 2: source address decremented"]
Dmasrcincr2 = 2,
#[doc = "3: DMA source increment 3: source address incremented"]
Dmasrcincr3 = 3,
}
impl From<Dmasrcincr> for u8 {
#[inline(always)]
fn from(variant: Dmasrcincr) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dmasrcincr {
type Ux = u8;
}
impl crate::IsEnum for Dmasrcincr {}
#[doc = "Field `DMASRCINCR` reader - DMA source increment bit 0"]
pub type DmasrcincrR = crate::FieldReader<Dmasrcincr>;
impl DmasrcincrR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dmasrcincr {
match self.bits {
0 => Dmasrcincr::Dmasrcincr0,
1 => Dmasrcincr::Dmasrcincr1,
2 => Dmasrcincr::Dmasrcincr2,
3 => Dmasrcincr::Dmasrcincr3,
_ => unreachable!(),
}
}
#[doc = "DMA source increment 0: source address unchanged"]
#[inline(always)]
pub fn is_dmasrcincr_0(&self) -> bool {
*self == Dmasrcincr::Dmasrcincr0
}
#[doc = "DMA source increment 1: source address unchanged"]
#[inline(always)]
pub fn is_dmasrcincr_1(&self) -> bool {
*self == Dmasrcincr::Dmasrcincr1
}
#[doc = "DMA source increment 2: source address decremented"]
#[inline(always)]
pub fn is_dmasrcincr_2(&self) -> bool {
*self == Dmasrcincr::Dmasrcincr2
}
#[doc = "DMA source increment 3: source address incremented"]
#[inline(always)]
pub fn is_dmasrcincr_3(&self) -> bool {
*self == Dmasrcincr::Dmasrcincr3
}
}
#[doc = "Field `DMASRCINCR` writer - DMA source increment bit 0"]
pub type DmasrcincrW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmasrcincr, crate::Safe>;
impl<'a, REG> DmasrcincrW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "DMA source increment 0: source address unchanged"]
#[inline(always)]
pub fn dmasrcincr_0(self) -> &'a mut crate::W<REG> {
self.variant(Dmasrcincr::Dmasrcincr0)
}
#[doc = "DMA source increment 1: source address unchanged"]
#[inline(always)]
pub fn dmasrcincr_1(self) -> &'a mut crate::W<REG> {
self.variant(Dmasrcincr::Dmasrcincr1)
}
#[doc = "DMA source increment 2: source address decremented"]
#[inline(always)]
pub fn dmasrcincr_2(self) -> &'a mut crate::W<REG> {
self.variant(Dmasrcincr::Dmasrcincr2)
}
#[doc = "DMA source increment 3: source address incremented"]
#[inline(always)]
pub fn dmasrcincr_3(self) -> &'a mut crate::W<REG> {
self.variant(Dmasrcincr::Dmasrcincr3)
}
}
#[doc = "DMA destination increment bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dmadstincr {
#[doc = "0: DMA destination increment 0: destination address unchanged"]
Dmadstincr0 = 0,
#[doc = "1: DMA destination increment 1: destination address unchanged"]
Dmadstincr1 = 1,
#[doc = "2: DMA destination increment 2: destination address decremented"]
Dmadstincr2 = 2,
#[doc = "3: DMA destination increment 3: destination address incremented"]
Dmadstincr3 = 3,
}
impl From<Dmadstincr> for u8 {
#[inline(always)]
fn from(variant: Dmadstincr) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dmadstincr {
type Ux = u8;
}
impl crate::IsEnum for Dmadstincr {}
#[doc = "Field `DMADSTINCR` reader - DMA destination increment bit 0"]
pub type DmadstincrR = crate::FieldReader<Dmadstincr>;
impl DmadstincrR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dmadstincr {
match self.bits {
0 => Dmadstincr::Dmadstincr0,
1 => Dmadstincr::Dmadstincr1,
2 => Dmadstincr::Dmadstincr2,
3 => Dmadstincr::Dmadstincr3,
_ => unreachable!(),
}
}
#[doc = "DMA destination increment 0: destination address unchanged"]
#[inline(always)]
pub fn is_dmadstincr_0(&self) -> bool {
*self == Dmadstincr::Dmadstincr0
}
#[doc = "DMA destination increment 1: destination address unchanged"]
#[inline(always)]
pub fn is_dmadstincr_1(&self) -> bool {
*self == Dmadstincr::Dmadstincr1
}
#[doc = "DMA destination increment 2: destination address decremented"]
#[inline(always)]
pub fn is_dmadstincr_2(&self) -> bool {
*self == Dmadstincr::Dmadstincr2
}
#[doc = "DMA destination increment 3: destination address incremented"]
#[inline(always)]
pub fn is_dmadstincr_3(&self) -> bool {
*self == Dmadstincr::Dmadstincr3
}
}
#[doc = "Field `DMADSTINCR` writer - DMA destination increment bit 0"]
pub type DmadstincrW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmadstincr, crate::Safe>;
impl<'a, REG> DmadstincrW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "DMA destination increment 0: destination address unchanged"]
#[inline(always)]
pub fn dmadstincr_0(self) -> &'a mut crate::W<REG> {
self.variant(Dmadstincr::Dmadstincr0)
}
#[doc = "DMA destination increment 1: destination address unchanged"]
#[inline(always)]
pub fn dmadstincr_1(self) -> &'a mut crate::W<REG> {
self.variant(Dmadstincr::Dmadstincr1)
}
#[doc = "DMA destination increment 2: destination address decremented"]
#[inline(always)]
pub fn dmadstincr_2(self) -> &'a mut crate::W<REG> {
self.variant(Dmadstincr::Dmadstincr2)
}
#[doc = "DMA destination increment 3: destination address incremented"]
#[inline(always)]
pub fn dmadstincr_3(self) -> &'a mut crate::W<REG> {
self.variant(Dmadstincr::Dmadstincr3)
}
}
#[doc = "DMA transfer mode bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dmadt {
#[doc = "0: DMA transfer mode 0: Single transfer"]
Dmadt0 = 0,
#[doc = "1: DMA transfer mode 1: Block transfer"]
Dmadt1 = 1,
#[doc = "2: DMA transfer mode 2: Burst-Block transfer"]
Dmadt2 = 2,
#[doc = "3: DMA transfer mode 3: Burst-Block transfer"]
Dmadt3 = 3,
#[doc = "4: DMA transfer mode 4: Repeated Single transfer"]
Dmadt4 = 4,
#[doc = "5: DMA transfer mode 5: Repeated Block transfer"]
Dmadt5 = 5,
#[doc = "6: DMA transfer mode 6: Repeated Burst-Block transfer"]
Dmadt6 = 6,
#[doc = "7: DMA transfer mode 7: Repeated Burst-Block transfer"]
Dmadt7 = 7,
}
impl From<Dmadt> for u8 {
#[inline(always)]
fn from(variant: Dmadt) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dmadt {
type Ux = u8;
}
impl crate::IsEnum for Dmadt {}
#[doc = "Field `DMADT` reader - DMA transfer mode bit 0"]
pub type DmadtR = crate::FieldReader<Dmadt>;
impl DmadtR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dmadt {
match self.bits {
0 => Dmadt::Dmadt0,
1 => Dmadt::Dmadt1,
2 => Dmadt::Dmadt2,
3 => Dmadt::Dmadt3,
4 => Dmadt::Dmadt4,
5 => Dmadt::Dmadt5,
6 => Dmadt::Dmadt6,
7 => Dmadt::Dmadt7,
_ => unreachable!(),
}
}
#[doc = "DMA transfer mode 0: Single transfer"]
#[inline(always)]
pub fn is_dmadt_0(&self) -> bool {
*self == Dmadt::Dmadt0
}
#[doc = "DMA transfer mode 1: Block transfer"]
#[inline(always)]
pub fn is_dmadt_1(&self) -> bool {
*self == Dmadt::Dmadt1
}
#[doc = "DMA transfer mode 2: Burst-Block transfer"]
#[inline(always)]
pub fn is_dmadt_2(&self) -> bool {
*self == Dmadt::Dmadt2
}
#[doc = "DMA transfer mode 3: Burst-Block transfer"]
#[inline(always)]
pub fn is_dmadt_3(&self) -> bool {
*self == Dmadt::Dmadt3
}
#[doc = "DMA transfer mode 4: Repeated Single transfer"]
#[inline(always)]
pub fn is_dmadt_4(&self) -> bool {
*self == Dmadt::Dmadt4
}
#[doc = "DMA transfer mode 5: Repeated Block transfer"]
#[inline(always)]
pub fn is_dmadt_5(&self) -> bool {
*self == Dmadt::Dmadt5
}
#[doc = "DMA transfer mode 6: Repeated Burst-Block transfer"]
#[inline(always)]
pub fn is_dmadt_6(&self) -> bool {
*self == Dmadt::Dmadt6
}
#[doc = "DMA transfer mode 7: Repeated Burst-Block transfer"]
#[inline(always)]
pub fn is_dmadt_7(&self) -> bool {
*self == Dmadt::Dmadt7
}
}
#[doc = "Field `DMADT` writer - DMA transfer mode bit 0"]
pub type DmadtW<'a, REG> = crate::FieldWriter<'a, REG, 3, Dmadt, crate::Safe>;
impl<'a, REG> DmadtW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "DMA transfer mode 0: Single transfer"]
#[inline(always)]
pub fn dmadt_0(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt0)
}
#[doc = "DMA transfer mode 1: Block transfer"]
#[inline(always)]
pub fn dmadt_1(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt1)
}
#[doc = "DMA transfer mode 2: Burst-Block transfer"]
#[inline(always)]
pub fn dmadt_2(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt2)
}
#[doc = "DMA transfer mode 3: Burst-Block transfer"]
#[inline(always)]
pub fn dmadt_3(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt3)
}
#[doc = "DMA transfer mode 4: Repeated Single transfer"]
#[inline(always)]
pub fn dmadt_4(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt4)
}
#[doc = "DMA transfer mode 5: Repeated Block transfer"]
#[inline(always)]
pub fn dmadt_5(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt5)
}
#[doc = "DMA transfer mode 6: Repeated Burst-Block transfer"]
#[inline(always)]
pub fn dmadt_6(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt6)
}
#[doc = "DMA transfer mode 7: Repeated Burst-Block transfer"]
#[inline(always)]
pub fn dmadt_7(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt7)
}
}
impl R {
#[doc = "Bit 0 - Initiate DMA transfer with DMATSEL"]
#[inline(always)]
pub fn dmareq(&self) -> DmareqR {
DmareqR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - DMA transfer aborted by NMI"]
#[inline(always)]
pub fn dmaabort(&self) -> DmaabortR {
DmaabortR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - DMA interrupt enable"]
#[inline(always)]
pub fn dmaie(&self) -> DmaieR {
DmaieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - DMA interrupt flag"]
#[inline(always)]
pub fn dmaifg(&self) -> DmaifgR {
DmaifgR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - DMA enable"]
#[inline(always)]
pub fn dmaen(&self) -> DmaenR {
DmaenR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - DMA level sensitive trigger select"]
#[inline(always)]
pub fn dmalevel(&self) -> DmalevelR {
DmalevelR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - DMA source byte"]
#[inline(always)]
pub fn dmasrcbyte(&self) -> DmasrcbyteR {
DmasrcbyteR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - DMA destination byte"]
#[inline(always)]
pub fn dmadstbyte(&self) -> DmadstbyteR {
DmadstbyteR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - DMA source increment bit 0"]
#[inline(always)]
pub fn dmasrcincr(&self) -> DmasrcincrR {
DmasrcincrR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - DMA destination increment bit 0"]
#[inline(always)]
pub fn dmadstincr(&self) -> DmadstincrR {
DmadstincrR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:14 - DMA transfer mode bit 0"]
#[inline(always)]
pub fn dmadt(&self) -> DmadtR {
DmadtR::new(((self.bits >> 12) & 7) as u8)
}
}
impl W {
#[doc = "Bit 0 - Initiate DMA transfer with DMATSEL"]
#[inline(always)]
pub fn dmareq(&mut self) -> DmareqW<'_, Dma1ctlSpec> {
DmareqW::new(self, 0)
}
#[doc = "Bit 1 - DMA transfer aborted by NMI"]
#[inline(always)]
pub fn dmaabort(&mut self) -> DmaabortW<'_, Dma1ctlSpec> {
DmaabortW::new(self, 1)
}
#[doc = "Bit 2 - DMA interrupt enable"]
#[inline(always)]
pub fn dmaie(&mut self) -> DmaieW<'_, Dma1ctlSpec> {
DmaieW::new(self, 2)
}
#[doc = "Bit 3 - DMA interrupt flag"]
#[inline(always)]
pub fn dmaifg(&mut self) -> DmaifgW<'_, Dma1ctlSpec> {
DmaifgW::new(self, 3)
}
#[doc = "Bit 4 - DMA enable"]
#[inline(always)]
pub fn dmaen(&mut self) -> DmaenW<'_, Dma1ctlSpec> {
DmaenW::new(self, 4)
}
#[doc = "Bit 5 - DMA level sensitive trigger select"]
#[inline(always)]
pub fn dmalevel(&mut self) -> DmalevelW<'_, Dma1ctlSpec> {
DmalevelW::new(self, 5)
}
#[doc = "Bit 6 - DMA source byte"]
#[inline(always)]
pub fn dmasrcbyte(&mut self) -> DmasrcbyteW<'_, Dma1ctlSpec> {
DmasrcbyteW::new(self, 6)
}
#[doc = "Bit 7 - DMA destination byte"]
#[inline(always)]
pub fn dmadstbyte(&mut self) -> DmadstbyteW<'_, Dma1ctlSpec> {
DmadstbyteW::new(self, 7)
}
#[doc = "Bits 8:9 - DMA source increment bit 0"]
#[inline(always)]
pub fn dmasrcincr(&mut self) -> DmasrcincrW<'_, Dma1ctlSpec> {
DmasrcincrW::new(self, 8)
}
#[doc = "Bits 10:11 - DMA destination increment bit 0"]
#[inline(always)]
pub fn dmadstincr(&mut self) -> DmadstincrW<'_, Dma1ctlSpec> {
DmadstincrW::new(self, 10)
}
#[doc = "Bits 12:14 - DMA transfer mode bit 0"]
#[inline(always)]
pub fn dmadt(&mut self) -> DmadtW<'_, Dma1ctlSpec> {
DmadtW::new(self, 12)
}
}
#[doc = "DMA Channel 1 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dma1ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma1ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dma1ctlSpec;
impl crate::RegisterSpec for Dma1ctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`dma1ctl::R`](R) reader structure"]
impl crate::Readable for Dma1ctlSpec {}
#[doc = "`write(|w| ..)` method takes [`dma1ctl::W`](W) writer structure"]
impl crate::Writable for Dma1ctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMA1CTL to value 0"]
impl crate::Resettable for Dma1ctlSpec {}
}
#[doc = "DMA1SZ (rw) register accessor: DMA Channel 1 Transfer Size\n\nYou can [`read`](crate::Reg::read) this register and get [`dma1sz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma1sz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma1sz`] module"]
#[doc(alias = "DMA1SZ")]
pub type Dma1sz = crate::Reg<dma1sz::Dma1szSpec>;
#[doc = "DMA Channel 1 Transfer Size"]
pub mod dma1sz {
#[doc = "Register `DMA1SZ` reader"]
pub type R = crate::R<Dma1szSpec>;
#[doc = "Register `DMA1SZ` writer"]
pub type W = crate::W<Dma1szSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "DMA Channel 1 Transfer Size\n\nYou can [`read`](crate::Reg::read) this register and get [`dma1sz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma1sz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dma1szSpec;
impl crate::RegisterSpec for Dma1szSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`dma1sz::R`](R) reader structure"]
impl crate::Readable for Dma1szSpec {}
#[doc = "`write(|w| ..)` method takes [`dma1sz::W`](W) writer structure"]
impl crate::Writable for Dma1szSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMA1SZ to value 0"]
impl crate::Resettable for Dma1szSpec {}
}
#[doc = "DMA2CTL (rw) register accessor: DMA Channel 2 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dma2ctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma2ctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2ctl`] module"]
#[doc(alias = "DMA2CTL")]
pub type Dma2ctl = crate::Reg<dma2ctl::Dma2ctlSpec>;
#[doc = "DMA Channel 2 Control"]
pub mod dma2ctl {
#[doc = "Register `DMA2CTL` reader"]
pub type R = crate::R<Dma2ctlSpec>;
#[doc = "Register `DMA2CTL` writer"]
pub type W = crate::W<Dma2ctlSpec>;
#[doc = "Field `DMAREQ` reader - Initiate DMA transfer with DMATSEL"]
pub type DmareqR = crate::BitReader;
#[doc = "Field `DMAREQ` writer - Initiate DMA transfer with DMATSEL"]
pub type DmareqW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAABORT` reader - DMA transfer aborted by NMI"]
pub type DmaabortR = crate::BitReader;
#[doc = "Field `DMAABORT` writer - DMA transfer aborted by NMI"]
pub type DmaabortW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAIE` reader - DMA interrupt enable"]
pub type DmaieR = crate::BitReader;
#[doc = "Field `DMAIE` writer - DMA interrupt enable"]
pub type DmaieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAIFG` reader - DMA interrupt flag"]
pub type DmaifgR = crate::BitReader;
#[doc = "Field `DMAIFG` writer - DMA interrupt flag"]
pub type DmaifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAEN` reader - DMA enable"]
pub type DmaenR = crate::BitReader;
#[doc = "Field `DMAEN` writer - DMA enable"]
pub type DmaenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMALEVEL` reader - DMA level sensitive trigger select"]
pub type DmalevelR = crate::BitReader;
#[doc = "Field `DMALEVEL` writer - DMA level sensitive trigger select"]
pub type DmalevelW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMASRCBYTE` reader - DMA source byte"]
pub type DmasrcbyteR = crate::BitReader;
#[doc = "Field `DMASRCBYTE` writer - DMA source byte"]
pub type DmasrcbyteW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMADSTBYTE` reader - DMA destination byte"]
pub type DmadstbyteR = crate::BitReader;
#[doc = "Field `DMADSTBYTE` writer - DMA destination byte"]
pub type DmadstbyteW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "DMA source increment bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dmasrcincr {
#[doc = "0: DMA source increment 0: source address unchanged"]
Dmasrcincr0 = 0,
#[doc = "1: DMA source increment 1: source address unchanged"]
Dmasrcincr1 = 1,
#[doc = "2: DMA source increment 2: source address decremented"]
Dmasrcincr2 = 2,
#[doc = "3: DMA source increment 3: source address incremented"]
Dmasrcincr3 = 3,
}
impl From<Dmasrcincr> for u8 {
#[inline(always)]
fn from(variant: Dmasrcincr) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dmasrcincr {
type Ux = u8;
}
impl crate::IsEnum for Dmasrcincr {}
#[doc = "Field `DMASRCINCR` reader - DMA source increment bit 0"]
pub type DmasrcincrR = crate::FieldReader<Dmasrcincr>;
impl DmasrcincrR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dmasrcincr {
match self.bits {
0 => Dmasrcincr::Dmasrcincr0,
1 => Dmasrcincr::Dmasrcincr1,
2 => Dmasrcincr::Dmasrcincr2,
3 => Dmasrcincr::Dmasrcincr3,
_ => unreachable!(),
}
}
#[doc = "DMA source increment 0: source address unchanged"]
#[inline(always)]
pub fn is_dmasrcincr_0(&self) -> bool {
*self == Dmasrcincr::Dmasrcincr0
}
#[doc = "DMA source increment 1: source address unchanged"]
#[inline(always)]
pub fn is_dmasrcincr_1(&self) -> bool {
*self == Dmasrcincr::Dmasrcincr1
}
#[doc = "DMA source increment 2: source address decremented"]
#[inline(always)]
pub fn is_dmasrcincr_2(&self) -> bool {
*self == Dmasrcincr::Dmasrcincr2
}
#[doc = "DMA source increment 3: source address incremented"]
#[inline(always)]
pub fn is_dmasrcincr_3(&self) -> bool {
*self == Dmasrcincr::Dmasrcincr3
}
}
#[doc = "Field `DMASRCINCR` writer - DMA source increment bit 0"]
pub type DmasrcincrW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmasrcincr, crate::Safe>;
impl<'a, REG> DmasrcincrW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "DMA source increment 0: source address unchanged"]
#[inline(always)]
pub fn dmasrcincr_0(self) -> &'a mut crate::W<REG> {
self.variant(Dmasrcincr::Dmasrcincr0)
}
#[doc = "DMA source increment 1: source address unchanged"]
#[inline(always)]
pub fn dmasrcincr_1(self) -> &'a mut crate::W<REG> {
self.variant(Dmasrcincr::Dmasrcincr1)
}
#[doc = "DMA source increment 2: source address decremented"]
#[inline(always)]
pub fn dmasrcincr_2(self) -> &'a mut crate::W<REG> {
self.variant(Dmasrcincr::Dmasrcincr2)
}
#[doc = "DMA source increment 3: source address incremented"]
#[inline(always)]
pub fn dmasrcincr_3(self) -> &'a mut crate::W<REG> {
self.variant(Dmasrcincr::Dmasrcincr3)
}
}
#[doc = "DMA destination increment bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dmadstincr {
#[doc = "0: DMA destination increment 0: destination address unchanged"]
Dmadstincr0 = 0,
#[doc = "1: DMA destination increment 1: destination address unchanged"]
Dmadstincr1 = 1,
#[doc = "2: DMA destination increment 2: destination address decremented"]
Dmadstincr2 = 2,
#[doc = "3: DMA destination increment 3: destination address incremented"]
Dmadstincr3 = 3,
}
impl From<Dmadstincr> for u8 {
#[inline(always)]
fn from(variant: Dmadstincr) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dmadstincr {
type Ux = u8;
}
impl crate::IsEnum for Dmadstincr {}
#[doc = "Field `DMADSTINCR` reader - DMA destination increment bit 0"]
pub type DmadstincrR = crate::FieldReader<Dmadstincr>;
impl DmadstincrR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dmadstincr {
match self.bits {
0 => Dmadstincr::Dmadstincr0,
1 => Dmadstincr::Dmadstincr1,
2 => Dmadstincr::Dmadstincr2,
3 => Dmadstincr::Dmadstincr3,
_ => unreachable!(),
}
}
#[doc = "DMA destination increment 0: destination address unchanged"]
#[inline(always)]
pub fn is_dmadstincr_0(&self) -> bool {
*self == Dmadstincr::Dmadstincr0
}
#[doc = "DMA destination increment 1: destination address unchanged"]
#[inline(always)]
pub fn is_dmadstincr_1(&self) -> bool {
*self == Dmadstincr::Dmadstincr1
}
#[doc = "DMA destination increment 2: destination address decremented"]
#[inline(always)]
pub fn is_dmadstincr_2(&self) -> bool {
*self == Dmadstincr::Dmadstincr2
}
#[doc = "DMA destination increment 3: destination address incremented"]
#[inline(always)]
pub fn is_dmadstincr_3(&self) -> bool {
*self == Dmadstincr::Dmadstincr3
}
}
#[doc = "Field `DMADSTINCR` writer - DMA destination increment bit 0"]
pub type DmadstincrW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmadstincr, crate::Safe>;
impl<'a, REG> DmadstincrW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "DMA destination increment 0: destination address unchanged"]
#[inline(always)]
pub fn dmadstincr_0(self) -> &'a mut crate::W<REG> {
self.variant(Dmadstincr::Dmadstincr0)
}
#[doc = "DMA destination increment 1: destination address unchanged"]
#[inline(always)]
pub fn dmadstincr_1(self) -> &'a mut crate::W<REG> {
self.variant(Dmadstincr::Dmadstincr1)
}
#[doc = "DMA destination increment 2: destination address decremented"]
#[inline(always)]
pub fn dmadstincr_2(self) -> &'a mut crate::W<REG> {
self.variant(Dmadstincr::Dmadstincr2)
}
#[doc = "DMA destination increment 3: destination address incremented"]
#[inline(always)]
pub fn dmadstincr_3(self) -> &'a mut crate::W<REG> {
self.variant(Dmadstincr::Dmadstincr3)
}
}
#[doc = "DMA transfer mode bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dmadt {
#[doc = "0: DMA transfer mode 0: Single transfer"]
Dmadt0 = 0,
#[doc = "1: DMA transfer mode 1: Block transfer"]
Dmadt1 = 1,
#[doc = "2: DMA transfer mode 2: Burst-Block transfer"]
Dmadt2 = 2,
#[doc = "3: DMA transfer mode 3: Burst-Block transfer"]
Dmadt3 = 3,
#[doc = "4: DMA transfer mode 4: Repeated Single transfer"]
Dmadt4 = 4,
#[doc = "5: DMA transfer mode 5: Repeated Block transfer"]
Dmadt5 = 5,
#[doc = "6: DMA transfer mode 6: Repeated Burst-Block transfer"]
Dmadt6 = 6,
#[doc = "7: DMA transfer mode 7: Repeated Burst-Block transfer"]
Dmadt7 = 7,
}
impl From<Dmadt> for u8 {
#[inline(always)]
fn from(variant: Dmadt) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dmadt {
type Ux = u8;
}
impl crate::IsEnum for Dmadt {}
#[doc = "Field `DMADT` reader - DMA transfer mode bit 0"]
pub type DmadtR = crate::FieldReader<Dmadt>;
impl DmadtR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dmadt {
match self.bits {
0 => Dmadt::Dmadt0,
1 => Dmadt::Dmadt1,
2 => Dmadt::Dmadt2,
3 => Dmadt::Dmadt3,
4 => Dmadt::Dmadt4,
5 => Dmadt::Dmadt5,
6 => Dmadt::Dmadt6,
7 => Dmadt::Dmadt7,
_ => unreachable!(),
}
}
#[doc = "DMA transfer mode 0: Single transfer"]
#[inline(always)]
pub fn is_dmadt_0(&self) -> bool {
*self == Dmadt::Dmadt0
}
#[doc = "DMA transfer mode 1: Block transfer"]
#[inline(always)]
pub fn is_dmadt_1(&self) -> bool {
*self == Dmadt::Dmadt1
}
#[doc = "DMA transfer mode 2: Burst-Block transfer"]
#[inline(always)]
pub fn is_dmadt_2(&self) -> bool {
*self == Dmadt::Dmadt2
}
#[doc = "DMA transfer mode 3: Burst-Block transfer"]
#[inline(always)]
pub fn is_dmadt_3(&self) -> bool {
*self == Dmadt::Dmadt3
}
#[doc = "DMA transfer mode 4: Repeated Single transfer"]
#[inline(always)]
pub fn is_dmadt_4(&self) -> bool {
*self == Dmadt::Dmadt4
}
#[doc = "DMA transfer mode 5: Repeated Block transfer"]
#[inline(always)]
pub fn is_dmadt_5(&self) -> bool {
*self == Dmadt::Dmadt5
}
#[doc = "DMA transfer mode 6: Repeated Burst-Block transfer"]
#[inline(always)]
pub fn is_dmadt_6(&self) -> bool {
*self == Dmadt::Dmadt6
}
#[doc = "DMA transfer mode 7: Repeated Burst-Block transfer"]
#[inline(always)]
pub fn is_dmadt_7(&self) -> bool {
*self == Dmadt::Dmadt7
}
}
#[doc = "Field `DMADT` writer - DMA transfer mode bit 0"]
pub type DmadtW<'a, REG> = crate::FieldWriter<'a, REG, 3, Dmadt, crate::Safe>;
impl<'a, REG> DmadtW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "DMA transfer mode 0: Single transfer"]
#[inline(always)]
pub fn dmadt_0(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt0)
}
#[doc = "DMA transfer mode 1: Block transfer"]
#[inline(always)]
pub fn dmadt_1(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt1)
}
#[doc = "DMA transfer mode 2: Burst-Block transfer"]
#[inline(always)]
pub fn dmadt_2(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt2)
}
#[doc = "DMA transfer mode 3: Burst-Block transfer"]
#[inline(always)]
pub fn dmadt_3(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt3)
}
#[doc = "DMA transfer mode 4: Repeated Single transfer"]
#[inline(always)]
pub fn dmadt_4(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt4)
}
#[doc = "DMA transfer mode 5: Repeated Block transfer"]
#[inline(always)]
pub fn dmadt_5(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt5)
}
#[doc = "DMA transfer mode 6: Repeated Burst-Block transfer"]
#[inline(always)]
pub fn dmadt_6(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt6)
}
#[doc = "DMA transfer mode 7: Repeated Burst-Block transfer"]
#[inline(always)]
pub fn dmadt_7(self) -> &'a mut crate::W<REG> {
self.variant(Dmadt::Dmadt7)
}
}
impl R {
#[doc = "Bit 0 - Initiate DMA transfer with DMATSEL"]
#[inline(always)]
pub fn dmareq(&self) -> DmareqR {
DmareqR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - DMA transfer aborted by NMI"]
#[inline(always)]
pub fn dmaabort(&self) -> DmaabortR {
DmaabortR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - DMA interrupt enable"]
#[inline(always)]
pub fn dmaie(&self) -> DmaieR {
DmaieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - DMA interrupt flag"]
#[inline(always)]
pub fn dmaifg(&self) -> DmaifgR {
DmaifgR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - DMA enable"]
#[inline(always)]
pub fn dmaen(&self) -> DmaenR {
DmaenR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - DMA level sensitive trigger select"]
#[inline(always)]
pub fn dmalevel(&self) -> DmalevelR {
DmalevelR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - DMA source byte"]
#[inline(always)]
pub fn dmasrcbyte(&self) -> DmasrcbyteR {
DmasrcbyteR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - DMA destination byte"]
#[inline(always)]
pub fn dmadstbyte(&self) -> DmadstbyteR {
DmadstbyteR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - DMA source increment bit 0"]
#[inline(always)]
pub fn dmasrcincr(&self) -> DmasrcincrR {
DmasrcincrR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - DMA destination increment bit 0"]
#[inline(always)]
pub fn dmadstincr(&self) -> DmadstincrR {
DmadstincrR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:14 - DMA transfer mode bit 0"]
#[inline(always)]
pub fn dmadt(&self) -> DmadtR {
DmadtR::new(((self.bits >> 12) & 7) as u8)
}
}
impl W {
#[doc = "Bit 0 - Initiate DMA transfer with DMATSEL"]
#[inline(always)]
pub fn dmareq(&mut self) -> DmareqW<'_, Dma2ctlSpec> {
DmareqW::new(self, 0)
}
#[doc = "Bit 1 - DMA transfer aborted by NMI"]
#[inline(always)]
pub fn dmaabort(&mut self) -> DmaabortW<'_, Dma2ctlSpec> {
DmaabortW::new(self, 1)
}
#[doc = "Bit 2 - DMA interrupt enable"]
#[inline(always)]
pub fn dmaie(&mut self) -> DmaieW<'_, Dma2ctlSpec> {
DmaieW::new(self, 2)
}
#[doc = "Bit 3 - DMA interrupt flag"]
#[inline(always)]
pub fn dmaifg(&mut self) -> DmaifgW<'_, Dma2ctlSpec> {
DmaifgW::new(self, 3)
}
#[doc = "Bit 4 - DMA enable"]
#[inline(always)]
pub fn dmaen(&mut self) -> DmaenW<'_, Dma2ctlSpec> {
DmaenW::new(self, 4)
}
#[doc = "Bit 5 - DMA level sensitive trigger select"]
#[inline(always)]
pub fn dmalevel(&mut self) -> DmalevelW<'_, Dma2ctlSpec> {
DmalevelW::new(self, 5)
}
#[doc = "Bit 6 - DMA source byte"]
#[inline(always)]
pub fn dmasrcbyte(&mut self) -> DmasrcbyteW<'_, Dma2ctlSpec> {
DmasrcbyteW::new(self, 6)
}
#[doc = "Bit 7 - DMA destination byte"]
#[inline(always)]
pub fn dmadstbyte(&mut self) -> DmadstbyteW<'_, Dma2ctlSpec> {
DmadstbyteW::new(self, 7)
}
#[doc = "Bits 8:9 - DMA source increment bit 0"]
#[inline(always)]
pub fn dmasrcincr(&mut self) -> DmasrcincrW<'_, Dma2ctlSpec> {
DmasrcincrW::new(self, 8)
}
#[doc = "Bits 10:11 - DMA destination increment bit 0"]
#[inline(always)]
pub fn dmadstincr(&mut self) -> DmadstincrW<'_, Dma2ctlSpec> {
DmadstincrW::new(self, 10)
}
#[doc = "Bits 12:14 - DMA transfer mode bit 0"]
#[inline(always)]
pub fn dmadt(&mut self) -> DmadtW<'_, Dma2ctlSpec> {
DmadtW::new(self, 12)
}
}
#[doc = "DMA Channel 2 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`dma2ctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma2ctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dma2ctlSpec;
impl crate::RegisterSpec for Dma2ctlSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`dma2ctl::R`](R) reader structure"]
impl crate::Readable for Dma2ctlSpec {}
#[doc = "`write(|w| ..)` method takes [`dma2ctl::W`](W) writer structure"]
impl crate::Writable for Dma2ctlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMA2CTL to value 0"]
impl crate::Resettable for Dma2ctlSpec {}
}
#[doc = "DMA2SZ (rw) register accessor: DMA Channel 2 Transfer Size\n\nYou can [`read`](crate::Reg::read) this register and get [`dma2sz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma2sz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2sz`] module"]
#[doc(alias = "DMA2SZ")]
pub type Dma2sz = crate::Reg<dma2sz::Dma2szSpec>;
#[doc = "DMA Channel 2 Transfer Size"]
pub mod dma2sz {
#[doc = "Register `DMA2SZ` reader"]
pub type R = crate::R<Dma2szSpec>;
#[doc = "Register `DMA2SZ` writer"]
pub type W = crate::W<Dma2szSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "DMA Channel 2 Transfer Size\n\nYou can [`read`](crate::Reg::read) this register and get [`dma2sz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma2sz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dma2szSpec;
impl crate::RegisterSpec for Dma2szSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`dma2sz::R`](R) reader structure"]
impl crate::Readable for Dma2szSpec {}
#[doc = "`write(|w| ..)` method takes [`dma2sz::W`](W) writer structure"]
impl crate::Writable for Dma2szSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMA2SZ to value 0"]
impl crate::Resettable for Dma2szSpec {}
}
#[doc = "DMA0SA (rw) register accessor: DMA Channel 0 Source Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma0sa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma0sa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma0sa`] module"]
#[doc(alias = "DMA0SA")]
pub type Dma0sa = crate::Reg<dma0sa::Dma0saSpec>;
#[doc = "DMA Channel 0 Source Address"]
pub mod dma0sa {
#[doc = "Register `DMA0SA` reader"]
pub type R = crate::R<Dma0saSpec>;
#[doc = "Register `DMA0SA` writer"]
pub type W = crate::W<Dma0saSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "DMA Channel 0 Source Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma0sa::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma0sa::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dma0saSpec;
impl crate::RegisterSpec for Dma0saSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dma0sa::R`](R) reader structure"]
impl crate::Readable for Dma0saSpec {}
#[doc = "`write(|w| ..)` method takes [`dma0sa::W`](W) writer structure"]
impl crate::Writable for Dma0saSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMA0SA to value 0"]
impl crate::Resettable for Dma0saSpec {}
}
#[doc = "DMA0DA (rw) register accessor: DMA Channel 0 Destination Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma0da::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma0da::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma0da`] module"]
#[doc(alias = "DMA0DA")]
pub type Dma0da = crate::Reg<dma0da::Dma0daSpec>;
#[doc = "DMA Channel 0 Destination Address"]
pub mod dma0da {
#[doc = "Register `DMA0DA` reader"]
pub type R = crate::R<Dma0daSpec>;
#[doc = "Register `DMA0DA` writer"]
pub type W = crate::W<Dma0daSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "DMA Channel 0 Destination Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma0da::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma0da::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dma0daSpec;
impl crate::RegisterSpec for Dma0daSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dma0da::R`](R) reader structure"]
impl crate::Readable for Dma0daSpec {}
#[doc = "`write(|w| ..)` method takes [`dma0da::W`](W) writer structure"]
impl crate::Writable for Dma0daSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMA0DA to value 0"]
impl crate::Resettable for Dma0daSpec {}
}
#[doc = "DMA1SA (rw) register accessor: DMA Channel 1 Source Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma1sa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma1sa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma1sa`] module"]
#[doc(alias = "DMA1SA")]
pub type Dma1sa = crate::Reg<dma1sa::Dma1saSpec>;
#[doc = "DMA Channel 1 Source Address"]
pub mod dma1sa {
#[doc = "Register `DMA1SA` reader"]
pub type R = crate::R<Dma1saSpec>;
#[doc = "Register `DMA1SA` writer"]
pub type W = crate::W<Dma1saSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "DMA Channel 1 Source Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma1sa::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma1sa::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dma1saSpec;
impl crate::RegisterSpec for Dma1saSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dma1sa::R`](R) reader structure"]
impl crate::Readable for Dma1saSpec {}
#[doc = "`write(|w| ..)` method takes [`dma1sa::W`](W) writer structure"]
impl crate::Writable for Dma1saSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMA1SA to value 0"]
impl crate::Resettable for Dma1saSpec {}
}
#[doc = "DMA1DA (rw) register accessor: DMA Channel 1 Destination Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma1da::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma1da::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma1da`] module"]
#[doc(alias = "DMA1DA")]
pub type Dma1da = crate::Reg<dma1da::Dma1daSpec>;
#[doc = "DMA Channel 1 Destination Address"]
pub mod dma1da {
#[doc = "Register `DMA1DA` reader"]
pub type R = crate::R<Dma1daSpec>;
#[doc = "Register `DMA1DA` writer"]
pub type W = crate::W<Dma1daSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "DMA Channel 1 Destination Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma1da::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma1da::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dma1daSpec;
impl crate::RegisterSpec for Dma1daSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dma1da::R`](R) reader structure"]
impl crate::Readable for Dma1daSpec {}
#[doc = "`write(|w| ..)` method takes [`dma1da::W`](W) writer structure"]
impl crate::Writable for Dma1daSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMA1DA to value 0"]
impl crate::Resettable for Dma1daSpec {}
}
#[doc = "DMA2SA (rw) register accessor: DMA Channel 2 Source Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma2sa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma2sa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2sa`] module"]
#[doc(alias = "DMA2SA")]
pub type Dma2sa = crate::Reg<dma2sa::Dma2saSpec>;
#[doc = "DMA Channel 2 Source Address"]
pub mod dma2sa {
#[doc = "Register `DMA2SA` reader"]
pub type R = crate::R<Dma2saSpec>;
#[doc = "Register `DMA2SA` writer"]
pub type W = crate::W<Dma2saSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "DMA Channel 2 Source Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma2sa::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma2sa::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dma2saSpec;
impl crate::RegisterSpec for Dma2saSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dma2sa::R`](R) reader structure"]
impl crate::Readable for Dma2saSpec {}
#[doc = "`write(|w| ..)` method takes [`dma2sa::W`](W) writer structure"]
impl crate::Writable for Dma2saSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMA2SA to value 0"]
impl crate::Resettable for Dma2saSpec {}
}
#[doc = "DMA2DA (rw) register accessor: DMA Channel 2 Destination Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma2da::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma2da::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma2da`] module"]
#[doc(alias = "DMA2DA")]
pub type Dma2da = crate::Reg<dma2da::Dma2daSpec>;
#[doc = "DMA Channel 2 Destination Address"]
pub mod dma2da {
#[doc = "Register `DMA2DA` reader"]
pub type R = crate::R<Dma2daSpec>;
#[doc = "Register `DMA2DA` writer"]
pub type W = crate::W<Dma2daSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "DMA Channel 2 Destination Address\n\nYou can [`read`](crate::Reg::read) this register and get [`dma2da::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma2da::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dma2daSpec;
impl crate::RegisterSpec for Dma2daSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dma2da::R`](R) reader structure"]
impl crate::Readable for Dma2daSpec {}
#[doc = "`write(|w| ..)` method takes [`dma2da::W`](W) writer structure"]
impl crate::Writable for Dma2daSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMA2DA to value 0"]
impl crate::Resettable for Dma2daSpec {}
}
}
#[doc = "MPU"]
pub type Mpu = crate::Periph<mpu::RegisterBlock, 0x05a0>;
impl core::fmt::Debug for Mpu {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Mpu").finish()
}
}
#[doc = "MPU"]
pub mod mpu {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
mpuctl0: Mpuctl0,
mpuctl1: Mpuctl1,
mpusegb2: Mpusegb2,
mpusegb1: Mpusegb1,
mpusam: Mpusam,
mpuipc0: Mpuipc0,
mpuipsegb2: Mpuipsegb2,
mpuipsegb1: Mpuipsegb1,
}
impl RegisterBlock {
#[doc = "0x00 - MPU Control Register 0"]
#[inline(always)]
pub const fn mpuctl0(&self) -> &Mpuctl0 {
&self.mpuctl0
}
#[doc = "0x02 - MPU Control Register 1"]
#[inline(always)]
pub const fn mpuctl1(&self) -> &Mpuctl1 {
&self.mpuctl1
}
#[doc = "0x04 - MPU Segmentation Border 2 Register"]
#[inline(always)]
pub const fn mpusegb2(&self) -> &Mpusegb2 {
&self.mpusegb2
}
#[doc = "0x06 - MPU Segmentation Border 1 Register"]
#[inline(always)]
pub const fn mpusegb1(&self) -> &Mpusegb1 {
&self.mpusegb1
}
#[doc = "0x08 - MPU Access Management Register"]
#[inline(always)]
pub const fn mpusam(&self) -> &Mpusam {
&self.mpusam
}
#[doc = "0x0a - MPU IP Control 0 Register"]
#[inline(always)]
pub const fn mpuipc0(&self) -> &Mpuipc0 {
&self.mpuipc0
}
#[doc = "0x0c - MPU IP Segment Border 2 Register"]
#[inline(always)]
pub const fn mpuipsegb2(&self) -> &Mpuipsegb2 {
&self.mpuipsegb2
}
#[doc = "0x0e - MPU IP Segment Border 1 Register"]
#[inline(always)]
pub const fn mpuipsegb1(&self) -> &Mpuipsegb1 {
&self.mpuipsegb1
}
}
#[doc = "MPUCTL0 (rw) register accessor: MPU Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mpuctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpuctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mpuctl0`] module"]
#[doc(alias = "MPUCTL0")]
pub type Mpuctl0 = crate::Reg<mpuctl0::Mpuctl0Spec>;
#[doc = "MPU Control Register 0"]
pub mod mpuctl0 {
#[doc = "Register `MPUCTL0` reader"]
pub type R = crate::R<Mpuctl0Spec>;
#[doc = "Register `MPUCTL0` writer"]
pub type W = crate::W<Mpuctl0Spec>;
#[doc = "Field `MPUENA` reader - MPU Enable"]
pub type MpuenaR = crate::BitReader;
#[doc = "Field `MPUENA` writer - MPU Enable"]
pub type MpuenaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPULOCK` reader - MPU Lock"]
pub type MpulockR = crate::BitReader;
#[doc = "Field `MPULOCK` writer - MPU Lock"]
pub type MpulockW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGIE` reader - MPU Enable NMI on Segment violation"]
pub type MpusegieR = crate::BitReader;
#[doc = "Field `MPUSEGIE` writer - MPU Enable NMI on Segment violation"]
pub type MpusegieW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - MPU Enable"]
#[inline(always)]
pub fn mpuena(&self) -> MpuenaR {
MpuenaR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - MPU Lock"]
#[inline(always)]
pub fn mpulock(&self) -> MpulockR {
MpulockR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 4 - MPU Enable NMI on Segment violation"]
#[inline(always)]
pub fn mpusegie(&self) -> MpusegieR {
MpusegieR::new(((self.bits >> 4) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - MPU Enable"]
#[inline(always)]
pub fn mpuena(&mut self) -> MpuenaW<'_, Mpuctl0Spec> {
MpuenaW::new(self, 0)
}
#[doc = "Bit 1 - MPU Lock"]
#[inline(always)]
pub fn mpulock(&mut self) -> MpulockW<'_, Mpuctl0Spec> {
MpulockW::new(self, 1)
}
#[doc = "Bit 4 - MPU Enable NMI on Segment violation"]
#[inline(always)]
pub fn mpusegie(&mut self) -> MpusegieW<'_, Mpuctl0Spec> {
MpusegieW::new(self, 4)
}
}
#[doc = "MPU Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mpuctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpuctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mpuctl0Spec;
impl crate::RegisterSpec for Mpuctl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mpuctl0::R`](R) reader structure"]
impl crate::Readable for Mpuctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`mpuctl0::W`](W) writer structure"]
impl crate::Writable for Mpuctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MPUCTL0 to value 0"]
impl crate::Resettable for Mpuctl0Spec {}
}
#[doc = "MPUCTL1 (rw) register accessor: MPU Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mpuctl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpuctl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mpuctl1`] module"]
#[doc(alias = "MPUCTL1")]
pub type Mpuctl1 = crate::Reg<mpuctl1::Mpuctl1Spec>;
#[doc = "MPU Control Register 1"]
pub mod mpuctl1 {
#[doc = "Register `MPUCTL1` reader"]
pub type R = crate::R<Mpuctl1Spec>;
#[doc = "Register `MPUCTL1` writer"]
pub type W = crate::W<Mpuctl1Spec>;
#[doc = "Field `MPUSEG1IFG` reader - MPU Main Memory Segment 1 violation interupt flag"]
pub type Mpuseg1ifgR = crate::BitReader;
#[doc = "Field `MPUSEG1IFG` writer - MPU Main Memory Segment 1 violation interupt flag"]
pub type Mpuseg1ifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEG2IFG` reader - MPU Main Memory Segment 2 violation interupt flag"]
pub type Mpuseg2ifgR = crate::BitReader;
#[doc = "Field `MPUSEG2IFG` writer - MPU Main Memory Segment 2 violation interupt flag"]
pub type Mpuseg2ifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEG3IFG` reader - MPU Main Memory Segment 3 violation interupt flag"]
pub type Mpuseg3ifgR = crate::BitReader;
#[doc = "Field `MPUSEG3IFG` writer - MPU Main Memory Segment 3 violation interupt flag"]
pub type Mpuseg3ifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGIIFG` reader - MPU Info Memory Segment violation interupt flag"]
pub type MpusegiifgR = crate::BitReader;
#[doc = "Field `MPUSEGIIFG` writer - MPU Info Memory Segment violation interupt flag"]
pub type MpusegiifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGIPIFG` reader - MPU IP Memory Segment violation interupt flag"]
pub type MpusegipifgR = crate::BitReader;
#[doc = "Field `MPUSEGIPIFG` writer - MPU IP Memory Segment violation interupt flag"]
pub type MpusegipifgW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - MPU Main Memory Segment 1 violation interupt flag"]
#[inline(always)]
pub fn mpuseg1ifg(&self) -> Mpuseg1ifgR {
Mpuseg1ifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - MPU Main Memory Segment 2 violation interupt flag"]
#[inline(always)]
pub fn mpuseg2ifg(&self) -> Mpuseg2ifgR {
Mpuseg2ifgR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - MPU Main Memory Segment 3 violation interupt flag"]
#[inline(always)]
pub fn mpuseg3ifg(&self) -> Mpuseg3ifgR {
Mpuseg3ifgR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - MPU Info Memory Segment violation interupt flag"]
#[inline(always)]
pub fn mpusegiifg(&self) -> MpusegiifgR {
MpusegiifgR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - MPU IP Memory Segment violation interupt flag"]
#[inline(always)]
pub fn mpusegipifg(&self) -> MpusegipifgR {
MpusegipifgR::new(((self.bits >> 4) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - MPU Main Memory Segment 1 violation interupt flag"]
#[inline(always)]
pub fn mpuseg1ifg(&mut self) -> Mpuseg1ifgW<'_, Mpuctl1Spec> {
Mpuseg1ifgW::new(self, 0)
}
#[doc = "Bit 1 - MPU Main Memory Segment 2 violation interupt flag"]
#[inline(always)]
pub fn mpuseg2ifg(&mut self) -> Mpuseg2ifgW<'_, Mpuctl1Spec> {
Mpuseg2ifgW::new(self, 1)
}
#[doc = "Bit 2 - MPU Main Memory Segment 3 violation interupt flag"]
#[inline(always)]
pub fn mpuseg3ifg(&mut self) -> Mpuseg3ifgW<'_, Mpuctl1Spec> {
Mpuseg3ifgW::new(self, 2)
}
#[doc = "Bit 3 - MPU Info Memory Segment violation interupt flag"]
#[inline(always)]
pub fn mpusegiifg(&mut self) -> MpusegiifgW<'_, Mpuctl1Spec> {
MpusegiifgW::new(self, 3)
}
#[doc = "Bit 4 - MPU IP Memory Segment violation interupt flag"]
#[inline(always)]
pub fn mpusegipifg(&mut self) -> MpusegipifgW<'_, Mpuctl1Spec> {
MpusegipifgW::new(self, 4)
}
}
#[doc = "MPU Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mpuctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpuctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mpuctl1Spec;
impl crate::RegisterSpec for Mpuctl1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mpuctl1::R`](R) reader structure"]
impl crate::Readable for Mpuctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`mpuctl1::W`](W) writer structure"]
impl crate::Writable for Mpuctl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MPUCTL1 to value 0"]
impl crate::Resettable for Mpuctl1Spec {}
}
#[doc = "MPUSEGB2 (rw) register accessor: MPU Segmentation Border 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mpusegb2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpusegb2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mpusegb2`] module"]
#[doc(alias = "MPUSEGB2")]
pub type Mpusegb2 = crate::Reg<mpusegb2::Mpusegb2Spec>;
#[doc = "MPU Segmentation Border 2 Register"]
pub mod mpusegb2 {
#[doc = "Register `MPUSEGB2` reader"]
pub type R = crate::R<Mpusegb2Spec>;
#[doc = "Register `MPUSEGB2` writer"]
pub type W = crate::W<Mpusegb2Spec>;
#[doc = "Field `MPUSEGB20` reader - MPU Segment Border 2 Bit: 0"]
pub type Mpusegb20R = crate::BitReader;
#[doc = "Field `MPUSEGB20` writer - MPU Segment Border 2 Bit: 0"]
pub type Mpusegb20W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB21` reader - MPU Segment Border 2 Bit: 1"]
pub type Mpusegb21R = crate::BitReader;
#[doc = "Field `MPUSEGB21` writer - MPU Segment Border 2 Bit: 1"]
pub type Mpusegb21W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB22` reader - MPU Segment Border 2 Bit: 2"]
pub type Mpusegb22R = crate::BitReader;
#[doc = "Field `MPUSEGB22` writer - MPU Segment Border 2 Bit: 2"]
pub type Mpusegb22W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB23` reader - MPU Segment Border 2 Bit: 3"]
pub type Mpusegb23R = crate::BitReader;
#[doc = "Field `MPUSEGB23` writer - MPU Segment Border 2 Bit: 3"]
pub type Mpusegb23W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB24` reader - MPU Segment Border 2 Bit: 4"]
pub type Mpusegb24R = crate::BitReader;
#[doc = "Field `MPUSEGB24` writer - MPU Segment Border 2 Bit: 4"]
pub type Mpusegb24W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB25` reader - MPU Segment Border 2 Bit: 5"]
pub type Mpusegb25R = crate::BitReader;
#[doc = "Field `MPUSEGB25` writer - MPU Segment Border 2 Bit: 5"]
pub type Mpusegb25W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB26` reader - MPU Segment Border 2 Bit: 6"]
pub type Mpusegb26R = crate::BitReader;
#[doc = "Field `MPUSEGB26` writer - MPU Segment Border 2 Bit: 6"]
pub type Mpusegb26W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB27` reader - MPU Segment Border 2 Bit: 7"]
pub type Mpusegb27R = crate::BitReader;
#[doc = "Field `MPUSEGB27` writer - MPU Segment Border 2 Bit: 7"]
pub type Mpusegb27W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB28` reader - MPU Segment Border 2 Bit: 8"]
pub type Mpusegb28R = crate::BitReader;
#[doc = "Field `MPUSEGB28` writer - MPU Segment Border 2 Bit: 8"]
pub type Mpusegb28W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB29` reader - MPU Segment Border 2 Bit: 9"]
pub type Mpusegb29R = crate::BitReader;
#[doc = "Field `MPUSEGB29` writer - MPU Segment Border 2 Bit: 9"]
pub type Mpusegb29W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB210` reader - MPU Segment Border 2 Bit: 10"]
pub type Mpusegb210R = crate::BitReader;
#[doc = "Field `MPUSEGB210` writer - MPU Segment Border 2 Bit: 10"]
pub type Mpusegb210W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB211` reader - MPU Segment Border 2 Bit: 11"]
pub type Mpusegb211R = crate::BitReader;
#[doc = "Field `MPUSEGB211` writer - MPU Segment Border 2 Bit: 11"]
pub type Mpusegb211W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB212` reader - MPU Segment Border 2 Bit: 12"]
pub type Mpusegb212R = crate::BitReader;
#[doc = "Field `MPUSEGB212` writer - MPU Segment Border 2 Bit: 12"]
pub type Mpusegb212W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB213` reader - MPU Segment Border 2 Bit: 13"]
pub type Mpusegb213R = crate::BitReader;
#[doc = "Field `MPUSEGB213` writer - MPU Segment Border 2 Bit: 13"]
pub type Mpusegb213W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB214` reader - MPU Segment Border 2 Bit: 14"]
pub type Mpusegb214R = crate::BitReader;
#[doc = "Field `MPUSEGB214` writer - MPU Segment Border 2 Bit: 14"]
pub type Mpusegb214W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB215` reader - MPU Segment Border 2 Bit: 15"]
pub type Mpusegb215R = crate::BitReader;
#[doc = "Field `MPUSEGB215` writer - MPU Segment Border 2 Bit: 15"]
pub type Mpusegb215W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - MPU Segment Border 2 Bit: 0"]
#[inline(always)]
pub fn mpusegb20(&self) -> Mpusegb20R {
Mpusegb20R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - MPU Segment Border 2 Bit: 1"]
#[inline(always)]
pub fn mpusegb21(&self) -> Mpusegb21R {
Mpusegb21R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - MPU Segment Border 2 Bit: 2"]
#[inline(always)]
pub fn mpusegb22(&self) -> Mpusegb22R {
Mpusegb22R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - MPU Segment Border 2 Bit: 3"]
#[inline(always)]
pub fn mpusegb23(&self) -> Mpusegb23R {
Mpusegb23R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - MPU Segment Border 2 Bit: 4"]
#[inline(always)]
pub fn mpusegb24(&self) -> Mpusegb24R {
Mpusegb24R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - MPU Segment Border 2 Bit: 5"]
#[inline(always)]
pub fn mpusegb25(&self) -> Mpusegb25R {
Mpusegb25R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - MPU Segment Border 2 Bit: 6"]
#[inline(always)]
pub fn mpusegb26(&self) -> Mpusegb26R {
Mpusegb26R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - MPU Segment Border 2 Bit: 7"]
#[inline(always)]
pub fn mpusegb27(&self) -> Mpusegb27R {
Mpusegb27R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - MPU Segment Border 2 Bit: 8"]
#[inline(always)]
pub fn mpusegb28(&self) -> Mpusegb28R {
Mpusegb28R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - MPU Segment Border 2 Bit: 9"]
#[inline(always)]
pub fn mpusegb29(&self) -> Mpusegb29R {
Mpusegb29R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - MPU Segment Border 2 Bit: 10"]
#[inline(always)]
pub fn mpusegb210(&self) -> Mpusegb210R {
Mpusegb210R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - MPU Segment Border 2 Bit: 11"]
#[inline(always)]
pub fn mpusegb211(&self) -> Mpusegb211R {
Mpusegb211R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - MPU Segment Border 2 Bit: 12"]
#[inline(always)]
pub fn mpusegb212(&self) -> Mpusegb212R {
Mpusegb212R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - MPU Segment Border 2 Bit: 13"]
#[inline(always)]
pub fn mpusegb213(&self) -> Mpusegb213R {
Mpusegb213R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - MPU Segment Border 2 Bit: 14"]
#[inline(always)]
pub fn mpusegb214(&self) -> Mpusegb214R {
Mpusegb214R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - MPU Segment Border 2 Bit: 15"]
#[inline(always)]
pub fn mpusegb215(&self) -> Mpusegb215R {
Mpusegb215R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - MPU Segment Border 2 Bit: 0"]
#[inline(always)]
pub fn mpusegb20(&mut self) -> Mpusegb20W<'_, Mpusegb2Spec> {
Mpusegb20W::new(self, 0)
}
#[doc = "Bit 1 - MPU Segment Border 2 Bit: 1"]
#[inline(always)]
pub fn mpusegb21(&mut self) -> Mpusegb21W<'_, Mpusegb2Spec> {
Mpusegb21W::new(self, 1)
}
#[doc = "Bit 2 - MPU Segment Border 2 Bit: 2"]
#[inline(always)]
pub fn mpusegb22(&mut self) -> Mpusegb22W<'_, Mpusegb2Spec> {
Mpusegb22W::new(self, 2)
}
#[doc = "Bit 3 - MPU Segment Border 2 Bit: 3"]
#[inline(always)]
pub fn mpusegb23(&mut self) -> Mpusegb23W<'_, Mpusegb2Spec> {
Mpusegb23W::new(self, 3)
}
#[doc = "Bit 4 - MPU Segment Border 2 Bit: 4"]
#[inline(always)]
pub fn mpusegb24(&mut self) -> Mpusegb24W<'_, Mpusegb2Spec> {
Mpusegb24W::new(self, 4)
}
#[doc = "Bit 5 - MPU Segment Border 2 Bit: 5"]
#[inline(always)]
pub fn mpusegb25(&mut self) -> Mpusegb25W<'_, Mpusegb2Spec> {
Mpusegb25W::new(self, 5)
}
#[doc = "Bit 6 - MPU Segment Border 2 Bit: 6"]
#[inline(always)]
pub fn mpusegb26(&mut self) -> Mpusegb26W<'_, Mpusegb2Spec> {
Mpusegb26W::new(self, 6)
}
#[doc = "Bit 7 - MPU Segment Border 2 Bit: 7"]
#[inline(always)]
pub fn mpusegb27(&mut self) -> Mpusegb27W<'_, Mpusegb2Spec> {
Mpusegb27W::new(self, 7)
}
#[doc = "Bit 8 - MPU Segment Border 2 Bit: 8"]
#[inline(always)]
pub fn mpusegb28(&mut self) -> Mpusegb28W<'_, Mpusegb2Spec> {
Mpusegb28W::new(self, 8)
}
#[doc = "Bit 9 - MPU Segment Border 2 Bit: 9"]
#[inline(always)]
pub fn mpusegb29(&mut self) -> Mpusegb29W<'_, Mpusegb2Spec> {
Mpusegb29W::new(self, 9)
}
#[doc = "Bit 10 - MPU Segment Border 2 Bit: 10"]
#[inline(always)]
pub fn mpusegb210(&mut self) -> Mpusegb210W<'_, Mpusegb2Spec> {
Mpusegb210W::new(self, 10)
}
#[doc = "Bit 11 - MPU Segment Border 2 Bit: 11"]
#[inline(always)]
pub fn mpusegb211(&mut self) -> Mpusegb211W<'_, Mpusegb2Spec> {
Mpusegb211W::new(self, 11)
}
#[doc = "Bit 12 - MPU Segment Border 2 Bit: 12"]
#[inline(always)]
pub fn mpusegb212(&mut self) -> Mpusegb212W<'_, Mpusegb2Spec> {
Mpusegb212W::new(self, 12)
}
#[doc = "Bit 13 - MPU Segment Border 2 Bit: 13"]
#[inline(always)]
pub fn mpusegb213(&mut self) -> Mpusegb213W<'_, Mpusegb2Spec> {
Mpusegb213W::new(self, 13)
}
#[doc = "Bit 14 - MPU Segment Border 2 Bit: 14"]
#[inline(always)]
pub fn mpusegb214(&mut self) -> Mpusegb214W<'_, Mpusegb2Spec> {
Mpusegb214W::new(self, 14)
}
#[doc = "Bit 15 - MPU Segment Border 2 Bit: 15"]
#[inline(always)]
pub fn mpusegb215(&mut self) -> Mpusegb215W<'_, Mpusegb2Spec> {
Mpusegb215W::new(self, 15)
}
}
#[doc = "MPU Segmentation Border 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mpusegb2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpusegb2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mpusegb2Spec;
impl crate::RegisterSpec for Mpusegb2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mpusegb2::R`](R) reader structure"]
impl crate::Readable for Mpusegb2Spec {}
#[doc = "`write(|w| ..)` method takes [`mpusegb2::W`](W) writer structure"]
impl crate::Writable for Mpusegb2Spec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets MPUSEGB2 to value 0"]
impl crate::Resettable for Mpusegb2Spec {}
}
#[doc = "MPUSEGB1 (rw) register accessor: MPU Segmentation Border 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mpusegb1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpusegb1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mpusegb1`] module"]
#[doc(alias = "MPUSEGB1")]
pub type Mpusegb1 = crate::Reg<mpusegb1::Mpusegb1Spec>;
#[doc = "MPU Segmentation Border 1 Register"]
pub mod mpusegb1 {
#[doc = "Register `MPUSEGB1` reader"]
pub type R = crate::R<Mpusegb1Spec>;
#[doc = "Register `MPUSEGB1` writer"]
pub type W = crate::W<Mpusegb1Spec>;
#[doc = "Field `MPUSEGB10` reader - MPU Segment Border 1 Bit: 0"]
pub type Mpusegb10R = crate::BitReader;
#[doc = "Field `MPUSEGB10` writer - MPU Segment Border 1 Bit: 0"]
pub type Mpusegb10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB11` reader - MPU Segment Border 1 Bit: 1"]
pub type Mpusegb11R = crate::BitReader;
#[doc = "Field `MPUSEGB11` writer - MPU Segment Border 1 Bit: 1"]
pub type Mpusegb11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB12` reader - MPU Segment Border 1 Bit: 2"]
pub type Mpusegb12R = crate::BitReader;
#[doc = "Field `MPUSEGB12` writer - MPU Segment Border 1 Bit: 2"]
pub type Mpusegb12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB13` reader - MPU Segment Border 1 Bit: 3"]
pub type Mpusegb13R = crate::BitReader;
#[doc = "Field `MPUSEGB13` writer - MPU Segment Border 1 Bit: 3"]
pub type Mpusegb13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB14` reader - MPU Segment Border 1 Bit: 4"]
pub type Mpusegb14R = crate::BitReader;
#[doc = "Field `MPUSEGB14` writer - MPU Segment Border 1 Bit: 4"]
pub type Mpusegb14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB15` reader - MPU Segment Border 1 Bit: 5"]
pub type Mpusegb15R = crate::BitReader;
#[doc = "Field `MPUSEGB15` writer - MPU Segment Border 1 Bit: 5"]
pub type Mpusegb15W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB16` reader - MPU Segment Border 1 Bit: 6"]
pub type Mpusegb16R = crate::BitReader;
#[doc = "Field `MPUSEGB16` writer - MPU Segment Border 1 Bit: 6"]
pub type Mpusegb16W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB17` reader - MPU Segment Border 1 Bit: 7"]
pub type Mpusegb17R = crate::BitReader;
#[doc = "Field `MPUSEGB17` writer - MPU Segment Border 1 Bit: 7"]
pub type Mpusegb17W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB18` reader - MPU Segment Border 1 Bit: 8"]
pub type Mpusegb18R = crate::BitReader;
#[doc = "Field `MPUSEGB18` writer - MPU Segment Border 1 Bit: 8"]
pub type Mpusegb18W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB19` reader - MPU Segment Border 1 Bit: 9"]
pub type Mpusegb19R = crate::BitReader;
#[doc = "Field `MPUSEGB19` writer - MPU Segment Border 1 Bit: 9"]
pub type Mpusegb19W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB110` reader - MPU Segment Border 1 Bit: 10"]
pub type Mpusegb110R = crate::BitReader;
#[doc = "Field `MPUSEGB110` writer - MPU Segment Border 1 Bit: 10"]
pub type Mpusegb110W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB111` reader - MPU Segment Border 1 Bit: 11"]
pub type Mpusegb111R = crate::BitReader;
#[doc = "Field `MPUSEGB111` writer - MPU Segment Border 1 Bit: 11"]
pub type Mpusegb111W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB112` reader - MPU Segment Border 1 Bit: 12"]
pub type Mpusegb112R = crate::BitReader;
#[doc = "Field `MPUSEGB112` writer - MPU Segment Border 1 Bit: 12"]
pub type Mpusegb112W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB113` reader - MPU Segment Border 1 Bit: 13"]
pub type Mpusegb113R = crate::BitReader;
#[doc = "Field `MPUSEGB113` writer - MPU Segment Border 1 Bit: 13"]
pub type Mpusegb113W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB114` reader - MPU Segment Border 1 Bit: 14"]
pub type Mpusegb114R = crate::BitReader;
#[doc = "Field `MPUSEGB114` writer - MPU Segment Border 1 Bit: 14"]
pub type Mpusegb114W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGB115` reader - MPU Segment Border 1 Bit: 15"]
pub type Mpusegb115R = crate::BitReader;
#[doc = "Field `MPUSEGB115` writer - MPU Segment Border 1 Bit: 15"]
pub type Mpusegb115W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - MPU Segment Border 1 Bit: 0"]
#[inline(always)]
pub fn mpusegb10(&self) -> Mpusegb10R {
Mpusegb10R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - MPU Segment Border 1 Bit: 1"]
#[inline(always)]
pub fn mpusegb11(&self) -> Mpusegb11R {
Mpusegb11R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - MPU Segment Border 1 Bit: 2"]
#[inline(always)]
pub fn mpusegb12(&self) -> Mpusegb12R {
Mpusegb12R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - MPU Segment Border 1 Bit: 3"]
#[inline(always)]
pub fn mpusegb13(&self) -> Mpusegb13R {
Mpusegb13R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - MPU Segment Border 1 Bit: 4"]
#[inline(always)]
pub fn mpusegb14(&self) -> Mpusegb14R {
Mpusegb14R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - MPU Segment Border 1 Bit: 5"]
#[inline(always)]
pub fn mpusegb15(&self) -> Mpusegb15R {
Mpusegb15R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - MPU Segment Border 1 Bit: 6"]
#[inline(always)]
pub fn mpusegb16(&self) -> Mpusegb16R {
Mpusegb16R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - MPU Segment Border 1 Bit: 7"]
#[inline(always)]
pub fn mpusegb17(&self) -> Mpusegb17R {
Mpusegb17R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - MPU Segment Border 1 Bit: 8"]
#[inline(always)]
pub fn mpusegb18(&self) -> Mpusegb18R {
Mpusegb18R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - MPU Segment Border 1 Bit: 9"]
#[inline(always)]
pub fn mpusegb19(&self) -> Mpusegb19R {
Mpusegb19R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - MPU Segment Border 1 Bit: 10"]
#[inline(always)]
pub fn mpusegb110(&self) -> Mpusegb110R {
Mpusegb110R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - MPU Segment Border 1 Bit: 11"]
#[inline(always)]
pub fn mpusegb111(&self) -> Mpusegb111R {
Mpusegb111R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - MPU Segment Border 1 Bit: 12"]
#[inline(always)]
pub fn mpusegb112(&self) -> Mpusegb112R {
Mpusegb112R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - MPU Segment Border 1 Bit: 13"]
#[inline(always)]
pub fn mpusegb113(&self) -> Mpusegb113R {
Mpusegb113R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - MPU Segment Border 1 Bit: 14"]
#[inline(always)]
pub fn mpusegb114(&self) -> Mpusegb114R {
Mpusegb114R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - MPU Segment Border 1 Bit: 15"]
#[inline(always)]
pub fn mpusegb115(&self) -> Mpusegb115R {
Mpusegb115R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - MPU Segment Border 1 Bit: 0"]
#[inline(always)]
pub fn mpusegb10(&mut self) -> Mpusegb10W<'_, Mpusegb1Spec> {
Mpusegb10W::new(self, 0)
}
#[doc = "Bit 1 - MPU Segment Border 1 Bit: 1"]
#[inline(always)]
pub fn mpusegb11(&mut self) -> Mpusegb11W<'_, Mpusegb1Spec> {
Mpusegb11W::new(self, 1)
}
#[doc = "Bit 2 - MPU Segment Border 1 Bit: 2"]
#[inline(always)]
pub fn mpusegb12(&mut self) -> Mpusegb12W<'_, Mpusegb1Spec> {
Mpusegb12W::new(self, 2)
}
#[doc = "Bit 3 - MPU Segment Border 1 Bit: 3"]
#[inline(always)]
pub fn mpusegb13(&mut self) -> Mpusegb13W<'_, Mpusegb1Spec> {
Mpusegb13W::new(self, 3)
}
#[doc = "Bit 4 - MPU Segment Border 1 Bit: 4"]
#[inline(always)]
pub fn mpusegb14(&mut self) -> Mpusegb14W<'_, Mpusegb1Spec> {
Mpusegb14W::new(self, 4)
}
#[doc = "Bit 5 - MPU Segment Border 1 Bit: 5"]
#[inline(always)]
pub fn mpusegb15(&mut self) -> Mpusegb15W<'_, Mpusegb1Spec> {
Mpusegb15W::new(self, 5)
}
#[doc = "Bit 6 - MPU Segment Border 1 Bit: 6"]
#[inline(always)]
pub fn mpusegb16(&mut self) -> Mpusegb16W<'_, Mpusegb1Spec> {
Mpusegb16W::new(self, 6)
}
#[doc = "Bit 7 - MPU Segment Border 1 Bit: 7"]
#[inline(always)]
pub fn mpusegb17(&mut self) -> Mpusegb17W<'_, Mpusegb1Spec> {
Mpusegb17W::new(self, 7)
}
#[doc = "Bit 8 - MPU Segment Border 1 Bit: 8"]
#[inline(always)]
pub fn mpusegb18(&mut self) -> Mpusegb18W<'_, Mpusegb1Spec> {
Mpusegb18W::new(self, 8)
}
#[doc = "Bit 9 - MPU Segment Border 1 Bit: 9"]
#[inline(always)]
pub fn mpusegb19(&mut self) -> Mpusegb19W<'_, Mpusegb1Spec> {
Mpusegb19W::new(self, 9)
}
#[doc = "Bit 10 - MPU Segment Border 1 Bit: 10"]
#[inline(always)]
pub fn mpusegb110(&mut self) -> Mpusegb110W<'_, Mpusegb1Spec> {
Mpusegb110W::new(self, 10)
}
#[doc = "Bit 11 - MPU Segment Border 1 Bit: 11"]
#[inline(always)]
pub fn mpusegb111(&mut self) -> Mpusegb111W<'_, Mpusegb1Spec> {
Mpusegb111W::new(self, 11)
}
#[doc = "Bit 12 - MPU Segment Border 1 Bit: 12"]
#[inline(always)]
pub fn mpusegb112(&mut self) -> Mpusegb112W<'_, Mpusegb1Spec> {
Mpusegb112W::new(self, 12)
}
#[doc = "Bit 13 - MPU Segment Border 1 Bit: 13"]
#[inline(always)]
pub fn mpusegb113(&mut self) -> Mpusegb113W<'_, Mpusegb1Spec> {
Mpusegb113W::new(self, 13)
}
#[doc = "Bit 14 - MPU Segment Border 1 Bit: 14"]
#[inline(always)]
pub fn mpusegb114(&mut self) -> Mpusegb114W<'_, Mpusegb1Spec> {
Mpusegb114W::new(self, 14)
}
#[doc = "Bit 15 - MPU Segment Border 1 Bit: 15"]
#[inline(always)]
pub fn mpusegb115(&mut self) -> Mpusegb115W<'_, Mpusegb1Spec> {
Mpusegb115W::new(self, 15)
}
}
#[doc = "MPU Segmentation Border 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mpusegb1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpusegb1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mpusegb1Spec;
impl crate::RegisterSpec for Mpusegb1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mpusegb1::R`](R) reader structure"]
impl crate::Readable for Mpusegb1Spec {}
#[doc = "`write(|w| ..)` method takes [`mpusegb1::W`](W) writer structure"]
impl crate::Writable for Mpusegb1Spec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets MPUSEGB1 to value 0"]
impl crate::Resettable for Mpusegb1Spec {}
}
#[doc = "MPUSAM (rw) register accessor: MPU Access Management Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mpusam::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpusam::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mpusam`] module"]
#[doc(alias = "MPUSAM")]
pub type Mpusam = crate::Reg<mpusam::MpusamSpec>;
#[doc = "MPU Access Management Register"]
pub mod mpusam {
#[doc = "Register `MPUSAM` reader"]
pub type R = crate::R<MpusamSpec>;
#[doc = "Register `MPUSAM` writer"]
pub type W = crate::W<MpusamSpec>;
#[doc = "Field `MPUSEG1RE` reader - MPU Main memory Segment 1 Read enable"]
pub type Mpuseg1reR = crate::BitReader;
#[doc = "Field `MPUSEG1RE` writer - MPU Main memory Segment 1 Read enable"]
pub type Mpuseg1reW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEG1WE` reader - MPU Main memory Segment 1 Write enable"]
pub type Mpuseg1weR = crate::BitReader;
#[doc = "Field `MPUSEG1WE` writer - MPU Main memory Segment 1 Write enable"]
pub type Mpuseg1weW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEG1XE` reader - MPU Main memory Segment 1 Execute enable"]
pub type Mpuseg1xeR = crate::BitReader;
#[doc = "Field `MPUSEG1XE` writer - MPU Main memory Segment 1 Execute enable"]
pub type Mpuseg1xeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEG1VS` reader - MPU Main memory Segment 1 Violation select"]
pub type Mpuseg1vsR = crate::BitReader;
#[doc = "Field `MPUSEG1VS` writer - MPU Main memory Segment 1 Violation select"]
pub type Mpuseg1vsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEG2RE` reader - MPU Main memory Segment 2 Read enable"]
pub type Mpuseg2reR = crate::BitReader;
#[doc = "Field `MPUSEG2RE` writer - MPU Main memory Segment 2 Read enable"]
pub type Mpuseg2reW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEG2WE` reader - MPU Main memory Segment 2 Write enable"]
pub type Mpuseg2weR = crate::BitReader;
#[doc = "Field `MPUSEG2WE` writer - MPU Main memory Segment 2 Write enable"]
pub type Mpuseg2weW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEG2XE` reader - MPU Main memory Segment 2 Execute enable"]
pub type Mpuseg2xeR = crate::BitReader;
#[doc = "Field `MPUSEG2XE` writer - MPU Main memory Segment 2 Execute enable"]
pub type Mpuseg2xeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEG2VS` reader - MPU Main memory Segment 2 Violation select"]
pub type Mpuseg2vsR = crate::BitReader;
#[doc = "Field `MPUSEG2VS` writer - MPU Main memory Segment 2 Violation select"]
pub type Mpuseg2vsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEG3RE` reader - MPU Main memory Segment 3 Read enable"]
pub type Mpuseg3reR = crate::BitReader;
#[doc = "Field `MPUSEG3RE` writer - MPU Main memory Segment 3 Read enable"]
pub type Mpuseg3reW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEG3WE` reader - MPU Main memory Segment 3 Write enable"]
pub type Mpuseg3weR = crate::BitReader;
#[doc = "Field `MPUSEG3WE` writer - MPU Main memory Segment 3 Write enable"]
pub type Mpuseg3weW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEG3XE` reader - MPU Main memory Segment 3 Execute enable"]
pub type Mpuseg3xeR = crate::BitReader;
#[doc = "Field `MPUSEG3XE` writer - MPU Main memory Segment 3 Execute enable"]
pub type Mpuseg3xeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEG3VS` reader - MPU Main memory Segment 3 Violation select"]
pub type Mpuseg3vsR = crate::BitReader;
#[doc = "Field `MPUSEG3VS` writer - MPU Main memory Segment 3 Violation select"]
pub type Mpuseg3vsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGIRE` reader - MPU Info memory Segment Read enable"]
pub type MpusegireR = crate::BitReader;
#[doc = "Field `MPUSEGIRE` writer - MPU Info memory Segment Read enable"]
pub type MpusegireW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGIWE` reader - MPU Info memory Segment Write enable"]
pub type MpusegiweR = crate::BitReader;
#[doc = "Field `MPUSEGIWE` writer - MPU Info memory Segment Write enable"]
pub type MpusegiweW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGIXE` reader - MPU Info memory Segment Execute enable"]
pub type MpusegixeR = crate::BitReader;
#[doc = "Field `MPUSEGIXE` writer - MPU Info memory Segment Execute enable"]
pub type MpusegixeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUSEGIVS` reader - MPU Info memory Segment Violation select"]
pub type MpusegivsR = crate::BitReader;
#[doc = "Field `MPUSEGIVS` writer - MPU Info memory Segment Violation select"]
pub type MpusegivsW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - MPU Main memory Segment 1 Read enable"]
#[inline(always)]
pub fn mpuseg1re(&self) -> Mpuseg1reR {
Mpuseg1reR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - MPU Main memory Segment 1 Write enable"]
#[inline(always)]
pub fn mpuseg1we(&self) -> Mpuseg1weR {
Mpuseg1weR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - MPU Main memory Segment 1 Execute enable"]
#[inline(always)]
pub fn mpuseg1xe(&self) -> Mpuseg1xeR {
Mpuseg1xeR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - MPU Main memory Segment 1 Violation select"]
#[inline(always)]
pub fn mpuseg1vs(&self) -> Mpuseg1vsR {
Mpuseg1vsR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - MPU Main memory Segment 2 Read enable"]
#[inline(always)]
pub fn mpuseg2re(&self) -> Mpuseg2reR {
Mpuseg2reR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - MPU Main memory Segment 2 Write enable"]
#[inline(always)]
pub fn mpuseg2we(&self) -> Mpuseg2weR {
Mpuseg2weR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - MPU Main memory Segment 2 Execute enable"]
#[inline(always)]
pub fn mpuseg2xe(&self) -> Mpuseg2xeR {
Mpuseg2xeR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - MPU Main memory Segment 2 Violation select"]
#[inline(always)]
pub fn mpuseg2vs(&self) -> Mpuseg2vsR {
Mpuseg2vsR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - MPU Main memory Segment 3 Read enable"]
#[inline(always)]
pub fn mpuseg3re(&self) -> Mpuseg3reR {
Mpuseg3reR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - MPU Main memory Segment 3 Write enable"]
#[inline(always)]
pub fn mpuseg3we(&self) -> Mpuseg3weR {
Mpuseg3weR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - MPU Main memory Segment 3 Execute enable"]
#[inline(always)]
pub fn mpuseg3xe(&self) -> Mpuseg3xeR {
Mpuseg3xeR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - MPU Main memory Segment 3 Violation select"]
#[inline(always)]
pub fn mpuseg3vs(&self) -> Mpuseg3vsR {
Mpuseg3vsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - MPU Info memory Segment Read enable"]
#[inline(always)]
pub fn mpusegire(&self) -> MpusegireR {
MpusegireR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - MPU Info memory Segment Write enable"]
#[inline(always)]
pub fn mpusegiwe(&self) -> MpusegiweR {
MpusegiweR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - MPU Info memory Segment Execute enable"]
#[inline(always)]
pub fn mpusegixe(&self) -> MpusegixeR {
MpusegixeR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - MPU Info memory Segment Violation select"]
#[inline(always)]
pub fn mpusegivs(&self) -> MpusegivsR {
MpusegivsR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - MPU Main memory Segment 1 Read enable"]
#[inline(always)]
pub fn mpuseg1re(&mut self) -> Mpuseg1reW<'_, MpusamSpec> {
Mpuseg1reW::new(self, 0)
}
#[doc = "Bit 1 - MPU Main memory Segment 1 Write enable"]
#[inline(always)]
pub fn mpuseg1we(&mut self) -> Mpuseg1weW<'_, MpusamSpec> {
Mpuseg1weW::new(self, 1)
}
#[doc = "Bit 2 - MPU Main memory Segment 1 Execute enable"]
#[inline(always)]
pub fn mpuseg1xe(&mut self) -> Mpuseg1xeW<'_, MpusamSpec> {
Mpuseg1xeW::new(self, 2)
}
#[doc = "Bit 3 - MPU Main memory Segment 1 Violation select"]
#[inline(always)]
pub fn mpuseg1vs(&mut self) -> Mpuseg1vsW<'_, MpusamSpec> {
Mpuseg1vsW::new(self, 3)
}
#[doc = "Bit 4 - MPU Main memory Segment 2 Read enable"]
#[inline(always)]
pub fn mpuseg2re(&mut self) -> Mpuseg2reW<'_, MpusamSpec> {
Mpuseg2reW::new(self, 4)
}
#[doc = "Bit 5 - MPU Main memory Segment 2 Write enable"]
#[inline(always)]
pub fn mpuseg2we(&mut self) -> Mpuseg2weW<'_, MpusamSpec> {
Mpuseg2weW::new(self, 5)
}
#[doc = "Bit 6 - MPU Main memory Segment 2 Execute enable"]
#[inline(always)]
pub fn mpuseg2xe(&mut self) -> Mpuseg2xeW<'_, MpusamSpec> {
Mpuseg2xeW::new(self, 6)
}
#[doc = "Bit 7 - MPU Main memory Segment 2 Violation select"]
#[inline(always)]
pub fn mpuseg2vs(&mut self) -> Mpuseg2vsW<'_, MpusamSpec> {
Mpuseg2vsW::new(self, 7)
}
#[doc = "Bit 8 - MPU Main memory Segment 3 Read enable"]
#[inline(always)]
pub fn mpuseg3re(&mut self) -> Mpuseg3reW<'_, MpusamSpec> {
Mpuseg3reW::new(self, 8)
}
#[doc = "Bit 9 - MPU Main memory Segment 3 Write enable"]
#[inline(always)]
pub fn mpuseg3we(&mut self) -> Mpuseg3weW<'_, MpusamSpec> {
Mpuseg3weW::new(self, 9)
}
#[doc = "Bit 10 - MPU Main memory Segment 3 Execute enable"]
#[inline(always)]
pub fn mpuseg3xe(&mut self) -> Mpuseg3xeW<'_, MpusamSpec> {
Mpuseg3xeW::new(self, 10)
}
#[doc = "Bit 11 - MPU Main memory Segment 3 Violation select"]
#[inline(always)]
pub fn mpuseg3vs(&mut self) -> Mpuseg3vsW<'_, MpusamSpec> {
Mpuseg3vsW::new(self, 11)
}
#[doc = "Bit 12 - MPU Info memory Segment Read enable"]
#[inline(always)]
pub fn mpusegire(&mut self) -> MpusegireW<'_, MpusamSpec> {
MpusegireW::new(self, 12)
}
#[doc = "Bit 13 - MPU Info memory Segment Write enable"]
#[inline(always)]
pub fn mpusegiwe(&mut self) -> MpusegiweW<'_, MpusamSpec> {
MpusegiweW::new(self, 13)
}
#[doc = "Bit 14 - MPU Info memory Segment Execute enable"]
#[inline(always)]
pub fn mpusegixe(&mut self) -> MpusegixeW<'_, MpusamSpec> {
MpusegixeW::new(self, 14)
}
#[doc = "Bit 15 - MPU Info memory Segment Violation select"]
#[inline(always)]
pub fn mpusegivs(&mut self) -> MpusegivsW<'_, MpusamSpec> {
MpusegivsW::new(self, 15)
}
}
#[doc = "MPU Access Management Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mpusam::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpusam::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MpusamSpec;
impl crate::RegisterSpec for MpusamSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mpusam::R`](R) reader structure"]
impl crate::Readable for MpusamSpec {}
#[doc = "`write(|w| ..)` method takes [`mpusam::W`](W) writer structure"]
impl crate::Writable for MpusamSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets MPUSAM to value 0"]
impl crate::Resettable for MpusamSpec {}
}
#[doc = "MPUIPC0 (rw) register accessor: MPU IP Control 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mpuipc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpuipc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mpuipc0`] module"]
#[doc(alias = "MPUIPC0")]
pub type Mpuipc0 = crate::Reg<mpuipc0::Mpuipc0Spec>;
#[doc = "MPU IP Control 0 Register"]
pub mod mpuipc0 {
#[doc = "Register `MPUIPC0` reader"]
pub type R = crate::R<Mpuipc0Spec>;
#[doc = "Register `MPUIPC0` writer"]
pub type W = crate::W<Mpuipc0Spec>;
#[doc = "Field `MPUIPVS` reader - MPU MPU IP protection segment Violation Select"]
pub type MpuipvsR = crate::BitReader;
#[doc = "Field `MPUIPVS` writer - MPU MPU IP protection segment Violation Select"]
pub type MpuipvsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPENA` reader - MPU MPU IP Protection Enable"]
pub type MpuipenaR = crate::BitReader;
#[doc = "Field `MPUIPENA` writer - MPU MPU IP Protection Enable"]
pub type MpuipenaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPLOCK` reader - MPU IP Protection Lock"]
pub type MpuiplockR = crate::BitReader;
#[doc = "Field `MPUIPLOCK` writer - MPU IP Protection Lock"]
pub type MpuiplockW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 5 - MPU MPU IP protection segment Violation Select"]
#[inline(always)]
pub fn mpuipvs(&self) -> MpuipvsR {
MpuipvsR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - MPU MPU IP Protection Enable"]
#[inline(always)]
pub fn mpuipena(&self) -> MpuipenaR {
MpuipenaR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - MPU IP Protection Lock"]
#[inline(always)]
pub fn mpuiplock(&self) -> MpuiplockR {
MpuiplockR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 5 - MPU MPU IP protection segment Violation Select"]
#[inline(always)]
pub fn mpuipvs(&mut self) -> MpuipvsW<'_, Mpuipc0Spec> {
MpuipvsW::new(self, 5)
}
#[doc = "Bit 6 - MPU MPU IP Protection Enable"]
#[inline(always)]
pub fn mpuipena(&mut self) -> MpuipenaW<'_, Mpuipc0Spec> {
MpuipenaW::new(self, 6)
}
#[doc = "Bit 7 - MPU IP Protection Lock"]
#[inline(always)]
pub fn mpuiplock(&mut self) -> MpuiplockW<'_, Mpuipc0Spec> {
MpuiplockW::new(self, 7)
}
}
#[doc = "MPU IP Control 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mpuipc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpuipc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mpuipc0Spec;
impl crate::RegisterSpec for Mpuipc0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mpuipc0::R`](R) reader structure"]
impl crate::Readable for Mpuipc0Spec {}
#[doc = "`write(|w| ..)` method takes [`mpuipc0::W`](W) writer structure"]
impl crate::Writable for Mpuipc0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MPUIPC0 to value 0"]
impl crate::Resettable for Mpuipc0Spec {}
}
#[doc = "MPUIPSEGB2 (rw) register accessor: MPU IP Segment Border 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mpuipsegb2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpuipsegb2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mpuipsegb2`] module"]
#[doc(alias = "MPUIPSEGB2")]
pub type Mpuipsegb2 = crate::Reg<mpuipsegb2::Mpuipsegb2Spec>;
#[doc = "MPU IP Segment Border 2 Register"]
pub mod mpuipsegb2 {
#[doc = "Register `MPUIPSEGB2` reader"]
pub type R = crate::R<Mpuipsegb2Spec>;
#[doc = "Register `MPUIPSEGB2` writer"]
pub type W = crate::W<Mpuipsegb2Spec>;
#[doc = "Field `MPUIPSEGB20` reader - MPU IP Segment Border 2 Bit: 0"]
pub type Mpuipsegb20R = crate::BitReader;
#[doc = "Field `MPUIPSEGB20` writer - MPU IP Segment Border 2 Bit: 0"]
pub type Mpuipsegb20W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB21` reader - MPU IP Segment Border 2 Bit: 1"]
pub type Mpuipsegb21R = crate::BitReader;
#[doc = "Field `MPUIPSEGB21` writer - MPU IP Segment Border 2 Bit: 1"]
pub type Mpuipsegb21W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB22` reader - MPU IP Segment Border 2 Bit: 2"]
pub type Mpuipsegb22R = crate::BitReader;
#[doc = "Field `MPUIPSEGB22` writer - MPU IP Segment Border 2 Bit: 2"]
pub type Mpuipsegb22W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB23` reader - MPU IP Segment Border 2 Bit: 3"]
pub type Mpuipsegb23R = crate::BitReader;
#[doc = "Field `MPUIPSEGB23` writer - MPU IP Segment Border 2 Bit: 3"]
pub type Mpuipsegb23W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB24` reader - MPU IP Segment Border 2 Bit: 4"]
pub type Mpuipsegb24R = crate::BitReader;
#[doc = "Field `MPUIPSEGB24` writer - MPU IP Segment Border 2 Bit: 4"]
pub type Mpuipsegb24W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB25` reader - MPU IP Segment Border 2 Bit: 5"]
pub type Mpuipsegb25R = crate::BitReader;
#[doc = "Field `MPUIPSEGB25` writer - MPU IP Segment Border 2 Bit: 5"]
pub type Mpuipsegb25W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB26` reader - MPU IP Segment Border 2 Bit: 6"]
pub type Mpuipsegb26R = crate::BitReader;
#[doc = "Field `MPUIPSEGB26` writer - MPU IP Segment Border 2 Bit: 6"]
pub type Mpuipsegb26W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB27` reader - MPU IP Segment Border 2 Bit: 7"]
pub type Mpuipsegb27R = crate::BitReader;
#[doc = "Field `MPUIPSEGB27` writer - MPU IP Segment Border 2 Bit: 7"]
pub type Mpuipsegb27W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB28` reader - MPU IP Segment Border 2 Bit: 8"]
pub type Mpuipsegb28R = crate::BitReader;
#[doc = "Field `MPUIPSEGB28` writer - MPU IP Segment Border 2 Bit: 8"]
pub type Mpuipsegb28W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB29` reader - MPU IP Segment Border 2 Bit: 9"]
pub type Mpuipsegb29R = crate::BitReader;
#[doc = "Field `MPUIPSEGB29` writer - MPU IP Segment Border 2 Bit: 9"]
pub type Mpuipsegb29W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB210` reader - MPU IP Segment Border 2 Bit: 10"]
pub type Mpuipsegb210R = crate::BitReader;
#[doc = "Field `MPUIPSEGB210` writer - MPU IP Segment Border 2 Bit: 10"]
pub type Mpuipsegb210W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB211` reader - MPU IP Segment Border 2 Bit: 11"]
pub type Mpuipsegb211R = crate::BitReader;
#[doc = "Field `MPUIPSEGB211` writer - MPU IP Segment Border 2 Bit: 11"]
pub type Mpuipsegb211W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB212` reader - MPU IP Segment Border 2 Bit: 12"]
pub type Mpuipsegb212R = crate::BitReader;
#[doc = "Field `MPUIPSEGB212` writer - MPU IP Segment Border 2 Bit: 12"]
pub type Mpuipsegb212W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB213` reader - MPU IP Segment Border 2 Bit: 13"]
pub type Mpuipsegb213R = crate::BitReader;
#[doc = "Field `MPUIPSEGB213` writer - MPU IP Segment Border 2 Bit: 13"]
pub type Mpuipsegb213W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB214` reader - MPU IP Segment Border 2 Bit: 14"]
pub type Mpuipsegb214R = crate::BitReader;
#[doc = "Field `MPUIPSEGB214` writer - MPU IP Segment Border 2 Bit: 14"]
pub type Mpuipsegb214W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB215` reader - MPU IP Segment Border 2 Bit: 15"]
pub type Mpuipsegb215R = crate::BitReader;
#[doc = "Field `MPUIPSEGB215` writer - MPU IP Segment Border 2 Bit: 15"]
pub type Mpuipsegb215W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - MPU IP Segment Border 2 Bit: 0"]
#[inline(always)]
pub fn mpuipsegb20(&self) -> Mpuipsegb20R {
Mpuipsegb20R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - MPU IP Segment Border 2 Bit: 1"]
#[inline(always)]
pub fn mpuipsegb21(&self) -> Mpuipsegb21R {
Mpuipsegb21R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - MPU IP Segment Border 2 Bit: 2"]
#[inline(always)]
pub fn mpuipsegb22(&self) -> Mpuipsegb22R {
Mpuipsegb22R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - MPU IP Segment Border 2 Bit: 3"]
#[inline(always)]
pub fn mpuipsegb23(&self) -> Mpuipsegb23R {
Mpuipsegb23R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - MPU IP Segment Border 2 Bit: 4"]
#[inline(always)]
pub fn mpuipsegb24(&self) -> Mpuipsegb24R {
Mpuipsegb24R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - MPU IP Segment Border 2 Bit: 5"]
#[inline(always)]
pub fn mpuipsegb25(&self) -> Mpuipsegb25R {
Mpuipsegb25R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - MPU IP Segment Border 2 Bit: 6"]
#[inline(always)]
pub fn mpuipsegb26(&self) -> Mpuipsegb26R {
Mpuipsegb26R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - MPU IP Segment Border 2 Bit: 7"]
#[inline(always)]
pub fn mpuipsegb27(&self) -> Mpuipsegb27R {
Mpuipsegb27R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - MPU IP Segment Border 2 Bit: 8"]
#[inline(always)]
pub fn mpuipsegb28(&self) -> Mpuipsegb28R {
Mpuipsegb28R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - MPU IP Segment Border 2 Bit: 9"]
#[inline(always)]
pub fn mpuipsegb29(&self) -> Mpuipsegb29R {
Mpuipsegb29R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - MPU IP Segment Border 2 Bit: 10"]
#[inline(always)]
pub fn mpuipsegb210(&self) -> Mpuipsegb210R {
Mpuipsegb210R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - MPU IP Segment Border 2 Bit: 11"]
#[inline(always)]
pub fn mpuipsegb211(&self) -> Mpuipsegb211R {
Mpuipsegb211R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - MPU IP Segment Border 2 Bit: 12"]
#[inline(always)]
pub fn mpuipsegb212(&self) -> Mpuipsegb212R {
Mpuipsegb212R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - MPU IP Segment Border 2 Bit: 13"]
#[inline(always)]
pub fn mpuipsegb213(&self) -> Mpuipsegb213R {
Mpuipsegb213R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - MPU IP Segment Border 2 Bit: 14"]
#[inline(always)]
pub fn mpuipsegb214(&self) -> Mpuipsegb214R {
Mpuipsegb214R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - MPU IP Segment Border 2 Bit: 15"]
#[inline(always)]
pub fn mpuipsegb215(&self) -> Mpuipsegb215R {
Mpuipsegb215R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - MPU IP Segment Border 2 Bit: 0"]
#[inline(always)]
pub fn mpuipsegb20(&mut self) -> Mpuipsegb20W<'_, Mpuipsegb2Spec> {
Mpuipsegb20W::new(self, 0)
}
#[doc = "Bit 1 - MPU IP Segment Border 2 Bit: 1"]
#[inline(always)]
pub fn mpuipsegb21(&mut self) -> Mpuipsegb21W<'_, Mpuipsegb2Spec> {
Mpuipsegb21W::new(self, 1)
}
#[doc = "Bit 2 - MPU IP Segment Border 2 Bit: 2"]
#[inline(always)]
pub fn mpuipsegb22(&mut self) -> Mpuipsegb22W<'_, Mpuipsegb2Spec> {
Mpuipsegb22W::new(self, 2)
}
#[doc = "Bit 3 - MPU IP Segment Border 2 Bit: 3"]
#[inline(always)]
pub fn mpuipsegb23(&mut self) -> Mpuipsegb23W<'_, Mpuipsegb2Spec> {
Mpuipsegb23W::new(self, 3)
}
#[doc = "Bit 4 - MPU IP Segment Border 2 Bit: 4"]
#[inline(always)]
pub fn mpuipsegb24(&mut self) -> Mpuipsegb24W<'_, Mpuipsegb2Spec> {
Mpuipsegb24W::new(self, 4)
}
#[doc = "Bit 5 - MPU IP Segment Border 2 Bit: 5"]
#[inline(always)]
pub fn mpuipsegb25(&mut self) -> Mpuipsegb25W<'_, Mpuipsegb2Spec> {
Mpuipsegb25W::new(self, 5)
}
#[doc = "Bit 6 - MPU IP Segment Border 2 Bit: 6"]
#[inline(always)]
pub fn mpuipsegb26(&mut self) -> Mpuipsegb26W<'_, Mpuipsegb2Spec> {
Mpuipsegb26W::new(self, 6)
}
#[doc = "Bit 7 - MPU IP Segment Border 2 Bit: 7"]
#[inline(always)]
pub fn mpuipsegb27(&mut self) -> Mpuipsegb27W<'_, Mpuipsegb2Spec> {
Mpuipsegb27W::new(self, 7)
}
#[doc = "Bit 8 - MPU IP Segment Border 2 Bit: 8"]
#[inline(always)]
pub fn mpuipsegb28(&mut self) -> Mpuipsegb28W<'_, Mpuipsegb2Spec> {
Mpuipsegb28W::new(self, 8)
}
#[doc = "Bit 9 - MPU IP Segment Border 2 Bit: 9"]
#[inline(always)]
pub fn mpuipsegb29(&mut self) -> Mpuipsegb29W<'_, Mpuipsegb2Spec> {
Mpuipsegb29W::new(self, 9)
}
#[doc = "Bit 10 - MPU IP Segment Border 2 Bit: 10"]
#[inline(always)]
pub fn mpuipsegb210(&mut self) -> Mpuipsegb210W<'_, Mpuipsegb2Spec> {
Mpuipsegb210W::new(self, 10)
}
#[doc = "Bit 11 - MPU IP Segment Border 2 Bit: 11"]
#[inline(always)]
pub fn mpuipsegb211(&mut self) -> Mpuipsegb211W<'_, Mpuipsegb2Spec> {
Mpuipsegb211W::new(self, 11)
}
#[doc = "Bit 12 - MPU IP Segment Border 2 Bit: 12"]
#[inline(always)]
pub fn mpuipsegb212(&mut self) -> Mpuipsegb212W<'_, Mpuipsegb2Spec> {
Mpuipsegb212W::new(self, 12)
}
#[doc = "Bit 13 - MPU IP Segment Border 2 Bit: 13"]
#[inline(always)]
pub fn mpuipsegb213(&mut self) -> Mpuipsegb213W<'_, Mpuipsegb2Spec> {
Mpuipsegb213W::new(self, 13)
}
#[doc = "Bit 14 - MPU IP Segment Border 2 Bit: 14"]
#[inline(always)]
pub fn mpuipsegb214(&mut self) -> Mpuipsegb214W<'_, Mpuipsegb2Spec> {
Mpuipsegb214W::new(self, 14)
}
#[doc = "Bit 15 - MPU IP Segment Border 2 Bit: 15"]
#[inline(always)]
pub fn mpuipsegb215(&mut self) -> Mpuipsegb215W<'_, Mpuipsegb2Spec> {
Mpuipsegb215W::new(self, 15)
}
}
#[doc = "MPU IP Segment Border 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mpuipsegb2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpuipsegb2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mpuipsegb2Spec;
impl crate::RegisterSpec for Mpuipsegb2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mpuipsegb2::R`](R) reader structure"]
impl crate::Readable for Mpuipsegb2Spec {}
#[doc = "`write(|w| ..)` method takes [`mpuipsegb2::W`](W) writer structure"]
impl crate::Writable for Mpuipsegb2Spec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets MPUIPSEGB2 to value 0"]
impl crate::Resettable for Mpuipsegb2Spec {}
}
#[doc = "MPUIPSEGB1 (rw) register accessor: MPU IP Segment Border 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mpuipsegb1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpuipsegb1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mpuipsegb1`] module"]
#[doc(alias = "MPUIPSEGB1")]
pub type Mpuipsegb1 = crate::Reg<mpuipsegb1::Mpuipsegb1Spec>;
#[doc = "MPU IP Segment Border 1 Register"]
pub mod mpuipsegb1 {
#[doc = "Register `MPUIPSEGB1` reader"]
pub type R = crate::R<Mpuipsegb1Spec>;
#[doc = "Register `MPUIPSEGB1` writer"]
pub type W = crate::W<Mpuipsegb1Spec>;
#[doc = "Field `MPUIPSEGB10` reader - MPU IP Segment Border 1 Bit: 0"]
pub type Mpuipsegb10R = crate::BitReader;
#[doc = "Field `MPUIPSEGB10` writer - MPU IP Segment Border 1 Bit: 0"]
pub type Mpuipsegb10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB11` reader - MPU IP Segment Border 1 Bit: 1"]
pub type Mpuipsegb11R = crate::BitReader;
#[doc = "Field `MPUIPSEGB11` writer - MPU IP Segment Border 1 Bit: 1"]
pub type Mpuipsegb11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB12` reader - MPU IP Segment Border 1 Bit: 2"]
pub type Mpuipsegb12R = crate::BitReader;
#[doc = "Field `MPUIPSEGB12` writer - MPU IP Segment Border 1 Bit: 2"]
pub type Mpuipsegb12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB13` reader - MPU IP Segment Border 1 Bit: 3"]
pub type Mpuipsegb13R = crate::BitReader;
#[doc = "Field `MPUIPSEGB13` writer - MPU IP Segment Border 1 Bit: 3"]
pub type Mpuipsegb13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB14` reader - MPU IP Segment Border 1 Bit: 4"]
pub type Mpuipsegb14R = crate::BitReader;
#[doc = "Field `MPUIPSEGB14` writer - MPU IP Segment Border 1 Bit: 4"]
pub type Mpuipsegb14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB15` reader - MPU IP Segment Border 1 Bit: 5"]
pub type Mpuipsegb15R = crate::BitReader;
#[doc = "Field `MPUIPSEGB15` writer - MPU IP Segment Border 1 Bit: 5"]
pub type Mpuipsegb15W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB16` reader - MPU IP Segment Border 1 Bit: 6"]
pub type Mpuipsegb16R = crate::BitReader;
#[doc = "Field `MPUIPSEGB16` writer - MPU IP Segment Border 1 Bit: 6"]
pub type Mpuipsegb16W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB17` reader - MPU IP Segment Border 1 Bit: 7"]
pub type Mpuipsegb17R = crate::BitReader;
#[doc = "Field `MPUIPSEGB17` writer - MPU IP Segment Border 1 Bit: 7"]
pub type Mpuipsegb17W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB18` reader - MPU IP Segment Border 1 Bit: 8"]
pub type Mpuipsegb18R = crate::BitReader;
#[doc = "Field `MPUIPSEGB18` writer - MPU IP Segment Border 1 Bit: 8"]
pub type Mpuipsegb18W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB19` reader - MPU IP Segment Border 1 Bit: 9"]
pub type Mpuipsegb19R = crate::BitReader;
#[doc = "Field `MPUIPSEGB19` writer - MPU IP Segment Border 1 Bit: 9"]
pub type Mpuipsegb19W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB110` reader - MPU IP Segment Border 1 Bit: 10"]
pub type Mpuipsegb110R = crate::BitReader;
#[doc = "Field `MPUIPSEGB110` writer - MPU IP Segment Border 1 Bit: 10"]
pub type Mpuipsegb110W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB111` reader - MPU IP Segment Border 1 Bit: 11"]
pub type Mpuipsegb111R = crate::BitReader;
#[doc = "Field `MPUIPSEGB111` writer - MPU IP Segment Border 1 Bit: 11"]
pub type Mpuipsegb111W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB112` reader - MPU IP Segment Border 1 Bit: 12"]
pub type Mpuipsegb112R = crate::BitReader;
#[doc = "Field `MPUIPSEGB112` writer - MPU IP Segment Border 1 Bit: 12"]
pub type Mpuipsegb112W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB113` reader - MPU IP Segment Border 1 Bit: 13"]
pub type Mpuipsegb113R = crate::BitReader;
#[doc = "Field `MPUIPSEGB113` writer - MPU IP Segment Border 1 Bit: 13"]
pub type Mpuipsegb113W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB114` reader - MPU IP Segment Border 1 Bit: 14"]
pub type Mpuipsegb114R = crate::BitReader;
#[doc = "Field `MPUIPSEGB114` writer - MPU IP Segment Border 1 Bit: 14"]
pub type Mpuipsegb114W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MPUIPSEGB115` reader - MPU IP Segment Border 1 Bit: 15"]
pub type Mpuipsegb115R = crate::BitReader;
#[doc = "Field `MPUIPSEGB115` writer - MPU IP Segment Border 1 Bit: 15"]
pub type Mpuipsegb115W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - MPU IP Segment Border 1 Bit: 0"]
#[inline(always)]
pub fn mpuipsegb10(&self) -> Mpuipsegb10R {
Mpuipsegb10R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - MPU IP Segment Border 1 Bit: 1"]
#[inline(always)]
pub fn mpuipsegb11(&self) -> Mpuipsegb11R {
Mpuipsegb11R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - MPU IP Segment Border 1 Bit: 2"]
#[inline(always)]
pub fn mpuipsegb12(&self) -> Mpuipsegb12R {
Mpuipsegb12R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - MPU IP Segment Border 1 Bit: 3"]
#[inline(always)]
pub fn mpuipsegb13(&self) -> Mpuipsegb13R {
Mpuipsegb13R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - MPU IP Segment Border 1 Bit: 4"]
#[inline(always)]
pub fn mpuipsegb14(&self) -> Mpuipsegb14R {
Mpuipsegb14R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - MPU IP Segment Border 1 Bit: 5"]
#[inline(always)]
pub fn mpuipsegb15(&self) -> Mpuipsegb15R {
Mpuipsegb15R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - MPU IP Segment Border 1 Bit: 6"]
#[inline(always)]
pub fn mpuipsegb16(&self) -> Mpuipsegb16R {
Mpuipsegb16R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - MPU IP Segment Border 1 Bit: 7"]
#[inline(always)]
pub fn mpuipsegb17(&self) -> Mpuipsegb17R {
Mpuipsegb17R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - MPU IP Segment Border 1 Bit: 8"]
#[inline(always)]
pub fn mpuipsegb18(&self) -> Mpuipsegb18R {
Mpuipsegb18R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - MPU IP Segment Border 1 Bit: 9"]
#[inline(always)]
pub fn mpuipsegb19(&self) -> Mpuipsegb19R {
Mpuipsegb19R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - MPU IP Segment Border 1 Bit: 10"]
#[inline(always)]
pub fn mpuipsegb110(&self) -> Mpuipsegb110R {
Mpuipsegb110R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - MPU IP Segment Border 1 Bit: 11"]
#[inline(always)]
pub fn mpuipsegb111(&self) -> Mpuipsegb111R {
Mpuipsegb111R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - MPU IP Segment Border 1 Bit: 12"]
#[inline(always)]
pub fn mpuipsegb112(&self) -> Mpuipsegb112R {
Mpuipsegb112R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - MPU IP Segment Border 1 Bit: 13"]
#[inline(always)]
pub fn mpuipsegb113(&self) -> Mpuipsegb113R {
Mpuipsegb113R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - MPU IP Segment Border 1 Bit: 14"]
#[inline(always)]
pub fn mpuipsegb114(&self) -> Mpuipsegb114R {
Mpuipsegb114R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - MPU IP Segment Border 1 Bit: 15"]
#[inline(always)]
pub fn mpuipsegb115(&self) -> Mpuipsegb115R {
Mpuipsegb115R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - MPU IP Segment Border 1 Bit: 0"]
#[inline(always)]
pub fn mpuipsegb10(&mut self) -> Mpuipsegb10W<'_, Mpuipsegb1Spec> {
Mpuipsegb10W::new(self, 0)
}
#[doc = "Bit 1 - MPU IP Segment Border 1 Bit: 1"]
#[inline(always)]
pub fn mpuipsegb11(&mut self) -> Mpuipsegb11W<'_, Mpuipsegb1Spec> {
Mpuipsegb11W::new(self, 1)
}
#[doc = "Bit 2 - MPU IP Segment Border 1 Bit: 2"]
#[inline(always)]
pub fn mpuipsegb12(&mut self) -> Mpuipsegb12W<'_, Mpuipsegb1Spec> {
Mpuipsegb12W::new(self, 2)
}
#[doc = "Bit 3 - MPU IP Segment Border 1 Bit: 3"]
#[inline(always)]
pub fn mpuipsegb13(&mut self) -> Mpuipsegb13W<'_, Mpuipsegb1Spec> {
Mpuipsegb13W::new(self, 3)
}
#[doc = "Bit 4 - MPU IP Segment Border 1 Bit: 4"]
#[inline(always)]
pub fn mpuipsegb14(&mut self) -> Mpuipsegb14W<'_, Mpuipsegb1Spec> {
Mpuipsegb14W::new(self, 4)
}
#[doc = "Bit 5 - MPU IP Segment Border 1 Bit: 5"]
#[inline(always)]
pub fn mpuipsegb15(&mut self) -> Mpuipsegb15W<'_, Mpuipsegb1Spec> {
Mpuipsegb15W::new(self, 5)
}
#[doc = "Bit 6 - MPU IP Segment Border 1 Bit: 6"]
#[inline(always)]
pub fn mpuipsegb16(&mut self) -> Mpuipsegb16W<'_, Mpuipsegb1Spec> {
Mpuipsegb16W::new(self, 6)
}
#[doc = "Bit 7 - MPU IP Segment Border 1 Bit: 7"]
#[inline(always)]
pub fn mpuipsegb17(&mut self) -> Mpuipsegb17W<'_, Mpuipsegb1Spec> {
Mpuipsegb17W::new(self, 7)
}
#[doc = "Bit 8 - MPU IP Segment Border 1 Bit: 8"]
#[inline(always)]
pub fn mpuipsegb18(&mut self) -> Mpuipsegb18W<'_, Mpuipsegb1Spec> {
Mpuipsegb18W::new(self, 8)
}
#[doc = "Bit 9 - MPU IP Segment Border 1 Bit: 9"]
#[inline(always)]
pub fn mpuipsegb19(&mut self) -> Mpuipsegb19W<'_, Mpuipsegb1Spec> {
Mpuipsegb19W::new(self, 9)
}
#[doc = "Bit 10 - MPU IP Segment Border 1 Bit: 10"]
#[inline(always)]
pub fn mpuipsegb110(&mut self) -> Mpuipsegb110W<'_, Mpuipsegb1Spec> {
Mpuipsegb110W::new(self, 10)
}
#[doc = "Bit 11 - MPU IP Segment Border 1 Bit: 11"]
#[inline(always)]
pub fn mpuipsegb111(&mut self) -> Mpuipsegb111W<'_, Mpuipsegb1Spec> {
Mpuipsegb111W::new(self, 11)
}
#[doc = "Bit 12 - MPU IP Segment Border 1 Bit: 12"]
#[inline(always)]
pub fn mpuipsegb112(&mut self) -> Mpuipsegb112W<'_, Mpuipsegb1Spec> {
Mpuipsegb112W::new(self, 12)
}
#[doc = "Bit 13 - MPU IP Segment Border 1 Bit: 13"]
#[inline(always)]
pub fn mpuipsegb113(&mut self) -> Mpuipsegb113W<'_, Mpuipsegb1Spec> {
Mpuipsegb113W::new(self, 13)
}
#[doc = "Bit 14 - MPU IP Segment Border 1 Bit: 14"]
#[inline(always)]
pub fn mpuipsegb114(&mut self) -> Mpuipsegb114W<'_, Mpuipsegb1Spec> {
Mpuipsegb114W::new(self, 14)
}
#[doc = "Bit 15 - MPU IP Segment Border 1 Bit: 15"]
#[inline(always)]
pub fn mpuipsegb115(&mut self) -> Mpuipsegb115W<'_, Mpuipsegb1Spec> {
Mpuipsegb115W::new(self, 15)
}
}
#[doc = "MPU IP Segment Border 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mpuipsegb1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpuipsegb1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mpuipsegb1Spec;
impl crate::RegisterSpec for Mpuipsegb1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`mpuipsegb1::R`](R) reader structure"]
impl crate::Readable for Mpuipsegb1Spec {}
#[doc = "`write(|w| ..)` method takes [`mpuipsegb1::W`](W) writer structure"]
impl crate::Writable for Mpuipsegb1Spec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets MPUIPSEGB1 to value 0"]
impl crate::Resettable for Mpuipsegb1Spec {}
}
}
#[doc = "ADC12"]
pub type Adc12 = crate::Periph<adc12::RegisterBlock, 0x0800>;
impl core::fmt::Debug for Adc12 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Adc12").finish()
}
}
#[doc = "ADC12"]
pub mod adc12 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
adc12ctl0: Adc12ctl0,
adc12ctl1: Adc12ctl1,
adc12ctl2: Adc12ctl2,
adc12ctl3: Adc12ctl3,
adc12lo: Adc12lo,
adc12hi: Adc12hi,
adc12ifgr0: Adc12ifgr0,
adc12ifgr1: Adc12ifgr1,
adc12ifgr2: Adc12ifgr2,
adc12ier0: Adc12ier0,
adc12ier1: Adc12ier1,
adc12ier2: Adc12ier2,
adc12iv: Adc12iv,
_reserved13: [u8; 0x06],
adc12mctl0: Adc12mctl0,
adc12mctl1: Adc12mctl1,
adc12mctl2: Adc12mctl2,
adc12mctl3: Adc12mctl3,
adc12mctl4: Adc12mctl4,
adc12mctl5: Adc12mctl5,
adc12mctl6: Adc12mctl6,
adc12mctl7: Adc12mctl7,
adc12mctl8: Adc12mctl8,
adc12mctl9: Adc12mctl9,
adc12mctl10: Adc12mctl10,
adc12mctl11: Adc12mctl11,
adc12mctl12: Adc12mctl12,
adc12mctl13: Adc12mctl13,
adc12mctl14: Adc12mctl14,
adc12mctl15: Adc12mctl15,
adc12mctl16: Adc12mctl16,
adc12mctl17: Adc12mctl17,
adc12mctl18: Adc12mctl18,
adc12mctl19: Adc12mctl19,
adc12mctl20: Adc12mctl20,
adc12mctl21: Adc12mctl21,
adc12mctl22: Adc12mctl22,
adc12mctl23: Adc12mctl23,
adc12mctl24: Adc12mctl24,
adc12mctl25: Adc12mctl25,
adc12mctl26: Adc12mctl26,
adc12mctl27: Adc12mctl27,
adc12mctl28: Adc12mctl28,
adc12mctl29: Adc12mctl29,
adc12mctl30: Adc12mctl30,
adc12mctl31: Adc12mctl31,
adc12mem0: Adc12mem0,
adc12mem1: Adc12mem1,
adc12mem2: Adc12mem2,
adc12mem3: Adc12mem3,
adc12mem4: Adc12mem4,
adc12mem5: Adc12mem5,
adc12mem6: Adc12mem6,
adc12mem7: Adc12mem7,
adc12mem8: Adc12mem8,
adc12mem9: Adc12mem9,
adc12mem10: Adc12mem10,
adc12mem11: Adc12mem11,
adc12mem12: Adc12mem12,
adc12mem13: Adc12mem13,
adc12mem14: Adc12mem14,
adc12mem15: Adc12mem15,
adc12mem16: Adc12mem16,
adc12mem17: Adc12mem17,
adc12mem18: Adc12mem18,
adc12mem19: Adc12mem19,
adc12mem20: Adc12mem20,
adc12mem21: Adc12mem21,
adc12mem22: Adc12mem22,
adc12mem23: Adc12mem23,
adc12mem24: Adc12mem24,
adc12mem25: Adc12mem25,
adc12mem26: Adc12mem26,
adc12mem27: Adc12mem27,
adc12mem28: Adc12mem28,
adc12mem29: Adc12mem29,
adc12mem30: Adc12mem30,
adc12mem31: Adc12mem31,
}
impl RegisterBlock {
#[doc = "0x00 - ADC12 B Control 0"]
#[inline(always)]
pub const fn adc12ctl0(&self) -> &Adc12ctl0 {
&self.adc12ctl0
}
#[doc = "0x02 - ADC12 B Control 1"]
#[inline(always)]
pub const fn adc12ctl1(&self) -> &Adc12ctl1 {
&self.adc12ctl1
}
#[doc = "0x04 - ADC12 B Control 2"]
#[inline(always)]
pub const fn adc12ctl2(&self) -> &Adc12ctl2 {
&self.adc12ctl2
}
#[doc = "0x06 - ADC12 B Control 3"]
#[inline(always)]
pub const fn adc12ctl3(&self) -> &Adc12ctl3 {
&self.adc12ctl3
}
#[doc = "0x08 - ADC12 B Window Comparator High Threshold"]
#[inline(always)]
pub const fn adc12lo(&self) -> &Adc12lo {
&self.adc12lo
}
#[doc = "0x0a - ADC12 B Window Comparator High Threshold"]
#[inline(always)]
pub const fn adc12hi(&self) -> &Adc12hi {
&self.adc12hi
}
#[doc = "0x0c - ADC12 B Interrupt Flag 0"]
#[inline(always)]
pub const fn adc12ifgr0(&self) -> &Adc12ifgr0 {
&self.adc12ifgr0
}
#[doc = "0x0e - ADC12 B Interrupt Flag 1"]
#[inline(always)]
pub const fn adc12ifgr1(&self) -> &Adc12ifgr1 {
&self.adc12ifgr1
}
#[doc = "0x10 - ADC12 B Interrupt Flag 2"]
#[inline(always)]
pub const fn adc12ifgr2(&self) -> &Adc12ifgr2 {
&self.adc12ifgr2
}
#[doc = "0x12 - ADC12 B Interrupt Enable 0"]
#[inline(always)]
pub const fn adc12ier0(&self) -> &Adc12ier0 {
&self.adc12ier0
}
#[doc = "0x14 - ADC12 B Interrupt Enable 1"]
#[inline(always)]
pub const fn adc12ier1(&self) -> &Adc12ier1 {
&self.adc12ier1
}
#[doc = "0x16 - ADC12 B Interrupt Enable 2"]
#[inline(always)]
pub const fn adc12ier2(&self) -> &Adc12ier2 {
&self.adc12ier2
}
#[doc = "0x18 - ADC12 B Interrupt Vector Word"]
#[inline(always)]
pub const fn adc12iv(&self) -> &Adc12iv {
&self.adc12iv
}
#[doc = "0x20 - ADC12 Memory Control 0"]
#[inline(always)]
pub const fn adc12mctl0(&self) -> &Adc12mctl0 {
&self.adc12mctl0
}
#[doc = "0x22 - ADC12 Memory Control 1"]
#[inline(always)]
pub const fn adc12mctl1(&self) -> &Adc12mctl1 {
&self.adc12mctl1
}
#[doc = "0x24 - ADC12 Memory Control 2"]
#[inline(always)]
pub const fn adc12mctl2(&self) -> &Adc12mctl2 {
&self.adc12mctl2
}
#[doc = "0x26 - ADC12 Memory Control 3"]
#[inline(always)]
pub const fn adc12mctl3(&self) -> &Adc12mctl3 {
&self.adc12mctl3
}
#[doc = "0x28 - ADC12 Memory Control 4"]
#[inline(always)]
pub const fn adc12mctl4(&self) -> &Adc12mctl4 {
&self.adc12mctl4
}
#[doc = "0x2a - ADC12 Memory Control 5"]
#[inline(always)]
pub const fn adc12mctl5(&self) -> &Adc12mctl5 {
&self.adc12mctl5
}
#[doc = "0x2c - ADC12 Memory Control 6"]
#[inline(always)]
pub const fn adc12mctl6(&self) -> &Adc12mctl6 {
&self.adc12mctl6
}
#[doc = "0x2e - ADC12 Memory Control 7"]
#[inline(always)]
pub const fn adc12mctl7(&self) -> &Adc12mctl7 {
&self.adc12mctl7
}
#[doc = "0x30 - ADC12 Memory Control 8"]
#[inline(always)]
pub const fn adc12mctl8(&self) -> &Adc12mctl8 {
&self.adc12mctl8
}
#[doc = "0x32 - ADC12 Memory Control 9"]
#[inline(always)]
pub const fn adc12mctl9(&self) -> &Adc12mctl9 {
&self.adc12mctl9
}
#[doc = "0x34 - ADC12 Memory Control 10"]
#[inline(always)]
pub const fn adc12mctl10(&self) -> &Adc12mctl10 {
&self.adc12mctl10
}
#[doc = "0x36 - ADC12 Memory Control 11"]
#[inline(always)]
pub const fn adc12mctl11(&self) -> &Adc12mctl11 {
&self.adc12mctl11
}
#[doc = "0x38 - ADC12 Memory Control 12"]
#[inline(always)]
pub const fn adc12mctl12(&self) -> &Adc12mctl12 {
&self.adc12mctl12
}
#[doc = "0x3a - ADC12 Memory Control 13"]
#[inline(always)]
pub const fn adc12mctl13(&self) -> &Adc12mctl13 {
&self.adc12mctl13
}
#[doc = "0x3c - ADC12 Memory Control 14"]
#[inline(always)]
pub const fn adc12mctl14(&self) -> &Adc12mctl14 {
&self.adc12mctl14
}
#[doc = "0x3e - ADC12 Memory Control 15"]
#[inline(always)]
pub const fn adc12mctl15(&self) -> &Adc12mctl15 {
&self.adc12mctl15
}
#[doc = "0x40 - ADC12 Memory Control 16"]
#[inline(always)]
pub const fn adc12mctl16(&self) -> &Adc12mctl16 {
&self.adc12mctl16
}
#[doc = "0x42 - ADC12 Memory Control 17"]
#[inline(always)]
pub const fn adc12mctl17(&self) -> &Adc12mctl17 {
&self.adc12mctl17
}
#[doc = "0x44 - ADC12 Memory Control 18"]
#[inline(always)]
pub const fn adc12mctl18(&self) -> &Adc12mctl18 {
&self.adc12mctl18
}
#[doc = "0x46 - ADC12 Memory Control 19"]
#[inline(always)]
pub const fn adc12mctl19(&self) -> &Adc12mctl19 {
&self.adc12mctl19
}
#[doc = "0x48 - ADC12 Memory Control 20"]
#[inline(always)]
pub const fn adc12mctl20(&self) -> &Adc12mctl20 {
&self.adc12mctl20
}
#[doc = "0x4a - ADC12 Memory Control 21"]
#[inline(always)]
pub const fn adc12mctl21(&self) -> &Adc12mctl21 {
&self.adc12mctl21
}
#[doc = "0x4c - ADC12 Memory Control 22"]
#[inline(always)]
pub const fn adc12mctl22(&self) -> &Adc12mctl22 {
&self.adc12mctl22
}
#[doc = "0x4e - ADC12 Memory Control 23"]
#[inline(always)]
pub const fn adc12mctl23(&self) -> &Adc12mctl23 {
&self.adc12mctl23
}
#[doc = "0x50 - ADC12 Memory Control 24"]
#[inline(always)]
pub const fn adc12mctl24(&self) -> &Adc12mctl24 {
&self.adc12mctl24
}
#[doc = "0x52 - ADC12 Memory Control 25"]
#[inline(always)]
pub const fn adc12mctl25(&self) -> &Adc12mctl25 {
&self.adc12mctl25
}
#[doc = "0x54 - ADC12 Memory Control 26"]
#[inline(always)]
pub const fn adc12mctl26(&self) -> &Adc12mctl26 {
&self.adc12mctl26
}
#[doc = "0x56 - ADC12 Memory Control 27"]
#[inline(always)]
pub const fn adc12mctl27(&self) -> &Adc12mctl27 {
&self.adc12mctl27
}
#[doc = "0x58 - ADC12 Memory Control 28"]
#[inline(always)]
pub const fn adc12mctl28(&self) -> &Adc12mctl28 {
&self.adc12mctl28
}
#[doc = "0x5a - ADC12 Memory Control 29"]
#[inline(always)]
pub const fn adc12mctl29(&self) -> &Adc12mctl29 {
&self.adc12mctl29
}
#[doc = "0x5c - ADC12 Memory Control 30"]
#[inline(always)]
pub const fn adc12mctl30(&self) -> &Adc12mctl30 {
&self.adc12mctl30
}
#[doc = "0x5e - ADC12 Memory Control 31"]
#[inline(always)]
pub const fn adc12mctl31(&self) -> &Adc12mctl31 {
&self.adc12mctl31
}
#[doc = "0x60 - ADC12 Conversion Memory 0"]
#[inline(always)]
pub const fn adc12mem0(&self) -> &Adc12mem0 {
&self.adc12mem0
}
#[doc = "0x62 - ADC12 Conversion Memory 1"]
#[inline(always)]
pub const fn adc12mem1(&self) -> &Adc12mem1 {
&self.adc12mem1
}
#[doc = "0x64 - ADC12 Conversion Memory 2"]
#[inline(always)]
pub const fn adc12mem2(&self) -> &Adc12mem2 {
&self.adc12mem2
}
#[doc = "0x66 - ADC12 Conversion Memory 3"]
#[inline(always)]
pub const fn adc12mem3(&self) -> &Adc12mem3 {
&self.adc12mem3
}
#[doc = "0x68 - ADC12 Conversion Memory 4"]
#[inline(always)]
pub const fn adc12mem4(&self) -> &Adc12mem4 {
&self.adc12mem4
}
#[doc = "0x6a - ADC12 Conversion Memory 5"]
#[inline(always)]
pub const fn adc12mem5(&self) -> &Adc12mem5 {
&self.adc12mem5
}
#[doc = "0x6c - ADC12 Conversion Memory 6"]
#[inline(always)]
pub const fn adc12mem6(&self) -> &Adc12mem6 {
&self.adc12mem6
}
#[doc = "0x6e - ADC12 Conversion Memory 7"]
#[inline(always)]
pub const fn adc12mem7(&self) -> &Adc12mem7 {
&self.adc12mem7
}
#[doc = "0x70 - ADC12 Conversion Memory 8"]
#[inline(always)]
pub const fn adc12mem8(&self) -> &Adc12mem8 {
&self.adc12mem8
}
#[doc = "0x72 - ADC12 Conversion Memory 9"]
#[inline(always)]
pub const fn adc12mem9(&self) -> &Adc12mem9 {
&self.adc12mem9
}
#[doc = "0x74 - ADC12 Conversion Memory 10"]
#[inline(always)]
pub const fn adc12mem10(&self) -> &Adc12mem10 {
&self.adc12mem10
}
#[doc = "0x76 - ADC12 Conversion Memory 11"]
#[inline(always)]
pub const fn adc12mem11(&self) -> &Adc12mem11 {
&self.adc12mem11
}
#[doc = "0x78 - ADC12 Conversion Memory 12"]
#[inline(always)]
pub const fn adc12mem12(&self) -> &Adc12mem12 {
&self.adc12mem12
}
#[doc = "0x7a - ADC12 Conversion Memory 13"]
#[inline(always)]
pub const fn adc12mem13(&self) -> &Adc12mem13 {
&self.adc12mem13
}
#[doc = "0x7c - ADC12 Conversion Memory 14"]
#[inline(always)]
pub const fn adc12mem14(&self) -> &Adc12mem14 {
&self.adc12mem14
}
#[doc = "0x7e - ADC12 Conversion Memory 15"]
#[inline(always)]
pub const fn adc12mem15(&self) -> &Adc12mem15 {
&self.adc12mem15
}
#[doc = "0x80 - ADC12 Conversion Memory 16"]
#[inline(always)]
pub const fn adc12mem16(&self) -> &Adc12mem16 {
&self.adc12mem16
}
#[doc = "0x82 - ADC12 Conversion Memory 17"]
#[inline(always)]
pub const fn adc12mem17(&self) -> &Adc12mem17 {
&self.adc12mem17
}
#[doc = "0x84 - ADC12 Conversion Memory 18"]
#[inline(always)]
pub const fn adc12mem18(&self) -> &Adc12mem18 {
&self.adc12mem18
}
#[doc = "0x86 - ADC12 Conversion Memory 19"]
#[inline(always)]
pub const fn adc12mem19(&self) -> &Adc12mem19 {
&self.adc12mem19
}
#[doc = "0x88 - ADC12 Conversion Memory 20"]
#[inline(always)]
pub const fn adc12mem20(&self) -> &Adc12mem20 {
&self.adc12mem20
}
#[doc = "0x8a - ADC12 Conversion Memory 21"]
#[inline(always)]
pub const fn adc12mem21(&self) -> &Adc12mem21 {
&self.adc12mem21
}
#[doc = "0x8c - ADC12 Conversion Memory 22"]
#[inline(always)]
pub const fn adc12mem22(&self) -> &Adc12mem22 {
&self.adc12mem22
}
#[doc = "0x8e - ADC12 Conversion Memory 23"]
#[inline(always)]
pub const fn adc12mem23(&self) -> &Adc12mem23 {
&self.adc12mem23
}
#[doc = "0x90 - ADC12 Conversion Memory 24"]
#[inline(always)]
pub const fn adc12mem24(&self) -> &Adc12mem24 {
&self.adc12mem24
}
#[doc = "0x92 - ADC12 Conversion Memory 25"]
#[inline(always)]
pub const fn adc12mem25(&self) -> &Adc12mem25 {
&self.adc12mem25
}
#[doc = "0x94 - ADC12 Conversion Memory 26"]
#[inline(always)]
pub const fn adc12mem26(&self) -> &Adc12mem26 {
&self.adc12mem26
}
#[doc = "0x96 - ADC12 Conversion Memory 27"]
#[inline(always)]
pub const fn adc12mem27(&self) -> &Adc12mem27 {
&self.adc12mem27
}
#[doc = "0x98 - ADC12 Conversion Memory 28"]
#[inline(always)]
pub const fn adc12mem28(&self) -> &Adc12mem28 {
&self.adc12mem28
}
#[doc = "0x9a - ADC12 Conversion Memory 29"]
#[inline(always)]
pub const fn adc12mem29(&self) -> &Adc12mem29 {
&self.adc12mem29
}
#[doc = "0x9c - ADC12 Conversion Memory 30"]
#[inline(always)]
pub const fn adc12mem30(&self) -> &Adc12mem30 {
&self.adc12mem30
}
#[doc = "0x9e - ADC12 Conversion Memory 31"]
#[inline(always)]
pub const fn adc12mem31(&self) -> &Adc12mem31 {
&self.adc12mem31
}
}
#[doc = "ADC12CTL0 (rw) register accessor: ADC12 B Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12ctl0`] module"]
#[doc(alias = "ADC12CTL0")]
pub type Adc12ctl0 = crate::Reg<adc12ctl0::Adc12ctl0Spec>;
#[doc = "ADC12 B Control 0"]
pub mod adc12ctl0 {
#[doc = "Register `ADC12CTL0` reader"]
pub type R = crate::R<Adc12ctl0Spec>;
#[doc = "Register `ADC12CTL0` writer"]
pub type W = crate::W<Adc12ctl0Spec>;
#[doc = "Field `ADC12SC` reader - ADC12 Start Conversion"]
pub type Adc12scR = crate::BitReader;
#[doc = "Field `ADC12SC` writer - ADC12 Start Conversion"]
pub type Adc12scW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12ENC` reader - ADC12 Enable Conversion"]
pub type Adc12encR = crate::BitReader;
#[doc = "Field `ADC12ENC` writer - ADC12 Enable Conversion"]
pub type Adc12encW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12ON` reader - ADC12 On/enable"]
pub type Adc12onR = crate::BitReader;
#[doc = "Field `ADC12ON` writer - ADC12 On/enable"]
pub type Adc12onW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12MSC` reader - ADC12 Multiple SampleConversion"]
pub type Adc12mscR = crate::BitReader;
#[doc = "Field `ADC12MSC` writer - ADC12 Multiple SampleConversion"]
pub type Adc12mscW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 Sample Hold 0 Select Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12sht0 {
#[doc = "0: ADC12 Sample Hold 0 Select Bit: 0"]
Adc12sht0_0 = 0,
#[doc = "1: ADC12 Sample Hold 0 Select Bit: 1"]
Adc12sht0_1 = 1,
#[doc = "2: ADC12 Sample Hold 0 Select Bit: 2"]
Adc12sht0_2 = 2,
#[doc = "3: ADC12 Sample Hold 0 Select Bit: 3"]
Adc12sht0_3 = 3,
#[doc = "4: ADC12 Sample Hold 0 Select Bit: 4"]
Adc12sht0_4 = 4,
#[doc = "5: ADC12 Sample Hold 0 Select Bit: 5"]
Adc12sht0_5 = 5,
#[doc = "6: ADC12 Sample Hold 0 Select Bit: 6"]
Adc12sht0_6 = 6,
#[doc = "7: ADC12 Sample Hold 0 Select Bit: 7"]
Adc12sht0_7 = 7,
#[doc = "8: ADC12 Sample Hold 0 Select Bit: 8"]
Adc12sht0_8 = 8,
#[doc = "9: ADC12 Sample Hold 0 Select Bit: 9"]
Adc12sht0_9 = 9,
#[doc = "10: ADC12 Sample Hold 0 Select Bit: 10"]
Adc12sht0_10 = 10,
#[doc = "11: ADC12 Sample Hold 0 Select Bit: 11"]
Adc12sht0_11 = 11,
#[doc = "12: ADC12 Sample Hold 0 Select Bit: 12"]
Adc12sht0_12 = 12,
#[doc = "13: ADC12 Sample Hold 0 Select Bit: 13"]
Adc12sht0_13 = 13,
#[doc = "14: ADC12 Sample Hold 0 Select Bit: 14"]
Adc12sht0_14 = 14,
#[doc = "15: ADC12 Sample Hold 0 Select Bit: 15"]
Adc12sht0_15 = 15,
}
impl From<Adc12sht0> for u8 {
#[inline(always)]
fn from(variant: Adc12sht0) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12sht0 {
type Ux = u8;
}
impl crate::IsEnum for Adc12sht0 {}
#[doc = "Field `ADC12SHT0` reader - ADC12 Sample Hold 0 Select Bit: 0"]
pub type Adc12sht0R = crate::FieldReader<Adc12sht0>;
impl Adc12sht0R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12sht0 {
match self.bits {
0 => Adc12sht0::Adc12sht0_0,
1 => Adc12sht0::Adc12sht0_1,
2 => Adc12sht0::Adc12sht0_2,
3 => Adc12sht0::Adc12sht0_3,
4 => Adc12sht0::Adc12sht0_4,
5 => Adc12sht0::Adc12sht0_5,
6 => Adc12sht0::Adc12sht0_6,
7 => Adc12sht0::Adc12sht0_7,
8 => Adc12sht0::Adc12sht0_8,
9 => Adc12sht0::Adc12sht0_9,
10 => Adc12sht0::Adc12sht0_10,
11 => Adc12sht0::Adc12sht0_11,
12 => Adc12sht0::Adc12sht0_12,
13 => Adc12sht0::Adc12sht0_13,
14 => Adc12sht0::Adc12sht0_14,
15 => Adc12sht0::Adc12sht0_15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 0"]
#[inline(always)]
pub fn is_adc12sht0_0(&self) -> bool {
*self == Adc12sht0::Adc12sht0_0
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 1"]
#[inline(always)]
pub fn is_adc12sht0_1(&self) -> bool {
*self == Adc12sht0::Adc12sht0_1
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 2"]
#[inline(always)]
pub fn is_adc12sht0_2(&self) -> bool {
*self == Adc12sht0::Adc12sht0_2
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 3"]
#[inline(always)]
pub fn is_adc12sht0_3(&self) -> bool {
*self == Adc12sht0::Adc12sht0_3
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 4"]
#[inline(always)]
pub fn is_adc12sht0_4(&self) -> bool {
*self == Adc12sht0::Adc12sht0_4
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 5"]
#[inline(always)]
pub fn is_adc12sht0_5(&self) -> bool {
*self == Adc12sht0::Adc12sht0_5
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 6"]
#[inline(always)]
pub fn is_adc12sht0_6(&self) -> bool {
*self == Adc12sht0::Adc12sht0_6
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 7"]
#[inline(always)]
pub fn is_adc12sht0_7(&self) -> bool {
*self == Adc12sht0::Adc12sht0_7
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 8"]
#[inline(always)]
pub fn is_adc12sht0_8(&self) -> bool {
*self == Adc12sht0::Adc12sht0_8
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 9"]
#[inline(always)]
pub fn is_adc12sht0_9(&self) -> bool {
*self == Adc12sht0::Adc12sht0_9
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 10"]
#[inline(always)]
pub fn is_adc12sht0_10(&self) -> bool {
*self == Adc12sht0::Adc12sht0_10
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 11"]
#[inline(always)]
pub fn is_adc12sht0_11(&self) -> bool {
*self == Adc12sht0::Adc12sht0_11
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 12"]
#[inline(always)]
pub fn is_adc12sht0_12(&self) -> bool {
*self == Adc12sht0::Adc12sht0_12
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 13"]
#[inline(always)]
pub fn is_adc12sht0_13(&self) -> bool {
*self == Adc12sht0::Adc12sht0_13
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 14"]
#[inline(always)]
pub fn is_adc12sht0_14(&self) -> bool {
*self == Adc12sht0::Adc12sht0_14
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 15"]
#[inline(always)]
pub fn is_adc12sht0_15(&self) -> bool {
*self == Adc12sht0::Adc12sht0_15
}
}
#[doc = "Field `ADC12SHT0` writer - ADC12 Sample Hold 0 Select Bit: 0"]
pub type Adc12sht0W<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12sht0, crate::Safe>;
impl<'a, REG> Adc12sht0W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Sample Hold 0 Select Bit: 0"]
#[inline(always)]
pub fn adc12sht0_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_0)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 1"]
#[inline(always)]
pub fn adc12sht0_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_1)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 2"]
#[inline(always)]
pub fn adc12sht0_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_2)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 3"]
#[inline(always)]
pub fn adc12sht0_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_3)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 4"]
#[inline(always)]
pub fn adc12sht0_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_4)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 5"]
#[inline(always)]
pub fn adc12sht0_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_5)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 6"]
#[inline(always)]
pub fn adc12sht0_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_6)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 7"]
#[inline(always)]
pub fn adc12sht0_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_7)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 8"]
#[inline(always)]
pub fn adc12sht0_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_8)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 9"]
#[inline(always)]
pub fn adc12sht0_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_9)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 10"]
#[inline(always)]
pub fn adc12sht0_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_10)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 11"]
#[inline(always)]
pub fn adc12sht0_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_11)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 12"]
#[inline(always)]
pub fn adc12sht0_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_12)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 13"]
#[inline(always)]
pub fn adc12sht0_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_13)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 14"]
#[inline(always)]
pub fn adc12sht0_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_14)
}
#[doc = "ADC12 Sample Hold 0 Select Bit: 15"]
#[inline(always)]
pub fn adc12sht0_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht0::Adc12sht0_15)
}
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12sht1 {
#[doc = "0: ADC12 Sample Hold 1 Select Bit: 0"]
Adc12sht1_0 = 0,
#[doc = "1: ADC12 Sample Hold 1 Select Bit: 1"]
Adc12sht1_1 = 1,
#[doc = "2: ADC12 Sample Hold 1 Select Bit: 2"]
Adc12sht1_2 = 2,
#[doc = "3: ADC12 Sample Hold 1 Select Bit: 3"]
Adc12sht1_3 = 3,
#[doc = "4: ADC12 Sample Hold 1 Select Bit: 4"]
Adc12sht1_4 = 4,
#[doc = "5: ADC12 Sample Hold 1 Select Bit: 5"]
Adc12sht1_5 = 5,
#[doc = "6: ADC12 Sample Hold 1 Select Bit: 6"]
Adc12sht1_6 = 6,
#[doc = "7: ADC12 Sample Hold 1 Select Bit: 7"]
Adc12sht1_7 = 7,
#[doc = "8: ADC12 Sample Hold 1 Select Bit: 8"]
Adc12sht1_8 = 8,
#[doc = "9: ADC12 Sample Hold 1 Select Bit: 9"]
Adc12sht1_9 = 9,
#[doc = "10: ADC12 Sample Hold 1 Select Bit: 10"]
Adc12sht1_10 = 10,
#[doc = "11: ADC12 Sample Hold 1 Select Bit: 11"]
Adc12sht1_11 = 11,
#[doc = "12: ADC12 Sample Hold 1 Select Bit: 12"]
Adc12sht1_12 = 12,
#[doc = "13: ADC12 Sample Hold 1 Select Bit: 13"]
Adc12sht1_13 = 13,
#[doc = "14: ADC12 Sample Hold 1 Select Bit: 14"]
Adc12sht1_14 = 14,
#[doc = "15: ADC12 Sample Hold 1 Select Bit: 15"]
Adc12sht1_15 = 15,
}
impl From<Adc12sht1> for u8 {
#[inline(always)]
fn from(variant: Adc12sht1) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12sht1 {
type Ux = u8;
}
impl crate::IsEnum for Adc12sht1 {}
#[doc = "Field `ADC12SHT1` reader - ADC12 Sample Hold 1 Select Bit: 0"]
pub type Adc12sht1R = crate::FieldReader<Adc12sht1>;
impl Adc12sht1R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12sht1 {
match self.bits {
0 => Adc12sht1::Adc12sht1_0,
1 => Adc12sht1::Adc12sht1_1,
2 => Adc12sht1::Adc12sht1_2,
3 => Adc12sht1::Adc12sht1_3,
4 => Adc12sht1::Adc12sht1_4,
5 => Adc12sht1::Adc12sht1_5,
6 => Adc12sht1::Adc12sht1_6,
7 => Adc12sht1::Adc12sht1_7,
8 => Adc12sht1::Adc12sht1_8,
9 => Adc12sht1::Adc12sht1_9,
10 => Adc12sht1::Adc12sht1_10,
11 => Adc12sht1::Adc12sht1_11,
12 => Adc12sht1::Adc12sht1_12,
13 => Adc12sht1::Adc12sht1_13,
14 => Adc12sht1::Adc12sht1_14,
15 => Adc12sht1::Adc12sht1_15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 0"]
#[inline(always)]
pub fn is_adc12sht1_0(&self) -> bool {
*self == Adc12sht1::Adc12sht1_0
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 1"]
#[inline(always)]
pub fn is_adc12sht1_1(&self) -> bool {
*self == Adc12sht1::Adc12sht1_1
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 2"]
#[inline(always)]
pub fn is_adc12sht1_2(&self) -> bool {
*self == Adc12sht1::Adc12sht1_2
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 3"]
#[inline(always)]
pub fn is_adc12sht1_3(&self) -> bool {
*self == Adc12sht1::Adc12sht1_3
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 4"]
#[inline(always)]
pub fn is_adc12sht1_4(&self) -> bool {
*self == Adc12sht1::Adc12sht1_4
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 5"]
#[inline(always)]
pub fn is_adc12sht1_5(&self) -> bool {
*self == Adc12sht1::Adc12sht1_5
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 6"]
#[inline(always)]
pub fn is_adc12sht1_6(&self) -> bool {
*self == Adc12sht1::Adc12sht1_6
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 7"]
#[inline(always)]
pub fn is_adc12sht1_7(&self) -> bool {
*self == Adc12sht1::Adc12sht1_7
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 8"]
#[inline(always)]
pub fn is_adc12sht1_8(&self) -> bool {
*self == Adc12sht1::Adc12sht1_8
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 9"]
#[inline(always)]
pub fn is_adc12sht1_9(&self) -> bool {
*self == Adc12sht1::Adc12sht1_9
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 10"]
#[inline(always)]
pub fn is_adc12sht1_10(&self) -> bool {
*self == Adc12sht1::Adc12sht1_10
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 11"]
#[inline(always)]
pub fn is_adc12sht1_11(&self) -> bool {
*self == Adc12sht1::Adc12sht1_11
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 12"]
#[inline(always)]
pub fn is_adc12sht1_12(&self) -> bool {
*self == Adc12sht1::Adc12sht1_12
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 13"]
#[inline(always)]
pub fn is_adc12sht1_13(&self) -> bool {
*self == Adc12sht1::Adc12sht1_13
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 14"]
#[inline(always)]
pub fn is_adc12sht1_14(&self) -> bool {
*self == Adc12sht1::Adc12sht1_14
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 15"]
#[inline(always)]
pub fn is_adc12sht1_15(&self) -> bool {
*self == Adc12sht1::Adc12sht1_15
}
}
#[doc = "Field `ADC12SHT1` writer - ADC12 Sample Hold 1 Select Bit: 0"]
pub type Adc12sht1W<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12sht1, crate::Safe>;
impl<'a, REG> Adc12sht1W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Sample Hold 1 Select Bit: 0"]
#[inline(always)]
pub fn adc12sht1_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_0)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 1"]
#[inline(always)]
pub fn adc12sht1_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_1)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 2"]
#[inline(always)]
pub fn adc12sht1_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_2)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 3"]
#[inline(always)]
pub fn adc12sht1_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_3)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 4"]
#[inline(always)]
pub fn adc12sht1_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_4)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 5"]
#[inline(always)]
pub fn adc12sht1_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_5)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 6"]
#[inline(always)]
pub fn adc12sht1_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_6)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 7"]
#[inline(always)]
pub fn adc12sht1_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_7)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 8"]
#[inline(always)]
pub fn adc12sht1_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_8)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 9"]
#[inline(always)]
pub fn adc12sht1_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_9)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 10"]
#[inline(always)]
pub fn adc12sht1_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_10)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 11"]
#[inline(always)]
pub fn adc12sht1_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_11)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 12"]
#[inline(always)]
pub fn adc12sht1_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_12)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 13"]
#[inline(always)]
pub fn adc12sht1_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_13)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 14"]
#[inline(always)]
pub fn adc12sht1_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_14)
}
#[doc = "ADC12 Sample Hold 1 Select Bit: 15"]
#[inline(always)]
pub fn adc12sht1_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12sht1::Adc12sht1_15)
}
}
impl R {
#[doc = "Bit 0 - ADC12 Start Conversion"]
#[inline(always)]
pub fn adc12sc(&self) -> Adc12scR {
Adc12scR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - ADC12 Enable Conversion"]
#[inline(always)]
pub fn adc12enc(&self) -> Adc12encR {
Adc12encR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 4 - ADC12 On/enable"]
#[inline(always)]
pub fn adc12on(&self) -> Adc12onR {
Adc12onR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 7 - ADC12 Multiple SampleConversion"]
#[inline(always)]
pub fn adc12msc(&self) -> Adc12mscR {
Adc12mscR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 Sample Hold 0 Select Bit: 0"]
#[inline(always)]
pub fn adc12sht0(&self) -> Adc12sht0R {
Adc12sht0R::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bits 12:15 - ADC12 Sample Hold 1 Select Bit: 0"]
#[inline(always)]
pub fn adc12sht1(&self) -> Adc12sht1R {
Adc12sht1R::new(((self.bits >> 12) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bit 0 - ADC12 Start Conversion"]
#[inline(always)]
pub fn adc12sc(&mut self) -> Adc12scW<'_, Adc12ctl0Spec> {
Adc12scW::new(self, 0)
}
#[doc = "Bit 1 - ADC12 Enable Conversion"]
#[inline(always)]
pub fn adc12enc(&mut self) -> Adc12encW<'_, Adc12ctl0Spec> {
Adc12encW::new(self, 1)
}
#[doc = "Bit 4 - ADC12 On/enable"]
#[inline(always)]
pub fn adc12on(&mut self) -> Adc12onW<'_, Adc12ctl0Spec> {
Adc12onW::new(self, 4)
}
#[doc = "Bit 7 - ADC12 Multiple SampleConversion"]
#[inline(always)]
pub fn adc12msc(&mut self) -> Adc12mscW<'_, Adc12ctl0Spec> {
Adc12mscW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 Sample Hold 0 Select Bit: 0"]
#[inline(always)]
pub fn adc12sht0(&mut self) -> Adc12sht0W<'_, Adc12ctl0Spec> {
Adc12sht0W::new(self, 8)
}
#[doc = "Bits 12:15 - ADC12 Sample Hold 1 Select Bit: 0"]
#[inline(always)]
pub fn adc12sht1(&mut self) -> Adc12sht1W<'_, Adc12ctl0Spec> {
Adc12sht1W::new(self, 12)
}
}
#[doc = "ADC12 B Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12ctl0Spec;
impl crate::RegisterSpec for Adc12ctl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12ctl0::R`](R) reader structure"]
impl crate::Readable for Adc12ctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12ctl0::W`](W) writer structure"]
impl crate::Writable for Adc12ctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12CTL0 to value 0"]
impl crate::Resettable for Adc12ctl0Spec {}
}
#[doc = "ADC12CTL1 (rw) register accessor: ADC12 B Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ctl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ctl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12ctl1`] module"]
#[doc(alias = "ADC12CTL1")]
pub type Adc12ctl1 = crate::Reg<adc12ctl1::Adc12ctl1Spec>;
#[doc = "ADC12 B Control 1"]
pub mod adc12ctl1 {
#[doc = "Register `ADC12CTL1` reader"]
pub type R = crate::R<Adc12ctl1Spec>;
#[doc = "Register `ADC12CTL1` writer"]
pub type W = crate::W<Adc12ctl1Spec>;
#[doc = "Field `ADC12BUSY` reader - ADC12 Busy"]
pub type Adc12busyR = crate::BitReader;
#[doc = "Field `ADC12BUSY` writer - ADC12 Busy"]
pub type Adc12busyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 Conversion Sequence Select Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12conseq {
#[doc = "0: ADC12 Conversion Sequence Select: 0"]
Adc12conseq0 = 0,
#[doc = "1: ADC12 Conversion Sequence Select: 1"]
Adc12conseq1 = 1,
#[doc = "2: ADC12 Conversion Sequence Select: 2"]
Adc12conseq2 = 2,
#[doc = "3: ADC12 Conversion Sequence Select: 3"]
Adc12conseq3 = 3,
}
impl From<Adc12conseq> for u8 {
#[inline(always)]
fn from(variant: Adc12conseq) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12conseq {
type Ux = u8;
}
impl crate::IsEnum for Adc12conseq {}
#[doc = "Field `ADC12CONSEQ` reader - ADC12 Conversion Sequence Select Bit: 0"]
pub type Adc12conseqR = crate::FieldReader<Adc12conseq>;
impl Adc12conseqR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12conseq {
match self.bits {
0 => Adc12conseq::Adc12conseq0,
1 => Adc12conseq::Adc12conseq1,
2 => Adc12conseq::Adc12conseq2,
3 => Adc12conseq::Adc12conseq3,
_ => unreachable!(),
}
}
#[doc = "ADC12 Conversion Sequence Select: 0"]
#[inline(always)]
pub fn is_adc12conseq_0(&self) -> bool {
*self == Adc12conseq::Adc12conseq0
}
#[doc = "ADC12 Conversion Sequence Select: 1"]
#[inline(always)]
pub fn is_adc12conseq_1(&self) -> bool {
*self == Adc12conseq::Adc12conseq1
}
#[doc = "ADC12 Conversion Sequence Select: 2"]
#[inline(always)]
pub fn is_adc12conseq_2(&self) -> bool {
*self == Adc12conseq::Adc12conseq2
}
#[doc = "ADC12 Conversion Sequence Select: 3"]
#[inline(always)]
pub fn is_adc12conseq_3(&self) -> bool {
*self == Adc12conseq::Adc12conseq3
}
}
#[doc = "Field `ADC12CONSEQ` writer - ADC12 Conversion Sequence Select Bit: 0"]
pub type Adc12conseqW<'a, REG> = crate::FieldWriter<'a, REG, 2, Adc12conseq, crate::Safe>;
impl<'a, REG> Adc12conseqW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Conversion Sequence Select: 0"]
#[inline(always)]
pub fn adc12conseq_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12conseq::Adc12conseq0)
}
#[doc = "ADC12 Conversion Sequence Select: 1"]
#[inline(always)]
pub fn adc12conseq_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12conseq::Adc12conseq1)
}
#[doc = "ADC12 Conversion Sequence Select: 2"]
#[inline(always)]
pub fn adc12conseq_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12conseq::Adc12conseq2)
}
#[doc = "ADC12 Conversion Sequence Select: 3"]
#[inline(always)]
pub fn adc12conseq_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12conseq::Adc12conseq3)
}
}
#[doc = "ADC12 Clock Source Select Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12ssel {
#[doc = "0: ADC12 Clock Source Select: 0"]
Adc12ssel0 = 0,
#[doc = "1: ADC12 Clock Source Select: 1"]
Adc12ssel1 = 1,
#[doc = "2: ADC12 Clock Source Select: 2"]
Adc12ssel2 = 2,
#[doc = "3: ADC12 Clock Source Select: 3"]
Adc12ssel3 = 3,
}
impl From<Adc12ssel> for u8 {
#[inline(always)]
fn from(variant: Adc12ssel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12ssel {
type Ux = u8;
}
impl crate::IsEnum for Adc12ssel {}
#[doc = "Field `ADC12SSEL` reader - ADC12 Clock Source Select Bit: 0"]
pub type Adc12sselR = crate::FieldReader<Adc12ssel>;
impl Adc12sselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12ssel {
match self.bits {
0 => Adc12ssel::Adc12ssel0,
1 => Adc12ssel::Adc12ssel1,
2 => Adc12ssel::Adc12ssel2,
3 => Adc12ssel::Adc12ssel3,
_ => unreachable!(),
}
}
#[doc = "ADC12 Clock Source Select: 0"]
#[inline(always)]
pub fn is_adc12ssel_0(&self) -> bool {
*self == Adc12ssel::Adc12ssel0
}
#[doc = "ADC12 Clock Source Select: 1"]
#[inline(always)]
pub fn is_adc12ssel_1(&self) -> bool {
*self == Adc12ssel::Adc12ssel1
}
#[doc = "ADC12 Clock Source Select: 2"]
#[inline(always)]
pub fn is_adc12ssel_2(&self) -> bool {
*self == Adc12ssel::Adc12ssel2
}
#[doc = "ADC12 Clock Source Select: 3"]
#[inline(always)]
pub fn is_adc12ssel_3(&self) -> bool {
*self == Adc12ssel::Adc12ssel3
}
}
#[doc = "Field `ADC12SSEL` writer - ADC12 Clock Source Select Bit: 0"]
pub type Adc12sselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Adc12ssel, crate::Safe>;
impl<'a, REG> Adc12sselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Clock Source Select: 0"]
#[inline(always)]
pub fn adc12ssel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12ssel::Adc12ssel0)
}
#[doc = "ADC12 Clock Source Select: 1"]
#[inline(always)]
pub fn adc12ssel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12ssel::Adc12ssel1)
}
#[doc = "ADC12 Clock Source Select: 2"]
#[inline(always)]
pub fn adc12ssel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12ssel::Adc12ssel2)
}
#[doc = "ADC12 Clock Source Select: 3"]
#[inline(always)]
pub fn adc12ssel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12ssel::Adc12ssel3)
}
}
#[doc = "ADC12 Clock Divider Select Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12div {
#[doc = "0: ADC12 Clock Divider Select: 0"]
Adc12div0 = 0,
#[doc = "1: ADC12 Clock Divider Select: 1"]
Adc12div1 = 1,
#[doc = "2: ADC12 Clock Divider Select: 2"]
Adc12div2 = 2,
#[doc = "3: ADC12 Clock Divider Select: 3"]
Adc12div3 = 3,
#[doc = "4: ADC12 Clock Divider Select: 4"]
Adc12div4 = 4,
#[doc = "5: ADC12 Clock Divider Select: 5"]
Adc12div5 = 5,
#[doc = "6: ADC12 Clock Divider Select: 6"]
Adc12div6 = 6,
#[doc = "7: ADC12 Clock Divider Select: 7"]
Adc12div7 = 7,
}
impl From<Adc12div> for u8 {
#[inline(always)]
fn from(variant: Adc12div) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12div {
type Ux = u8;
}
impl crate::IsEnum for Adc12div {}
#[doc = "Field `ADC12DIV` reader - ADC12 Clock Divider Select Bit: 0"]
pub type Adc12divR = crate::FieldReader<Adc12div>;
impl Adc12divR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12div {
match self.bits {
0 => Adc12div::Adc12div0,
1 => Adc12div::Adc12div1,
2 => Adc12div::Adc12div2,
3 => Adc12div::Adc12div3,
4 => Adc12div::Adc12div4,
5 => Adc12div::Adc12div5,
6 => Adc12div::Adc12div6,
7 => Adc12div::Adc12div7,
_ => unreachable!(),
}
}
#[doc = "ADC12 Clock Divider Select: 0"]
#[inline(always)]
pub fn is_adc12div_0(&self) -> bool {
*self == Adc12div::Adc12div0
}
#[doc = "ADC12 Clock Divider Select: 1"]
#[inline(always)]
pub fn is_adc12div_1(&self) -> bool {
*self == Adc12div::Adc12div1
}
#[doc = "ADC12 Clock Divider Select: 2"]
#[inline(always)]
pub fn is_adc12div_2(&self) -> bool {
*self == Adc12div::Adc12div2
}
#[doc = "ADC12 Clock Divider Select: 3"]
#[inline(always)]
pub fn is_adc12div_3(&self) -> bool {
*self == Adc12div::Adc12div3
}
#[doc = "ADC12 Clock Divider Select: 4"]
#[inline(always)]
pub fn is_adc12div_4(&self) -> bool {
*self == Adc12div::Adc12div4
}
#[doc = "ADC12 Clock Divider Select: 5"]
#[inline(always)]
pub fn is_adc12div_5(&self) -> bool {
*self == Adc12div::Adc12div5
}
#[doc = "ADC12 Clock Divider Select: 6"]
#[inline(always)]
pub fn is_adc12div_6(&self) -> bool {
*self == Adc12div::Adc12div6
}
#[doc = "ADC12 Clock Divider Select: 7"]
#[inline(always)]
pub fn is_adc12div_7(&self) -> bool {
*self == Adc12div::Adc12div7
}
}
#[doc = "Field `ADC12DIV` writer - ADC12 Clock Divider Select Bit: 0"]
pub type Adc12divW<'a, REG> = crate::FieldWriter<'a, REG, 3, Adc12div, crate::Safe>;
impl<'a, REG> Adc12divW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Clock Divider Select: 0"]
#[inline(always)]
pub fn adc12div_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12div::Adc12div0)
}
#[doc = "ADC12 Clock Divider Select: 1"]
#[inline(always)]
pub fn adc12div_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12div::Adc12div1)
}
#[doc = "ADC12 Clock Divider Select: 2"]
#[inline(always)]
pub fn adc12div_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12div::Adc12div2)
}
#[doc = "ADC12 Clock Divider Select: 3"]
#[inline(always)]
pub fn adc12div_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12div::Adc12div3)
}
#[doc = "ADC12 Clock Divider Select: 4"]
#[inline(always)]
pub fn adc12div_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12div::Adc12div4)
}
#[doc = "ADC12 Clock Divider Select: 5"]
#[inline(always)]
pub fn adc12div_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12div::Adc12div5)
}
#[doc = "ADC12 Clock Divider Select: 6"]
#[inline(always)]
pub fn adc12div_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12div::Adc12div6)
}
#[doc = "ADC12 Clock Divider Select: 7"]
#[inline(always)]
pub fn adc12div_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12div::Adc12div7)
}
}
#[doc = "Field `ADC12ISSH` reader - ADC12 Invert Sample Hold Signal"]
pub type Adc12isshR = crate::BitReader;
#[doc = "Field `ADC12ISSH` writer - ADC12 Invert Sample Hold Signal"]
pub type Adc12isshW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12SHP` reader - ADC12 Sample/Hold Pulse Mode"]
pub type Adc12shpR = crate::BitReader;
#[doc = "Field `ADC12SHP` writer - ADC12 Sample/Hold Pulse Mode"]
pub type Adc12shpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 Sample/Hold Source Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12shs {
#[doc = "0: ADC12 Sample/Hold Source: 0"]
Adc12shs0 = 0,
#[doc = "1: ADC12 Sample/Hold Source: 1"]
Adc12shs1 = 1,
#[doc = "2: ADC12 Sample/Hold Source: 2"]
Adc12shs2 = 2,
#[doc = "3: ADC12 Sample/Hold Source: 3"]
Adc12shs3 = 3,
#[doc = "4: ADC12 Sample/Hold Source: 4"]
Adc12shs4 = 4,
#[doc = "5: ADC12 Sample/Hold Source: 5"]
Adc12shs5 = 5,
#[doc = "6: ADC12 Sample/Hold Source: 6"]
Adc12shs6 = 6,
#[doc = "7: ADC12 Sample/Hold Source: 7"]
Adc12shs7 = 7,
}
impl From<Adc12shs> for u8 {
#[inline(always)]
fn from(variant: Adc12shs) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12shs {
type Ux = u8;
}
impl crate::IsEnum for Adc12shs {}
#[doc = "Field `ADC12SHS` reader - ADC12 Sample/Hold Source Bit: 0"]
pub type Adc12shsR = crate::FieldReader<Adc12shs>;
impl Adc12shsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12shs {
match self.bits {
0 => Adc12shs::Adc12shs0,
1 => Adc12shs::Adc12shs1,
2 => Adc12shs::Adc12shs2,
3 => Adc12shs::Adc12shs3,
4 => Adc12shs::Adc12shs4,
5 => Adc12shs::Adc12shs5,
6 => Adc12shs::Adc12shs6,
7 => Adc12shs::Adc12shs7,
_ => unreachable!(),
}
}
#[doc = "ADC12 Sample/Hold Source: 0"]
#[inline(always)]
pub fn is_adc12shs_0(&self) -> bool {
*self == Adc12shs::Adc12shs0
}
#[doc = "ADC12 Sample/Hold Source: 1"]
#[inline(always)]
pub fn is_adc12shs_1(&self) -> bool {
*self == Adc12shs::Adc12shs1
}
#[doc = "ADC12 Sample/Hold Source: 2"]
#[inline(always)]
pub fn is_adc12shs_2(&self) -> bool {
*self == Adc12shs::Adc12shs2
}
#[doc = "ADC12 Sample/Hold Source: 3"]
#[inline(always)]
pub fn is_adc12shs_3(&self) -> bool {
*self == Adc12shs::Adc12shs3
}
#[doc = "ADC12 Sample/Hold Source: 4"]
#[inline(always)]
pub fn is_adc12shs_4(&self) -> bool {
*self == Adc12shs::Adc12shs4
}
#[doc = "ADC12 Sample/Hold Source: 5"]
#[inline(always)]
pub fn is_adc12shs_5(&self) -> bool {
*self == Adc12shs::Adc12shs5
}
#[doc = "ADC12 Sample/Hold Source: 6"]
#[inline(always)]
pub fn is_adc12shs_6(&self) -> bool {
*self == Adc12shs::Adc12shs6
}
#[doc = "ADC12 Sample/Hold Source: 7"]
#[inline(always)]
pub fn is_adc12shs_7(&self) -> bool {
*self == Adc12shs::Adc12shs7
}
}
#[doc = "Field `ADC12SHS` writer - ADC12 Sample/Hold Source Bit: 0"]
pub type Adc12shsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Adc12shs, crate::Safe>;
impl<'a, REG> Adc12shsW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Sample/Hold Source: 0"]
#[inline(always)]
pub fn adc12shs_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12shs::Adc12shs0)
}
#[doc = "ADC12 Sample/Hold Source: 1"]
#[inline(always)]
pub fn adc12shs_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12shs::Adc12shs1)
}
#[doc = "ADC12 Sample/Hold Source: 2"]
#[inline(always)]
pub fn adc12shs_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12shs::Adc12shs2)
}
#[doc = "ADC12 Sample/Hold Source: 3"]
#[inline(always)]
pub fn adc12shs_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12shs::Adc12shs3)
}
#[doc = "ADC12 Sample/Hold Source: 4"]
#[inline(always)]
pub fn adc12shs_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12shs::Adc12shs4)
}
#[doc = "ADC12 Sample/Hold Source: 5"]
#[inline(always)]
pub fn adc12shs_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12shs::Adc12shs5)
}
#[doc = "ADC12 Sample/Hold Source: 6"]
#[inline(always)]
pub fn adc12shs_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12shs::Adc12shs6)
}
#[doc = "ADC12 Sample/Hold Source: 7"]
#[inline(always)]
pub fn adc12shs_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12shs::Adc12shs7)
}
}
#[doc = "ADC12 Predivider Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12pdiv {
#[doc = "0: ADC12 Clock predivider Select 0"]
Adc12pdiv0 = 0,
#[doc = "1: ADC12 Clock predivider Select 1"]
Adc12pdiv1 = 1,
#[doc = "2: ADC12 Clock predivider Select 2"]
Adc12pdiv2 = 2,
#[doc = "3: ADC12 Clock predivider Select 3"]
Adc12pdiv3 = 3,
}
impl From<Adc12pdiv> for u8 {
#[inline(always)]
fn from(variant: Adc12pdiv) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12pdiv {
type Ux = u8;
}
impl crate::IsEnum for Adc12pdiv {}
#[doc = "Field `ADC12PDIV` reader - ADC12 Predivider Bit: 0"]
pub type Adc12pdivR = crate::FieldReader<Adc12pdiv>;
impl Adc12pdivR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12pdiv {
match self.bits {
0 => Adc12pdiv::Adc12pdiv0,
1 => Adc12pdiv::Adc12pdiv1,
2 => Adc12pdiv::Adc12pdiv2,
3 => Adc12pdiv::Adc12pdiv3,
_ => unreachable!(),
}
}
#[doc = "ADC12 Clock predivider Select 0"]
#[inline(always)]
pub fn is_adc12pdiv_0(&self) -> bool {
*self == Adc12pdiv::Adc12pdiv0
}
#[doc = "ADC12 Clock predivider Select 1"]
#[inline(always)]
pub fn is_adc12pdiv_1(&self) -> bool {
*self == Adc12pdiv::Adc12pdiv1
}
#[doc = "ADC12 Clock predivider Select 2"]
#[inline(always)]
pub fn is_adc12pdiv_2(&self) -> bool {
*self == Adc12pdiv::Adc12pdiv2
}
#[doc = "ADC12 Clock predivider Select 3"]
#[inline(always)]
pub fn is_adc12pdiv_3(&self) -> bool {
*self == Adc12pdiv::Adc12pdiv3
}
}
#[doc = "Field `ADC12PDIV` writer - ADC12 Predivider Bit: 0"]
pub type Adc12pdivW<'a, REG> = crate::FieldWriter<'a, REG, 2, Adc12pdiv, crate::Safe>;
impl<'a, REG> Adc12pdivW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Clock predivider Select 0"]
#[inline(always)]
pub fn adc12pdiv_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12pdiv::Adc12pdiv0)
}
#[doc = "ADC12 Clock predivider Select 1"]
#[inline(always)]
pub fn adc12pdiv_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12pdiv::Adc12pdiv1)
}
#[doc = "ADC12 Clock predivider Select 2"]
#[inline(always)]
pub fn adc12pdiv_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12pdiv::Adc12pdiv2)
}
#[doc = "ADC12 Clock predivider Select 3"]
#[inline(always)]
pub fn adc12pdiv_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12pdiv::Adc12pdiv3)
}
}
impl R {
#[doc = "Bit 0 - ADC12 Busy"]
#[inline(always)]
pub fn adc12busy(&self) -> Adc12busyR {
Adc12busyR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2 - ADC12 Conversion Sequence Select Bit: 0"]
#[inline(always)]
pub fn adc12conseq(&self) -> Adc12conseqR {
Adc12conseqR::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bits 3:4 - ADC12 Clock Source Select Bit: 0"]
#[inline(always)]
pub fn adc12ssel(&self) -> Adc12sselR {
Adc12sselR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bits 5:7 - ADC12 Clock Divider Select Bit: 0"]
#[inline(always)]
pub fn adc12div(&self) -> Adc12divR {
Adc12divR::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bit 8 - ADC12 Invert Sample Hold Signal"]
#[inline(always)]
pub fn adc12issh(&self) -> Adc12isshR {
Adc12isshR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - ADC12 Sample/Hold Pulse Mode"]
#[inline(always)]
pub fn adc12shp(&self) -> Adc12shpR {
Adc12shpR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:12 - ADC12 Sample/Hold Source Bit: 0"]
#[inline(always)]
pub fn adc12shs(&self) -> Adc12shsR {
Adc12shsR::new(((self.bits >> 10) & 7) as u8)
}
#[doc = "Bits 13:14 - ADC12 Predivider Bit: 0"]
#[inline(always)]
pub fn adc12pdiv(&self) -> Adc12pdivR {
Adc12pdivR::new(((self.bits >> 13) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - ADC12 Busy"]
#[inline(always)]
pub fn adc12busy(&mut self) -> Adc12busyW<'_, Adc12ctl1Spec> {
Adc12busyW::new(self, 0)
}
#[doc = "Bits 1:2 - ADC12 Conversion Sequence Select Bit: 0"]
#[inline(always)]
pub fn adc12conseq(&mut self) -> Adc12conseqW<'_, Adc12ctl1Spec> {
Adc12conseqW::new(self, 1)
}
#[doc = "Bits 3:4 - ADC12 Clock Source Select Bit: 0"]
#[inline(always)]
pub fn adc12ssel(&mut self) -> Adc12sselW<'_, Adc12ctl1Spec> {
Adc12sselW::new(self, 3)
}
#[doc = "Bits 5:7 - ADC12 Clock Divider Select Bit: 0"]
#[inline(always)]
pub fn adc12div(&mut self) -> Adc12divW<'_, Adc12ctl1Spec> {
Adc12divW::new(self, 5)
}
#[doc = "Bit 8 - ADC12 Invert Sample Hold Signal"]
#[inline(always)]
pub fn adc12issh(&mut self) -> Adc12isshW<'_, Adc12ctl1Spec> {
Adc12isshW::new(self, 8)
}
#[doc = "Bit 9 - ADC12 Sample/Hold Pulse Mode"]
#[inline(always)]
pub fn adc12shp(&mut self) -> Adc12shpW<'_, Adc12ctl1Spec> {
Adc12shpW::new(self, 9)
}
#[doc = "Bits 10:12 - ADC12 Sample/Hold Source Bit: 0"]
#[inline(always)]
pub fn adc12shs(&mut self) -> Adc12shsW<'_, Adc12ctl1Spec> {
Adc12shsW::new(self, 10)
}
#[doc = "Bits 13:14 - ADC12 Predivider Bit: 0"]
#[inline(always)]
pub fn adc12pdiv(&mut self) -> Adc12pdivW<'_, Adc12ctl1Spec> {
Adc12pdivW::new(self, 13)
}
}
#[doc = "ADC12 B Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12ctl1Spec;
impl crate::RegisterSpec for Adc12ctl1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12ctl1::R`](R) reader structure"]
impl crate::Readable for Adc12ctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12ctl1::W`](W) writer structure"]
impl crate::Writable for Adc12ctl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12CTL1 to value 0"]
impl crate::Resettable for Adc12ctl1Spec {}
}
#[doc = "ADC12CTL2 (rw) register accessor: ADC12 B Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ctl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ctl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12ctl2`] module"]
#[doc(alias = "ADC12CTL2")]
pub type Adc12ctl2 = crate::Reg<adc12ctl2::Adc12ctl2Spec>;
#[doc = "ADC12 B Control 2"]
pub mod adc12ctl2 {
#[doc = "Register `ADC12CTL2` reader"]
pub type R = crate::R<Adc12ctl2Spec>;
#[doc = "Register `ADC12CTL2` writer"]
pub type W = crate::W<Adc12ctl2Spec>;
#[doc = "Field `ADC12PWRMD` reader - ADC12 Power Mode"]
pub type Adc12pwrmdR = crate::BitReader;
#[doc = "Field `ADC12PWRMD` writer - ADC12 Power Mode"]
pub type Adc12pwrmdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12DF` reader - ADC12 Data Format"]
pub type Adc12dfR = crate::BitReader;
#[doc = "Field `ADC12DF` writer - ADC12 Data Format"]
pub type Adc12dfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 Resolution Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12res {
#[doc = "0: ADC12+ Resolution : 8 Bit"]
Adc12res0 = 0,
#[doc = "1: ADC12+ Resolution : 10 Bit"]
Adc12res1 = 1,
#[doc = "2: ADC12+ Resolution : 12 Bit"]
Adc12res2 = 2,
#[doc = "3: ADC12+ Resolution : reserved"]
Adc12res3 = 3,
}
impl From<Adc12res> for u8 {
#[inline(always)]
fn from(variant: Adc12res) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12res {
type Ux = u8;
}
impl crate::IsEnum for Adc12res {}
#[doc = "Field `ADC12RES` reader - ADC12 Resolution Bit: 0"]
pub type Adc12resR = crate::FieldReader<Adc12res>;
impl Adc12resR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12res {
match self.bits {
0 => Adc12res::Adc12res0,
1 => Adc12res::Adc12res1,
2 => Adc12res::Adc12res2,
3 => Adc12res::Adc12res3,
_ => unreachable!(),
}
}
#[doc = "ADC12+ Resolution : 8 Bit"]
#[inline(always)]
pub fn is_adc12res_0(&self) -> bool {
*self == Adc12res::Adc12res0
}
#[doc = "ADC12+ Resolution : 10 Bit"]
#[inline(always)]
pub fn is_adc12res_1(&self) -> bool {
*self == Adc12res::Adc12res1
}
#[doc = "ADC12+ Resolution : 12 Bit"]
#[inline(always)]
pub fn is_adc12res_2(&self) -> bool {
*self == Adc12res::Adc12res2
}
#[doc = "ADC12+ Resolution : reserved"]
#[inline(always)]
pub fn is_adc12res_3(&self) -> bool {
*self == Adc12res::Adc12res3
}
}
#[doc = "Field `ADC12RES` writer - ADC12 Resolution Bit: 0"]
pub type Adc12resW<'a, REG> = crate::FieldWriter<'a, REG, 2, Adc12res, crate::Safe>;
impl<'a, REG> Adc12resW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12+ Resolution : 8 Bit"]
#[inline(always)]
pub fn adc12res_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12res::Adc12res0)
}
#[doc = "ADC12+ Resolution : 10 Bit"]
#[inline(always)]
pub fn adc12res_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12res::Adc12res1)
}
#[doc = "ADC12+ Resolution : 12 Bit"]
#[inline(always)]
pub fn adc12res_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12res::Adc12res2)
}
#[doc = "ADC12+ Resolution : reserved"]
#[inline(always)]
pub fn adc12res_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12res::Adc12res3)
}
}
impl R {
#[doc = "Bit 0 - ADC12 Power Mode"]
#[inline(always)]
pub fn adc12pwrmd(&self) -> Adc12pwrmdR {
Adc12pwrmdR::new((self.bits & 1) != 0)
}
#[doc = "Bit 3 - ADC12 Data Format"]
#[inline(always)]
pub fn adc12df(&self) -> Adc12dfR {
Adc12dfR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:5 - ADC12 Resolution Bit: 0"]
#[inline(always)]
pub fn adc12res(&self) -> Adc12resR {
Adc12resR::new(((self.bits >> 4) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - ADC12 Power Mode"]
#[inline(always)]
pub fn adc12pwrmd(&mut self) -> Adc12pwrmdW<'_, Adc12ctl2Spec> {
Adc12pwrmdW::new(self, 0)
}
#[doc = "Bit 3 - ADC12 Data Format"]
#[inline(always)]
pub fn adc12df(&mut self) -> Adc12dfW<'_, Adc12ctl2Spec> {
Adc12dfW::new(self, 3)
}
#[doc = "Bits 4:5 - ADC12 Resolution Bit: 0"]
#[inline(always)]
pub fn adc12res(&mut self) -> Adc12resW<'_, Adc12ctl2Spec> {
Adc12resW::new(self, 4)
}
}
#[doc = "ADC12 B Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ctl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ctl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12ctl2Spec;
impl crate::RegisterSpec for Adc12ctl2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12ctl2::R`](R) reader structure"]
impl crate::Readable for Adc12ctl2Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12ctl2::W`](W) writer structure"]
impl crate::Writable for Adc12ctl2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12CTL2 to value 0"]
impl crate::Resettable for Adc12ctl2Spec {}
}
#[doc = "ADC12CTL3 (rw) register accessor: ADC12 B Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ctl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ctl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12ctl3`] module"]
#[doc(alias = "ADC12CTL3")]
pub type Adc12ctl3 = crate::Reg<adc12ctl3::Adc12ctl3Spec>;
#[doc = "ADC12 B Control 3"]
pub mod adc12ctl3 {
#[doc = "Register `ADC12CTL3` reader"]
pub type R = crate::R<Adc12ctl3Spec>;
#[doc = "Register `ADC12CTL3` writer"]
pub type W = crate::W<Adc12ctl3Spec>;
#[doc = "ADC12 Conversion Start Address Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12cstartadd {
#[doc = "0: ADC12 Conversion Start Address: 0"]
Adc12cstartadd0 = 0,
#[doc = "1: ADC12 Conversion Start Address: 1"]
Adc12cstartadd1 = 1,
#[doc = "2: ADC12 Conversion Start Address: 2"]
Adc12cstartadd2 = 2,
#[doc = "3: ADC12 Conversion Start Address: 3"]
Adc12cstartadd3 = 3,
#[doc = "4: ADC12 Conversion Start Address: 4"]
Adc12cstartadd4 = 4,
#[doc = "5: ADC12 Conversion Start Address: 5"]
Adc12cstartadd5 = 5,
#[doc = "6: ADC12 Conversion Start Address: 6"]
Adc12cstartadd6 = 6,
#[doc = "7: ADC12 Conversion Start Address: 7"]
Adc12cstartadd7 = 7,
#[doc = "8: ADC12 Conversion Start Address: 8"]
Adc12cstartadd8 = 8,
#[doc = "9: ADC12 Conversion Start Address: 9"]
Adc12cstartadd9 = 9,
#[doc = "10: ADC12 Conversion Start Address: 10"]
Adc12cstartadd10 = 10,
#[doc = "11: ADC12 Conversion Start Address: 11"]
Adc12cstartadd11 = 11,
#[doc = "12: ADC12 Conversion Start Address: 12"]
Adc12cstartadd12 = 12,
#[doc = "13: ADC12 Conversion Start Address: 13"]
Adc12cstartadd13 = 13,
#[doc = "14: ADC12 Conversion Start Address: 14"]
Adc12cstartadd14 = 14,
#[doc = "15: ADC12 Conversion Start Address: 15"]
Adc12cstartadd15 = 15,
#[doc = "16: ADC12 Conversion Start Address: 16"]
Adc12cstartadd16 = 16,
#[doc = "17: ADC12 Conversion Start Address: 17"]
Adc12cstartadd17 = 17,
#[doc = "18: ADC12 Conversion Start Address: 18"]
Adc12cstartadd18 = 18,
#[doc = "19: ADC12 Conversion Start Address: 19"]
Adc12cstartadd19 = 19,
#[doc = "20: ADC12 Conversion Start Address: 20"]
Adc12cstartadd20 = 20,
#[doc = "21: ADC12 Conversion Start Address: 21"]
Adc12cstartadd21 = 21,
#[doc = "22: ADC12 Conversion Start Address: 22"]
Adc12cstartadd22 = 22,
#[doc = "23: ADC12 Conversion Start Address: 23"]
Adc12cstartadd23 = 23,
#[doc = "24: ADC12 Conversion Start Address: 24"]
Adc12cstartadd24 = 24,
#[doc = "25: ADC12 Conversion Start Address: 25"]
Adc12cstartadd25 = 25,
#[doc = "26: ADC12 Conversion Start Address: 26"]
Adc12cstartadd26 = 26,
#[doc = "27: ADC12 Conversion Start Address: 27"]
Adc12cstartadd27 = 27,
#[doc = "28: ADC12 Conversion Start Address: 28"]
Adc12cstartadd28 = 28,
#[doc = "29: ADC12 Conversion Start Address: 29"]
Adc12cstartadd29 = 29,
#[doc = "30: ADC12 Conversion Start Address: 30"]
Adc12cstartadd30 = 30,
#[doc = "31: ADC12 Conversion Start Address: 31"]
Adc12cstartadd31 = 31,
}
impl From<Adc12cstartadd> for u8 {
#[inline(always)]
fn from(variant: Adc12cstartadd) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12cstartadd {
type Ux = u8;
}
impl crate::IsEnum for Adc12cstartadd {}
#[doc = "Field `ADC12CSTARTADD` reader - ADC12 Conversion Start Address Bit: 0"]
pub type Adc12cstartaddR = crate::FieldReader<Adc12cstartadd>;
impl Adc12cstartaddR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12cstartadd {
match self.bits {
0 => Adc12cstartadd::Adc12cstartadd0,
1 => Adc12cstartadd::Adc12cstartadd1,
2 => Adc12cstartadd::Adc12cstartadd2,
3 => Adc12cstartadd::Adc12cstartadd3,
4 => Adc12cstartadd::Adc12cstartadd4,
5 => Adc12cstartadd::Adc12cstartadd5,
6 => Adc12cstartadd::Adc12cstartadd6,
7 => Adc12cstartadd::Adc12cstartadd7,
8 => Adc12cstartadd::Adc12cstartadd8,
9 => Adc12cstartadd::Adc12cstartadd9,
10 => Adc12cstartadd::Adc12cstartadd10,
11 => Adc12cstartadd::Adc12cstartadd11,
12 => Adc12cstartadd::Adc12cstartadd12,
13 => Adc12cstartadd::Adc12cstartadd13,
14 => Adc12cstartadd::Adc12cstartadd14,
15 => Adc12cstartadd::Adc12cstartadd15,
16 => Adc12cstartadd::Adc12cstartadd16,
17 => Adc12cstartadd::Adc12cstartadd17,
18 => Adc12cstartadd::Adc12cstartadd18,
19 => Adc12cstartadd::Adc12cstartadd19,
20 => Adc12cstartadd::Adc12cstartadd20,
21 => Adc12cstartadd::Adc12cstartadd21,
22 => Adc12cstartadd::Adc12cstartadd22,
23 => Adc12cstartadd::Adc12cstartadd23,
24 => Adc12cstartadd::Adc12cstartadd24,
25 => Adc12cstartadd::Adc12cstartadd25,
26 => Adc12cstartadd::Adc12cstartadd26,
27 => Adc12cstartadd::Adc12cstartadd27,
28 => Adc12cstartadd::Adc12cstartadd28,
29 => Adc12cstartadd::Adc12cstartadd29,
30 => Adc12cstartadd::Adc12cstartadd30,
31 => Adc12cstartadd::Adc12cstartadd31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Conversion Start Address: 0"]
#[inline(always)]
pub fn is_adc12cstartadd_0(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd0
}
#[doc = "ADC12 Conversion Start Address: 1"]
#[inline(always)]
pub fn is_adc12cstartadd_1(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd1
}
#[doc = "ADC12 Conversion Start Address: 2"]
#[inline(always)]
pub fn is_adc12cstartadd_2(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd2
}
#[doc = "ADC12 Conversion Start Address: 3"]
#[inline(always)]
pub fn is_adc12cstartadd_3(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd3
}
#[doc = "ADC12 Conversion Start Address: 4"]
#[inline(always)]
pub fn is_adc12cstartadd_4(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd4
}
#[doc = "ADC12 Conversion Start Address: 5"]
#[inline(always)]
pub fn is_adc12cstartadd_5(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd5
}
#[doc = "ADC12 Conversion Start Address: 6"]
#[inline(always)]
pub fn is_adc12cstartadd_6(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd6
}
#[doc = "ADC12 Conversion Start Address: 7"]
#[inline(always)]
pub fn is_adc12cstartadd_7(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd7
}
#[doc = "ADC12 Conversion Start Address: 8"]
#[inline(always)]
pub fn is_adc12cstartadd_8(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd8
}
#[doc = "ADC12 Conversion Start Address: 9"]
#[inline(always)]
pub fn is_adc12cstartadd_9(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd9
}
#[doc = "ADC12 Conversion Start Address: 10"]
#[inline(always)]
pub fn is_adc12cstartadd_10(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd10
}
#[doc = "ADC12 Conversion Start Address: 11"]
#[inline(always)]
pub fn is_adc12cstartadd_11(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd11
}
#[doc = "ADC12 Conversion Start Address: 12"]
#[inline(always)]
pub fn is_adc12cstartadd_12(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd12
}
#[doc = "ADC12 Conversion Start Address: 13"]
#[inline(always)]
pub fn is_adc12cstartadd_13(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd13
}
#[doc = "ADC12 Conversion Start Address: 14"]
#[inline(always)]
pub fn is_adc12cstartadd_14(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd14
}
#[doc = "ADC12 Conversion Start Address: 15"]
#[inline(always)]
pub fn is_adc12cstartadd_15(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd15
}
#[doc = "ADC12 Conversion Start Address: 16"]
#[inline(always)]
pub fn is_adc12cstartadd_16(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd16
}
#[doc = "ADC12 Conversion Start Address: 17"]
#[inline(always)]
pub fn is_adc12cstartadd_17(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd17
}
#[doc = "ADC12 Conversion Start Address: 18"]
#[inline(always)]
pub fn is_adc12cstartadd_18(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd18
}
#[doc = "ADC12 Conversion Start Address: 19"]
#[inline(always)]
pub fn is_adc12cstartadd_19(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd19
}
#[doc = "ADC12 Conversion Start Address: 20"]
#[inline(always)]
pub fn is_adc12cstartadd_20(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd20
}
#[doc = "ADC12 Conversion Start Address: 21"]
#[inline(always)]
pub fn is_adc12cstartadd_21(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd21
}
#[doc = "ADC12 Conversion Start Address: 22"]
#[inline(always)]
pub fn is_adc12cstartadd_22(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd22
}
#[doc = "ADC12 Conversion Start Address: 23"]
#[inline(always)]
pub fn is_adc12cstartadd_23(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd23
}
#[doc = "ADC12 Conversion Start Address: 24"]
#[inline(always)]
pub fn is_adc12cstartadd_24(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd24
}
#[doc = "ADC12 Conversion Start Address: 25"]
#[inline(always)]
pub fn is_adc12cstartadd_25(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd25
}
#[doc = "ADC12 Conversion Start Address: 26"]
#[inline(always)]
pub fn is_adc12cstartadd_26(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd26
}
#[doc = "ADC12 Conversion Start Address: 27"]
#[inline(always)]
pub fn is_adc12cstartadd_27(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd27
}
#[doc = "ADC12 Conversion Start Address: 28"]
#[inline(always)]
pub fn is_adc12cstartadd_28(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd28
}
#[doc = "ADC12 Conversion Start Address: 29"]
#[inline(always)]
pub fn is_adc12cstartadd_29(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd29
}
#[doc = "ADC12 Conversion Start Address: 30"]
#[inline(always)]
pub fn is_adc12cstartadd_30(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd30
}
#[doc = "ADC12 Conversion Start Address: 31"]
#[inline(always)]
pub fn is_adc12cstartadd_31(&self) -> bool {
*self == Adc12cstartadd::Adc12cstartadd31
}
}
#[doc = "Field `ADC12CSTARTADD` writer - ADC12 Conversion Start Address Bit: 0"]
pub type Adc12cstartaddW<'a, REG> =
crate::FieldWriter<'a, REG, 5, Adc12cstartadd, crate::Safe>;
impl<'a, REG> Adc12cstartaddW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Conversion Start Address: 0"]
#[inline(always)]
pub fn adc12cstartadd_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd0)
}
#[doc = "ADC12 Conversion Start Address: 1"]
#[inline(always)]
pub fn adc12cstartadd_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd1)
}
#[doc = "ADC12 Conversion Start Address: 2"]
#[inline(always)]
pub fn adc12cstartadd_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd2)
}
#[doc = "ADC12 Conversion Start Address: 3"]
#[inline(always)]
pub fn adc12cstartadd_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd3)
}
#[doc = "ADC12 Conversion Start Address: 4"]
#[inline(always)]
pub fn adc12cstartadd_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd4)
}
#[doc = "ADC12 Conversion Start Address: 5"]
#[inline(always)]
pub fn adc12cstartadd_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd5)
}
#[doc = "ADC12 Conversion Start Address: 6"]
#[inline(always)]
pub fn adc12cstartadd_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd6)
}
#[doc = "ADC12 Conversion Start Address: 7"]
#[inline(always)]
pub fn adc12cstartadd_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd7)
}
#[doc = "ADC12 Conversion Start Address: 8"]
#[inline(always)]
pub fn adc12cstartadd_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd8)
}
#[doc = "ADC12 Conversion Start Address: 9"]
#[inline(always)]
pub fn adc12cstartadd_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd9)
}
#[doc = "ADC12 Conversion Start Address: 10"]
#[inline(always)]
pub fn adc12cstartadd_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd10)
}
#[doc = "ADC12 Conversion Start Address: 11"]
#[inline(always)]
pub fn adc12cstartadd_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd11)
}
#[doc = "ADC12 Conversion Start Address: 12"]
#[inline(always)]
pub fn adc12cstartadd_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd12)
}
#[doc = "ADC12 Conversion Start Address: 13"]
#[inline(always)]
pub fn adc12cstartadd_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd13)
}
#[doc = "ADC12 Conversion Start Address: 14"]
#[inline(always)]
pub fn adc12cstartadd_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd14)
}
#[doc = "ADC12 Conversion Start Address: 15"]
#[inline(always)]
pub fn adc12cstartadd_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd15)
}
#[doc = "ADC12 Conversion Start Address: 16"]
#[inline(always)]
pub fn adc12cstartadd_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd16)
}
#[doc = "ADC12 Conversion Start Address: 17"]
#[inline(always)]
pub fn adc12cstartadd_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd17)
}
#[doc = "ADC12 Conversion Start Address: 18"]
#[inline(always)]
pub fn adc12cstartadd_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd18)
}
#[doc = "ADC12 Conversion Start Address: 19"]
#[inline(always)]
pub fn adc12cstartadd_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd19)
}
#[doc = "ADC12 Conversion Start Address: 20"]
#[inline(always)]
pub fn adc12cstartadd_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd20)
}
#[doc = "ADC12 Conversion Start Address: 21"]
#[inline(always)]
pub fn adc12cstartadd_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd21)
}
#[doc = "ADC12 Conversion Start Address: 22"]
#[inline(always)]
pub fn adc12cstartadd_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd22)
}
#[doc = "ADC12 Conversion Start Address: 23"]
#[inline(always)]
pub fn adc12cstartadd_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd23)
}
#[doc = "ADC12 Conversion Start Address: 24"]
#[inline(always)]
pub fn adc12cstartadd_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd24)
}
#[doc = "ADC12 Conversion Start Address: 25"]
#[inline(always)]
pub fn adc12cstartadd_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd25)
}
#[doc = "ADC12 Conversion Start Address: 26"]
#[inline(always)]
pub fn adc12cstartadd_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd26)
}
#[doc = "ADC12 Conversion Start Address: 27"]
#[inline(always)]
pub fn adc12cstartadd_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd27)
}
#[doc = "ADC12 Conversion Start Address: 28"]
#[inline(always)]
pub fn adc12cstartadd_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd28)
}
#[doc = "ADC12 Conversion Start Address: 29"]
#[inline(always)]
pub fn adc12cstartadd_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd29)
}
#[doc = "ADC12 Conversion Start Address: 30"]
#[inline(always)]
pub fn adc12cstartadd_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd30)
}
#[doc = "ADC12 Conversion Start Address: 31"]
#[inline(always)]
pub fn adc12cstartadd_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12cstartadd::Adc12cstartadd31)
}
}
#[doc = "Field `ADC12BATMAP` reader - ADC12 Internal AVCC/2 select"]
pub type Adc12batmapR = crate::BitReader;
#[doc = "Field `ADC12BATMAP` writer - ADC12 Internal AVCC/2 select"]
pub type Adc12batmapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12TCMAP` reader - ADC12 Internal TempSensor select"]
pub type Adc12tcmapR = crate::BitReader;
#[doc = "Field `ADC12TCMAP` writer - ADC12 Internal TempSensor select"]
pub type Adc12tcmapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12ICH0MAP` reader - ADC12 Internal Channel 0 select"]
pub type Adc12ich0mapR = crate::BitReader;
#[doc = "Field `ADC12ICH0MAP` writer - ADC12 Internal Channel 0 select"]
pub type Adc12ich0mapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12ICH1MAP` reader - ADC12 Internal Channel 1 select"]
pub type Adc12ich1mapR = crate::BitReader;
#[doc = "Field `ADC12ICH1MAP` writer - ADC12 Internal Channel 1 select"]
pub type Adc12ich1mapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12ICH2MAP` reader - ADC12 Internal Channel 2 select"]
pub type Adc12ich2mapR = crate::BitReader;
#[doc = "Field `ADC12ICH2MAP` writer - ADC12 Internal Channel 2 select"]
pub type Adc12ich2mapW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12ICH3MAP` reader - ADC12 Internal Channel 3 select"]
pub type Adc12ich3mapR = crate::BitReader;
#[doc = "Field `ADC12ICH3MAP` writer - ADC12 Internal Channel 3 select"]
pub type Adc12ich3mapW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Conversion Start Address Bit: 0"]
#[inline(always)]
pub fn adc12cstartadd(&self) -> Adc12cstartaddR {
Adc12cstartaddR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 6 - ADC12 Internal AVCC/2 select"]
#[inline(always)]
pub fn adc12batmap(&self) -> Adc12batmapR {
Adc12batmapR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - ADC12 Internal TempSensor select"]
#[inline(always)]
pub fn adc12tcmap(&self) -> Adc12tcmapR {
Adc12tcmapR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - ADC12 Internal Channel 0 select"]
#[inline(always)]
pub fn adc12ich0map(&self) -> Adc12ich0mapR {
Adc12ich0mapR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - ADC12 Internal Channel 1 select"]
#[inline(always)]
pub fn adc12ich1map(&self) -> Adc12ich1mapR {
Adc12ich1mapR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - ADC12 Internal Channel 2 select"]
#[inline(always)]
pub fn adc12ich2map(&self) -> Adc12ich2mapR {
Adc12ich2mapR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - ADC12 Internal Channel 3 select"]
#[inline(always)]
pub fn adc12ich3map(&self) -> Adc12ich3mapR {
Adc12ich3mapR::new(((self.bits >> 11) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Conversion Start Address Bit: 0"]
#[inline(always)]
pub fn adc12cstartadd(&mut self) -> Adc12cstartaddW<'_, Adc12ctl3Spec> {
Adc12cstartaddW::new(self, 0)
}
#[doc = "Bit 6 - ADC12 Internal AVCC/2 select"]
#[inline(always)]
pub fn adc12batmap(&mut self) -> Adc12batmapW<'_, Adc12ctl3Spec> {
Adc12batmapW::new(self, 6)
}
#[doc = "Bit 7 - ADC12 Internal TempSensor select"]
#[inline(always)]
pub fn adc12tcmap(&mut self) -> Adc12tcmapW<'_, Adc12ctl3Spec> {
Adc12tcmapW::new(self, 7)
}
#[doc = "Bit 8 - ADC12 Internal Channel 0 select"]
#[inline(always)]
pub fn adc12ich0map(&mut self) -> Adc12ich0mapW<'_, Adc12ctl3Spec> {
Adc12ich0mapW::new(self, 8)
}
#[doc = "Bit 9 - ADC12 Internal Channel 1 select"]
#[inline(always)]
pub fn adc12ich1map(&mut self) -> Adc12ich1mapW<'_, Adc12ctl3Spec> {
Adc12ich1mapW::new(self, 9)
}
#[doc = "Bit 10 - ADC12 Internal Channel 2 select"]
#[inline(always)]
pub fn adc12ich2map(&mut self) -> Adc12ich2mapW<'_, Adc12ctl3Spec> {
Adc12ich2mapW::new(self, 10)
}
#[doc = "Bit 11 - ADC12 Internal Channel 3 select"]
#[inline(always)]
pub fn adc12ich3map(&mut self) -> Adc12ich3mapW<'_, Adc12ctl3Spec> {
Adc12ich3mapW::new(self, 11)
}
}
#[doc = "ADC12 B Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ctl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ctl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12ctl3Spec;
impl crate::RegisterSpec for Adc12ctl3Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12ctl3::R`](R) reader structure"]
impl crate::Readable for Adc12ctl3Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12ctl3::W`](W) writer structure"]
impl crate::Writable for Adc12ctl3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12CTL3 to value 0"]
impl crate::Resettable for Adc12ctl3Spec {}
}
#[doc = "ADC12LO (rw) register accessor: ADC12 B Window Comparator High Threshold\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12lo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12lo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12lo`] module"]
#[doc(alias = "ADC12LO")]
pub type Adc12lo = crate::Reg<adc12lo::Adc12loSpec>;
#[doc = "ADC12 B Window Comparator High Threshold"]
pub mod adc12lo {
#[doc = "Register `ADC12LO` reader"]
pub type R = crate::R<Adc12loSpec>;
#[doc = "Register `ADC12LO` writer"]
pub type W = crate::W<Adc12loSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 B Window Comparator High Threshold\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12lo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12lo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12loSpec;
impl crate::RegisterSpec for Adc12loSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12lo::R`](R) reader structure"]
impl crate::Readable for Adc12loSpec {}
#[doc = "`write(|w| ..)` method takes [`adc12lo::W`](W) writer structure"]
impl crate::Writable for Adc12loSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12LO to value 0"]
impl crate::Resettable for Adc12loSpec {}
}
#[doc = "ADC12HI (rw) register accessor: ADC12 B Window Comparator High Threshold\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12hi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12hi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12hi`] module"]
#[doc(alias = "ADC12HI")]
pub type Adc12hi = crate::Reg<adc12hi::Adc12hiSpec>;
#[doc = "ADC12 B Window Comparator High Threshold"]
pub mod adc12hi {
#[doc = "Register `ADC12HI` reader"]
pub type R = crate::R<Adc12hiSpec>;
#[doc = "Register `ADC12HI` writer"]
pub type W = crate::W<Adc12hiSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 B Window Comparator High Threshold\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12hi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12hi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12hiSpec;
impl crate::RegisterSpec for Adc12hiSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12hi::R`](R) reader structure"]
impl crate::Readable for Adc12hiSpec {}
#[doc = "`write(|w| ..)` method takes [`adc12hi::W`](W) writer structure"]
impl crate::Writable for Adc12hiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12HI to value 0"]
impl crate::Resettable for Adc12hiSpec {}
}
#[doc = "ADC12IFGR0 (rw) register accessor: ADC12 B Interrupt Flag 0\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ifgr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ifgr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12ifgr0`] module"]
#[doc(alias = "ADC12IFGR0")]
pub type Adc12ifgr0 = crate::Reg<adc12ifgr0::Adc12ifgr0Spec>;
#[doc = "ADC12 B Interrupt Flag 0"]
pub mod adc12ifgr0 {
#[doc = "Register `ADC12IFGR0` reader"]
pub type R = crate::R<Adc12ifgr0Spec>;
#[doc = "Register `ADC12IFGR0` writer"]
pub type W = crate::W<Adc12ifgr0Spec>;
#[doc = "Field `ADC12IFG0` reader - ADC12 Memory 0 Interrupt Flag"]
pub type Adc12ifg0R = crate::BitReader;
#[doc = "Field `ADC12IFG0` writer - ADC12 Memory 0 Interrupt Flag"]
pub type Adc12ifg0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG1` reader - ADC12 Memory 1 Interrupt Flag"]
pub type Adc12ifg1R = crate::BitReader;
#[doc = "Field `ADC12IFG1` writer - ADC12 Memory 1 Interrupt Flag"]
pub type Adc12ifg1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG2` reader - ADC12 Memory 2 Interrupt Flag"]
pub type Adc12ifg2R = crate::BitReader;
#[doc = "Field `ADC12IFG2` writer - ADC12 Memory 2 Interrupt Flag"]
pub type Adc12ifg2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG3` reader - ADC12 Memory 3 Interrupt Flag"]
pub type Adc12ifg3R = crate::BitReader;
#[doc = "Field `ADC12IFG3` writer - ADC12 Memory 3 Interrupt Flag"]
pub type Adc12ifg3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG4` reader - ADC12 Memory 4 Interrupt Flag"]
pub type Adc12ifg4R = crate::BitReader;
#[doc = "Field `ADC12IFG4` writer - ADC12 Memory 4 Interrupt Flag"]
pub type Adc12ifg4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG5` reader - ADC12 Memory 5 Interrupt Flag"]
pub type Adc12ifg5R = crate::BitReader;
#[doc = "Field `ADC12IFG5` writer - ADC12 Memory 5 Interrupt Flag"]
pub type Adc12ifg5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG6` reader - ADC12 Memory 6 Interrupt Flag"]
pub type Adc12ifg6R = crate::BitReader;
#[doc = "Field `ADC12IFG6` writer - ADC12 Memory 6 Interrupt Flag"]
pub type Adc12ifg6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG7` reader - ADC12 Memory 7 Interrupt Flag"]
pub type Adc12ifg7R = crate::BitReader;
#[doc = "Field `ADC12IFG7` writer - ADC12 Memory 7 Interrupt Flag"]
pub type Adc12ifg7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG8` reader - ADC12 Memory 8 Interrupt Flag"]
pub type Adc12ifg8R = crate::BitReader;
#[doc = "Field `ADC12IFG8` writer - ADC12 Memory 8 Interrupt Flag"]
pub type Adc12ifg8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG9` reader - ADC12 Memory 9 Interrupt Flag"]
pub type Adc12ifg9R = crate::BitReader;
#[doc = "Field `ADC12IFG9` writer - ADC12 Memory 9 Interrupt Flag"]
pub type Adc12ifg9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG10` reader - ADC12 Memory 10 Interrupt Flag"]
pub type Adc12ifg10R = crate::BitReader;
#[doc = "Field `ADC12IFG10` writer - ADC12 Memory 10 Interrupt Flag"]
pub type Adc12ifg10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG11` reader - ADC12 Memory 11 Interrupt Flag"]
pub type Adc12ifg11R = crate::BitReader;
#[doc = "Field `ADC12IFG11` writer - ADC12 Memory 11 Interrupt Flag"]
pub type Adc12ifg11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG12` reader - ADC12 Memory 12 Interrupt Flag"]
pub type Adc12ifg12R = crate::BitReader;
#[doc = "Field `ADC12IFG12` writer - ADC12 Memory 12 Interrupt Flag"]
pub type Adc12ifg12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG13` reader - ADC12 Memory 13 Interrupt Flag"]
pub type Adc12ifg13R = crate::BitReader;
#[doc = "Field `ADC12IFG13` writer - ADC12 Memory 13 Interrupt Flag"]
pub type Adc12ifg13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG14` reader - ADC12 Memory 14 Interrupt Flag"]
pub type Adc12ifg14R = crate::BitReader;
#[doc = "Field `ADC12IFG14` writer - ADC12 Memory 14 Interrupt Flag"]
pub type Adc12ifg14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG15` reader - ADC12 Memory 15 Interrupt Flag"]
pub type Adc12ifg15R = crate::BitReader;
#[doc = "Field `ADC12IFG15` writer - ADC12 Memory 15 Interrupt Flag"]
pub type Adc12ifg15W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - ADC12 Memory 0 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg0(&self) -> Adc12ifg0R {
Adc12ifg0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - ADC12 Memory 1 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg1(&self) -> Adc12ifg1R {
Adc12ifg1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - ADC12 Memory 2 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg2(&self) -> Adc12ifg2R {
Adc12ifg2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - ADC12 Memory 3 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg3(&self) -> Adc12ifg3R {
Adc12ifg3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - ADC12 Memory 4 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg4(&self) -> Adc12ifg4R {
Adc12ifg4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - ADC12 Memory 5 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg5(&self) -> Adc12ifg5R {
Adc12ifg5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - ADC12 Memory 6 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg6(&self) -> Adc12ifg6R {
Adc12ifg6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - ADC12 Memory 7 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg7(&self) -> Adc12ifg7R {
Adc12ifg7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - ADC12 Memory 8 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg8(&self) -> Adc12ifg8R {
Adc12ifg8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - ADC12 Memory 9 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg9(&self) -> Adc12ifg9R {
Adc12ifg9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - ADC12 Memory 10 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg10(&self) -> Adc12ifg10R {
Adc12ifg10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - ADC12 Memory 11 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg11(&self) -> Adc12ifg11R {
Adc12ifg11R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - ADC12 Memory 12 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg12(&self) -> Adc12ifg12R {
Adc12ifg12R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - ADC12 Memory 13 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg13(&self) -> Adc12ifg13R {
Adc12ifg13R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Memory 14 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg14(&self) -> Adc12ifg14R {
Adc12ifg14R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - ADC12 Memory 15 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg15(&self) -> Adc12ifg15R {
Adc12ifg15R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - ADC12 Memory 0 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg0(&mut self) -> Adc12ifg0W<'_, Adc12ifgr0Spec> {
Adc12ifg0W::new(self, 0)
}
#[doc = "Bit 1 - ADC12 Memory 1 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg1(&mut self) -> Adc12ifg1W<'_, Adc12ifgr0Spec> {
Adc12ifg1W::new(self, 1)
}
#[doc = "Bit 2 - ADC12 Memory 2 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg2(&mut self) -> Adc12ifg2W<'_, Adc12ifgr0Spec> {
Adc12ifg2W::new(self, 2)
}
#[doc = "Bit 3 - ADC12 Memory 3 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg3(&mut self) -> Adc12ifg3W<'_, Adc12ifgr0Spec> {
Adc12ifg3W::new(self, 3)
}
#[doc = "Bit 4 - ADC12 Memory 4 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg4(&mut self) -> Adc12ifg4W<'_, Adc12ifgr0Spec> {
Adc12ifg4W::new(self, 4)
}
#[doc = "Bit 5 - ADC12 Memory 5 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg5(&mut self) -> Adc12ifg5W<'_, Adc12ifgr0Spec> {
Adc12ifg5W::new(self, 5)
}
#[doc = "Bit 6 - ADC12 Memory 6 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg6(&mut self) -> Adc12ifg6W<'_, Adc12ifgr0Spec> {
Adc12ifg6W::new(self, 6)
}
#[doc = "Bit 7 - ADC12 Memory 7 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg7(&mut self) -> Adc12ifg7W<'_, Adc12ifgr0Spec> {
Adc12ifg7W::new(self, 7)
}
#[doc = "Bit 8 - ADC12 Memory 8 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg8(&mut self) -> Adc12ifg8W<'_, Adc12ifgr0Spec> {
Adc12ifg8W::new(self, 8)
}
#[doc = "Bit 9 - ADC12 Memory 9 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg9(&mut self) -> Adc12ifg9W<'_, Adc12ifgr0Spec> {
Adc12ifg9W::new(self, 9)
}
#[doc = "Bit 10 - ADC12 Memory 10 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg10(&mut self) -> Adc12ifg10W<'_, Adc12ifgr0Spec> {
Adc12ifg10W::new(self, 10)
}
#[doc = "Bit 11 - ADC12 Memory 11 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg11(&mut self) -> Adc12ifg11W<'_, Adc12ifgr0Spec> {
Adc12ifg11W::new(self, 11)
}
#[doc = "Bit 12 - ADC12 Memory 12 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg12(&mut self) -> Adc12ifg12W<'_, Adc12ifgr0Spec> {
Adc12ifg12W::new(self, 12)
}
#[doc = "Bit 13 - ADC12 Memory 13 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg13(&mut self) -> Adc12ifg13W<'_, Adc12ifgr0Spec> {
Adc12ifg13W::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Memory 14 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg14(&mut self) -> Adc12ifg14W<'_, Adc12ifgr0Spec> {
Adc12ifg14W::new(self, 14)
}
#[doc = "Bit 15 - ADC12 Memory 15 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg15(&mut self) -> Adc12ifg15W<'_, Adc12ifgr0Spec> {
Adc12ifg15W::new(self, 15)
}
}
#[doc = "ADC12 B Interrupt Flag 0\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ifgr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ifgr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12ifgr0Spec;
impl crate::RegisterSpec for Adc12ifgr0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12ifgr0::R`](R) reader structure"]
impl crate::Readable for Adc12ifgr0Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12ifgr0::W`](W) writer structure"]
impl crate::Writable for Adc12ifgr0Spec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets ADC12IFGR0 to value 0"]
impl crate::Resettable for Adc12ifgr0Spec {}
}
#[doc = "ADC12IFGR1 (rw) register accessor: ADC12 B Interrupt Flag 1\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ifgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ifgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12ifgr1`] module"]
#[doc(alias = "ADC12IFGR1")]
pub type Adc12ifgr1 = crate::Reg<adc12ifgr1::Adc12ifgr1Spec>;
#[doc = "ADC12 B Interrupt Flag 1"]
pub mod adc12ifgr1 {
#[doc = "Register `ADC12IFGR1` reader"]
pub type R = crate::R<Adc12ifgr1Spec>;
#[doc = "Register `ADC12IFGR1` writer"]
pub type W = crate::W<Adc12ifgr1Spec>;
#[doc = "Field `ADC12IFG16` reader - ADC12 Memory 16 Interrupt Flag"]
pub type Adc12ifg16R = crate::BitReader;
#[doc = "Field `ADC12IFG16` writer - ADC12 Memory 16 Interrupt Flag"]
pub type Adc12ifg16W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG17` reader - ADC12 Memory 17 Interrupt Flag"]
pub type Adc12ifg17R = crate::BitReader;
#[doc = "Field `ADC12IFG17` writer - ADC12 Memory 17 Interrupt Flag"]
pub type Adc12ifg17W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG18` reader - ADC12 Memory 18 Interrupt Flag"]
pub type Adc12ifg18R = crate::BitReader;
#[doc = "Field `ADC12IFG18` writer - ADC12 Memory 18 Interrupt Flag"]
pub type Adc12ifg18W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG19` reader - ADC12 Memory 19 Interrupt Flag"]
pub type Adc12ifg19R = crate::BitReader;
#[doc = "Field `ADC12IFG19` writer - ADC12 Memory 19 Interrupt Flag"]
pub type Adc12ifg19W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG20` reader - ADC12 Memory 20 Interrupt Flag"]
pub type Adc12ifg20R = crate::BitReader;
#[doc = "Field `ADC12IFG20` writer - ADC12 Memory 20 Interrupt Flag"]
pub type Adc12ifg20W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG21` reader - ADC12 Memory 21 Interrupt Flag"]
pub type Adc12ifg21R = crate::BitReader;
#[doc = "Field `ADC12IFG21` writer - ADC12 Memory 21 Interrupt Flag"]
pub type Adc12ifg21W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG22` reader - ADC12 Memory 22 Interrupt Flag"]
pub type Adc12ifg22R = crate::BitReader;
#[doc = "Field `ADC12IFG22` writer - ADC12 Memory 22 Interrupt Flag"]
pub type Adc12ifg22W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG23` reader - ADC12 Memory 23 Interrupt Flag"]
pub type Adc12ifg23R = crate::BitReader;
#[doc = "Field `ADC12IFG23` writer - ADC12 Memory 23 Interrupt Flag"]
pub type Adc12ifg23W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG24` reader - ADC12 Memory 24 Interrupt Flag"]
pub type Adc12ifg24R = crate::BitReader;
#[doc = "Field `ADC12IFG24` writer - ADC12 Memory 24 Interrupt Flag"]
pub type Adc12ifg24W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG25` reader - ADC12 Memory 25 Interrupt Flag"]
pub type Adc12ifg25R = crate::BitReader;
#[doc = "Field `ADC12IFG25` writer - ADC12 Memory 25 Interrupt Flag"]
pub type Adc12ifg25W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG26` reader - ADC12 Memory 26 Interrupt Flag"]
pub type Adc12ifg26R = crate::BitReader;
#[doc = "Field `ADC12IFG26` writer - ADC12 Memory 26 Interrupt Flag"]
pub type Adc12ifg26W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG27` reader - ADC12 Memory 27 Interrupt Flag"]
pub type Adc12ifg27R = crate::BitReader;
#[doc = "Field `ADC12IFG27` writer - ADC12 Memory 27 Interrupt Flag"]
pub type Adc12ifg27W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG28` reader - ADC12 Memory 28 Interrupt Flag"]
pub type Adc12ifg28R = crate::BitReader;
#[doc = "Field `ADC12IFG28` writer - ADC12 Memory 28 Interrupt Flag"]
pub type Adc12ifg28W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG29` reader - ADC12 Memory 29 Interrupt Flag"]
pub type Adc12ifg29R = crate::BitReader;
#[doc = "Field `ADC12IFG29` writer - ADC12 Memory 29 Interrupt Flag"]
pub type Adc12ifg29W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG30` reader - ADC12 Memory 30 Interrupt Flag"]
pub type Adc12ifg30R = crate::BitReader;
#[doc = "Field `ADC12IFG30` writer - ADC12 Memory 30 Interrupt Flag"]
pub type Adc12ifg30W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IFG31` reader - ADC12 Memory 31 Interrupt Flag"]
pub type Adc12ifg31R = crate::BitReader;
#[doc = "Field `ADC12IFG31` writer - ADC12 Memory 31 Interrupt Flag"]
pub type Adc12ifg31W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - ADC12 Memory 16 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg16(&self) -> Adc12ifg16R {
Adc12ifg16R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - ADC12 Memory 17 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg17(&self) -> Adc12ifg17R {
Adc12ifg17R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - ADC12 Memory 18 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg18(&self) -> Adc12ifg18R {
Adc12ifg18R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - ADC12 Memory 19 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg19(&self) -> Adc12ifg19R {
Adc12ifg19R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - ADC12 Memory 20 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg20(&self) -> Adc12ifg20R {
Adc12ifg20R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - ADC12 Memory 21 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg21(&self) -> Adc12ifg21R {
Adc12ifg21R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - ADC12 Memory 22 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg22(&self) -> Adc12ifg22R {
Adc12ifg22R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - ADC12 Memory 23 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg23(&self) -> Adc12ifg23R {
Adc12ifg23R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - ADC12 Memory 24 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg24(&self) -> Adc12ifg24R {
Adc12ifg24R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - ADC12 Memory 25 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg25(&self) -> Adc12ifg25R {
Adc12ifg25R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - ADC12 Memory 26 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg26(&self) -> Adc12ifg26R {
Adc12ifg26R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - ADC12 Memory 27 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg27(&self) -> Adc12ifg27R {
Adc12ifg27R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - ADC12 Memory 28 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg28(&self) -> Adc12ifg28R {
Adc12ifg28R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - ADC12 Memory 29 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg29(&self) -> Adc12ifg29R {
Adc12ifg29R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Memory 30 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg30(&self) -> Adc12ifg30R {
Adc12ifg30R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - ADC12 Memory 31 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg31(&self) -> Adc12ifg31R {
Adc12ifg31R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - ADC12 Memory 16 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg16(&mut self) -> Adc12ifg16W<'_, Adc12ifgr1Spec> {
Adc12ifg16W::new(self, 0)
}
#[doc = "Bit 1 - ADC12 Memory 17 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg17(&mut self) -> Adc12ifg17W<'_, Adc12ifgr1Spec> {
Adc12ifg17W::new(self, 1)
}
#[doc = "Bit 2 - ADC12 Memory 18 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg18(&mut self) -> Adc12ifg18W<'_, Adc12ifgr1Spec> {
Adc12ifg18W::new(self, 2)
}
#[doc = "Bit 3 - ADC12 Memory 19 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg19(&mut self) -> Adc12ifg19W<'_, Adc12ifgr1Spec> {
Adc12ifg19W::new(self, 3)
}
#[doc = "Bit 4 - ADC12 Memory 20 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg20(&mut self) -> Adc12ifg20W<'_, Adc12ifgr1Spec> {
Adc12ifg20W::new(self, 4)
}
#[doc = "Bit 5 - ADC12 Memory 21 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg21(&mut self) -> Adc12ifg21W<'_, Adc12ifgr1Spec> {
Adc12ifg21W::new(self, 5)
}
#[doc = "Bit 6 - ADC12 Memory 22 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg22(&mut self) -> Adc12ifg22W<'_, Adc12ifgr1Spec> {
Adc12ifg22W::new(self, 6)
}
#[doc = "Bit 7 - ADC12 Memory 23 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg23(&mut self) -> Adc12ifg23W<'_, Adc12ifgr1Spec> {
Adc12ifg23W::new(self, 7)
}
#[doc = "Bit 8 - ADC12 Memory 24 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg24(&mut self) -> Adc12ifg24W<'_, Adc12ifgr1Spec> {
Adc12ifg24W::new(self, 8)
}
#[doc = "Bit 9 - ADC12 Memory 25 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg25(&mut self) -> Adc12ifg25W<'_, Adc12ifgr1Spec> {
Adc12ifg25W::new(self, 9)
}
#[doc = "Bit 10 - ADC12 Memory 26 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg26(&mut self) -> Adc12ifg26W<'_, Adc12ifgr1Spec> {
Adc12ifg26W::new(self, 10)
}
#[doc = "Bit 11 - ADC12 Memory 27 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg27(&mut self) -> Adc12ifg27W<'_, Adc12ifgr1Spec> {
Adc12ifg27W::new(self, 11)
}
#[doc = "Bit 12 - ADC12 Memory 28 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg28(&mut self) -> Adc12ifg28W<'_, Adc12ifgr1Spec> {
Adc12ifg28W::new(self, 12)
}
#[doc = "Bit 13 - ADC12 Memory 29 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg29(&mut self) -> Adc12ifg29W<'_, Adc12ifgr1Spec> {
Adc12ifg29W::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Memory 30 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg30(&mut self) -> Adc12ifg30W<'_, Adc12ifgr1Spec> {
Adc12ifg30W::new(self, 14)
}
#[doc = "Bit 15 - ADC12 Memory 31 Interrupt Flag"]
#[inline(always)]
pub fn adc12ifg31(&mut self) -> Adc12ifg31W<'_, Adc12ifgr1Spec> {
Adc12ifg31W::new(self, 15)
}
}
#[doc = "ADC12 B Interrupt Flag 1\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ifgr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ifgr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12ifgr1Spec;
impl crate::RegisterSpec for Adc12ifgr1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12ifgr1::R`](R) reader structure"]
impl crate::Readable for Adc12ifgr1Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12ifgr1::W`](W) writer structure"]
impl crate::Writable for Adc12ifgr1Spec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets ADC12IFGR1 to value 0"]
impl crate::Resettable for Adc12ifgr1Spec {}
}
#[doc = "ADC12IFGR2 (rw) register accessor: ADC12 B Interrupt Flag 2\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ifgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ifgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12ifgr2`] module"]
#[doc(alias = "ADC12IFGR2")]
pub type Adc12ifgr2 = crate::Reg<adc12ifgr2::Adc12ifgr2Spec>;
#[doc = "ADC12 B Interrupt Flag 2"]
pub mod adc12ifgr2 {
#[doc = "Register `ADC12IFGR2` reader"]
pub type R = crate::R<Adc12ifgr2Spec>;
#[doc = "Register `ADC12IFGR2` writer"]
pub type W = crate::W<Adc12ifgr2Spec>;
#[doc = "Field `ADC12INIFG` reader - ADC12 Interrupt Flag for the inside of window of the Window comparator"]
pub type Adc12inifgR = crate::BitReader;
#[doc = "Field `ADC12INIFG` writer - ADC12 Interrupt Flag for the inside of window of the Window comparator"]
pub type Adc12inifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12LOIFG` reader - ADC12 Interrupt Flag for lower threshold of the Window comparator"]
pub type Adc12loifgR = crate::BitReader;
#[doc = "Field `ADC12LOIFG` writer - ADC12 Interrupt Flag for lower threshold of the Window comparator"]
pub type Adc12loifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12HIIFG` reader - ADC12 Interrupt Flag for upper threshold of the Window comparator"]
pub type Adc12hiifgR = crate::BitReader;
#[doc = "Field `ADC12HIIFG` writer - ADC12 Interrupt Flag for upper threshold of the Window comparator"]
pub type Adc12hiifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12OVIFG` reader - ADC12 ADC12MEMx Overflow interrupt Flag"]
pub type Adc12ovifgR = crate::BitReader;
#[doc = "Field `ADC12OVIFG` writer - ADC12 ADC12MEMx Overflow interrupt Flag"]
pub type Adc12ovifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12TOVIFG` reader - ADC12 Timer Overflow interrupt Flag"]
pub type Adc12tovifgR = crate::BitReader;
#[doc = "Field `ADC12TOVIFG` writer - ADC12 Timer Overflow interrupt Flag"]
pub type Adc12tovifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12RDYIFG` reader - ADC12 local buffered reference ready interrupt Flag"]
pub type Adc12rdyifgR = crate::BitReader;
#[doc = "Field `ADC12RDYIFG` writer - ADC12 local buffered reference ready interrupt Flag"]
pub type Adc12rdyifgW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 1 - ADC12 Interrupt Flag for the inside of window of the Window comparator"]
#[inline(always)]
pub fn adc12inifg(&self) -> Adc12inifgR {
Adc12inifgR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - ADC12 Interrupt Flag for lower threshold of the Window comparator"]
#[inline(always)]
pub fn adc12loifg(&self) -> Adc12loifgR {
Adc12loifgR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - ADC12 Interrupt Flag for upper threshold of the Window comparator"]
#[inline(always)]
pub fn adc12hiifg(&self) -> Adc12hiifgR {
Adc12hiifgR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - ADC12 ADC12MEMx Overflow interrupt Flag"]
#[inline(always)]
pub fn adc12ovifg(&self) -> Adc12ovifgR {
Adc12ovifgR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - ADC12 Timer Overflow interrupt Flag"]
#[inline(always)]
pub fn adc12tovifg(&self) -> Adc12tovifgR {
Adc12tovifgR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - ADC12 local buffered reference ready interrupt Flag"]
#[inline(always)]
pub fn adc12rdyifg(&self) -> Adc12rdyifgR {
Adc12rdyifgR::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1 - ADC12 Interrupt Flag for the inside of window of the Window comparator"]
#[inline(always)]
pub fn adc12inifg(&mut self) -> Adc12inifgW<'_, Adc12ifgr2Spec> {
Adc12inifgW::new(self, 1)
}
#[doc = "Bit 2 - ADC12 Interrupt Flag for lower threshold of the Window comparator"]
#[inline(always)]
pub fn adc12loifg(&mut self) -> Adc12loifgW<'_, Adc12ifgr2Spec> {
Adc12loifgW::new(self, 2)
}
#[doc = "Bit 3 - ADC12 Interrupt Flag for upper threshold of the Window comparator"]
#[inline(always)]
pub fn adc12hiifg(&mut self) -> Adc12hiifgW<'_, Adc12ifgr2Spec> {
Adc12hiifgW::new(self, 3)
}
#[doc = "Bit 4 - ADC12 ADC12MEMx Overflow interrupt Flag"]
#[inline(always)]
pub fn adc12ovifg(&mut self) -> Adc12ovifgW<'_, Adc12ifgr2Spec> {
Adc12ovifgW::new(self, 4)
}
#[doc = "Bit 5 - ADC12 Timer Overflow interrupt Flag"]
#[inline(always)]
pub fn adc12tovifg(&mut self) -> Adc12tovifgW<'_, Adc12ifgr2Spec> {
Adc12tovifgW::new(self, 5)
}
#[doc = "Bit 6 - ADC12 local buffered reference ready interrupt Flag"]
#[inline(always)]
pub fn adc12rdyifg(&mut self) -> Adc12rdyifgW<'_, Adc12ifgr2Spec> {
Adc12rdyifgW::new(self, 6)
}
}
#[doc = "ADC12 B Interrupt Flag 2\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ifgr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ifgr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12ifgr2Spec;
impl crate::RegisterSpec for Adc12ifgr2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12ifgr2::R`](R) reader structure"]
impl crate::Readable for Adc12ifgr2Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12ifgr2::W`](W) writer structure"]
impl crate::Writable for Adc12ifgr2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12IFGR2 to value 0"]
impl crate::Resettable for Adc12ifgr2Spec {}
}
#[doc = "ADC12IER0 (rw) register accessor: ADC12 B Interrupt Enable 0\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ier0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ier0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12ier0`] module"]
#[doc(alias = "ADC12IER0")]
pub type Adc12ier0 = crate::Reg<adc12ier0::Adc12ier0Spec>;
#[doc = "ADC12 B Interrupt Enable 0"]
pub mod adc12ier0 {
#[doc = "Register `ADC12IER0` reader"]
pub type R = crate::R<Adc12ier0Spec>;
#[doc = "Register `ADC12IER0` writer"]
pub type W = crate::W<Adc12ier0Spec>;
#[doc = "Field `ADC12IE0` reader - ADC12 Memory 0 Interrupt Enable"]
pub type Adc12ie0R = crate::BitReader;
#[doc = "Field `ADC12IE0` writer - ADC12 Memory 0 Interrupt Enable"]
pub type Adc12ie0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE1` reader - ADC12 Memory 1 Interrupt Enable"]
pub type Adc12ie1R = crate::BitReader;
#[doc = "Field `ADC12IE1` writer - ADC12 Memory 1 Interrupt Enable"]
pub type Adc12ie1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE2` reader - ADC12 Memory 2 Interrupt Enable"]
pub type Adc12ie2R = crate::BitReader;
#[doc = "Field `ADC12IE2` writer - ADC12 Memory 2 Interrupt Enable"]
pub type Adc12ie2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE3` reader - ADC12 Memory 3 Interrupt Enable"]
pub type Adc12ie3R = crate::BitReader;
#[doc = "Field `ADC12IE3` writer - ADC12 Memory 3 Interrupt Enable"]
pub type Adc12ie3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE4` reader - ADC12 Memory 4 Interrupt Enable"]
pub type Adc12ie4R = crate::BitReader;
#[doc = "Field `ADC12IE4` writer - ADC12 Memory 4 Interrupt Enable"]
pub type Adc12ie4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE5` reader - ADC12 Memory 5 Interrupt Enable"]
pub type Adc12ie5R = crate::BitReader;
#[doc = "Field `ADC12IE5` writer - ADC12 Memory 5 Interrupt Enable"]
pub type Adc12ie5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE6` reader - ADC12 Memory 6 Interrupt Enable"]
pub type Adc12ie6R = crate::BitReader;
#[doc = "Field `ADC12IE6` writer - ADC12 Memory 6 Interrupt Enable"]
pub type Adc12ie6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE7` reader - ADC12 Memory 7 Interrupt Enable"]
pub type Adc12ie7R = crate::BitReader;
#[doc = "Field `ADC12IE7` writer - ADC12 Memory 7 Interrupt Enable"]
pub type Adc12ie7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE8` reader - ADC12 Memory 8 Interrupt Enable"]
pub type Adc12ie8R = crate::BitReader;
#[doc = "Field `ADC12IE8` writer - ADC12 Memory 8 Interrupt Enable"]
pub type Adc12ie8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE9` reader - ADC12 Memory 9 Interrupt Enable"]
pub type Adc12ie9R = crate::BitReader;
#[doc = "Field `ADC12IE9` writer - ADC12 Memory 9 Interrupt Enable"]
pub type Adc12ie9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE10` reader - ADC12 Memory 10 Interrupt Enable"]
pub type Adc12ie10R = crate::BitReader;
#[doc = "Field `ADC12IE10` writer - ADC12 Memory 10 Interrupt Enable"]
pub type Adc12ie10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE11` reader - ADC12 Memory 11 Interrupt Enable"]
pub type Adc12ie11R = crate::BitReader;
#[doc = "Field `ADC12IE11` writer - ADC12 Memory 11 Interrupt Enable"]
pub type Adc12ie11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE12` reader - ADC12 Memory 12 Interrupt Enable"]
pub type Adc12ie12R = crate::BitReader;
#[doc = "Field `ADC12IE12` writer - ADC12 Memory 12 Interrupt Enable"]
pub type Adc12ie12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE13` reader - ADC12 Memory 13 Interrupt Enable"]
pub type Adc12ie13R = crate::BitReader;
#[doc = "Field `ADC12IE13` writer - ADC12 Memory 13 Interrupt Enable"]
pub type Adc12ie13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE14` reader - ADC12 Memory 14 Interrupt Enable"]
pub type Adc12ie14R = crate::BitReader;
#[doc = "Field `ADC12IE14` writer - ADC12 Memory 14 Interrupt Enable"]
pub type Adc12ie14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE15` reader - ADC12 Memory 15 Interrupt Enable"]
pub type Adc12ie15R = crate::BitReader;
#[doc = "Field `ADC12IE15` writer - ADC12 Memory 15 Interrupt Enable"]
pub type Adc12ie15W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - ADC12 Memory 0 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie0(&self) -> Adc12ie0R {
Adc12ie0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - ADC12 Memory 1 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie1(&self) -> Adc12ie1R {
Adc12ie1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - ADC12 Memory 2 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie2(&self) -> Adc12ie2R {
Adc12ie2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - ADC12 Memory 3 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie3(&self) -> Adc12ie3R {
Adc12ie3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - ADC12 Memory 4 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie4(&self) -> Adc12ie4R {
Adc12ie4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - ADC12 Memory 5 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie5(&self) -> Adc12ie5R {
Adc12ie5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - ADC12 Memory 6 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie6(&self) -> Adc12ie6R {
Adc12ie6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - ADC12 Memory 7 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie7(&self) -> Adc12ie7R {
Adc12ie7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - ADC12 Memory 8 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie8(&self) -> Adc12ie8R {
Adc12ie8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - ADC12 Memory 9 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie9(&self) -> Adc12ie9R {
Adc12ie9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - ADC12 Memory 10 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie10(&self) -> Adc12ie10R {
Adc12ie10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - ADC12 Memory 11 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie11(&self) -> Adc12ie11R {
Adc12ie11R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - ADC12 Memory 12 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie12(&self) -> Adc12ie12R {
Adc12ie12R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - ADC12 Memory 13 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie13(&self) -> Adc12ie13R {
Adc12ie13R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Memory 14 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie14(&self) -> Adc12ie14R {
Adc12ie14R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - ADC12 Memory 15 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie15(&self) -> Adc12ie15R {
Adc12ie15R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - ADC12 Memory 0 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie0(&mut self) -> Adc12ie0W<'_, Adc12ier0Spec> {
Adc12ie0W::new(self, 0)
}
#[doc = "Bit 1 - ADC12 Memory 1 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie1(&mut self) -> Adc12ie1W<'_, Adc12ier0Spec> {
Adc12ie1W::new(self, 1)
}
#[doc = "Bit 2 - ADC12 Memory 2 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie2(&mut self) -> Adc12ie2W<'_, Adc12ier0Spec> {
Adc12ie2W::new(self, 2)
}
#[doc = "Bit 3 - ADC12 Memory 3 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie3(&mut self) -> Adc12ie3W<'_, Adc12ier0Spec> {
Adc12ie3W::new(self, 3)
}
#[doc = "Bit 4 - ADC12 Memory 4 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie4(&mut self) -> Adc12ie4W<'_, Adc12ier0Spec> {
Adc12ie4W::new(self, 4)
}
#[doc = "Bit 5 - ADC12 Memory 5 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie5(&mut self) -> Adc12ie5W<'_, Adc12ier0Spec> {
Adc12ie5W::new(self, 5)
}
#[doc = "Bit 6 - ADC12 Memory 6 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie6(&mut self) -> Adc12ie6W<'_, Adc12ier0Spec> {
Adc12ie6W::new(self, 6)
}
#[doc = "Bit 7 - ADC12 Memory 7 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie7(&mut self) -> Adc12ie7W<'_, Adc12ier0Spec> {
Adc12ie7W::new(self, 7)
}
#[doc = "Bit 8 - ADC12 Memory 8 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie8(&mut self) -> Adc12ie8W<'_, Adc12ier0Spec> {
Adc12ie8W::new(self, 8)
}
#[doc = "Bit 9 - ADC12 Memory 9 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie9(&mut self) -> Adc12ie9W<'_, Adc12ier0Spec> {
Adc12ie9W::new(self, 9)
}
#[doc = "Bit 10 - ADC12 Memory 10 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie10(&mut self) -> Adc12ie10W<'_, Adc12ier0Spec> {
Adc12ie10W::new(self, 10)
}
#[doc = "Bit 11 - ADC12 Memory 11 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie11(&mut self) -> Adc12ie11W<'_, Adc12ier0Spec> {
Adc12ie11W::new(self, 11)
}
#[doc = "Bit 12 - ADC12 Memory 12 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie12(&mut self) -> Adc12ie12W<'_, Adc12ier0Spec> {
Adc12ie12W::new(self, 12)
}
#[doc = "Bit 13 - ADC12 Memory 13 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie13(&mut self) -> Adc12ie13W<'_, Adc12ier0Spec> {
Adc12ie13W::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Memory 14 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie14(&mut self) -> Adc12ie14W<'_, Adc12ier0Spec> {
Adc12ie14W::new(self, 14)
}
#[doc = "Bit 15 - ADC12 Memory 15 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie15(&mut self) -> Adc12ie15W<'_, Adc12ier0Spec> {
Adc12ie15W::new(self, 15)
}
}
#[doc = "ADC12 B Interrupt Enable 0\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ier0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ier0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12ier0Spec;
impl crate::RegisterSpec for Adc12ier0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12ier0::R`](R) reader structure"]
impl crate::Readable for Adc12ier0Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12ier0::W`](W) writer structure"]
impl crate::Writable for Adc12ier0Spec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets ADC12IER0 to value 0"]
impl crate::Resettable for Adc12ier0Spec {}
}
#[doc = "ADC12IER1 (rw) register accessor: ADC12 B Interrupt Enable 1\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ier1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ier1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12ier1`] module"]
#[doc(alias = "ADC12IER1")]
pub type Adc12ier1 = crate::Reg<adc12ier1::Adc12ier1Spec>;
#[doc = "ADC12 B Interrupt Enable 1"]
pub mod adc12ier1 {
#[doc = "Register `ADC12IER1` reader"]
pub type R = crate::R<Adc12ier1Spec>;
#[doc = "Register `ADC12IER1` writer"]
pub type W = crate::W<Adc12ier1Spec>;
#[doc = "Field `ADC12IE16` reader - ADC12 Memory 16 Interrupt Enable"]
pub type Adc12ie16R = crate::BitReader;
#[doc = "Field `ADC12IE16` writer - ADC12 Memory 16 Interrupt Enable"]
pub type Adc12ie16W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE17` reader - ADC12 Memory 17 Interrupt Enable"]
pub type Adc12ie17R = crate::BitReader;
#[doc = "Field `ADC12IE17` writer - ADC12 Memory 17 Interrupt Enable"]
pub type Adc12ie17W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE18` reader - ADC12 Memory 18 Interrupt Enable"]
pub type Adc12ie18R = crate::BitReader;
#[doc = "Field `ADC12IE18` writer - ADC12 Memory 18 Interrupt Enable"]
pub type Adc12ie18W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE19` reader - ADC12 Memory 19 Interrupt Enable"]
pub type Adc12ie19R = crate::BitReader;
#[doc = "Field `ADC12IE19` writer - ADC12 Memory 19 Interrupt Enable"]
pub type Adc12ie19W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE20` reader - ADC12 Memory 20 Interrupt Enable"]
pub type Adc12ie20R = crate::BitReader;
#[doc = "Field `ADC12IE20` writer - ADC12 Memory 20 Interrupt Enable"]
pub type Adc12ie20W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE21` reader - ADC12 Memory 21 Interrupt Enable"]
pub type Adc12ie21R = crate::BitReader;
#[doc = "Field `ADC12IE21` writer - ADC12 Memory 21 Interrupt Enable"]
pub type Adc12ie21W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE22` reader - ADC12 Memory 22 Interrupt Enable"]
pub type Adc12ie22R = crate::BitReader;
#[doc = "Field `ADC12IE22` writer - ADC12 Memory 22 Interrupt Enable"]
pub type Adc12ie22W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE23` reader - ADC12 Memory 23 Interrupt Enable"]
pub type Adc12ie23R = crate::BitReader;
#[doc = "Field `ADC12IE23` writer - ADC12 Memory 23 Interrupt Enable"]
pub type Adc12ie23W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE24` reader - ADC12 Memory 24 Interrupt Enable"]
pub type Adc12ie24R = crate::BitReader;
#[doc = "Field `ADC12IE24` writer - ADC12 Memory 24 Interrupt Enable"]
pub type Adc12ie24W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE25` reader - ADC12 Memory 25 Interrupt Enable"]
pub type Adc12ie25R = crate::BitReader;
#[doc = "Field `ADC12IE25` writer - ADC12 Memory 25 Interrupt Enable"]
pub type Adc12ie25W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE26` reader - ADC12 Memory 26 Interrupt Enable"]
pub type Adc12ie26R = crate::BitReader;
#[doc = "Field `ADC12IE26` writer - ADC12 Memory 26 Interrupt Enable"]
pub type Adc12ie26W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE27` reader - ADC12 Memory 27 Interrupt Enable"]
pub type Adc12ie27R = crate::BitReader;
#[doc = "Field `ADC12IE27` writer - ADC12 Memory 27 Interrupt Enable"]
pub type Adc12ie27W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE28` reader - ADC12 Memory 28 Interrupt Enable"]
pub type Adc12ie28R = crate::BitReader;
#[doc = "Field `ADC12IE28` writer - ADC12 Memory 28 Interrupt Enable"]
pub type Adc12ie28W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE29` reader - ADC12 Memory 29 Interrupt Enable"]
pub type Adc12ie29R = crate::BitReader;
#[doc = "Field `ADC12IE29` writer - ADC12 Memory 29 Interrupt Enable"]
pub type Adc12ie29W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE30` reader - ADC12 Memory 30 Interrupt Enable"]
pub type Adc12ie30R = crate::BitReader;
#[doc = "Field `ADC12IE30` writer - ADC12 Memory 30 Interrupt Enable"]
pub type Adc12ie30W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12IE31` reader - ADC12 Memory 31 Interrupt Enable"]
pub type Adc12ie31R = crate::BitReader;
#[doc = "Field `ADC12IE31` writer - ADC12 Memory 31 Interrupt Enable"]
pub type Adc12ie31W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - ADC12 Memory 16 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie16(&self) -> Adc12ie16R {
Adc12ie16R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - ADC12 Memory 17 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie17(&self) -> Adc12ie17R {
Adc12ie17R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - ADC12 Memory 18 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie18(&self) -> Adc12ie18R {
Adc12ie18R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - ADC12 Memory 19 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie19(&self) -> Adc12ie19R {
Adc12ie19R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - ADC12 Memory 20 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie20(&self) -> Adc12ie20R {
Adc12ie20R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - ADC12 Memory 21 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie21(&self) -> Adc12ie21R {
Adc12ie21R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - ADC12 Memory 22 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie22(&self) -> Adc12ie22R {
Adc12ie22R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - ADC12 Memory 23 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie23(&self) -> Adc12ie23R {
Adc12ie23R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - ADC12 Memory 24 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie24(&self) -> Adc12ie24R {
Adc12ie24R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - ADC12 Memory 25 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie25(&self) -> Adc12ie25R {
Adc12ie25R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - ADC12 Memory 26 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie26(&self) -> Adc12ie26R {
Adc12ie26R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - ADC12 Memory 27 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie27(&self) -> Adc12ie27R {
Adc12ie27R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - ADC12 Memory 28 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie28(&self) -> Adc12ie28R {
Adc12ie28R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - ADC12 Memory 29 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie29(&self) -> Adc12ie29R {
Adc12ie29R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Memory 30 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie30(&self) -> Adc12ie30R {
Adc12ie30R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - ADC12 Memory 31 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie31(&self) -> Adc12ie31R {
Adc12ie31R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - ADC12 Memory 16 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie16(&mut self) -> Adc12ie16W<'_, Adc12ier1Spec> {
Adc12ie16W::new(self, 0)
}
#[doc = "Bit 1 - ADC12 Memory 17 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie17(&mut self) -> Adc12ie17W<'_, Adc12ier1Spec> {
Adc12ie17W::new(self, 1)
}
#[doc = "Bit 2 - ADC12 Memory 18 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie18(&mut self) -> Adc12ie18W<'_, Adc12ier1Spec> {
Adc12ie18W::new(self, 2)
}
#[doc = "Bit 3 - ADC12 Memory 19 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie19(&mut self) -> Adc12ie19W<'_, Adc12ier1Spec> {
Adc12ie19W::new(self, 3)
}
#[doc = "Bit 4 - ADC12 Memory 20 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie20(&mut self) -> Adc12ie20W<'_, Adc12ier1Spec> {
Adc12ie20W::new(self, 4)
}
#[doc = "Bit 5 - ADC12 Memory 21 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie21(&mut self) -> Adc12ie21W<'_, Adc12ier1Spec> {
Adc12ie21W::new(self, 5)
}
#[doc = "Bit 6 - ADC12 Memory 22 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie22(&mut self) -> Adc12ie22W<'_, Adc12ier1Spec> {
Adc12ie22W::new(self, 6)
}
#[doc = "Bit 7 - ADC12 Memory 23 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie23(&mut self) -> Adc12ie23W<'_, Adc12ier1Spec> {
Adc12ie23W::new(self, 7)
}
#[doc = "Bit 8 - ADC12 Memory 24 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie24(&mut self) -> Adc12ie24W<'_, Adc12ier1Spec> {
Adc12ie24W::new(self, 8)
}
#[doc = "Bit 9 - ADC12 Memory 25 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie25(&mut self) -> Adc12ie25W<'_, Adc12ier1Spec> {
Adc12ie25W::new(self, 9)
}
#[doc = "Bit 10 - ADC12 Memory 26 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie26(&mut self) -> Adc12ie26W<'_, Adc12ier1Spec> {
Adc12ie26W::new(self, 10)
}
#[doc = "Bit 11 - ADC12 Memory 27 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie27(&mut self) -> Adc12ie27W<'_, Adc12ier1Spec> {
Adc12ie27W::new(self, 11)
}
#[doc = "Bit 12 - ADC12 Memory 28 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie28(&mut self) -> Adc12ie28W<'_, Adc12ier1Spec> {
Adc12ie28W::new(self, 12)
}
#[doc = "Bit 13 - ADC12 Memory 29 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie29(&mut self) -> Adc12ie29W<'_, Adc12ier1Spec> {
Adc12ie29W::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Memory 30 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie30(&mut self) -> Adc12ie30W<'_, Adc12ier1Spec> {
Adc12ie30W::new(self, 14)
}
#[doc = "Bit 15 - ADC12 Memory 31 Interrupt Enable"]
#[inline(always)]
pub fn adc12ie31(&mut self) -> Adc12ie31W<'_, Adc12ier1Spec> {
Adc12ie31W::new(self, 15)
}
}
#[doc = "ADC12 B Interrupt Enable 1\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ier1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ier1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12ier1Spec;
impl crate::RegisterSpec for Adc12ier1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12ier1::R`](R) reader structure"]
impl crate::Readable for Adc12ier1Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12ier1::W`](W) writer structure"]
impl crate::Writable for Adc12ier1Spec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets ADC12IER1 to value 0"]
impl crate::Resettable for Adc12ier1Spec {}
}
#[doc = "ADC12IER2 (rw) register accessor: ADC12 B Interrupt Enable 2\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ier2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ier2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12ier2`] module"]
#[doc(alias = "ADC12IER2")]
pub type Adc12ier2 = crate::Reg<adc12ier2::Adc12ier2Spec>;
#[doc = "ADC12 B Interrupt Enable 2"]
pub mod adc12ier2 {
#[doc = "Register `ADC12IER2` reader"]
pub type R = crate::R<Adc12ier2Spec>;
#[doc = "Register `ADC12IER2` writer"]
pub type W = crate::W<Adc12ier2Spec>;
#[doc = "Field `ADC12INIE` reader - ADC12 Interrupt enable for the inside of window of the Window comparator"]
pub type Adc12inieR = crate::BitReader;
#[doc = "Field `ADC12INIE` writer - ADC12 Interrupt enable for the inside of window of the Window comparator"]
pub type Adc12inieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12LOIE` reader - ADC12 Interrupt enable for lower threshold of the Window comparator"]
pub type Adc12loieR = crate::BitReader;
#[doc = "Field `ADC12LOIE` writer - ADC12 Interrupt enable for lower threshold of the Window comparator"]
pub type Adc12loieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12HIIE` reader - ADC12 Interrupt enable for upper threshold of the Window comparator"]
pub type Adc12hiieR = crate::BitReader;
#[doc = "Field `ADC12HIIE` writer - ADC12 Interrupt enable for upper threshold of the Window comparator"]
pub type Adc12hiieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12OVIE` reader - ADC12 ADC12MEMx Overflow interrupt enable"]
pub type Adc12ovieR = crate::BitReader;
#[doc = "Field `ADC12OVIE` writer - ADC12 ADC12MEMx Overflow interrupt enable"]
pub type Adc12ovieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12TOVIE` reader - ADC12 Timer Overflow interrupt enable"]
pub type Adc12tovieR = crate::BitReader;
#[doc = "Field `ADC12TOVIE` writer - ADC12 Timer Overflow interrupt enable"]
pub type Adc12tovieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12RDYIE` reader - ADC12 local buffered reference ready interrupt enable"]
pub type Adc12rdyieR = crate::BitReader;
#[doc = "Field `ADC12RDYIE` writer - ADC12 local buffered reference ready interrupt enable"]
pub type Adc12rdyieW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 1 - ADC12 Interrupt enable for the inside of window of the Window comparator"]
#[inline(always)]
pub fn adc12inie(&self) -> Adc12inieR {
Adc12inieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - ADC12 Interrupt enable for lower threshold of the Window comparator"]
#[inline(always)]
pub fn adc12loie(&self) -> Adc12loieR {
Adc12loieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - ADC12 Interrupt enable for upper threshold of the Window comparator"]
#[inline(always)]
pub fn adc12hiie(&self) -> Adc12hiieR {
Adc12hiieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - ADC12 ADC12MEMx Overflow interrupt enable"]
#[inline(always)]
pub fn adc12ovie(&self) -> Adc12ovieR {
Adc12ovieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - ADC12 Timer Overflow interrupt enable"]
#[inline(always)]
pub fn adc12tovie(&self) -> Adc12tovieR {
Adc12tovieR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - ADC12 local buffered reference ready interrupt enable"]
#[inline(always)]
pub fn adc12rdyie(&self) -> Adc12rdyieR {
Adc12rdyieR::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1 - ADC12 Interrupt enable for the inside of window of the Window comparator"]
#[inline(always)]
pub fn adc12inie(&mut self) -> Adc12inieW<'_, Adc12ier2Spec> {
Adc12inieW::new(self, 1)
}
#[doc = "Bit 2 - ADC12 Interrupt enable for lower threshold of the Window comparator"]
#[inline(always)]
pub fn adc12loie(&mut self) -> Adc12loieW<'_, Adc12ier2Spec> {
Adc12loieW::new(self, 2)
}
#[doc = "Bit 3 - ADC12 Interrupt enable for upper threshold of the Window comparator"]
#[inline(always)]
pub fn adc12hiie(&mut self) -> Adc12hiieW<'_, Adc12ier2Spec> {
Adc12hiieW::new(self, 3)
}
#[doc = "Bit 4 - ADC12 ADC12MEMx Overflow interrupt enable"]
#[inline(always)]
pub fn adc12ovie(&mut self) -> Adc12ovieW<'_, Adc12ier2Spec> {
Adc12ovieW::new(self, 4)
}
#[doc = "Bit 5 - ADC12 Timer Overflow interrupt enable"]
#[inline(always)]
pub fn adc12tovie(&mut self) -> Adc12tovieW<'_, Adc12ier2Spec> {
Adc12tovieW::new(self, 5)
}
#[doc = "Bit 6 - ADC12 local buffered reference ready interrupt enable"]
#[inline(always)]
pub fn adc12rdyie(&mut self) -> Adc12rdyieW<'_, Adc12ier2Spec> {
Adc12rdyieW::new(self, 6)
}
}
#[doc = "ADC12 B Interrupt Enable 2\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12ier2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12ier2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12ier2Spec;
impl crate::RegisterSpec for Adc12ier2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12ier2::R`](R) reader structure"]
impl crate::Readable for Adc12ier2Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12ier2::W`](W) writer structure"]
impl crate::Writable for Adc12ier2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12IER2 to value 0"]
impl crate::Resettable for Adc12ier2Spec {}
}
#[doc = "ADC12IV (rw) register accessor: ADC12 B Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12iv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12iv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12iv`] module"]
#[doc(alias = "ADC12IV")]
pub type Adc12iv = crate::Reg<adc12iv::Adc12ivSpec>;
#[doc = "ADC12 B Interrupt Vector Word"]
pub mod adc12iv {
#[doc = "Register `ADC12IV` reader"]
pub type R = crate::R<Adc12ivSpec>;
#[doc = "Register `ADC12IV` writer"]
pub type W = crate::W<Adc12ivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 B Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12iv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12iv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12ivSpec;
impl crate::RegisterSpec for Adc12ivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12iv::R`](R) reader structure"]
impl crate::Readable for Adc12ivSpec {}
#[doc = "`write(|w| ..)` method takes [`adc12iv::W`](W) writer structure"]
impl crate::Writable for Adc12ivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12IV to value 0"]
impl crate::Resettable for Adc12ivSpec {}
}
#[doc = "ADC12MCTL0 (rw) register accessor: ADC12 Memory Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl0`] module"]
#[doc(alias = "ADC12MCTL0")]
pub type Adc12mctl0 = crate::Reg<adc12mctl0::Adc12mctl0Spec>;
#[doc = "ADC12 Memory Control 0"]
pub mod adc12mctl0 {
#[doc = "Register `ADC12MCTL0` reader"]
pub type R = crate::R<Adc12mctl0Spec>;
#[doc = "Register `ADC12MCTL0` writer"]
pub type W = crate::W<Adc12mctl0Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl0Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl0Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl0Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl0Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl0Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl0Spec;
impl crate::RegisterSpec for Adc12mctl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl0::R`](R) reader structure"]
impl crate::Readable for Adc12mctl0Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl0::W`](W) writer structure"]
impl crate::Writable for Adc12mctl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL0 to value 0"]
impl crate::Resettable for Adc12mctl0Spec {}
}
#[doc = "ADC12MCTL1 (rw) register accessor: ADC12 Memory Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl1`] module"]
#[doc(alias = "ADC12MCTL1")]
pub type Adc12mctl1 = crate::Reg<adc12mctl1::Adc12mctl1Spec>;
#[doc = "ADC12 Memory Control 1"]
pub mod adc12mctl1 {
#[doc = "Register `ADC12MCTL1` reader"]
pub type R = crate::R<Adc12mctl1Spec>;
#[doc = "Register `ADC12MCTL1` writer"]
pub type W = crate::W<Adc12mctl1Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl1Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl1Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl1Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl1Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl1Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl1Spec;
impl crate::RegisterSpec for Adc12mctl1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl1::R`](R) reader structure"]
impl crate::Readable for Adc12mctl1Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl1::W`](W) writer structure"]
impl crate::Writable for Adc12mctl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL1 to value 0"]
impl crate::Resettable for Adc12mctl1Spec {}
}
#[doc = "ADC12MCTL2 (rw) register accessor: ADC12 Memory Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl2`] module"]
#[doc(alias = "ADC12MCTL2")]
pub type Adc12mctl2 = crate::Reg<adc12mctl2::Adc12mctl2Spec>;
#[doc = "ADC12 Memory Control 2"]
pub mod adc12mctl2 {
#[doc = "Register `ADC12MCTL2` reader"]
pub type R = crate::R<Adc12mctl2Spec>;
#[doc = "Register `ADC12MCTL2` writer"]
pub type W = crate::W<Adc12mctl2Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl2Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl2Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl2Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl2Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl2Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl2Spec;
impl crate::RegisterSpec for Adc12mctl2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl2::R`](R) reader structure"]
impl crate::Readable for Adc12mctl2Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl2::W`](W) writer structure"]
impl crate::Writable for Adc12mctl2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL2 to value 0"]
impl crate::Resettable for Adc12mctl2Spec {}
}
#[doc = "ADC12MCTL3 (rw) register accessor: ADC12 Memory Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl3`] module"]
#[doc(alias = "ADC12MCTL3")]
pub type Adc12mctl3 = crate::Reg<adc12mctl3::Adc12mctl3Spec>;
#[doc = "ADC12 Memory Control 3"]
pub mod adc12mctl3 {
#[doc = "Register `ADC12MCTL3` reader"]
pub type R = crate::R<Adc12mctl3Spec>;
#[doc = "Register `ADC12MCTL3` writer"]
pub type W = crate::W<Adc12mctl3Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl3Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl3Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl3Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl3Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl3Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl3Spec;
impl crate::RegisterSpec for Adc12mctl3Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl3::R`](R) reader structure"]
impl crate::Readable for Adc12mctl3Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl3::W`](W) writer structure"]
impl crate::Writable for Adc12mctl3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL3 to value 0"]
impl crate::Resettable for Adc12mctl3Spec {}
}
#[doc = "ADC12MCTL4 (rw) register accessor: ADC12 Memory Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl4`] module"]
#[doc(alias = "ADC12MCTL4")]
pub type Adc12mctl4 = crate::Reg<adc12mctl4::Adc12mctl4Spec>;
#[doc = "ADC12 Memory Control 4"]
pub mod adc12mctl4 {
#[doc = "Register `ADC12MCTL4` reader"]
pub type R = crate::R<Adc12mctl4Spec>;
#[doc = "Register `ADC12MCTL4` writer"]
pub type W = crate::W<Adc12mctl4Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl4Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl4Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl4Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl4Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl4Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl4Spec;
impl crate::RegisterSpec for Adc12mctl4Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl4::R`](R) reader structure"]
impl crate::Readable for Adc12mctl4Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl4::W`](W) writer structure"]
impl crate::Writable for Adc12mctl4Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL4 to value 0"]
impl crate::Resettable for Adc12mctl4Spec {}
}
#[doc = "ADC12MCTL5 (rw) register accessor: ADC12 Memory Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl5`] module"]
#[doc(alias = "ADC12MCTL5")]
pub type Adc12mctl5 = crate::Reg<adc12mctl5::Adc12mctl5Spec>;
#[doc = "ADC12 Memory Control 5"]
pub mod adc12mctl5 {
#[doc = "Register `ADC12MCTL5` reader"]
pub type R = crate::R<Adc12mctl5Spec>;
#[doc = "Register `ADC12MCTL5` writer"]
pub type W = crate::W<Adc12mctl5Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl5Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl5Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl5Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl5Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl5Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl5Spec;
impl crate::RegisterSpec for Adc12mctl5Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl5::R`](R) reader structure"]
impl crate::Readable for Adc12mctl5Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl5::W`](W) writer structure"]
impl crate::Writable for Adc12mctl5Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL5 to value 0"]
impl crate::Resettable for Adc12mctl5Spec {}
}
#[doc = "ADC12MCTL6 (rw) register accessor: ADC12 Memory Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl6`] module"]
#[doc(alias = "ADC12MCTL6")]
pub type Adc12mctl6 = crate::Reg<adc12mctl6::Adc12mctl6Spec>;
#[doc = "ADC12 Memory Control 6"]
pub mod adc12mctl6 {
#[doc = "Register `ADC12MCTL6` reader"]
pub type R = crate::R<Adc12mctl6Spec>;
#[doc = "Register `ADC12MCTL6` writer"]
pub type W = crate::W<Adc12mctl6Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl6Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl6Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl6Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl6Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl6Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl6Spec;
impl crate::RegisterSpec for Adc12mctl6Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl6::R`](R) reader structure"]
impl crate::Readable for Adc12mctl6Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl6::W`](W) writer structure"]
impl crate::Writable for Adc12mctl6Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL6 to value 0"]
impl crate::Resettable for Adc12mctl6Spec {}
}
#[doc = "ADC12MCTL7 (rw) register accessor: ADC12 Memory Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl7`] module"]
#[doc(alias = "ADC12MCTL7")]
pub type Adc12mctl7 = crate::Reg<adc12mctl7::Adc12mctl7Spec>;
#[doc = "ADC12 Memory Control 7"]
pub mod adc12mctl7 {
#[doc = "Register `ADC12MCTL7` reader"]
pub type R = crate::R<Adc12mctl7Spec>;
#[doc = "Register `ADC12MCTL7` writer"]
pub type W = crate::W<Adc12mctl7Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl7Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl7Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl7Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl7Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl7Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl7Spec;
impl crate::RegisterSpec for Adc12mctl7Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl7::R`](R) reader structure"]
impl crate::Readable for Adc12mctl7Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl7::W`](W) writer structure"]
impl crate::Writable for Adc12mctl7Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL7 to value 0"]
impl crate::Resettable for Adc12mctl7Spec {}
}
#[doc = "ADC12MCTL8 (rw) register accessor: ADC12 Memory Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl8`] module"]
#[doc(alias = "ADC12MCTL8")]
pub type Adc12mctl8 = crate::Reg<adc12mctl8::Adc12mctl8Spec>;
#[doc = "ADC12 Memory Control 8"]
pub mod adc12mctl8 {
#[doc = "Register `ADC12MCTL8` reader"]
pub type R = crate::R<Adc12mctl8Spec>;
#[doc = "Register `ADC12MCTL8` writer"]
pub type W = crate::W<Adc12mctl8Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl8Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl8Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl8Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl8Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl8Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 8\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl8Spec;
impl crate::RegisterSpec for Adc12mctl8Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl8::R`](R) reader structure"]
impl crate::Readable for Adc12mctl8Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl8::W`](W) writer structure"]
impl crate::Writable for Adc12mctl8Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL8 to value 0"]
impl crate::Resettable for Adc12mctl8Spec {}
}
#[doc = "ADC12MCTL9 (rw) register accessor: ADC12 Memory Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl9`] module"]
#[doc(alias = "ADC12MCTL9")]
pub type Adc12mctl9 = crate::Reg<adc12mctl9::Adc12mctl9Spec>;
#[doc = "ADC12 Memory Control 9"]
pub mod adc12mctl9 {
#[doc = "Register `ADC12MCTL9` reader"]
pub type R = crate::R<Adc12mctl9Spec>;
#[doc = "Register `ADC12MCTL9` writer"]
pub type W = crate::W<Adc12mctl9Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl9Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl9Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl9Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl9Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl9Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 9\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl9Spec;
impl crate::RegisterSpec for Adc12mctl9Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl9::R`](R) reader structure"]
impl crate::Readable for Adc12mctl9Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl9::W`](W) writer structure"]
impl crate::Writable for Adc12mctl9Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL9 to value 0"]
impl crate::Resettable for Adc12mctl9Spec {}
}
#[doc = "ADC12MCTL10 (rw) register accessor: ADC12 Memory Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl10`] module"]
#[doc(alias = "ADC12MCTL10")]
pub type Adc12mctl10 = crate::Reg<adc12mctl10::Adc12mctl10Spec>;
#[doc = "ADC12 Memory Control 10"]
pub mod adc12mctl10 {
#[doc = "Register `ADC12MCTL10` reader"]
pub type R = crate::R<Adc12mctl10Spec>;
#[doc = "Register `ADC12MCTL10` writer"]
pub type W = crate::W<Adc12mctl10Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl10Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl10Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl10Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl10Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl10Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 10\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl10Spec;
impl crate::RegisterSpec for Adc12mctl10Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl10::R`](R) reader structure"]
impl crate::Readable for Adc12mctl10Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl10::W`](W) writer structure"]
impl crate::Writable for Adc12mctl10Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL10 to value 0"]
impl crate::Resettable for Adc12mctl10Spec {}
}
#[doc = "ADC12MCTL11 (rw) register accessor: ADC12 Memory Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl11`] module"]
#[doc(alias = "ADC12MCTL11")]
pub type Adc12mctl11 = crate::Reg<adc12mctl11::Adc12mctl11Spec>;
#[doc = "ADC12 Memory Control 11"]
pub mod adc12mctl11 {
#[doc = "Register `ADC12MCTL11` reader"]
pub type R = crate::R<Adc12mctl11Spec>;
#[doc = "Register `ADC12MCTL11` writer"]
pub type W = crate::W<Adc12mctl11Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl11Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl11Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl11Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl11Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl11Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 11\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl11Spec;
impl crate::RegisterSpec for Adc12mctl11Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl11::R`](R) reader structure"]
impl crate::Readable for Adc12mctl11Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl11::W`](W) writer structure"]
impl crate::Writable for Adc12mctl11Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL11 to value 0"]
impl crate::Resettable for Adc12mctl11Spec {}
}
#[doc = "ADC12MCTL12 (rw) register accessor: ADC12 Memory Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl12`] module"]
#[doc(alias = "ADC12MCTL12")]
pub type Adc12mctl12 = crate::Reg<adc12mctl12::Adc12mctl12Spec>;
#[doc = "ADC12 Memory Control 12"]
pub mod adc12mctl12 {
#[doc = "Register `ADC12MCTL12` reader"]
pub type R = crate::R<Adc12mctl12Spec>;
#[doc = "Register `ADC12MCTL12` writer"]
pub type W = crate::W<Adc12mctl12Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl12Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl12Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl12Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl12Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl12Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 12\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl12Spec;
impl crate::RegisterSpec for Adc12mctl12Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl12::R`](R) reader structure"]
impl crate::Readable for Adc12mctl12Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl12::W`](W) writer structure"]
impl crate::Writable for Adc12mctl12Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL12 to value 0"]
impl crate::Resettable for Adc12mctl12Spec {}
}
#[doc = "ADC12MCTL13 (rw) register accessor: ADC12 Memory Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl13`] module"]
#[doc(alias = "ADC12MCTL13")]
pub type Adc12mctl13 = crate::Reg<adc12mctl13::Adc12mctl13Spec>;
#[doc = "ADC12 Memory Control 13"]
pub mod adc12mctl13 {
#[doc = "Register `ADC12MCTL13` reader"]
pub type R = crate::R<Adc12mctl13Spec>;
#[doc = "Register `ADC12MCTL13` writer"]
pub type W = crate::W<Adc12mctl13Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl13Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl13Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl13Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl13Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl13Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 13\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl13Spec;
impl crate::RegisterSpec for Adc12mctl13Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl13::R`](R) reader structure"]
impl crate::Readable for Adc12mctl13Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl13::W`](W) writer structure"]
impl crate::Writable for Adc12mctl13Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL13 to value 0"]
impl crate::Resettable for Adc12mctl13Spec {}
}
#[doc = "ADC12MCTL14 (rw) register accessor: ADC12 Memory Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl14`] module"]
#[doc(alias = "ADC12MCTL14")]
pub type Adc12mctl14 = crate::Reg<adc12mctl14::Adc12mctl14Spec>;
#[doc = "ADC12 Memory Control 14"]
pub mod adc12mctl14 {
#[doc = "Register `ADC12MCTL14` reader"]
pub type R = crate::R<Adc12mctl14Spec>;
#[doc = "Register `ADC12MCTL14` writer"]
pub type W = crate::W<Adc12mctl14Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl14Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl14Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl14Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl14Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl14Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 14\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl14Spec;
impl crate::RegisterSpec for Adc12mctl14Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl14::R`](R) reader structure"]
impl crate::Readable for Adc12mctl14Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl14::W`](W) writer structure"]
impl crate::Writable for Adc12mctl14Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL14 to value 0"]
impl crate::Resettable for Adc12mctl14Spec {}
}
#[doc = "ADC12MCTL15 (rw) register accessor: ADC12 Memory Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl15`] module"]
#[doc(alias = "ADC12MCTL15")]
pub type Adc12mctl15 = crate::Reg<adc12mctl15::Adc12mctl15Spec>;
#[doc = "ADC12 Memory Control 15"]
pub mod adc12mctl15 {
#[doc = "Register `ADC12MCTL15` reader"]
pub type R = crate::R<Adc12mctl15Spec>;
#[doc = "Register `ADC12MCTL15` writer"]
pub type W = crate::W<Adc12mctl15Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl15Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl15Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl15Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl15Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl15Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 15\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl15Spec;
impl crate::RegisterSpec for Adc12mctl15Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl15::R`](R) reader structure"]
impl crate::Readable for Adc12mctl15Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl15::W`](W) writer structure"]
impl crate::Writable for Adc12mctl15Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL15 to value 0"]
impl crate::Resettable for Adc12mctl15Spec {}
}
#[doc = "ADC12MCTL16 (rw) register accessor: ADC12 Memory Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl16`] module"]
#[doc(alias = "ADC12MCTL16")]
pub type Adc12mctl16 = crate::Reg<adc12mctl16::Adc12mctl16Spec>;
#[doc = "ADC12 Memory Control 16"]
pub mod adc12mctl16 {
#[doc = "Register `ADC12MCTL16` reader"]
pub type R = crate::R<Adc12mctl16Spec>;
#[doc = "Register `ADC12MCTL16` writer"]
pub type W = crate::W<Adc12mctl16Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl16Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl16Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl16Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl16Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl16Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 16\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl16Spec;
impl crate::RegisterSpec for Adc12mctl16Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl16::R`](R) reader structure"]
impl crate::Readable for Adc12mctl16Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl16::W`](W) writer structure"]
impl crate::Writable for Adc12mctl16Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL16 to value 0"]
impl crate::Resettable for Adc12mctl16Spec {}
}
#[doc = "ADC12MCTL17 (rw) register accessor: ADC12 Memory Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl17`] module"]
#[doc(alias = "ADC12MCTL17")]
pub type Adc12mctl17 = crate::Reg<adc12mctl17::Adc12mctl17Spec>;
#[doc = "ADC12 Memory Control 17"]
pub mod adc12mctl17 {
#[doc = "Register `ADC12MCTL17` reader"]
pub type R = crate::R<Adc12mctl17Spec>;
#[doc = "Register `ADC12MCTL17` writer"]
pub type W = crate::W<Adc12mctl17Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl17Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl17Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl17Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl17Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl17Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 17\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl17Spec;
impl crate::RegisterSpec for Adc12mctl17Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl17::R`](R) reader structure"]
impl crate::Readable for Adc12mctl17Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl17::W`](W) writer structure"]
impl crate::Writable for Adc12mctl17Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL17 to value 0"]
impl crate::Resettable for Adc12mctl17Spec {}
}
#[doc = "ADC12MCTL18 (rw) register accessor: ADC12 Memory Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl18`] module"]
#[doc(alias = "ADC12MCTL18")]
pub type Adc12mctl18 = crate::Reg<adc12mctl18::Adc12mctl18Spec>;
#[doc = "ADC12 Memory Control 18"]
pub mod adc12mctl18 {
#[doc = "Register `ADC12MCTL18` reader"]
pub type R = crate::R<Adc12mctl18Spec>;
#[doc = "Register `ADC12MCTL18` writer"]
pub type W = crate::W<Adc12mctl18Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl18Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl18Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl18Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl18Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl18Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 18\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl18Spec;
impl crate::RegisterSpec for Adc12mctl18Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl18::R`](R) reader structure"]
impl crate::Readable for Adc12mctl18Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl18::W`](W) writer structure"]
impl crate::Writable for Adc12mctl18Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL18 to value 0"]
impl crate::Resettable for Adc12mctl18Spec {}
}
#[doc = "ADC12MCTL19 (rw) register accessor: ADC12 Memory Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl19`] module"]
#[doc(alias = "ADC12MCTL19")]
pub type Adc12mctl19 = crate::Reg<adc12mctl19::Adc12mctl19Spec>;
#[doc = "ADC12 Memory Control 19"]
pub mod adc12mctl19 {
#[doc = "Register `ADC12MCTL19` reader"]
pub type R = crate::R<Adc12mctl19Spec>;
#[doc = "Register `ADC12MCTL19` writer"]
pub type W = crate::W<Adc12mctl19Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl19Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl19Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl19Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl19Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl19Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 19\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl19Spec;
impl crate::RegisterSpec for Adc12mctl19Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl19::R`](R) reader structure"]
impl crate::Readable for Adc12mctl19Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl19::W`](W) writer structure"]
impl crate::Writable for Adc12mctl19Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL19 to value 0"]
impl crate::Resettable for Adc12mctl19Spec {}
}
#[doc = "ADC12MCTL20 (rw) register accessor: ADC12 Memory Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl20`] module"]
#[doc(alias = "ADC12MCTL20")]
pub type Adc12mctl20 = crate::Reg<adc12mctl20::Adc12mctl20Spec>;
#[doc = "ADC12 Memory Control 20"]
pub mod adc12mctl20 {
#[doc = "Register `ADC12MCTL20` reader"]
pub type R = crate::R<Adc12mctl20Spec>;
#[doc = "Register `ADC12MCTL20` writer"]
pub type W = crate::W<Adc12mctl20Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl20Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl20Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl20Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl20Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl20Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 20\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl20Spec;
impl crate::RegisterSpec for Adc12mctl20Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl20::R`](R) reader structure"]
impl crate::Readable for Adc12mctl20Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl20::W`](W) writer structure"]
impl crate::Writable for Adc12mctl20Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL20 to value 0"]
impl crate::Resettable for Adc12mctl20Spec {}
}
#[doc = "ADC12MCTL21 (rw) register accessor: ADC12 Memory Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl21`] module"]
#[doc(alias = "ADC12MCTL21")]
pub type Adc12mctl21 = crate::Reg<adc12mctl21::Adc12mctl21Spec>;
#[doc = "ADC12 Memory Control 21"]
pub mod adc12mctl21 {
#[doc = "Register `ADC12MCTL21` reader"]
pub type R = crate::R<Adc12mctl21Spec>;
#[doc = "Register `ADC12MCTL21` writer"]
pub type W = crate::W<Adc12mctl21Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl21Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl21Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl21Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl21Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl21Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 21\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl21Spec;
impl crate::RegisterSpec for Adc12mctl21Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl21::R`](R) reader structure"]
impl crate::Readable for Adc12mctl21Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl21::W`](W) writer structure"]
impl crate::Writable for Adc12mctl21Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL21 to value 0"]
impl crate::Resettable for Adc12mctl21Spec {}
}
#[doc = "ADC12MCTL22 (rw) register accessor: ADC12 Memory Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl22`] module"]
#[doc(alias = "ADC12MCTL22")]
pub type Adc12mctl22 = crate::Reg<adc12mctl22::Adc12mctl22Spec>;
#[doc = "ADC12 Memory Control 22"]
pub mod adc12mctl22 {
#[doc = "Register `ADC12MCTL22` reader"]
pub type R = crate::R<Adc12mctl22Spec>;
#[doc = "Register `ADC12MCTL22` writer"]
pub type W = crate::W<Adc12mctl22Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl22Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl22Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl22Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl22Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl22Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 22\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl22Spec;
impl crate::RegisterSpec for Adc12mctl22Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl22::R`](R) reader structure"]
impl crate::Readable for Adc12mctl22Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl22::W`](W) writer structure"]
impl crate::Writable for Adc12mctl22Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL22 to value 0"]
impl crate::Resettable for Adc12mctl22Spec {}
}
#[doc = "ADC12MCTL23 (rw) register accessor: ADC12 Memory Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl23`] module"]
#[doc(alias = "ADC12MCTL23")]
pub type Adc12mctl23 = crate::Reg<adc12mctl23::Adc12mctl23Spec>;
#[doc = "ADC12 Memory Control 23"]
pub mod adc12mctl23 {
#[doc = "Register `ADC12MCTL23` reader"]
pub type R = crate::R<Adc12mctl23Spec>;
#[doc = "Register `ADC12MCTL23` writer"]
pub type W = crate::W<Adc12mctl23Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl23Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl23Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl23Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl23Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl23Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 23\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl23Spec;
impl crate::RegisterSpec for Adc12mctl23Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl23::R`](R) reader structure"]
impl crate::Readable for Adc12mctl23Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl23::W`](W) writer structure"]
impl crate::Writable for Adc12mctl23Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL23 to value 0"]
impl crate::Resettable for Adc12mctl23Spec {}
}
#[doc = "ADC12MCTL24 (rw) register accessor: ADC12 Memory Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl24`] module"]
#[doc(alias = "ADC12MCTL24")]
pub type Adc12mctl24 = crate::Reg<adc12mctl24::Adc12mctl24Spec>;
#[doc = "ADC12 Memory Control 24"]
pub mod adc12mctl24 {
#[doc = "Register `ADC12MCTL24` reader"]
pub type R = crate::R<Adc12mctl24Spec>;
#[doc = "Register `ADC12MCTL24` writer"]
pub type W = crate::W<Adc12mctl24Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl24Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl24Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl24Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl24Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl24Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 24\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl24Spec;
impl crate::RegisterSpec for Adc12mctl24Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl24::R`](R) reader structure"]
impl crate::Readable for Adc12mctl24Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl24::W`](W) writer structure"]
impl crate::Writable for Adc12mctl24Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL24 to value 0"]
impl crate::Resettable for Adc12mctl24Spec {}
}
#[doc = "ADC12MCTL25 (rw) register accessor: ADC12 Memory Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl25`] module"]
#[doc(alias = "ADC12MCTL25")]
pub type Adc12mctl25 = crate::Reg<adc12mctl25::Adc12mctl25Spec>;
#[doc = "ADC12 Memory Control 25"]
pub mod adc12mctl25 {
#[doc = "Register `ADC12MCTL25` reader"]
pub type R = crate::R<Adc12mctl25Spec>;
#[doc = "Register `ADC12MCTL25` writer"]
pub type W = crate::W<Adc12mctl25Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl25Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl25Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl25Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl25Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl25Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 25\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl25Spec;
impl crate::RegisterSpec for Adc12mctl25Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl25::R`](R) reader structure"]
impl crate::Readable for Adc12mctl25Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl25::W`](W) writer structure"]
impl crate::Writable for Adc12mctl25Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL25 to value 0"]
impl crate::Resettable for Adc12mctl25Spec {}
}
#[doc = "ADC12MCTL26 (rw) register accessor: ADC12 Memory Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl26`] module"]
#[doc(alias = "ADC12MCTL26")]
pub type Adc12mctl26 = crate::Reg<adc12mctl26::Adc12mctl26Spec>;
#[doc = "ADC12 Memory Control 26"]
pub mod adc12mctl26 {
#[doc = "Register `ADC12MCTL26` reader"]
pub type R = crate::R<Adc12mctl26Spec>;
#[doc = "Register `ADC12MCTL26` writer"]
pub type W = crate::W<Adc12mctl26Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl26Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl26Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl26Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl26Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl26Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 26\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl26Spec;
impl crate::RegisterSpec for Adc12mctl26Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl26::R`](R) reader structure"]
impl crate::Readable for Adc12mctl26Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl26::W`](W) writer structure"]
impl crate::Writable for Adc12mctl26Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL26 to value 0"]
impl crate::Resettable for Adc12mctl26Spec {}
}
#[doc = "ADC12MCTL27 (rw) register accessor: ADC12 Memory Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl27`] module"]
#[doc(alias = "ADC12MCTL27")]
pub type Adc12mctl27 = crate::Reg<adc12mctl27::Adc12mctl27Spec>;
#[doc = "ADC12 Memory Control 27"]
pub mod adc12mctl27 {
#[doc = "Register `ADC12MCTL27` reader"]
pub type R = crate::R<Adc12mctl27Spec>;
#[doc = "Register `ADC12MCTL27` writer"]
pub type W = crate::W<Adc12mctl27Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl27Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl27Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl27Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl27Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl27Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 27\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl27Spec;
impl crate::RegisterSpec for Adc12mctl27Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl27::R`](R) reader structure"]
impl crate::Readable for Adc12mctl27Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl27::W`](W) writer structure"]
impl crate::Writable for Adc12mctl27Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL27 to value 0"]
impl crate::Resettable for Adc12mctl27Spec {}
}
#[doc = "ADC12MCTL28 (rw) register accessor: ADC12 Memory Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl28`] module"]
#[doc(alias = "ADC12MCTL28")]
pub type Adc12mctl28 = crate::Reg<adc12mctl28::Adc12mctl28Spec>;
#[doc = "ADC12 Memory Control 28"]
pub mod adc12mctl28 {
#[doc = "Register `ADC12MCTL28` reader"]
pub type R = crate::R<Adc12mctl28Spec>;
#[doc = "Register `ADC12MCTL28` writer"]
pub type W = crate::W<Adc12mctl28Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl28Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl28Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl28Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl28Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl28Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 28\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl28Spec;
impl crate::RegisterSpec for Adc12mctl28Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl28::R`](R) reader structure"]
impl crate::Readable for Adc12mctl28Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl28::W`](W) writer structure"]
impl crate::Writable for Adc12mctl28Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL28 to value 0"]
impl crate::Resettable for Adc12mctl28Spec {}
}
#[doc = "ADC12MCTL29 (rw) register accessor: ADC12 Memory Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl29`] module"]
#[doc(alias = "ADC12MCTL29")]
pub type Adc12mctl29 = crate::Reg<adc12mctl29::Adc12mctl29Spec>;
#[doc = "ADC12 Memory Control 29"]
pub mod adc12mctl29 {
#[doc = "Register `ADC12MCTL29` reader"]
pub type R = crate::R<Adc12mctl29Spec>;
#[doc = "Register `ADC12MCTL29` writer"]
pub type W = crate::W<Adc12mctl29Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl29Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl29Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl29Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl29Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl29Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 29\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl29Spec;
impl crate::RegisterSpec for Adc12mctl29Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl29::R`](R) reader structure"]
impl crate::Readable for Adc12mctl29Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl29::W`](W) writer structure"]
impl crate::Writable for Adc12mctl29Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL29 to value 0"]
impl crate::Resettable for Adc12mctl29Spec {}
}
#[doc = "ADC12MCTL30 (rw) register accessor: ADC12 Memory Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl30`] module"]
#[doc(alias = "ADC12MCTL30")]
pub type Adc12mctl30 = crate::Reg<adc12mctl30::Adc12mctl30Spec>;
#[doc = "ADC12 Memory Control 30"]
pub mod adc12mctl30 {
#[doc = "Register `ADC12MCTL30` reader"]
pub type R = crate::R<Adc12mctl30Spec>;
#[doc = "Register `ADC12MCTL30` writer"]
pub type W = crate::W<Adc12mctl30Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl30Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl30Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl30Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl30Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl30Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 30\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl30Spec;
impl crate::RegisterSpec for Adc12mctl30Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl30::R`](R) reader structure"]
impl crate::Readable for Adc12mctl30Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl30::W`](W) writer structure"]
impl crate::Writable for Adc12mctl30Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL30 to value 0"]
impl crate::Resettable for Adc12mctl30Spec {}
}
#[doc = "ADC12MCTL31 (rw) register accessor: ADC12 Memory Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mctl31`] module"]
#[doc(alias = "ADC12MCTL31")]
pub type Adc12mctl31 = crate::Reg<adc12mctl31::Adc12mctl31Spec>;
#[doc = "ADC12 Memory Control 31"]
pub mod adc12mctl31 {
#[doc = "Register `ADC12MCTL31` reader"]
pub type R = crate::R<Adc12mctl31Spec>;
#[doc = "Register `ADC12MCTL31` writer"]
pub type W = crate::W<Adc12mctl31Spec>;
#[doc = "ADC12 Input Channel Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12inch {
#[doc = "0: ADC12 Input Channel 0"]
Adc12inch0 = 0,
#[doc = "1: ADC12 Input Channel 1"]
Adc12inch1 = 1,
#[doc = "2: ADC12 Input Channel 2"]
Adc12inch2 = 2,
#[doc = "3: ADC12 Input Channel 3"]
Adc12inch3 = 3,
#[doc = "4: ADC12 Input Channel 4"]
Adc12inch4 = 4,
#[doc = "5: ADC12 Input Channel 5"]
Adc12inch5 = 5,
#[doc = "6: ADC12 Input Channel 6"]
Adc12inch6 = 6,
#[doc = "7: ADC12 Input Channel 7"]
Adc12inch7 = 7,
#[doc = "8: ADC12 Input Channel 8"]
Adc12inch8 = 8,
#[doc = "9: ADC12 Input Channel 9"]
Adc12inch9 = 9,
#[doc = "10: ADC12 Input Channel 10"]
Adc12inch10 = 10,
#[doc = "11: ADC12 Input Channel 11"]
Adc12inch11 = 11,
#[doc = "12: ADC12 Input Channel 12"]
Adc12inch12 = 12,
#[doc = "13: ADC12 Input Channel 13"]
Adc12inch13 = 13,
#[doc = "14: ADC12 Input Channel 14"]
Adc12inch14 = 14,
#[doc = "15: ADC12 Input Channel 15"]
Adc12inch15 = 15,
#[doc = "16: ADC12 Input Channel 16"]
Adc12inch16 = 16,
#[doc = "17: ADC12 Input Channel 17"]
Adc12inch17 = 17,
#[doc = "18: ADC12 Input Channel 18"]
Adc12inch18 = 18,
#[doc = "19: ADC12 Input Channel 19"]
Adc12inch19 = 19,
#[doc = "20: ADC12 Input Channel 20"]
Adc12inch20 = 20,
#[doc = "21: ADC12 Input Channel 21"]
Adc12inch21 = 21,
#[doc = "22: ADC12 Input Channel 22"]
Adc12inch22 = 22,
#[doc = "23: ADC12 Input Channel 23"]
Adc12inch23 = 23,
#[doc = "24: ADC12 Input Channel 24"]
Adc12inch24 = 24,
#[doc = "25: ADC12 Input Channel 25"]
Adc12inch25 = 25,
#[doc = "26: ADC12 Input Channel 26"]
Adc12inch26 = 26,
#[doc = "27: ADC12 Input Channel 27"]
Adc12inch27 = 27,
#[doc = "28: ADC12 Input Channel 28"]
Adc12inch28 = 28,
#[doc = "29: ADC12 Input Channel 29"]
Adc12inch29 = 29,
#[doc = "30: ADC12 Input Channel 30"]
Adc12inch30 = 30,
#[doc = "31: ADC12 Input Channel 31"]
Adc12inch31 = 31,
}
impl From<Adc12inch> for u8 {
#[inline(always)]
fn from(variant: Adc12inch) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12inch {
type Ux = u8;
}
impl crate::IsEnum for Adc12inch {}
#[doc = "Field `ADC12INCH` reader - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchR = crate::FieldReader<Adc12inch>;
impl Adc12inchR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12inch {
match self.bits {
0 => Adc12inch::Adc12inch0,
1 => Adc12inch::Adc12inch1,
2 => Adc12inch::Adc12inch2,
3 => Adc12inch::Adc12inch3,
4 => Adc12inch::Adc12inch4,
5 => Adc12inch::Adc12inch5,
6 => Adc12inch::Adc12inch6,
7 => Adc12inch::Adc12inch7,
8 => Adc12inch::Adc12inch8,
9 => Adc12inch::Adc12inch9,
10 => Adc12inch::Adc12inch10,
11 => Adc12inch::Adc12inch11,
12 => Adc12inch::Adc12inch12,
13 => Adc12inch::Adc12inch13,
14 => Adc12inch::Adc12inch14,
15 => Adc12inch::Adc12inch15,
16 => Adc12inch::Adc12inch16,
17 => Adc12inch::Adc12inch17,
18 => Adc12inch::Adc12inch18,
19 => Adc12inch::Adc12inch19,
20 => Adc12inch::Adc12inch20,
21 => Adc12inch::Adc12inch21,
22 => Adc12inch::Adc12inch22,
23 => Adc12inch::Adc12inch23,
24 => Adc12inch::Adc12inch24,
25 => Adc12inch::Adc12inch25,
26 => Adc12inch::Adc12inch26,
27 => Adc12inch::Adc12inch27,
28 => Adc12inch::Adc12inch28,
29 => Adc12inch::Adc12inch29,
30 => Adc12inch::Adc12inch30,
31 => Adc12inch::Adc12inch31,
_ => unreachable!(),
}
}
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn is_adc12inch_0(&self) -> bool {
*self == Adc12inch::Adc12inch0
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn is_adc12inch_1(&self) -> bool {
*self == Adc12inch::Adc12inch1
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn is_adc12inch_2(&self) -> bool {
*self == Adc12inch::Adc12inch2
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn is_adc12inch_3(&self) -> bool {
*self == Adc12inch::Adc12inch3
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn is_adc12inch_4(&self) -> bool {
*self == Adc12inch::Adc12inch4
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn is_adc12inch_5(&self) -> bool {
*self == Adc12inch::Adc12inch5
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn is_adc12inch_6(&self) -> bool {
*self == Adc12inch::Adc12inch6
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn is_adc12inch_7(&self) -> bool {
*self == Adc12inch::Adc12inch7
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn is_adc12inch_8(&self) -> bool {
*self == Adc12inch::Adc12inch8
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn is_adc12inch_9(&self) -> bool {
*self == Adc12inch::Adc12inch9
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn is_adc12inch_10(&self) -> bool {
*self == Adc12inch::Adc12inch10
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn is_adc12inch_11(&self) -> bool {
*self == Adc12inch::Adc12inch11
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn is_adc12inch_12(&self) -> bool {
*self == Adc12inch::Adc12inch12
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn is_adc12inch_13(&self) -> bool {
*self == Adc12inch::Adc12inch13
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn is_adc12inch_14(&self) -> bool {
*self == Adc12inch::Adc12inch14
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn is_adc12inch_15(&self) -> bool {
*self == Adc12inch::Adc12inch15
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn is_adc12inch_16(&self) -> bool {
*self == Adc12inch::Adc12inch16
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn is_adc12inch_17(&self) -> bool {
*self == Adc12inch::Adc12inch17
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn is_adc12inch_18(&self) -> bool {
*self == Adc12inch::Adc12inch18
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn is_adc12inch_19(&self) -> bool {
*self == Adc12inch::Adc12inch19
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn is_adc12inch_20(&self) -> bool {
*self == Adc12inch::Adc12inch20
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn is_adc12inch_21(&self) -> bool {
*self == Adc12inch::Adc12inch21
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn is_adc12inch_22(&self) -> bool {
*self == Adc12inch::Adc12inch22
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn is_adc12inch_23(&self) -> bool {
*self == Adc12inch::Adc12inch23
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn is_adc12inch_24(&self) -> bool {
*self == Adc12inch::Adc12inch24
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn is_adc12inch_25(&self) -> bool {
*self == Adc12inch::Adc12inch25
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn is_adc12inch_26(&self) -> bool {
*self == Adc12inch::Adc12inch26
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn is_adc12inch_27(&self) -> bool {
*self == Adc12inch::Adc12inch27
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn is_adc12inch_28(&self) -> bool {
*self == Adc12inch::Adc12inch28
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn is_adc12inch_29(&self) -> bool {
*self == Adc12inch::Adc12inch29
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn is_adc12inch_30(&self) -> bool {
*self == Adc12inch::Adc12inch30
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn is_adc12inch_31(&self) -> bool {
*self == Adc12inch::Adc12inch31
}
}
#[doc = "Field `ADC12INCH` writer - ADC12 Input Channel Select Bit 0"]
pub type Adc12inchW<'a, REG> = crate::FieldWriter<'a, REG, 5, Adc12inch, crate::Safe>;
impl<'a, REG> Adc12inchW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Input Channel 0"]
#[inline(always)]
pub fn adc12inch_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch0)
}
#[doc = "ADC12 Input Channel 1"]
#[inline(always)]
pub fn adc12inch_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch1)
}
#[doc = "ADC12 Input Channel 2"]
#[inline(always)]
pub fn adc12inch_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch2)
}
#[doc = "ADC12 Input Channel 3"]
#[inline(always)]
pub fn adc12inch_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch3)
}
#[doc = "ADC12 Input Channel 4"]
#[inline(always)]
pub fn adc12inch_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch4)
}
#[doc = "ADC12 Input Channel 5"]
#[inline(always)]
pub fn adc12inch_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch5)
}
#[doc = "ADC12 Input Channel 6"]
#[inline(always)]
pub fn adc12inch_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch6)
}
#[doc = "ADC12 Input Channel 7"]
#[inline(always)]
pub fn adc12inch_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch7)
}
#[doc = "ADC12 Input Channel 8"]
#[inline(always)]
pub fn adc12inch_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch8)
}
#[doc = "ADC12 Input Channel 9"]
#[inline(always)]
pub fn adc12inch_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch9)
}
#[doc = "ADC12 Input Channel 10"]
#[inline(always)]
pub fn adc12inch_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch10)
}
#[doc = "ADC12 Input Channel 11"]
#[inline(always)]
pub fn adc12inch_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch11)
}
#[doc = "ADC12 Input Channel 12"]
#[inline(always)]
pub fn adc12inch_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch12)
}
#[doc = "ADC12 Input Channel 13"]
#[inline(always)]
pub fn adc12inch_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch13)
}
#[doc = "ADC12 Input Channel 14"]
#[inline(always)]
pub fn adc12inch_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch14)
}
#[doc = "ADC12 Input Channel 15"]
#[inline(always)]
pub fn adc12inch_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch15)
}
#[doc = "ADC12 Input Channel 16"]
#[inline(always)]
pub fn adc12inch_16(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch16)
}
#[doc = "ADC12 Input Channel 17"]
#[inline(always)]
pub fn adc12inch_17(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch17)
}
#[doc = "ADC12 Input Channel 18"]
#[inline(always)]
pub fn adc12inch_18(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch18)
}
#[doc = "ADC12 Input Channel 19"]
#[inline(always)]
pub fn adc12inch_19(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch19)
}
#[doc = "ADC12 Input Channel 20"]
#[inline(always)]
pub fn adc12inch_20(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch20)
}
#[doc = "ADC12 Input Channel 21"]
#[inline(always)]
pub fn adc12inch_21(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch21)
}
#[doc = "ADC12 Input Channel 22"]
#[inline(always)]
pub fn adc12inch_22(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch22)
}
#[doc = "ADC12 Input Channel 23"]
#[inline(always)]
pub fn adc12inch_23(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch23)
}
#[doc = "ADC12 Input Channel 24"]
#[inline(always)]
pub fn adc12inch_24(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch24)
}
#[doc = "ADC12 Input Channel 25"]
#[inline(always)]
pub fn adc12inch_25(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch25)
}
#[doc = "ADC12 Input Channel 26"]
#[inline(always)]
pub fn adc12inch_26(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch26)
}
#[doc = "ADC12 Input Channel 27"]
#[inline(always)]
pub fn adc12inch_27(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch27)
}
#[doc = "ADC12 Input Channel 28"]
#[inline(always)]
pub fn adc12inch_28(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch28)
}
#[doc = "ADC12 Input Channel 29"]
#[inline(always)]
pub fn adc12inch_29(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch29)
}
#[doc = "ADC12 Input Channel 30"]
#[inline(always)]
pub fn adc12inch_30(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch30)
}
#[doc = "ADC12 Input Channel 31"]
#[inline(always)]
pub fn adc12inch_31(self) -> &'a mut crate::W<REG> {
self.variant(Adc12inch::Adc12inch31)
}
}
#[doc = "Field `ADC12EOS` reader - ADC12 End of Sequence"]
pub type Adc12eosR = crate::BitReader;
#[doc = "Field `ADC12EOS` writer - ADC12 End of Sequence"]
pub type Adc12eosW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "ADC12 VR Select Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Adc12vrsel {
#[doc = "0: ADC12 Select Reference 0"]
Adc12vrsel0 = 0,
#[doc = "1: ADC12 Select Reference 1"]
Adc12vrsel1 = 1,
#[doc = "2: ADC12 Select Reference 2"]
Adc12vrsel2 = 2,
#[doc = "3: ADC12 Select Reference 3"]
Adc12vrsel3 = 3,
#[doc = "4: ADC12 Select Reference 4"]
Adc12vrsel4 = 4,
#[doc = "5: ADC12 Select Reference 5"]
Adc12vrsel5 = 5,
#[doc = "6: ADC12 Select Reference 6"]
Adc12vrsel6 = 6,
#[doc = "7: ADC12 Select Reference 7"]
Adc12vrsel7 = 7,
#[doc = "8: ADC12 Select Reference 8"]
Adc12vrsel8 = 8,
#[doc = "9: ADC12 Select Reference 9"]
Adc12vrsel9 = 9,
#[doc = "10: ADC12 Select Reference 10"]
Adc12vrsel10 = 10,
#[doc = "11: ADC12 Select Reference 11"]
Adc12vrsel11 = 11,
#[doc = "12: ADC12 Select Reference 12"]
Adc12vrsel12 = 12,
#[doc = "13: ADC12 Select Reference 13"]
Adc12vrsel13 = 13,
#[doc = "14: ADC12 Select Reference 14"]
Adc12vrsel14 = 14,
#[doc = "15: ADC12 Select Reference 15"]
Adc12vrsel15 = 15,
}
impl From<Adc12vrsel> for u8 {
#[inline(always)]
fn from(variant: Adc12vrsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Adc12vrsel {
type Ux = u8;
}
impl crate::IsEnum for Adc12vrsel {}
#[doc = "Field `ADC12VRSEL` reader - ADC12 VR Select Bit 0"]
pub type Adc12vrselR = crate::FieldReader<Adc12vrsel>;
impl Adc12vrselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Adc12vrsel {
match self.bits {
0 => Adc12vrsel::Adc12vrsel0,
1 => Adc12vrsel::Adc12vrsel1,
2 => Adc12vrsel::Adc12vrsel2,
3 => Adc12vrsel::Adc12vrsel3,
4 => Adc12vrsel::Adc12vrsel4,
5 => Adc12vrsel::Adc12vrsel5,
6 => Adc12vrsel::Adc12vrsel6,
7 => Adc12vrsel::Adc12vrsel7,
8 => Adc12vrsel::Adc12vrsel8,
9 => Adc12vrsel::Adc12vrsel9,
10 => Adc12vrsel::Adc12vrsel10,
11 => Adc12vrsel::Adc12vrsel11,
12 => Adc12vrsel::Adc12vrsel12,
13 => Adc12vrsel::Adc12vrsel13,
14 => Adc12vrsel::Adc12vrsel14,
15 => Adc12vrsel::Adc12vrsel15,
_ => unreachable!(),
}
}
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn is_adc12vrsel_0(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel0
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn is_adc12vrsel_1(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel1
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn is_adc12vrsel_2(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel2
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn is_adc12vrsel_3(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel3
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn is_adc12vrsel_4(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel4
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn is_adc12vrsel_5(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel5
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn is_adc12vrsel_6(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel6
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn is_adc12vrsel_7(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel7
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn is_adc12vrsel_8(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel8
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn is_adc12vrsel_9(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel9
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn is_adc12vrsel_10(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel10
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn is_adc12vrsel_11(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel11
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn is_adc12vrsel_12(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel12
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn is_adc12vrsel_13(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel13
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn is_adc12vrsel_14(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel14
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn is_adc12vrsel_15(&self) -> bool {
*self == Adc12vrsel::Adc12vrsel15
}
}
#[doc = "Field `ADC12VRSEL` writer - ADC12 VR Select Bit 0"]
pub type Adc12vrselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Adc12vrsel, crate::Safe>;
impl<'a, REG> Adc12vrselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ADC12 Select Reference 0"]
#[inline(always)]
pub fn adc12vrsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel0)
}
#[doc = "ADC12 Select Reference 1"]
#[inline(always)]
pub fn adc12vrsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel1)
}
#[doc = "ADC12 Select Reference 2"]
#[inline(always)]
pub fn adc12vrsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel2)
}
#[doc = "ADC12 Select Reference 3"]
#[inline(always)]
pub fn adc12vrsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel3)
}
#[doc = "ADC12 Select Reference 4"]
#[inline(always)]
pub fn adc12vrsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel4)
}
#[doc = "ADC12 Select Reference 5"]
#[inline(always)]
pub fn adc12vrsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel5)
}
#[doc = "ADC12 Select Reference 6"]
#[inline(always)]
pub fn adc12vrsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel6)
}
#[doc = "ADC12 Select Reference 7"]
#[inline(always)]
pub fn adc12vrsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel7)
}
#[doc = "ADC12 Select Reference 8"]
#[inline(always)]
pub fn adc12vrsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel8)
}
#[doc = "ADC12 Select Reference 9"]
#[inline(always)]
pub fn adc12vrsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel9)
}
#[doc = "ADC12 Select Reference 10"]
#[inline(always)]
pub fn adc12vrsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel10)
}
#[doc = "ADC12 Select Reference 11"]
#[inline(always)]
pub fn adc12vrsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel11)
}
#[doc = "ADC12 Select Reference 12"]
#[inline(always)]
pub fn adc12vrsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel12)
}
#[doc = "ADC12 Select Reference 13"]
#[inline(always)]
pub fn adc12vrsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel13)
}
#[doc = "ADC12 Select Reference 14"]
#[inline(always)]
pub fn adc12vrsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel14)
}
#[doc = "ADC12 Select Reference 15"]
#[inline(always)]
pub fn adc12vrsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Adc12vrsel::Adc12vrsel15)
}
}
#[doc = "Field `ADC12DIF` reader - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difR = crate::BitReader;
#[doc = "Field `ADC12DIF` writer - ADC12 Differential mode (only for even Registers)"]
pub type Adc12difW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ADC12WINC` reader - ADC12 Comparator window enable"]
pub type Adc12wincR = crate::BitReader;
#[doc = "Field `ADC12WINC` writer - ADC12 Comparator window enable"]
pub type Adc12wincW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&self) -> Adc12inchR {
Adc12inchR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&self) -> Adc12eosR {
Adc12eosR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&self) -> Adc12vrselR {
Adc12vrselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&self) -> Adc12difR {
Adc12difR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&self) -> Adc12wincR {
Adc12wincR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - ADC12 Input Channel Select Bit 0"]
#[inline(always)]
pub fn adc12inch(&mut self) -> Adc12inchW<'_, Adc12mctl31Spec> {
Adc12inchW::new(self, 0)
}
#[doc = "Bit 7 - ADC12 End of Sequence"]
#[inline(always)]
pub fn adc12eos(&mut self) -> Adc12eosW<'_, Adc12mctl31Spec> {
Adc12eosW::new(self, 7)
}
#[doc = "Bits 8:11 - ADC12 VR Select Bit 0"]
#[inline(always)]
pub fn adc12vrsel(&mut self) -> Adc12vrselW<'_, Adc12mctl31Spec> {
Adc12vrselW::new(self, 8)
}
#[doc = "Bit 13 - ADC12 Differential mode (only for even Registers)"]
#[inline(always)]
pub fn adc12dif(&mut self) -> Adc12difW<'_, Adc12mctl31Spec> {
Adc12difW::new(self, 13)
}
#[doc = "Bit 14 - ADC12 Comparator window enable"]
#[inline(always)]
pub fn adc12winc(&mut self) -> Adc12wincW<'_, Adc12mctl31Spec> {
Adc12wincW::new(self, 14)
}
}
#[doc = "ADC12 Memory Control 31\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mctl31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mctl31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mctl31Spec;
impl crate::RegisterSpec for Adc12mctl31Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mctl31::R`](R) reader structure"]
impl crate::Readable for Adc12mctl31Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mctl31::W`](W) writer structure"]
impl crate::Writable for Adc12mctl31Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MCTL31 to value 0"]
impl crate::Resettable for Adc12mctl31Spec {}
}
#[doc = "ADC12MEM0 (rw) register accessor: ADC12 Conversion Memory 0\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem0`] module"]
#[doc(alias = "ADC12MEM0")]
pub type Adc12mem0 = crate::Reg<adc12mem0::Adc12mem0Spec>;
#[doc = "ADC12 Conversion Memory 0"]
pub mod adc12mem0 {
#[doc = "Register `ADC12MEM0` reader"]
pub type R = crate::R<Adc12mem0Spec>;
#[doc = "Register `ADC12MEM0` writer"]
pub type W = crate::W<Adc12mem0Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 0\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem0Spec;
impl crate::RegisterSpec for Adc12mem0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem0::R`](R) reader structure"]
impl crate::Readable for Adc12mem0Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem0::W`](W) writer structure"]
impl crate::Writable for Adc12mem0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM0 to value 0"]
impl crate::Resettable for Adc12mem0Spec {}
}
#[doc = "ADC12MEM1 (rw) register accessor: ADC12 Conversion Memory 1\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem1`] module"]
#[doc(alias = "ADC12MEM1")]
pub type Adc12mem1 = crate::Reg<adc12mem1::Adc12mem1Spec>;
#[doc = "ADC12 Conversion Memory 1"]
pub mod adc12mem1 {
#[doc = "Register `ADC12MEM1` reader"]
pub type R = crate::R<Adc12mem1Spec>;
#[doc = "Register `ADC12MEM1` writer"]
pub type W = crate::W<Adc12mem1Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 1\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem1Spec;
impl crate::RegisterSpec for Adc12mem1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem1::R`](R) reader structure"]
impl crate::Readable for Adc12mem1Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem1::W`](W) writer structure"]
impl crate::Writable for Adc12mem1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM1 to value 0"]
impl crate::Resettable for Adc12mem1Spec {}
}
#[doc = "ADC12MEM2 (rw) register accessor: ADC12 Conversion Memory 2\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem2`] module"]
#[doc(alias = "ADC12MEM2")]
pub type Adc12mem2 = crate::Reg<adc12mem2::Adc12mem2Spec>;
#[doc = "ADC12 Conversion Memory 2"]
pub mod adc12mem2 {
#[doc = "Register `ADC12MEM2` reader"]
pub type R = crate::R<Adc12mem2Spec>;
#[doc = "Register `ADC12MEM2` writer"]
pub type W = crate::W<Adc12mem2Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 2\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem2Spec;
impl crate::RegisterSpec for Adc12mem2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem2::R`](R) reader structure"]
impl crate::Readable for Adc12mem2Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem2::W`](W) writer structure"]
impl crate::Writable for Adc12mem2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM2 to value 0"]
impl crate::Resettable for Adc12mem2Spec {}
}
#[doc = "ADC12MEM3 (rw) register accessor: ADC12 Conversion Memory 3\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem3`] module"]
#[doc(alias = "ADC12MEM3")]
pub type Adc12mem3 = crate::Reg<adc12mem3::Adc12mem3Spec>;
#[doc = "ADC12 Conversion Memory 3"]
pub mod adc12mem3 {
#[doc = "Register `ADC12MEM3` reader"]
pub type R = crate::R<Adc12mem3Spec>;
#[doc = "Register `ADC12MEM3` writer"]
pub type W = crate::W<Adc12mem3Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 3\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem3Spec;
impl crate::RegisterSpec for Adc12mem3Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem3::R`](R) reader structure"]
impl crate::Readable for Adc12mem3Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem3::W`](W) writer structure"]
impl crate::Writable for Adc12mem3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM3 to value 0"]
impl crate::Resettable for Adc12mem3Spec {}
}
#[doc = "ADC12MEM4 (rw) register accessor: ADC12 Conversion Memory 4\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem4`] module"]
#[doc(alias = "ADC12MEM4")]
pub type Adc12mem4 = crate::Reg<adc12mem4::Adc12mem4Spec>;
#[doc = "ADC12 Conversion Memory 4"]
pub mod adc12mem4 {
#[doc = "Register `ADC12MEM4` reader"]
pub type R = crate::R<Adc12mem4Spec>;
#[doc = "Register `ADC12MEM4` writer"]
pub type W = crate::W<Adc12mem4Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 4\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem4Spec;
impl crate::RegisterSpec for Adc12mem4Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem4::R`](R) reader structure"]
impl crate::Readable for Adc12mem4Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem4::W`](W) writer structure"]
impl crate::Writable for Adc12mem4Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM4 to value 0"]
impl crate::Resettable for Adc12mem4Spec {}
}
#[doc = "ADC12MEM5 (rw) register accessor: ADC12 Conversion Memory 5\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem5`] module"]
#[doc(alias = "ADC12MEM5")]
pub type Adc12mem5 = crate::Reg<adc12mem5::Adc12mem5Spec>;
#[doc = "ADC12 Conversion Memory 5"]
pub mod adc12mem5 {
#[doc = "Register `ADC12MEM5` reader"]
pub type R = crate::R<Adc12mem5Spec>;
#[doc = "Register `ADC12MEM5` writer"]
pub type W = crate::W<Adc12mem5Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 5\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem5Spec;
impl crate::RegisterSpec for Adc12mem5Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem5::R`](R) reader structure"]
impl crate::Readable for Adc12mem5Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem5::W`](W) writer structure"]
impl crate::Writable for Adc12mem5Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM5 to value 0"]
impl crate::Resettable for Adc12mem5Spec {}
}
#[doc = "ADC12MEM6 (rw) register accessor: ADC12 Conversion Memory 6\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem6`] module"]
#[doc(alias = "ADC12MEM6")]
pub type Adc12mem6 = crate::Reg<adc12mem6::Adc12mem6Spec>;
#[doc = "ADC12 Conversion Memory 6"]
pub mod adc12mem6 {
#[doc = "Register `ADC12MEM6` reader"]
pub type R = crate::R<Adc12mem6Spec>;
#[doc = "Register `ADC12MEM6` writer"]
pub type W = crate::W<Adc12mem6Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 6\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem6Spec;
impl crate::RegisterSpec for Adc12mem6Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem6::R`](R) reader structure"]
impl crate::Readable for Adc12mem6Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem6::W`](W) writer structure"]
impl crate::Writable for Adc12mem6Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM6 to value 0"]
impl crate::Resettable for Adc12mem6Spec {}
}
#[doc = "ADC12MEM7 (rw) register accessor: ADC12 Conversion Memory 7\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem7`] module"]
#[doc(alias = "ADC12MEM7")]
pub type Adc12mem7 = crate::Reg<adc12mem7::Adc12mem7Spec>;
#[doc = "ADC12 Conversion Memory 7"]
pub mod adc12mem7 {
#[doc = "Register `ADC12MEM7` reader"]
pub type R = crate::R<Adc12mem7Spec>;
#[doc = "Register `ADC12MEM7` writer"]
pub type W = crate::W<Adc12mem7Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 7\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem7Spec;
impl crate::RegisterSpec for Adc12mem7Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem7::R`](R) reader structure"]
impl crate::Readable for Adc12mem7Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem7::W`](W) writer structure"]
impl crate::Writable for Adc12mem7Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM7 to value 0"]
impl crate::Resettable for Adc12mem7Spec {}
}
#[doc = "ADC12MEM8 (rw) register accessor: ADC12 Conversion Memory 8\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem8`] module"]
#[doc(alias = "ADC12MEM8")]
pub type Adc12mem8 = crate::Reg<adc12mem8::Adc12mem8Spec>;
#[doc = "ADC12 Conversion Memory 8"]
pub mod adc12mem8 {
#[doc = "Register `ADC12MEM8` reader"]
pub type R = crate::R<Adc12mem8Spec>;
#[doc = "Register `ADC12MEM8` writer"]
pub type W = crate::W<Adc12mem8Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 8\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem8Spec;
impl crate::RegisterSpec for Adc12mem8Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem8::R`](R) reader structure"]
impl crate::Readable for Adc12mem8Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem8::W`](W) writer structure"]
impl crate::Writable for Adc12mem8Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM8 to value 0"]
impl crate::Resettable for Adc12mem8Spec {}
}
#[doc = "ADC12MEM9 (rw) register accessor: ADC12 Conversion Memory 9\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem9`] module"]
#[doc(alias = "ADC12MEM9")]
pub type Adc12mem9 = crate::Reg<adc12mem9::Adc12mem9Spec>;
#[doc = "ADC12 Conversion Memory 9"]
pub mod adc12mem9 {
#[doc = "Register `ADC12MEM9` reader"]
pub type R = crate::R<Adc12mem9Spec>;
#[doc = "Register `ADC12MEM9` writer"]
pub type W = crate::W<Adc12mem9Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 9\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem9Spec;
impl crate::RegisterSpec for Adc12mem9Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem9::R`](R) reader structure"]
impl crate::Readable for Adc12mem9Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem9::W`](W) writer structure"]
impl crate::Writable for Adc12mem9Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM9 to value 0"]
impl crate::Resettable for Adc12mem9Spec {}
}
#[doc = "ADC12MEM10 (rw) register accessor: ADC12 Conversion Memory 10\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem10`] module"]
#[doc(alias = "ADC12MEM10")]
pub type Adc12mem10 = crate::Reg<adc12mem10::Adc12mem10Spec>;
#[doc = "ADC12 Conversion Memory 10"]
pub mod adc12mem10 {
#[doc = "Register `ADC12MEM10` reader"]
pub type R = crate::R<Adc12mem10Spec>;
#[doc = "Register `ADC12MEM10` writer"]
pub type W = crate::W<Adc12mem10Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 10\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem10Spec;
impl crate::RegisterSpec for Adc12mem10Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem10::R`](R) reader structure"]
impl crate::Readable for Adc12mem10Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem10::W`](W) writer structure"]
impl crate::Writable for Adc12mem10Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM10 to value 0"]
impl crate::Resettable for Adc12mem10Spec {}
}
#[doc = "ADC12MEM11 (rw) register accessor: ADC12 Conversion Memory 11\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem11`] module"]
#[doc(alias = "ADC12MEM11")]
pub type Adc12mem11 = crate::Reg<adc12mem11::Adc12mem11Spec>;
#[doc = "ADC12 Conversion Memory 11"]
pub mod adc12mem11 {
#[doc = "Register `ADC12MEM11` reader"]
pub type R = crate::R<Adc12mem11Spec>;
#[doc = "Register `ADC12MEM11` writer"]
pub type W = crate::W<Adc12mem11Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 11\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem11Spec;
impl crate::RegisterSpec for Adc12mem11Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem11::R`](R) reader structure"]
impl crate::Readable for Adc12mem11Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem11::W`](W) writer structure"]
impl crate::Writable for Adc12mem11Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM11 to value 0"]
impl crate::Resettable for Adc12mem11Spec {}
}
#[doc = "ADC12MEM12 (rw) register accessor: ADC12 Conversion Memory 12\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem12`] module"]
#[doc(alias = "ADC12MEM12")]
pub type Adc12mem12 = crate::Reg<adc12mem12::Adc12mem12Spec>;
#[doc = "ADC12 Conversion Memory 12"]
pub mod adc12mem12 {
#[doc = "Register `ADC12MEM12` reader"]
pub type R = crate::R<Adc12mem12Spec>;
#[doc = "Register `ADC12MEM12` writer"]
pub type W = crate::W<Adc12mem12Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 12\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem12Spec;
impl crate::RegisterSpec for Adc12mem12Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem12::R`](R) reader structure"]
impl crate::Readable for Adc12mem12Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem12::W`](W) writer structure"]
impl crate::Writable for Adc12mem12Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM12 to value 0"]
impl crate::Resettable for Adc12mem12Spec {}
}
#[doc = "ADC12MEM13 (rw) register accessor: ADC12 Conversion Memory 13\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem13`] module"]
#[doc(alias = "ADC12MEM13")]
pub type Adc12mem13 = crate::Reg<adc12mem13::Adc12mem13Spec>;
#[doc = "ADC12 Conversion Memory 13"]
pub mod adc12mem13 {
#[doc = "Register `ADC12MEM13` reader"]
pub type R = crate::R<Adc12mem13Spec>;
#[doc = "Register `ADC12MEM13` writer"]
pub type W = crate::W<Adc12mem13Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 13\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem13Spec;
impl crate::RegisterSpec for Adc12mem13Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem13::R`](R) reader structure"]
impl crate::Readable for Adc12mem13Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem13::W`](W) writer structure"]
impl crate::Writable for Adc12mem13Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM13 to value 0"]
impl crate::Resettable for Adc12mem13Spec {}
}
#[doc = "ADC12MEM14 (rw) register accessor: ADC12 Conversion Memory 14\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem14`] module"]
#[doc(alias = "ADC12MEM14")]
pub type Adc12mem14 = crate::Reg<adc12mem14::Adc12mem14Spec>;
#[doc = "ADC12 Conversion Memory 14"]
pub mod adc12mem14 {
#[doc = "Register `ADC12MEM14` reader"]
pub type R = crate::R<Adc12mem14Spec>;
#[doc = "Register `ADC12MEM14` writer"]
pub type W = crate::W<Adc12mem14Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 14\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem14Spec;
impl crate::RegisterSpec for Adc12mem14Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem14::R`](R) reader structure"]
impl crate::Readable for Adc12mem14Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem14::W`](W) writer structure"]
impl crate::Writable for Adc12mem14Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM14 to value 0"]
impl crate::Resettable for Adc12mem14Spec {}
}
#[doc = "ADC12MEM15 (rw) register accessor: ADC12 Conversion Memory 15\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem15`] module"]
#[doc(alias = "ADC12MEM15")]
pub type Adc12mem15 = crate::Reg<adc12mem15::Adc12mem15Spec>;
#[doc = "ADC12 Conversion Memory 15"]
pub mod adc12mem15 {
#[doc = "Register `ADC12MEM15` reader"]
pub type R = crate::R<Adc12mem15Spec>;
#[doc = "Register `ADC12MEM15` writer"]
pub type W = crate::W<Adc12mem15Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 15\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem15Spec;
impl crate::RegisterSpec for Adc12mem15Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem15::R`](R) reader structure"]
impl crate::Readable for Adc12mem15Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem15::W`](W) writer structure"]
impl crate::Writable for Adc12mem15Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM15 to value 0"]
impl crate::Resettable for Adc12mem15Spec {}
}
#[doc = "ADC12MEM16 (rw) register accessor: ADC12 Conversion Memory 16\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem16`] module"]
#[doc(alias = "ADC12MEM16")]
pub type Adc12mem16 = crate::Reg<adc12mem16::Adc12mem16Spec>;
#[doc = "ADC12 Conversion Memory 16"]
pub mod adc12mem16 {
#[doc = "Register `ADC12MEM16` reader"]
pub type R = crate::R<Adc12mem16Spec>;
#[doc = "Register `ADC12MEM16` writer"]
pub type W = crate::W<Adc12mem16Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 16\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem16Spec;
impl crate::RegisterSpec for Adc12mem16Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem16::R`](R) reader structure"]
impl crate::Readable for Adc12mem16Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem16::W`](W) writer structure"]
impl crate::Writable for Adc12mem16Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM16 to value 0"]
impl crate::Resettable for Adc12mem16Spec {}
}
#[doc = "ADC12MEM17 (rw) register accessor: ADC12 Conversion Memory 17\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem17`] module"]
#[doc(alias = "ADC12MEM17")]
pub type Adc12mem17 = crate::Reg<adc12mem17::Adc12mem17Spec>;
#[doc = "ADC12 Conversion Memory 17"]
pub mod adc12mem17 {
#[doc = "Register `ADC12MEM17` reader"]
pub type R = crate::R<Adc12mem17Spec>;
#[doc = "Register `ADC12MEM17` writer"]
pub type W = crate::W<Adc12mem17Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 17\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem17Spec;
impl crate::RegisterSpec for Adc12mem17Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem17::R`](R) reader structure"]
impl crate::Readable for Adc12mem17Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem17::W`](W) writer structure"]
impl crate::Writable for Adc12mem17Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM17 to value 0"]
impl crate::Resettable for Adc12mem17Spec {}
}
#[doc = "ADC12MEM18 (rw) register accessor: ADC12 Conversion Memory 18\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem18`] module"]
#[doc(alias = "ADC12MEM18")]
pub type Adc12mem18 = crate::Reg<adc12mem18::Adc12mem18Spec>;
#[doc = "ADC12 Conversion Memory 18"]
pub mod adc12mem18 {
#[doc = "Register `ADC12MEM18` reader"]
pub type R = crate::R<Adc12mem18Spec>;
#[doc = "Register `ADC12MEM18` writer"]
pub type W = crate::W<Adc12mem18Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 18\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem18Spec;
impl crate::RegisterSpec for Adc12mem18Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem18::R`](R) reader structure"]
impl crate::Readable for Adc12mem18Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem18::W`](W) writer structure"]
impl crate::Writable for Adc12mem18Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM18 to value 0"]
impl crate::Resettable for Adc12mem18Spec {}
}
#[doc = "ADC12MEM19 (rw) register accessor: ADC12 Conversion Memory 19\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem19`] module"]
#[doc(alias = "ADC12MEM19")]
pub type Adc12mem19 = crate::Reg<adc12mem19::Adc12mem19Spec>;
#[doc = "ADC12 Conversion Memory 19"]
pub mod adc12mem19 {
#[doc = "Register `ADC12MEM19` reader"]
pub type R = crate::R<Adc12mem19Spec>;
#[doc = "Register `ADC12MEM19` writer"]
pub type W = crate::W<Adc12mem19Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 19\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem19Spec;
impl crate::RegisterSpec for Adc12mem19Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem19::R`](R) reader structure"]
impl crate::Readable for Adc12mem19Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem19::W`](W) writer structure"]
impl crate::Writable for Adc12mem19Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM19 to value 0"]
impl crate::Resettable for Adc12mem19Spec {}
}
#[doc = "ADC12MEM20 (rw) register accessor: ADC12 Conversion Memory 20\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem20`] module"]
#[doc(alias = "ADC12MEM20")]
pub type Adc12mem20 = crate::Reg<adc12mem20::Adc12mem20Spec>;
#[doc = "ADC12 Conversion Memory 20"]
pub mod adc12mem20 {
#[doc = "Register `ADC12MEM20` reader"]
pub type R = crate::R<Adc12mem20Spec>;
#[doc = "Register `ADC12MEM20` writer"]
pub type W = crate::W<Adc12mem20Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 20\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem20Spec;
impl crate::RegisterSpec for Adc12mem20Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem20::R`](R) reader structure"]
impl crate::Readable for Adc12mem20Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem20::W`](W) writer structure"]
impl crate::Writable for Adc12mem20Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM20 to value 0"]
impl crate::Resettable for Adc12mem20Spec {}
}
#[doc = "ADC12MEM21 (rw) register accessor: ADC12 Conversion Memory 21\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem21`] module"]
#[doc(alias = "ADC12MEM21")]
pub type Adc12mem21 = crate::Reg<adc12mem21::Adc12mem21Spec>;
#[doc = "ADC12 Conversion Memory 21"]
pub mod adc12mem21 {
#[doc = "Register `ADC12MEM21` reader"]
pub type R = crate::R<Adc12mem21Spec>;
#[doc = "Register `ADC12MEM21` writer"]
pub type W = crate::W<Adc12mem21Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 21\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem21Spec;
impl crate::RegisterSpec for Adc12mem21Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem21::R`](R) reader structure"]
impl crate::Readable for Adc12mem21Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem21::W`](W) writer structure"]
impl crate::Writable for Adc12mem21Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM21 to value 0"]
impl crate::Resettable for Adc12mem21Spec {}
}
#[doc = "ADC12MEM22 (rw) register accessor: ADC12 Conversion Memory 22\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem22`] module"]
#[doc(alias = "ADC12MEM22")]
pub type Adc12mem22 = crate::Reg<adc12mem22::Adc12mem22Spec>;
#[doc = "ADC12 Conversion Memory 22"]
pub mod adc12mem22 {
#[doc = "Register `ADC12MEM22` reader"]
pub type R = crate::R<Adc12mem22Spec>;
#[doc = "Register `ADC12MEM22` writer"]
pub type W = crate::W<Adc12mem22Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 22\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem22Spec;
impl crate::RegisterSpec for Adc12mem22Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem22::R`](R) reader structure"]
impl crate::Readable for Adc12mem22Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem22::W`](W) writer structure"]
impl crate::Writable for Adc12mem22Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM22 to value 0"]
impl crate::Resettable for Adc12mem22Spec {}
}
#[doc = "ADC12MEM23 (rw) register accessor: ADC12 Conversion Memory 23\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem23`] module"]
#[doc(alias = "ADC12MEM23")]
pub type Adc12mem23 = crate::Reg<adc12mem23::Adc12mem23Spec>;
#[doc = "ADC12 Conversion Memory 23"]
pub mod adc12mem23 {
#[doc = "Register `ADC12MEM23` reader"]
pub type R = crate::R<Adc12mem23Spec>;
#[doc = "Register `ADC12MEM23` writer"]
pub type W = crate::W<Adc12mem23Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 23\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem23Spec;
impl crate::RegisterSpec for Adc12mem23Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem23::R`](R) reader structure"]
impl crate::Readable for Adc12mem23Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem23::W`](W) writer structure"]
impl crate::Writable for Adc12mem23Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM23 to value 0"]
impl crate::Resettable for Adc12mem23Spec {}
}
#[doc = "ADC12MEM24 (rw) register accessor: ADC12 Conversion Memory 24\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem24`] module"]
#[doc(alias = "ADC12MEM24")]
pub type Adc12mem24 = crate::Reg<adc12mem24::Adc12mem24Spec>;
#[doc = "ADC12 Conversion Memory 24"]
pub mod adc12mem24 {
#[doc = "Register `ADC12MEM24` reader"]
pub type R = crate::R<Adc12mem24Spec>;
#[doc = "Register `ADC12MEM24` writer"]
pub type W = crate::W<Adc12mem24Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 24\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem24Spec;
impl crate::RegisterSpec for Adc12mem24Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem24::R`](R) reader structure"]
impl crate::Readable for Adc12mem24Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem24::W`](W) writer structure"]
impl crate::Writable for Adc12mem24Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM24 to value 0"]
impl crate::Resettable for Adc12mem24Spec {}
}
#[doc = "ADC12MEM25 (rw) register accessor: ADC12 Conversion Memory 25\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem25`] module"]
#[doc(alias = "ADC12MEM25")]
pub type Adc12mem25 = crate::Reg<adc12mem25::Adc12mem25Spec>;
#[doc = "ADC12 Conversion Memory 25"]
pub mod adc12mem25 {
#[doc = "Register `ADC12MEM25` reader"]
pub type R = crate::R<Adc12mem25Spec>;
#[doc = "Register `ADC12MEM25` writer"]
pub type W = crate::W<Adc12mem25Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 25\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem25Spec;
impl crate::RegisterSpec for Adc12mem25Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem25::R`](R) reader structure"]
impl crate::Readable for Adc12mem25Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem25::W`](W) writer structure"]
impl crate::Writable for Adc12mem25Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM25 to value 0"]
impl crate::Resettable for Adc12mem25Spec {}
}
#[doc = "ADC12MEM26 (rw) register accessor: ADC12 Conversion Memory 26\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem26`] module"]
#[doc(alias = "ADC12MEM26")]
pub type Adc12mem26 = crate::Reg<adc12mem26::Adc12mem26Spec>;
#[doc = "ADC12 Conversion Memory 26"]
pub mod adc12mem26 {
#[doc = "Register `ADC12MEM26` reader"]
pub type R = crate::R<Adc12mem26Spec>;
#[doc = "Register `ADC12MEM26` writer"]
pub type W = crate::W<Adc12mem26Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 26\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem26Spec;
impl crate::RegisterSpec for Adc12mem26Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem26::R`](R) reader structure"]
impl crate::Readable for Adc12mem26Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem26::W`](W) writer structure"]
impl crate::Writable for Adc12mem26Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM26 to value 0"]
impl crate::Resettable for Adc12mem26Spec {}
}
#[doc = "ADC12MEM27 (rw) register accessor: ADC12 Conversion Memory 27\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem27`] module"]
#[doc(alias = "ADC12MEM27")]
pub type Adc12mem27 = crate::Reg<adc12mem27::Adc12mem27Spec>;
#[doc = "ADC12 Conversion Memory 27"]
pub mod adc12mem27 {
#[doc = "Register `ADC12MEM27` reader"]
pub type R = crate::R<Adc12mem27Spec>;
#[doc = "Register `ADC12MEM27` writer"]
pub type W = crate::W<Adc12mem27Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 27\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem27Spec;
impl crate::RegisterSpec for Adc12mem27Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem27::R`](R) reader structure"]
impl crate::Readable for Adc12mem27Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem27::W`](W) writer structure"]
impl crate::Writable for Adc12mem27Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM27 to value 0"]
impl crate::Resettable for Adc12mem27Spec {}
}
#[doc = "ADC12MEM28 (rw) register accessor: ADC12 Conversion Memory 28\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem28`] module"]
#[doc(alias = "ADC12MEM28")]
pub type Adc12mem28 = crate::Reg<adc12mem28::Adc12mem28Spec>;
#[doc = "ADC12 Conversion Memory 28"]
pub mod adc12mem28 {
#[doc = "Register `ADC12MEM28` reader"]
pub type R = crate::R<Adc12mem28Spec>;
#[doc = "Register `ADC12MEM28` writer"]
pub type W = crate::W<Adc12mem28Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 28\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem28Spec;
impl crate::RegisterSpec for Adc12mem28Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem28::R`](R) reader structure"]
impl crate::Readable for Adc12mem28Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem28::W`](W) writer structure"]
impl crate::Writable for Adc12mem28Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM28 to value 0"]
impl crate::Resettable for Adc12mem28Spec {}
}
#[doc = "ADC12MEM29 (rw) register accessor: ADC12 Conversion Memory 29\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem29`] module"]
#[doc(alias = "ADC12MEM29")]
pub type Adc12mem29 = crate::Reg<adc12mem29::Adc12mem29Spec>;
#[doc = "ADC12 Conversion Memory 29"]
pub mod adc12mem29 {
#[doc = "Register `ADC12MEM29` reader"]
pub type R = crate::R<Adc12mem29Spec>;
#[doc = "Register `ADC12MEM29` writer"]
pub type W = crate::W<Adc12mem29Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 29\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem29Spec;
impl crate::RegisterSpec for Adc12mem29Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem29::R`](R) reader structure"]
impl crate::Readable for Adc12mem29Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem29::W`](W) writer structure"]
impl crate::Writable for Adc12mem29Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM29 to value 0"]
impl crate::Resettable for Adc12mem29Spec {}
}
#[doc = "ADC12MEM30 (rw) register accessor: ADC12 Conversion Memory 30\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem30`] module"]
#[doc(alias = "ADC12MEM30")]
pub type Adc12mem30 = crate::Reg<adc12mem30::Adc12mem30Spec>;
#[doc = "ADC12 Conversion Memory 30"]
pub mod adc12mem30 {
#[doc = "Register `ADC12MEM30` reader"]
pub type R = crate::R<Adc12mem30Spec>;
#[doc = "Register `ADC12MEM30` writer"]
pub type W = crate::W<Adc12mem30Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 30\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem30Spec;
impl crate::RegisterSpec for Adc12mem30Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem30::R`](R) reader structure"]
impl crate::Readable for Adc12mem30Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem30::W`](W) writer structure"]
impl crate::Writable for Adc12mem30Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM30 to value 0"]
impl crate::Resettable for Adc12mem30Spec {}
}
#[doc = "ADC12MEM31 (rw) register accessor: ADC12 Conversion Memory 31\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc12mem31`] module"]
#[doc(alias = "ADC12MEM31")]
pub type Adc12mem31 = crate::Reg<adc12mem31::Adc12mem31Spec>;
#[doc = "ADC12 Conversion Memory 31"]
pub mod adc12mem31 {
#[doc = "Register `ADC12MEM31` reader"]
pub type R = crate::R<Adc12mem31Spec>;
#[doc = "Register `ADC12MEM31` writer"]
pub type W = crate::W<Adc12mem31Spec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "ADC12 Conversion Memory 31\n\nYou can [`read`](crate::Reg::read) this register and get [`adc12mem31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc12mem31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Adc12mem31Spec;
impl crate::RegisterSpec for Adc12mem31Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`adc12mem31::R`](R) reader structure"]
impl crate::Readable for Adc12mem31Spec {}
#[doc = "`write(|w| ..)` method takes [`adc12mem31::W`](W) writer structure"]
impl crate::Writable for Adc12mem31Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADC12MEM31 to value 0"]
impl crate::Resettable for Adc12mem31Spec {}
}
}
#[doc = "Comparator E"]
pub type ComparatorE = crate::Periph<comparator_e::RegisterBlock, 0x08c0>;
impl core::fmt::Debug for ComparatorE {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ComparatorE").finish()
}
}
#[doc = "Comparator E"]
pub mod comparator_e {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cectl0: Cectl0,
cectl1: Cectl1,
cectl2: Cectl2,
cectl3: Cectl3,
_reserved4: [u8; 0x04],
ceint: Ceint,
ceiv: Ceiv,
}
impl RegisterBlock {
#[doc = "0x00 - Comparator E Control Register 0"]
#[inline(always)]
pub const fn cectl0(&self) -> &Cectl0 {
&self.cectl0
}
#[doc = "0x02 - Comparator E Control Register 1"]
#[inline(always)]
pub const fn cectl1(&self) -> &Cectl1 {
&self.cectl1
}
#[doc = "0x04 - Comparator E Control Register 2"]
#[inline(always)]
pub const fn cectl2(&self) -> &Cectl2 {
&self.cectl2
}
#[doc = "0x06 - Comparator E Control Register 3"]
#[inline(always)]
pub const fn cectl3(&self) -> &Cectl3 {
&self.cectl3
}
#[doc = "0x0c - Comparator E Interrupt Register"]
#[inline(always)]
pub const fn ceint(&self) -> &Ceint {
&self.ceint
}
#[doc = "0x0e - Comparator E Interrupt Vector Word"]
#[inline(always)]
pub const fn ceiv(&self) -> &Ceiv {
&self.ceiv
}
}
#[doc = "CECTL0 (rw) register accessor: Comparator E Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cectl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cectl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cectl0`] module"]
#[doc(alias = "CECTL0")]
pub type Cectl0 = crate::Reg<cectl0::Cectl0Spec>;
#[doc = "Comparator E Control Register 0"]
pub mod cectl0 {
#[doc = "Register `CECTL0` reader"]
pub type R = crate::R<Cectl0Spec>;
#[doc = "Register `CECTL0` writer"]
pub type W = crate::W<Cectl0Spec>;
#[doc = "Comp. E Pos. Channel Input Select 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ceipsel {
#[doc = "0: Comp. E V+ terminal Input Select: Channel 0"]
Ceipsel0 = 0,
#[doc = "1: Comp. E V+ terminal Input Select: Channel 1"]
Ceipsel1 = 1,
#[doc = "2: Comp. E V+ terminal Input Select: Channel 2"]
Ceipsel2 = 2,
#[doc = "3: Comp. E V+ terminal Input Select: Channel 3"]
Ceipsel3 = 3,
#[doc = "4: Comp. E V+ terminal Input Select: Channel 4"]
Ceipsel4 = 4,
#[doc = "5: Comp. E V+ terminal Input Select: Channel 5"]
Ceipsel5 = 5,
#[doc = "6: Comp. E V+ terminal Input Select: Channel 6"]
Ceipsel6 = 6,
#[doc = "7: Comp. E V+ terminal Input Select: Channel 7"]
Ceipsel7 = 7,
#[doc = "8: Comp. E V+ terminal Input Select: Channel 8"]
Ceipsel8 = 8,
#[doc = "9: Comp. E V+ terminal Input Select: Channel 9"]
Ceipsel9 = 9,
#[doc = "10: Comp. E V+ terminal Input Select: Channel 10"]
Ceipsel10 = 10,
#[doc = "11: Comp. E V+ terminal Input Select: Channel 11"]
Ceipsel11 = 11,
#[doc = "12: Comp. E V+ terminal Input Select: Channel 12"]
Ceipsel12 = 12,
#[doc = "13: Comp. E V+ terminal Input Select: Channel 13"]
Ceipsel13 = 13,
#[doc = "14: Comp. E V+ terminal Input Select: Channel 14"]
Ceipsel14 = 14,
#[doc = "15: Comp. E V+ terminal Input Select: Channel 15"]
Ceipsel15 = 15,
}
impl From<Ceipsel> for u8 {
#[inline(always)]
fn from(variant: Ceipsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ceipsel {
type Ux = u8;
}
impl crate::IsEnum for Ceipsel {}
#[doc = "Field `CEIPSEL` reader - Comp. E Pos. Channel Input Select 0"]
pub type CeipselR = crate::FieldReader<Ceipsel>;
impl CeipselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ceipsel {
match self.bits {
0 => Ceipsel::Ceipsel0,
1 => Ceipsel::Ceipsel1,
2 => Ceipsel::Ceipsel2,
3 => Ceipsel::Ceipsel3,
4 => Ceipsel::Ceipsel4,
5 => Ceipsel::Ceipsel5,
6 => Ceipsel::Ceipsel6,
7 => Ceipsel::Ceipsel7,
8 => Ceipsel::Ceipsel8,
9 => Ceipsel::Ceipsel9,
10 => Ceipsel::Ceipsel10,
11 => Ceipsel::Ceipsel11,
12 => Ceipsel::Ceipsel12,
13 => Ceipsel::Ceipsel13,
14 => Ceipsel::Ceipsel14,
15 => Ceipsel::Ceipsel15,
_ => unreachable!(),
}
}
#[doc = "Comp. E V+ terminal Input Select: Channel 0"]
#[inline(always)]
pub fn is_ceipsel_0(&self) -> bool {
*self == Ceipsel::Ceipsel0
}
#[doc = "Comp. E V+ terminal Input Select: Channel 1"]
#[inline(always)]
pub fn is_ceipsel_1(&self) -> bool {
*self == Ceipsel::Ceipsel1
}
#[doc = "Comp. E V+ terminal Input Select: Channel 2"]
#[inline(always)]
pub fn is_ceipsel_2(&self) -> bool {
*self == Ceipsel::Ceipsel2
}
#[doc = "Comp. E V+ terminal Input Select: Channel 3"]
#[inline(always)]
pub fn is_ceipsel_3(&self) -> bool {
*self == Ceipsel::Ceipsel3
}
#[doc = "Comp. E V+ terminal Input Select: Channel 4"]
#[inline(always)]
pub fn is_ceipsel_4(&self) -> bool {
*self == Ceipsel::Ceipsel4
}
#[doc = "Comp. E V+ terminal Input Select: Channel 5"]
#[inline(always)]
pub fn is_ceipsel_5(&self) -> bool {
*self == Ceipsel::Ceipsel5
}
#[doc = "Comp. E V+ terminal Input Select: Channel 6"]
#[inline(always)]
pub fn is_ceipsel_6(&self) -> bool {
*self == Ceipsel::Ceipsel6
}
#[doc = "Comp. E V+ terminal Input Select: Channel 7"]
#[inline(always)]
pub fn is_ceipsel_7(&self) -> bool {
*self == Ceipsel::Ceipsel7
}
#[doc = "Comp. E V+ terminal Input Select: Channel 8"]
#[inline(always)]
pub fn is_ceipsel_8(&self) -> bool {
*self == Ceipsel::Ceipsel8
}
#[doc = "Comp. E V+ terminal Input Select: Channel 9"]
#[inline(always)]
pub fn is_ceipsel_9(&self) -> bool {
*self == Ceipsel::Ceipsel9
}
#[doc = "Comp. E V+ terminal Input Select: Channel 10"]
#[inline(always)]
pub fn is_ceipsel_10(&self) -> bool {
*self == Ceipsel::Ceipsel10
}
#[doc = "Comp. E V+ terminal Input Select: Channel 11"]
#[inline(always)]
pub fn is_ceipsel_11(&self) -> bool {
*self == Ceipsel::Ceipsel11
}
#[doc = "Comp. E V+ terminal Input Select: Channel 12"]
#[inline(always)]
pub fn is_ceipsel_12(&self) -> bool {
*self == Ceipsel::Ceipsel12
}
#[doc = "Comp. E V+ terminal Input Select: Channel 13"]
#[inline(always)]
pub fn is_ceipsel_13(&self) -> bool {
*self == Ceipsel::Ceipsel13
}
#[doc = "Comp. E V+ terminal Input Select: Channel 14"]
#[inline(always)]
pub fn is_ceipsel_14(&self) -> bool {
*self == Ceipsel::Ceipsel14
}
#[doc = "Comp. E V+ terminal Input Select: Channel 15"]
#[inline(always)]
pub fn is_ceipsel_15(&self) -> bool {
*self == Ceipsel::Ceipsel15
}
}
#[doc = "Field `CEIPSEL` writer - Comp. E Pos. Channel Input Select 0"]
pub type CeipselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ceipsel, crate::Safe>;
impl<'a, REG> CeipselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Comp. E V+ terminal Input Select: Channel 0"]
#[inline(always)]
pub fn ceipsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Ceipsel::Ceipsel0)
}
#[doc = "Comp. E V+ terminal Input Select: Channel 1"]
#[inline(always)]
pub fn ceipsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Ceipsel::Ceipsel1)
}
#[doc = "Comp. E V+ terminal Input Select: Channel 2"]
#[inline(always)]
pub fn ceipsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Ceipsel::Ceipsel2)
}
#[doc = "Comp. E V+ terminal Input Select: Channel 3"]
#[inline(always)]
pub fn ceipsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Ceipsel::Ceipsel3)
}
#[doc = "Comp. E V+ terminal Input Select: Channel 4"]
#[inline(always)]
pub fn ceipsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Ceipsel::Ceipsel4)
}
#[doc = "Comp. E V+ terminal Input Select: Channel 5"]
#[inline(always)]
pub fn ceipsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Ceipsel::Ceipsel5)
}
#[doc = "Comp. E V+ terminal Input Select: Channel 6"]
#[inline(always)]
pub fn ceipsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Ceipsel::Ceipsel6)
}
#[doc = "Comp. E V+ terminal Input Select: Channel 7"]
#[inline(always)]
pub fn ceipsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Ceipsel::Ceipsel7)
}
#[doc = "Comp. E V+ terminal Input Select: Channel 8"]
#[inline(always)]
pub fn ceipsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Ceipsel::Ceipsel8)
}
#[doc = "Comp. E V+ terminal Input Select: Channel 9"]
#[inline(always)]
pub fn ceipsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Ceipsel::Ceipsel9)
}
#[doc = "Comp. E V+ terminal Input Select: Channel 10"]
#[inline(always)]
pub fn ceipsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Ceipsel::Ceipsel10)
}
#[doc = "Comp. E V+ terminal Input Select: Channel 11"]
#[inline(always)]
pub fn ceipsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Ceipsel::Ceipsel11)
}
#[doc = "Comp. E V+ terminal Input Select: Channel 12"]
#[inline(always)]
pub fn ceipsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Ceipsel::Ceipsel12)
}
#[doc = "Comp. E V+ terminal Input Select: Channel 13"]
#[inline(always)]
pub fn ceipsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Ceipsel::Ceipsel13)
}
#[doc = "Comp. E V+ terminal Input Select: Channel 14"]
#[inline(always)]
pub fn ceipsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Ceipsel::Ceipsel14)
}
#[doc = "Comp. E V+ terminal Input Select: Channel 15"]
#[inline(always)]
pub fn ceipsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Ceipsel::Ceipsel15)
}
}
#[doc = "Field `CEIPEN` reader - Comp. E Pos. Channel Input Enable"]
pub type CeipenR = crate::BitReader;
#[doc = "Field `CEIPEN` writer - Comp. E Pos. Channel Input Enable"]
pub type CeipenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Comp. E Neg. Channel Input Select 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ceimsel {
#[doc = "0: Comp. E V- Terminal Input Select: Channel 0"]
Ceimsel0 = 0,
#[doc = "1: Comp. E V- Terminal Input Select: Channel 1"]
Ceimsel1 = 1,
#[doc = "2: Comp. E V- Terminal Input Select: Channel 2"]
Ceimsel2 = 2,
#[doc = "3: Comp. E V- Terminal Input Select: Channel 3"]
Ceimsel3 = 3,
#[doc = "4: Comp. E V- Terminal Input Select: Channel 4"]
Ceimsel4 = 4,
#[doc = "5: Comp. E V- Terminal Input Select: Channel 5"]
Ceimsel5 = 5,
#[doc = "6: Comp. E V- Terminal Input Select: Channel 6"]
Ceimsel6 = 6,
#[doc = "7: Comp. E V- Terminal Input Select: Channel 7"]
Ceimsel7 = 7,
#[doc = "8: Comp. E V- terminal Input Select: Channel 8"]
Ceimsel8 = 8,
#[doc = "9: Comp. E V- terminal Input Select: Channel 9"]
Ceimsel9 = 9,
#[doc = "10: Comp. E V- terminal Input Select: Channel 10"]
Ceimsel10 = 10,
#[doc = "11: Comp. E V- terminal Input Select: Channel 11"]
Ceimsel11 = 11,
#[doc = "12: Comp. E V- terminal Input Select: Channel 12"]
Ceimsel12 = 12,
#[doc = "13: Comp. E V- terminal Input Select: Channel 13"]
Ceimsel13 = 13,
#[doc = "14: Comp. E V- terminal Input Select: Channel 14"]
Ceimsel14 = 14,
#[doc = "15: Comp. E V- terminal Input Select: Channel 15"]
Ceimsel15 = 15,
}
impl From<Ceimsel> for u8 {
#[inline(always)]
fn from(variant: Ceimsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ceimsel {
type Ux = u8;
}
impl crate::IsEnum for Ceimsel {}
#[doc = "Field `CEIMSEL` reader - Comp. E Neg. Channel Input Select 0"]
pub type CeimselR = crate::FieldReader<Ceimsel>;
impl CeimselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ceimsel {
match self.bits {
0 => Ceimsel::Ceimsel0,
1 => Ceimsel::Ceimsel1,
2 => Ceimsel::Ceimsel2,
3 => Ceimsel::Ceimsel3,
4 => Ceimsel::Ceimsel4,
5 => Ceimsel::Ceimsel5,
6 => Ceimsel::Ceimsel6,
7 => Ceimsel::Ceimsel7,
8 => Ceimsel::Ceimsel8,
9 => Ceimsel::Ceimsel9,
10 => Ceimsel::Ceimsel10,
11 => Ceimsel::Ceimsel11,
12 => Ceimsel::Ceimsel12,
13 => Ceimsel::Ceimsel13,
14 => Ceimsel::Ceimsel14,
15 => Ceimsel::Ceimsel15,
_ => unreachable!(),
}
}
#[doc = "Comp. E V- Terminal Input Select: Channel 0"]
#[inline(always)]
pub fn is_ceimsel_0(&self) -> bool {
*self == Ceimsel::Ceimsel0
}
#[doc = "Comp. E V- Terminal Input Select: Channel 1"]
#[inline(always)]
pub fn is_ceimsel_1(&self) -> bool {
*self == Ceimsel::Ceimsel1
}
#[doc = "Comp. E V- Terminal Input Select: Channel 2"]
#[inline(always)]
pub fn is_ceimsel_2(&self) -> bool {
*self == Ceimsel::Ceimsel2
}
#[doc = "Comp. E V- Terminal Input Select: Channel 3"]
#[inline(always)]
pub fn is_ceimsel_3(&self) -> bool {
*self == Ceimsel::Ceimsel3
}
#[doc = "Comp. E V- Terminal Input Select: Channel 4"]
#[inline(always)]
pub fn is_ceimsel_4(&self) -> bool {
*self == Ceimsel::Ceimsel4
}
#[doc = "Comp. E V- Terminal Input Select: Channel 5"]
#[inline(always)]
pub fn is_ceimsel_5(&self) -> bool {
*self == Ceimsel::Ceimsel5
}
#[doc = "Comp. E V- Terminal Input Select: Channel 6"]
#[inline(always)]
pub fn is_ceimsel_6(&self) -> bool {
*self == Ceimsel::Ceimsel6
}
#[doc = "Comp. E V- Terminal Input Select: Channel 7"]
#[inline(always)]
pub fn is_ceimsel_7(&self) -> bool {
*self == Ceimsel::Ceimsel7
}
#[doc = "Comp. E V- terminal Input Select: Channel 8"]
#[inline(always)]
pub fn is_ceimsel_8(&self) -> bool {
*self == Ceimsel::Ceimsel8
}
#[doc = "Comp. E V- terminal Input Select: Channel 9"]
#[inline(always)]
pub fn is_ceimsel_9(&self) -> bool {
*self == Ceimsel::Ceimsel9
}
#[doc = "Comp. E V- terminal Input Select: Channel 10"]
#[inline(always)]
pub fn is_ceimsel_10(&self) -> bool {
*self == Ceimsel::Ceimsel10
}
#[doc = "Comp. E V- terminal Input Select: Channel 11"]
#[inline(always)]
pub fn is_ceimsel_11(&self) -> bool {
*self == Ceimsel::Ceimsel11
}
#[doc = "Comp. E V- terminal Input Select: Channel 12"]
#[inline(always)]
pub fn is_ceimsel_12(&self) -> bool {
*self == Ceimsel::Ceimsel12
}
#[doc = "Comp. E V- terminal Input Select: Channel 13"]
#[inline(always)]
pub fn is_ceimsel_13(&self) -> bool {
*self == Ceimsel::Ceimsel13
}
#[doc = "Comp. E V- terminal Input Select: Channel 14"]
#[inline(always)]
pub fn is_ceimsel_14(&self) -> bool {
*self == Ceimsel::Ceimsel14
}
#[doc = "Comp. E V- terminal Input Select: Channel 15"]
#[inline(always)]
pub fn is_ceimsel_15(&self) -> bool {
*self == Ceimsel::Ceimsel15
}
}
#[doc = "Field `CEIMSEL` writer - Comp. E Neg. Channel Input Select 0"]
pub type CeimselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ceimsel, crate::Safe>;
impl<'a, REG> CeimselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Comp. E V- Terminal Input Select: Channel 0"]
#[inline(always)]
pub fn ceimsel_0(self) -> &'a mut crate::W<REG> {
self.variant(Ceimsel::Ceimsel0)
}
#[doc = "Comp. E V- Terminal Input Select: Channel 1"]
#[inline(always)]
pub fn ceimsel_1(self) -> &'a mut crate::W<REG> {
self.variant(Ceimsel::Ceimsel1)
}
#[doc = "Comp. E V- Terminal Input Select: Channel 2"]
#[inline(always)]
pub fn ceimsel_2(self) -> &'a mut crate::W<REG> {
self.variant(Ceimsel::Ceimsel2)
}
#[doc = "Comp. E V- Terminal Input Select: Channel 3"]
#[inline(always)]
pub fn ceimsel_3(self) -> &'a mut crate::W<REG> {
self.variant(Ceimsel::Ceimsel3)
}
#[doc = "Comp. E V- Terminal Input Select: Channel 4"]
#[inline(always)]
pub fn ceimsel_4(self) -> &'a mut crate::W<REG> {
self.variant(Ceimsel::Ceimsel4)
}
#[doc = "Comp. E V- Terminal Input Select: Channel 5"]
#[inline(always)]
pub fn ceimsel_5(self) -> &'a mut crate::W<REG> {
self.variant(Ceimsel::Ceimsel5)
}
#[doc = "Comp. E V- Terminal Input Select: Channel 6"]
#[inline(always)]
pub fn ceimsel_6(self) -> &'a mut crate::W<REG> {
self.variant(Ceimsel::Ceimsel6)
}
#[doc = "Comp. E V- Terminal Input Select: Channel 7"]
#[inline(always)]
pub fn ceimsel_7(self) -> &'a mut crate::W<REG> {
self.variant(Ceimsel::Ceimsel7)
}
#[doc = "Comp. E V- terminal Input Select: Channel 8"]
#[inline(always)]
pub fn ceimsel_8(self) -> &'a mut crate::W<REG> {
self.variant(Ceimsel::Ceimsel8)
}
#[doc = "Comp. E V- terminal Input Select: Channel 9"]
#[inline(always)]
pub fn ceimsel_9(self) -> &'a mut crate::W<REG> {
self.variant(Ceimsel::Ceimsel9)
}
#[doc = "Comp. E V- terminal Input Select: Channel 10"]
#[inline(always)]
pub fn ceimsel_10(self) -> &'a mut crate::W<REG> {
self.variant(Ceimsel::Ceimsel10)
}
#[doc = "Comp. E V- terminal Input Select: Channel 11"]
#[inline(always)]
pub fn ceimsel_11(self) -> &'a mut crate::W<REG> {
self.variant(Ceimsel::Ceimsel11)
}
#[doc = "Comp. E V- terminal Input Select: Channel 12"]
#[inline(always)]
pub fn ceimsel_12(self) -> &'a mut crate::W<REG> {
self.variant(Ceimsel::Ceimsel12)
}
#[doc = "Comp. E V- terminal Input Select: Channel 13"]
#[inline(always)]
pub fn ceimsel_13(self) -> &'a mut crate::W<REG> {
self.variant(Ceimsel::Ceimsel13)
}
#[doc = "Comp. E V- terminal Input Select: Channel 14"]
#[inline(always)]
pub fn ceimsel_14(self) -> &'a mut crate::W<REG> {
self.variant(Ceimsel::Ceimsel14)
}
#[doc = "Comp. E V- terminal Input Select: Channel 15"]
#[inline(always)]
pub fn ceimsel_15(self) -> &'a mut crate::W<REG> {
self.variant(Ceimsel::Ceimsel15)
}
}
#[doc = "Field `CEIMEN` reader - Comp. E Neg. Channel Input Enable"]
pub type CeimenR = crate::BitReader;
#[doc = "Field `CEIMEN` writer - Comp. E Neg. Channel Input Enable"]
pub type CeimenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:3 - Comp. E Pos. Channel Input Select 0"]
#[inline(always)]
pub fn ceipsel(&self) -> CeipselR {
CeipselR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bit 7 - Comp. E Pos. Channel Input Enable"]
#[inline(always)]
pub fn ceipen(&self) -> CeipenR {
CeipenR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - Comp. E Neg. Channel Input Select 0"]
#[inline(always)]
pub fn ceimsel(&self) -> CeimselR {
CeimselR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 15 - Comp. E Neg. Channel Input Enable"]
#[inline(always)]
pub fn ceimen(&self) -> CeimenR {
CeimenR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:3 - Comp. E Pos. Channel Input Select 0"]
#[inline(always)]
pub fn ceipsel(&mut self) -> CeipselW<'_, Cectl0Spec> {
CeipselW::new(self, 0)
}
#[doc = "Bit 7 - Comp. E Pos. Channel Input Enable"]
#[inline(always)]
pub fn ceipen(&mut self) -> CeipenW<'_, Cectl0Spec> {
CeipenW::new(self, 7)
}
#[doc = "Bits 8:11 - Comp. E Neg. Channel Input Select 0"]
#[inline(always)]
pub fn ceimsel(&mut self) -> CeimselW<'_, Cectl0Spec> {
CeimselW::new(self, 8)
}
#[doc = "Bit 15 - Comp. E Neg. Channel Input Enable"]
#[inline(always)]
pub fn ceimen(&mut self) -> CeimenW<'_, Cectl0Spec> {
CeimenW::new(self, 15)
}
}
#[doc = "Comparator E Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cectl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cectl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cectl0Spec;
impl crate::RegisterSpec for Cectl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`cectl0::R`](R) reader structure"]
impl crate::Readable for Cectl0Spec {}
#[doc = "`write(|w| ..)` method takes [`cectl0::W`](W) writer structure"]
impl crate::Writable for Cectl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CECTL0 to value 0"]
impl crate::Resettable for Cectl0Spec {}
}
#[doc = "CECTL1 (rw) register accessor: Comparator E Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cectl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cectl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cectl1`] module"]
#[doc(alias = "CECTL1")]
pub type Cectl1 = crate::Reg<cectl1::Cectl1Spec>;
#[doc = "Comparator E Control Register 1"]
pub mod cectl1 {
#[doc = "Register `CECTL1` reader"]
pub type R = crate::R<Cectl1Spec>;
#[doc = "Register `CECTL1` writer"]
pub type W = crate::W<Cectl1Spec>;
#[doc = "Field `CEOUT` reader - Comp. E Output"]
pub type CeoutR = crate::BitReader;
#[doc = "Field `CEOUT` writer - Comp. E Output"]
pub type CeoutW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEOUTPOL` reader - Comp. E Output Polarity"]
pub type CeoutpolR = crate::BitReader;
#[doc = "Field `CEOUTPOL` writer - Comp. E Output Polarity"]
pub type CeoutpolW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEF` reader - Comp. E Enable Output Filter"]
pub type CefR = crate::BitReader;
#[doc = "Field `CEF` writer - Comp. E Enable Output Filter"]
pub type CefW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEIES` reader - Comp. E Interrupt Edge Select"]
pub type CeiesR = crate::BitReader;
#[doc = "Field `CEIES` writer - Comp. E Interrupt Edge Select"]
pub type CeiesW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CESHORT` reader - Comp. E Input Short"]
pub type CeshortR = crate::BitReader;
#[doc = "Field `CESHORT` writer - Comp. E Input Short"]
pub type CeshortW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEEX` reader - Comp. E Exchange Inputs"]
pub type CeexR = crate::BitReader;
#[doc = "Field `CEEX` writer - Comp. E Exchange Inputs"]
pub type CeexW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Comp. E Filter delay Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cefdly {
#[doc = "0: Comp. E Filter delay 0 : 450ns"]
Cefdly0 = 0,
#[doc = "1: Comp. E Filter delay 1 : 900ns"]
Cefdly1 = 1,
#[doc = "2: Comp. E Filter delay 2 : 1800ns"]
Cefdly2 = 2,
#[doc = "3: Comp. E Filter delay 3 : 3600ns"]
Cefdly3 = 3,
}
impl From<Cefdly> for u8 {
#[inline(always)]
fn from(variant: Cefdly) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cefdly {
type Ux = u8;
}
impl crate::IsEnum for Cefdly {}
#[doc = "Field `CEFDLY` reader - Comp. E Filter delay Bit 0"]
pub type CefdlyR = crate::FieldReader<Cefdly>;
impl CefdlyR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cefdly {
match self.bits {
0 => Cefdly::Cefdly0,
1 => Cefdly::Cefdly1,
2 => Cefdly::Cefdly2,
3 => Cefdly::Cefdly3,
_ => unreachable!(),
}
}
#[doc = "Comp. E Filter delay 0 : 450ns"]
#[inline(always)]
pub fn is_cefdly_0(&self) -> bool {
*self == Cefdly::Cefdly0
}
#[doc = "Comp. E Filter delay 1 : 900ns"]
#[inline(always)]
pub fn is_cefdly_1(&self) -> bool {
*self == Cefdly::Cefdly1
}
#[doc = "Comp. E Filter delay 2 : 1800ns"]
#[inline(always)]
pub fn is_cefdly_2(&self) -> bool {
*self == Cefdly::Cefdly2
}
#[doc = "Comp. E Filter delay 3 : 3600ns"]
#[inline(always)]
pub fn is_cefdly_3(&self) -> bool {
*self == Cefdly::Cefdly3
}
}
#[doc = "Field `CEFDLY` writer - Comp. E Filter delay Bit 0"]
pub type CefdlyW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cefdly, crate::Safe>;
impl<'a, REG> CefdlyW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Comp. E Filter delay 0 : 450ns"]
#[inline(always)]
pub fn cefdly_0(self) -> &'a mut crate::W<REG> {
self.variant(Cefdly::Cefdly0)
}
#[doc = "Comp. E Filter delay 1 : 900ns"]
#[inline(always)]
pub fn cefdly_1(self) -> &'a mut crate::W<REG> {
self.variant(Cefdly::Cefdly1)
}
#[doc = "Comp. E Filter delay 2 : 1800ns"]
#[inline(always)]
pub fn cefdly_2(self) -> &'a mut crate::W<REG> {
self.variant(Cefdly::Cefdly2)
}
#[doc = "Comp. E Filter delay 3 : 3600ns"]
#[inline(always)]
pub fn cefdly_3(self) -> &'a mut crate::W<REG> {
self.variant(Cefdly::Cefdly3)
}
}
#[doc = "Comp. E Power mode Bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cepwrmd {
#[doc = "0: Comp. E Power mode 0"]
Cepwrmd0 = 0,
#[doc = "1: Comp. E Power mode 1"]
Cepwrmd1 = 1,
#[doc = "2: Comp. E Power mode 2"]
Cepwrmd2 = 2,
#[doc = "3: Comp. E Power mode 3"]
Cepwrmd3 = 3,
}
impl From<Cepwrmd> for u8 {
#[inline(always)]
fn from(variant: Cepwrmd) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cepwrmd {
type Ux = u8;
}
impl crate::IsEnum for Cepwrmd {}
#[doc = "Field `CEPWRMD` reader - Comp. E Power mode Bit 0"]
pub type CepwrmdR = crate::FieldReader<Cepwrmd>;
impl CepwrmdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cepwrmd {
match self.bits {
0 => Cepwrmd::Cepwrmd0,
1 => Cepwrmd::Cepwrmd1,
2 => Cepwrmd::Cepwrmd2,
3 => Cepwrmd::Cepwrmd3,
_ => unreachable!(),
}
}
#[doc = "Comp. E Power mode 0"]
#[inline(always)]
pub fn is_cepwrmd_0(&self) -> bool {
*self == Cepwrmd::Cepwrmd0
}
#[doc = "Comp. E Power mode 1"]
#[inline(always)]
pub fn is_cepwrmd_1(&self) -> bool {
*self == Cepwrmd::Cepwrmd1
}
#[doc = "Comp. E Power mode 2"]
#[inline(always)]
pub fn is_cepwrmd_2(&self) -> bool {
*self == Cepwrmd::Cepwrmd2
}
#[doc = "Comp. E Power mode 3"]
#[inline(always)]
pub fn is_cepwrmd_3(&self) -> bool {
*self == Cepwrmd::Cepwrmd3
}
}
#[doc = "Field `CEPWRMD` writer - Comp. E Power mode Bit 0"]
pub type CepwrmdW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cepwrmd, crate::Safe>;
impl<'a, REG> CepwrmdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Comp. E Power mode 0"]
#[inline(always)]
pub fn cepwrmd_0(self) -> &'a mut crate::W<REG> {
self.variant(Cepwrmd::Cepwrmd0)
}
#[doc = "Comp. E Power mode 1"]
#[inline(always)]
pub fn cepwrmd_1(self) -> &'a mut crate::W<REG> {
self.variant(Cepwrmd::Cepwrmd1)
}
#[doc = "Comp. E Power mode 2"]
#[inline(always)]
pub fn cepwrmd_2(self) -> &'a mut crate::W<REG> {
self.variant(Cepwrmd::Cepwrmd2)
}
#[doc = "Comp. E Power mode 3"]
#[inline(always)]
pub fn cepwrmd_3(self) -> &'a mut crate::W<REG> {
self.variant(Cepwrmd::Cepwrmd3)
}
}
#[doc = "Field `CEON` reader - Comp. E enable"]
pub type CeonR = crate::BitReader;
#[doc = "Field `CEON` writer - Comp. E enable"]
pub type CeonW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEMRVL` reader - Comp. E CEMRV Level"]
pub type CemrvlR = crate::BitReader;
#[doc = "Field `CEMRVL` writer - Comp. E CEMRV Level"]
pub type CemrvlW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEMRVS` reader - Comp. E Output selects between VREF0 or VREF1"]
pub type CemrvsR = crate::BitReader;
#[doc = "Field `CEMRVS` writer - Comp. E Output selects between VREF0 or VREF1"]
pub type CemrvsW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Comp. E Output"]
#[inline(always)]
pub fn ceout(&self) -> CeoutR {
CeoutR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Comp. E Output Polarity"]
#[inline(always)]
pub fn ceoutpol(&self) -> CeoutpolR {
CeoutpolR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Comp. E Enable Output Filter"]
#[inline(always)]
pub fn cef(&self) -> CefR {
CefR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Comp. E Interrupt Edge Select"]
#[inline(always)]
pub fn ceies(&self) -> CeiesR {
CeiesR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Comp. E Input Short"]
#[inline(always)]
pub fn ceshort(&self) -> CeshortR {
CeshortR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Comp. E Exchange Inputs"]
#[inline(always)]
pub fn ceex(&self) -> CeexR {
CeexR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:7 - Comp. E Filter delay Bit 0"]
#[inline(always)]
pub fn cefdly(&self) -> CefdlyR {
CefdlyR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:9 - Comp. E Power mode Bit 0"]
#[inline(always)]
pub fn cepwrmd(&self) -> CepwrmdR {
CepwrmdR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 10 - Comp. E enable"]
#[inline(always)]
pub fn ceon(&self) -> CeonR {
CeonR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Comp. E CEMRV Level"]
#[inline(always)]
pub fn cemrvl(&self) -> CemrvlR {
CemrvlR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Comp. E Output selects between VREF0 or VREF1"]
#[inline(always)]
pub fn cemrvs(&self) -> CemrvsR {
CemrvsR::new(((self.bits >> 12) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Comp. E Output"]
#[inline(always)]
pub fn ceout(&mut self) -> CeoutW<'_, Cectl1Spec> {
CeoutW::new(self, 0)
}
#[doc = "Bit 1 - Comp. E Output Polarity"]
#[inline(always)]
pub fn ceoutpol(&mut self) -> CeoutpolW<'_, Cectl1Spec> {
CeoutpolW::new(self, 1)
}
#[doc = "Bit 2 - Comp. E Enable Output Filter"]
#[inline(always)]
pub fn cef(&mut self) -> CefW<'_, Cectl1Spec> {
CefW::new(self, 2)
}
#[doc = "Bit 3 - Comp. E Interrupt Edge Select"]
#[inline(always)]
pub fn ceies(&mut self) -> CeiesW<'_, Cectl1Spec> {
CeiesW::new(self, 3)
}
#[doc = "Bit 4 - Comp. E Input Short"]
#[inline(always)]
pub fn ceshort(&mut self) -> CeshortW<'_, Cectl1Spec> {
CeshortW::new(self, 4)
}
#[doc = "Bit 5 - Comp. E Exchange Inputs"]
#[inline(always)]
pub fn ceex(&mut self) -> CeexW<'_, Cectl1Spec> {
CeexW::new(self, 5)
}
#[doc = "Bits 6:7 - Comp. E Filter delay Bit 0"]
#[inline(always)]
pub fn cefdly(&mut self) -> CefdlyW<'_, Cectl1Spec> {
CefdlyW::new(self, 6)
}
#[doc = "Bits 8:9 - Comp. E Power mode Bit 0"]
#[inline(always)]
pub fn cepwrmd(&mut self) -> CepwrmdW<'_, Cectl1Spec> {
CepwrmdW::new(self, 8)
}
#[doc = "Bit 10 - Comp. E enable"]
#[inline(always)]
pub fn ceon(&mut self) -> CeonW<'_, Cectl1Spec> {
CeonW::new(self, 10)
}
#[doc = "Bit 11 - Comp. E CEMRV Level"]
#[inline(always)]
pub fn cemrvl(&mut self) -> CemrvlW<'_, Cectl1Spec> {
CemrvlW::new(self, 11)
}
#[doc = "Bit 12 - Comp. E Output selects between VREF0 or VREF1"]
#[inline(always)]
pub fn cemrvs(&mut self) -> CemrvsW<'_, Cectl1Spec> {
CemrvsW::new(self, 12)
}
}
#[doc = "Comparator E Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cectl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cectl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cectl1Spec;
impl crate::RegisterSpec for Cectl1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`cectl1::R`](R) reader structure"]
impl crate::Readable for Cectl1Spec {}
#[doc = "`write(|w| ..)` method takes [`cectl1::W`](W) writer structure"]
impl crate::Writable for Cectl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CECTL1 to value 0"]
impl crate::Resettable for Cectl1Spec {}
}
#[doc = "CECTL2 (rw) register accessor: Comparator E Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`cectl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cectl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cectl2`] module"]
#[doc(alias = "CECTL2")]
pub type Cectl2 = crate::Reg<cectl2::Cectl2Spec>;
#[doc = "Comparator E Control Register 2"]
pub mod cectl2 {
#[doc = "Register `CECTL2` reader"]
pub type R = crate::R<Cectl2Spec>;
#[doc = "Register `CECTL2` writer"]
pub type W = crate::W<Cectl2Spec>;
#[doc = "Comp. E Reference 0 Resistor Select Bit : 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ceref0 {
#[doc = "0: Comp. E Int. Ref.0 Select 0 : 1/32"]
Ceref0_0 = 0,
#[doc = "1: Comp. E Int. Ref.0 Select 1 : 2/32"]
Ceref0_1 = 1,
#[doc = "2: Comp. E Int. Ref.0 Select 2 : 3/32"]
Ceref0_2 = 2,
#[doc = "3: Comp. E Int. Ref.0 Select 3 : 4/32"]
Ceref0_3 = 3,
#[doc = "4: Comp. E Int. Ref.0 Select 4 : 5/32"]
Ceref0_4 = 4,
#[doc = "5: Comp. E Int. Ref.0 Select 5 : 6/32"]
Ceref0_5 = 5,
#[doc = "6: Comp. E Int. Ref.0 Select 6 : 7/32"]
Ceref0_6 = 6,
#[doc = "7: Comp. E Int. Ref.0 Select 7 : 8/32"]
Ceref0_7 = 7,
#[doc = "8: Comp. E Int. Ref.0 Select 0 : 9/32"]
Ceref0_8 = 8,
#[doc = "9: Comp. E Int. Ref.0 Select 1 : 10/32"]
Ceref0_9 = 9,
#[doc = "10: Comp. E Int. Ref.0 Select 2 : 11/32"]
Ceref0_10 = 10,
#[doc = "11: Comp. E Int. Ref.0 Select 3 : 12/32"]
Ceref0_11 = 11,
#[doc = "12: Comp. E Int. Ref.0 Select 4 : 13/32"]
Ceref0_12 = 12,
#[doc = "13: Comp. E Int. Ref.0 Select 5 : 14/32"]
Ceref0_13 = 13,
#[doc = "14: Comp. E Int. Ref.0 Select 6 : 15/32"]
Ceref0_14 = 14,
#[doc = "15: Comp. E Int. Ref.0 Select 7 : 16/32"]
Ceref0_15 = 15,
#[doc = "16: Comp. E Int. Ref.0 Select 0 : 17/32"]
Ceref0_16 = 16,
#[doc = "17: Comp. E Int. Ref.0 Select 1 : 18/32"]
Ceref0_17 = 17,
#[doc = "18: Comp. E Int. Ref.0 Select 2 : 19/32"]
Ceref0_18 = 18,
#[doc = "19: Comp. E Int. Ref.0 Select 3 : 20/32"]
Ceref0_19 = 19,
#[doc = "20: Comp. E Int. Ref.0 Select 4 : 21/32"]
Ceref0_20 = 20,
#[doc = "21: Comp. E Int. Ref.0 Select 5 : 22/32"]
Ceref0_21 = 21,
#[doc = "22: Comp. E Int. Ref.0 Select 6 : 23/32"]
Ceref0_22 = 22,
#[doc = "23: Comp. E Int. Ref.0 Select 7 : 24/32"]
Ceref0_23 = 23,
#[doc = "24: Comp. E Int. Ref.0 Select 0 : 25/32"]
Ceref0_24 = 24,
#[doc = "25: Comp. E Int. Ref.0 Select 1 : 26/32"]
Ceref0_25 = 25,
#[doc = "26: Comp. E Int. Ref.0 Select 2 : 27/32"]
Ceref0_26 = 26,
#[doc = "27: Comp. E Int. Ref.0 Select 3 : 28/32"]
Ceref0_27 = 27,
#[doc = "28: Comp. E Int. Ref.0 Select 4 : 29/32"]
Ceref0_28 = 28,
#[doc = "29: Comp. E Int. Ref.0 Select 5 : 30/32"]
Ceref0_29 = 29,
#[doc = "30: Comp. E Int. Ref.0 Select 6 : 31/32"]
Ceref0_30 = 30,
#[doc = "31: Comp. E Int. Ref.0 Select 7 : 32/32"]
Ceref0_31 = 31,
}
impl From<Ceref0> for u8 {
#[inline(always)]
fn from(variant: Ceref0) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ceref0 {
type Ux = u8;
}
impl crate::IsEnum for Ceref0 {}
#[doc = "Field `CEREF0` reader - Comp. E Reference 0 Resistor Select Bit : 0"]
pub type Ceref0R = crate::FieldReader<Ceref0>;
impl Ceref0R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ceref0 {
match self.bits {
0 => Ceref0::Ceref0_0,
1 => Ceref0::Ceref0_1,
2 => Ceref0::Ceref0_2,
3 => Ceref0::Ceref0_3,
4 => Ceref0::Ceref0_4,
5 => Ceref0::Ceref0_5,
6 => Ceref0::Ceref0_6,
7 => Ceref0::Ceref0_7,
8 => Ceref0::Ceref0_8,
9 => Ceref0::Ceref0_9,
10 => Ceref0::Ceref0_10,
11 => Ceref0::Ceref0_11,
12 => Ceref0::Ceref0_12,
13 => Ceref0::Ceref0_13,
14 => Ceref0::Ceref0_14,
15 => Ceref0::Ceref0_15,
16 => Ceref0::Ceref0_16,
17 => Ceref0::Ceref0_17,
18 => Ceref0::Ceref0_18,
19 => Ceref0::Ceref0_19,
20 => Ceref0::Ceref0_20,
21 => Ceref0::Ceref0_21,
22 => Ceref0::Ceref0_22,
23 => Ceref0::Ceref0_23,
24 => Ceref0::Ceref0_24,
25 => Ceref0::Ceref0_25,
26 => Ceref0::Ceref0_26,
27 => Ceref0::Ceref0_27,
28 => Ceref0::Ceref0_28,
29 => Ceref0::Ceref0_29,
30 => Ceref0::Ceref0_30,
31 => Ceref0::Ceref0_31,
_ => unreachable!(),
}
}
#[doc = "Comp. E Int. Ref.0 Select 0 : 1/32"]
#[inline(always)]
pub fn is_ceref0_0(&self) -> bool {
*self == Ceref0::Ceref0_0
}
#[doc = "Comp. E Int. Ref.0 Select 1 : 2/32"]
#[inline(always)]
pub fn is_ceref0_1(&self) -> bool {
*self == Ceref0::Ceref0_1
}
#[doc = "Comp. E Int. Ref.0 Select 2 : 3/32"]
#[inline(always)]
pub fn is_ceref0_2(&self) -> bool {
*self == Ceref0::Ceref0_2
}
#[doc = "Comp. E Int. Ref.0 Select 3 : 4/32"]
#[inline(always)]
pub fn is_ceref0_3(&self) -> bool {
*self == Ceref0::Ceref0_3
}
#[doc = "Comp. E Int. Ref.0 Select 4 : 5/32"]
#[inline(always)]
pub fn is_ceref0_4(&self) -> bool {
*self == Ceref0::Ceref0_4
}
#[doc = "Comp. E Int. Ref.0 Select 5 : 6/32"]
#[inline(always)]
pub fn is_ceref0_5(&self) -> bool {
*self == Ceref0::Ceref0_5
}
#[doc = "Comp. E Int. Ref.0 Select 6 : 7/32"]
#[inline(always)]
pub fn is_ceref0_6(&self) -> bool {
*self == Ceref0::Ceref0_6
}
#[doc = "Comp. E Int. Ref.0 Select 7 : 8/32"]
#[inline(always)]
pub fn is_ceref0_7(&self) -> bool {
*self == Ceref0::Ceref0_7
}
#[doc = "Comp. E Int. Ref.0 Select 0 : 9/32"]
#[inline(always)]
pub fn is_ceref0_8(&self) -> bool {
*self == Ceref0::Ceref0_8
}
#[doc = "Comp. E Int. Ref.0 Select 1 : 10/32"]
#[inline(always)]
pub fn is_ceref0_9(&self) -> bool {
*self == Ceref0::Ceref0_9
}
#[doc = "Comp. E Int. Ref.0 Select 2 : 11/32"]
#[inline(always)]
pub fn is_ceref0_10(&self) -> bool {
*self == Ceref0::Ceref0_10
}
#[doc = "Comp. E Int. Ref.0 Select 3 : 12/32"]
#[inline(always)]
pub fn is_ceref0_11(&self) -> bool {
*self == Ceref0::Ceref0_11
}
#[doc = "Comp. E Int. Ref.0 Select 4 : 13/32"]
#[inline(always)]
pub fn is_ceref0_12(&self) -> bool {
*self == Ceref0::Ceref0_12
}
#[doc = "Comp. E Int. Ref.0 Select 5 : 14/32"]
#[inline(always)]
pub fn is_ceref0_13(&self) -> bool {
*self == Ceref0::Ceref0_13
}
#[doc = "Comp. E Int. Ref.0 Select 6 : 15/32"]
#[inline(always)]
pub fn is_ceref0_14(&self) -> bool {
*self == Ceref0::Ceref0_14
}
#[doc = "Comp. E Int. Ref.0 Select 7 : 16/32"]
#[inline(always)]
pub fn is_ceref0_15(&self) -> bool {
*self == Ceref0::Ceref0_15
}
#[doc = "Comp. E Int. Ref.0 Select 0 : 17/32"]
#[inline(always)]
pub fn is_ceref0_16(&self) -> bool {
*self == Ceref0::Ceref0_16
}
#[doc = "Comp. E Int. Ref.0 Select 1 : 18/32"]
#[inline(always)]
pub fn is_ceref0_17(&self) -> bool {
*self == Ceref0::Ceref0_17
}
#[doc = "Comp. E Int. Ref.0 Select 2 : 19/32"]
#[inline(always)]
pub fn is_ceref0_18(&self) -> bool {
*self == Ceref0::Ceref0_18
}
#[doc = "Comp. E Int. Ref.0 Select 3 : 20/32"]
#[inline(always)]
pub fn is_ceref0_19(&self) -> bool {
*self == Ceref0::Ceref0_19
}
#[doc = "Comp. E Int. Ref.0 Select 4 : 21/32"]
#[inline(always)]
pub fn is_ceref0_20(&self) -> bool {
*self == Ceref0::Ceref0_20
}
#[doc = "Comp. E Int. Ref.0 Select 5 : 22/32"]
#[inline(always)]
pub fn is_ceref0_21(&self) -> bool {
*self == Ceref0::Ceref0_21
}
#[doc = "Comp. E Int. Ref.0 Select 6 : 23/32"]
#[inline(always)]
pub fn is_ceref0_22(&self) -> bool {
*self == Ceref0::Ceref0_22
}
#[doc = "Comp. E Int. Ref.0 Select 7 : 24/32"]
#[inline(always)]
pub fn is_ceref0_23(&self) -> bool {
*self == Ceref0::Ceref0_23
}
#[doc = "Comp. E Int. Ref.0 Select 0 : 25/32"]
#[inline(always)]
pub fn is_ceref0_24(&self) -> bool {
*self == Ceref0::Ceref0_24
}
#[doc = "Comp. E Int. Ref.0 Select 1 : 26/32"]
#[inline(always)]
pub fn is_ceref0_25(&self) -> bool {
*self == Ceref0::Ceref0_25
}
#[doc = "Comp. E Int. Ref.0 Select 2 : 27/32"]
#[inline(always)]
pub fn is_ceref0_26(&self) -> bool {
*self == Ceref0::Ceref0_26
}
#[doc = "Comp. E Int. Ref.0 Select 3 : 28/32"]
#[inline(always)]
pub fn is_ceref0_27(&self) -> bool {
*self == Ceref0::Ceref0_27
}
#[doc = "Comp. E Int. Ref.0 Select 4 : 29/32"]
#[inline(always)]
pub fn is_ceref0_28(&self) -> bool {
*self == Ceref0::Ceref0_28
}
#[doc = "Comp. E Int. Ref.0 Select 5 : 30/32"]
#[inline(always)]
pub fn is_ceref0_29(&self) -> bool {
*self == Ceref0::Ceref0_29
}
#[doc = "Comp. E Int. Ref.0 Select 6 : 31/32"]
#[inline(always)]
pub fn is_ceref0_30(&self) -> bool {
*self == Ceref0::Ceref0_30
}
#[doc = "Comp. E Int. Ref.0 Select 7 : 32/32"]
#[inline(always)]
pub fn is_ceref0_31(&self) -> bool {
*self == Ceref0::Ceref0_31
}
}
#[doc = "Field `CEREF0` writer - Comp. E Reference 0 Resistor Select Bit : 0"]
pub type Ceref0W<'a, REG> = crate::FieldWriter<'a, REG, 5, Ceref0, crate::Safe>;
impl<'a, REG> Ceref0W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Comp. E Int. Ref.0 Select 0 : 1/32"]
#[inline(always)]
pub fn ceref0_0(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_0)
}
#[doc = "Comp. E Int. Ref.0 Select 1 : 2/32"]
#[inline(always)]
pub fn ceref0_1(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_1)
}
#[doc = "Comp. E Int. Ref.0 Select 2 : 3/32"]
#[inline(always)]
pub fn ceref0_2(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_2)
}
#[doc = "Comp. E Int. Ref.0 Select 3 : 4/32"]
#[inline(always)]
pub fn ceref0_3(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_3)
}
#[doc = "Comp. E Int. Ref.0 Select 4 : 5/32"]
#[inline(always)]
pub fn ceref0_4(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_4)
}
#[doc = "Comp. E Int. Ref.0 Select 5 : 6/32"]
#[inline(always)]
pub fn ceref0_5(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_5)
}
#[doc = "Comp. E Int. Ref.0 Select 6 : 7/32"]
#[inline(always)]
pub fn ceref0_6(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_6)
}
#[doc = "Comp. E Int. Ref.0 Select 7 : 8/32"]
#[inline(always)]
pub fn ceref0_7(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_7)
}
#[doc = "Comp. E Int. Ref.0 Select 0 : 9/32"]
#[inline(always)]
pub fn ceref0_8(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_8)
}
#[doc = "Comp. E Int. Ref.0 Select 1 : 10/32"]
#[inline(always)]
pub fn ceref0_9(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_9)
}
#[doc = "Comp. E Int. Ref.0 Select 2 : 11/32"]
#[inline(always)]
pub fn ceref0_10(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_10)
}
#[doc = "Comp. E Int. Ref.0 Select 3 : 12/32"]
#[inline(always)]
pub fn ceref0_11(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_11)
}
#[doc = "Comp. E Int. Ref.0 Select 4 : 13/32"]
#[inline(always)]
pub fn ceref0_12(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_12)
}
#[doc = "Comp. E Int. Ref.0 Select 5 : 14/32"]
#[inline(always)]
pub fn ceref0_13(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_13)
}
#[doc = "Comp. E Int. Ref.0 Select 6 : 15/32"]
#[inline(always)]
pub fn ceref0_14(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_14)
}
#[doc = "Comp. E Int. Ref.0 Select 7 : 16/32"]
#[inline(always)]
pub fn ceref0_15(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_15)
}
#[doc = "Comp. E Int. Ref.0 Select 0 : 17/32"]
#[inline(always)]
pub fn ceref0_16(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_16)
}
#[doc = "Comp. E Int. Ref.0 Select 1 : 18/32"]
#[inline(always)]
pub fn ceref0_17(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_17)
}
#[doc = "Comp. E Int. Ref.0 Select 2 : 19/32"]
#[inline(always)]
pub fn ceref0_18(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_18)
}
#[doc = "Comp. E Int. Ref.0 Select 3 : 20/32"]
#[inline(always)]
pub fn ceref0_19(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_19)
}
#[doc = "Comp. E Int. Ref.0 Select 4 : 21/32"]
#[inline(always)]
pub fn ceref0_20(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_20)
}
#[doc = "Comp. E Int. Ref.0 Select 5 : 22/32"]
#[inline(always)]
pub fn ceref0_21(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_21)
}
#[doc = "Comp. E Int. Ref.0 Select 6 : 23/32"]
#[inline(always)]
pub fn ceref0_22(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_22)
}
#[doc = "Comp. E Int. Ref.0 Select 7 : 24/32"]
#[inline(always)]
pub fn ceref0_23(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_23)
}
#[doc = "Comp. E Int. Ref.0 Select 0 : 25/32"]
#[inline(always)]
pub fn ceref0_24(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_24)
}
#[doc = "Comp. E Int. Ref.0 Select 1 : 26/32"]
#[inline(always)]
pub fn ceref0_25(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_25)
}
#[doc = "Comp. E Int. Ref.0 Select 2 : 27/32"]
#[inline(always)]
pub fn ceref0_26(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_26)
}
#[doc = "Comp. E Int. Ref.0 Select 3 : 28/32"]
#[inline(always)]
pub fn ceref0_27(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_27)
}
#[doc = "Comp. E Int. Ref.0 Select 4 : 29/32"]
#[inline(always)]
pub fn ceref0_28(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_28)
}
#[doc = "Comp. E Int. Ref.0 Select 5 : 30/32"]
#[inline(always)]
pub fn ceref0_29(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_29)
}
#[doc = "Comp. E Int. Ref.0 Select 6 : 31/32"]
#[inline(always)]
pub fn ceref0_30(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_30)
}
#[doc = "Comp. E Int. Ref.0 Select 7 : 32/32"]
#[inline(always)]
pub fn ceref0_31(self) -> &'a mut crate::W<REG> {
self.variant(Ceref0::Ceref0_31)
}
}
#[doc = "Field `CERSEL` reader - Comp. E Reference select"]
pub type CerselR = crate::BitReader;
#[doc = "Field `CERSEL` writer - Comp. E Reference select"]
pub type CerselW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Comp. E Reference Source Bit : 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cers {
#[doc = "0: Comp. E Reference Source 0 : Off"]
Cers0 = 0,
#[doc = "1: Comp. E Reference Source 1 : Vcc"]
Cers1 = 1,
#[doc = "2: Comp. E Reference Source 2 : Shared Ref."]
Cers2 = 2,
#[doc = "3: Comp. E Reference Source 3 : Shared Ref. / Off"]
Cers3 = 3,
}
impl From<Cers> for u8 {
#[inline(always)]
fn from(variant: Cers) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cers {
type Ux = u8;
}
impl crate::IsEnum for Cers {}
#[doc = "Field `CERS` reader - Comp. E Reference Source Bit : 0"]
pub type CersR = crate::FieldReader<Cers>;
impl CersR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cers {
match self.bits {
0 => Cers::Cers0,
1 => Cers::Cers1,
2 => Cers::Cers2,
3 => Cers::Cers3,
_ => unreachable!(),
}
}
#[doc = "Comp. E Reference Source 0 : Off"]
#[inline(always)]
pub fn is_cers_0(&self) -> bool {
*self == Cers::Cers0
}
#[doc = "Comp. E Reference Source 1 : Vcc"]
#[inline(always)]
pub fn is_cers_1(&self) -> bool {
*self == Cers::Cers1
}
#[doc = "Comp. E Reference Source 2 : Shared Ref."]
#[inline(always)]
pub fn is_cers_2(&self) -> bool {
*self == Cers::Cers2
}
#[doc = "Comp. E Reference Source 3 : Shared Ref. / Off"]
#[inline(always)]
pub fn is_cers_3(&self) -> bool {
*self == Cers::Cers3
}
}
#[doc = "Field `CERS` writer - Comp. E Reference Source Bit : 0"]
pub type CersW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cers, crate::Safe>;
impl<'a, REG> CersW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Comp. E Reference Source 0 : Off"]
#[inline(always)]
pub fn cers_0(self) -> &'a mut crate::W<REG> {
self.variant(Cers::Cers0)
}
#[doc = "Comp. E Reference Source 1 : Vcc"]
#[inline(always)]
pub fn cers_1(self) -> &'a mut crate::W<REG> {
self.variant(Cers::Cers1)
}
#[doc = "Comp. E Reference Source 2 : Shared Ref."]
#[inline(always)]
pub fn cers_2(self) -> &'a mut crate::W<REG> {
self.variant(Cers::Cers2)
}
#[doc = "Comp. E Reference Source 3 : Shared Ref. / Off"]
#[inline(always)]
pub fn cers_3(self) -> &'a mut crate::W<REG> {
self.variant(Cers::Cers3)
}
}
#[doc = "Comp. E Reference 1 Resistor Select Bit : 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ceref1 {
#[doc = "0: Comp. E Int. Ref.1 Select 0 : 1/32"]
Ceref1_0 = 0,
#[doc = "1: Comp. E Int. Ref.1 Select 1 : 2/32"]
Ceref1_1 = 1,
#[doc = "2: Comp. E Int. Ref.1 Select 2 : 3/32"]
Ceref1_2 = 2,
#[doc = "3: Comp. E Int. Ref.1 Select 3 : 4/32"]
Ceref1_3 = 3,
#[doc = "4: Comp. E Int. Ref.1 Select 4 : 5/32"]
Ceref1_4 = 4,
#[doc = "5: Comp. E Int. Ref.1 Select 5 : 6/32"]
Ceref1_5 = 5,
#[doc = "6: Comp. E Int. Ref.1 Select 6 : 7/32"]
Ceref1_6 = 6,
#[doc = "7: Comp. E Int. Ref.1 Select 7 : 8/32"]
Ceref1_7 = 7,
#[doc = "8: Comp. E Int. Ref.1 Select 0 : 9/32"]
Ceref1_8 = 8,
#[doc = "9: Comp. E Int. Ref.1 Select 1 : 10/32"]
Ceref1_9 = 9,
#[doc = "10: Comp. E Int. Ref.1 Select 2 : 11/32"]
Ceref1_10 = 10,
#[doc = "11: Comp. E Int. Ref.1 Select 3 : 12/32"]
Ceref1_11 = 11,
#[doc = "12: Comp. E Int. Ref.1 Select 4 : 13/32"]
Ceref1_12 = 12,
#[doc = "13: Comp. E Int. Ref.1 Select 5 : 14/32"]
Ceref1_13 = 13,
#[doc = "14: Comp. E Int. Ref.1 Select 6 : 15/32"]
Ceref1_14 = 14,
#[doc = "15: Comp. E Int. Ref.1 Select 7 : 16/32"]
Ceref1_15 = 15,
#[doc = "16: Comp. E Int. Ref.1 Select 0 : 17/32"]
Ceref1_16 = 16,
#[doc = "17: Comp. E Int. Ref.1 Select 1 : 18/32"]
Ceref1_17 = 17,
#[doc = "18: Comp. E Int. Ref.1 Select 2 : 19/32"]
Ceref1_18 = 18,
#[doc = "19: Comp. E Int. Ref.1 Select 3 : 20/32"]
Ceref1_19 = 19,
#[doc = "20: Comp. E Int. Ref.1 Select 4 : 21/32"]
Ceref1_20 = 20,
#[doc = "21: Comp. E Int. Ref.1 Select 5 : 22/32"]
Ceref1_21 = 21,
#[doc = "22: Comp. E Int. Ref.1 Select 6 : 23/32"]
Ceref1_22 = 22,
#[doc = "23: Comp. E Int. Ref.1 Select 7 : 24/32"]
Ceref1_23 = 23,
#[doc = "24: Comp. E Int. Ref.1 Select 0 : 25/32"]
Ceref1_24 = 24,
#[doc = "25: Comp. E Int. Ref.1 Select 1 : 26/32"]
Ceref1_25 = 25,
#[doc = "26: Comp. E Int. Ref.1 Select 2 : 27/32"]
Ceref1_26 = 26,
#[doc = "27: Comp. E Int. Ref.1 Select 3 : 28/32"]
Ceref1_27 = 27,
#[doc = "28: Comp. E Int. Ref.1 Select 4 : 29/32"]
Ceref1_28 = 28,
#[doc = "29: Comp. E Int. Ref.1 Select 5 : 30/32"]
Ceref1_29 = 29,
#[doc = "30: Comp. E Int. Ref.1 Select 6 : 31/32"]
Ceref1_30 = 30,
#[doc = "31: Comp. E Int. Ref.1 Select 7 : 32/32"]
Ceref1_31 = 31,
}
impl From<Ceref1> for u8 {
#[inline(always)]
fn from(variant: Ceref1) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ceref1 {
type Ux = u8;
}
impl crate::IsEnum for Ceref1 {}
#[doc = "Field `CEREF1` reader - Comp. E Reference 1 Resistor Select Bit : 0"]
pub type Ceref1R = crate::FieldReader<Ceref1>;
impl Ceref1R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ceref1 {
match self.bits {
0 => Ceref1::Ceref1_0,
1 => Ceref1::Ceref1_1,
2 => Ceref1::Ceref1_2,
3 => Ceref1::Ceref1_3,
4 => Ceref1::Ceref1_4,
5 => Ceref1::Ceref1_5,
6 => Ceref1::Ceref1_6,
7 => Ceref1::Ceref1_7,
8 => Ceref1::Ceref1_8,
9 => Ceref1::Ceref1_9,
10 => Ceref1::Ceref1_10,
11 => Ceref1::Ceref1_11,
12 => Ceref1::Ceref1_12,
13 => Ceref1::Ceref1_13,
14 => Ceref1::Ceref1_14,
15 => Ceref1::Ceref1_15,
16 => Ceref1::Ceref1_16,
17 => Ceref1::Ceref1_17,
18 => Ceref1::Ceref1_18,
19 => Ceref1::Ceref1_19,
20 => Ceref1::Ceref1_20,
21 => Ceref1::Ceref1_21,
22 => Ceref1::Ceref1_22,
23 => Ceref1::Ceref1_23,
24 => Ceref1::Ceref1_24,
25 => Ceref1::Ceref1_25,
26 => Ceref1::Ceref1_26,
27 => Ceref1::Ceref1_27,
28 => Ceref1::Ceref1_28,
29 => Ceref1::Ceref1_29,
30 => Ceref1::Ceref1_30,
31 => Ceref1::Ceref1_31,
_ => unreachable!(),
}
}
#[doc = "Comp. E Int. Ref.1 Select 0 : 1/32"]
#[inline(always)]
pub fn is_ceref1_0(&self) -> bool {
*self == Ceref1::Ceref1_0
}
#[doc = "Comp. E Int. Ref.1 Select 1 : 2/32"]
#[inline(always)]
pub fn is_ceref1_1(&self) -> bool {
*self == Ceref1::Ceref1_1
}
#[doc = "Comp. E Int. Ref.1 Select 2 : 3/32"]
#[inline(always)]
pub fn is_ceref1_2(&self) -> bool {
*self == Ceref1::Ceref1_2
}
#[doc = "Comp. E Int. Ref.1 Select 3 : 4/32"]
#[inline(always)]
pub fn is_ceref1_3(&self) -> bool {
*self == Ceref1::Ceref1_3
}
#[doc = "Comp. E Int. Ref.1 Select 4 : 5/32"]
#[inline(always)]
pub fn is_ceref1_4(&self) -> bool {
*self == Ceref1::Ceref1_4
}
#[doc = "Comp. E Int. Ref.1 Select 5 : 6/32"]
#[inline(always)]
pub fn is_ceref1_5(&self) -> bool {
*self == Ceref1::Ceref1_5
}
#[doc = "Comp. E Int. Ref.1 Select 6 : 7/32"]
#[inline(always)]
pub fn is_ceref1_6(&self) -> bool {
*self == Ceref1::Ceref1_6
}
#[doc = "Comp. E Int. Ref.1 Select 7 : 8/32"]
#[inline(always)]
pub fn is_ceref1_7(&self) -> bool {
*self == Ceref1::Ceref1_7
}
#[doc = "Comp. E Int. Ref.1 Select 0 : 9/32"]
#[inline(always)]
pub fn is_ceref1_8(&self) -> bool {
*self == Ceref1::Ceref1_8
}
#[doc = "Comp. E Int. Ref.1 Select 1 : 10/32"]
#[inline(always)]
pub fn is_ceref1_9(&self) -> bool {
*self == Ceref1::Ceref1_9
}
#[doc = "Comp. E Int. Ref.1 Select 2 : 11/32"]
#[inline(always)]
pub fn is_ceref1_10(&self) -> bool {
*self == Ceref1::Ceref1_10
}
#[doc = "Comp. E Int. Ref.1 Select 3 : 12/32"]
#[inline(always)]
pub fn is_ceref1_11(&self) -> bool {
*self == Ceref1::Ceref1_11
}
#[doc = "Comp. E Int. Ref.1 Select 4 : 13/32"]
#[inline(always)]
pub fn is_ceref1_12(&self) -> bool {
*self == Ceref1::Ceref1_12
}
#[doc = "Comp. E Int. Ref.1 Select 5 : 14/32"]
#[inline(always)]
pub fn is_ceref1_13(&self) -> bool {
*self == Ceref1::Ceref1_13
}
#[doc = "Comp. E Int. Ref.1 Select 6 : 15/32"]
#[inline(always)]
pub fn is_ceref1_14(&self) -> bool {
*self == Ceref1::Ceref1_14
}
#[doc = "Comp. E Int. Ref.1 Select 7 : 16/32"]
#[inline(always)]
pub fn is_ceref1_15(&self) -> bool {
*self == Ceref1::Ceref1_15
}
#[doc = "Comp. E Int. Ref.1 Select 0 : 17/32"]
#[inline(always)]
pub fn is_ceref1_16(&self) -> bool {
*self == Ceref1::Ceref1_16
}
#[doc = "Comp. E Int. Ref.1 Select 1 : 18/32"]
#[inline(always)]
pub fn is_ceref1_17(&self) -> bool {
*self == Ceref1::Ceref1_17
}
#[doc = "Comp. E Int. Ref.1 Select 2 : 19/32"]
#[inline(always)]
pub fn is_ceref1_18(&self) -> bool {
*self == Ceref1::Ceref1_18
}
#[doc = "Comp. E Int. Ref.1 Select 3 : 20/32"]
#[inline(always)]
pub fn is_ceref1_19(&self) -> bool {
*self == Ceref1::Ceref1_19
}
#[doc = "Comp. E Int. Ref.1 Select 4 : 21/32"]
#[inline(always)]
pub fn is_ceref1_20(&self) -> bool {
*self == Ceref1::Ceref1_20
}
#[doc = "Comp. E Int. Ref.1 Select 5 : 22/32"]
#[inline(always)]
pub fn is_ceref1_21(&self) -> bool {
*self == Ceref1::Ceref1_21
}
#[doc = "Comp. E Int. Ref.1 Select 6 : 23/32"]
#[inline(always)]
pub fn is_ceref1_22(&self) -> bool {
*self == Ceref1::Ceref1_22
}
#[doc = "Comp. E Int. Ref.1 Select 7 : 24/32"]
#[inline(always)]
pub fn is_ceref1_23(&self) -> bool {
*self == Ceref1::Ceref1_23
}
#[doc = "Comp. E Int. Ref.1 Select 0 : 25/32"]
#[inline(always)]
pub fn is_ceref1_24(&self) -> bool {
*self == Ceref1::Ceref1_24
}
#[doc = "Comp. E Int. Ref.1 Select 1 : 26/32"]
#[inline(always)]
pub fn is_ceref1_25(&self) -> bool {
*self == Ceref1::Ceref1_25
}
#[doc = "Comp. E Int. Ref.1 Select 2 : 27/32"]
#[inline(always)]
pub fn is_ceref1_26(&self) -> bool {
*self == Ceref1::Ceref1_26
}
#[doc = "Comp. E Int. Ref.1 Select 3 : 28/32"]
#[inline(always)]
pub fn is_ceref1_27(&self) -> bool {
*self == Ceref1::Ceref1_27
}
#[doc = "Comp. E Int. Ref.1 Select 4 : 29/32"]
#[inline(always)]
pub fn is_ceref1_28(&self) -> bool {
*self == Ceref1::Ceref1_28
}
#[doc = "Comp. E Int. Ref.1 Select 5 : 30/32"]
#[inline(always)]
pub fn is_ceref1_29(&self) -> bool {
*self == Ceref1::Ceref1_29
}
#[doc = "Comp. E Int. Ref.1 Select 6 : 31/32"]
#[inline(always)]
pub fn is_ceref1_30(&self) -> bool {
*self == Ceref1::Ceref1_30
}
#[doc = "Comp. E Int. Ref.1 Select 7 : 32/32"]
#[inline(always)]
pub fn is_ceref1_31(&self) -> bool {
*self == Ceref1::Ceref1_31
}
}
#[doc = "Field `CEREF1` writer - Comp. E Reference 1 Resistor Select Bit : 0"]
pub type Ceref1W<'a, REG> = crate::FieldWriter<'a, REG, 5, Ceref1, crate::Safe>;
impl<'a, REG> Ceref1W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Comp. E Int. Ref.1 Select 0 : 1/32"]
#[inline(always)]
pub fn ceref1_0(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_0)
}
#[doc = "Comp. E Int. Ref.1 Select 1 : 2/32"]
#[inline(always)]
pub fn ceref1_1(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_1)
}
#[doc = "Comp. E Int. Ref.1 Select 2 : 3/32"]
#[inline(always)]
pub fn ceref1_2(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_2)
}
#[doc = "Comp. E Int. Ref.1 Select 3 : 4/32"]
#[inline(always)]
pub fn ceref1_3(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_3)
}
#[doc = "Comp. E Int. Ref.1 Select 4 : 5/32"]
#[inline(always)]
pub fn ceref1_4(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_4)
}
#[doc = "Comp. E Int. Ref.1 Select 5 : 6/32"]
#[inline(always)]
pub fn ceref1_5(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_5)
}
#[doc = "Comp. E Int. Ref.1 Select 6 : 7/32"]
#[inline(always)]
pub fn ceref1_6(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_6)
}
#[doc = "Comp. E Int. Ref.1 Select 7 : 8/32"]
#[inline(always)]
pub fn ceref1_7(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_7)
}
#[doc = "Comp. E Int. Ref.1 Select 0 : 9/32"]
#[inline(always)]
pub fn ceref1_8(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_8)
}
#[doc = "Comp. E Int. Ref.1 Select 1 : 10/32"]
#[inline(always)]
pub fn ceref1_9(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_9)
}
#[doc = "Comp. E Int. Ref.1 Select 2 : 11/32"]
#[inline(always)]
pub fn ceref1_10(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_10)
}
#[doc = "Comp. E Int. Ref.1 Select 3 : 12/32"]
#[inline(always)]
pub fn ceref1_11(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_11)
}
#[doc = "Comp. E Int. Ref.1 Select 4 : 13/32"]
#[inline(always)]
pub fn ceref1_12(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_12)
}
#[doc = "Comp. E Int. Ref.1 Select 5 : 14/32"]
#[inline(always)]
pub fn ceref1_13(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_13)
}
#[doc = "Comp. E Int. Ref.1 Select 6 : 15/32"]
#[inline(always)]
pub fn ceref1_14(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_14)
}
#[doc = "Comp. E Int. Ref.1 Select 7 : 16/32"]
#[inline(always)]
pub fn ceref1_15(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_15)
}
#[doc = "Comp. E Int. Ref.1 Select 0 : 17/32"]
#[inline(always)]
pub fn ceref1_16(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_16)
}
#[doc = "Comp. E Int. Ref.1 Select 1 : 18/32"]
#[inline(always)]
pub fn ceref1_17(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_17)
}
#[doc = "Comp. E Int. Ref.1 Select 2 : 19/32"]
#[inline(always)]
pub fn ceref1_18(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_18)
}
#[doc = "Comp. E Int. Ref.1 Select 3 : 20/32"]
#[inline(always)]
pub fn ceref1_19(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_19)
}
#[doc = "Comp. E Int. Ref.1 Select 4 : 21/32"]
#[inline(always)]
pub fn ceref1_20(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_20)
}
#[doc = "Comp. E Int. Ref.1 Select 5 : 22/32"]
#[inline(always)]
pub fn ceref1_21(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_21)
}
#[doc = "Comp. E Int. Ref.1 Select 6 : 23/32"]
#[inline(always)]
pub fn ceref1_22(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_22)
}
#[doc = "Comp. E Int. Ref.1 Select 7 : 24/32"]
#[inline(always)]
pub fn ceref1_23(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_23)
}
#[doc = "Comp. E Int. Ref.1 Select 0 : 25/32"]
#[inline(always)]
pub fn ceref1_24(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_24)
}
#[doc = "Comp. E Int. Ref.1 Select 1 : 26/32"]
#[inline(always)]
pub fn ceref1_25(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_25)
}
#[doc = "Comp. E Int. Ref.1 Select 2 : 27/32"]
#[inline(always)]
pub fn ceref1_26(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_26)
}
#[doc = "Comp. E Int. Ref.1 Select 3 : 28/32"]
#[inline(always)]
pub fn ceref1_27(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_27)
}
#[doc = "Comp. E Int. Ref.1 Select 4 : 29/32"]
#[inline(always)]
pub fn ceref1_28(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_28)
}
#[doc = "Comp. E Int. Ref.1 Select 5 : 30/32"]
#[inline(always)]
pub fn ceref1_29(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_29)
}
#[doc = "Comp. E Int. Ref.1 Select 6 : 31/32"]
#[inline(always)]
pub fn ceref1_30(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_30)
}
#[doc = "Comp. E Int. Ref.1 Select 7 : 32/32"]
#[inline(always)]
pub fn ceref1_31(self) -> &'a mut crate::W<REG> {
self.variant(Ceref1::Ceref1_31)
}
}
#[doc = "Comp. E Reference voltage level Bit : 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cerefl {
#[doc = "0: Comp. E Reference voltage level 0 : None"]
Cerefl0 = 0,
#[doc = "1: Comp. E Reference voltage level 1 : 1.2V"]
Cerefl1 = 1,
#[doc = "2: Comp. E Reference voltage level 2 : 2.0V"]
Cerefl2 = 2,
#[doc = "3: Comp. E Reference voltage level 3 : 2.5V"]
Cerefl3 = 3,
}
impl From<Cerefl> for u8 {
#[inline(always)]
fn from(variant: Cerefl) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cerefl {
type Ux = u8;
}
impl crate::IsEnum for Cerefl {}
#[doc = "Field `CEREFL` reader - Comp. E Reference voltage level Bit : 0"]
pub type CereflR = crate::FieldReader<Cerefl>;
impl CereflR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cerefl {
match self.bits {
0 => Cerefl::Cerefl0,
1 => Cerefl::Cerefl1,
2 => Cerefl::Cerefl2,
3 => Cerefl::Cerefl3,
_ => unreachable!(),
}
}
#[doc = "Comp. E Reference voltage level 0 : None"]
#[inline(always)]
pub fn is_cerefl_0(&self) -> bool {
*self == Cerefl::Cerefl0
}
#[doc = "Comp. E Reference voltage level 1 : 1.2V"]
#[inline(always)]
pub fn is_cerefl_1(&self) -> bool {
*self == Cerefl::Cerefl1
}
#[doc = "Comp. E Reference voltage level 2 : 2.0V"]
#[inline(always)]
pub fn is_cerefl_2(&self) -> bool {
*self == Cerefl::Cerefl2
}
#[doc = "Comp. E Reference voltage level 3 : 2.5V"]
#[inline(always)]
pub fn is_cerefl_3(&self) -> bool {
*self == Cerefl::Cerefl3
}
}
#[doc = "Field `CEREFL` writer - Comp. E Reference voltage level Bit : 0"]
pub type CereflW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cerefl, crate::Safe>;
impl<'a, REG> CereflW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Comp. E Reference voltage level 0 : None"]
#[inline(always)]
pub fn cerefl_0(self) -> &'a mut crate::W<REG> {
self.variant(Cerefl::Cerefl0)
}
#[doc = "Comp. E Reference voltage level 1 : 1.2V"]
#[inline(always)]
pub fn cerefl_1(self) -> &'a mut crate::W<REG> {
self.variant(Cerefl::Cerefl1)
}
#[doc = "Comp. E Reference voltage level 2 : 2.0V"]
#[inline(always)]
pub fn cerefl_2(self) -> &'a mut crate::W<REG> {
self.variant(Cerefl::Cerefl2)
}
#[doc = "Comp. E Reference voltage level 3 : 2.5V"]
#[inline(always)]
pub fn cerefl_3(self) -> &'a mut crate::W<REG> {
self.variant(Cerefl::Cerefl3)
}
}
#[doc = "Field `CEREFACC` reader - Comp. E Reference Accuracy"]
pub type CerefaccR = crate::BitReader;
#[doc = "Field `CEREFACC` writer - Comp. E Reference Accuracy"]
pub type CerefaccW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:4 - Comp. E Reference 0 Resistor Select Bit : 0"]
#[inline(always)]
pub fn ceref0(&self) -> Ceref0R {
Ceref0R::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 5 - Comp. E Reference select"]
#[inline(always)]
pub fn cersel(&self) -> CerselR {
CerselR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:7 - Comp. E Reference Source Bit : 0"]
#[inline(always)]
pub fn cers(&self) -> CersR {
CersR::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:12 - Comp. E Reference 1 Resistor Select Bit : 0"]
#[inline(always)]
pub fn ceref1(&self) -> Ceref1R {
Ceref1R::new(((self.bits >> 8) & 0x1f) as u8)
}
#[doc = "Bits 13:14 - Comp. E Reference voltage level Bit : 0"]
#[inline(always)]
pub fn cerefl(&self) -> CereflR {
CereflR::new(((self.bits >> 13) & 3) as u8)
}
#[doc = "Bit 15 - Comp. E Reference Accuracy"]
#[inline(always)]
pub fn cerefacc(&self) -> CerefaccR {
CerefaccR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - Comp. E Reference 0 Resistor Select Bit : 0"]
#[inline(always)]
pub fn ceref0(&mut self) -> Ceref0W<'_, Cectl2Spec> {
Ceref0W::new(self, 0)
}
#[doc = "Bit 5 - Comp. E Reference select"]
#[inline(always)]
pub fn cersel(&mut self) -> CerselW<'_, Cectl2Spec> {
CerselW::new(self, 5)
}
#[doc = "Bits 6:7 - Comp. E Reference Source Bit : 0"]
#[inline(always)]
pub fn cers(&mut self) -> CersW<'_, Cectl2Spec> {
CersW::new(self, 6)
}
#[doc = "Bits 8:12 - Comp. E Reference 1 Resistor Select Bit : 0"]
#[inline(always)]
pub fn ceref1(&mut self) -> Ceref1W<'_, Cectl2Spec> {
Ceref1W::new(self, 8)
}
#[doc = "Bits 13:14 - Comp. E Reference voltage level Bit : 0"]
#[inline(always)]
pub fn cerefl(&mut self) -> CereflW<'_, Cectl2Spec> {
CereflW::new(self, 13)
}
#[doc = "Bit 15 - Comp. E Reference Accuracy"]
#[inline(always)]
pub fn cerefacc(&mut self) -> CerefaccW<'_, Cectl2Spec> {
CerefaccW::new(self, 15)
}
}
#[doc = "Comparator E Control Register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`cectl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cectl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cectl2Spec;
impl crate::RegisterSpec for Cectl2Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`cectl2::R`](R) reader structure"]
impl crate::Readable for Cectl2Spec {}
#[doc = "`write(|w| ..)` method takes [`cectl2::W`](W) writer structure"]
impl crate::Writable for Cectl2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CECTL2 to value 0"]
impl crate::Resettable for Cectl2Spec {}
}
#[doc = "CECTL3 (rw) register accessor: Comparator E Control Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`cectl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cectl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cectl3`] module"]
#[doc(alias = "CECTL3")]
pub type Cectl3 = crate::Reg<cectl3::Cectl3Spec>;
#[doc = "Comparator E Control Register 3"]
pub mod cectl3 {
#[doc = "Register `CECTL3` reader"]
pub type R = crate::R<Cectl3Spec>;
#[doc = "Register `CECTL3` writer"]
pub type W = crate::W<Cectl3Spec>;
#[doc = "Field `CEPD0` reader - Comp. E Disable Input Buffer of Port Register .0"]
pub type Cepd0R = crate::BitReader;
#[doc = "Field `CEPD0` writer - Comp. E Disable Input Buffer of Port Register .0"]
pub type Cepd0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEPD1` reader - Comp. E Disable Input Buffer of Port Register .1"]
pub type Cepd1R = crate::BitReader;
#[doc = "Field `CEPD1` writer - Comp. E Disable Input Buffer of Port Register .1"]
pub type Cepd1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEPD2` reader - Comp. E Disable Input Buffer of Port Register .2"]
pub type Cepd2R = crate::BitReader;
#[doc = "Field `CEPD2` writer - Comp. E Disable Input Buffer of Port Register .2"]
pub type Cepd2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEPD3` reader - Comp. E Disable Input Buffer of Port Register .3"]
pub type Cepd3R = crate::BitReader;
#[doc = "Field `CEPD3` writer - Comp. E Disable Input Buffer of Port Register .3"]
pub type Cepd3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEPD4` reader - Comp. E Disable Input Buffer of Port Register .4"]
pub type Cepd4R = crate::BitReader;
#[doc = "Field `CEPD4` writer - Comp. E Disable Input Buffer of Port Register .4"]
pub type Cepd4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEPD5` reader - Comp. E Disable Input Buffer of Port Register .5"]
pub type Cepd5R = crate::BitReader;
#[doc = "Field `CEPD5` writer - Comp. E Disable Input Buffer of Port Register .5"]
pub type Cepd5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEPD6` reader - Comp. E Disable Input Buffer of Port Register .6"]
pub type Cepd6R = crate::BitReader;
#[doc = "Field `CEPD6` writer - Comp. E Disable Input Buffer of Port Register .6"]
pub type Cepd6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEPD7` reader - Comp. E Disable Input Buffer of Port Register .7"]
pub type Cepd7R = crate::BitReader;
#[doc = "Field `CEPD7` writer - Comp. E Disable Input Buffer of Port Register .7"]
pub type Cepd7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEPD8` reader - Comp. E Disable Input Buffer of Port Register .8"]
pub type Cepd8R = crate::BitReader;
#[doc = "Field `CEPD8` writer - Comp. E Disable Input Buffer of Port Register .8"]
pub type Cepd8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEPD9` reader - Comp. E Disable Input Buffer of Port Register .9"]
pub type Cepd9R = crate::BitReader;
#[doc = "Field `CEPD9` writer - Comp. E Disable Input Buffer of Port Register .9"]
pub type Cepd9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEPD10` reader - Comp. E Disable Input Buffer of Port Register .10"]
pub type Cepd10R = crate::BitReader;
#[doc = "Field `CEPD10` writer - Comp. E Disable Input Buffer of Port Register .10"]
pub type Cepd10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEPD11` reader - Comp. E Disable Input Buffer of Port Register .11"]
pub type Cepd11R = crate::BitReader;
#[doc = "Field `CEPD11` writer - Comp. E Disable Input Buffer of Port Register .11"]
pub type Cepd11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEPD12` reader - Comp. E Disable Input Buffer of Port Register .12"]
pub type Cepd12R = crate::BitReader;
#[doc = "Field `CEPD12` writer - Comp. E Disable Input Buffer of Port Register .12"]
pub type Cepd12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEPD13` reader - Comp. E Disable Input Buffer of Port Register .13"]
pub type Cepd13R = crate::BitReader;
#[doc = "Field `CEPD13` writer - Comp. E Disable Input Buffer of Port Register .13"]
pub type Cepd13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEPD14` reader - Comp. E Disable Input Buffer of Port Register .14"]
pub type Cepd14R = crate::BitReader;
#[doc = "Field `CEPD14` writer - Comp. E Disable Input Buffer of Port Register .14"]
pub type Cepd14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEPD15` reader - Comp. E Disable Input Buffer of Port Register .15"]
pub type Cepd15R = crate::BitReader;
#[doc = "Field `CEPD15` writer - Comp. E Disable Input Buffer of Port Register .15"]
pub type Cepd15W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Comp. E Disable Input Buffer of Port Register .0"]
#[inline(always)]
pub fn cepd0(&self) -> Cepd0R {
Cepd0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Comp. E Disable Input Buffer of Port Register .1"]
#[inline(always)]
pub fn cepd1(&self) -> Cepd1R {
Cepd1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Comp. E Disable Input Buffer of Port Register .2"]
#[inline(always)]
pub fn cepd2(&self) -> Cepd2R {
Cepd2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Comp. E Disable Input Buffer of Port Register .3"]
#[inline(always)]
pub fn cepd3(&self) -> Cepd3R {
Cepd3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Comp. E Disable Input Buffer of Port Register .4"]
#[inline(always)]
pub fn cepd4(&self) -> Cepd4R {
Cepd4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Comp. E Disable Input Buffer of Port Register .5"]
#[inline(always)]
pub fn cepd5(&self) -> Cepd5R {
Cepd5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Comp. E Disable Input Buffer of Port Register .6"]
#[inline(always)]
pub fn cepd6(&self) -> Cepd6R {
Cepd6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Comp. E Disable Input Buffer of Port Register .7"]
#[inline(always)]
pub fn cepd7(&self) -> Cepd7R {
Cepd7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Comp. E Disable Input Buffer of Port Register .8"]
#[inline(always)]
pub fn cepd8(&self) -> Cepd8R {
Cepd8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Comp. E Disable Input Buffer of Port Register .9"]
#[inline(always)]
pub fn cepd9(&self) -> Cepd9R {
Cepd9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Comp. E Disable Input Buffer of Port Register .10"]
#[inline(always)]
pub fn cepd10(&self) -> Cepd10R {
Cepd10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Comp. E Disable Input Buffer of Port Register .11"]
#[inline(always)]
pub fn cepd11(&self) -> Cepd11R {
Cepd11R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Comp. E Disable Input Buffer of Port Register .12"]
#[inline(always)]
pub fn cepd12(&self) -> Cepd12R {
Cepd12R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Comp. E Disable Input Buffer of Port Register .13"]
#[inline(always)]
pub fn cepd13(&self) -> Cepd13R {
Cepd13R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Comp. E Disable Input Buffer of Port Register .14"]
#[inline(always)]
pub fn cepd14(&self) -> Cepd14R {
Cepd14R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Comp. E Disable Input Buffer of Port Register .15"]
#[inline(always)]
pub fn cepd15(&self) -> Cepd15R {
Cepd15R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Comp. E Disable Input Buffer of Port Register .0"]
#[inline(always)]
pub fn cepd0(&mut self) -> Cepd0W<'_, Cectl3Spec> {
Cepd0W::new(self, 0)
}
#[doc = "Bit 1 - Comp. E Disable Input Buffer of Port Register .1"]
#[inline(always)]
pub fn cepd1(&mut self) -> Cepd1W<'_, Cectl3Spec> {
Cepd1W::new(self, 1)
}
#[doc = "Bit 2 - Comp. E Disable Input Buffer of Port Register .2"]
#[inline(always)]
pub fn cepd2(&mut self) -> Cepd2W<'_, Cectl3Spec> {
Cepd2W::new(self, 2)
}
#[doc = "Bit 3 - Comp. E Disable Input Buffer of Port Register .3"]
#[inline(always)]
pub fn cepd3(&mut self) -> Cepd3W<'_, Cectl3Spec> {
Cepd3W::new(self, 3)
}
#[doc = "Bit 4 - Comp. E Disable Input Buffer of Port Register .4"]
#[inline(always)]
pub fn cepd4(&mut self) -> Cepd4W<'_, Cectl3Spec> {
Cepd4W::new(self, 4)
}
#[doc = "Bit 5 - Comp. E Disable Input Buffer of Port Register .5"]
#[inline(always)]
pub fn cepd5(&mut self) -> Cepd5W<'_, Cectl3Spec> {
Cepd5W::new(self, 5)
}
#[doc = "Bit 6 - Comp. E Disable Input Buffer of Port Register .6"]
#[inline(always)]
pub fn cepd6(&mut self) -> Cepd6W<'_, Cectl3Spec> {
Cepd6W::new(self, 6)
}
#[doc = "Bit 7 - Comp. E Disable Input Buffer of Port Register .7"]
#[inline(always)]
pub fn cepd7(&mut self) -> Cepd7W<'_, Cectl3Spec> {
Cepd7W::new(self, 7)
}
#[doc = "Bit 8 - Comp. E Disable Input Buffer of Port Register .8"]
#[inline(always)]
pub fn cepd8(&mut self) -> Cepd8W<'_, Cectl3Spec> {
Cepd8W::new(self, 8)
}
#[doc = "Bit 9 - Comp. E Disable Input Buffer of Port Register .9"]
#[inline(always)]
pub fn cepd9(&mut self) -> Cepd9W<'_, Cectl3Spec> {
Cepd9W::new(self, 9)
}
#[doc = "Bit 10 - Comp. E Disable Input Buffer of Port Register .10"]
#[inline(always)]
pub fn cepd10(&mut self) -> Cepd10W<'_, Cectl3Spec> {
Cepd10W::new(self, 10)
}
#[doc = "Bit 11 - Comp. E Disable Input Buffer of Port Register .11"]
#[inline(always)]
pub fn cepd11(&mut self) -> Cepd11W<'_, Cectl3Spec> {
Cepd11W::new(self, 11)
}
#[doc = "Bit 12 - Comp. E Disable Input Buffer of Port Register .12"]
#[inline(always)]
pub fn cepd12(&mut self) -> Cepd12W<'_, Cectl3Spec> {
Cepd12W::new(self, 12)
}
#[doc = "Bit 13 - Comp. E Disable Input Buffer of Port Register .13"]
#[inline(always)]
pub fn cepd13(&mut self) -> Cepd13W<'_, Cectl3Spec> {
Cepd13W::new(self, 13)
}
#[doc = "Bit 14 - Comp. E Disable Input Buffer of Port Register .14"]
#[inline(always)]
pub fn cepd14(&mut self) -> Cepd14W<'_, Cectl3Spec> {
Cepd14W::new(self, 14)
}
#[doc = "Bit 15 - Comp. E Disable Input Buffer of Port Register .15"]
#[inline(always)]
pub fn cepd15(&mut self) -> Cepd15W<'_, Cectl3Spec> {
Cepd15W::new(self, 15)
}
}
#[doc = "Comparator E Control Register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`cectl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cectl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cectl3Spec;
impl crate::RegisterSpec for Cectl3Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`cectl3::R`](R) reader structure"]
impl crate::Readable for Cectl3Spec {}
#[doc = "`write(|w| ..)` method takes [`cectl3::W`](W) writer structure"]
impl crate::Writable for Cectl3Spec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets CECTL3 to value 0"]
impl crate::Resettable for Cectl3Spec {}
}
#[doc = "CEINT (rw) register accessor: Comparator E Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ceint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ceint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ceint`] module"]
#[doc(alias = "CEINT")]
pub type Ceint = crate::Reg<ceint::CeintSpec>;
#[doc = "Comparator E Interrupt Register"]
pub mod ceint {
#[doc = "Register `CEINT` reader"]
pub type R = crate::R<CeintSpec>;
#[doc = "Register `CEINT` writer"]
pub type W = crate::W<CeintSpec>;
#[doc = "Field `CEIFG` reader - Comp. E Interrupt Flag"]
pub type CeifgR = crate::BitReader;
#[doc = "Field `CEIFG` writer - Comp. E Interrupt Flag"]
pub type CeifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEIIFG` reader - Comp. E Interrupt Flag Inverted Polarity"]
pub type CeiifgR = crate::BitReader;
#[doc = "Field `CEIIFG` writer - Comp. E Interrupt Flag Inverted Polarity"]
pub type CeiifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CERDYIFG` reader - Comp. E Comparator_E ready interrupt flag"]
pub type CerdyifgR = crate::BitReader;
#[doc = "Field `CERDYIFG` writer - Comp. E Comparator_E ready interrupt flag"]
pub type CerdyifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEIE` reader - Comp. E Interrupt Enable"]
pub type CeieR = crate::BitReader;
#[doc = "Field `CEIE` writer - Comp. E Interrupt Enable"]
pub type CeieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CEIIE` reader - Comp. E Interrupt Enable Inverted Polarity"]
pub type CeiieR = crate::BitReader;
#[doc = "Field `CEIIE` writer - Comp. E Interrupt Enable Inverted Polarity"]
pub type CeiieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CERDYIE` reader - Comp. E Comparator_E ready interrupt enable"]
pub type CerdyieR = crate::BitReader;
#[doc = "Field `CERDYIE` writer - Comp. E Comparator_E ready interrupt enable"]
pub type CerdyieW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Comp. E Interrupt Flag"]
#[inline(always)]
pub fn ceifg(&self) -> CeifgR {
CeifgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Comp. E Interrupt Flag Inverted Polarity"]
#[inline(always)]
pub fn ceiifg(&self) -> CeiifgR {
CeiifgR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 4 - Comp. E Comparator_E ready interrupt flag"]
#[inline(always)]
pub fn cerdyifg(&self) -> CerdyifgR {
CerdyifgR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 8 - Comp. E Interrupt Enable"]
#[inline(always)]
pub fn ceie(&self) -> CeieR {
CeieR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Comp. E Interrupt Enable Inverted Polarity"]
#[inline(always)]
pub fn ceiie(&self) -> CeiieR {
CeiieR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 12 - Comp. E Comparator_E ready interrupt enable"]
#[inline(always)]
pub fn cerdyie(&self) -> CerdyieR {
CerdyieR::new(((self.bits >> 12) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Comp. E Interrupt Flag"]
#[inline(always)]
pub fn ceifg(&mut self) -> CeifgW<'_, CeintSpec> {
CeifgW::new(self, 0)
}
#[doc = "Bit 1 - Comp. E Interrupt Flag Inverted Polarity"]
#[inline(always)]
pub fn ceiifg(&mut self) -> CeiifgW<'_, CeintSpec> {
CeiifgW::new(self, 1)
}
#[doc = "Bit 4 - Comp. E Comparator_E ready interrupt flag"]
#[inline(always)]
pub fn cerdyifg(&mut self) -> CerdyifgW<'_, CeintSpec> {
CerdyifgW::new(self, 4)
}
#[doc = "Bit 8 - Comp. E Interrupt Enable"]
#[inline(always)]
pub fn ceie(&mut self) -> CeieW<'_, CeintSpec> {
CeieW::new(self, 8)
}
#[doc = "Bit 9 - Comp. E Interrupt Enable Inverted Polarity"]
#[inline(always)]
pub fn ceiie(&mut self) -> CeiieW<'_, CeintSpec> {
CeiieW::new(self, 9)
}
#[doc = "Bit 12 - Comp. E Comparator_E ready interrupt enable"]
#[inline(always)]
pub fn cerdyie(&mut self) -> CerdyieW<'_, CeintSpec> {
CerdyieW::new(self, 12)
}
}
#[doc = "Comparator E Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ceint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ceint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CeintSpec;
impl crate::RegisterSpec for CeintSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ceint::R`](R) reader structure"]
impl crate::Readable for CeintSpec {}
#[doc = "`write(|w| ..)` method takes [`ceint::W`](W) writer structure"]
impl crate::Writable for CeintSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CEINT to value 0"]
impl crate::Resettable for CeintSpec {}
}
#[doc = "CEIV (rw) register accessor: Comparator E Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`ceiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ceiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ceiv`] module"]
#[doc(alias = "CEIV")]
pub type Ceiv = crate::Reg<ceiv::CeivSpec>;
#[doc = "Comparator E Interrupt Vector Word"]
pub mod ceiv {
#[doc = "Register `CEIV` reader"]
pub type R = crate::R<CeivSpec>;
#[doc = "Register `CEIV` writer"]
pub type W = crate::W<CeivSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "Comparator E Interrupt Vector Word\n\nYou can [`read`](crate::Reg::read) this register and get [`ceiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ceiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CeivSpec;
impl crate::RegisterSpec for CeivSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`ceiv::R`](R) reader structure"]
impl crate::Readable for CeivSpec {}
#[doc = "`write(|w| ..)` method takes [`ceiv::W`](W) writer structure"]
impl crate::Writable for CeivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CEIV to value 0"]
impl crate::Resettable for CeivSpec {}
}
}
#[doc = "AES Accelerator"]
pub type AesAccelerator = crate::Periph<aes_accelerator::RegisterBlock, 0x09c0>;
impl core::fmt::Debug for AesAccelerator {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("AesAccelerator").finish()
}
}
#[doc = "AES Accelerator"]
pub mod aes_accelerator {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
aesactl0: Aesactl0,
aesactl1: Aesactl1,
aesastat: Aesastat,
aesakey: Aesakey,
aesadin: Aesadin,
aesadout: Aesadout,
aesaxdin: Aesaxdin,
aesaxin: Aesaxin,
}
impl RegisterBlock {
#[doc = "0x00 - AES accelerator control register 0"]
#[inline(always)]
pub const fn aesactl0(&self) -> &Aesactl0 {
&self.aesactl0
}
#[doc = "0x02 - AES accelerator control register 1"]
#[inline(always)]
pub const fn aesactl1(&self) -> &Aesactl1 {
&self.aesactl1
}
#[doc = "0x04 - AES accelerator status register"]
#[inline(always)]
pub const fn aesastat(&self) -> &Aesastat {
&self.aesastat
}
#[doc = "0x06 - AES accelerator key register"]
#[inline(always)]
pub const fn aesakey(&self) -> &Aesakey {
&self.aesakey
}
#[doc = "0x08 - AES accelerator data in register"]
#[inline(always)]
pub const fn aesadin(&self) -> &Aesadin {
&self.aesadin
}
#[doc = "0x0a - AES accelerator data out register"]
#[inline(always)]
pub const fn aesadout(&self) -> &Aesadout {
&self.aesadout
}
#[doc = "0x0c - AES accelerator XORed data in register"]
#[inline(always)]
pub const fn aesaxdin(&self) -> &Aesaxdin {
&self.aesaxdin
}
#[doc = "0x0e - AES accelerator XORed data in register (no trigger)"]
#[inline(always)]
pub const fn aesaxin(&self) -> &Aesaxin {
&self.aesaxin
}
}
#[doc = "AESACTL0 (rw) register accessor: AES accelerator control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`aesactl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aesactl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aesactl0`] module"]
#[doc(alias = "AESACTL0")]
pub type Aesactl0 = crate::Reg<aesactl0::Aesactl0Spec>;
#[doc = "AES accelerator control register 0"]
pub mod aesactl0 {
#[doc = "Register `AESACTL0` reader"]
pub type R = crate::R<Aesactl0Spec>;
#[doc = "Register `AESACTL0` writer"]
pub type W = crate::W<Aesactl0Spec>;
#[doc = "AES Operation Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Aesop {
#[doc = "0: AES Operation: Encrypt"]
Aesop0 = 0,
#[doc = "1: AES Operation: Decrypt (same Key)"]
Aesop1 = 1,
#[doc = "2: AES Operation: Generate first round Key"]
Aesop2 = 2,
#[doc = "3: AES Operation: Decrypt (first round Key)"]
Aesop3 = 3,
}
impl From<Aesop> for u8 {
#[inline(always)]
fn from(variant: Aesop) -> Self {
variant as _
}
}
impl crate::FieldSpec for Aesop {
type Ux = u8;
}
impl crate::IsEnum for Aesop {}
#[doc = "Field `AESOP` reader - AES Operation Bit: 0"]
pub type AesopR = crate::FieldReader<Aesop>;
impl AesopR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Aesop {
match self.bits {
0 => Aesop::Aesop0,
1 => Aesop::Aesop1,
2 => Aesop::Aesop2,
3 => Aesop::Aesop3,
_ => unreachable!(),
}
}
#[doc = "AES Operation: Encrypt"]
#[inline(always)]
pub fn is_aesop_0(&self) -> bool {
*self == Aesop::Aesop0
}
#[doc = "AES Operation: Decrypt (same Key)"]
#[inline(always)]
pub fn is_aesop_1(&self) -> bool {
*self == Aesop::Aesop1
}
#[doc = "AES Operation: Generate first round Key"]
#[inline(always)]
pub fn is_aesop_2(&self) -> bool {
*self == Aesop::Aesop2
}
#[doc = "AES Operation: Decrypt (first round Key)"]
#[inline(always)]
pub fn is_aesop_3(&self) -> bool {
*self == Aesop::Aesop3
}
}
#[doc = "Field `AESOP` writer - AES Operation Bit: 0"]
pub type AesopW<'a, REG> = crate::FieldWriter<'a, REG, 2, Aesop, crate::Safe>;
impl<'a, REG> AesopW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "AES Operation: Encrypt"]
#[inline(always)]
pub fn aesop_0(self) -> &'a mut crate::W<REG> {
self.variant(Aesop::Aesop0)
}
#[doc = "AES Operation: Decrypt (same Key)"]
#[inline(always)]
pub fn aesop_1(self) -> &'a mut crate::W<REG> {
self.variant(Aesop::Aesop1)
}
#[doc = "AES Operation: Generate first round Key"]
#[inline(always)]
pub fn aesop_2(self) -> &'a mut crate::W<REG> {
self.variant(Aesop::Aesop2)
}
#[doc = "AES Operation: Decrypt (first round Key)"]
#[inline(always)]
pub fn aesop_3(self) -> &'a mut crate::W<REG> {
self.variant(Aesop::Aesop3)
}
}
#[doc = "AES Key length Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Aeskl {
#[doc = "0: AES Key length: AES128"]
Aeskl0 = 0,
#[doc = "1: AES Key length: AES192"]
Aeskl1 = 1,
#[doc = "2: AES Key length: AES256"]
Aeskl2 = 2,
}
impl From<Aeskl> for u8 {
#[inline(always)]
fn from(variant: Aeskl) -> Self {
variant as _
}
}
impl crate::FieldSpec for Aeskl {
type Ux = u8;
}
impl crate::IsEnum for Aeskl {}
#[doc = "Field `AESKL` reader - AES Key length Bit: 0"]
pub type AesklR = crate::FieldReader<Aeskl>;
impl AesklR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Aeskl> {
match self.bits {
0 => Some(Aeskl::Aeskl0),
1 => Some(Aeskl::Aeskl1),
2 => Some(Aeskl::Aeskl2),
_ => None,
}
}
#[doc = "AES Key length: AES128"]
#[inline(always)]
pub fn is_aeskl_0(&self) -> bool {
*self == Aeskl::Aeskl0
}
#[doc = "AES Key length: AES192"]
#[inline(always)]
pub fn is_aeskl_1(&self) -> bool {
*self == Aeskl::Aeskl1
}
#[doc = "AES Key length: AES256"]
#[inline(always)]
pub fn is_aeskl_2(&self) -> bool {
*self == Aeskl::Aeskl2
}
}
#[doc = "Field `AESKL` writer - AES Key length Bit: 0"]
pub type AesklW<'a, REG> = crate::FieldWriter<'a, REG, 2, Aeskl>;
impl<'a, REG> AesklW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "AES Key length: AES128"]
#[inline(always)]
pub fn aeskl_0(self) -> &'a mut crate::W<REG> {
self.variant(Aeskl::Aeskl0)
}
#[doc = "AES Key length: AES192"]
#[inline(always)]
pub fn aeskl_1(self) -> &'a mut crate::W<REG> {
self.variant(Aeskl::Aeskl1)
}
#[doc = "AES Key length: AES256"]
#[inline(always)]
pub fn aeskl_2(self) -> &'a mut crate::W<REG> {
self.variant(Aeskl::Aeskl2)
}
}
#[doc = "Field `AESTRIG` reader - AES Trigger Select"]
pub type AestrigR = crate::BitReader;
#[doc = "Field `AESTRIG` writer - AES Trigger Select"]
pub type AestrigW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "AES Cipher mode select Bit: 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Aescm {
#[doc = "0: AES Cipher mode select: ECB"]
Aescm0 = 0,
#[doc = "1: AES Cipher mode select: CBC"]
Aescm1 = 1,
#[doc = "2: AES Cipher mode select: OFB"]
Aescm2 = 2,
#[doc = "3: AES Cipher mode select: CFB"]
Aescm3 = 3,
}
impl From<Aescm> for u8 {
#[inline(always)]
fn from(variant: Aescm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Aescm {
type Ux = u8;
}
impl crate::IsEnum for Aescm {}
#[doc = "Field `AESCM` reader - AES Cipher mode select Bit: 0"]
pub type AescmR = crate::FieldReader<Aescm>;
impl AescmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Aescm {
match self.bits {
0 => Aescm::Aescm0,
1 => Aescm::Aescm1,
2 => Aescm::Aescm2,
3 => Aescm::Aescm3,
_ => unreachable!(),
}
}
#[doc = "AES Cipher mode select: ECB"]
#[inline(always)]
pub fn is_aescm_0(&self) -> bool {
*self == Aescm::Aescm0
}
#[doc = "AES Cipher mode select: CBC"]
#[inline(always)]
pub fn is_aescm_1(&self) -> bool {
*self == Aescm::Aescm1
}
#[doc = "AES Cipher mode select: OFB"]
#[inline(always)]
pub fn is_aescm_2(&self) -> bool {
*self == Aescm::Aescm2
}
#[doc = "AES Cipher mode select: CFB"]
#[inline(always)]
pub fn is_aescm_3(&self) -> bool {
*self == Aescm::Aescm3
}
}
#[doc = "Field `AESCM` writer - AES Cipher mode select Bit: 0"]
pub type AescmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Aescm, crate::Safe>;
impl<'a, REG> AescmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "AES Cipher mode select: ECB"]
#[inline(always)]
pub fn aescm_0(self) -> &'a mut crate::W<REG> {
self.variant(Aescm::Aescm0)
}
#[doc = "AES Cipher mode select: CBC"]
#[inline(always)]
pub fn aescm_1(self) -> &'a mut crate::W<REG> {
self.variant(Aescm::Aescm1)
}
#[doc = "AES Cipher mode select: OFB"]
#[inline(always)]
pub fn aescm_2(self) -> &'a mut crate::W<REG> {
self.variant(Aescm::Aescm2)
}
#[doc = "AES Cipher mode select: CFB"]
#[inline(always)]
pub fn aescm_3(self) -> &'a mut crate::W<REG> {
self.variant(Aescm::Aescm3)
}
}
#[doc = "Field `AESSWRST` reader - AES Software Reset"]
pub type AesswrstR = crate::BitReader;
#[doc = "Field `AESSWRST` writer - AES Software Reset"]
pub type AesswrstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESRDYIFG` reader - AES ready interrupt flag"]
pub type AesrdyifgR = crate::BitReader;
#[doc = "Field `AESRDYIFG` writer - AES ready interrupt flag"]
pub type AesrdyifgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESERRFG` reader - AES Error Flag"]
pub type AeserrfgR = crate::BitReader;
#[doc = "Field `AESERRFG` writer - AES Error Flag"]
pub type AeserrfgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESRDYIE` reader - AES ready interrupt enable"]
pub type AesrdyieR = crate::BitReader;
#[doc = "Field `AESRDYIE` writer - AES ready interrupt enable"]
pub type AesrdyieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESCMEN` reader - AES DMA cipher mode enable"]
pub type AescmenR = crate::BitReader;
#[doc = "Field `AESCMEN` writer - AES DMA cipher mode enable"]
pub type AescmenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - AES Operation Bit: 0"]
#[inline(always)]
pub fn aesop(&self) -> AesopR {
AesopR::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3 - AES Key length Bit: 0"]
#[inline(always)]
pub fn aeskl(&self) -> AesklR {
AesklR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bit 4 - AES Trigger Select"]
#[inline(always)]
pub fn aestrig(&self) -> AestrigR {
AestrigR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6 - AES Cipher mode select Bit: 0"]
#[inline(always)]
pub fn aescm(&self) -> AescmR {
AescmR::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7 - AES Software Reset"]
#[inline(always)]
pub fn aesswrst(&self) -> AesswrstR {
AesswrstR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - AES ready interrupt flag"]
#[inline(always)]
pub fn aesrdyifg(&self) -> AesrdyifgR {
AesrdyifgR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 11 - AES Error Flag"]
#[inline(always)]
pub fn aeserrfg(&self) -> AeserrfgR {
AeserrfgR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - AES ready interrupt enable"]
#[inline(always)]
pub fn aesrdyie(&self) -> AesrdyieR {
AesrdyieR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 15 - AES DMA cipher mode enable"]
#[inline(always)]
pub fn aescmen(&self) -> AescmenR {
AescmenR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - AES Operation Bit: 0"]
#[inline(always)]
pub fn aesop(&mut self) -> AesopW<'_, Aesactl0Spec> {
AesopW::new(self, 0)
}
#[doc = "Bits 2:3 - AES Key length Bit: 0"]
#[inline(always)]
pub fn aeskl(&mut self) -> AesklW<'_, Aesactl0Spec> {
AesklW::new(self, 2)
}
#[doc = "Bit 4 - AES Trigger Select"]
#[inline(always)]
pub fn aestrig(&mut self) -> AestrigW<'_, Aesactl0Spec> {
AestrigW::new(self, 4)
}
#[doc = "Bits 5:6 - AES Cipher mode select Bit: 0"]
#[inline(always)]
pub fn aescm(&mut self) -> AescmW<'_, Aesactl0Spec> {
AescmW::new(self, 5)
}
#[doc = "Bit 7 - AES Software Reset"]
#[inline(always)]
pub fn aesswrst(&mut self) -> AesswrstW<'_, Aesactl0Spec> {
AesswrstW::new(self, 7)
}
#[doc = "Bit 8 - AES ready interrupt flag"]
#[inline(always)]
pub fn aesrdyifg(&mut self) -> AesrdyifgW<'_, Aesactl0Spec> {
AesrdyifgW::new(self, 8)
}
#[doc = "Bit 11 - AES Error Flag"]
#[inline(always)]
pub fn aeserrfg(&mut self) -> AeserrfgW<'_, Aesactl0Spec> {
AeserrfgW::new(self, 11)
}
#[doc = "Bit 12 - AES ready interrupt enable"]
#[inline(always)]
pub fn aesrdyie(&mut self) -> AesrdyieW<'_, Aesactl0Spec> {
AesrdyieW::new(self, 12)
}
#[doc = "Bit 15 - AES DMA cipher mode enable"]
#[inline(always)]
pub fn aescmen(&mut self) -> AescmenW<'_, Aesactl0Spec> {
AescmenW::new(self, 15)
}
}
#[doc = "AES accelerator control register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`aesactl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aesactl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Aesactl0Spec;
impl crate::RegisterSpec for Aesactl0Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`aesactl0::R`](R) reader structure"]
impl crate::Readable for Aesactl0Spec {}
#[doc = "`write(|w| ..)` method takes [`aesactl0::W`](W) writer structure"]
impl crate::Writable for Aesactl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets AESACTL0 to value 0"]
impl crate::Resettable for Aesactl0Spec {}
}
#[doc = "AESACTL1 (rw) register accessor: AES accelerator control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`aesactl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aesactl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aesactl1`] module"]
#[doc(alias = "AESACTL1")]
pub type Aesactl1 = crate::Reg<aesactl1::Aesactl1Spec>;
#[doc = "AES accelerator control register 1"]
pub mod aesactl1 {
#[doc = "Register `AESACTL1` reader"]
pub type R = crate::R<Aesactl1Spec>;
#[doc = "Register `AESACTL1` writer"]
pub type W = crate::W<Aesactl1Spec>;
#[doc = "Field `AESBLKCNT0` reader - AES Cipher Block Counter Bit: 0"]
pub type Aesblkcnt0R = crate::BitReader;
#[doc = "Field `AESBLKCNT0` writer - AES Cipher Block Counter Bit: 0"]
pub type Aesblkcnt0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESBLKCNT1` reader - AES Cipher Block Counter Bit: 1"]
pub type Aesblkcnt1R = crate::BitReader;
#[doc = "Field `AESBLKCNT1` writer - AES Cipher Block Counter Bit: 1"]
pub type Aesblkcnt1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESBLKCNT2` reader - AES Cipher Block Counter Bit: 2"]
pub type Aesblkcnt2R = crate::BitReader;
#[doc = "Field `AESBLKCNT2` writer - AES Cipher Block Counter Bit: 2"]
pub type Aesblkcnt2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESBLKCNT3` reader - AES Cipher Block Counter Bit: 3"]
pub type Aesblkcnt3R = crate::BitReader;
#[doc = "Field `AESBLKCNT3` writer - AES Cipher Block Counter Bit: 3"]
pub type Aesblkcnt3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESBLKCNT4` reader - AES Cipher Block Counter Bit: 4"]
pub type Aesblkcnt4R = crate::BitReader;
#[doc = "Field `AESBLKCNT4` writer - AES Cipher Block Counter Bit: 4"]
pub type Aesblkcnt4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESBLKCNT5` reader - AES Cipher Block Counter Bit: 5"]
pub type Aesblkcnt5R = crate::BitReader;
#[doc = "Field `AESBLKCNT5` writer - AES Cipher Block Counter Bit: 5"]
pub type Aesblkcnt5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESBLKCNT6` reader - AES Cipher Block Counter Bit: 6"]
pub type Aesblkcnt6R = crate::BitReader;
#[doc = "Field `AESBLKCNT6` writer - AES Cipher Block Counter Bit: 6"]
pub type Aesblkcnt6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESBLKCNT7` reader - AES Cipher Block Counter Bit: 7"]
pub type Aesblkcnt7R = crate::BitReader;
#[doc = "Field `AESBLKCNT7` writer - AES Cipher Block Counter Bit: 7"]
pub type Aesblkcnt7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - AES Cipher Block Counter Bit: 0"]
#[inline(always)]
pub fn aesblkcnt0(&self) -> Aesblkcnt0R {
Aesblkcnt0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - AES Cipher Block Counter Bit: 1"]
#[inline(always)]
pub fn aesblkcnt1(&self) -> Aesblkcnt1R {
Aesblkcnt1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - AES Cipher Block Counter Bit: 2"]
#[inline(always)]
pub fn aesblkcnt2(&self) -> Aesblkcnt2R {
Aesblkcnt2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - AES Cipher Block Counter Bit: 3"]
#[inline(always)]
pub fn aesblkcnt3(&self) -> Aesblkcnt3R {
Aesblkcnt3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - AES Cipher Block Counter Bit: 4"]
#[inline(always)]
pub fn aesblkcnt4(&self) -> Aesblkcnt4R {
Aesblkcnt4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - AES Cipher Block Counter Bit: 5"]
#[inline(always)]
pub fn aesblkcnt5(&self) -> Aesblkcnt5R {
Aesblkcnt5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - AES Cipher Block Counter Bit: 6"]
#[inline(always)]
pub fn aesblkcnt6(&self) -> Aesblkcnt6R {
Aesblkcnt6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - AES Cipher Block Counter Bit: 7"]
#[inline(always)]
pub fn aesblkcnt7(&self) -> Aesblkcnt7R {
Aesblkcnt7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - AES Cipher Block Counter Bit: 0"]
#[inline(always)]
pub fn aesblkcnt0(&mut self) -> Aesblkcnt0W<'_, Aesactl1Spec> {
Aesblkcnt0W::new(self, 0)
}
#[doc = "Bit 1 - AES Cipher Block Counter Bit: 1"]
#[inline(always)]
pub fn aesblkcnt1(&mut self) -> Aesblkcnt1W<'_, Aesactl1Spec> {
Aesblkcnt1W::new(self, 1)
}
#[doc = "Bit 2 - AES Cipher Block Counter Bit: 2"]
#[inline(always)]
pub fn aesblkcnt2(&mut self) -> Aesblkcnt2W<'_, Aesactl1Spec> {
Aesblkcnt2W::new(self, 2)
}
#[doc = "Bit 3 - AES Cipher Block Counter Bit: 3"]
#[inline(always)]
pub fn aesblkcnt3(&mut self) -> Aesblkcnt3W<'_, Aesactl1Spec> {
Aesblkcnt3W::new(self, 3)
}
#[doc = "Bit 4 - AES Cipher Block Counter Bit: 4"]
#[inline(always)]
pub fn aesblkcnt4(&mut self) -> Aesblkcnt4W<'_, Aesactl1Spec> {
Aesblkcnt4W::new(self, 4)
}
#[doc = "Bit 5 - AES Cipher Block Counter Bit: 5"]
#[inline(always)]
pub fn aesblkcnt5(&mut self) -> Aesblkcnt5W<'_, Aesactl1Spec> {
Aesblkcnt5W::new(self, 5)
}
#[doc = "Bit 6 - AES Cipher Block Counter Bit: 6"]
#[inline(always)]
pub fn aesblkcnt6(&mut self) -> Aesblkcnt6W<'_, Aesactl1Spec> {
Aesblkcnt6W::new(self, 6)
}
#[doc = "Bit 7 - AES Cipher Block Counter Bit: 7"]
#[inline(always)]
pub fn aesblkcnt7(&mut self) -> Aesblkcnt7W<'_, Aesactl1Spec> {
Aesblkcnt7W::new(self, 7)
}
}
#[doc = "AES accelerator control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`aesactl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aesactl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Aesactl1Spec;
impl crate::RegisterSpec for Aesactl1Spec {
type Ux = u16;
}
#[doc = "`read()` method returns [`aesactl1::R`](R) reader structure"]
impl crate::Readable for Aesactl1Spec {}
#[doc = "`write(|w| ..)` method takes [`aesactl1::W`](W) writer structure"]
impl crate::Writable for Aesactl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets AESACTL1 to value 0"]
impl crate::Resettable for Aesactl1Spec {}
}
#[doc = "AESASTAT (rw) register accessor: AES accelerator status register\n\nYou can [`read`](crate::Reg::read) this register and get [`aesastat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aesastat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aesastat`] module"]
#[doc(alias = "AESASTAT")]
pub type Aesastat = crate::Reg<aesastat::AesastatSpec>;
#[doc = "AES accelerator status register"]
pub mod aesastat {
#[doc = "Register `AESASTAT` reader"]
pub type R = crate::R<AesastatSpec>;
#[doc = "Register `AESASTAT` writer"]
pub type W = crate::W<AesastatSpec>;
#[doc = "Field `AESBUSY` reader - AES Busy"]
pub type AesbusyR = crate::BitReader;
#[doc = "Field `AESBUSY` writer - AES Busy"]
pub type AesbusyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESKEYWR` reader - AES All 16 bytes written to AESAKEY"]
pub type AeskeywrR = crate::BitReader;
#[doc = "Field `AESKEYWR` writer - AES All 16 bytes written to AESAKEY"]
pub type AeskeywrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESDINWR` reader - AES All 16 bytes written to AESADIN"]
pub type AesdinwrR = crate::BitReader;
#[doc = "Field `AESDINWR` writer - AES All 16 bytes written to AESADIN"]
pub type AesdinwrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESDOUTRD` reader - AES All 16 bytes read from AESADOUT"]
pub type AesdoutrdR = crate::BitReader;
#[doc = "Field `AESDOUTRD` writer - AES All 16 bytes read from AESADOUT"]
pub type AesdoutrdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESKEYCNT0` reader - AES Bytes written via AESAKEY Bit: 0"]
pub type Aeskeycnt0R = crate::BitReader;
#[doc = "Field `AESKEYCNT0` writer - AES Bytes written via AESAKEY Bit: 0"]
pub type Aeskeycnt0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESKEYCNT1` reader - AES Bytes written via AESAKEY Bit: 1"]
pub type Aeskeycnt1R = crate::BitReader;
#[doc = "Field `AESKEYCNT1` writer - AES Bytes written via AESAKEY Bit: 1"]
pub type Aeskeycnt1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESKEYCNT2` reader - AES Bytes written via AESAKEY Bit: 2"]
pub type Aeskeycnt2R = crate::BitReader;
#[doc = "Field `AESKEYCNT2` writer - AES Bytes written via AESAKEY Bit: 2"]
pub type Aeskeycnt2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESKEYCNT3` reader - AES Bytes written via AESAKEY Bit: 3"]
pub type Aeskeycnt3R = crate::BitReader;
#[doc = "Field `AESKEYCNT3` writer - AES Bytes written via AESAKEY Bit: 3"]
pub type Aeskeycnt3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESDINCNT0` reader - AES Bytes written via AESADIN Bit: 0"]
pub type Aesdincnt0R = crate::BitReader;
#[doc = "Field `AESDINCNT0` writer - AES Bytes written via AESADIN Bit: 0"]
pub type Aesdincnt0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESDINCNT1` reader - AES Bytes written via AESADIN Bit: 1"]
pub type Aesdincnt1R = crate::BitReader;
#[doc = "Field `AESDINCNT1` writer - AES Bytes written via AESADIN Bit: 1"]
pub type Aesdincnt1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESDINCNT2` reader - AES Bytes written via AESADIN Bit: 2"]
pub type Aesdincnt2R = crate::BitReader;
#[doc = "Field `AESDINCNT2` writer - AES Bytes written via AESADIN Bit: 2"]
pub type Aesdincnt2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESDINCNT3` reader - AES Bytes written via AESADIN Bit: 3"]
pub type Aesdincnt3R = crate::BitReader;
#[doc = "Field `AESDINCNT3` writer - AES Bytes written via AESADIN Bit: 3"]
pub type Aesdincnt3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESDOUTCNT0` reader - AES Bytes read via AESADOUT Bit: 0"]
pub type Aesdoutcnt0R = crate::BitReader;
#[doc = "Field `AESDOUTCNT0` writer - AES Bytes read via AESADOUT Bit: 0"]
pub type Aesdoutcnt0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESDOUTCNT1` reader - AES Bytes read via AESADOUT Bit: 1"]
pub type Aesdoutcnt1R = crate::BitReader;
#[doc = "Field `AESDOUTCNT1` writer - AES Bytes read via AESADOUT Bit: 1"]
pub type Aesdoutcnt1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESDOUTCNT2` reader - AES Bytes read via AESADOUT Bit: 2"]
pub type Aesdoutcnt2R = crate::BitReader;
#[doc = "Field `AESDOUTCNT2` writer - AES Bytes read via AESADOUT Bit: 2"]
pub type Aesdoutcnt2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AESDOUTCNT3` reader - AES Bytes read via AESADOUT Bit: 3"]
pub type Aesdoutcnt3R = crate::BitReader;
#[doc = "Field `AESDOUTCNT3` writer - AES Bytes read via AESADOUT Bit: 3"]
pub type Aesdoutcnt3W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - AES Busy"]
#[inline(always)]
pub fn aesbusy(&self) -> AesbusyR {
AesbusyR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - AES All 16 bytes written to AESAKEY"]
#[inline(always)]
pub fn aeskeywr(&self) -> AeskeywrR {
AeskeywrR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - AES All 16 bytes written to AESADIN"]
#[inline(always)]
pub fn aesdinwr(&self) -> AesdinwrR {
AesdinwrR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - AES All 16 bytes read from AESADOUT"]
#[inline(always)]
pub fn aesdoutrd(&self) -> AesdoutrdR {
AesdoutrdR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - AES Bytes written via AESAKEY Bit: 0"]
#[inline(always)]
pub fn aeskeycnt0(&self) -> Aeskeycnt0R {
Aeskeycnt0R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - AES Bytes written via AESAKEY Bit: 1"]
#[inline(always)]
pub fn aeskeycnt1(&self) -> Aeskeycnt1R {
Aeskeycnt1R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - AES Bytes written via AESAKEY Bit: 2"]
#[inline(always)]
pub fn aeskeycnt2(&self) -> Aeskeycnt2R {
Aeskeycnt2R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - AES Bytes written via AESAKEY Bit: 3"]
#[inline(always)]
pub fn aeskeycnt3(&self) -> Aeskeycnt3R {
Aeskeycnt3R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - AES Bytes written via AESADIN Bit: 0"]
#[inline(always)]
pub fn aesdincnt0(&self) -> Aesdincnt0R {
Aesdincnt0R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - AES Bytes written via AESADIN Bit: 1"]
#[inline(always)]
pub fn aesdincnt1(&self) -> Aesdincnt1R {
Aesdincnt1R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - AES Bytes written via AESADIN Bit: 2"]
#[inline(always)]
pub fn aesdincnt2(&self) -> Aesdincnt2R {
Aesdincnt2R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - AES Bytes written via AESADIN Bit: 3"]
#[inline(always)]
pub fn aesdincnt3(&self) -> Aesdincnt3R {
Aesdincnt3R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - AES Bytes read via AESADOUT Bit: 0"]
#[inline(always)]
pub fn aesdoutcnt0(&self) -> Aesdoutcnt0R {
Aesdoutcnt0R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - AES Bytes read via AESADOUT Bit: 1"]
#[inline(always)]
pub fn aesdoutcnt1(&self) -> Aesdoutcnt1R {
Aesdoutcnt1R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - AES Bytes read via AESADOUT Bit: 2"]
#[inline(always)]
pub fn aesdoutcnt2(&self) -> Aesdoutcnt2R {
Aesdoutcnt2R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - AES Bytes read via AESADOUT Bit: 3"]
#[inline(always)]
pub fn aesdoutcnt3(&self) -> Aesdoutcnt3R {
Aesdoutcnt3R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - AES Busy"]
#[inline(always)]
pub fn aesbusy(&mut self) -> AesbusyW<'_, AesastatSpec> {
AesbusyW::new(self, 0)
}
#[doc = "Bit 1 - AES All 16 bytes written to AESAKEY"]
#[inline(always)]
pub fn aeskeywr(&mut self) -> AeskeywrW<'_, AesastatSpec> {
AeskeywrW::new(self, 1)
}
#[doc = "Bit 2 - AES All 16 bytes written to AESADIN"]
#[inline(always)]
pub fn aesdinwr(&mut self) -> AesdinwrW<'_, AesastatSpec> {
AesdinwrW::new(self, 2)
}
#[doc = "Bit 3 - AES All 16 bytes read from AESADOUT"]
#[inline(always)]
pub fn aesdoutrd(&mut self) -> AesdoutrdW<'_, AesastatSpec> {
AesdoutrdW::new(self, 3)
}
#[doc = "Bit 4 - AES Bytes written via AESAKEY Bit: 0"]
#[inline(always)]
pub fn aeskeycnt0(&mut self) -> Aeskeycnt0W<'_, AesastatSpec> {
Aeskeycnt0W::new(self, 4)
}
#[doc = "Bit 5 - AES Bytes written via AESAKEY Bit: 1"]
#[inline(always)]
pub fn aeskeycnt1(&mut self) -> Aeskeycnt1W<'_, AesastatSpec> {
Aeskeycnt1W::new(self, 5)
}
#[doc = "Bit 6 - AES Bytes written via AESAKEY Bit: 2"]
#[inline(always)]
pub fn aeskeycnt2(&mut self) -> Aeskeycnt2W<'_, AesastatSpec> {
Aeskeycnt2W::new(self, 6)
}
#[doc = "Bit 7 - AES Bytes written via AESAKEY Bit: 3"]
#[inline(always)]
pub fn aeskeycnt3(&mut self) -> Aeskeycnt3W<'_, AesastatSpec> {
Aeskeycnt3W::new(self, 7)
}
#[doc = "Bit 8 - AES Bytes written via AESADIN Bit: 0"]
#[inline(always)]
pub fn aesdincnt0(&mut self) -> Aesdincnt0W<'_, AesastatSpec> {
Aesdincnt0W::new(self, 8)
}
#[doc = "Bit 9 - AES Bytes written via AESADIN Bit: 1"]
#[inline(always)]
pub fn aesdincnt1(&mut self) -> Aesdincnt1W<'_, AesastatSpec> {
Aesdincnt1W::new(self, 9)
}
#[doc = "Bit 10 - AES Bytes written via AESADIN Bit: 2"]
#[inline(always)]
pub fn aesdincnt2(&mut self) -> Aesdincnt2W<'_, AesastatSpec> {
Aesdincnt2W::new(self, 10)
}
#[doc = "Bit 11 - AES Bytes written via AESADIN Bit: 3"]
#[inline(always)]
pub fn aesdincnt3(&mut self) -> Aesdincnt3W<'_, AesastatSpec> {
Aesdincnt3W::new(self, 11)
}
#[doc = "Bit 12 - AES Bytes read via AESADOUT Bit: 0"]
#[inline(always)]
pub fn aesdoutcnt0(&mut self) -> Aesdoutcnt0W<'_, AesastatSpec> {
Aesdoutcnt0W::new(self, 12)
}
#[doc = "Bit 13 - AES Bytes read via AESADOUT Bit: 1"]
#[inline(always)]
pub fn aesdoutcnt1(&mut self) -> Aesdoutcnt1W<'_, AesastatSpec> {
Aesdoutcnt1W::new(self, 13)
}
#[doc = "Bit 14 - AES Bytes read via AESADOUT Bit: 2"]
#[inline(always)]
pub fn aesdoutcnt2(&mut self) -> Aesdoutcnt2W<'_, AesastatSpec> {
Aesdoutcnt2W::new(self, 14)
}
#[doc = "Bit 15 - AES Bytes read via AESADOUT Bit: 3"]
#[inline(always)]
pub fn aesdoutcnt3(&mut self) -> Aesdoutcnt3W<'_, AesastatSpec> {
Aesdoutcnt3W::new(self, 15)
}
}
#[doc = "AES accelerator status register\n\nYou can [`read`](crate::Reg::read) this register and get [`aesastat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aesastat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AesastatSpec;
impl crate::RegisterSpec for AesastatSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`aesastat::R`](R) reader structure"]
impl crate::Readable for AesastatSpec {}
#[doc = "`write(|w| ..)` method takes [`aesastat::W`](W) writer structure"]
impl crate::Writable for AesastatSpec {
type Safety = crate::Safe;
}
#[doc = "`reset()` method sets AESASTAT to value 0"]
impl crate::Resettable for AesastatSpec {}
}
#[doc = "AESAKEY (rw) register accessor: AES accelerator key register\n\nYou can [`read`](crate::Reg::read) this register and get [`aesakey::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aesakey::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aesakey`] module"]
#[doc(alias = "AESAKEY")]
pub type Aesakey = crate::Reg<aesakey::AesakeySpec>;
#[doc = "AES accelerator key register"]
pub mod aesakey {
#[doc = "Register `AESAKEY` reader"]
pub type R = crate::R<AesakeySpec>;
#[doc = "Register `AESAKEY` writer"]
pub type W = crate::W<AesakeySpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "AES accelerator key register\n\nYou can [`read`](crate::Reg::read) this register and get [`aesakey::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aesakey::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AesakeySpec;
impl crate::RegisterSpec for AesakeySpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`aesakey::R`](R) reader structure"]
impl crate::Readable for AesakeySpec {}
#[doc = "`write(|w| ..)` method takes [`aesakey::W`](W) writer structure"]
impl crate::Writable for AesakeySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets AESAKEY to value 0"]
impl crate::Resettable for AesakeySpec {}
}
#[doc = "AESADIN (rw) register accessor: AES accelerator data in register\n\nYou can [`read`](crate::Reg::read) this register and get [`aesadin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aesadin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aesadin`] module"]
#[doc(alias = "AESADIN")]
pub type Aesadin = crate::Reg<aesadin::AesadinSpec>;
#[doc = "AES accelerator data in register"]
pub mod aesadin {
#[doc = "Register `AESADIN` reader"]
pub type R = crate::R<AesadinSpec>;
#[doc = "Register `AESADIN` writer"]
pub type W = crate::W<AesadinSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "AES accelerator data in register\n\nYou can [`read`](crate::Reg::read) this register and get [`aesadin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aesadin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AesadinSpec;
impl crate::RegisterSpec for AesadinSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`aesadin::R`](R) reader structure"]
impl crate::Readable for AesadinSpec {}
#[doc = "`write(|w| ..)` method takes [`aesadin::W`](W) writer structure"]
impl crate::Writable for AesadinSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets AESADIN to value 0"]
impl crate::Resettable for AesadinSpec {}
}
#[doc = "AESADOUT (rw) register accessor: AES accelerator data out register\n\nYou can [`read`](crate::Reg::read) this register and get [`aesadout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aesadout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aesadout`] module"]
#[doc(alias = "AESADOUT")]
pub type Aesadout = crate::Reg<aesadout::AesadoutSpec>;
#[doc = "AES accelerator data out register"]
pub mod aesadout {
#[doc = "Register `AESADOUT` reader"]
pub type R = crate::R<AesadoutSpec>;
#[doc = "Register `AESADOUT` writer"]
pub type W = crate::W<AesadoutSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "AES accelerator data out register\n\nYou can [`read`](crate::Reg::read) this register and get [`aesadout::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aesadout::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AesadoutSpec;
impl crate::RegisterSpec for AesadoutSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`aesadout::R`](R) reader structure"]
impl crate::Readable for AesadoutSpec {}
#[doc = "`write(|w| ..)` method takes [`aesadout::W`](W) writer structure"]
impl crate::Writable for AesadoutSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets AESADOUT to value 0"]
impl crate::Resettable for AesadoutSpec {}
}
#[doc = "AESAXDIN (rw) register accessor: AES accelerator XORed data in register\n\nYou can [`read`](crate::Reg::read) this register and get [`aesaxdin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aesaxdin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aesaxdin`] module"]
#[doc(alias = "AESAXDIN")]
pub type Aesaxdin = crate::Reg<aesaxdin::AesaxdinSpec>;
#[doc = "AES accelerator XORed data in register"]
pub mod aesaxdin {
#[doc = "Register `AESAXDIN` reader"]
pub type R = crate::R<AesaxdinSpec>;
#[doc = "Register `AESAXDIN` writer"]
pub type W = crate::W<AesaxdinSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "AES accelerator XORed data in register\n\nYou can [`read`](crate::Reg::read) this register and get [`aesaxdin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aesaxdin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AesaxdinSpec;
impl crate::RegisterSpec for AesaxdinSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`aesaxdin::R`](R) reader structure"]
impl crate::Readable for AesaxdinSpec {}
#[doc = "`write(|w| ..)` method takes [`aesaxdin::W`](W) writer structure"]
impl crate::Writable for AesaxdinSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets AESAXDIN to value 0"]
impl crate::Resettable for AesaxdinSpec {}
}
#[doc = "AESAXIN (rw) register accessor: AES accelerator XORed data in register (no trigger)\n\nYou can [`read`](crate::Reg::read) this register and get [`aesaxin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aesaxin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aesaxin`] module"]
#[doc(alias = "AESAXIN")]
pub type Aesaxin = crate::Reg<aesaxin::AesaxinSpec>;
#[doc = "AES accelerator XORed data in register (no trigger)"]
pub mod aesaxin {
#[doc = "Register `AESAXIN` reader"]
pub type R = crate::R<AesaxinSpec>;
#[doc = "Register `AESAXIN` writer"]
pub type W = crate::W<AesaxinSpec>;
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
write!(f, "{}", self.bits())
}
}
impl W {}
#[doc = "AES accelerator XORed data in register (no trigger)\n\nYou can [`read`](crate::Reg::read) this register and get [`aesaxin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aesaxin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AesaxinSpec;
impl crate::RegisterSpec for AesaxinSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`aesaxin::R`](R) reader structure"]
impl crate::Readable for AesaxinSpec {}
#[doc = "`write(|w| ..)` method takes [`aesaxin::W`](W) writer structure"]
impl crate::Writable for AesaxinSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets AESAXIN to value 0"]
impl crate::Resettable for AesaxinSpec {}
}
}
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
#[doc = r" All the peripherals."]
#[allow(non_snake_case)]
pub struct Peripherals {
#[doc = "PORT_1_2"]
pub port_1_2: Port1_2,
#[doc = "PORT_3_4"]
pub port_3_4: Port3_4,
#[doc = "RTC_B_REAL_TIME_CLOCK"]
pub rtc_b_real_time_clock: RtcBRealTimeClock,
#[doc = "USCI_A0_UART_MODE"]
pub usci_a0_uart_mode: UsciA0UartMode,
#[doc = "USCI_A0_SPI_MODE"]
pub usci_a0_spi_mode: UsciA0SpiMode,
#[doc = "USCI_A1_UART_MODE"]
pub usci_a1_uart_mode: UsciA1UartMode,
#[doc = "USCI_A1_SPI_MODE"]
pub usci_a1_spi_mode: UsciA1SpiMode,
#[doc = "USCI_B0_I2C_MODE"]
pub usci_b0_i2c_mode: UsciB0I2cMode,
#[doc = "USCI_B0_SPI_MODE"]
pub usci_b0_spi_mode: UsciB0SpiMode,
#[doc = "SFR"]
pub sfr: Sfr,
#[doc = "PMM"]
pub pmm: Pmm,
#[doc = "FRAM"]
pub fram: Fram,
#[doc = "CRC16"]
pub crc16: Crc16,
#[doc = "WATCHDOG_TIMER"]
pub watchdog_timer: WatchdogTimer,
#[doc = "CS"]
pub cs: Cs,
#[doc = "SYS"]
pub sys: Sys,
#[doc = "SHARED_REFERENCE"]
pub shared_reference: SharedReference,
#[doc = "PORT_J"]
pub port_j: PortJ,
#[doc = "TIMER_0_A3"]
pub timer_0_a3: Timer0A3,
#[doc = "TIMER_1_A3"]
pub timer_1_a3: Timer1A3,
#[doc = "TIMER_0_B7"]
pub timer_0_b7: Timer0B7,
#[doc = "TIMER_2_A2"]
pub timer_2_a2: Timer2A2,
#[doc = "CAPACITIVE_TOUCH_IO_0"]
pub capacitive_touch_io_0: CapacitiveTouchIo0,
#[doc = "TIMER_3_A2"]
pub timer_3_a2: Timer3A2,
#[doc = "CAPACITIVE_TOUCH_IO_1"]
pub capacitive_touch_io_1: CapacitiveTouchIo1,
#[doc = "MPY_16"]
pub mpy_16: Mpy16,
#[doc = "MPY_32"]
pub mpy_32: Mpy32,
#[doc = "DMA"]
pub dma: Dma,
#[doc = "MPU"]
pub mpu: Mpu,
#[doc = "ADC12"]
pub adc12: Adc12,
#[doc = "COMPARATOR_E"]
pub comparator_e: ComparatorE,
#[doc = "AES_ACCELERATOR"]
pub aes_accelerator: AesAccelerator,
}
impl Peripherals {
#[doc = r" Returns all the peripherals *once*."]
#[cfg(feature = "critical-section")]
#[inline]
pub fn take() -> Option<Self> {
critical_section::with(|_| {
if unsafe { DEVICE_PERIPHERALS } {
return None;
}
Some(unsafe { Peripherals::steal() })
})
}
#[doc = r" Unchecked version of `Peripherals::take`."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Each of the returned peripherals must be used at most once."]
#[inline]
pub unsafe fn steal() -> Self {
DEVICE_PERIPHERALS = true;
Peripherals {
port_1_2: Port1_2::steal(),
port_3_4: Port3_4::steal(),
rtc_b_real_time_clock: RtcBRealTimeClock::steal(),
usci_a0_uart_mode: UsciA0UartMode::steal(),
usci_a0_spi_mode: UsciA0SpiMode::steal(),
usci_a1_uart_mode: UsciA1UartMode::steal(),
usci_a1_spi_mode: UsciA1SpiMode::steal(),
usci_b0_i2c_mode: UsciB0I2cMode::steal(),
usci_b0_spi_mode: UsciB0SpiMode::steal(),
sfr: Sfr::steal(),
pmm: Pmm::steal(),
fram: Fram::steal(),
crc16: Crc16::steal(),
watchdog_timer: WatchdogTimer::steal(),
cs: Cs::steal(),
sys: Sys::steal(),
shared_reference: SharedReference::steal(),
port_j: PortJ::steal(),
timer_0_a3: Timer0A3::steal(),
timer_1_a3: Timer1A3::steal(),
timer_0_b7: Timer0B7::steal(),
timer_2_a2: Timer2A2::steal(),
capacitive_touch_io_0: CapacitiveTouchIo0::steal(),
timer_3_a2: Timer3A2::steal(),
capacitive_touch_io_1: CapacitiveTouchIo1::steal(),
mpy_16: Mpy16::steal(),
mpy_32: Mpy32::steal(),
dma: Dma::steal(),
mpu: Mpu::steal(),
adc12: Adc12::steal(),
comparator_e: ComparatorE::steal(),
aes_accelerator: AesAccelerator::steal(),
}
}
}