msp430fr5962/sys/
sysctl.rs

1#[doc = "Register `SYSCTL` reader"]
2pub type R = crate::R<SysctlSpec>;
3#[doc = "Register `SYSCTL` writer"]
4pub type W = crate::W<SysctlSpec>;
5#[doc = "0:0\\]
6RAM-based interrupt vectors\n\nValue on reset: 0"]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Sysrivect {
9    #[doc = "0: Interrupt vectors generated with end address TOP of lower 64K FRAM FFFFh"]
10    Fram = 0,
11    #[doc = "1: Interrupt vectors generated with end address TOP of RAM, when RAM available"]
12    Ram = 1,
13}
14impl From<Sysrivect> for bool {
15    #[inline(always)]
16    fn from(variant: Sysrivect) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `SYSRIVECT` reader - 0:0\\]
21RAM-based interrupt vectors"]
22pub type SysrivectR = crate::BitReader<Sysrivect>;
23impl SysrivectR {
24    #[doc = "Get enumerated values variant"]
25    #[inline(always)]
26    pub const fn variant(&self) -> Sysrivect {
27        match self.bits {
28            false => Sysrivect::Fram,
29            true => Sysrivect::Ram,
30        }
31    }
32    #[doc = "Interrupt vectors generated with end address TOP of lower 64K FRAM FFFFh"]
33    #[inline(always)]
34    pub fn is_fram(&self) -> bool {
35        *self == Sysrivect::Fram
36    }
37    #[doc = "Interrupt vectors generated with end address TOP of RAM, when RAM available"]
38    #[inline(always)]
39    pub fn is_ram(&self) -> bool {
40        *self == Sysrivect::Ram
41    }
42}
43#[doc = "Field `SYSRIVECT` writer - 0:0\\]
44RAM-based interrupt vectors"]
45pub type SysrivectW<'a, REG> = crate::BitWriter<'a, REG, Sysrivect>;
46impl<'a, REG> SysrivectW<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    #[doc = "Interrupt vectors generated with end address TOP of lower 64K FRAM FFFFh"]
51    #[inline(always)]
52    pub fn fram(self) -> &'a mut crate::W<REG> {
53        self.variant(Sysrivect::Fram)
54    }
55    #[doc = "Interrupt vectors generated with end address TOP of RAM, when RAM available"]
56    #[inline(always)]
57    pub fn ram(self) -> &'a mut crate::W<REG> {
58        self.variant(Sysrivect::Ram)
59    }
60}
61#[doc = "2:2\\]
62PMM access protect\n\nValue on reset: 0"]
63#[derive(Clone, Copy, Debug, PartialEq, Eq)]
64pub enum Syspmmpe {
65    #[doc = "0: Access from anywhere in memory"]
66    Syspmmpe0 = 0,
67    #[doc = "1: Access only from the BSL segments"]
68    Syspmmpe1 = 1,
69}
70impl From<Syspmmpe> for bool {
71    #[inline(always)]
72    fn from(variant: Syspmmpe) -> Self {
73        variant as u8 != 0
74    }
75}
76#[doc = "Field `SYSPMMPE` reader - 2:2\\]
77PMM access protect"]
78pub type SyspmmpeR = crate::BitReader<Syspmmpe>;
79impl SyspmmpeR {
80    #[doc = "Get enumerated values variant"]
81    #[inline(always)]
82    pub const fn variant(&self) -> Syspmmpe {
83        match self.bits {
84            false => Syspmmpe::Syspmmpe0,
85            true => Syspmmpe::Syspmmpe1,
86        }
87    }
88    #[doc = "Access from anywhere in memory"]
89    #[inline(always)]
90    pub fn is_syspmmpe_0(&self) -> bool {
91        *self == Syspmmpe::Syspmmpe0
92    }
93    #[doc = "Access only from the BSL segments"]
94    #[inline(always)]
95    pub fn is_syspmmpe_1(&self) -> bool {
96        *self == Syspmmpe::Syspmmpe1
97    }
98}
99#[doc = "Field `SYSPMMPE` writer - 2:2\\]
100PMM access protect"]
101pub type SyspmmpeW<'a, REG> = crate::BitWriter<'a, REG, Syspmmpe>;
102impl<'a, REG> SyspmmpeW<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    #[doc = "Access from anywhere in memory"]
107    #[inline(always)]
108    pub fn syspmmpe_0(self) -> &'a mut crate::W<REG> {
109        self.variant(Syspmmpe::Syspmmpe0)
110    }
111    #[doc = "Access only from the BSL segments"]
112    #[inline(always)]
113    pub fn syspmmpe_1(self) -> &'a mut crate::W<REG> {
114        self.variant(Syspmmpe::Syspmmpe1)
115    }
116}
117#[doc = "4:4\\]
118BSL entry indication\n\nValue on reset: 0"]
119#[derive(Clone, Copy, Debug, PartialEq, Eq)]
120pub enum Sysbslind {
121    #[doc = "0: No BSL entry sequence detected"]
122    Sysbslind0 = 0,
123    #[doc = "1: BSL entry sequence detected"]
124    Sysbslind1 = 1,
125}
126impl From<Sysbslind> for bool {
127    #[inline(always)]
128    fn from(variant: Sysbslind) -> Self {
129        variant as u8 != 0
130    }
131}
132#[doc = "Field `SYSBSLIND` reader - 4:4\\]
133BSL entry indication"]
134pub type SysbslindR = crate::BitReader<Sysbslind>;
135impl SysbslindR {
136    #[doc = "Get enumerated values variant"]
137    #[inline(always)]
138    pub const fn variant(&self) -> Sysbslind {
139        match self.bits {
140            false => Sysbslind::Sysbslind0,
141            true => Sysbslind::Sysbslind1,
142        }
143    }
144    #[doc = "No BSL entry sequence detected"]
145    #[inline(always)]
146    pub fn is_sysbslind_0(&self) -> bool {
147        *self == Sysbslind::Sysbslind0
148    }
149    #[doc = "BSL entry sequence detected"]
150    #[inline(always)]
151    pub fn is_sysbslind_1(&self) -> bool {
152        *self == Sysbslind::Sysbslind1
153    }
154}
155#[doc = "Field `SYSBSLIND` writer - 4:4\\]
156BSL entry indication"]
157pub type SysbslindW<'a, REG> = crate::BitWriter<'a, REG, Sysbslind>;
158impl<'a, REG> SysbslindW<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    #[doc = "No BSL entry sequence detected"]
163    #[inline(always)]
164    pub fn sysbslind_0(self) -> &'a mut crate::W<REG> {
165        self.variant(Sysbslind::Sysbslind0)
166    }
167    #[doc = "BSL entry sequence detected"]
168    #[inline(always)]
169    pub fn sysbslind_1(self) -> &'a mut crate::W<REG> {
170        self.variant(Sysbslind::Sysbslind1)
171    }
172}
173#[doc = "5:5\\]
174Dedicated JTAG pins enable\n\nValue on reset: 0"]
175#[derive(Clone, Copy, Debug, PartialEq, Eq)]
176pub enum Sysjtagpin {
177    #[doc = "0: Shared JTAG pins (JTAG mode selectable using SBW sequence)"]
178    Shared = 0,
179    #[doc = "1: Dedicated JTAG pins (explicit 4-wire JTAG mode selection)"]
180    Dedicated = 1,
181}
182impl From<Sysjtagpin> for bool {
183    #[inline(always)]
184    fn from(variant: Sysjtagpin) -> Self {
185        variant as u8 != 0
186    }
187}
188#[doc = "Field `SYSJTAGPIN` reader - 5:5\\]
189Dedicated JTAG pins enable"]
190pub type SysjtagpinR = crate::BitReader<Sysjtagpin>;
191impl SysjtagpinR {
192    #[doc = "Get enumerated values variant"]
193    #[inline(always)]
194    pub const fn variant(&self) -> Sysjtagpin {
195        match self.bits {
196            false => Sysjtagpin::Shared,
197            true => Sysjtagpin::Dedicated,
198        }
199    }
200    #[doc = "Shared JTAG pins (JTAG mode selectable using SBW sequence)"]
201    #[inline(always)]
202    pub fn is_shared(&self) -> bool {
203        *self == Sysjtagpin::Shared
204    }
205    #[doc = "Dedicated JTAG pins (explicit 4-wire JTAG mode selection)"]
206    #[inline(always)]
207    pub fn is_dedicated(&self) -> bool {
208        *self == Sysjtagpin::Dedicated
209    }
210}
211#[doc = "Field `SYSJTAGPIN` writer - 5:5\\]
212Dedicated JTAG pins enable"]
213pub type SysjtagpinW<'a, REG> = crate::BitWriter<'a, REG, Sysjtagpin>;
214impl<'a, REG> SysjtagpinW<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    #[doc = "Shared JTAG pins (JTAG mode selectable using SBW sequence)"]
219    #[inline(always)]
220    pub fn shared(self) -> &'a mut crate::W<REG> {
221        self.variant(Sysjtagpin::Shared)
222    }
223    #[doc = "Dedicated JTAG pins (explicit 4-wire JTAG mode selection)"]
224    #[inline(always)]
225    pub fn dedicated(self) -> &'a mut crate::W<REG> {
226        self.variant(Sysjtagpin::Dedicated)
227    }
228}
229impl R {
230    #[doc = "Bit 0 - 0:0\\]
231RAM-based interrupt vectors"]
232    #[inline(always)]
233    pub fn sysrivect(&self) -> SysrivectR {
234        SysrivectR::new((self.bits & 1) != 0)
235    }
236    #[doc = "Bit 2 - 2:2\\]
237PMM access protect"]
238    #[inline(always)]
239    pub fn syspmmpe(&self) -> SyspmmpeR {
240        SyspmmpeR::new(((self.bits >> 2) & 1) != 0)
241    }
242    #[doc = "Bit 4 - 4:4\\]
243BSL entry indication"]
244    #[inline(always)]
245    pub fn sysbslind(&self) -> SysbslindR {
246        SysbslindR::new(((self.bits >> 4) & 1) != 0)
247    }
248    #[doc = "Bit 5 - 5:5\\]
249Dedicated JTAG pins enable"]
250    #[inline(always)]
251    pub fn sysjtagpin(&self) -> SysjtagpinR {
252        SysjtagpinR::new(((self.bits >> 5) & 1) != 0)
253    }
254}
255impl W {
256    #[doc = "Bit 0 - 0:0\\]
257RAM-based interrupt vectors"]
258    #[inline(always)]
259    #[must_use]
260    pub fn sysrivect(&mut self) -> SysrivectW<SysctlSpec> {
261        SysrivectW::new(self, 0)
262    }
263    #[doc = "Bit 2 - 2:2\\]
264PMM access protect"]
265    #[inline(always)]
266    #[must_use]
267    pub fn syspmmpe(&mut self) -> SyspmmpeW<SysctlSpec> {
268        SyspmmpeW::new(self, 2)
269    }
270    #[doc = "Bit 4 - 4:4\\]
271BSL entry indication"]
272    #[inline(always)]
273    #[must_use]
274    pub fn sysbslind(&mut self) -> SysbslindW<SysctlSpec> {
275        SysbslindW::new(self, 4)
276    }
277    #[doc = "Bit 5 - 5:5\\]
278Dedicated JTAG pins enable"]
279    #[inline(always)]
280    #[must_use]
281    pub fn sysjtagpin(&mut self) -> SysjtagpinW<SysctlSpec> {
282        SysjtagpinW::new(self, 5)
283    }
284}
285#[doc = "System Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sysctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
286pub struct SysctlSpec;
287impl crate::RegisterSpec for SysctlSpec {
288    type Ux = u16;
289}
290#[doc = "`read()` method returns [`sysctl::R`](R) reader structure"]
291impl crate::Readable for SysctlSpec {}
292#[doc = "`write(|w| ..)` method takes [`sysctl::W`](W) writer structure"]
293impl crate::Writable for SysctlSpec {
294    type Safety = crate::Unsafe;
295    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
296    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
297}
298#[doc = "`reset()` method sets SYSCTL to value 0"]
299impl crate::Resettable for SysctlSpec {
300    const RESET_VALUE: u16 = 0;
301}
msp430fr5962/sys/sysctl.rs

msp430fr5962/sys/
sysctl.rs
