1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4 p3in: P3in,
5 _reserved1: [u8; 0x01],
6 p3out: P3out,
7 _reserved2: [u8; 0x01],
8 p3dir: P3dir,
9 _reserved3: [u8; 0x01],
10 p3ren: P3ren,
11 _reserved4: [u8; 0x03],
12 p3sel0: P3sel0,
13 _reserved5: [u8; 0x01],
14 p3sel1: P3sel1,
15 _reserved6: [u8; 0x01],
16 p3iv: P3iv,
17 _reserved7: [u8; 0x06],
18 p3selc: P3selc,
19 _reserved8: [u8; 0x01],
20 p3ies: P3ies,
21 _reserved9: [u8; 0x01],
22 p3ie: P3ie,
23 _reserved10: [u8; 0x01],
24 p3ifg: P3ifg,
25}
26impl RegisterBlock {
27 #[doc = "0x00 - Port 3 Input"]
28 #[inline(always)]
29 pub const fn p3in(&self) -> &P3in {
30 &self.p3in
31 }
32 #[doc = "0x02 - Port 3 Output"]
33 #[inline(always)]
34 pub const fn p3out(&self) -> &P3out {
35 &self.p3out
36 }
37 #[doc = "0x04 - Port 3 Direction"]
38 #[inline(always)]
39 pub const fn p3dir(&self) -> &P3dir {
40 &self.p3dir
41 }
42 #[doc = "0x06 - Port 3 Resistor Enable"]
43 #[inline(always)]
44 pub const fn p3ren(&self) -> &P3ren {
45 &self.p3ren
46 }
47 #[doc = "0x0a - Port 3 Select 0"]
48 #[inline(always)]
49 pub const fn p3sel0(&self) -> &P3sel0 {
50 &self.p3sel0
51 }
52 #[doc = "0x0c - Port 3 Select 1"]
53 #[inline(always)]
54 pub const fn p3sel1(&self) -> &P3sel1 {
55 &self.p3sel1
56 }
57 #[doc = "0x0e - Port 3 Interrupt Vector Register"]
58 #[inline(always)]
59 pub const fn p3iv(&self) -> &P3iv {
60 &self.p3iv
61 }
62 #[doc = "0x16 - Port 3 Complement Select"]
63 #[inline(always)]
64 pub const fn p3selc(&self) -> &P3selc {
65 &self.p3selc
66 }
67 #[doc = "0x18 - Port 3 Interrupt Edge Select"]
68 #[inline(always)]
69 pub const fn p3ies(&self) -> &P3ies {
70 &self.p3ies
71 }
72 #[doc = "0x1a - Port 3 Interrupt Enable"]
73 #[inline(always)]
74 pub const fn p3ie(&self) -> &P3ie {
75 &self.p3ie
76 }
77 #[doc = "0x1c - Port 3 Interrupt Flag"]
78 #[inline(always)]
79 pub const fn p3ifg(&self) -> &P3ifg {
80 &self.p3ifg
81 }
82}
83#[doc = "P3IN (rw) register accessor: Port 3 Input\n\nYou can [`read`](crate::Reg::read) this register and get [`p3in::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3in::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3in`] module"]
84#[doc(alias = "P3IN")]
85pub type P3in = crate::Reg<p3in::P3inSpec>;
86#[doc = "Port 3 Input"]
87pub mod p3in;
88#[doc = "P3OUT (rw) register accessor: Port 3 Output\n\nYou can [`read`](crate::Reg::read) this register and get [`p3out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3out`] module"]
89#[doc(alias = "P3OUT")]
90pub type P3out = crate::Reg<p3out::P3outSpec>;
91#[doc = "Port 3 Output"]
92pub mod p3out;
93#[doc = "P3DIR (rw) register accessor: Port 3 Direction\n\nYou can [`read`](crate::Reg::read) this register and get [`p3dir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3dir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3dir`] module"]
94#[doc(alias = "P3DIR")]
95pub type P3dir = crate::Reg<p3dir::P3dirSpec>;
96#[doc = "Port 3 Direction"]
97pub mod p3dir;
98#[doc = "P3REN (rw) register accessor: Port 3 Resistor Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p3ren::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3ren::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3ren`] module"]
99#[doc(alias = "P3REN")]
100pub type P3ren = crate::Reg<p3ren::P3renSpec>;
101#[doc = "Port 3 Resistor Enable"]
102pub mod p3ren;
103#[doc = "P3SEL0 (rw) register accessor: Port 3 Select 0\n\nYou can [`read`](crate::Reg::read) this register and get [`p3sel0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3sel0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3sel0`] module"]
104#[doc(alias = "P3SEL0")]
105pub type P3sel0 = crate::Reg<p3sel0::P3sel0Spec>;
106#[doc = "Port 3 Select 0"]
107pub mod p3sel0;
108#[doc = "P3SEL1 (rw) register accessor: Port 3 Select 1\n\nYou can [`read`](crate::Reg::read) this register and get [`p3sel1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3sel1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3sel1`] module"]
109#[doc(alias = "P3SEL1")]
110pub type P3sel1 = crate::Reg<p3sel1::P3sel1Spec>;
111#[doc = "Port 3 Select 1"]
112pub mod p3sel1;
113#[doc = "P3SELC (rw) register accessor: Port 3 Complement Select\n\nYou can [`read`](crate::Reg::read) this register and get [`p3selc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3selc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3selc`] module"]
114#[doc(alias = "P3SELC")]
115pub type P3selc = crate::Reg<p3selc::P3selcSpec>;
116#[doc = "Port 3 Complement Select"]
117pub mod p3selc;
118#[doc = "P3IES (rw) register accessor: Port 3 Interrupt Edge Select\n\nYou can [`read`](crate::Reg::read) this register and get [`p3ies::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3ies::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3ies`] module"]
119#[doc(alias = "P3IES")]
120pub type P3ies = crate::Reg<p3ies::P3iesSpec>;
121#[doc = "Port 3 Interrupt Edge Select"]
122pub mod p3ies;
123#[doc = "P3IE (rw) register accessor: Port 3 Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`p3ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3ie`] module"]
124#[doc(alias = "P3IE")]
125pub type P3ie = crate::Reg<p3ie::P3ieSpec>;
126#[doc = "Port 3 Interrupt Enable"]
127pub mod p3ie;
128#[doc = "P3IFG (rw) register accessor: Port 3 Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`p3ifg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3ifg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3ifg`] module"]
129#[doc(alias = "P3IFG")]
130pub type P3ifg = crate::Reg<p3ifg::P3ifgSpec>;
131#[doc = "Port 3 Interrupt Flag"]
132pub mod p3ifg;
133#[doc = "P3IV (rw) register accessor: Port 3 Interrupt Vector Register\n\nYou can [`read`](crate::Reg::read) this register and get [`p3iv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`p3iv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p3iv`] module"]
134#[doc(alias = "P3IV")]
135pub type P3iv = crate::Reg<p3iv::P3ivSpec>;
136#[doc = "Port 3 Interrupt Vector Register"]
137pub mod p3iv;