1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - Port 3 Input"]
5 pub p3in: P3IN,
6 _reserved1: [u8; 0x01],
7 #[doc = "0x02 - Port 3 Output"]
8 pub p3out: P3OUT,
9 _reserved2: [u8; 0x01],
10 #[doc = "0x04 - Port 3 Direction"]
11 pub p3dir: P3DIR,
12 _reserved3: [u8; 0x01],
13 #[doc = "0x06 - Port 3 Resistor Enable"]
14 pub p3ren: P3REN,
15 _reserved4: [u8; 0x03],
16 #[doc = "0x0a - Port 3 Select 0"]
17 pub p3sel0: P3SEL0,
18 _reserved5: [u8; 0x01],
19 #[doc = "0x0c - Port 3 Select 1"]
20 pub p3sel1: P3SEL1,
21 _reserved6: [u8; 0x01],
22 #[doc = "0x0e - Port 3 Interrupt Vector Register"]
23 pub p3iv: P3IV,
24 _reserved7: [u8; 0x06],
25 #[doc = "0x16 - Port 3 Complement Select"]
26 pub p3selc: P3SELC,
27 _reserved8: [u8; 0x01],
28 #[doc = "0x18 - Port 3 Interrupt Edge Select"]
29 pub p3ies: P3IES,
30 _reserved9: [u8; 0x01],
31 #[doc = "0x1a - Port 3 Interrupt Enable"]
32 pub p3ie: P3IE,
33 _reserved10: [u8; 0x01],
34 #[doc = "0x1c - Port 3 Interrupt Flag"]
35 pub p3ifg: P3IFG,
36}
37#[doc = "P3IN (rw) register accessor: an alias for `Reg<P3IN_SPEC>`"]
38pub type P3IN = crate::Reg<p3in::P3IN_SPEC>;
39#[doc = "Port 3 Input"]
40pub mod p3in;
41#[doc = "P3OUT (rw) register accessor: an alias for `Reg<P3OUT_SPEC>`"]
42pub type P3OUT = crate::Reg<p3out::P3OUT_SPEC>;
43#[doc = "Port 3 Output"]
44pub mod p3out;
45#[doc = "P3DIR (rw) register accessor: an alias for `Reg<P3DIR_SPEC>`"]
46pub type P3DIR = crate::Reg<p3dir::P3DIR_SPEC>;
47#[doc = "Port 3 Direction"]
48pub mod p3dir;
49#[doc = "P3REN (rw) register accessor: an alias for `Reg<P3REN_SPEC>`"]
50pub type P3REN = crate::Reg<p3ren::P3REN_SPEC>;
51#[doc = "Port 3 Resistor Enable"]
52pub mod p3ren;
53#[doc = "P3SEL0 (rw) register accessor: an alias for `Reg<P3SEL0_SPEC>`"]
54pub type P3SEL0 = crate::Reg<p3sel0::P3SEL0_SPEC>;
55#[doc = "Port 3 Select 0"]
56pub mod p3sel0;
57#[doc = "P3SEL1 (rw) register accessor: an alias for `Reg<P3SEL1_SPEC>`"]
58pub type P3SEL1 = crate::Reg<p3sel1::P3SEL1_SPEC>;
59#[doc = "Port 3 Select 1"]
60pub mod p3sel1;
61#[doc = "P3SELC (rw) register accessor: an alias for `Reg<P3SELC_SPEC>`"]
62pub type P3SELC = crate::Reg<p3selc::P3SELC_SPEC>;
63#[doc = "Port 3 Complement Select"]
64pub mod p3selc;
65#[doc = "P3IES (rw) register accessor: an alias for `Reg<P3IES_SPEC>`"]
66pub type P3IES = crate::Reg<p3ies::P3IES_SPEC>;
67#[doc = "Port 3 Interrupt Edge Select"]
68pub mod p3ies;
69#[doc = "P3IE (rw) register accessor: an alias for `Reg<P3IE_SPEC>`"]
70pub type P3IE = crate::Reg<p3ie::P3IE_SPEC>;
71#[doc = "Port 3 Interrupt Enable"]
72pub mod p3ie;
73#[doc = "P3IFG (rw) register accessor: an alias for `Reg<P3IFG_SPEC>`"]
74pub type P3IFG = crate::Reg<p3ifg::P3IFG_SPEC>;
75#[doc = "Port 3 Interrupt Flag"]
76pub mod p3ifg;
77#[doc = "P3IV (rw) register accessor: an alias for `Reg<P3IV_SPEC>`"]
78pub type P3IV = crate::Reg<p3iv::P3IV_SPEC>;
79#[doc = "Port 3 Interrupt Vector Register"]
80pub mod p3iv;