1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - DMA Module Control 0"]
5 pub dmactl0: crate::Reg<dmactl0::DMACTL0_SPEC>,
6 #[doc = "0x02 - DMA Module Control 1"]
7 pub dmactl1: crate::Reg<dmactl1::DMACTL1_SPEC>,
8 #[doc = "0x04 - DMA Module Control 2"]
9 pub dmactl2: crate::Reg<dmactl2::DMACTL2_SPEC>,
10 #[doc = "0x06 - DMA Module Control 3"]
11 pub dmactl3: crate::Reg<dmactl3::DMACTL3_SPEC>,
12 #[doc = "0x08 - DMA Module Control 4"]
13 pub dmactl4: crate::Reg<dmactl4::DMACTL4_SPEC>,
14 _reserved5: [u8; 0x04],
15 #[doc = "0x0e - DMA Interrupt Vector Word"]
16 pub dmaiv: crate::Reg<dmaiv::DMAIV_SPEC>,
17 #[doc = "0x10 - DMA Channel 0 Control"]
18 pub dma0ctl: crate::Reg<dma0ctl::DMA0CTL_SPEC>,
19 #[doc = "0x12 - DMA Channel 0 Source Address"]
20 pub dma0sa: crate::Reg<dma0sa::DMA0SA_SPEC>,
21 #[doc = "0x16 - DMA Channel 0 Destination Address"]
22 pub dma0da: crate::Reg<dma0da::DMA0DA_SPEC>,
23 #[doc = "0x1a - DMA Channel 0 Transfer Size"]
24 pub dma0sz: crate::Reg<dma0sz::DMA0SZ_SPEC>,
25 _reserved10: [u8; 0x04],
26 #[doc = "0x20 - DMA Channel 1 Control"]
27 pub dma1ctl: crate::Reg<dma1ctl::DMA1CTL_SPEC>,
28 #[doc = "0x22 - DMA Channel 1 Source Address"]
29 pub dma1sa: crate::Reg<dma1sa::DMA1SA_SPEC>,
30 #[doc = "0x26 - DMA Channel 1 Destination Address"]
31 pub dma1da: crate::Reg<dma1da::DMA1DA_SPEC>,
32 #[doc = "0x2a - DMA Channel 1 Transfer Size"]
33 pub dma1sz: crate::Reg<dma1sz::DMA1SZ_SPEC>,
34 _reserved14: [u8; 0x04],
35 #[doc = "0x30 - DMA Channel 2 Control"]
36 pub dma2ctl: crate::Reg<dma2ctl::DMA2CTL_SPEC>,
37 #[doc = "0x32 - DMA Channel 2 Source Address"]
38 pub dma2sa: crate::Reg<dma2sa::DMA2SA_SPEC>,
39 #[doc = "0x36 - DMA Channel 2 Destination Address"]
40 pub dma2da: crate::Reg<dma2da::DMA2DA_SPEC>,
41 #[doc = "0x3a - DMA Channel 2 Transfer Size"]
42 pub dma2sz: crate::Reg<dma2sz::DMA2SZ_SPEC>,
43}
44#[doc = "DMACTL0 register accessor: an alias for `Reg<DMACTL0_SPEC>`"]
45pub type DMACTL0 = crate::Reg<dmactl0::DMACTL0_SPEC>;
46#[doc = "DMA Module Control 0"]
47pub mod dmactl0;
48#[doc = "DMACTL1 register accessor: an alias for `Reg<DMACTL1_SPEC>`"]
49pub type DMACTL1 = crate::Reg<dmactl1::DMACTL1_SPEC>;
50#[doc = "DMA Module Control 1"]
51pub mod dmactl1;
52#[doc = "DMACTL2 register accessor: an alias for `Reg<DMACTL2_SPEC>`"]
53pub type DMACTL2 = crate::Reg<dmactl2::DMACTL2_SPEC>;
54#[doc = "DMA Module Control 2"]
55pub mod dmactl2;
56#[doc = "DMACTL3 register accessor: an alias for `Reg<DMACTL3_SPEC>`"]
57pub type DMACTL3 = crate::Reg<dmactl3::DMACTL3_SPEC>;
58#[doc = "DMA Module Control 3"]
59pub mod dmactl3;
60#[doc = "DMACTL4 register accessor: an alias for `Reg<DMACTL4_SPEC>`"]
61pub type DMACTL4 = crate::Reg<dmactl4::DMACTL4_SPEC>;
62#[doc = "DMA Module Control 4"]
63pub mod dmactl4;
64#[doc = "DMAIV register accessor: an alias for `Reg<DMAIV_SPEC>`"]
65pub type DMAIV = crate::Reg<dmaiv::DMAIV_SPEC>;
66#[doc = "DMA Interrupt Vector Word"]
67pub mod dmaiv;
68#[doc = "DMA0CTL register accessor: an alias for `Reg<DMA0CTL_SPEC>`"]
69pub type DMA0CTL = crate::Reg<dma0ctl::DMA0CTL_SPEC>;
70#[doc = "DMA Channel 0 Control"]
71pub mod dma0ctl;
72#[doc = "DMA0SZ register accessor: an alias for `Reg<DMA0SZ_SPEC>`"]
73pub type DMA0SZ = crate::Reg<dma0sz::DMA0SZ_SPEC>;
74#[doc = "DMA Channel 0 Transfer Size"]
75pub mod dma0sz;
76#[doc = "DMA1CTL register accessor: an alias for `Reg<DMA1CTL_SPEC>`"]
77pub type DMA1CTL = crate::Reg<dma1ctl::DMA1CTL_SPEC>;
78#[doc = "DMA Channel 1 Control"]
79pub mod dma1ctl;
80#[doc = "DMA1SZ register accessor: an alias for `Reg<DMA1SZ_SPEC>`"]
81pub type DMA1SZ = crate::Reg<dma1sz::DMA1SZ_SPEC>;
82#[doc = "DMA Channel 1 Transfer Size"]
83pub mod dma1sz;
84#[doc = "DMA2CTL register accessor: an alias for `Reg<DMA2CTL_SPEC>`"]
85pub type DMA2CTL = crate::Reg<dma2ctl::DMA2CTL_SPEC>;
86#[doc = "DMA Channel 2 Control"]
87pub mod dma2ctl;
88#[doc = "DMA2SZ register accessor: an alias for `Reg<DMA2SZ_SPEC>`"]
89pub type DMA2SZ = crate::Reg<dma2sz::DMA2SZ_SPEC>;
90#[doc = "DMA Channel 2 Transfer Size"]
91pub mod dma2sz;
92#[doc = "DMA0SA register accessor: an alias for `Reg<DMA0SA_SPEC>`"]
93pub type DMA0SA = crate::Reg<dma0sa::DMA0SA_SPEC>;
94#[doc = "DMA Channel 0 Source Address"]
95pub mod dma0sa;
96#[doc = "DMA0DA register accessor: an alias for `Reg<DMA0DA_SPEC>`"]
97pub type DMA0DA = crate::Reg<dma0da::DMA0DA_SPEC>;
98#[doc = "DMA Channel 0 Destination Address"]
99pub mod dma0da;
100#[doc = "DMA1SA register accessor: an alias for `Reg<DMA1SA_SPEC>`"]
101pub type DMA1SA = crate::Reg<dma1sa::DMA1SA_SPEC>;
102#[doc = "DMA Channel 1 Source Address"]
103pub mod dma1sa;
104#[doc = "DMA1DA register accessor: an alias for `Reg<DMA1DA_SPEC>`"]
105pub type DMA1DA = crate::Reg<dma1da::DMA1DA_SPEC>;
106#[doc = "DMA Channel 1 Destination Address"]
107pub mod dma1da;
108#[doc = "DMA2SA register accessor: an alias for `Reg<DMA2SA_SPEC>`"]
109pub type DMA2SA = crate::Reg<dma2sa::DMA2SA_SPEC>;
110#[doc = "DMA Channel 2 Source Address"]
111pub mod dma2sa;
112#[doc = "DMA2DA register accessor: an alias for `Reg<DMA2DA_SPEC>`"]
113pub type DMA2DA = crate::Reg<dma2da::DMA2DA_SPEC>;
114#[doc = "DMA Channel 2 Destination Address"]
115pub mod dma2da;