msp430f5529/adc12/
adc12ctl1.rs

1#[doc = "Register `ADC12CTL1` reader"]
2pub struct R(crate::R<ADC12CTL1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ADC12CTL1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ADC12CTL1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ADC12CTL1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ADC12CTL1` writer"]
17pub struct W(crate::W<ADC12CTL1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ADC12CTL1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ADC12CTL1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ADC12CTL1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ADC12BUSY` reader - ADC12 Busy"]
38pub struct ADC12BUSY_R(crate::FieldReader<bool, bool>);
39impl ADC12BUSY_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: bool) -> Self {
42        ADC12BUSY_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for ADC12BUSY_R {
46    type Target = crate::FieldReader<bool, bool>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `ADC12BUSY` writer - ADC12 Busy"]
53pub struct ADC12BUSY_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> ADC12BUSY_W<'a> {
57    #[doc = r"Sets the field bit"]
58    #[inline(always)]
59    pub fn set_bit(self) -> &'a mut W {
60        self.bit(true)
61    }
62    #[doc = r"Clears the field bit"]
63    #[inline(always)]
64    pub fn clear_bit(self) -> &'a mut W {
65        self.bit(false)
66    }
67    #[doc = r"Writes raw bits to the field"]
68    #[inline(always)]
69    pub fn bit(self, value: bool) -> &'a mut W {
70        self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01);
71        self.w
72    }
73}
74#[doc = "ADC12 Conversion Sequence Select Bit: 0\n\nValue on reset: 0"]
75#[derive(Clone, Copy, Debug, PartialEq)]
76#[repr(u8)]
77pub enum ADC12CONSEQ_A {
78    #[doc = "0: ADC12 Conversion Sequence Select: 0"]
79    ADC12CONSEQ_0 = 0,
80    #[doc = "1: ADC12 Conversion Sequence Select: 1"]
81    ADC12CONSEQ_1 = 1,
82    #[doc = "2: ADC12 Conversion Sequence Select: 2"]
83    ADC12CONSEQ_2 = 2,
84    #[doc = "3: ADC12 Conversion Sequence Select: 3"]
85    ADC12CONSEQ_3 = 3,
86}
87impl From<ADC12CONSEQ_A> for u8 {
88    #[inline(always)]
89    fn from(variant: ADC12CONSEQ_A) -> Self {
90        variant as _
91    }
92}
93#[doc = "Field `ADC12CONSEQ` reader - ADC12 Conversion Sequence Select Bit: 0"]
94pub struct ADC12CONSEQ_R(crate::FieldReader<u8, ADC12CONSEQ_A>);
95impl ADC12CONSEQ_R {
96    #[inline(always)]
97    pub(crate) fn new(bits: u8) -> Self {
98        ADC12CONSEQ_R(crate::FieldReader::new(bits))
99    }
100    #[doc = r"Get enumerated values variant"]
101    #[inline(always)]
102    pub fn variant(&self) -> ADC12CONSEQ_A {
103        match self.bits {
104            0 => ADC12CONSEQ_A::ADC12CONSEQ_0,
105            1 => ADC12CONSEQ_A::ADC12CONSEQ_1,
106            2 => ADC12CONSEQ_A::ADC12CONSEQ_2,
107            3 => ADC12CONSEQ_A::ADC12CONSEQ_3,
108            _ => unreachable!(),
109        }
110    }
111    #[doc = "Checks if the value of the field is `ADC12CONSEQ_0`"]
112    #[inline(always)]
113    pub fn is_adc12conseq_0(&self) -> bool {
114        **self == ADC12CONSEQ_A::ADC12CONSEQ_0
115    }
116    #[doc = "Checks if the value of the field is `ADC12CONSEQ_1`"]
117    #[inline(always)]
118    pub fn is_adc12conseq_1(&self) -> bool {
119        **self == ADC12CONSEQ_A::ADC12CONSEQ_1
120    }
121    #[doc = "Checks if the value of the field is `ADC12CONSEQ_2`"]
122    #[inline(always)]
123    pub fn is_adc12conseq_2(&self) -> bool {
124        **self == ADC12CONSEQ_A::ADC12CONSEQ_2
125    }
126    #[doc = "Checks if the value of the field is `ADC12CONSEQ_3`"]
127    #[inline(always)]
128    pub fn is_adc12conseq_3(&self) -> bool {
129        **self == ADC12CONSEQ_A::ADC12CONSEQ_3
130    }
131}
132impl core::ops::Deref for ADC12CONSEQ_R {
133    type Target = crate::FieldReader<u8, ADC12CONSEQ_A>;
134    #[inline(always)]
135    fn deref(&self) -> &Self::Target {
136        &self.0
137    }
138}
139#[doc = "Field `ADC12CONSEQ` writer - ADC12 Conversion Sequence Select Bit: 0"]
140pub struct ADC12CONSEQ_W<'a> {
141    w: &'a mut W,
142}
143impl<'a> ADC12CONSEQ_W<'a> {
144    #[doc = r"Writes `variant` to the field"]
145    #[inline(always)]
146    pub fn variant(self, variant: ADC12CONSEQ_A) -> &'a mut W {
147        self.bits(variant.into())
148    }
149    #[doc = "ADC12 Conversion Sequence Select: 0"]
150    #[inline(always)]
151    pub fn adc12conseq_0(self) -> &'a mut W {
152        self.variant(ADC12CONSEQ_A::ADC12CONSEQ_0)
153    }
154    #[doc = "ADC12 Conversion Sequence Select: 1"]
155    #[inline(always)]
156    pub fn adc12conseq_1(self) -> &'a mut W {
157        self.variant(ADC12CONSEQ_A::ADC12CONSEQ_1)
158    }
159    #[doc = "ADC12 Conversion Sequence Select: 2"]
160    #[inline(always)]
161    pub fn adc12conseq_2(self) -> &'a mut W {
162        self.variant(ADC12CONSEQ_A::ADC12CONSEQ_2)
163    }
164    #[doc = "ADC12 Conversion Sequence Select: 3"]
165    #[inline(always)]
166    pub fn adc12conseq_3(self) -> &'a mut W {
167        self.variant(ADC12CONSEQ_A::ADC12CONSEQ_3)
168    }
169    #[doc = r"Writes raw bits to the field"]
170    #[inline(always)]
171    pub fn bits(self, value: u8) -> &'a mut W {
172        self.w.bits = (self.w.bits & !(0x03 << 1)) | ((value as u16 & 0x03) << 1);
173        self.w
174    }
175}
176#[doc = "ADC12 Clock Source Select Bit: 0\n\nValue on reset: 0"]
177#[derive(Clone, Copy, Debug, PartialEq)]
178#[repr(u8)]
179pub enum ADC12SSEL_A {
180    #[doc = "0: ADC12 Clock Source Select: 0"]
181    ADC12SSEL_0 = 0,
182    #[doc = "1: ADC12 Clock Source Select: 1"]
183    ADC12SSEL_1 = 1,
184    #[doc = "2: ADC12 Clock Source Select: 2"]
185    ADC12SSEL_2 = 2,
186    #[doc = "3: ADC12 Clock Source Select: 3"]
187    ADC12SSEL_3 = 3,
188}
189impl From<ADC12SSEL_A> for u8 {
190    #[inline(always)]
191    fn from(variant: ADC12SSEL_A) -> Self {
192        variant as _
193    }
194}
195#[doc = "Field `ADC12SSEL` reader - ADC12 Clock Source Select Bit: 0"]
196pub struct ADC12SSEL_R(crate::FieldReader<u8, ADC12SSEL_A>);
197impl ADC12SSEL_R {
198    #[inline(always)]
199    pub(crate) fn new(bits: u8) -> Self {
200        ADC12SSEL_R(crate::FieldReader::new(bits))
201    }
202    #[doc = r"Get enumerated values variant"]
203    #[inline(always)]
204    pub fn variant(&self) -> ADC12SSEL_A {
205        match self.bits {
206            0 => ADC12SSEL_A::ADC12SSEL_0,
207            1 => ADC12SSEL_A::ADC12SSEL_1,
208            2 => ADC12SSEL_A::ADC12SSEL_2,
209            3 => ADC12SSEL_A::ADC12SSEL_3,
210            _ => unreachable!(),
211        }
212    }
213    #[doc = "Checks if the value of the field is `ADC12SSEL_0`"]
214    #[inline(always)]
215    pub fn is_adc12ssel_0(&self) -> bool {
216        **self == ADC12SSEL_A::ADC12SSEL_0
217    }
218    #[doc = "Checks if the value of the field is `ADC12SSEL_1`"]
219    #[inline(always)]
220    pub fn is_adc12ssel_1(&self) -> bool {
221        **self == ADC12SSEL_A::ADC12SSEL_1
222    }
223    #[doc = "Checks if the value of the field is `ADC12SSEL_2`"]
224    #[inline(always)]
225    pub fn is_adc12ssel_2(&self) -> bool {
226        **self == ADC12SSEL_A::ADC12SSEL_2
227    }
228    #[doc = "Checks if the value of the field is `ADC12SSEL_3`"]
229    #[inline(always)]
230    pub fn is_adc12ssel_3(&self) -> bool {
231        **self == ADC12SSEL_A::ADC12SSEL_3
232    }
233}
234impl core::ops::Deref for ADC12SSEL_R {
235    type Target = crate::FieldReader<u8, ADC12SSEL_A>;
236    #[inline(always)]
237    fn deref(&self) -> &Self::Target {
238        &self.0
239    }
240}
241#[doc = "Field `ADC12SSEL` writer - ADC12 Clock Source Select Bit: 0"]
242pub struct ADC12SSEL_W<'a> {
243    w: &'a mut W,
244}
245impl<'a> ADC12SSEL_W<'a> {
246    #[doc = r"Writes `variant` to the field"]
247    #[inline(always)]
248    pub fn variant(self, variant: ADC12SSEL_A) -> &'a mut W {
249        self.bits(variant.into())
250    }
251    #[doc = "ADC12 Clock Source Select: 0"]
252    #[inline(always)]
253    pub fn adc12ssel_0(self) -> &'a mut W {
254        self.variant(ADC12SSEL_A::ADC12SSEL_0)
255    }
256    #[doc = "ADC12 Clock Source Select: 1"]
257    #[inline(always)]
258    pub fn adc12ssel_1(self) -> &'a mut W {
259        self.variant(ADC12SSEL_A::ADC12SSEL_1)
260    }
261    #[doc = "ADC12 Clock Source Select: 2"]
262    #[inline(always)]
263    pub fn adc12ssel_2(self) -> &'a mut W {
264        self.variant(ADC12SSEL_A::ADC12SSEL_2)
265    }
266    #[doc = "ADC12 Clock Source Select: 3"]
267    #[inline(always)]
268    pub fn adc12ssel_3(self) -> &'a mut W {
269        self.variant(ADC12SSEL_A::ADC12SSEL_3)
270    }
271    #[doc = r"Writes raw bits to the field"]
272    #[inline(always)]
273    pub fn bits(self, value: u8) -> &'a mut W {
274        self.w.bits = (self.w.bits & !(0x03 << 3)) | ((value as u16 & 0x03) << 3);
275        self.w
276    }
277}
278#[doc = "ADC12 Clock Divider Select Bit: 0\n\nValue on reset: 0"]
279#[derive(Clone, Copy, Debug, PartialEq)]
280#[repr(u8)]
281pub enum ADC12DIV_A {
282    #[doc = "0: ADC12 Clock Divider Select: 0"]
283    ADC12DIV_0 = 0,
284    #[doc = "1: ADC12 Clock Divider Select: 1"]
285    ADC12DIV_1 = 1,
286    #[doc = "2: ADC12 Clock Divider Select: 2"]
287    ADC12DIV_2 = 2,
288    #[doc = "3: ADC12 Clock Divider Select: 3"]
289    ADC12DIV_3 = 3,
290    #[doc = "4: ADC12 Clock Divider Select: 4"]
291    ADC12DIV_4 = 4,
292    #[doc = "5: ADC12 Clock Divider Select: 5"]
293    ADC12DIV_5 = 5,
294    #[doc = "6: ADC12 Clock Divider Select: 6"]
295    ADC12DIV_6 = 6,
296    #[doc = "7: ADC12 Clock Divider Select: 7"]
297    ADC12DIV_7 = 7,
298}
299impl From<ADC12DIV_A> for u8 {
300    #[inline(always)]
301    fn from(variant: ADC12DIV_A) -> Self {
302        variant as _
303    }
304}
305#[doc = "Field `ADC12DIV` reader - ADC12 Clock Divider Select Bit: 0"]
306pub struct ADC12DIV_R(crate::FieldReader<u8, ADC12DIV_A>);
307impl ADC12DIV_R {
308    #[inline(always)]
309    pub(crate) fn new(bits: u8) -> Self {
310        ADC12DIV_R(crate::FieldReader::new(bits))
311    }
312    #[doc = r"Get enumerated values variant"]
313    #[inline(always)]
314    pub fn variant(&self) -> ADC12DIV_A {
315        match self.bits {
316            0 => ADC12DIV_A::ADC12DIV_0,
317            1 => ADC12DIV_A::ADC12DIV_1,
318            2 => ADC12DIV_A::ADC12DIV_2,
319            3 => ADC12DIV_A::ADC12DIV_3,
320            4 => ADC12DIV_A::ADC12DIV_4,
321            5 => ADC12DIV_A::ADC12DIV_5,
322            6 => ADC12DIV_A::ADC12DIV_6,
323            7 => ADC12DIV_A::ADC12DIV_7,
324            _ => unreachable!(),
325        }
326    }
327    #[doc = "Checks if the value of the field is `ADC12DIV_0`"]
328    #[inline(always)]
329    pub fn is_adc12div_0(&self) -> bool {
330        **self == ADC12DIV_A::ADC12DIV_0
331    }
332    #[doc = "Checks if the value of the field is `ADC12DIV_1`"]
333    #[inline(always)]
334    pub fn is_adc12div_1(&self) -> bool {
335        **self == ADC12DIV_A::ADC12DIV_1
336    }
337    #[doc = "Checks if the value of the field is `ADC12DIV_2`"]
338    #[inline(always)]
339    pub fn is_adc12div_2(&self) -> bool {
340        **self == ADC12DIV_A::ADC12DIV_2
341    }
342    #[doc = "Checks if the value of the field is `ADC12DIV_3`"]
343    #[inline(always)]
344    pub fn is_adc12div_3(&self) -> bool {
345        **self == ADC12DIV_A::ADC12DIV_3
346    }
347    #[doc = "Checks if the value of the field is `ADC12DIV_4`"]
348    #[inline(always)]
349    pub fn is_adc12div_4(&self) -> bool {
350        **self == ADC12DIV_A::ADC12DIV_4
351    }
352    #[doc = "Checks if the value of the field is `ADC12DIV_5`"]
353    #[inline(always)]
354    pub fn is_adc12div_5(&self) -> bool {
355        **self == ADC12DIV_A::ADC12DIV_5
356    }
357    #[doc = "Checks if the value of the field is `ADC12DIV_6`"]
358    #[inline(always)]
359    pub fn is_adc12div_6(&self) -> bool {
360        **self == ADC12DIV_A::ADC12DIV_6
361    }
362    #[doc = "Checks if the value of the field is `ADC12DIV_7`"]
363    #[inline(always)]
364    pub fn is_adc12div_7(&self) -> bool {
365        **self == ADC12DIV_A::ADC12DIV_7
366    }
367}
368impl core::ops::Deref for ADC12DIV_R {
369    type Target = crate::FieldReader<u8, ADC12DIV_A>;
370    #[inline(always)]
371    fn deref(&self) -> &Self::Target {
372        &self.0
373    }
374}
375#[doc = "Field `ADC12DIV` writer - ADC12 Clock Divider Select Bit: 0"]
376pub struct ADC12DIV_W<'a> {
377    w: &'a mut W,
378}
379impl<'a> ADC12DIV_W<'a> {
380    #[doc = r"Writes `variant` to the field"]
381    #[inline(always)]
382    pub fn variant(self, variant: ADC12DIV_A) -> &'a mut W {
383        self.bits(variant.into())
384    }
385    #[doc = "ADC12 Clock Divider Select: 0"]
386    #[inline(always)]
387    pub fn adc12div_0(self) -> &'a mut W {
388        self.variant(ADC12DIV_A::ADC12DIV_0)
389    }
390    #[doc = "ADC12 Clock Divider Select: 1"]
391    #[inline(always)]
392    pub fn adc12div_1(self) -> &'a mut W {
393        self.variant(ADC12DIV_A::ADC12DIV_1)
394    }
395    #[doc = "ADC12 Clock Divider Select: 2"]
396    #[inline(always)]
397    pub fn adc12div_2(self) -> &'a mut W {
398        self.variant(ADC12DIV_A::ADC12DIV_2)
399    }
400    #[doc = "ADC12 Clock Divider Select: 3"]
401    #[inline(always)]
402    pub fn adc12div_3(self) -> &'a mut W {
403        self.variant(ADC12DIV_A::ADC12DIV_3)
404    }
405    #[doc = "ADC12 Clock Divider Select: 4"]
406    #[inline(always)]
407    pub fn adc12div_4(self) -> &'a mut W {
408        self.variant(ADC12DIV_A::ADC12DIV_4)
409    }
410    #[doc = "ADC12 Clock Divider Select: 5"]
411    #[inline(always)]
412    pub fn adc12div_5(self) -> &'a mut W {
413        self.variant(ADC12DIV_A::ADC12DIV_5)
414    }
415    #[doc = "ADC12 Clock Divider Select: 6"]
416    #[inline(always)]
417    pub fn adc12div_6(self) -> &'a mut W {
418        self.variant(ADC12DIV_A::ADC12DIV_6)
419    }
420    #[doc = "ADC12 Clock Divider Select: 7"]
421    #[inline(always)]
422    pub fn adc12div_7(self) -> &'a mut W {
423        self.variant(ADC12DIV_A::ADC12DIV_7)
424    }
425    #[doc = r"Writes raw bits to the field"]
426    #[inline(always)]
427    pub fn bits(self, value: u8) -> &'a mut W {
428        self.w.bits = (self.w.bits & !(0x07 << 5)) | ((value as u16 & 0x07) << 5);
429        self.w
430    }
431}
432#[doc = "Field `ADC12ISSH` reader - ADC12 Invert Sample Hold Signal"]
433pub struct ADC12ISSH_R(crate::FieldReader<bool, bool>);
434impl ADC12ISSH_R {
435    #[inline(always)]
436    pub(crate) fn new(bits: bool) -> Self {
437        ADC12ISSH_R(crate::FieldReader::new(bits))
438    }
439}
440impl core::ops::Deref for ADC12ISSH_R {
441    type Target = crate::FieldReader<bool, bool>;
442    #[inline(always)]
443    fn deref(&self) -> &Self::Target {
444        &self.0
445    }
446}
447#[doc = "Field `ADC12ISSH` writer - ADC12 Invert Sample Hold Signal"]
448pub struct ADC12ISSH_W<'a> {
449    w: &'a mut W,
450}
451impl<'a> ADC12ISSH_W<'a> {
452    #[doc = r"Sets the field bit"]
453    #[inline(always)]
454    pub fn set_bit(self) -> &'a mut W {
455        self.bit(true)
456    }
457    #[doc = r"Clears the field bit"]
458    #[inline(always)]
459    pub fn clear_bit(self) -> &'a mut W {
460        self.bit(false)
461    }
462    #[doc = r"Writes raw bits to the field"]
463    #[inline(always)]
464    pub fn bit(self, value: bool) -> &'a mut W {
465        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8);
466        self.w
467    }
468}
469#[doc = "Field `ADC12SHP` reader - ADC12 Sample/Hold Pulse Mode"]
470pub struct ADC12SHP_R(crate::FieldReader<bool, bool>);
471impl ADC12SHP_R {
472    #[inline(always)]
473    pub(crate) fn new(bits: bool) -> Self {
474        ADC12SHP_R(crate::FieldReader::new(bits))
475    }
476}
477impl core::ops::Deref for ADC12SHP_R {
478    type Target = crate::FieldReader<bool, bool>;
479    #[inline(always)]
480    fn deref(&self) -> &Self::Target {
481        &self.0
482    }
483}
484#[doc = "Field `ADC12SHP` writer - ADC12 Sample/Hold Pulse Mode"]
485pub struct ADC12SHP_W<'a> {
486    w: &'a mut W,
487}
488impl<'a> ADC12SHP_W<'a> {
489    #[doc = r"Sets the field bit"]
490    #[inline(always)]
491    pub fn set_bit(self) -> &'a mut W {
492        self.bit(true)
493    }
494    #[doc = r"Clears the field bit"]
495    #[inline(always)]
496    pub fn clear_bit(self) -> &'a mut W {
497        self.bit(false)
498    }
499    #[doc = r"Writes raw bits to the field"]
500    #[inline(always)]
501    pub fn bit(self, value: bool) -> &'a mut W {
502        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9);
503        self.w
504    }
505}
506#[doc = "ADC12 Sample/Hold Source Bit: 0\n\nValue on reset: 0"]
507#[derive(Clone, Copy, Debug, PartialEq)]
508#[repr(u8)]
509pub enum ADC12SHS_A {
510    #[doc = "0: ADC12 Sample/Hold Source: 0"]
511    ADC12SHS_0 = 0,
512    #[doc = "1: ADC12 Sample/Hold Source: 1"]
513    ADC12SHS_1 = 1,
514    #[doc = "2: ADC12 Sample/Hold Source: 2"]
515    ADC12SHS_2 = 2,
516    #[doc = "3: ADC12 Sample/Hold Source: 3"]
517    ADC12SHS_3 = 3,
518}
519impl From<ADC12SHS_A> for u8 {
520    #[inline(always)]
521    fn from(variant: ADC12SHS_A) -> Self {
522        variant as _
523    }
524}
525#[doc = "Field `ADC12SHS` reader - ADC12 Sample/Hold Source Bit: 0"]
526pub struct ADC12SHS_R(crate::FieldReader<u8, ADC12SHS_A>);
527impl ADC12SHS_R {
528    #[inline(always)]
529    pub(crate) fn new(bits: u8) -> Self {
530        ADC12SHS_R(crate::FieldReader::new(bits))
531    }
532    #[doc = r"Get enumerated values variant"]
533    #[inline(always)]
534    pub fn variant(&self) -> ADC12SHS_A {
535        match self.bits {
536            0 => ADC12SHS_A::ADC12SHS_0,
537            1 => ADC12SHS_A::ADC12SHS_1,
538            2 => ADC12SHS_A::ADC12SHS_2,
539            3 => ADC12SHS_A::ADC12SHS_3,
540            _ => unreachable!(),
541        }
542    }
543    #[doc = "Checks if the value of the field is `ADC12SHS_0`"]
544    #[inline(always)]
545    pub fn is_adc12shs_0(&self) -> bool {
546        **self == ADC12SHS_A::ADC12SHS_0
547    }
548    #[doc = "Checks if the value of the field is `ADC12SHS_1`"]
549    #[inline(always)]
550    pub fn is_adc12shs_1(&self) -> bool {
551        **self == ADC12SHS_A::ADC12SHS_1
552    }
553    #[doc = "Checks if the value of the field is `ADC12SHS_2`"]
554    #[inline(always)]
555    pub fn is_adc12shs_2(&self) -> bool {
556        **self == ADC12SHS_A::ADC12SHS_2
557    }
558    #[doc = "Checks if the value of the field is `ADC12SHS_3`"]
559    #[inline(always)]
560    pub fn is_adc12shs_3(&self) -> bool {
561        **self == ADC12SHS_A::ADC12SHS_3
562    }
563}
564impl core::ops::Deref for ADC12SHS_R {
565    type Target = crate::FieldReader<u8, ADC12SHS_A>;
566    #[inline(always)]
567    fn deref(&self) -> &Self::Target {
568        &self.0
569    }
570}
571#[doc = "Field `ADC12SHS` writer - ADC12 Sample/Hold Source Bit: 0"]
572pub struct ADC12SHS_W<'a> {
573    w: &'a mut W,
574}
575impl<'a> ADC12SHS_W<'a> {
576    #[doc = r"Writes `variant` to the field"]
577    #[inline(always)]
578    pub fn variant(self, variant: ADC12SHS_A) -> &'a mut W {
579        self.bits(variant.into())
580    }
581    #[doc = "ADC12 Sample/Hold Source: 0"]
582    #[inline(always)]
583    pub fn adc12shs_0(self) -> &'a mut W {
584        self.variant(ADC12SHS_A::ADC12SHS_0)
585    }
586    #[doc = "ADC12 Sample/Hold Source: 1"]
587    #[inline(always)]
588    pub fn adc12shs_1(self) -> &'a mut W {
589        self.variant(ADC12SHS_A::ADC12SHS_1)
590    }
591    #[doc = "ADC12 Sample/Hold Source: 2"]
592    #[inline(always)]
593    pub fn adc12shs_2(self) -> &'a mut W {
594        self.variant(ADC12SHS_A::ADC12SHS_2)
595    }
596    #[doc = "ADC12 Sample/Hold Source: 3"]
597    #[inline(always)]
598    pub fn adc12shs_3(self) -> &'a mut W {
599        self.variant(ADC12SHS_A::ADC12SHS_3)
600    }
601    #[doc = r"Writes raw bits to the field"]
602    #[inline(always)]
603    pub fn bits(self, value: u8) -> &'a mut W {
604        self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u16 & 0x03) << 10);
605        self.w
606    }
607}
608#[doc = "ADC12 Conversion Start Address Bit: 0\n\nValue on reset: 0"]
609#[derive(Clone, Copy, Debug, PartialEq)]
610#[repr(u8)]
611pub enum ADC12CSTARTADD_A {
612    #[doc = "0: ADC12 Conversion Start Address: 0"]
613    ADC12CSTARTADD_0 = 0,
614    #[doc = "1: ADC12 Conversion Start Address: 1"]
615    ADC12CSTARTADD_1 = 1,
616    #[doc = "2: ADC12 Conversion Start Address: 2"]
617    ADC12CSTARTADD_2 = 2,
618    #[doc = "3: ADC12 Conversion Start Address: 3"]
619    ADC12CSTARTADD_3 = 3,
620    #[doc = "4: ADC12 Conversion Start Address: 4"]
621    ADC12CSTARTADD_4 = 4,
622    #[doc = "5: ADC12 Conversion Start Address: 5"]
623    ADC12CSTARTADD_5 = 5,
624    #[doc = "6: ADC12 Conversion Start Address: 6"]
625    ADC12CSTARTADD_6 = 6,
626    #[doc = "7: ADC12 Conversion Start Address: 7"]
627    ADC12CSTARTADD_7 = 7,
628    #[doc = "8: ADC12 Conversion Start Address: 8"]
629    ADC12CSTARTADD_8 = 8,
630    #[doc = "9: ADC12 Conversion Start Address: 9"]
631    ADC12CSTARTADD_9 = 9,
632    #[doc = "10: ADC12 Conversion Start Address: 10"]
633    ADC12CSTARTADD_10 = 10,
634    #[doc = "11: ADC12 Conversion Start Address: 11"]
635    ADC12CSTARTADD_11 = 11,
636    #[doc = "12: ADC12 Conversion Start Address: 12"]
637    ADC12CSTARTADD_12 = 12,
638    #[doc = "13: ADC12 Conversion Start Address: 13"]
639    ADC12CSTARTADD_13 = 13,
640    #[doc = "14: ADC12 Conversion Start Address: 14"]
641    ADC12CSTARTADD_14 = 14,
642    #[doc = "15: ADC12 Conversion Start Address: 15"]
643    ADC12CSTARTADD_15 = 15,
644}
645impl From<ADC12CSTARTADD_A> for u8 {
646    #[inline(always)]
647    fn from(variant: ADC12CSTARTADD_A) -> Self {
648        variant as _
649    }
650}
651#[doc = "Field `ADC12CSTARTADD` reader - ADC12 Conversion Start Address Bit: 0"]
652pub struct ADC12CSTARTADD_R(crate::FieldReader<u8, ADC12CSTARTADD_A>);
653impl ADC12CSTARTADD_R {
654    #[inline(always)]
655    pub(crate) fn new(bits: u8) -> Self {
656        ADC12CSTARTADD_R(crate::FieldReader::new(bits))
657    }
658    #[doc = r"Get enumerated values variant"]
659    #[inline(always)]
660    pub fn variant(&self) -> ADC12CSTARTADD_A {
661        match self.bits {
662            0 => ADC12CSTARTADD_A::ADC12CSTARTADD_0,
663            1 => ADC12CSTARTADD_A::ADC12CSTARTADD_1,
664            2 => ADC12CSTARTADD_A::ADC12CSTARTADD_2,
665            3 => ADC12CSTARTADD_A::ADC12CSTARTADD_3,
666            4 => ADC12CSTARTADD_A::ADC12CSTARTADD_4,
667            5 => ADC12CSTARTADD_A::ADC12CSTARTADD_5,
668            6 => ADC12CSTARTADD_A::ADC12CSTARTADD_6,
669            7 => ADC12CSTARTADD_A::ADC12CSTARTADD_7,
670            8 => ADC12CSTARTADD_A::ADC12CSTARTADD_8,
671            9 => ADC12CSTARTADD_A::ADC12CSTARTADD_9,
672            10 => ADC12CSTARTADD_A::ADC12CSTARTADD_10,
673            11 => ADC12CSTARTADD_A::ADC12CSTARTADD_11,
674            12 => ADC12CSTARTADD_A::ADC12CSTARTADD_12,
675            13 => ADC12CSTARTADD_A::ADC12CSTARTADD_13,
676            14 => ADC12CSTARTADD_A::ADC12CSTARTADD_14,
677            15 => ADC12CSTARTADD_A::ADC12CSTARTADD_15,
678            _ => unreachable!(),
679        }
680    }
681    #[doc = "Checks if the value of the field is `ADC12CSTARTADD_0`"]
682    #[inline(always)]
683    pub fn is_adc12cstartadd_0(&self) -> bool {
684        **self == ADC12CSTARTADD_A::ADC12CSTARTADD_0
685    }
686    #[doc = "Checks if the value of the field is `ADC12CSTARTADD_1`"]
687    #[inline(always)]
688    pub fn is_adc12cstartadd_1(&self) -> bool {
689        **self == ADC12CSTARTADD_A::ADC12CSTARTADD_1
690    }
691    #[doc = "Checks if the value of the field is `ADC12CSTARTADD_2`"]
692    #[inline(always)]
693    pub fn is_adc12cstartadd_2(&self) -> bool {
694        **self == ADC12CSTARTADD_A::ADC12CSTARTADD_2
695    }
696    #[doc = "Checks if the value of the field is `ADC12CSTARTADD_3`"]
697    #[inline(always)]
698    pub fn is_adc12cstartadd_3(&self) -> bool {
699        **self == ADC12CSTARTADD_A::ADC12CSTARTADD_3
700    }
701    #[doc = "Checks if the value of the field is `ADC12CSTARTADD_4`"]
702    #[inline(always)]
703    pub fn is_adc12cstartadd_4(&self) -> bool {
704        **self == ADC12CSTARTADD_A::ADC12CSTARTADD_4
705    }
706    #[doc = "Checks if the value of the field is `ADC12CSTARTADD_5`"]
707    #[inline(always)]
708    pub fn is_adc12cstartadd_5(&self) -> bool {
709        **self == ADC12CSTARTADD_A::ADC12CSTARTADD_5
710    }
711    #[doc = "Checks if the value of the field is `ADC12CSTARTADD_6`"]
712    #[inline(always)]
713    pub fn is_adc12cstartadd_6(&self) -> bool {
714        **self == ADC12CSTARTADD_A::ADC12CSTARTADD_6
715    }
716    #[doc = "Checks if the value of the field is `ADC12CSTARTADD_7`"]
717    #[inline(always)]
718    pub fn is_adc12cstartadd_7(&self) -> bool {
719        **self == ADC12CSTARTADD_A::ADC12CSTARTADD_7
720    }
721    #[doc = "Checks if the value of the field is `ADC12CSTARTADD_8`"]
722    #[inline(always)]
723    pub fn is_adc12cstartadd_8(&self) -> bool {
724        **self == ADC12CSTARTADD_A::ADC12CSTARTADD_8
725    }
726    #[doc = "Checks if the value of the field is `ADC12CSTARTADD_9`"]
727    #[inline(always)]
728    pub fn is_adc12cstartadd_9(&self) -> bool {
729        **self == ADC12CSTARTADD_A::ADC12CSTARTADD_9
730    }
731    #[doc = "Checks if the value of the field is `ADC12CSTARTADD_10`"]
732    #[inline(always)]
733    pub fn is_adc12cstartadd_10(&self) -> bool {
734        **self == ADC12CSTARTADD_A::ADC12CSTARTADD_10
735    }
736    #[doc = "Checks if the value of the field is `ADC12CSTARTADD_11`"]
737    #[inline(always)]
738    pub fn is_adc12cstartadd_11(&self) -> bool {
739        **self == ADC12CSTARTADD_A::ADC12CSTARTADD_11
740    }
741    #[doc = "Checks if the value of the field is `ADC12CSTARTADD_12`"]
742    #[inline(always)]
743    pub fn is_adc12cstartadd_12(&self) -> bool {
744        **self == ADC12CSTARTADD_A::ADC12CSTARTADD_12
745    }
746    #[doc = "Checks if the value of the field is `ADC12CSTARTADD_13`"]
747    #[inline(always)]
748    pub fn is_adc12cstartadd_13(&self) -> bool {
749        **self == ADC12CSTARTADD_A::ADC12CSTARTADD_13
750    }
751    #[doc = "Checks if the value of the field is `ADC12CSTARTADD_14`"]
752    #[inline(always)]
753    pub fn is_adc12cstartadd_14(&self) -> bool {
754        **self == ADC12CSTARTADD_A::ADC12CSTARTADD_14
755    }
756    #[doc = "Checks if the value of the field is `ADC12CSTARTADD_15`"]
757    #[inline(always)]
758    pub fn is_adc12cstartadd_15(&self) -> bool {
759        **self == ADC12CSTARTADD_A::ADC12CSTARTADD_15
760    }
761}
762impl core::ops::Deref for ADC12CSTARTADD_R {
763    type Target = crate::FieldReader<u8, ADC12CSTARTADD_A>;
764    #[inline(always)]
765    fn deref(&self) -> &Self::Target {
766        &self.0
767    }
768}
769#[doc = "Field `ADC12CSTARTADD` writer - ADC12 Conversion Start Address Bit: 0"]
770pub struct ADC12CSTARTADD_W<'a> {
771    w: &'a mut W,
772}
773impl<'a> ADC12CSTARTADD_W<'a> {
774    #[doc = r"Writes `variant` to the field"]
775    #[inline(always)]
776    pub fn variant(self, variant: ADC12CSTARTADD_A) -> &'a mut W {
777        self.bits(variant.into())
778    }
779    #[doc = "ADC12 Conversion Start Address: 0"]
780    #[inline(always)]
781    pub fn adc12cstartadd_0(self) -> &'a mut W {
782        self.variant(ADC12CSTARTADD_A::ADC12CSTARTADD_0)
783    }
784    #[doc = "ADC12 Conversion Start Address: 1"]
785    #[inline(always)]
786    pub fn adc12cstartadd_1(self) -> &'a mut W {
787        self.variant(ADC12CSTARTADD_A::ADC12CSTARTADD_1)
788    }
789    #[doc = "ADC12 Conversion Start Address: 2"]
790    #[inline(always)]
791    pub fn adc12cstartadd_2(self) -> &'a mut W {
792        self.variant(ADC12CSTARTADD_A::ADC12CSTARTADD_2)
793    }
794    #[doc = "ADC12 Conversion Start Address: 3"]
795    #[inline(always)]
796    pub fn adc12cstartadd_3(self) -> &'a mut W {
797        self.variant(ADC12CSTARTADD_A::ADC12CSTARTADD_3)
798    }
799    #[doc = "ADC12 Conversion Start Address: 4"]
800    #[inline(always)]
801    pub fn adc12cstartadd_4(self) -> &'a mut W {
802        self.variant(ADC12CSTARTADD_A::ADC12CSTARTADD_4)
803    }
804    #[doc = "ADC12 Conversion Start Address: 5"]
805    #[inline(always)]
806    pub fn adc12cstartadd_5(self) -> &'a mut W {
807        self.variant(ADC12CSTARTADD_A::ADC12CSTARTADD_5)
808    }
809    #[doc = "ADC12 Conversion Start Address: 6"]
810    #[inline(always)]
811    pub fn adc12cstartadd_6(self) -> &'a mut W {
812        self.variant(ADC12CSTARTADD_A::ADC12CSTARTADD_6)
813    }
814    #[doc = "ADC12 Conversion Start Address: 7"]
815    #[inline(always)]
816    pub fn adc12cstartadd_7(self) -> &'a mut W {
817        self.variant(ADC12CSTARTADD_A::ADC12CSTARTADD_7)
818    }
819    #[doc = "ADC12 Conversion Start Address: 8"]
820    #[inline(always)]
821    pub fn adc12cstartadd_8(self) -> &'a mut W {
822        self.variant(ADC12CSTARTADD_A::ADC12CSTARTADD_8)
823    }
824    #[doc = "ADC12 Conversion Start Address: 9"]
825    #[inline(always)]
826    pub fn adc12cstartadd_9(self) -> &'a mut W {
827        self.variant(ADC12CSTARTADD_A::ADC12CSTARTADD_9)
828    }
829    #[doc = "ADC12 Conversion Start Address: 10"]
830    #[inline(always)]
831    pub fn adc12cstartadd_10(self) -> &'a mut W {
832        self.variant(ADC12CSTARTADD_A::ADC12CSTARTADD_10)
833    }
834    #[doc = "ADC12 Conversion Start Address: 11"]
835    #[inline(always)]
836    pub fn adc12cstartadd_11(self) -> &'a mut W {
837        self.variant(ADC12CSTARTADD_A::ADC12CSTARTADD_11)
838    }
839    #[doc = "ADC12 Conversion Start Address: 12"]
840    #[inline(always)]
841    pub fn adc12cstartadd_12(self) -> &'a mut W {
842        self.variant(ADC12CSTARTADD_A::ADC12CSTARTADD_12)
843    }
844    #[doc = "ADC12 Conversion Start Address: 13"]
845    #[inline(always)]
846    pub fn adc12cstartadd_13(self) -> &'a mut W {
847        self.variant(ADC12CSTARTADD_A::ADC12CSTARTADD_13)
848    }
849    #[doc = "ADC12 Conversion Start Address: 14"]
850    #[inline(always)]
851    pub fn adc12cstartadd_14(self) -> &'a mut W {
852        self.variant(ADC12CSTARTADD_A::ADC12CSTARTADD_14)
853    }
854    #[doc = "ADC12 Conversion Start Address: 15"]
855    #[inline(always)]
856    pub fn adc12cstartadd_15(self) -> &'a mut W {
857        self.variant(ADC12CSTARTADD_A::ADC12CSTARTADD_15)
858    }
859    #[doc = r"Writes raw bits to the field"]
860    #[inline(always)]
861    pub fn bits(self, value: u8) -> &'a mut W {
862        self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u16 & 0x0f) << 12);
863        self.w
864    }
865}
866impl R {
867    #[doc = "Bit 0 - ADC12 Busy"]
868    #[inline(always)]
869    pub fn adc12busy(&self) -> ADC12BUSY_R {
870        ADC12BUSY_R::new((self.bits & 0x01) != 0)
871    }
872    #[doc = "Bits 1:2 - ADC12 Conversion Sequence Select Bit: 0"]
873    #[inline(always)]
874    pub fn adc12conseq(&self) -> ADC12CONSEQ_R {
875        ADC12CONSEQ_R::new(((self.bits >> 1) & 0x03) as u8)
876    }
877    #[doc = "Bits 3:4 - ADC12 Clock Source Select Bit: 0"]
878    #[inline(always)]
879    pub fn adc12ssel(&self) -> ADC12SSEL_R {
880        ADC12SSEL_R::new(((self.bits >> 3) & 0x03) as u8)
881    }
882    #[doc = "Bits 5:7 - ADC12 Clock Divider Select Bit: 0"]
883    #[inline(always)]
884    pub fn adc12div(&self) -> ADC12DIV_R {
885        ADC12DIV_R::new(((self.bits >> 5) & 0x07) as u8)
886    }
887    #[doc = "Bit 8 - ADC12 Invert Sample Hold Signal"]
888    #[inline(always)]
889    pub fn adc12issh(&self) -> ADC12ISSH_R {
890        ADC12ISSH_R::new(((self.bits >> 8) & 0x01) != 0)
891    }
892    #[doc = "Bit 9 - ADC12 Sample/Hold Pulse Mode"]
893    #[inline(always)]
894    pub fn adc12shp(&self) -> ADC12SHP_R {
895        ADC12SHP_R::new(((self.bits >> 9) & 0x01) != 0)
896    }
897    #[doc = "Bits 10:11 - ADC12 Sample/Hold Source Bit: 0"]
898    #[inline(always)]
899    pub fn adc12shs(&self) -> ADC12SHS_R {
900        ADC12SHS_R::new(((self.bits >> 10) & 0x03) as u8)
901    }
902    #[doc = "Bits 12:15 - ADC12 Conversion Start Address Bit: 0"]
903    #[inline(always)]
904    pub fn adc12cstartadd(&self) -> ADC12CSTARTADD_R {
905        ADC12CSTARTADD_R::new(((self.bits >> 12) & 0x0f) as u8)
906    }
907}
908impl W {
909    #[doc = "Bit 0 - ADC12 Busy"]
910    #[inline(always)]
911    pub fn adc12busy(&mut self) -> ADC12BUSY_W {
912        ADC12BUSY_W { w: self }
913    }
914    #[doc = "Bits 1:2 - ADC12 Conversion Sequence Select Bit: 0"]
915    #[inline(always)]
916    pub fn adc12conseq(&mut self) -> ADC12CONSEQ_W {
917        ADC12CONSEQ_W { w: self }
918    }
919    #[doc = "Bits 3:4 - ADC12 Clock Source Select Bit: 0"]
920    #[inline(always)]
921    pub fn adc12ssel(&mut self) -> ADC12SSEL_W {
922        ADC12SSEL_W { w: self }
923    }
924    #[doc = "Bits 5:7 - ADC12 Clock Divider Select Bit: 0"]
925    #[inline(always)]
926    pub fn adc12div(&mut self) -> ADC12DIV_W {
927        ADC12DIV_W { w: self }
928    }
929    #[doc = "Bit 8 - ADC12 Invert Sample Hold Signal"]
930    #[inline(always)]
931    pub fn adc12issh(&mut self) -> ADC12ISSH_W {
932        ADC12ISSH_W { w: self }
933    }
934    #[doc = "Bit 9 - ADC12 Sample/Hold Pulse Mode"]
935    #[inline(always)]
936    pub fn adc12shp(&mut self) -> ADC12SHP_W {
937        ADC12SHP_W { w: self }
938    }
939    #[doc = "Bits 10:11 - ADC12 Sample/Hold Source Bit: 0"]
940    #[inline(always)]
941    pub fn adc12shs(&mut self) -> ADC12SHS_W {
942        ADC12SHS_W { w: self }
943    }
944    #[doc = "Bits 12:15 - ADC12 Conversion Start Address Bit: 0"]
945    #[inline(always)]
946    pub fn adc12cstartadd(&mut self) -> ADC12CSTARTADD_W {
947        ADC12CSTARTADD_W { w: self }
948    }
949    #[doc = "Writes raw bits to the register."]
950    #[inline(always)]
951    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
952        self.0.bits(bits);
953        self
954    }
955}
956#[doc = "ADC12+ Control 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adc12ctl1](index.html) module"]
957pub struct ADC12CTL1_SPEC;
958impl crate::RegisterSpec for ADC12CTL1_SPEC {
959    type Ux = u16;
960}
961#[doc = "`read()` method returns [adc12ctl1::R](R) reader structure"]
962impl crate::Readable for ADC12CTL1_SPEC {
963    type Reader = R;
964}
965#[doc = "`write(|w| ..)` method takes [adc12ctl1::W](W) writer structure"]
966impl crate::Writable for ADC12CTL1_SPEC {
967    type Writer = W;
968}
969#[doc = "`reset()` method sets ADC12CTL1 to value 0"]
970impl crate::Resettable for ADC12CTL1_SPEC {
971    #[inline(always)]
972    fn reset_value() -> Self::Ux {
973        0
974    }
975}
msp430f5529/adc12/adc12ctl1.rs

msp430f5529/adc12/
adc12ctl1.rs
