msp430f5529/
usci_a0_spi_mode.rs

1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "0x00 - USCI A0 Control Register 1"]
5    pub uca0ctl1_spi: crate::Reg<uca0ctl1_spi::UCA0CTL1_SPI_SPEC>,
6    #[doc = "0x01 - USCI A0 Control Register 0"]
7    pub uca0ctl0_spi: crate::Reg<uca0ctl0_spi::UCA0CTL0_SPI_SPEC>,
8    _reserved2: [u8; 0x04],
9    #[doc = "0x06 - USCI A0 Baud Rate 0"]
10    pub uca0br0_spi: crate::Reg<uca0br0_spi::UCA0BR0_SPI_SPEC>,
11    #[doc = "0x07 - USCI A0 Baud Rate 1"]
12    pub uca0br1_spi: crate::Reg<uca0br1_spi::UCA0BR1_SPI_SPEC>,
13    #[doc = "0x08 - USCI A0 Modulation Control"]
14    pub uca0mctl_spi: crate::Reg<uca0mctl_spi::UCA0MCTL_SPI_SPEC>,
15    _reserved5: [u8; 0x01],
16    #[doc = "0x0a - USCI A0 Status Register"]
17    pub uca0stat_spi: crate::Reg<uca0stat_spi::UCA0STAT_SPI_SPEC>,
18    _reserved6: [u8; 0x01],
19    #[doc = "0x0c - USCI A0 Receive Buffer"]
20    pub uca0rxbuf_spi: crate::Reg<uca0rxbuf_spi::UCA0RXBUF_SPI_SPEC>,
21    _reserved7: [u8; 0x01],
22    #[doc = "0x0e - USCI A0 Transmit Buffer"]
23    pub uca0txbuf_spi: crate::Reg<uca0txbuf_spi::UCA0TXBUF_SPI_SPEC>,
24    _reserved8: [u8; 0x0d],
25    #[doc = "0x1c - USCI A0 Interrupt Enable Register"]
26    pub uca0ie_spi: crate::Reg<uca0ie_spi::UCA0IE_SPI_SPEC>,
27    #[doc = "0x1d - USCI A0 Interrupt Flags Register"]
28    pub uca0ifg_spi: crate::Reg<uca0ifg_spi::UCA0IFG_SPI_SPEC>,
29    #[doc = "0x1e - USCI A0 Interrupt Vector Register"]
30    pub uca0iv_spi: crate::Reg<uca0iv_spi::UCA0IV_SPI_SPEC>,
31}
32#[doc = "UCA0CTL1_SPI register accessor: an alias for `Reg<UCA0CTL1_SPI_SPEC>`"]
33pub type UCA0CTL1_SPI = crate::Reg<uca0ctl1_spi::UCA0CTL1_SPI_SPEC>;
34#[doc = "USCI A0 Control Register 1"]
35pub mod uca0ctl1_spi;
36#[doc = "UCA0CTL0_SPI register accessor: an alias for `Reg<UCA0CTL0_SPI_SPEC>`"]
37pub type UCA0CTL0_SPI = crate::Reg<uca0ctl0_spi::UCA0CTL0_SPI_SPEC>;
38#[doc = "USCI A0 Control Register 0"]
39pub mod uca0ctl0_spi;
40#[doc = "UCA0BR0_SPI register accessor: an alias for `Reg<UCA0BR0_SPI_SPEC>`"]
41pub type UCA0BR0_SPI = crate::Reg<uca0br0_spi::UCA0BR0_SPI_SPEC>;
42#[doc = "USCI A0 Baud Rate 0"]
43pub mod uca0br0_spi;
44#[doc = "UCA0BR1_SPI register accessor: an alias for `Reg<UCA0BR1_SPI_SPEC>`"]
45pub type UCA0BR1_SPI = crate::Reg<uca0br1_spi::UCA0BR1_SPI_SPEC>;
46#[doc = "USCI A0 Baud Rate 1"]
47pub mod uca0br1_spi;
48#[doc = "UCA0MCTL_SPI register accessor: an alias for `Reg<UCA0MCTL_SPI_SPEC>`"]
49pub type UCA0MCTL_SPI = crate::Reg<uca0mctl_spi::UCA0MCTL_SPI_SPEC>;
50#[doc = "USCI A0 Modulation Control"]
51pub mod uca0mctl_spi;
52#[doc = "UCA0STAT_SPI register accessor: an alias for `Reg<UCA0STAT_SPI_SPEC>`"]
53pub type UCA0STAT_SPI = crate::Reg<uca0stat_spi::UCA0STAT_SPI_SPEC>;
54#[doc = "USCI A0 Status Register"]
55pub mod uca0stat_spi;
56#[doc = "UCA0RXBUF_SPI register accessor: an alias for `Reg<UCA0RXBUF_SPI_SPEC>`"]
57pub type UCA0RXBUF_SPI = crate::Reg<uca0rxbuf_spi::UCA0RXBUF_SPI_SPEC>;
58#[doc = "USCI A0 Receive Buffer"]
59pub mod uca0rxbuf_spi;
60#[doc = "UCA0TXBUF_SPI register accessor: an alias for `Reg<UCA0TXBUF_SPI_SPEC>`"]
61pub type UCA0TXBUF_SPI = crate::Reg<uca0txbuf_spi::UCA0TXBUF_SPI_SPEC>;
62#[doc = "USCI A0 Transmit Buffer"]
63pub mod uca0txbuf_spi;
64#[doc = "UCA0IE_SPI register accessor: an alias for `Reg<UCA0IE_SPI_SPEC>`"]
65pub type UCA0IE_SPI = crate::Reg<uca0ie_spi::UCA0IE_SPI_SPEC>;
66#[doc = "USCI A0 Interrupt Enable Register"]
67pub mod uca0ie_spi;
68#[doc = "UCA0IFG_SPI register accessor: an alias for `Reg<UCA0IFG_SPI_SPEC>`"]
69pub type UCA0IFG_SPI = crate::Reg<uca0ifg_spi::UCA0IFG_SPI_SPEC>;
70#[doc = "USCI A0 Interrupt Flags Register"]
71pub mod uca0ifg_spi;
72#[doc = "UCA0IV_SPI register accessor: an alias for `Reg<UCA0IV_SPI_SPEC>`"]
73pub type UCA0IV_SPI = crate::Reg<uca0iv_spi::UCA0IV_SPI_SPEC>;
74#[doc = "USCI A0 Interrupt Vector Register"]
75pub mod uca0iv_spi;
msp430f5529/usci_a0_spi_mode.rs

msp430f5529/
usci_a0_spi_mode.rs
