msp430f5529/dma/
dma0ctl.rs

1#[doc = "Register `DMA0CTL` reader"]
2pub struct R(crate::R<DMA0CTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DMA0CTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DMA0CTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DMA0CTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DMA0CTL` writer"]
17pub struct W(crate::W<DMA0CTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DMA0CTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DMA0CTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DMA0CTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DMAREQ` reader - Initiate DMA transfer with DMATSEL"]
38pub struct DMAREQ_R(crate::FieldReader<bool, bool>);
39impl DMAREQ_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: bool) -> Self {
42        DMAREQ_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for DMAREQ_R {
46    type Target = crate::FieldReader<bool, bool>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `DMAREQ` writer - Initiate DMA transfer with DMATSEL"]
53pub struct DMAREQ_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> DMAREQ_W<'a> {
57    #[doc = r"Sets the field bit"]
58    #[inline(always)]
59    pub fn set_bit(self) -> &'a mut W {
60        self.bit(true)
61    }
62    #[doc = r"Clears the field bit"]
63    #[inline(always)]
64    pub fn clear_bit(self) -> &'a mut W {
65        self.bit(false)
66    }
67    #[doc = r"Writes raw bits to the field"]
68    #[inline(always)]
69    pub fn bit(self, value: bool) -> &'a mut W {
70        self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01);
71        self.w
72    }
73}
74#[doc = "Field `DMAABORT` reader - DMA transfer aborted by NMI"]
75pub struct DMAABORT_R(crate::FieldReader<bool, bool>);
76impl DMAABORT_R {
77    #[inline(always)]
78    pub(crate) fn new(bits: bool) -> Self {
79        DMAABORT_R(crate::FieldReader::new(bits))
80    }
81}
82impl core::ops::Deref for DMAABORT_R {
83    type Target = crate::FieldReader<bool, bool>;
84    #[inline(always)]
85    fn deref(&self) -> &Self::Target {
86        &self.0
87    }
88}
89#[doc = "Field `DMAABORT` writer - DMA transfer aborted by NMI"]
90pub struct DMAABORT_W<'a> {
91    w: &'a mut W,
92}
93impl<'a> DMAABORT_W<'a> {
94    #[doc = r"Sets the field bit"]
95    #[inline(always)]
96    pub fn set_bit(self) -> &'a mut W {
97        self.bit(true)
98    }
99    #[doc = r"Clears the field bit"]
100    #[inline(always)]
101    pub fn clear_bit(self) -> &'a mut W {
102        self.bit(false)
103    }
104    #[doc = r"Writes raw bits to the field"]
105    #[inline(always)]
106    pub fn bit(self, value: bool) -> &'a mut W {
107        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1);
108        self.w
109    }
110}
111#[doc = "Field `DMAIE` reader - DMA interrupt enable"]
112pub struct DMAIE_R(crate::FieldReader<bool, bool>);
113impl DMAIE_R {
114    #[inline(always)]
115    pub(crate) fn new(bits: bool) -> Self {
116        DMAIE_R(crate::FieldReader::new(bits))
117    }
118}
119impl core::ops::Deref for DMAIE_R {
120    type Target = crate::FieldReader<bool, bool>;
121    #[inline(always)]
122    fn deref(&self) -> &Self::Target {
123        &self.0
124    }
125}
126#[doc = "Field `DMAIE` writer - DMA interrupt enable"]
127pub struct DMAIE_W<'a> {
128    w: &'a mut W,
129}
130impl<'a> DMAIE_W<'a> {
131    #[doc = r"Sets the field bit"]
132    #[inline(always)]
133    pub fn set_bit(self) -> &'a mut W {
134        self.bit(true)
135    }
136    #[doc = r"Clears the field bit"]
137    #[inline(always)]
138    pub fn clear_bit(self) -> &'a mut W {
139        self.bit(false)
140    }
141    #[doc = r"Writes raw bits to the field"]
142    #[inline(always)]
143    pub fn bit(self, value: bool) -> &'a mut W {
144        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2);
145        self.w
146    }
147}
148#[doc = "Field `DMAIFG` reader - DMA interrupt flag"]
149pub struct DMAIFG_R(crate::FieldReader<bool, bool>);
150impl DMAIFG_R {
151    #[inline(always)]
152    pub(crate) fn new(bits: bool) -> Self {
153        DMAIFG_R(crate::FieldReader::new(bits))
154    }
155}
156impl core::ops::Deref for DMAIFG_R {
157    type Target = crate::FieldReader<bool, bool>;
158    #[inline(always)]
159    fn deref(&self) -> &Self::Target {
160        &self.0
161    }
162}
163#[doc = "Field `DMAIFG` writer - DMA interrupt flag"]
164pub struct DMAIFG_W<'a> {
165    w: &'a mut W,
166}
167impl<'a> DMAIFG_W<'a> {
168    #[doc = r"Sets the field bit"]
169    #[inline(always)]
170    pub fn set_bit(self) -> &'a mut W {
171        self.bit(true)
172    }
173    #[doc = r"Clears the field bit"]
174    #[inline(always)]
175    pub fn clear_bit(self) -> &'a mut W {
176        self.bit(false)
177    }
178    #[doc = r"Writes raw bits to the field"]
179    #[inline(always)]
180    pub fn bit(self, value: bool) -> &'a mut W {
181        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3);
182        self.w
183    }
184}
185#[doc = "Field `DMAEN` reader - DMA enable"]
186pub struct DMAEN_R(crate::FieldReader<bool, bool>);
187impl DMAEN_R {
188    #[inline(always)]
189    pub(crate) fn new(bits: bool) -> Self {
190        DMAEN_R(crate::FieldReader::new(bits))
191    }
192}
193impl core::ops::Deref for DMAEN_R {
194    type Target = crate::FieldReader<bool, bool>;
195    #[inline(always)]
196    fn deref(&self) -> &Self::Target {
197        &self.0
198    }
199}
200#[doc = "Field `DMAEN` writer - DMA enable"]
201pub struct DMAEN_W<'a> {
202    w: &'a mut W,
203}
204impl<'a> DMAEN_W<'a> {
205    #[doc = r"Sets the field bit"]
206    #[inline(always)]
207    pub fn set_bit(self) -> &'a mut W {
208        self.bit(true)
209    }
210    #[doc = r"Clears the field bit"]
211    #[inline(always)]
212    pub fn clear_bit(self) -> &'a mut W {
213        self.bit(false)
214    }
215    #[doc = r"Writes raw bits to the field"]
216    #[inline(always)]
217    pub fn bit(self, value: bool) -> &'a mut W {
218        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4);
219        self.w
220    }
221}
222#[doc = "Field `DMALEVEL` reader - DMA level sensitive trigger select"]
223pub struct DMALEVEL_R(crate::FieldReader<bool, bool>);
224impl DMALEVEL_R {
225    #[inline(always)]
226    pub(crate) fn new(bits: bool) -> Self {
227        DMALEVEL_R(crate::FieldReader::new(bits))
228    }
229}
230impl core::ops::Deref for DMALEVEL_R {
231    type Target = crate::FieldReader<bool, bool>;
232    #[inline(always)]
233    fn deref(&self) -> &Self::Target {
234        &self.0
235    }
236}
237#[doc = "Field `DMALEVEL` writer - DMA level sensitive trigger select"]
238pub struct DMALEVEL_W<'a> {
239    w: &'a mut W,
240}
241impl<'a> DMALEVEL_W<'a> {
242    #[doc = r"Sets the field bit"]
243    #[inline(always)]
244    pub fn set_bit(self) -> &'a mut W {
245        self.bit(true)
246    }
247    #[doc = r"Clears the field bit"]
248    #[inline(always)]
249    pub fn clear_bit(self) -> &'a mut W {
250        self.bit(false)
251    }
252    #[doc = r"Writes raw bits to the field"]
253    #[inline(always)]
254    pub fn bit(self, value: bool) -> &'a mut W {
255        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5);
256        self.w
257    }
258}
259#[doc = "Field `DMASRCBYTE` reader - DMA source byte"]
260pub struct DMASRCBYTE_R(crate::FieldReader<bool, bool>);
261impl DMASRCBYTE_R {
262    #[inline(always)]
263    pub(crate) fn new(bits: bool) -> Self {
264        DMASRCBYTE_R(crate::FieldReader::new(bits))
265    }
266}
267impl core::ops::Deref for DMASRCBYTE_R {
268    type Target = crate::FieldReader<bool, bool>;
269    #[inline(always)]
270    fn deref(&self) -> &Self::Target {
271        &self.0
272    }
273}
274#[doc = "Field `DMASRCBYTE` writer - DMA source byte"]
275pub struct DMASRCBYTE_W<'a> {
276    w: &'a mut W,
277}
278impl<'a> DMASRCBYTE_W<'a> {
279    #[doc = r"Sets the field bit"]
280    #[inline(always)]
281    pub fn set_bit(self) -> &'a mut W {
282        self.bit(true)
283    }
284    #[doc = r"Clears the field bit"]
285    #[inline(always)]
286    pub fn clear_bit(self) -> &'a mut W {
287        self.bit(false)
288    }
289    #[doc = r"Writes raw bits to the field"]
290    #[inline(always)]
291    pub fn bit(self, value: bool) -> &'a mut W {
292        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6);
293        self.w
294    }
295}
296#[doc = "Field `DMADSTBYTE` reader - DMA destination byte"]
297pub struct DMADSTBYTE_R(crate::FieldReader<bool, bool>);
298impl DMADSTBYTE_R {
299    #[inline(always)]
300    pub(crate) fn new(bits: bool) -> Self {
301        DMADSTBYTE_R(crate::FieldReader::new(bits))
302    }
303}
304impl core::ops::Deref for DMADSTBYTE_R {
305    type Target = crate::FieldReader<bool, bool>;
306    #[inline(always)]
307    fn deref(&self) -> &Self::Target {
308        &self.0
309    }
310}
311#[doc = "Field `DMADSTBYTE` writer - DMA destination byte"]
312pub struct DMADSTBYTE_W<'a> {
313    w: &'a mut W,
314}
315impl<'a> DMADSTBYTE_W<'a> {
316    #[doc = r"Sets the field bit"]
317    #[inline(always)]
318    pub fn set_bit(self) -> &'a mut W {
319        self.bit(true)
320    }
321    #[doc = r"Clears the field bit"]
322    #[inline(always)]
323    pub fn clear_bit(self) -> &'a mut W {
324        self.bit(false)
325    }
326    #[doc = r"Writes raw bits to the field"]
327    #[inline(always)]
328    pub fn bit(self, value: bool) -> &'a mut W {
329        self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7);
330        self.w
331    }
332}
333#[doc = "DMA source increment bit 0\n\nValue on reset: 0"]
334#[derive(Clone, Copy, Debug, PartialEq)]
335#[repr(u8)]
336pub enum DMASRCINCR_A {
337    #[doc = "0: DMA source increment 0: source address unchanged"]
338    DMASRCINCR_0 = 0,
339    #[doc = "1: DMA source increment 1: source address unchanged"]
340    DMASRCINCR_1 = 1,
341    #[doc = "2: DMA source increment 2: source address decremented"]
342    DMASRCINCR_2 = 2,
343    #[doc = "3: DMA source increment 3: source address incremented"]
344    DMASRCINCR_3 = 3,
345}
346impl From<DMASRCINCR_A> for u8 {
347    #[inline(always)]
348    fn from(variant: DMASRCINCR_A) -> Self {
349        variant as _
350    }
351}
352#[doc = "Field `DMASRCINCR` reader - DMA source increment bit 0"]
353pub struct DMASRCINCR_R(crate::FieldReader<u8, DMASRCINCR_A>);
354impl DMASRCINCR_R {
355    #[inline(always)]
356    pub(crate) fn new(bits: u8) -> Self {
357        DMASRCINCR_R(crate::FieldReader::new(bits))
358    }
359    #[doc = r"Get enumerated values variant"]
360    #[inline(always)]
361    pub fn variant(&self) -> DMASRCINCR_A {
362        match self.bits {
363            0 => DMASRCINCR_A::DMASRCINCR_0,
364            1 => DMASRCINCR_A::DMASRCINCR_1,
365            2 => DMASRCINCR_A::DMASRCINCR_2,
366            3 => DMASRCINCR_A::DMASRCINCR_3,
367            _ => unreachable!(),
368        }
369    }
370    #[doc = "Checks if the value of the field is `DMASRCINCR_0`"]
371    #[inline(always)]
372    pub fn is_dmasrcincr_0(&self) -> bool {
373        **self == DMASRCINCR_A::DMASRCINCR_0
374    }
375    #[doc = "Checks if the value of the field is `DMASRCINCR_1`"]
376    #[inline(always)]
377    pub fn is_dmasrcincr_1(&self) -> bool {
378        **self == DMASRCINCR_A::DMASRCINCR_1
379    }
380    #[doc = "Checks if the value of the field is `DMASRCINCR_2`"]
381    #[inline(always)]
382    pub fn is_dmasrcincr_2(&self) -> bool {
383        **self == DMASRCINCR_A::DMASRCINCR_2
384    }
385    #[doc = "Checks if the value of the field is `DMASRCINCR_3`"]
386    #[inline(always)]
387    pub fn is_dmasrcincr_3(&self) -> bool {
388        **self == DMASRCINCR_A::DMASRCINCR_3
389    }
390}
391impl core::ops::Deref for DMASRCINCR_R {
392    type Target = crate::FieldReader<u8, DMASRCINCR_A>;
393    #[inline(always)]
394    fn deref(&self) -> &Self::Target {
395        &self.0
396    }
397}
398#[doc = "Field `DMASRCINCR` writer - DMA source increment bit 0"]
399pub struct DMASRCINCR_W<'a> {
400    w: &'a mut W,
401}
402impl<'a> DMASRCINCR_W<'a> {
403    #[doc = r"Writes `variant` to the field"]
404    #[inline(always)]
405    pub fn variant(self, variant: DMASRCINCR_A) -> &'a mut W {
406        self.bits(variant.into())
407    }
408    #[doc = "DMA source increment 0: source address unchanged"]
409    #[inline(always)]
410    pub fn dmasrcincr_0(self) -> &'a mut W {
411        self.variant(DMASRCINCR_A::DMASRCINCR_0)
412    }
413    #[doc = "DMA source increment 1: source address unchanged"]
414    #[inline(always)]
415    pub fn dmasrcincr_1(self) -> &'a mut W {
416        self.variant(DMASRCINCR_A::DMASRCINCR_1)
417    }
418    #[doc = "DMA source increment 2: source address decremented"]
419    #[inline(always)]
420    pub fn dmasrcincr_2(self) -> &'a mut W {
421        self.variant(DMASRCINCR_A::DMASRCINCR_2)
422    }
423    #[doc = "DMA source increment 3: source address incremented"]
424    #[inline(always)]
425    pub fn dmasrcincr_3(self) -> &'a mut W {
426        self.variant(DMASRCINCR_A::DMASRCINCR_3)
427    }
428    #[doc = r"Writes raw bits to the field"]
429    #[inline(always)]
430    pub fn bits(self, value: u8) -> &'a mut W {
431        self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u16 & 0x03) << 8);
432        self.w
433    }
434}
435#[doc = "DMA destination increment bit 0\n\nValue on reset: 0"]
436#[derive(Clone, Copy, Debug, PartialEq)]
437#[repr(u8)]
438pub enum DMADSTINCR_A {
439    #[doc = "0: DMA destination increment 0: destination address unchanged"]
440    DMADSTINCR_0 = 0,
441    #[doc = "1: DMA destination increment 1: destination address unchanged"]
442    DMADSTINCR_1 = 1,
443    #[doc = "2: DMA destination increment 2: destination address decremented"]
444    DMADSTINCR_2 = 2,
445    #[doc = "3: DMA destination increment 3: destination address incremented"]
446    DMADSTINCR_3 = 3,
447}
448impl From<DMADSTINCR_A> for u8 {
449    #[inline(always)]
450    fn from(variant: DMADSTINCR_A) -> Self {
451        variant as _
452    }
453}
454#[doc = "Field `DMADSTINCR` reader - DMA destination increment bit 0"]
455pub struct DMADSTINCR_R(crate::FieldReader<u8, DMADSTINCR_A>);
456impl DMADSTINCR_R {
457    #[inline(always)]
458    pub(crate) fn new(bits: u8) -> Self {
459        DMADSTINCR_R(crate::FieldReader::new(bits))
460    }
461    #[doc = r"Get enumerated values variant"]
462    #[inline(always)]
463    pub fn variant(&self) -> DMADSTINCR_A {
464        match self.bits {
465            0 => DMADSTINCR_A::DMADSTINCR_0,
466            1 => DMADSTINCR_A::DMADSTINCR_1,
467            2 => DMADSTINCR_A::DMADSTINCR_2,
468            3 => DMADSTINCR_A::DMADSTINCR_3,
469            _ => unreachable!(),
470        }
471    }
472    #[doc = "Checks if the value of the field is `DMADSTINCR_0`"]
473    #[inline(always)]
474    pub fn is_dmadstincr_0(&self) -> bool {
475        **self == DMADSTINCR_A::DMADSTINCR_0
476    }
477    #[doc = "Checks if the value of the field is `DMADSTINCR_1`"]
478    #[inline(always)]
479    pub fn is_dmadstincr_1(&self) -> bool {
480        **self == DMADSTINCR_A::DMADSTINCR_1
481    }
482    #[doc = "Checks if the value of the field is `DMADSTINCR_2`"]
483    #[inline(always)]
484    pub fn is_dmadstincr_2(&self) -> bool {
485        **self == DMADSTINCR_A::DMADSTINCR_2
486    }
487    #[doc = "Checks if the value of the field is `DMADSTINCR_3`"]
488    #[inline(always)]
489    pub fn is_dmadstincr_3(&self) -> bool {
490        **self == DMADSTINCR_A::DMADSTINCR_3
491    }
492}
493impl core::ops::Deref for DMADSTINCR_R {
494    type Target = crate::FieldReader<u8, DMADSTINCR_A>;
495    #[inline(always)]
496    fn deref(&self) -> &Self::Target {
497        &self.0
498    }
499}
500#[doc = "Field `DMADSTINCR` writer - DMA destination increment bit 0"]
501pub struct DMADSTINCR_W<'a> {
502    w: &'a mut W,
503}
504impl<'a> DMADSTINCR_W<'a> {
505    #[doc = r"Writes `variant` to the field"]
506    #[inline(always)]
507    pub fn variant(self, variant: DMADSTINCR_A) -> &'a mut W {
508        self.bits(variant.into())
509    }
510    #[doc = "DMA destination increment 0: destination address unchanged"]
511    #[inline(always)]
512    pub fn dmadstincr_0(self) -> &'a mut W {
513        self.variant(DMADSTINCR_A::DMADSTINCR_0)
514    }
515    #[doc = "DMA destination increment 1: destination address unchanged"]
516    #[inline(always)]
517    pub fn dmadstincr_1(self) -> &'a mut W {
518        self.variant(DMADSTINCR_A::DMADSTINCR_1)
519    }
520    #[doc = "DMA destination increment 2: destination address decremented"]
521    #[inline(always)]
522    pub fn dmadstincr_2(self) -> &'a mut W {
523        self.variant(DMADSTINCR_A::DMADSTINCR_2)
524    }
525    #[doc = "DMA destination increment 3: destination address incremented"]
526    #[inline(always)]
527    pub fn dmadstincr_3(self) -> &'a mut W {
528        self.variant(DMADSTINCR_A::DMADSTINCR_3)
529    }
530    #[doc = r"Writes raw bits to the field"]
531    #[inline(always)]
532    pub fn bits(self, value: u8) -> &'a mut W {
533        self.w.bits = (self.w.bits & !(0x03 << 10)) | ((value as u16 & 0x03) << 10);
534        self.w
535    }
536}
537#[doc = "DMA transfer mode bit 0\n\nValue on reset: 0"]
538#[derive(Clone, Copy, Debug, PartialEq)]
539#[repr(u8)]
540pub enum DMADT_A {
541    #[doc = "0: DMA transfer mode 0: Single transfer"]
542    DMADT_0 = 0,
543    #[doc = "1: DMA transfer mode 1: Block transfer"]
544    DMADT_1 = 1,
545    #[doc = "2: DMA transfer mode 2: Burst-Block transfer"]
546    DMADT_2 = 2,
547    #[doc = "3: DMA transfer mode 3: Burst-Block transfer"]
548    DMADT_3 = 3,
549    #[doc = "4: DMA transfer mode 4: Repeated Single transfer"]
550    DMADT_4 = 4,
551    #[doc = "5: DMA transfer mode 5: Repeated Block transfer"]
552    DMADT_5 = 5,
553    #[doc = "6: DMA transfer mode 6: Repeated Burst-Block transfer"]
554    DMADT_6 = 6,
555    #[doc = "7: DMA transfer mode 7: Repeated Burst-Block transfer"]
556    DMADT_7 = 7,
557}
558impl From<DMADT_A> for u8 {
559    #[inline(always)]
560    fn from(variant: DMADT_A) -> Self {
561        variant as _
562    }
563}
564#[doc = "Field `DMADT` reader - DMA transfer mode bit 0"]
565pub struct DMADT_R(crate::FieldReader<u8, DMADT_A>);
566impl DMADT_R {
567    #[inline(always)]
568    pub(crate) fn new(bits: u8) -> Self {
569        DMADT_R(crate::FieldReader::new(bits))
570    }
571    #[doc = r"Get enumerated values variant"]
572    #[inline(always)]
573    pub fn variant(&self) -> DMADT_A {
574        match self.bits {
575            0 => DMADT_A::DMADT_0,
576            1 => DMADT_A::DMADT_1,
577            2 => DMADT_A::DMADT_2,
578            3 => DMADT_A::DMADT_3,
579            4 => DMADT_A::DMADT_4,
580            5 => DMADT_A::DMADT_5,
581            6 => DMADT_A::DMADT_6,
582            7 => DMADT_A::DMADT_7,
583            _ => unreachable!(),
584        }
585    }
586    #[doc = "Checks if the value of the field is `DMADT_0`"]
587    #[inline(always)]
588    pub fn is_dmadt_0(&self) -> bool {
589        **self == DMADT_A::DMADT_0
590    }
591    #[doc = "Checks if the value of the field is `DMADT_1`"]
592    #[inline(always)]
593    pub fn is_dmadt_1(&self) -> bool {
594        **self == DMADT_A::DMADT_1
595    }
596    #[doc = "Checks if the value of the field is `DMADT_2`"]
597    #[inline(always)]
598    pub fn is_dmadt_2(&self) -> bool {
599        **self == DMADT_A::DMADT_2
600    }
601    #[doc = "Checks if the value of the field is `DMADT_3`"]
602    #[inline(always)]
603    pub fn is_dmadt_3(&self) -> bool {
604        **self == DMADT_A::DMADT_3
605    }
606    #[doc = "Checks if the value of the field is `DMADT_4`"]
607    #[inline(always)]
608    pub fn is_dmadt_4(&self) -> bool {
609        **self == DMADT_A::DMADT_4
610    }
611    #[doc = "Checks if the value of the field is `DMADT_5`"]
612    #[inline(always)]
613    pub fn is_dmadt_5(&self) -> bool {
614        **self == DMADT_A::DMADT_5
615    }
616    #[doc = "Checks if the value of the field is `DMADT_6`"]
617    #[inline(always)]
618    pub fn is_dmadt_6(&self) -> bool {
619        **self == DMADT_A::DMADT_6
620    }
621    #[doc = "Checks if the value of the field is `DMADT_7`"]
622    #[inline(always)]
623    pub fn is_dmadt_7(&self) -> bool {
624        **self == DMADT_A::DMADT_7
625    }
626}
627impl core::ops::Deref for DMADT_R {
628    type Target = crate::FieldReader<u8, DMADT_A>;
629    #[inline(always)]
630    fn deref(&self) -> &Self::Target {
631        &self.0
632    }
633}
634#[doc = "Field `DMADT` writer - DMA transfer mode bit 0"]
635pub struct DMADT_W<'a> {
636    w: &'a mut W,
637}
638impl<'a> DMADT_W<'a> {
639    #[doc = r"Writes `variant` to the field"]
640    #[inline(always)]
641    pub fn variant(self, variant: DMADT_A) -> &'a mut W {
642        self.bits(variant.into())
643    }
644    #[doc = "DMA transfer mode 0: Single transfer"]
645    #[inline(always)]
646    pub fn dmadt_0(self) -> &'a mut W {
647        self.variant(DMADT_A::DMADT_0)
648    }
649    #[doc = "DMA transfer mode 1: Block transfer"]
650    #[inline(always)]
651    pub fn dmadt_1(self) -> &'a mut W {
652        self.variant(DMADT_A::DMADT_1)
653    }
654    #[doc = "DMA transfer mode 2: Burst-Block transfer"]
655    #[inline(always)]
656    pub fn dmadt_2(self) -> &'a mut W {
657        self.variant(DMADT_A::DMADT_2)
658    }
659    #[doc = "DMA transfer mode 3: Burst-Block transfer"]
660    #[inline(always)]
661    pub fn dmadt_3(self) -> &'a mut W {
662        self.variant(DMADT_A::DMADT_3)
663    }
664    #[doc = "DMA transfer mode 4: Repeated Single transfer"]
665    #[inline(always)]
666    pub fn dmadt_4(self) -> &'a mut W {
667        self.variant(DMADT_A::DMADT_4)
668    }
669    #[doc = "DMA transfer mode 5: Repeated Block transfer"]
670    #[inline(always)]
671    pub fn dmadt_5(self) -> &'a mut W {
672        self.variant(DMADT_A::DMADT_5)
673    }
674    #[doc = "DMA transfer mode 6: Repeated Burst-Block transfer"]
675    #[inline(always)]
676    pub fn dmadt_6(self) -> &'a mut W {
677        self.variant(DMADT_A::DMADT_6)
678    }
679    #[doc = "DMA transfer mode 7: Repeated Burst-Block transfer"]
680    #[inline(always)]
681    pub fn dmadt_7(self) -> &'a mut W {
682        self.variant(DMADT_A::DMADT_7)
683    }
684    #[doc = r"Writes raw bits to the field"]
685    #[inline(always)]
686    pub fn bits(self, value: u8) -> &'a mut W {
687        self.w.bits = (self.w.bits & !(0x07 << 12)) | ((value as u16 & 0x07) << 12);
688        self.w
689    }
690}
691impl R {
692    #[doc = "Bit 0 - Initiate DMA transfer with DMATSEL"]
693    #[inline(always)]
694    pub fn dmareq(&self) -> DMAREQ_R {
695        DMAREQ_R::new((self.bits & 0x01) != 0)
696    }
697    #[doc = "Bit 1 - DMA transfer aborted by NMI"]
698    #[inline(always)]
699    pub fn dmaabort(&self) -> DMAABORT_R {
700        DMAABORT_R::new(((self.bits >> 1) & 0x01) != 0)
701    }
702    #[doc = "Bit 2 - DMA interrupt enable"]
703    #[inline(always)]
704    pub fn dmaie(&self) -> DMAIE_R {
705        DMAIE_R::new(((self.bits >> 2) & 0x01) != 0)
706    }
707    #[doc = "Bit 3 - DMA interrupt flag"]
708    #[inline(always)]
709    pub fn dmaifg(&self) -> DMAIFG_R {
710        DMAIFG_R::new(((self.bits >> 3) & 0x01) != 0)
711    }
712    #[doc = "Bit 4 - DMA enable"]
713    #[inline(always)]
714    pub fn dmaen(&self) -> DMAEN_R {
715        DMAEN_R::new(((self.bits >> 4) & 0x01) != 0)
716    }
717    #[doc = "Bit 5 - DMA level sensitive trigger select"]
718    #[inline(always)]
719    pub fn dmalevel(&self) -> DMALEVEL_R {
720        DMALEVEL_R::new(((self.bits >> 5) & 0x01) != 0)
721    }
722    #[doc = "Bit 6 - DMA source byte"]
723    #[inline(always)]
724    pub fn dmasrcbyte(&self) -> DMASRCBYTE_R {
725        DMASRCBYTE_R::new(((self.bits >> 6) & 0x01) != 0)
726    }
727    #[doc = "Bit 7 - DMA destination byte"]
728    #[inline(always)]
729    pub fn dmadstbyte(&self) -> DMADSTBYTE_R {
730        DMADSTBYTE_R::new(((self.bits >> 7) & 0x01) != 0)
731    }
732    #[doc = "Bits 8:9 - DMA source increment bit 0"]
733    #[inline(always)]
734    pub fn dmasrcincr(&self) -> DMASRCINCR_R {
735        DMASRCINCR_R::new(((self.bits >> 8) & 0x03) as u8)
736    }
737    #[doc = "Bits 10:11 - DMA destination increment bit 0"]
738    #[inline(always)]
739    pub fn dmadstincr(&self) -> DMADSTINCR_R {
740        DMADSTINCR_R::new(((self.bits >> 10) & 0x03) as u8)
741    }
742    #[doc = "Bits 12:14 - DMA transfer mode bit 0"]
743    #[inline(always)]
744    pub fn dmadt(&self) -> DMADT_R {
745        DMADT_R::new(((self.bits >> 12) & 0x07) as u8)
746    }
747}
748impl W {
749    #[doc = "Bit 0 - Initiate DMA transfer with DMATSEL"]
750    #[inline(always)]
751    pub fn dmareq(&mut self) -> DMAREQ_W {
752        DMAREQ_W { w: self }
753    }
754    #[doc = "Bit 1 - DMA transfer aborted by NMI"]
755    #[inline(always)]
756    pub fn dmaabort(&mut self) -> DMAABORT_W {
757        DMAABORT_W { w: self }
758    }
759    #[doc = "Bit 2 - DMA interrupt enable"]
760    #[inline(always)]
761    pub fn dmaie(&mut self) -> DMAIE_W {
762        DMAIE_W { w: self }
763    }
764    #[doc = "Bit 3 - DMA interrupt flag"]
765    #[inline(always)]
766    pub fn dmaifg(&mut self) -> DMAIFG_W {
767        DMAIFG_W { w: self }
768    }
769    #[doc = "Bit 4 - DMA enable"]
770    #[inline(always)]
771    pub fn dmaen(&mut self) -> DMAEN_W {
772        DMAEN_W { w: self }
773    }
774    #[doc = "Bit 5 - DMA level sensitive trigger select"]
775    #[inline(always)]
776    pub fn dmalevel(&mut self) -> DMALEVEL_W {
777        DMALEVEL_W { w: self }
778    }
779    #[doc = "Bit 6 - DMA source byte"]
780    #[inline(always)]
781    pub fn dmasrcbyte(&mut self) -> DMASRCBYTE_W {
782        DMASRCBYTE_W { w: self }
783    }
784    #[doc = "Bit 7 - DMA destination byte"]
785    #[inline(always)]
786    pub fn dmadstbyte(&mut self) -> DMADSTBYTE_W {
787        DMADSTBYTE_W { w: self }
788    }
789    #[doc = "Bits 8:9 - DMA source increment bit 0"]
790    #[inline(always)]
791    pub fn dmasrcincr(&mut self) -> DMASRCINCR_W {
792        DMASRCINCR_W { w: self }
793    }
794    #[doc = "Bits 10:11 - DMA destination increment bit 0"]
795    #[inline(always)]
796    pub fn dmadstincr(&mut self) -> DMADSTINCR_W {
797        DMADSTINCR_W { w: self }
798    }
799    #[doc = "Bits 12:14 - DMA transfer mode bit 0"]
800    #[inline(always)]
801    pub fn dmadt(&mut self) -> DMADT_W {
802        DMADT_W { w: self }
803    }
804    #[doc = "Writes raw bits to the register."]
805    #[inline(always)]
806    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
807        self.0.bits(bits);
808        self
809    }
810}
811#[doc = "DMA Channel 0 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma0ctl](index.html) module"]
812pub struct DMA0CTL_SPEC;
813impl crate::RegisterSpec for DMA0CTL_SPEC {
814    type Ux = u16;
815}
816#[doc = "`read()` method returns [dma0ctl::R](R) reader structure"]
817impl crate::Readable for DMA0CTL_SPEC {
818    type Reader = R;
819}
820#[doc = "`write(|w| ..)` method takes [dma0ctl::W](W) writer structure"]
821impl crate::Writable for DMA0CTL_SPEC {
822    type Writer = W;
823}
824#[doc = "`reset()` method sets DMA0CTL to value 0"]
825impl crate::Resettable for DMA0CTL_SPEC {
826    #[inline(always)]
827    fn reset_value() -> Self::Ux {
828        0
829    }
830}
msp430f5529/dma/dma0ctl.rs

msp430f5529/dma/
dma0ctl.rs
