Module moore_svlog_syntax::ast
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An abstract syntax tree for SystemVerilog.
Re-exports
Structs
An arena.
An argument to a a function or task call.
A class declaration.
A continuous assignment statement.
An enum definition.
A single entry in an enum.
A foreach-loop index variable.
Format a node in definite form.
Format a node in indefinite form.
A body of a generate construct.
A case generate statement.
A for generate statement.
An if generate statement.
A generate variable declaration.
An implicit data type.
An import declaration.
A single import.
An instantiation of a module.
A single module instance.
An interface.
A modport declaration in an interface.
A single modport declaration.
A single simple modport port.
A module.
A net declaration.
Common denominator across all AST nodes.
A package.
A parameter or localparam declaration.
A single type assignment within a parameter or localparam declaration.
A single value assignment within a parameter or localparam declaration.
A port declaration in an item body.
A procedure such as always*, initial, or final.
All things being compiled.
An entire source file.
A statement.
A struct definition.
A struct field.
A function or task declaration.
A function or task port.
A function or task port declaration located in the body.
A single name of a function or task port.
A function or task prototype.
A time unit specification.
A type.
A type definition.
A variable declaration.
A variable or net declaration name.
Enums
An exhaustive list of all nodes.
A parsing result which may be ambiguous.
A data type.
A possible implicit data type.
A DPI declaration such as import "DPI-C" or export "DPI-C".
A DPI function/task property.
An expression.
An integer type.
An item that may appear in a hierarchical scope.
Lifetime specifier for variables, tasks, and functions. Defaults to static.
A modport ports declaration.
A packed dimension.
A segment of a type name.
A field in a '{...} pattern.
A port connection in an instantiation.
How a named port connection is made.
A module or interface port as declared in the port list.
A real type.
The different kinds of statement.
A type without sign and packed dimensions.
An ambiguous node that can either be a type or and expression.
An unpacked dimension.
A variable dimension.
Whether a declaration is a variable or a net.
Traits
A node that accepts Visitors.
An AST node.
Common details of an AST node.
Basic attributes of an AST node.
A node which allows iterating over each child node.
A node which can pass itself as AnyNode to a callback.
A visitor.
A node that walks a Visitor over itself.