moon-struct 0.1.1

Windows Kernel Struct offset
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227

pub mod msr_index {
    // MSR Constants
    pub const MSR_APIC_BASE: u32 = 0x01B;
    pub const MSR_IA32_FEATURE_CONTROL: u32 = 0x03A;
    pub const MSR_IA32_VMX_BASIC: u32 = 0x480;
    pub const MSR_IA32_VMX_PINBASED_CTLS: u32 = 0x481;
    pub const MSR_IA32_VMX_PROCBASED_CTLS: u32 = 0x482;
    pub const MSR_IA32_VMX_EXIT_CTLS: u32 = 0x483;
    pub const MSR_IA32_VMX_ENTRY_CTLS: u32 = 0x484;
    pub const MSR_IA32_VMX_MISC: u32 = 0x485;
    pub const MSR_IA32_VMX_CR0_FIXED0: u32 = 0x486;
    pub const MSR_IA32_VMX_CR0_FIXED1: u32 = 0x487;
    pub const MSR_IA32_VMX_CR4_FIXED0: u32 = 0x488;
    pub const MSR_IA32_VMX_CR4_FIXED1: u32 = 0x489;
    pub const MSR_IA32_VMX_VMCS_ENUM: u32 = 0x48A;
    pub const MSR_IA32_VMX_PROCBASED_CTLS2: u32 = 0x48B;
    pub const MSR_IA32_VMX_EPT_VPID_CAP: u32 = 0x48C;
    pub const MSR_IA32_VMX_TRUE_PINBASED_CTLS: u32 = 0x48D;
    pub const MSR_IA32_VMX_TRUE_PROCBASED_CTLS: u32 = 0x48E;
    pub const MSR_IA32_VMX_TRUE_EXIT_CTLS: u32 = 0x48F;
    pub const MSR_IA32_VMX_TRUE_ENTRY_CTLS: u32 = 0x490;
    pub const MSR_IA32_VMX_VMFUNC: u32 = 0x491;
    /** Tertiary processor-based VM execution controls. */
    pub const MSR_IA32_VMX_PROCBASED_CTLS3: u32 = 0x492;
    /** Secondary VM-exit controls. */
    pub const MSR_IA32_VMX_EXIT_CTLS2: u32 = 0x493;

    pub const MSR_IA32_SYSENTER_CS: u32 = 0x174;
    pub const MSR_IA32_SYSENTER_ESP: u32 = 0x175;
    pub const MSR_IA32_SYSENTER_EIP: u32 = 0x176;
    pub const MSR_IA32_DEBUGCTL: u32 = 0x1D9;
    pub const MSR_LSTAR: u32 = 0xC0000082;
    pub const MSR_FS_BASE: u32 = 0xC0000100;
    pub const MSR_GS_BASE: u32 = 0xC0000101;
    pub const MSR_SHADOW_GS_BASE: u32 = 0xC0000102; // SwapGS GS shadow

    pub const MSR_IA32_MTRR_DEF_TYPE: u32 = 0x000002FF;

    // MTRR Capabilities MSR
    pub const MSR_IA32_MTRR_CAPABILITIES: u32 = 0x000000FE;

    // MTRR Physical Base MSRs
    pub const MSR_IA32_MTRR_PHYSBASE0: u32 = 0x00000200;
    pub const MSR_IA32_MTRR_PHYSBASE1: u32 = 0x00000202;
    pub const MSR_IA32_MTRR_PHYSBASE2: u32 = 0x00000204;
    pub const MSR_IA32_MTRR_PHYSBASE3: u32 = 0x00000206;
    pub const MSR_IA32_MTRR_PHYSBASE4: u32 = 0x00000208;
    pub const MSR_IA32_MTRR_PHYSBASE5: u32 = 0x0000020A;
    pub const MSR_IA32_MTRR_PHYSBASE6: u32 = 0x0000020C;
    pub const MSR_IA32_MTRR_PHYSBASE7: u32 = 0x0000020E;
    pub const MSR_IA32_MTRR_PHYSBASE8: u32 = 0x00000210;
    pub const MSR_IA32_MTRR_PHYSBASE9: u32 = 0x00000212;

    // MTRR Physical Mask MSRs
    pub const MSR_IA32_MTRR_PHYSMASK0: u32 = 0x00000201;
    pub const MSR_IA32_MTRR_PHYSMASK1: u32 = 0x00000203;
    pub const MSR_IA32_MTRR_PHYSMASK2: u32 = 0x00000205;
    pub const MSR_IA32_MTRR_PHYSMASK3: u32 = 0x00000207;
    pub const MSR_IA32_MTRR_PHYSMASK4: u32 = 0x00000209;
    pub const MSR_IA32_MTRR_PHYSMASK5: u32 = 0x0000020B;
    pub const MSR_IA32_MTRR_PHYSMASK6: u32 = 0x0000020D;
    pub const MSR_IA32_MTRR_PHYSMASK7: u32 = 0x0000020F;
    pub const MSR_IA32_MTRR_PHYSMASK8: u32 = 0x00000211;
    pub const MSR_IA32_MTRR_PHYSMASK9: u32 = 0x00000213;

    pub const MSR_IA32_U_CET: u32 = 0x000006A0;
    pub const MSR_IA32_SSP: u32 = 0x000006A1;
    pub const MSR_IA32_S_CET: u32 = 0x000006A2;

    pub const MSR_IA32_PL0_SSP: u32 = 0x000006A4;
    pub const MSR_IA32_PL1_SSP: u32 = 0x000006A5;
    pub const MSR_IA32_PL2_SSP: u32 = 0x000006A6;
    pub const MSR_IA32_PL3_SSP: u32 = 0x000006A7;

    pub const MSR_IA32_INTERRUPT_SSP_TABLE_ADDR: u32 = 0x000006A8;

    // Hyper-V Synthetic MSR
    pub const MSR_SYNTHETIC_MIN: u32 = 0x40000000; // Synthetic MSR Address Space Min
    pub const MSR_SYNTHETIC_MAX: u32 = 0x400000FF; // Synthetic MSR Address Space Max

    // Hyper-V Synthetic Timer
    pub const MSR_STIMER0_CONFIG: u32 = 0x400000b0;
    pub const MSR_STIMER0_COUNT: u32 = 0x400000b1;
    pub const MSR_STIMER1_CONFIG: u32 = 0x400000b2;
    pub const MSR_STIMER1_COUNT: u32 = 0x400000b3;
    pub const MSR_STIMER2_CONFIG: u32 = 0x400000b4;
    pub const MSR_STIMER2_COUNT: u32 = 0x400000b5;
    pub const MSR_STIMER3_CONFIG: u32 = 0x400000b6;
    pub const MSR_STIMER3_COUNT: u32 = 0x400000b7;

    pub const MSR_CRASH_CTL: u32 = 0x40000105;
    pub const MSR_CRASH_P0: u32 = 0x40000100;

    pub const MSR_GUEST_IDLE: u32 = 0x400000F0;

    // RW Reserve MSR will #GP
    pub const MSR_LOW_MIN: u32 = 0;
    pub const MSR_LOW_MAX: u32 = 0x1FFF;
    pub const MSR_HIGH_MIN: u32 = 0xC0000000;
    pub const MSR_HIGH_MAX: u32 = 0xC0001FFF;

    /** SVM Control. */
    pub const MSR_K8_VM_CR: u32 = 0xc0010114;
}

pub mod ia32_mtrr_capabilities_msr {
    pub const VARIABLE_RANGE_COUNT_START: u64 = 0;
    pub const VARIABLE_RANGE_COUNT_LEN: u64 = 8;

    pub const PAGE_FRAME_NUMBER_START: u64 = 12;
    pub const PAGE_FRAME_NUMBER_LEN: u64 = 36;
}

pub mod ia32_mtrr_phys_base_msr {

    pub const TYPE_START: u64 = 0;
    pub const TYPE_LEN: u64 = 8;

    pub const PAGE_FRAME_NUMBER_START: u64 = 12;
    pub const PAGE_FRAME_NUMBER_LEN: u64 = 36;
}

pub mod ia32_mtrr_phys_mask_msr {
    use crate::RT_BIT_64;

    pub const VALID: u64 = RT_BIT_64!(11);

    pub const PAGE_FRAME_NUMBER_START: u64 = 12;
    pub const PAGE_FRAME_NUMBER_LEN: u64 = 36;
}

pub mod ia32_feature_control_msr {
    use crate::RT_BIT_64;

    /** Feature control - Lock MSR from writes (R/W0). */
    pub const MSR_IA32_FEATURE_CONTROL_LOCK: u64 = RT_BIT_64!(0);
    /** Feature control - Enable VMX inside SMX operation (R/WL). */
    pub const MSR_IA32_FEATURE_CONTROL_SMX_VMXON: u64 = RT_BIT_64!(1);
    /** Feature control - Enable VMX outside SMX operation (R/WL). */
    pub const MSR_IA32_FEATURE_CONTROL_VMXON: u64 = RT_BIT_64!(2);
    /** Feature control - SENTER local functions enable (R/WL).  */
    pub const MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0: u64 = RT_BIT_64!(8);
    pub const MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1: u64 = RT_BIT_64!(9);
    pub const MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2: u64 = RT_BIT_64!(10);
    pub const MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3: u64 = RT_BIT_64!(11);
    pub const MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4: u64 = RT_BIT_64!(12);
    pub const MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5: u64 = RT_BIT_64!(13);
    pub const MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6: u64 = RT_BIT_64!(14);
    /** Feature control - SENTER global enable (R/WL). */
    pub const MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN: u64 = RT_BIT_64!(15);
    /** Feature control - SGX launch control enable (R/WL). */
    pub const MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN: u64 = RT_BIT_64!(17);
    /** Feature control - SGX global enable (R/WL). */
    pub const MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN: u64 = RT_BIT_64!(18);
    /** Feature control - LMCE on (R/WL). */
    pub const MSR_IA32_FEATURE_CONTROL_LMCE: u64 = RT_BIT_64!(20);
}

pub mod ia32_vmx_basic_msr {
    use crate::RT_BIT_64;

    pub const VMX_CAPABILITY_HINT_MASK: u64 = RT_BIT_64!(55);
}

pub mod ia32_mtrr_def_type_msr {
    use crate::RT_BIT_64;

    pub const MTRR_ENABLE_MASK: u64 = RT_BIT_64!(11);
}

/// VMX MSR - EPT/VPID capabilities.
pub mod ia32_vmx_ept_vpid_cap_msr {
    use crate::RT_BIT_64;

    /** Supports execute-only translations by EPT. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY: u64 = RT_BIT_64!(0);
    /** Supports page-walk length of 4. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4: u64 = RT_BIT_64!(6);
    /** Supports page-walk length of 5. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5: u64 = RT_BIT_64!(7);
    /** Supports EPT paging-structure memory type to be uncacheable. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_UC: u64 = RT_BIT_64!(8);
    /** Supports EPT paging structure memory type to be write-back. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB: u64 = RT_BIT_64!(14);
    /** Supports EPT PDE to map a 2 MB page. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M: u64 = RT_BIT_64!(16);
    /** Supports EPT PDPTE to map a 1 GB page. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G: u64 = RT_BIT_64!(17);
    /** Supports INVEPT instruction. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_INVEPT: u64 = RT_BIT_64!(20);
    /** Supports accessed and dirty flags for EPT. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY: u64 = RT_BIT_64!(21);
    /** Supports advanced VM-exit info. for EPT violations. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION: u64 = RT_BIT_64!(22);
    /** Supports supervisor shadow-stack control. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK: u64 = RT_BIT_64!(23);
    /** Supports single-context INVEPT type. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT: u64 = RT_BIT_64!(25);
    /** Supports all-context INVEPT type. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS: u64 = RT_BIT_64!(26);
    /** Supports INVVPID instruction. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_INVVPID: u64 = RT_BIT_64!(32);
    /** Supports individual-address INVVPID type. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR: u64 = RT_BIT_64!(40);
    /** Supports single-context INVVPID type. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT: u64 = RT_BIT_64!(41);
    /** Supports all-context INVVPID type. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS: u64 = RT_BIT_64!(42);
    /** Supports singe-context-retaining-globals INVVPID type. */
    pub const MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS: u64 = RT_BIT_64!(43);
}

pub mod msr_k8_vm_cr {
    use crate::RT_BIT_64;

    pub const MSR_K8_VM_CR_DPD: u64 = RT_BIT_64!(0);
    /** If set, non-intercepted INIT signals are converted to \#SX
     *  exceptions. */
    pub const MSR_K8_VM_CR_R_INIT: u64 = RT_BIT_64!(1);
    /** Disables A20 masking.  */
    pub const MSR_K8_VM_CR_DIS_A20M: u64 = RT_BIT_64!(2);
    /** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
    pub const MSR_K8_VM_CR_LOCK: u64 = RT_BIT_64!(3);
    /** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
     *  clear, EFER.SVME can be written normally. */
    pub const MSR_K8_VM_CR_SVM_DISABLE: u64 = RT_BIT_64!(4);
}