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//! Zero-overhead, `no_std` memory-mapped I/O register abstraction.
//!
//! # Quick start
//!
//! ```ignore
//! use mmio_rs::prelude::*;
//!
//! // Implement a critical section for your target once per binary.
//! mmio_rs::impl_critical_section!(
//! acquire: { /* disable interrupts, return previous state */ 0 },
//! release: |_state| { /* restore interrupt state */ }
//! );
//!
//! // Define a peripheral's register layout.
//! mmio_rs::register_block! {
//! pub struct Uart @ 0x4000_1000 {
//! dr: u32 => ReadWrite @ 0x00,
//! sr: u32 => ReadOnly @ 0x04,
//! brr: u32 => ReadWrite @ 0x08,
//! }
//! }
//!
//! // Use it.
//! Uart::dr().write(b'A' as u32);
//! let status = Uart::sr().read();
//! Uart::brr().write_field(0xFFFF, 0, 0x0683); // set baud divisor
//! ```
pub use ;
pub use AtomicRegister;
pub use ;
pub use ;
pub use Register;
/// Convenience re-export of the most commonly used types.
///
/// Add `use mmio_rs::prelude::*;` to bring the whole public API into scope.