#![doc = "Peripheral access API for MM32F5277E microcontrollers (generated using svd2rust v0.28.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.28.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
#![deny(dead_code)]
#![deny(improper_ctypes)]
#![deny(missing_docs)]
#![deny(no_mangle_generic_items)]
#![deny(non_shorthand_field_patterns)]
#![deny(overflowing_literals)]
#![deny(path_statements)]
#![deny(patterns_in_fns_without_body)]
#![deny(private_in_public)]
#![deny(unconditional_recursion)]
#![deny(unused_allocation)]
#![deny(unused_comparisons)]
#![deny(unused_parens)]
#![deny(while_true)]
#![allow(non_camel_case_types)]
#![allow(non_snake_case)]
#![no_std]
use core::marker::PhantomData;
use core::ops::Deref;
#[doc = r"Number available in the NVIC for configuring priority"]
pub const NVIC_PRIO_BITS: u8 = 3;
#[cfg(feature = "rt")]
pub use self::Interrupt as interrupt;
pub use cortex_m::peripheral::Peripherals as CorePeripherals;
pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU};
#[cfg(feature = "rt")]
pub use cortex_m_rt::interrupt;
#[allow(unused_imports)]
use generic::*;
#[doc = "Common register and bit access and modify traits"]
pub mod generic;
#[cfg(feature = "rt")]
extern "C" {
fn WWDG_IWDG();
fn PVD();
fn BKP_TAMPER();
fn RTC();
fn FLASH();
fn RCC_CRS();
fn EXTI0();
fn EXTI1();
fn EXTI2();
fn EXTI3();
fn EXTI4();
fn DMA1_CH1();
fn DMA1_CH2();
fn DMA1_CH3();
fn DMA1_CH4();
fn DMA1_CH5();
fn DMA1_CH6();
fn DMA1_CH7();
fn ADC1_2();
fn DMA1_CH8();
fn FLEXCAN1();
fn EXTI9_5();
fn TIM1_BRK();
fn TIM1_UP();
fn TIM1_TRG_COM();
fn TIM1_CC();
fn TIM2();
fn TIM4();
fn I2C1();
fn I2C2();
fn SPI1();
fn SPI2();
fn UART1();
fn UART2();
fn UART3();
fn EXTI15_10();
fn RTC_ALR();
fn TIM8_BRK();
fn TIM8_UP();
fn TIM8_TRG_COM();
fn TIM8_CC();
fn TIM5();
fn SPI3();
fn UART4();
fn UART5();
fn TIM6();
fn TIM7();
fn DMA2_CH1();
fn DMA2_CH2();
fn DMA2_CH3();
fn DMA2_CH4();
fn DMA2_CH5();
fn ENET();
fn ENET_WKUP();
fn COMP();
fn FLEXCAN2();
fn USB_FS();
fn DMA2_CH6();
fn DMA2_CH7();
fn DMA2_CH8();
fn UART6();
fn UART7();
fn QSPI();
fn LPTIM();
fn LPUART();
}
#[doc(hidden)]
pub union Vector {
_handler: unsafe extern "C" fn(),
_reserved: u32,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[link_section = ".vector_table.interrupts"]
#[no_mangle]
pub static __INTERRUPTS: [Vector; 105] = [
Vector {
_handler: WWDG_IWDG,
},
Vector { _handler: PVD },
Vector {
_handler: BKP_TAMPER,
},
Vector { _handler: RTC },
Vector { _handler: FLASH },
Vector { _handler: RCC_CRS },
Vector { _handler: EXTI0 },
Vector { _handler: EXTI1 },
Vector { _handler: EXTI2 },
Vector { _handler: EXTI3 },
Vector { _handler: EXTI4 },
Vector { _handler: DMA1_CH1 },
Vector { _handler: DMA1_CH2 },
Vector { _handler: DMA1_CH3 },
Vector { _handler: DMA1_CH4 },
Vector { _handler: DMA1_CH5 },
Vector { _handler: DMA1_CH6 },
Vector { _handler: DMA1_CH7 },
Vector { _handler: ADC1_2 },
Vector { _reserved: 0 },
Vector { _handler: DMA1_CH8 },
Vector { _handler: FLEXCAN1 },
Vector { _reserved: 0 },
Vector { _handler: EXTI9_5 },
Vector { _handler: TIM1_BRK },
Vector { _handler: TIM1_UP },
Vector {
_handler: TIM1_TRG_COM,
},
Vector { _handler: TIM1_CC },
Vector { _handler: TIM2 },
Vector { _reserved: 0 },
Vector { _handler: TIM4 },
Vector { _handler: I2C1 },
Vector { _reserved: 0 },
Vector { _handler: I2C2 },
Vector { _reserved: 0 },
Vector { _handler: SPI1 },
Vector { _handler: SPI2 },
Vector { _handler: UART1 },
Vector { _handler: UART2 },
Vector { _handler: UART3 },
Vector {
_handler: EXTI15_10,
},
Vector { _handler: RTC_ALR },
Vector { _reserved: 0 },
Vector { _handler: TIM8_BRK },
Vector { _handler: TIM8_UP },
Vector {
_handler: TIM8_TRG_COM,
},
Vector { _handler: TIM8_CC },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: TIM5 },
Vector { _handler: SPI3 },
Vector { _handler: UART4 },
Vector { _handler: UART5 },
Vector { _handler: TIM6 },
Vector { _handler: TIM7 },
Vector { _handler: DMA2_CH1 },
Vector { _handler: DMA2_CH2 },
Vector { _handler: DMA2_CH3 },
Vector { _handler: DMA2_CH4 },
Vector { _handler: DMA2_CH5 },
Vector { _handler: ENET },
Vector {
_handler: ENET_WKUP,
},
Vector { _reserved: 0 },
Vector { _handler: COMP },
Vector { _handler: FLEXCAN2 },
Vector { _reserved: 0 },
Vector { _handler: USB_FS },
Vector { _handler: DMA2_CH6 },
Vector { _handler: DMA2_CH7 },
Vector { _handler: DMA2_CH8 },
Vector { _handler: UART6 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: UART7 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: QSPI },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _reserved: 0 },
Vector { _handler: LPTIM },
Vector { _reserved: 0 },
Vector { _handler: LPUART },
];
#[doc = r"Enumeration of all the interrupts."]
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[repr(u16)]
pub enum Interrupt {
#[doc = "0 - WWDG_IWDG global interrupt"]
WWDG_IWDG = 0,
#[doc = "1 - PVD and EXTI16 global interrupt"]
PVD = 1,
#[doc = "2 - BKP tamper interrupt"]
BKP_TAMPER = 2,
#[doc = "3 - RTC global interrupt"]
RTC = 3,
#[doc = "4 - Flash global interrupt"]
FLASH = 4,
#[doc = "5 - RCC and CRS global interrupt"]
RCC_CRS = 5,
#[doc = "6 - EXTI line0 interrupt"]
EXTI0 = 6,
#[doc = "7 - EXTI line1 interrupt"]
EXTI1 = 7,
#[doc = "8 - EXTI line2 interrupt"]
EXTI2 = 8,
#[doc = "9 - EXTI line3 interrupt"]
EXTI3 = 9,
#[doc = "10 - EXTI line4 interrupt"]
EXTI4 = 10,
#[doc = "11 - DMA1 channel 1 global interrupt"]
DMA1_CH1 = 11,
#[doc = "12 - DMA1 channel 2 global interrupt"]
DMA1_CH2 = 12,
#[doc = "13 - DMA1 channel 3 global interrupt"]
DMA1_CH3 = 13,
#[doc = "14 - DMA1 channel 4 global interrupt"]
DMA1_CH4 = 14,
#[doc = "15 - DMA1 channel 5 global interrupt"]
DMA1_CH5 = 15,
#[doc = "16 - DMA1 channel 6 global interrupt"]
DMA1_CH6 = 16,
#[doc = "17 - DMA1 channel 7 global interrupt"]
DMA1_CH7 = 17,
#[doc = "18 - ADC1_2 global interrupt"]
ADC1_2 = 18,
#[doc = "20 - DMA1 channel 8 global interrupt"]
DMA1_CH8 = 20,
#[doc = "21 - FLEXCAN1 global interrupt"]
FLEXCAN1 = 21,
#[doc = "23 - EXTI line5_6_7_8_9 interrupt"]
EXTI9_5 = 23,
#[doc = "24 - TIM1 break global interrupt"]
TIM1_BRK = 24,
#[doc = "25 - TIM1 update global interrupt"]
TIM1_UP = 25,
#[doc = "26 - TIM1 trigger com global interrupt"]
TIM1_TRG_COM = 26,
#[doc = "27 - TIM1 capture compare global interrupt"]
TIM1_CC = 27,
#[doc = "28 - TIM2 global interrupt"]
TIM2 = 28,
#[doc = "30 - TIM4 global interrupt"]
TIM4 = 30,
#[doc = "31 - I2C1 global interrupt"]
I2C1 = 31,
#[doc = "33 - I2C2 global interrupt"]
I2C2 = 33,
#[doc = "35 - SPI1 global interrupt"]
SPI1 = 35,
#[doc = "36 - SPI2 global interrupt"]
SPI2 = 36,
#[doc = "37 - UART1 global interrupt"]
UART1 = 37,
#[doc = "38 - UART2 global interrupt"]
UART2 = 38,
#[doc = "39 - UART3 global interrupt"]
UART3 = 39,
#[doc = "40 - EXTI line10_11_12_13_14_15 interrupt"]
EXTI15_10 = 40,
#[doc = "41 - RTC_ALR global interrupt"]
RTC_ALR = 41,
#[doc = "43 - TIM8_BRK global interrupt"]
TIM8_BRK = 43,
#[doc = "44 - TIM8_UP global interrupt"]
TIM8_UP = 44,
#[doc = "45 - TIM8_TRG_COM global interrupt"]
TIM8_TRG_COM = 45,
#[doc = "46 - TIM8_CC global interrupt"]
TIM8_CC = 46,
#[doc = "50 - TIM5 global interrupt"]
TIM5 = 50,
#[doc = "51 - SPI3 global interrupt"]
SPI3 = 51,
#[doc = "52 - UART4 global interrupt"]
UART4 = 52,
#[doc = "53 - UART5 global interrupt"]
UART5 = 53,
#[doc = "54 - TIM6 global interrupt"]
TIM6 = 54,
#[doc = "55 - TIM7 global interrupt"]
TIM7 = 55,
#[doc = "56 - DMA2 channel 1 global interrupt"]
DMA2_CH1 = 56,
#[doc = "57 - DMA2 channel 2 global interrupt"]
DMA2_CH2 = 57,
#[doc = "58 - DMA2 channel 3 global interrupt"]
DMA2_CH3 = 58,
#[doc = "59 - DMA2 channel 4 global interrupt"]
DMA2_CH4 = 59,
#[doc = "60 - DMA2 channel 5 global interrupt"]
DMA2_CH5 = 60,
#[doc = "61 - ENET global interrupt"]
ENET = 61,
#[doc = "62 - ENET wakeup global interrupt"]
ENET_WKUP = 62,
#[doc = "64 - COMP1_2_3 global interrupt"]
COMP = 64,
#[doc = "65 - FLEXCAN2 global interrupt"]
FLEXCAN2 = 65,
#[doc = "67 - USB FS OTG global interrupt"]
USB_FS = 67,
#[doc = "68 - DMA2 channel 6 global interrupt"]
DMA2_CH6 = 68,
#[doc = "69 - DMA2 channel 7 global interrupt"]
DMA2_CH7 = 69,
#[doc = "70 - DMA2 channel 8 global interrupt"]
DMA2_CH8 = 70,
#[doc = "71 - UART6 global interrupt"]
UART6 = 71,
#[doc = "82 - UART7 global interrupt"]
UART7 = 82,
#[doc = "95 - QSPI global interrupt"]
QSPI = 95,
#[doc = "102 - LPTIM global interrupt"]
LPTIM = 102,
#[doc = "104 - LPUART global interrupt"]
LPUART = 104,
}
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
#[inline(always)]
fn number(self) -> u16 {
self as u16
}
}
#[doc = "ADC1"]
pub struct ADC1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for ADC1 {}
impl ADC1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const adc1::RegisterBlock = 0x4001_2400 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const adc1::RegisterBlock {
Self::PTR
}
}
impl Deref for ADC1 {
type Target = adc1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for ADC1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ADC1").finish()
}
}
#[doc = "ADC1"]
pub mod adc1 {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - A/D data register"]
pub addata: ADDATA,
#[doc = "0x04 - A/D Configuration Register"]
pub adcfg: ADCFG,
#[doc = "0x08 - A/D Control Register"]
pub adcr: ADCR,
#[doc = "0x0c - A/D Channel Select Register"]
pub adchs: ADCHS,
#[doc = "0x10 - A/D Analog Watchdog Compare Register"]
pub adcmpr: ADCMPR,
#[doc = "0x14 - A/D Status Register"]
pub adsta: ADSTA,
#[doc = "0x18 - A/D Channel Data Register"]
pub addr0: ADDR0,
#[doc = "0x1c - A/D Channel Data Register"]
pub addr1: ADDR1,
#[doc = "0x20 - A/D Channel Data Register"]
pub addr2: ADDR2,
#[doc = "0x24 - A/D Channel Data Register"]
pub addr3: ADDR3,
#[doc = "0x28 - A/D Channel Data Register"]
pub addr4: ADDR4,
#[doc = "0x2c - A/D Channel Data Register"]
pub addr5: ADDR5,
#[doc = "0x30 - A/D Channel Data Register"]
pub addr6: ADDR6,
#[doc = "0x34 - A/D Channel Data Register"]
pub addr7: ADDR7,
#[doc = "0x38 - A/D Channel Data Register"]
pub addr8: ADDR8,
#[doc = "0x3c - A/D Channel Data Register"]
pub addr9: ADDR9,
#[doc = "0x40 - A/D Channel Data Register"]
pub addr10: ADDR10,
#[doc = "0x44 - A/D Channel Data Register"]
pub addr11: ADDR11,
#[doc = "0x48 - A/D Channel Data Register"]
pub addr12: ADDR12,
#[doc = "0x4c - A/D Channel Data Register"]
pub addr13: ADDR13,
#[doc = "0x50 - A/D Channel Data Register"]
pub addr14: ADDR14,
#[doc = "0x54 - A/D Channel Data Register"]
pub addr15: ADDR15,
#[doc = "0x58 - A/D Extended Status Register"]
pub adsta_ext: ADSTA_EXT,
#[doc = "0x5c - A/D any channel channel select register 0"]
pub chany0: CHANY0,
#[doc = "0x60 - A/D arbitrary channel channel selection register 1"]
pub chany1: CHANY1,
#[doc = "0x64 - A/D Arbitrary Channel Configuration Register"]
pub any_cfg: ANY_CFG,
#[doc = "0x68 - A/D arbitrary channel control register"]
pub any_cr: ANY_CR,
#[doc = "0x6c - ADC Configuration Register"]
pub adcfg2: ADCFG2,
#[doc = "0x70 - A/D Sampling Configuration Register 1"]
pub smpr1: SMPR1,
#[doc = "0x74 - A/D Sampling Configuration Register 2"]
pub smpr2: SMPR2,
_reserved30: [u8; 0x04],
#[doc = "0x7c - A/D Injection Channel Data Compensation Register"]
pub jofr0: JOFR0,
#[doc = "0x80 - A/D Injection Channel Data Compensation Register"]
pub jofr1: JOFR1,
#[doc = "0x84 - A/D Injection Channel Data Compensation Register"]
pub jofr2: JOFR2,
#[doc = "0x88 - A/D Injection Channel Data Compensation Register"]
pub jofr3: JOFR3,
#[doc = "0x8c - A/D injection channel sequence register"]
pub jsqr: JSQR,
#[doc = "0x90 - A/D injection data register"]
pub jaddata: JADDATA,
_reserved36: [u8; 0x1c],
#[doc = "0xb0 - A/D injection channel data register"]
pub jdr0: JDR0,
#[doc = "0xb4 - A/D injection channel data register"]
pub jdr1: JDR1,
#[doc = "0xb8 - A/D injection channel data register"]
pub jdr2: JDR2,
#[doc = "0xbc - A/D injection channel data register"]
pub jdr3: JDR3,
}
#[doc = "ADDATA (r) register accessor: an alias for `Reg<ADDATA_SPEC>`"]
pub type ADDATA = crate::Reg<addata::ADDATA_SPEC>;
#[doc = "A/D data register"]
pub mod addata {
#[doc = "Register `ADDATA` reader"]
pub struct R(crate::R<ADDATA_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ADDATA_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ADDATA_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ADDATA_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `DATA` reader - "]
pub type DATA_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CHANNELSELL` reader - "]
pub type CHANNELSELL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OVERRUN` reader - "]
pub type OVERRUN_R = crate::BitReader<bool>;
#[doc = "Field `VALID` reader - "]
pub type VALID_R = crate::BitReader<bool>;
#[doc = "Field `CHANNELSELH` reader - "]
pub type CHANNELSELH_R = crate::BitReader<bool>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn data(&self) -> DATA_R {
DATA_R::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:19"]
#[inline(always)]
pub fn channelsell(&self) -> CHANNELSELL_R {
CHANNELSELL_R::new(((self.bits >> 16) & 0x0f) as u8)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn overrun(&self) -> OVERRUN_R {
OVERRUN_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn valid(&self) -> VALID_R {
VALID_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn channelselh(&self) -> CHANNELSELH_R {
CHANNELSELH_R::new(((self.bits >> 22) & 1) != 0)
}
}
#[doc = "A/D data register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addata](index.html) module"]
pub struct ADDATA_SPEC;
impl crate::RegisterSpec for ADDATA_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [addata::R](R) reader structure"]
impl crate::Readable for ADDATA_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets ADDATA to value 0"]
impl crate::Resettable for ADDATA_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ADCFG (rw) register accessor: an alias for `Reg<ADCFG_SPEC>`"]
pub type ADCFG = crate::Reg<adcfg::ADCFG_SPEC>;
#[doc = "A/D Configuration Register"]
pub mod adcfg {
#[doc = "Register `ADCFG` reader"]
pub struct R(crate::R<ADCFG_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ADCFG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ADCFG_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ADCFG_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ADCFG` writer"]
pub struct W(crate::W<ADCFG_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ADCFG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ADCFG_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ADCFG_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `ADEN` reader - "]
pub type ADEN_R = crate::BitReader<bool>;
#[doc = "Field `ADEN` writer - "]
pub type ADEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCFG_SPEC, bool, O>;
#[doc = "Field `AWDEN` reader - "]
pub type AWDEN_R = crate::BitReader<bool>;
#[doc = "Field `AWDEN` writer - "]
pub type AWDEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCFG_SPEC, bool, O>;
#[doc = "Field `TSEN` reader - "]
pub type TSEN_R = crate::BitReader<bool>;
#[doc = "Field `TSEN` writer - "]
pub type TSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCFG_SPEC, bool, O>;
#[doc = "Field `VSEN` reader - "]
pub type VSEN_R = crate::BitReader<bool>;
#[doc = "Field `VSEN` writer - "]
pub type VSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCFG_SPEC, bool, O>;
#[doc = "Field `RSLTCTL` reader - "]
pub type RSLTCTL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `RSLTCTL` writer - "]
pub type RSLTCTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADCFG_SPEC, u8, u8, 3, O>;
#[doc = "Field `JAWDEN` reader - "]
pub type JAWDEN_R = crate::BitReader<bool>;
#[doc = "Field `JAWDEN` writer - "]
pub type JAWDEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCFG_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn aden(&self) -> ADEN_R {
ADEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn awden(&self) -> AWDEN_R {
AWDEN_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn tsen(&self) -> TSEN_R {
TSEN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn vsen(&self) -> VSEN_R {
VSEN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 7:9"]
#[inline(always)]
pub fn rsltctl(&self) -> RSLTCTL_R {
RSLTCTL_R::new(((self.bits >> 7) & 7) as u8)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn jawden(&self) -> JAWDEN_R {
JAWDEN_R::new(((self.bits >> 16) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn aden(&mut self) -> ADEN_W<0> {
ADEN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn awden(&mut self) -> AWDEN_W<1> {
AWDEN_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn tsen(&mut self) -> TSEN_W<2> {
TSEN_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn vsen(&mut self) -> VSEN_W<3> {
VSEN_W::new(self)
}
#[doc = "Bits 7:9"]
#[inline(always)]
#[must_use]
pub fn rsltctl(&mut self) -> RSLTCTL_W<7> {
RSLTCTL_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn jawden(&mut self) -> JAWDEN_W<16> {
JAWDEN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "A/D Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adcfg](index.html) module"]
pub struct ADCFG_SPEC;
impl crate::RegisterSpec for ADCFG_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [adcfg::R](R) reader structure"]
impl crate::Readable for ADCFG_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [adcfg::W](W) writer structure"]
impl crate::Writable for ADCFG_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ADCFG to value 0"]
impl crate::Resettable for ADCFG_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ADCR (rw) register accessor: an alias for `Reg<ADCR_SPEC>`"]
pub type ADCR = crate::Reg<adcr::ADCR_SPEC>;
#[doc = "A/D Control Register"]
pub mod adcr {
#[doc = "Register `ADCR` reader"]
pub struct R(crate::R<ADCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ADCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ADCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ADCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ADCR` writer"]
pub struct W(crate::W<ADCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ADCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ADCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ADCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EOSIE` reader - "]
pub type EOSIE_R = crate::BitReader<bool>;
#[doc = "Field `EOSIE` writer - "]
pub type EOSIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCR_SPEC, bool, O>;
#[doc = "Field `AWDIE` reader - "]
pub type AWDIE_R = crate::BitReader<bool>;
#[doc = "Field `AWDIE` writer - "]
pub type AWDIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCR_SPEC, bool, O>;
#[doc = "Field `TRGEN` reader - "]
pub type TRGEN_R = crate::BitReader<bool>;
#[doc = "Field `TRGEN` writer - "]
pub type TRGEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCR_SPEC, bool, O>;
#[doc = "Field `DMAEN` reader - "]
pub type DMAEN_R = crate::BitReader<bool>;
#[doc = "Field `DMAEN` writer - "]
pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCR_SPEC, bool, O>;
#[doc = "Field `ADST` reader - "]
pub type ADST_R = crate::BitReader<bool>;
#[doc = "Field `ADST` writer - "]
pub type ADST_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCR_SPEC, bool, O>;
#[doc = "Field `ADMD` reader - "]
pub type ADMD_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ADMD` writer - "]
pub type ADMD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `ALIGN` reader - "]
pub type ALIGN_R = crate::BitReader<bool>;
#[doc = "Field `ALIGN` writer - "]
pub type ALIGN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCR_SPEC, bool, O>;
#[doc = "Field `CMPCHL` reader - "]
pub type CMPCHL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CMPCHL` writer - "]
pub type CMPCHL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADCR_SPEC, u8, u8, 4, O>;
#[doc = "Field `SCANDIR` reader - "]
pub type SCANDIR_R = crate::BitReader<bool>;
#[doc = "Field `SCANDIR` writer - "]
pub type SCANDIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCR_SPEC, bool, O>;
#[doc = "Field `TRGSHIFT` reader - "]
pub type TRGSHIFT_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TRGSHIFT` writer - "]
pub type TRGSHIFT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADCR_SPEC, u8, u8, 3, O>;
#[doc = "Field `TRG_EDGE` reader - "]
pub type TRG_EDGE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TRG_EDGE` writer - "]
pub type TRG_EDGE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `EOSMPIE` reader - "]
pub type EOSMPIE_R = crate::BitReader<bool>;
#[doc = "Field `EOSMPIE` writer - "]
pub type EOSMPIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCR_SPEC, bool, O>;
#[doc = "Field `EOCIE` reader - "]
pub type EOCIE_R = crate::BitReader<bool>;
#[doc = "Field `EOCIE` writer - "]
pub type EOCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCR_SPEC, bool, O>;
#[doc = "Field `CMPCHH` reader - "]
pub type CMPCHH_R = crate::BitReader<bool>;
#[doc = "Field `CMPCHH` writer - "]
pub type CMPCHH_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn eosie(&self) -> EOSIE_R {
EOSIE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn awdie(&self) -> AWDIE_R {
AWDIE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn trgen(&self) -> TRGEN_R {
TRGEN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn dmaen(&self) -> DMAEN_R {
DMAEN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn adst(&self) -> ADST_R {
ADST_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:10"]
#[inline(always)]
pub fn admd(&self) -> ADMD_R {
ADMD_R::new(((self.bits >> 9) & 3) as u8)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn align(&self) -> ALIGN_R {
ALIGN_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:15"]
#[inline(always)]
pub fn cmpchl(&self) -> CMPCHL_R {
CMPCHL_R::new(((self.bits >> 12) & 0x0f) as u8)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn scandir(&self) -> SCANDIR_R {
SCANDIR_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 19:21"]
#[inline(always)]
pub fn trgshift(&self) -> TRGSHIFT_R {
TRGSHIFT_R::new(((self.bits >> 19) & 7) as u8)
}
#[doc = "Bits 24:25"]
#[inline(always)]
pub fn trg_edge(&self) -> TRG_EDGE_R {
TRG_EDGE_R::new(((self.bits >> 24) & 3) as u8)
}
#[doc = "Bit 26"]
#[inline(always)]
pub fn eosmpie(&self) -> EOSMPIE_R {
EOSMPIE_R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27"]
#[inline(always)]
pub fn eocie(&self) -> EOCIE_R {
EOCIE_R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn cmpchh(&self) -> CMPCHH_R {
CMPCHH_R::new(((self.bits >> 28) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn eosie(&mut self) -> EOSIE_W<0> {
EOSIE_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn awdie(&mut self) -> AWDIE_W<1> {
AWDIE_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn trgen(&mut self) -> TRGEN_W<2> {
TRGEN_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn dmaen(&mut self) -> DMAEN_W<3> {
DMAEN_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn adst(&mut self) -> ADST_W<8> {
ADST_W::new(self)
}
#[doc = "Bits 9:10"]
#[inline(always)]
#[must_use]
pub fn admd(&mut self) -> ADMD_W<9> {
ADMD_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn align(&mut self) -> ALIGN_W<11> {
ALIGN_W::new(self)
}
#[doc = "Bits 12:15"]
#[inline(always)]
#[must_use]
pub fn cmpchl(&mut self) -> CMPCHL_W<12> {
CMPCHL_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn scandir(&mut self) -> SCANDIR_W<16> {
SCANDIR_W::new(self)
}
#[doc = "Bits 19:21"]
#[inline(always)]
#[must_use]
pub fn trgshift(&mut self) -> TRGSHIFT_W<19> {
TRGSHIFT_W::new(self)
}
#[doc = "Bits 24:25"]
#[inline(always)]
#[must_use]
pub fn trg_edge(&mut self) -> TRG_EDGE_W<24> {
TRG_EDGE_W::new(self)
}
#[doc = "Bit 26"]
#[inline(always)]
#[must_use]
pub fn eosmpie(&mut self) -> EOSMPIE_W<26> {
EOSMPIE_W::new(self)
}
#[doc = "Bit 27"]
#[inline(always)]
#[must_use]
pub fn eocie(&mut self) -> EOCIE_W<27> {
EOCIE_W::new(self)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn cmpchh(&mut self) -> CMPCHH_W<28> {
CMPCHH_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "A/D Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adcr](index.html) module"]
pub struct ADCR_SPEC;
impl crate::RegisterSpec for ADCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [adcr::R](R) reader structure"]
impl crate::Readable for ADCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [adcr::W](W) writer structure"]
impl crate::Writable for ADCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ADCR to value 0"]
impl crate::Resettable for ADCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ADCHS (rw) register accessor: an alias for `Reg<ADCHS_SPEC>`"]
pub type ADCHS = crate::Reg<adchs::ADCHS_SPEC>;
#[doc = "A/D Channel Select Register"]
pub mod adchs {
#[doc = "Register `ADCHS` reader"]
pub struct R(crate::R<ADCHS_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ADCHS_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ADCHS_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ADCHS_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ADCHS` writer"]
pub struct W(crate::W<ADCHS_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ADCHS_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ADCHS_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ADCHS_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CHEN0` reader - "]
pub type CHEN0_R = crate::BitReader<bool>;
#[doc = "Field `CHEN0` writer - "]
pub type CHEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCHS_SPEC, bool, O>;
#[doc = "Field `CHEN1` reader - "]
pub type CHEN1_R = crate::BitReader<bool>;
#[doc = "Field `CHEN1` writer - "]
pub type CHEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCHS_SPEC, bool, O>;
#[doc = "Field `CHEN2` reader - "]
pub type CHEN2_R = crate::BitReader<bool>;
#[doc = "Field `CHEN2` writer - "]
pub type CHEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCHS_SPEC, bool, O>;
#[doc = "Field `CHEN3` reader - "]
pub type CHEN3_R = crate::BitReader<bool>;
#[doc = "Field `CHEN3` writer - "]
pub type CHEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCHS_SPEC, bool, O>;
#[doc = "Field `CHEN4` reader - "]
pub type CHEN4_R = crate::BitReader<bool>;
#[doc = "Field `CHEN4` writer - "]
pub type CHEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCHS_SPEC, bool, O>;
#[doc = "Field `CHEN5` reader - "]
pub type CHEN5_R = crate::BitReader<bool>;
#[doc = "Field `CHEN5` writer - "]
pub type CHEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCHS_SPEC, bool, O>;
#[doc = "Field `CHEN6` reader - "]
pub type CHEN6_R = crate::BitReader<bool>;
#[doc = "Field `CHEN6` writer - "]
pub type CHEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCHS_SPEC, bool, O>;
#[doc = "Field `CHEN7` reader - "]
pub type CHEN7_R = crate::BitReader<bool>;
#[doc = "Field `CHEN7` writer - "]
pub type CHEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCHS_SPEC, bool, O>;
#[doc = "Field `CHEN8` reader - "]
pub type CHEN8_R = crate::BitReader<bool>;
#[doc = "Field `CHEN8` writer - "]
pub type CHEN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCHS_SPEC, bool, O>;
#[doc = "Field `CHEN9` reader - "]
pub type CHEN9_R = crate::BitReader<bool>;
#[doc = "Field `CHEN9` writer - "]
pub type CHEN9_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCHS_SPEC, bool, O>;
#[doc = "Field `CHEN10` reader - "]
pub type CHEN10_R = crate::BitReader<bool>;
#[doc = "Field `CHEN10` writer - "]
pub type CHEN10_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCHS_SPEC, bool, O>;
#[doc = "Field `CHEN11` reader - "]
pub type CHEN11_R = crate::BitReader<bool>;
#[doc = "Field `CHEN11` writer - "]
pub type CHEN11_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCHS_SPEC, bool, O>;
#[doc = "Field `CHEN12` reader - "]
pub type CHEN12_R = crate::BitReader<bool>;
#[doc = "Field `CHEN12` writer - "]
pub type CHEN12_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCHS_SPEC, bool, O>;
#[doc = "Field `CHEN13` reader - "]
pub type CHEN13_R = crate::BitReader<bool>;
#[doc = "Field `CHEN13` writer - "]
pub type CHEN13_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCHS_SPEC, bool, O>;
#[doc = "Field `CHEN14` reader - "]
pub type CHEN14_R = crate::BitReader<bool>;
#[doc = "Field `CHEN14` writer - "]
pub type CHEN14_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCHS_SPEC, bool, O>;
#[doc = "Field `CHEN15` reader - "]
pub type CHEN15_R = crate::BitReader<bool>;
#[doc = "Field `CHEN15` writer - "]
pub type CHEN15_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCHS_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn chen0(&self) -> CHEN0_R {
CHEN0_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn chen1(&self) -> CHEN1_R {
CHEN1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn chen2(&self) -> CHEN2_R {
CHEN2_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn chen3(&self) -> CHEN3_R {
CHEN3_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn chen4(&self) -> CHEN4_R {
CHEN4_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn chen5(&self) -> CHEN5_R {
CHEN5_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn chen6(&self) -> CHEN6_R {
CHEN6_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn chen7(&self) -> CHEN7_R {
CHEN7_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn chen8(&self) -> CHEN8_R {
CHEN8_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn chen9(&self) -> CHEN9_R {
CHEN9_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn chen10(&self) -> CHEN10_R {
CHEN10_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn chen11(&self) -> CHEN11_R {
CHEN11_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn chen12(&self) -> CHEN12_R {
CHEN12_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn chen13(&self) -> CHEN13_R {
CHEN13_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn chen14(&self) -> CHEN14_R {
CHEN14_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn chen15(&self) -> CHEN15_R {
CHEN15_R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn chen0(&mut self) -> CHEN0_W<0> {
CHEN0_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn chen1(&mut self) -> CHEN1_W<1> {
CHEN1_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn chen2(&mut self) -> CHEN2_W<2> {
CHEN2_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn chen3(&mut self) -> CHEN3_W<3> {
CHEN3_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn chen4(&mut self) -> CHEN4_W<4> {
CHEN4_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn chen5(&mut self) -> CHEN5_W<5> {
CHEN5_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn chen6(&mut self) -> CHEN6_W<6> {
CHEN6_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn chen7(&mut self) -> CHEN7_W<7> {
CHEN7_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn chen8(&mut self) -> CHEN8_W<8> {
CHEN8_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn chen9(&mut self) -> CHEN9_W<9> {
CHEN9_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn chen10(&mut self) -> CHEN10_W<10> {
CHEN10_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn chen11(&mut self) -> CHEN11_W<11> {
CHEN11_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn chen12(&mut self) -> CHEN12_W<12> {
CHEN12_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn chen13(&mut self) -> CHEN13_W<13> {
CHEN13_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn chen14(&mut self) -> CHEN14_W<14> {
CHEN14_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn chen15(&mut self) -> CHEN15_W<15> {
CHEN15_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "A/D Channel Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adchs](index.html) module"]
pub struct ADCHS_SPEC;
impl crate::RegisterSpec for ADCHS_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [adchs::R](R) reader structure"]
impl crate::Readable for ADCHS_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [adchs::W](W) writer structure"]
impl crate::Writable for ADCHS_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ADCHS to value 0"]
impl crate::Resettable for ADCHS_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ADCMPR (rw) register accessor: an alias for `Reg<ADCMPR_SPEC>`"]
pub type ADCMPR = crate::Reg<adcmpr::ADCMPR_SPEC>;
#[doc = "A/D Analog Watchdog Compare Register"]
pub mod adcmpr {
#[doc = "Register `ADCMPR` reader"]
pub struct R(crate::R<ADCMPR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ADCMPR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ADCMPR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ADCMPR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ADCMPR` writer"]
pub struct W(crate::W<ADCMPR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ADCMPR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ADCMPR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ADCMPR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CMPLDATA` reader - "]
pub type CMPLDATA_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CMPLDATA` writer - "]
pub type CMPLDATA_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, ADCMPR_SPEC, u16, u16, 12, O>;
#[doc = "Field `CMPHDATA` reader - "]
pub type CMPHDATA_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CMPHDATA` writer - "]
pub type CMPHDATA_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, ADCMPR_SPEC, u16, u16, 12, O>;
impl R {
#[doc = "Bits 0:11"]
#[inline(always)]
pub fn cmpldata(&self) -> CMPLDATA_R {
CMPLDATA_R::new((self.bits & 0x0fff) as u16)
}
#[doc = "Bits 16:27"]
#[inline(always)]
pub fn cmphdata(&self) -> CMPHDATA_R {
CMPHDATA_R::new(((self.bits >> 16) & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:11"]
#[inline(always)]
#[must_use]
pub fn cmpldata(&mut self) -> CMPLDATA_W<0> {
CMPLDATA_W::new(self)
}
#[doc = "Bits 16:27"]
#[inline(always)]
#[must_use]
pub fn cmphdata(&mut self) -> CMPHDATA_W<16> {
CMPHDATA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "A/D Analog Watchdog Compare Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adcmpr](index.html) module"]
pub struct ADCMPR_SPEC;
impl crate::RegisterSpec for ADCMPR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [adcmpr::R](R) reader structure"]
impl crate::Readable for ADCMPR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [adcmpr::W](W) writer structure"]
impl crate::Writable for ADCMPR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ADCMPR to value 0"]
impl crate::Resettable for ADCMPR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ADSTA (rw) register accessor: an alias for `Reg<ADSTA_SPEC>`"]
pub type ADSTA = crate::Reg<adsta::ADSTA_SPEC>;
#[doc = "A/D Status Register"]
pub mod adsta {
#[doc = "Register `ADSTA` reader"]
pub struct R(crate::R<ADSTA_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ADSTA_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ADSTA_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ADSTA_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ADSTA` writer"]
pub struct W(crate::W<ADSTA_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ADSTA_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ADSTA_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ADSTA_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EOSIF` reader - "]
pub type EOSIF_R = crate::BitReader<bool>;
#[doc = "Field `EOSIF` writer - "]
pub type EOSIF_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ADSTA_SPEC, bool, O>;
#[doc = "Field `AWDIF` reader - "]
pub type AWDIF_R = crate::BitReader<bool>;
#[doc = "Field `AWDIF` writer - "]
pub type AWDIF_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ADSTA_SPEC, bool, O>;
#[doc = "Field `BUSY` reader - "]
pub type BUSY_R = crate::BitReader<bool>;
#[doc = "Field `CHANNELH` reader - "]
pub type CHANNELH_R = crate::BitReader<bool>;
#[doc = "Field `CHANNELL` reader - "]
pub type CHANNELL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `VALID` reader - "]
pub type VALID_R = crate::FieldReader<u16, u16>;
#[doc = "Field `OVERRUN` reader - "]
pub type OVERRUN_R = crate::FieldReader<u16, u16>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn eosif(&self) -> EOSIF_R {
EOSIF_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn awdif(&self) -> AWDIF_R {
AWDIF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn busy(&self) -> BUSY_R {
BUSY_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn channelh(&self) -> CHANNELH_R {
CHANNELH_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn channell(&self) -> CHANNELL_R {
CHANNELL_R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:19"]
#[inline(always)]
pub fn valid(&self) -> VALID_R {
VALID_R::new(((self.bits >> 8) & 0x0fff) as u16)
}
#[doc = "Bits 20:31"]
#[inline(always)]
pub fn overrun(&self) -> OVERRUN_R {
OVERRUN_R::new(((self.bits >> 20) & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn eosif(&mut self) -> EOSIF_W<0> {
EOSIF_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn awdif(&mut self) -> AWDIF_W<1> {
AWDIF_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "A/D Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adsta](index.html) module"]
pub struct ADSTA_SPEC;
impl crate::RegisterSpec for ADSTA_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [adsta::R](R) reader structure"]
impl crate::Readable for ADSTA_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [adsta::W](W) writer structure"]
impl crate::Writable for ADSTA_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x03;
}
#[doc = "`reset()` method sets ADSTA to value 0"]
impl crate::Resettable for ADSTA_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ADDR0 (r) register accessor: an alias for `Reg<ADDR0_SPEC>`"]
pub type ADDR0 = crate::Reg<addr0::ADDR0_SPEC>;
#[doc = "A/D Channel Data Register"]
pub mod addr0 {
#[doc = "Register `ADDR0` reader"]
pub struct R(crate::R<ADDR0_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ADDR0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ADDR0_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ADDR0_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `DATA` reader - "]
pub type DATA_R = crate::FieldReader<u16, u16>;
#[doc = "Field `OVERRUN` reader - "]
pub type OVERRUN_R = crate::BitReader<bool>;
#[doc = "Field `VALID` reader - "]
pub type VALID_R = crate::BitReader<bool>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn data(&self) -> DATA_R {
DATA_R::new((self.bits & 0xffff) as u16)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn overrun(&self) -> OVERRUN_R {
OVERRUN_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn valid(&self) -> VALID_R {
VALID_R::new(((self.bits >> 21) & 1) != 0)
}
}
#[doc = "A/D Channel Data Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr0](index.html) module"]
pub struct ADDR0_SPEC;
impl crate::RegisterSpec for ADDR0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [addr0::R](R) reader structure"]
impl crate::Readable for ADDR0_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets ADDR0 to value 0"]
impl crate::Resettable for ADDR0_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
pub use addr0 as addr1;
pub use addr0 as addr2;
pub use addr0 as addr3;
pub use addr0 as addr4;
pub use addr0 as addr5;
pub use addr0 as addr6;
pub use addr0 as addr7;
pub use addr0 as addr8;
pub use addr0 as addr9;
pub use addr0 as addr10;
pub use addr0 as addr11;
pub use addr0 as addr12;
pub use addr0 as addr13;
pub use addr0 as addr14;
pub use addr0 as addr15;
pub use ADDR0 as ADDR1;
pub use ADDR0 as ADDR2;
pub use ADDR0 as ADDR3;
pub use ADDR0 as ADDR4;
pub use ADDR0 as ADDR5;
pub use ADDR0 as ADDR6;
pub use ADDR0 as ADDR7;
pub use ADDR0 as ADDR8;
pub use ADDR0 as ADDR9;
pub use ADDR0 as ADDR10;
pub use ADDR0 as ADDR11;
pub use ADDR0 as ADDR12;
pub use ADDR0 as ADDR13;
pub use ADDR0 as ADDR14;
pub use ADDR0 as ADDR15;
#[doc = "ADSTA_EXT (rw) register accessor: an alias for `Reg<ADSTA_EXT_SPEC>`"]
pub type ADSTA_EXT = crate::Reg<adsta_ext::ADSTA_EXT_SPEC>;
#[doc = "A/D Extended Status Register"]
pub mod adsta_ext {
#[doc = "Register `ADSTA_EXT` reader"]
pub struct R(crate::R<ADSTA_EXT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ADSTA_EXT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ADSTA_EXT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ADSTA_EXT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ADSTA_EXT` writer"]
pub struct W(crate::W<ADSTA_EXT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ADSTA_EXT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ADSTA_EXT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ADSTA_EXT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `VALID` reader - "]
pub type VALID_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OVERRUN` reader - "]
pub type OVERRUN_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EOSMPIF` reader - "]
pub type EOSMPIF_R = crate::BitReader<bool>;
#[doc = "Field `EOSMPIF` writer - "]
pub type EOSMPIF_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ADSTA_EXT_SPEC, bool, O>;
#[doc = "Field `EOCIF` reader - "]
pub type EOCIF_R = crate::BitReader<bool>;
#[doc = "Field `EOCIF` writer - "]
pub type EOCIF_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ADSTA_EXT_SPEC, bool, O>;
#[doc = "Field `JEOSMPIF` reader - "]
pub type JEOSMPIF_R = crate::BitReader<bool>;
#[doc = "Field `JEOSMPIF` writer - "]
pub type JEOSMPIF_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ADSTA_EXT_SPEC, bool, O>;
#[doc = "Field `JEOCIF` reader - "]
pub type JEOCIF_R = crate::BitReader<bool>;
#[doc = "Field `JEOCIF` writer - "]
pub type JEOCIF_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ADSTA_EXT_SPEC, bool, O>;
#[doc = "Field `JEOSIF` reader - "]
pub type JEOSIF_R = crate::BitReader<bool>;
#[doc = "Field `JEOSIF` writer - "]
pub type JEOSIF_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ADSTA_EXT_SPEC, bool, O>;
#[doc = "Field `JBUSY` reader - "]
pub type JBUSY_R = crate::BitReader<bool>;
#[doc = "Field `EOCALIF` reader - "]
pub type EOCALIF_R = crate::BitReader<bool>;
#[doc = "Field `EOCALIF` writer - "]
pub type EOCALIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADSTA_EXT_SPEC, bool, O>;
#[doc = "Field `CALBUSY` reader - "]
pub type CALBUSY_R = crate::BitReader<bool>;
#[doc = "Field `CALBUSY` writer - "]
pub type CALBUSY_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADSTA_EXT_SPEC, bool, O>;
#[doc = "Field `FREOCIF` reader - "]
pub type FREOCIF_R = crate::BitReader<bool>;
#[doc = "Field `FREOCIF` writer - "]
pub type FREOCIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADSTA_EXT_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn valid(&self) -> VALID_R {
VALID_R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn overrun(&self) -> OVERRUN_R {
OVERRUN_R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn eosmpif(&self) -> EOSMPIF_R {
EOSMPIF_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn eocif(&self) -> EOCIF_R {
EOCIF_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn jeosmpif(&self) -> JEOSMPIF_R {
JEOSMPIF_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn jeocif(&self) -> JEOCIF_R {
JEOCIF_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn jeosif(&self) -> JEOSIF_R {
JEOSIF_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn jbusy(&self) -> JBUSY_R {
JBUSY_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn eocalif(&self) -> EOCALIF_R {
EOCALIF_R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn calbusy(&self) -> CALBUSY_R {
CALBUSY_R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26"]
#[inline(always)]
pub fn freocif(&self) -> FREOCIF_R {
FREOCIF_R::new(((self.bits >> 26) & 1) != 0)
}
}
impl W {
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn eosmpif(&mut self) -> EOSMPIF_W<16> {
EOSMPIF_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn eocif(&mut self) -> EOCIF_W<17> {
EOCIF_W::new(self)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn jeosmpif(&mut self) -> JEOSMPIF_W<18> {
JEOSMPIF_W::new(self)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn jeocif(&mut self) -> JEOCIF_W<19> {
JEOCIF_W::new(self)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn jeosif(&mut self) -> JEOSIF_W<20> {
JEOSIF_W::new(self)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn eocalif(&mut self) -> EOCALIF_W<24> {
EOCALIF_W::new(self)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn calbusy(&mut self) -> CALBUSY_W<25> {
CALBUSY_W::new(self)
}
#[doc = "Bit 26"]
#[inline(always)]
#[must_use]
pub fn freocif(&mut self) -> FREOCIF_W<26> {
FREOCIF_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "A/D Extended Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adsta_ext](index.html) module"]
pub struct ADSTA_EXT_SPEC;
impl crate::RegisterSpec for ADSTA_EXT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [adsta_ext::R](R) reader structure"]
impl crate::Readable for ADSTA_EXT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [adsta_ext::W](W) writer structure"]
impl crate::Writable for ADSTA_EXT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x001f_0000;
}
#[doc = "`reset()` method sets ADSTA_EXT to value 0"]
impl crate::Resettable for ADSTA_EXT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CHANY0 (rw) register accessor: an alias for `Reg<CHANY0_SPEC>`"]
pub type CHANY0 = crate::Reg<chany0::CHANY0_SPEC>;
#[doc = "A/D any channel channel select register 0"]
pub mod chany0 {
#[doc = "Register `CHANY0` reader"]
pub struct R(crate::R<CHANY0_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CHANY0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CHANY0_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CHANY0_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CHANY0` writer"]
pub struct W(crate::W<CHANY0_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CHANY0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CHANY0_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CHANY0_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CHANY_SELL0` reader - "]
pub type CHANY_SELL0_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHANY_SELL0` writer - "]
pub type CHANY_SELL0_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CHANY0_SPEC, u8, u8, 4, O>;
#[doc = "Field `CHANY_SELL1` reader - "]
pub type CHANY_SELL1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHANY_SELL1` writer - "]
pub type CHANY_SELL1_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CHANY0_SPEC, u8, u8, 4, O>;
#[doc = "Field `CHANY_SELL2` reader - "]
pub type CHANY_SELL2_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHANY_SELL2` writer - "]
pub type CHANY_SELL2_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CHANY0_SPEC, u8, u8, 4, O>;
#[doc = "Field `CHANY_SELL3` reader - "]
pub type CHANY_SELL3_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHANY_SELL3` writer - "]
pub type CHANY_SELL3_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CHANY0_SPEC, u8, u8, 4, O>;
#[doc = "Field `CHANY_SELL4` reader - "]
pub type CHANY_SELL4_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHANY_SELL4` writer - "]
pub type CHANY_SELL4_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CHANY0_SPEC, u8, u8, 4, O>;
#[doc = "Field `CHANY_SELL5` reader - "]
pub type CHANY_SELL5_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHANY_SELL5` writer - "]
pub type CHANY_SELL5_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CHANY0_SPEC, u8, u8, 4, O>;
#[doc = "Field `CHANY_SELL6` reader - "]
pub type CHANY_SELL6_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHANY_SELL6` writer - "]
pub type CHANY_SELL6_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CHANY0_SPEC, u8, u8, 4, O>;
#[doc = "Field `CHANY_SELL7` reader - "]
pub type CHANY_SELL7_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHANY_SELL7` writer - "]
pub type CHANY_SELL7_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CHANY0_SPEC, u8, u8, 4, O>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn chany_sell0(&self) -> CHANY_SELL0_R {
CHANY_SELL0_R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn chany_sell1(&self) -> CHANY_SELL1_R {
CHANY_SELL1_R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:11"]
#[inline(always)]
pub fn chany_sell2(&self) -> CHANY_SELL2_R {
CHANY_SELL2_R::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bits 12:15"]
#[inline(always)]
pub fn chany_sell3(&self) -> CHANY_SELL3_R {
CHANY_SELL3_R::new(((self.bits >> 12) & 0x0f) as u8)
}
#[doc = "Bits 16:19"]
#[inline(always)]
pub fn chany_sell4(&self) -> CHANY_SELL4_R {
CHANY_SELL4_R::new(((self.bits >> 16) & 0x0f) as u8)
}
#[doc = "Bits 20:23"]
#[inline(always)]
pub fn chany_sell5(&self) -> CHANY_SELL5_R {
CHANY_SELL5_R::new(((self.bits >> 20) & 0x0f) as u8)
}
#[doc = "Bits 24:27"]
#[inline(always)]
pub fn chany_sell6(&self) -> CHANY_SELL6_R {
CHANY_SELL6_R::new(((self.bits >> 24) & 0x0f) as u8)
}
#[doc = "Bits 28:31"]
#[inline(always)]
pub fn chany_sell7(&self) -> CHANY_SELL7_R {
CHANY_SELL7_R::new(((self.bits >> 28) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn chany_sell0(&mut self) -> CHANY_SELL0_W<0> {
CHANY_SELL0_W::new(self)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn chany_sell1(&mut self) -> CHANY_SELL1_W<4> {
CHANY_SELL1_W::new(self)
}
#[doc = "Bits 8:11"]
#[inline(always)]
#[must_use]
pub fn chany_sell2(&mut self) -> CHANY_SELL2_W<8> {
CHANY_SELL2_W::new(self)
}
#[doc = "Bits 12:15"]
#[inline(always)]
#[must_use]
pub fn chany_sell3(&mut self) -> CHANY_SELL3_W<12> {
CHANY_SELL3_W::new(self)
}
#[doc = "Bits 16:19"]
#[inline(always)]
#[must_use]
pub fn chany_sell4(&mut self) -> CHANY_SELL4_W<16> {
CHANY_SELL4_W::new(self)
}
#[doc = "Bits 20:23"]
#[inline(always)]
#[must_use]
pub fn chany_sell5(&mut self) -> CHANY_SELL5_W<20> {
CHANY_SELL5_W::new(self)
}
#[doc = "Bits 24:27"]
#[inline(always)]
#[must_use]
pub fn chany_sell6(&mut self) -> CHANY_SELL6_W<24> {
CHANY_SELL6_W::new(self)
}
#[doc = "Bits 28:31"]
#[inline(always)]
#[must_use]
pub fn chany_sell7(&mut self) -> CHANY_SELL7_W<28> {
CHANY_SELL7_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "A/D any channel channel select register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chany0](index.html) module"]
pub struct CHANY0_SPEC;
impl crate::RegisterSpec for CHANY0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [chany0::R](R) reader structure"]
impl crate::Readable for CHANY0_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [chany0::W](W) writer structure"]
impl crate::Writable for CHANY0_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CHANY0 to value 0"]
impl crate::Resettable for CHANY0_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CHANY1 (rw) register accessor: an alias for `Reg<CHANY1_SPEC>`"]
pub type CHANY1 = crate::Reg<chany1::CHANY1_SPEC>;
#[doc = "A/D arbitrary channel channel selection register 1"]
pub mod chany1 {
#[doc = "Register `CHANY1` reader"]
pub struct R(crate::R<CHANY1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CHANY1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CHANY1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CHANY1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CHANY1` writer"]
pub struct W(crate::W<CHANY1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CHANY1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CHANY1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CHANY1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CHANY_SELL8` reader - "]
pub type CHANY_SELL8_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHANY_SELL8` writer - "]
pub type CHANY_SELL8_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CHANY1_SPEC, u8, u8, 4, O>;
#[doc = "Field `CHANY_SELL9` reader - "]
pub type CHANY_SELL9_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHANY_SELL9` writer - "]
pub type CHANY_SELL9_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CHANY1_SPEC, u8, u8, 4, O>;
#[doc = "Field `CHANY_SELL10` reader - "]
pub type CHANY_SELL10_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHANY_SELL10` writer - "]
pub type CHANY_SELL10_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CHANY1_SPEC, u8, u8, 4, O>;
#[doc = "Field `CHANY_SELL11` reader - "]
pub type CHANY_SELL11_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHANY_SELL11` writer - "]
pub type CHANY_SELL11_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CHANY1_SPEC, u8, u8, 4, O>;
#[doc = "Field `CHANY_SELL12` reader - "]
pub type CHANY_SELL12_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHANY_SELL12` writer - "]
pub type CHANY_SELL12_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CHANY1_SPEC, u8, u8, 4, O>;
#[doc = "Field `CHANY_SELL13` reader - "]
pub type CHANY_SELL13_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHANY_SELL13` writer - "]
pub type CHANY_SELL13_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CHANY1_SPEC, u8, u8, 4, O>;
#[doc = "Field `CHANY_SELL14` reader - "]
pub type CHANY_SELL14_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHANY_SELL14` writer - "]
pub type CHANY_SELL14_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CHANY1_SPEC, u8, u8, 4, O>;
#[doc = "Field `CHANY_SELL15` reader - "]
pub type CHANY_SELL15_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHANY_SELL15` writer - "]
pub type CHANY_SELL15_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CHANY1_SPEC, u8, u8, 4, O>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn chany_sell8(&self) -> CHANY_SELL8_R {
CHANY_SELL8_R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn chany_sell9(&self) -> CHANY_SELL9_R {
CHANY_SELL9_R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:11"]
#[inline(always)]
pub fn chany_sell10(&self) -> CHANY_SELL10_R {
CHANY_SELL10_R::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bits 12:15"]
#[inline(always)]
pub fn chany_sell11(&self) -> CHANY_SELL11_R {
CHANY_SELL11_R::new(((self.bits >> 12) & 0x0f) as u8)
}
#[doc = "Bits 16:19"]
#[inline(always)]
pub fn chany_sell12(&self) -> CHANY_SELL12_R {
CHANY_SELL12_R::new(((self.bits >> 16) & 0x0f) as u8)
}
#[doc = "Bits 20:23"]
#[inline(always)]
pub fn chany_sell13(&self) -> CHANY_SELL13_R {
CHANY_SELL13_R::new(((self.bits >> 20) & 0x0f) as u8)
}
#[doc = "Bits 24:27"]
#[inline(always)]
pub fn chany_sell14(&self) -> CHANY_SELL14_R {
CHANY_SELL14_R::new(((self.bits >> 24) & 0x0f) as u8)
}
#[doc = "Bits 28:31"]
#[inline(always)]
pub fn chany_sell15(&self) -> CHANY_SELL15_R {
CHANY_SELL15_R::new(((self.bits >> 28) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn chany_sell8(&mut self) -> CHANY_SELL8_W<0> {
CHANY_SELL8_W::new(self)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn chany_sell9(&mut self) -> CHANY_SELL9_W<4> {
CHANY_SELL9_W::new(self)
}
#[doc = "Bits 8:11"]
#[inline(always)]
#[must_use]
pub fn chany_sell10(&mut self) -> CHANY_SELL10_W<8> {
CHANY_SELL10_W::new(self)
}
#[doc = "Bits 12:15"]
#[inline(always)]
#[must_use]
pub fn chany_sell11(&mut self) -> CHANY_SELL11_W<12> {
CHANY_SELL11_W::new(self)
}
#[doc = "Bits 16:19"]
#[inline(always)]
#[must_use]
pub fn chany_sell12(&mut self) -> CHANY_SELL12_W<16> {
CHANY_SELL12_W::new(self)
}
#[doc = "Bits 20:23"]
#[inline(always)]
#[must_use]
pub fn chany_sell13(&mut self) -> CHANY_SELL13_W<20> {
CHANY_SELL13_W::new(self)
}
#[doc = "Bits 24:27"]
#[inline(always)]
#[must_use]
pub fn chany_sell14(&mut self) -> CHANY_SELL14_W<24> {
CHANY_SELL14_W::new(self)
}
#[doc = "Bits 28:31"]
#[inline(always)]
#[must_use]
pub fn chany_sell15(&mut self) -> CHANY_SELL15_W<28> {
CHANY_SELL15_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "A/D arbitrary channel channel selection register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chany1](index.html) module"]
pub struct CHANY1_SPEC;
impl crate::RegisterSpec for CHANY1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [chany1::R](R) reader structure"]
impl crate::Readable for CHANY1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [chany1::W](W) writer structure"]
impl crate::Writable for CHANY1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CHANY1 to value 0"]
impl crate::Resettable for CHANY1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ANY_CFG (rw) register accessor: an alias for `Reg<ANY_CFG_SPEC>`"]
pub type ANY_CFG = crate::Reg<any_cfg::ANY_CFG_SPEC>;
#[doc = "A/D Arbitrary Channel Configuration Register"]
pub mod any_cfg {
#[doc = "Register `ANY_CFG` reader"]
pub struct R(crate::R<ANY_CFG_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ANY_CFG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ANY_CFG_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ANY_CFG_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ANY_CFG` writer"]
pub struct W(crate::W<ANY_CFG_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ANY_CFG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ANY_CFG_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ANY_CFG_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CHANY_NUM` reader - "]
pub type CHANY_NUM_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHANY_NUM` writer - "]
pub type CHANY_NUM_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, ANY_CFG_SPEC, u8, u8, 4, O>;
#[doc = "Field `CHANY_SELH0` reader - "]
pub type CHANY_SELH0_R = crate::BitReader<bool>;
#[doc = "Field `CHANY_SELH0` writer - "]
pub type CHANY_SELH0_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CFG_SPEC, bool, O>;
#[doc = "Field `CHANY_SELH1` reader - "]
pub type CHANY_SELH1_R = crate::BitReader<bool>;
#[doc = "Field `CHANY_SELH1` writer - "]
pub type CHANY_SELH1_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CFG_SPEC, bool, O>;
#[doc = "Field `CHANY_SELH2` reader - "]
pub type CHANY_SELH2_R = crate::BitReader<bool>;
#[doc = "Field `CHANY_SELH2` writer - "]
pub type CHANY_SELH2_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CFG_SPEC, bool, O>;
#[doc = "Field `CHANY_SELH3` reader - "]
pub type CHANY_SELH3_R = crate::BitReader<bool>;
#[doc = "Field `CHANY_SELH3` writer - "]
pub type CHANY_SELH3_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CFG_SPEC, bool, O>;
#[doc = "Field `CHANY_SELH4` reader - "]
pub type CHANY_SELH4_R = crate::BitReader<bool>;
#[doc = "Field `CHANY_SELH4` writer - "]
pub type CHANY_SELH4_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CFG_SPEC, bool, O>;
#[doc = "Field `CHANY_SELH5` reader - "]
pub type CHANY_SELH5_R = crate::BitReader<bool>;
#[doc = "Field `CHANY_SELH5` writer - "]
pub type CHANY_SELH5_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CFG_SPEC, bool, O>;
#[doc = "Field `CHANY_SELH6` reader - "]
pub type CHANY_SELH6_R = crate::BitReader<bool>;
#[doc = "Field `CHANY_SELH6` writer - "]
pub type CHANY_SELH6_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CFG_SPEC, bool, O>;
#[doc = "Field `CHANY_SELH7` reader - "]
pub type CHANY_SELH7_R = crate::BitReader<bool>;
#[doc = "Field `CHANY_SELH7` writer - "]
pub type CHANY_SELH7_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CFG_SPEC, bool, O>;
#[doc = "Field `CHANY_SELH8` reader - "]
pub type CHANY_SELH8_R = crate::BitReader<bool>;
#[doc = "Field `CHANY_SELH8` writer - "]
pub type CHANY_SELH8_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CFG_SPEC, bool, O>;
#[doc = "Field `CHANY_SELH9` reader - "]
pub type CHANY_SELH9_R = crate::BitReader<bool>;
#[doc = "Field `CHANY_SELH9` writer - "]
pub type CHANY_SELH9_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CFG_SPEC, bool, O>;
#[doc = "Field `CHANY_SELH10` reader - "]
pub type CHANY_SELH10_R = crate::BitReader<bool>;
#[doc = "Field `CHANY_SELH10` writer - "]
pub type CHANY_SELH10_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CFG_SPEC, bool, O>;
#[doc = "Field `CHANY_SELH11` reader - "]
pub type CHANY_SELH11_R = crate::BitReader<bool>;
#[doc = "Field `CHANY_SELH11` writer - "]
pub type CHANY_SELH11_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CFG_SPEC, bool, O>;
#[doc = "Field `CHANY_SELH12` reader - "]
pub type CHANY_SELH12_R = crate::BitReader<bool>;
#[doc = "Field `CHANY_SELH12` writer - "]
pub type CHANY_SELH12_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CFG_SPEC, bool, O>;
#[doc = "Field `CHANY_SELH13` reader - "]
pub type CHANY_SELH13_R = crate::BitReader<bool>;
#[doc = "Field `CHANY_SELH13` writer - "]
pub type CHANY_SELH13_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CFG_SPEC, bool, O>;
#[doc = "Field `CHANY_SELH14` reader - "]
pub type CHANY_SELH14_R = crate::BitReader<bool>;
#[doc = "Field `CHANY_SELH14` writer - "]
pub type CHANY_SELH14_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CFG_SPEC, bool, O>;
#[doc = "Field `CHANY_SELH15` reader - "]
pub type CHANY_SELH15_R = crate::BitReader<bool>;
#[doc = "Field `CHANY_SELH15` writer - "]
pub type CHANY_SELH15_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CFG_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn chany_num(&self) -> CHANY_NUM_R {
CHANY_NUM_R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn chany_selh0(&self) -> CHANY_SELH0_R {
CHANY_SELH0_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn chany_selh1(&self) -> CHANY_SELH1_R {
CHANY_SELH1_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn chany_selh2(&self) -> CHANY_SELH2_R {
CHANY_SELH2_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn chany_selh3(&self) -> CHANY_SELH3_R {
CHANY_SELH3_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn chany_selh4(&self) -> CHANY_SELH4_R {
CHANY_SELH4_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn chany_selh5(&self) -> CHANY_SELH5_R {
CHANY_SELH5_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn chany_selh6(&self) -> CHANY_SELH6_R {
CHANY_SELH6_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn chany_selh7(&self) -> CHANY_SELH7_R {
CHANY_SELH7_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn chany_selh8(&self) -> CHANY_SELH8_R {
CHANY_SELH8_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn chany_selh9(&self) -> CHANY_SELH9_R {
CHANY_SELH9_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn chany_selh10(&self) -> CHANY_SELH10_R {
CHANY_SELH10_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn chany_selh11(&self) -> CHANY_SELH11_R {
CHANY_SELH11_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn chany_selh12(&self) -> CHANY_SELH12_R {
CHANY_SELH12_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn chany_selh13(&self) -> CHANY_SELH13_R {
CHANY_SELH13_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn chany_selh14(&self) -> CHANY_SELH14_R {
CHANY_SELH14_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23"]
#[inline(always)]
pub fn chany_selh15(&self) -> CHANY_SELH15_R {
CHANY_SELH15_R::new(((self.bits >> 23) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn chany_num(&mut self) -> CHANY_NUM_W<0> {
CHANY_NUM_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn chany_selh0(&mut self) -> CHANY_SELH0_W<8> {
CHANY_SELH0_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn chany_selh1(&mut self) -> CHANY_SELH1_W<9> {
CHANY_SELH1_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn chany_selh2(&mut self) -> CHANY_SELH2_W<10> {
CHANY_SELH2_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn chany_selh3(&mut self) -> CHANY_SELH3_W<11> {
CHANY_SELH3_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn chany_selh4(&mut self) -> CHANY_SELH4_W<12> {
CHANY_SELH4_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn chany_selh5(&mut self) -> CHANY_SELH5_W<13> {
CHANY_SELH5_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn chany_selh6(&mut self) -> CHANY_SELH6_W<14> {
CHANY_SELH6_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn chany_selh7(&mut self) -> CHANY_SELH7_W<15> {
CHANY_SELH7_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn chany_selh8(&mut self) -> CHANY_SELH8_W<16> {
CHANY_SELH8_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn chany_selh9(&mut self) -> CHANY_SELH9_W<17> {
CHANY_SELH9_W::new(self)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn chany_selh10(&mut self) -> CHANY_SELH10_W<18> {
CHANY_SELH10_W::new(self)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn chany_selh11(&mut self) -> CHANY_SELH11_W<19> {
CHANY_SELH11_W::new(self)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn chany_selh12(&mut self) -> CHANY_SELH12_W<20> {
CHANY_SELH12_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn chany_selh13(&mut self) -> CHANY_SELH13_W<21> {
CHANY_SELH13_W::new(self)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn chany_selh14(&mut self) -> CHANY_SELH14_W<22> {
CHANY_SELH14_W::new(self)
}
#[doc = "Bit 23"]
#[inline(always)]
#[must_use]
pub fn chany_selh15(&mut self) -> CHANY_SELH15_W<23> {
CHANY_SELH15_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "A/D Arbitrary Channel Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [any_cfg](index.html) module"]
pub struct ANY_CFG_SPEC;
impl crate::RegisterSpec for ANY_CFG_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [any_cfg::R](R) reader structure"]
impl crate::Readable for ANY_CFG_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [any_cfg::W](W) writer structure"]
impl crate::Writable for ANY_CFG_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ANY_CFG to value 0"]
impl crate::Resettable for ANY_CFG_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ANY_CR (rw) register accessor: an alias for `Reg<ANY_CR_SPEC>`"]
pub type ANY_CR = crate::Reg<any_cr::ANY_CR_SPEC>;
#[doc = "A/D arbitrary channel control register"]
pub mod any_cr {
#[doc = "Register `ANY_CR` reader"]
pub struct R(crate::R<ANY_CR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ANY_CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ANY_CR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ANY_CR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ANY_CR` writer"]
pub struct W(crate::W<ANY_CR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ANY_CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ANY_CR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ANY_CR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CHANY_MDEN` reader - "]
pub type CHANY_MDEN_R = crate::BitReader<bool>;
#[doc = "Field `CHANY_MDEN` writer - "]
pub type CHANY_MDEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CR_SPEC, bool, O>;
#[doc = "Field `JCEN` reader - "]
pub type JCEN_R = crate::BitReader<bool>;
#[doc = "Field `JCEN` writer - "]
pub type JCEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CR_SPEC, bool, O>;
#[doc = "Field `JEOSMPIE` reader - "]
pub type JEOSMPIE_R = crate::BitReader<bool>;
#[doc = "Field `JEOSMPIE` writer - "]
pub type JEOSMPIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CR_SPEC, bool, O>;
#[doc = "Field `JEOCIE` reader - "]
pub type JEOCIE_R = crate::BitReader<bool>;
#[doc = "Field `JEOCIE` writer - "]
pub type JEOCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CR_SPEC, bool, O>;
#[doc = "Field `JEOSIE` reader - "]
pub type JEOSIE_R = crate::BitReader<bool>;
#[doc = "Field `JEOSIE` writer - "]
pub type JEOSIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CR_SPEC, bool, O>;
#[doc = "Field `JAUTO` reader - "]
pub type JAUTO_R = crate::BitReader<bool>;
#[doc = "Field `JAUTO` writer - "]
pub type JAUTO_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CR_SPEC, bool, O>;
#[doc = "Field `JADST` reader - "]
pub type JADST_R = crate::BitReader<bool>;
#[doc = "Field `JADST` writer - "]
pub type JADST_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CR_SPEC, bool, O>;
#[doc = "Field `JTRGEN` reader - "]
pub type JTRGEN_R = crate::BitReader<bool>;
#[doc = "Field `JTRGEN` writer - "]
pub type JTRGEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CR_SPEC, bool, O>;
#[doc = "Field `JTRGSHIFT` reader - "]
pub type JTRGSHIFT_R = crate::FieldReader<u8, u8>;
#[doc = "Field `JTRGSHIFT` writer - "]
pub type JTRGSHIFT_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, ANY_CR_SPEC, u8, u8, 3, O>;
#[doc = "Field `JTRG_EDGE` reader - "]
pub type JTRG_EDGE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `JTRG_EDGE` writer - "]
pub type JTRG_EDGE_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, ANY_CR_SPEC, u8, u8, 2, O>;
#[doc = "Field `ADCAL` reader - "]
pub type ADCAL_R = crate::BitReader<bool>;
#[doc = "Field `ADCAL` writer - "]
pub type ADCAL_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CR_SPEC, bool, O>;
#[doc = "Field `EOCALIE` reader - "]
pub type EOCALIE_R = crate::BitReader<bool>;
#[doc = "Field `EOCALIE` writer - "]
pub type EOCALIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ANY_CR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn chany_mden(&self) -> CHANY_MDEN_R {
CHANY_MDEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn jcen(&self) -> JCEN_R {
JCEN_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn jeosmpie(&self) -> JEOSMPIE_R {
JEOSMPIE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn jeocie(&self) -> JEOCIE_R {
JEOCIE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn jeosie(&self) -> JEOSIE_R {
JEOSIE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn jauto(&self) -> JAUTO_R {
JAUTO_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn jadst(&self) -> JADST_R {
JADST_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn jtrgen(&self) -> JTRGEN_R {
JTRGEN_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 13:15"]
#[inline(always)]
pub fn jtrgshift(&self) -> JTRGSHIFT_R {
JTRGSHIFT_R::new(((self.bits >> 13) & 7) as u8)
}
#[doc = "Bits 16:17"]
#[inline(always)]
pub fn jtrg_edge(&self) -> JTRG_EDGE_R {
JTRG_EDGE_R::new(((self.bits >> 16) & 3) as u8)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn adcal(&self) -> ADCAL_R {
ADCAL_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn eocalie(&self) -> EOCALIE_R {
EOCALIE_R::new(((self.bits >> 21) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn chany_mden(&mut self) -> CHANY_MDEN_W<0> {
CHANY_MDEN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn jcen(&mut self) -> JCEN_W<1> {
JCEN_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn jeosmpie(&mut self) -> JEOSMPIE_W<2> {
JEOSMPIE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn jeocie(&mut self) -> JEOCIE_W<3> {
JEOCIE_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn jeosie(&mut self) -> JEOSIE_W<4> {
JEOSIE_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn jauto(&mut self) -> JAUTO_W<5> {
JAUTO_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn jadst(&mut self) -> JADST_W<6> {
JADST_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn jtrgen(&mut self) -> JTRGEN_W<7> {
JTRGEN_W::new(self)
}
#[doc = "Bits 13:15"]
#[inline(always)]
#[must_use]
pub fn jtrgshift(&mut self) -> JTRGSHIFT_W<13> {
JTRGSHIFT_W::new(self)
}
#[doc = "Bits 16:17"]
#[inline(always)]
#[must_use]
pub fn jtrg_edge(&mut self) -> JTRG_EDGE_W<16> {
JTRG_EDGE_W::new(self)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn adcal(&mut self) -> ADCAL_W<20> {
ADCAL_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn eocalie(&mut self) -> EOCALIE_W<21> {
EOCALIE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "A/D arbitrary channel control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [any_cr](index.html) module"]
pub struct ANY_CR_SPEC;
impl crate::RegisterSpec for ANY_CR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [any_cr::R](R) reader structure"]
impl crate::Readable for ANY_CR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [any_cr::W](W) writer structure"]
impl crate::Writable for ANY_CR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ANY_CR to value 0"]
impl crate::Resettable for ANY_CR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ADCFG2 (rw) register accessor: an alias for `Reg<ADCFG2_SPEC>`"]
pub type ADCFG2 = crate::Reg<adcfg2::ADCFG2_SPEC>;
#[doc = "ADC Configuration Register"]
pub mod adcfg2 {
#[doc = "Register `ADCFG2` reader"]
pub struct R(crate::R<ADCFG2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ADCFG2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ADCFG2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ADCFG2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ADCFG2` writer"]
pub struct W(crate::W<ADCFG2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ADCFG2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ADCFG2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ADCFG2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `ADCCR` reader - "]
pub type ADCCR_R = crate::BitReader<bool>;
#[doc = "Field `ADCCR` writer - "]
pub type ADCCR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCFG2_SPEC, bool, O>;
#[doc = "Field `ADCSREF` reader - "]
pub type ADCSREF_R = crate::BitReader<bool>;
#[doc = "Field `ADCSREF` writer - "]
pub type ADCSREF_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCFG2_SPEC, bool, O>;
#[doc = "Field `DC` reader - "]
pub type DC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DC` writer - "]
pub type DC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADCFG2_SPEC, u8, u8, 5, O>;
#[doc = "Field `PSDC` reader - "]
pub type PSDC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PSDC` writer - "]
pub type PSDC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADCFG2_SPEC, u8, u8, 5, O>;
#[doc = "Field `ROVSE` reader - "]
pub type ROVSE_R = crate::BitReader<bool>;
#[doc = "Field `ROVSE` writer - "]
pub type ROVSE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCFG2_SPEC, bool, O>;
#[doc = "Field `JOVSE` reader - "]
pub type JOVSE_R = crate::BitReader<bool>;
#[doc = "Field `JOVSE` writer - "]
pub type JOVSE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCFG2_SPEC, bool, O>;
#[doc = "Field `OVSR` reader - "]
pub type OVSR_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OVSR` writer - "]
pub type OVSR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADCFG2_SPEC, u8, u8, 3, O>;
#[doc = "Field `OVSS` reader - "]
pub type OVSS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OVSS` writer - "]
pub type OVSS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADCFG2_SPEC, u8, u8, 4, O>;
#[doc = "Field `TROVS` reader - "]
pub type TROVS_R = crate::BitReader<bool>;
#[doc = "Field `TROVS` writer - "]
pub type TROVS_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCFG2_SPEC, bool, O>;
#[doc = "Field `ROVSM` reader - "]
pub type ROVSM_R = crate::BitReader<bool>;
#[doc = "Field `ROVSM` writer - "]
pub type ROVSM_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCFG2_SPEC, bool, O>;
impl R {
#[doc = "Bit 1"]
#[inline(always)]
pub fn adccr(&self) -> ADCCR_R {
ADCCR_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn adcsref(&self) -> ADCSREF_R {
ADCSREF_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 4:8"]
#[inline(always)]
pub fn dc(&self) -> DC_R {
DC_R::new(((self.bits >> 4) & 0x1f) as u8)
}
#[doc = "Bits 10:14"]
#[inline(always)]
pub fn psdc(&self) -> PSDC_R {
PSDC_R::new(((self.bits >> 10) & 0x1f) as u8)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn rovse(&self) -> ROVSE_R {
ROVSE_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn jovse(&self) -> JOVSE_R {
JOVSE_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bits 18:20"]
#[inline(always)]
pub fn ovsr(&self) -> OVSR_R {
OVSR_R::new(((self.bits >> 18) & 7) as u8)
}
#[doc = "Bits 21:24"]
#[inline(always)]
pub fn ovss(&self) -> OVSS_R {
OVSS_R::new(((self.bits >> 21) & 0x0f) as u8)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn trovs(&self) -> TROVS_R {
TROVS_R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26"]
#[inline(always)]
pub fn rovsm(&self) -> ROVSM_R {
ROVSM_R::new(((self.bits >> 26) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn adccr(&mut self) -> ADCCR_W<1> {
ADCCR_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn adcsref(&mut self) -> ADCSREF_W<2> {
ADCSREF_W::new(self)
}
#[doc = "Bits 4:8"]
#[inline(always)]
#[must_use]
pub fn dc(&mut self) -> DC_W<4> {
DC_W::new(self)
}
#[doc = "Bits 10:14"]
#[inline(always)]
#[must_use]
pub fn psdc(&mut self) -> PSDC_W<10> {
PSDC_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn rovse(&mut self) -> ROVSE_W<16> {
ROVSE_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn jovse(&mut self) -> JOVSE_W<17> {
JOVSE_W::new(self)
}
#[doc = "Bits 18:20"]
#[inline(always)]
#[must_use]
pub fn ovsr(&mut self) -> OVSR_W<18> {
OVSR_W::new(self)
}
#[doc = "Bits 21:24"]
#[inline(always)]
#[must_use]
pub fn ovss(&mut self) -> OVSS_W<21> {
OVSS_W::new(self)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn trovs(&mut self) -> TROVS_W<25> {
TROVS_W::new(self)
}
#[doc = "Bit 26"]
#[inline(always)]
#[must_use]
pub fn rovsm(&mut self) -> ROVSM_W<26> {
ROVSM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "ADC Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adcfg2](index.html) module"]
pub struct ADCFG2_SPEC;
impl crate::RegisterSpec for ADCFG2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [adcfg2::R](R) reader structure"]
impl crate::Readable for ADCFG2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [adcfg2::W](W) writer structure"]
impl crate::Writable for ADCFG2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ADCFG2 to value 0x003e_0000"]
impl crate::Resettable for ADCFG2_SPEC {
const RESET_VALUE: Self::Ux = 0x003e_0000;
}
}
#[doc = "SMPR1 (rw) register accessor: an alias for `Reg<SMPR1_SPEC>`"]
pub type SMPR1 = crate::Reg<smpr1::SMPR1_SPEC>;
#[doc = "A/D Sampling Configuration Register 1"]
pub mod smpr1 {
#[doc = "Register `SMPR1` reader"]
pub struct R(crate::R<SMPR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SMPR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SMPR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SMPR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SMPR1` writer"]
pub struct W(crate::W<SMPR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SMPR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SMPR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SMPR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SAMP` reader - "]
pub type SAMP_R = crate::FieldReader<u32, u32>;
#[doc = "Field `SAMP` writer - "]
pub type SAMP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SMPR1_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn samp(&self) -> SAMP_R {
SAMP_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn samp(&mut self) -> SAMP_W<0> {
SAMP_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "A/D Sampling Configuration Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smpr1](index.html) module"]
pub struct SMPR1_SPEC;
impl crate::RegisterSpec for SMPR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [smpr1::R](R) reader structure"]
impl crate::Readable for SMPR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [smpr1::W](W) writer structure"]
impl crate::Writable for SMPR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SMPR1 to value 0"]
impl crate::Resettable for SMPR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SMPR2 (rw) register accessor: an alias for `Reg<SMPR2_SPEC>`"]
pub type SMPR2 = crate::Reg<smpr2::SMPR2_SPEC>;
#[doc = "A/D Sampling Configuration Register 2"]
pub mod smpr2 {
#[doc = "Register `SMPR2` reader"]
pub struct R(crate::R<SMPR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SMPR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SMPR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SMPR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SMPR2` writer"]
pub struct W(crate::W<SMPR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SMPR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SMPR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SMPR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SAMP` reader - "]
pub type SAMP_R = crate::FieldReader<u32, u32>;
#[doc = "Field `SAMP` writer - "]
pub type SAMP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SMPR2_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn samp(&self) -> SAMP_R {
SAMP_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn samp(&mut self) -> SAMP_W<0> {
SAMP_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "A/D Sampling Configuration Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smpr2](index.html) module"]
pub struct SMPR2_SPEC;
impl crate::RegisterSpec for SMPR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [smpr2::R](R) reader structure"]
impl crate::Readable for SMPR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [smpr2::W](W) writer structure"]
impl crate::Writable for SMPR2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SMPR2 to value 0"]
impl crate::Resettable for SMPR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "JOFR0 (rw) register accessor: an alias for `Reg<JOFR0_SPEC>`"]
pub type JOFR0 = crate::Reg<jofr0::JOFR0_SPEC>;
#[doc = "A/D Injection Channel Data Compensation Register"]
pub mod jofr0 {
#[doc = "Register `JOFR0` reader"]
pub struct R(crate::R<JOFR0_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<JOFR0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<JOFR0_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<JOFR0_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `JOFR0` writer"]
pub struct W(crate::W<JOFR0_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<JOFR0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<JOFR0_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<JOFR0_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `JOFFSET` reader - "]
pub type JOFFSET_R = crate::FieldReader<u16, u16>;
#[doc = "Field `JOFFSET` writer - "]
pub type JOFFSET_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, JOFR0_SPEC, u16, u16, 12, O>;
impl R {
#[doc = "Bits 0:11"]
#[inline(always)]
pub fn joffset(&self) -> JOFFSET_R {
JOFFSET_R::new((self.bits & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:11"]
#[inline(always)]
#[must_use]
pub fn joffset(&mut self) -> JOFFSET_W<0> {
JOFFSET_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "A/D Injection Channel Data Compensation Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [jofr0](index.html) module"]
pub struct JOFR0_SPEC;
impl crate::RegisterSpec for JOFR0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [jofr0::R](R) reader structure"]
impl crate::Readable for JOFR0_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [jofr0::W](W) writer structure"]
impl crate::Writable for JOFR0_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets JOFR0 to value 0"]
impl crate::Resettable for JOFR0_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
pub use jofr0 as jofr1;
pub use jofr0 as jofr2;
pub use jofr0 as jofr3;
pub use JOFR0 as JOFR1;
pub use JOFR0 as JOFR2;
pub use JOFR0 as JOFR3;
#[doc = "JSQR (rw) register accessor: an alias for `Reg<JSQR_SPEC>`"]
pub type JSQR = crate::Reg<jsqr::JSQR_SPEC>;
#[doc = "A/D injection channel sequence register"]
pub mod jsqr {
#[doc = "Register `JSQR` reader"]
pub struct R(crate::R<JSQR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<JSQR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<JSQR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<JSQR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `JSQR` writer"]
pub struct W(crate::W<JSQR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<JSQR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<JSQR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<JSQR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `JSQ0` reader - "]
pub type JSQ0_R = crate::FieldReader<u8, u8>;
#[doc = "Field `JSQ0` writer - "]
pub type JSQ0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, JSQR_SPEC, u8, u8, 5, O>;
#[doc = "Field `JSQ1` reader - "]
pub type JSQ1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `JSQ1` writer - "]
pub type JSQ1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, JSQR_SPEC, u8, u8, 5, O>;
#[doc = "Field `JSQ2` reader - "]
pub type JSQ2_R = crate::FieldReader<u8, u8>;
#[doc = "Field `JSQ2` writer - "]
pub type JSQ2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, JSQR_SPEC, u8, u8, 5, O>;
#[doc = "Field `JSQ3` reader - "]
pub type JSQ3_R = crate::FieldReader<u8, u8>;
#[doc = "Field `JSQ3` writer - "]
pub type JSQ3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, JSQR_SPEC, u8, u8, 5, O>;
#[doc = "Field `JNUM` reader - "]
pub type JNUM_R = crate::FieldReader<u8, u8>;
#[doc = "Field `JNUM` writer - "]
pub type JNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, JSQR_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bits 0:4"]
#[inline(always)]
pub fn jsq0(&self) -> JSQ0_R {
JSQ0_R::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 5:9"]
#[inline(always)]
pub fn jsq1(&self) -> JSQ1_R {
JSQ1_R::new(((self.bits >> 5) & 0x1f) as u8)
}
#[doc = "Bits 10:14"]
#[inline(always)]
pub fn jsq2(&self) -> JSQ2_R {
JSQ2_R::new(((self.bits >> 10) & 0x1f) as u8)
}
#[doc = "Bits 15:19"]
#[inline(always)]
pub fn jsq3(&self) -> JSQ3_R {
JSQ3_R::new(((self.bits >> 15) & 0x1f) as u8)
}
#[doc = "Bits 20:21"]
#[inline(always)]
pub fn jnum(&self) -> JNUM_R {
JNUM_R::new(((self.bits >> 20) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:4"]
#[inline(always)]
#[must_use]
pub fn jsq0(&mut self) -> JSQ0_W<0> {
JSQ0_W::new(self)
}
#[doc = "Bits 5:9"]
#[inline(always)]
#[must_use]
pub fn jsq1(&mut self) -> JSQ1_W<5> {
JSQ1_W::new(self)
}
#[doc = "Bits 10:14"]
#[inline(always)]
#[must_use]
pub fn jsq2(&mut self) -> JSQ2_W<10> {
JSQ2_W::new(self)
}
#[doc = "Bits 15:19"]
#[inline(always)]
#[must_use]
pub fn jsq3(&mut self) -> JSQ3_W<15> {
JSQ3_W::new(self)
}
#[doc = "Bits 20:21"]
#[inline(always)]
#[must_use]
pub fn jnum(&mut self) -> JNUM_W<20> {
JNUM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "A/D injection channel sequence register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [jsqr](index.html) module"]
pub struct JSQR_SPEC;
impl crate::RegisterSpec for JSQR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [jsqr::R](R) reader structure"]
impl crate::Readable for JSQR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [jsqr::W](W) writer structure"]
impl crate::Writable for JSQR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets JSQR to value 0"]
impl crate::Resettable for JSQR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "JADDATA (r) register accessor: an alias for `Reg<JADDATA_SPEC>`"]
pub type JADDATA = crate::Reg<jaddata::JADDATA_SPEC>;
#[doc = "A/D injection data register"]
pub mod jaddata {
#[doc = "Register `JADDATA` reader"]
pub struct R(crate::R<JADDATA_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<JADDATA_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<JADDATA_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<JADDATA_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `JDATA` reader - "]
pub type JDATA_R = crate::FieldReader<u16, u16>;
#[doc = "Field `JCHANNELSEL` reader - "]
pub type JCHANNELSEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `JOVERRUN` reader - "]
pub type JOVERRUN_R = crate::BitReader<bool>;
#[doc = "Field `JVALID` reader - "]
pub type JVALID_R = crate::BitReader<bool>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn jdata(&self) -> JDATA_R {
JDATA_R::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:20"]
#[inline(always)]
pub fn jchannelsel(&self) -> JCHANNELSEL_R {
JCHANNELSEL_R::new(((self.bits >> 16) & 0x1f) as u8)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn joverrun(&self) -> JOVERRUN_R {
JOVERRUN_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn jvalid(&self) -> JVALID_R {
JVALID_R::new(((self.bits >> 22) & 1) != 0)
}
}
#[doc = "A/D injection data register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [jaddata](index.html) module"]
pub struct JADDATA_SPEC;
impl crate::RegisterSpec for JADDATA_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [jaddata::R](R) reader structure"]
impl crate::Readable for JADDATA_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets JADDATA to value 0"]
impl crate::Resettable for JADDATA_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "JDR0 (r) register accessor: an alias for `Reg<JDR0_SPEC>`"]
pub type JDR0 = crate::Reg<jdr0::JDR0_SPEC>;
#[doc = "A/D injection channel data register"]
pub mod jdr0 {
#[doc = "Register `JDR0` reader"]
pub struct R(crate::R<JDR0_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<JDR0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<JDR0_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<JDR0_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `JDATA` reader - "]
pub type JDATA_R = crate::FieldReader<u16, u16>;
#[doc = "Field `JOVERRUN` reader - "]
pub type JOVERRUN_R = crate::BitReader<bool>;
#[doc = "Field `JVALID` reader - "]
pub type JVALID_R = crate::BitReader<bool>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn jdata(&self) -> JDATA_R {
JDATA_R::new((self.bits & 0xffff) as u16)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn joverrun(&self) -> JOVERRUN_R {
JOVERRUN_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn jvalid(&self) -> JVALID_R {
JVALID_R::new(((self.bits >> 22) & 1) != 0)
}
}
#[doc = "A/D injection channel data register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [jdr0](index.html) module"]
pub struct JDR0_SPEC;
impl crate::RegisterSpec for JDR0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [jdr0::R](R) reader structure"]
impl crate::Readable for JDR0_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets JDR0 to value 0"]
impl crate::Resettable for JDR0_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
pub use jdr0 as jdr1;
pub use jdr0 as jdr2;
pub use jdr0 as jdr3;
pub use JDR0 as JDR1;
pub use JDR0 as JDR2;
pub use JDR0 as JDR3;
}
#[doc = "ADC2"]
pub struct ADC2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for ADC2 {}
impl ADC2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const adc1::RegisterBlock = 0x4001_2800 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const adc1::RegisterBlock {
Self::PTR
}
}
impl Deref for ADC2 {
type Target = adc1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for ADC2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ADC2").finish()
}
}
#[doc = "ADC2"]
pub use self::adc1 as adc2;
#[doc = "BKP"]
pub struct BKP {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for BKP {}
impl BKP {
#[doc = r"Pointer to the register block"]
pub const PTR: *const bkp::RegisterBlock = 0x4000_2840 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const bkp::RegisterBlock {
Self::PTR
}
}
impl Deref for BKP {
type Target = bkp::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for BKP {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("BKP").finish()
}
}
#[doc = "BKP"]
pub mod bkp {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
_reserved0: [u8; 0x40],
#[doc = "0x40 - RTC Clock Calibration Register"]
pub rtccr: RTCCR,
#[doc = "0x44 - Backup Control Register"]
pub cr: CR,
#[doc = "0x48 - Backup Control Status Register"]
pub csr: CSR,
_reserved3: [u8; 0x04],
#[doc = "0x50 - Backup data register n"]
pub dr: DR,
}
#[doc = "RTCCR (rw) register accessor: an alias for `Reg<RTCCR_SPEC>`"]
pub type RTCCR = crate::Reg<rtccr::RTCCR_SPEC>;
#[doc = "RTC Clock Calibration Register"]
pub mod rtccr {
#[doc = "Register `RTCCR` reader"]
pub struct R(crate::R<RTCCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RTCCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RTCCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RTCCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `RTCCR` writer"]
pub struct W(crate::W<RTCCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<RTCCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<RTCCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<RTCCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CAL` reader - "]
pub type CAL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CAL` writer - "]
pub type CAL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RTCCR_SPEC, u8, u8, 7, O>;
#[doc = "Field `CCO` reader - "]
pub type CCO_R = crate::BitReader<bool>;
#[doc = "Field `CCO` writer - "]
pub type CCO_W<'a, const O: u8> = crate::BitWriter<'a, u32, RTCCR_SPEC, bool, O>;
#[doc = "Field `ASOE` reader - "]
pub type ASOE_R = crate::BitReader<bool>;
#[doc = "Field `ASOE` writer - "]
pub type ASOE_W<'a, const O: u8> = crate::BitWriter<'a, u32, RTCCR_SPEC, bool, O>;
#[doc = "Field `ASOS` reader - "]
pub type ASOS_R = crate::BitReader<bool>;
#[doc = "Field `ASOS` writer - "]
pub type ASOS_W<'a, const O: u8> = crate::BitWriter<'a, u32, RTCCR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:6"]
#[inline(always)]
pub fn cal(&self) -> CAL_R {
CAL_R::new((self.bits & 0x7f) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn cco(&self) -> CCO_R {
CCO_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn asoe(&self) -> ASOE_R {
ASOE_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn asos(&self) -> ASOS_R {
ASOS_R::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:6"]
#[inline(always)]
#[must_use]
pub fn cal(&mut self) -> CAL_W<0> {
CAL_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn cco(&mut self) -> CCO_W<7> {
CCO_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn asoe(&mut self) -> ASOE_W<8> {
ASOE_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn asos(&mut self) -> ASOS_W<9> {
ASOS_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "RTC Clock Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtccr](index.html) module"]
pub struct RTCCR_SPEC;
impl crate::RegisterSpec for RTCCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rtccr::R](R) reader structure"]
impl crate::Readable for RTCCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [rtccr::W](W) writer structure"]
impl crate::Writable for RTCCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets RTCCR to value 0"]
impl crate::Resettable for RTCCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CR (rw) register accessor: an alias for `Reg<CR_SPEC>`"]
pub type CR = crate::Reg<cr::CR_SPEC>;
#[doc = "Backup Control Register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub struct R(crate::R<CR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR` writer"]
pub struct W(crate::W<CR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TPE` reader - "]
pub type TPE_R = crate::BitReader<bool>;
#[doc = "Field `TPE` writer - "]
pub type TPE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `TPAL` reader - "]
pub type TPAL_R = crate::BitReader<bool>;
#[doc = "Field `TPAL` writer - "]
pub type TPAL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn tpe(&self) -> TPE_R {
TPE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn tpal(&self) -> TPAL_R {
TPAL_R::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn tpe(&mut self) -> TPE_W<0> {
TPE_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn tpal(&mut self) -> TPAL_W<1> {
TPAL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Backup Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"]
pub struct CR_SPEC;
impl crate::RegisterSpec for CR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr::R](R) reader structure"]
impl crate::Readable for CR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"]
impl crate::Writable for CR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CSR (rw) register accessor: an alias for `Reg<CSR_SPEC>`"]
pub type CSR = crate::Reg<csr::CSR_SPEC>;
#[doc = "Backup Control Status Register"]
pub mod csr {
#[doc = "Register `CSR` reader"]
pub struct R(crate::R<CSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CSR` writer"]
pub struct W(crate::W<CSR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CSR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CSR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CTE` writer - "]
pub type CTE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
#[doc = "Field `CTI` writer - "]
pub type CTI_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
#[doc = "Field `TPIE` reader - "]
pub type TPIE_R = crate::BitReader<bool>;
#[doc = "Field `TPIE` writer - "]
pub type TPIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
#[doc = "Field `TEF` reader - "]
pub type TEF_R = crate::BitReader<bool>;
#[doc = "Field `TIF` reader - "]
pub type TIF_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 2"]
#[inline(always)]
pub fn tpie(&self) -> TPIE_R {
TPIE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn tef(&self) -> TEF_R {
TEF_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn tif(&self) -> TIF_R {
TIF_R::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn cte(&mut self) -> CTE_W<0> {
CTE_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn cti(&mut self) -> CTI_W<1> {
CTI_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn tpie(&mut self) -> TPIE_W<2> {
TPIE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Backup Control Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"]
pub struct CSR_SPEC;
impl crate::RegisterSpec for CSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [csr::R](R) reader structure"]
impl crate::Readable for CSR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"]
impl crate::Writable for CSR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CSR to value 0"]
impl crate::Resettable for CSR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DR (rw) register accessor: an alias for `Reg<DR_SPEC>`"]
pub type DR = crate::Reg<dr::DR_SPEC>;
#[doc = "Backup data register n"]
pub mod dr {
#[doc = "Register `DR` reader"]
pub struct R(crate::R<DR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DR` writer"]
pub struct W(crate::W<DR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `BKP` reader - "]
pub type BKP_R = crate::FieldReader<u16, u16>;
#[doc = "Field `BKP` writer - "]
pub type BKP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DR_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn bkp(&self) -> BKP_R {
BKP_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn bkp(&mut self) -> BKP_W<0> {
BKP_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Backup data register n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](index.html) module"]
pub struct DR_SPEC;
impl crate::RegisterSpec for DR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dr::R](R) reader structure"]
impl crate::Readable for DR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dr::W](W) writer structure"]
impl crate::Writable for DR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DR to value 0"]
impl crate::Resettable for DR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "COMP"]
pub struct COMP {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for COMP {}
impl COMP {
#[doc = r"Pointer to the register block"]
pub const PTR: *const comp::RegisterBlock = 0x4001_4000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const comp::RegisterBlock {
Self::PTR
}
}
impl Deref for COMP {
type Target = comp::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for COMP {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("COMP").finish()
}
}
#[doc = "COMP"]
pub mod comp {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
_reserved0: [u8; 0x0c],
#[doc = "0x0c - Comparator x (x=1, 2, 3) Control and Status Register"]
pub csr: CSR,
_reserved1: [u8; 0x08],
#[doc = "0x18 - Comparator External Reference Voltage Register"]
pub crv: CRV,
#[doc = "0x1c - Comparator x (x=1, 2, 3) polling register"]
pub poll: POLL,
}
#[doc = "CSR (rw) register accessor: an alias for `Reg<CSR_SPEC>`"]
pub type CSR = crate::Reg<csr::CSR_SPEC>;
#[doc = "Comparator x (x=1, 2, 3) Control and Status Register"]
pub mod csr {
#[doc = "Register `CSR` reader"]
pub struct R(crate::R<CSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CSR` writer"]
pub struct W(crate::W<CSR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CSR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CSR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EN` reader - "]
pub type EN_R = crate::BitReader<bool>;
#[doc = "Field `EN` writer - "]
pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
#[doc = "Field `MODE` reader - "]
pub type MODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MODE` writer - "]
pub type MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSR_SPEC, u8, u8, 2, O>;
#[doc = "Field `INM_SEL` reader - "]
pub type INM_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `INM_SEL` writer - "]
pub type INM_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSR_SPEC, u8, u8, 2, O>;
#[doc = "Field `INP_SEL` reader - "]
pub type INP_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `INP_SEL` writer - "]
pub type INP_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSR_SPEC, u8, u8, 2, O>;
#[doc = "Field `OUT_SEL` reader - "]
pub type OUT_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OUT_SEL` writer - "]
pub type OUT_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSR_SPEC, u8, u8, 4, O>;
#[doc = "Field `POL` reader - "]
pub type POL_R = crate::BitReader<bool>;
#[doc = "Field `POL` writer - "]
pub type POL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
#[doc = "Field `HYST` reader - "]
pub type HYST_R = crate::FieldReader<u8, u8>;
#[doc = "Field `HYST` writer - "]
pub type HYST_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSR_SPEC, u8, u8, 2, O>;
#[doc = "Field `OFLT` reader - "]
pub type OFLT_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OFLT` writer - "]
pub type OFLT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSR_SPEC, u8, u8, 3, O>;
#[doc = "Field `WE` reader - "]
pub type WE_R = crate::BitReader<bool>;
#[doc = "Field `WE` writer - "]
pub type WE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
#[doc = "Field `OUT_ANA_SEL` reader - "]
pub type OUT_ANA_SEL_R = crate::BitReader<bool>;
#[doc = "Field `OUT_ANA_SEL` writer - "]
pub type OUT_ANA_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
#[doc = "Field `OUT` reader - "]
pub type OUT_R = crate::BitReader<bool>;
#[doc = "Field `OUT` writer - "]
pub type OUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
#[doc = "Field `LOCK` reader - "]
pub type LOCK_R = crate::BitReader<bool>;
#[doc = "Field `LOCK` writer - "]
pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn en(&self) -> EN_R {
EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bits 2:3"]
#[inline(always)]
pub fn mode(&self) -> MODE_R {
MODE_R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:5"]
#[inline(always)]
pub fn inm_sel(&self) -> INM_SEL_R {
INM_SEL_R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 7:8"]
#[inline(always)]
pub fn inp_sel(&self) -> INP_SEL_R {
INP_SEL_R::new(((self.bits >> 7) & 3) as u8)
}
#[doc = "Bits 10:13"]
#[inline(always)]
pub fn out_sel(&self) -> OUT_SEL_R {
OUT_SEL_R::new(((self.bits >> 10) & 0x0f) as u8)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn pol(&self) -> POL_R {
POL_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:17"]
#[inline(always)]
pub fn hyst(&self) -> HYST_R {
HYST_R::new(((self.bits >> 16) & 3) as u8)
}
#[doc = "Bits 18:20"]
#[inline(always)]
pub fn oflt(&self) -> OFLT_R {
OFLT_R::new(((self.bits >> 18) & 7) as u8)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn we(&self) -> WE_R {
WE_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29"]
#[inline(always)]
pub fn out_ana_sel(&self) -> OUT_ANA_SEL_R {
OUT_ANA_SEL_R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn out(&self) -> OUT_R {
OUT_R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn lock(&self) -> LOCK_R {
LOCK_R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EN_W<0> {
EN_W::new(self)
}
#[doc = "Bits 2:3"]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> MODE_W<2> {
MODE_W::new(self)
}
#[doc = "Bits 4:5"]
#[inline(always)]
#[must_use]
pub fn inm_sel(&mut self) -> INM_SEL_W<4> {
INM_SEL_W::new(self)
}
#[doc = "Bits 7:8"]
#[inline(always)]
#[must_use]
pub fn inp_sel(&mut self) -> INP_SEL_W<7> {
INP_SEL_W::new(self)
}
#[doc = "Bits 10:13"]
#[inline(always)]
#[must_use]
pub fn out_sel(&mut self) -> OUT_SEL_W<10> {
OUT_SEL_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn pol(&mut self) -> POL_W<15> {
POL_W::new(self)
}
#[doc = "Bits 16:17"]
#[inline(always)]
#[must_use]
pub fn hyst(&mut self) -> HYST_W<16> {
HYST_W::new(self)
}
#[doc = "Bits 18:20"]
#[inline(always)]
#[must_use]
pub fn oflt(&mut self) -> OFLT_W<18> {
OFLT_W::new(self)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn we(&mut self) -> WE_W<28> {
WE_W::new(self)
}
#[doc = "Bit 29"]
#[inline(always)]
#[must_use]
pub fn out_ana_sel(&mut self) -> OUT_ANA_SEL_W<29> {
OUT_ANA_SEL_W::new(self)
}
#[doc = "Bit 30"]
#[inline(always)]
#[must_use]
pub fn out(&mut self) -> OUT_W<30> {
OUT_W::new(self)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn lock(&mut self) -> LOCK_W<31> {
LOCK_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Comparator x (x=1, 2, 3) Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"]
pub struct CSR_SPEC;
impl crate::RegisterSpec for CSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [csr::R](R) reader structure"]
impl crate::Readable for CSR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"]
impl crate::Writable for CSR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CSR to value 0"]
impl crate::Resettable for CSR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CRV (rw) register accessor: an alias for `Reg<CRV_SPEC>`"]
pub type CRV = crate::Reg<crv::CRV_SPEC>;
#[doc = "Comparator External Reference Voltage Register"]
pub mod crv {
#[doc = "Register `CRV` reader"]
pub struct R(crate::R<CRV_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CRV_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CRV_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CRV_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CRV` writer"]
pub struct W(crate::W<CRV_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CRV_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CRV_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CRV_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CRV_SEL` reader - "]
pub type CRV_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CRV_SEL` writer - "]
pub type CRV_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRV_SPEC, u8, u8, 4, O>;
#[doc = "Field `CRV_EN` reader - "]
pub type CRV_EN_R = crate::BitReader<bool>;
#[doc = "Field `CRV_EN` writer - "]
pub type CRV_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CRV_SPEC, bool, O>;
#[doc = "Field `CRV_SRC` reader - "]
pub type CRV_SRC_R = crate::BitReader<bool>;
#[doc = "Field `CRV_SRC` writer - "]
pub type CRV_SRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CRV_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn crv_sel(&self) -> CRV_SEL_R {
CRV_SEL_R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn crv_en(&self) -> CRV_EN_R {
CRV_EN_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn crv_src(&self) -> CRV_SRC_R {
CRV_SRC_R::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn crv_sel(&mut self) -> CRV_SEL_W<0> {
CRV_SEL_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn crv_en(&mut self) -> CRV_EN_W<4> {
CRV_EN_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn crv_src(&mut self) -> CRV_SRC_W<5> {
CRV_SRC_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Comparator External Reference Voltage Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crv](index.html) module"]
pub struct CRV_SPEC;
impl crate::RegisterSpec for CRV_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [crv::R](R) reader structure"]
impl crate::Readable for CRV_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [crv::W](W) writer structure"]
impl crate::Writable for CRV_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CRV to value 0"]
impl crate::Resettable for CRV_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "POLL (rw) register accessor: an alias for `Reg<POLL_SPEC>`"]
pub type POLL = crate::Reg<poll::POLL_SPEC>;
#[doc = "Comparator x (x=1, 2, 3) polling register"]
pub mod poll {
#[doc = "Register `POLL` reader"]
pub struct R(crate::R<POLL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<POLL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<POLL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<POLL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `POLL` writer"]
pub struct W(crate::W<POLL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<POLL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<POLL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<POLL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `POLL_EN` reader - "]
pub type POLL_EN_R = crate::BitReader<bool>;
#[doc = "Field `POLL_EN` writer - "]
pub type POLL_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, POLL_SPEC, bool, O>;
#[doc = "Field `POLL_CH` reader - "]
pub type POLL_CH_R = crate::BitReader<bool>;
#[doc = "Field `POLL_CH` writer - "]
pub type POLL_CH_W<'a, const O: u8> = crate::BitWriter<'a, u32, POLL_SPEC, bool, O>;
#[doc = "Field `FIXN` reader - "]
pub type FIXN_R = crate::BitReader<bool>;
#[doc = "Field `FIXN` writer - "]
pub type FIXN_W<'a, const O: u8> = crate::BitWriter<'a, u32, POLL_SPEC, bool, O>;
#[doc = "Field `PERIOD` reader - "]
pub type PERIOD_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PERIOD` writer - "]
pub type PERIOD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, POLL_SPEC, u8, u8, 3, O>;
#[doc = "Field `POUT` reader - "]
pub type POUT_R = crate::FieldReader<u8, u8>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn poll_en(&self) -> POLL_EN_R {
POLL_EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn poll_ch(&self) -> POLL_CH_R {
POLL_CH_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn fixn(&self) -> FIXN_R {
FIXN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn period(&self) -> PERIOD_R {
PERIOD_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bits 8:10"]
#[inline(always)]
pub fn pout(&self) -> POUT_R {
POUT_R::new(((self.bits >> 8) & 7) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn poll_en(&mut self) -> POLL_EN_W<0> {
POLL_EN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn poll_ch(&mut self) -> POLL_CH_W<1> {
POLL_CH_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn fixn(&mut self) -> FIXN_W<2> {
FIXN_W::new(self)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn period(&mut self) -> PERIOD_W<4> {
PERIOD_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Comparator x (x=1, 2, 3) polling register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [poll](index.html) module"]
pub struct POLL_SPEC;
impl crate::RegisterSpec for POLL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [poll::R](R) reader structure"]
impl crate::Readable for POLL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [poll::W](W) writer structure"]
impl crate::Writable for POLL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets POLL to value 0"]
impl crate::Resettable for POLL_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "CORDIC"]
pub struct CORDIC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for CORDIC {}
impl CORDIC {
#[doc = r"Pointer to the register block"]
pub const PTR: *const cordic::RegisterBlock = 0x4002_a000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const cordic::RegisterBlock {
Self::PTR
}
}
impl Deref for CORDIC {
type Target = cordic::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for CORDIC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CORDIC").finish()
}
}
#[doc = "CORDIC"]
pub mod cordic {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - CORDIC X Data Register"]
pub dxr: DXR,
#[doc = "0x04 - CORDIC Y data register"]
pub dyr: DYR,
#[doc = "0x08 - CORDIC Z data register"]
pub dzr: DZR,
#[doc = "0x0c - CORDIC X Result Register"]
pub rxr: RXR,
#[doc = "0x10 - CORDIC Y result register"]
pub ryr: RYR,
#[doc = "0x14 - CORDIC Z result register"]
pub rzr: RZR,
#[doc = "0x18 - CORDIC Control Register"]
pub cr: CR,
#[doc = "0x1c - CORDIC Status Register"]
pub sr: SR,
}
#[doc = "DXR (rw) register accessor: an alias for `Reg<DXR_SPEC>`"]
pub type DXR = crate::Reg<dxr::DXR_SPEC>;
#[doc = "CORDIC X Data Register"]
pub mod dxr {
#[doc = "Register `DXR` reader"]
pub struct R(crate::R<DXR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DXR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DXR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DXR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DXR` writer"]
pub struct W(crate::W<DXR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DXR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DXR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DXR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DX` reader - "]
pub type DX_R = crate::FieldReader<u32, u32>;
#[doc = "Field `DX` writer - "]
pub type DX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DXR_SPEC, u32, u32, 24, O>;
impl R {
#[doc = "Bits 0:23"]
#[inline(always)]
pub fn dx(&self) -> DX_R {
DX_R::new(self.bits & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:23"]
#[inline(always)]
#[must_use]
pub fn dx(&mut self) -> DX_W<0> {
DX_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "CORDIC X Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dxr](index.html) module"]
pub struct DXR_SPEC;
impl crate::RegisterSpec for DXR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dxr::R](R) reader structure"]
impl crate::Readable for DXR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dxr::W](W) writer structure"]
impl crate::Writable for DXR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DXR to value 0"]
impl crate::Resettable for DXR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DYR (rw) register accessor: an alias for `Reg<DYR_SPEC>`"]
pub type DYR = crate::Reg<dyr::DYR_SPEC>;
#[doc = "CORDIC Y data register"]
pub mod dyr {
#[doc = "Register `DYR` reader"]
pub struct R(crate::R<DYR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DYR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DYR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DYR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DYR` writer"]
pub struct W(crate::W<DYR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DYR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DYR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DYR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DY` reader - "]
pub type DY_R = crate::FieldReader<u32, u32>;
#[doc = "Field `DY` writer - "]
pub type DY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DYR_SPEC, u32, u32, 24, O>;
impl R {
#[doc = "Bits 0:23"]
#[inline(always)]
pub fn dy(&self) -> DY_R {
DY_R::new(self.bits & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:23"]
#[inline(always)]
#[must_use]
pub fn dy(&mut self) -> DY_W<0> {
DY_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "CORDIC Y data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dyr](index.html) module"]
pub struct DYR_SPEC;
impl crate::RegisterSpec for DYR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dyr::R](R) reader structure"]
impl crate::Readable for DYR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dyr::W](W) writer structure"]
impl crate::Writable for DYR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DYR to value 0"]
impl crate::Resettable for DYR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DZR (rw) register accessor: an alias for `Reg<DZR_SPEC>`"]
pub type DZR = crate::Reg<dzr::DZR_SPEC>;
#[doc = "CORDIC Z data register"]
pub mod dzr {
#[doc = "Register `DZR` reader"]
pub struct R(crate::R<DZR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DZR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DZR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DZR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DZR` writer"]
pub struct W(crate::W<DZR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DZR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DZR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DZR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DZ` reader - "]
pub type DZ_R = crate::FieldReader<u32, u32>;
#[doc = "Field `DZ` writer - "]
pub type DZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DZR_SPEC, u32, u32, 24, O>;
impl R {
#[doc = "Bits 0:23"]
#[inline(always)]
pub fn dz(&self) -> DZ_R {
DZ_R::new(self.bits & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:23"]
#[inline(always)]
#[must_use]
pub fn dz(&mut self) -> DZ_W<0> {
DZ_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "CORDIC Z data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dzr](index.html) module"]
pub struct DZR_SPEC;
impl crate::RegisterSpec for DZR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dzr::R](R) reader structure"]
impl crate::Readable for DZR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dzr::W](W) writer structure"]
impl crate::Writable for DZR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DZR to value 0"]
impl crate::Resettable for DZR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RXR (r) register accessor: an alias for `Reg<RXR_SPEC>`"]
pub type RXR = crate::Reg<rxr::RXR_SPEC>;
#[doc = "CORDIC X Result Register"]
pub mod rxr {
#[doc = "Register `RXR` reader"]
pub struct R(crate::R<RXR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RXR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RXR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RXR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `RX` reader - "]
pub type RX_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:24"]
#[inline(always)]
pub fn rx(&self) -> RX_R {
RX_R::new(self.bits & 0x01ff_ffff)
}
}
#[doc = "CORDIC X Result Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxr](index.html) module"]
pub struct RXR_SPEC;
impl crate::RegisterSpec for RXR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rxr::R](R) reader structure"]
impl crate::Readable for RXR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets RXR to value 0"]
impl crate::Resettable for RXR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RYR (r) register accessor: an alias for `Reg<RYR_SPEC>`"]
pub type RYR = crate::Reg<ryr::RYR_SPEC>;
#[doc = "CORDIC Y result register"]
pub mod ryr {
#[doc = "Register `RYR` reader"]
pub struct R(crate::R<RYR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RYR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RYR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RYR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `RY` reader - "]
pub type RY_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:24"]
#[inline(always)]
pub fn ry(&self) -> RY_R {
RY_R::new(self.bits & 0x01ff_ffff)
}
}
#[doc = "CORDIC Y result register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ryr](index.html) module"]
pub struct RYR_SPEC;
impl crate::RegisterSpec for RYR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ryr::R](R) reader structure"]
impl crate::Readable for RYR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets RYR to value 0"]
impl crate::Resettable for RYR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RZR (r) register accessor: an alias for `Reg<RZR_SPEC>`"]
pub type RZR = crate::Reg<rzr::RZR_SPEC>;
#[doc = "CORDIC Z result register"]
pub mod rzr {
#[doc = "Register `RZR` reader"]
pub struct R(crate::R<RZR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RZR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RZR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RZR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `RZ` reader - "]
pub type RZ_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:23"]
#[inline(always)]
pub fn rz(&self) -> RZ_R {
RZ_R::new(self.bits & 0x00ff_ffff)
}
}
#[doc = "CORDIC Z result register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rzr](index.html) module"]
pub struct RZR_SPEC;
impl crate::RegisterSpec for RZR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rzr::R](R) reader structure"]
impl crate::Readable for RZR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets RZR to value 0"]
impl crate::Resettable for RZR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CR (rw) register accessor: an alias for `Reg<CR_SPEC>`"]
pub type CR = crate::Reg<cr::CR_SPEC>;
#[doc = "CORDIC Control Register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub struct R(crate::R<CR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR` writer"]
pub struct W(crate::W<CR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `START` reader - "]
pub type START_R = crate::BitReader<bool>;
#[doc = "Field `START` writer - "]
pub type START_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `WORKMODE` reader - "]
pub type WORKMODE_R = crate::BitReader<bool>;
#[doc = "Field `WORKMODE` writer - "]
pub type WORKMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `STARTMODE` reader - "]
pub type STARTMODE_R = crate::BitReader<bool>;
#[doc = "Field `STARTMODE` writer - "]
pub type STARTMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `ENABLE` reader - "]
pub type ENABLE_R = crate::BitReader<bool>;
#[doc = "Field `ENABLE` writer - "]
pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn start(&self) -> START_R {
START_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn workmode(&self) -> WORKMODE_R {
WORKMODE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn startmode(&self) -> STARTMODE_R {
STARTMODE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn enable(&self) -> ENABLE_R {
ENABLE_R::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn start(&mut self) -> START_W<0> {
START_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn workmode(&mut self) -> WORKMODE_W<1> {
WORKMODE_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn startmode(&mut self) -> STARTMODE_W<2> {
STARTMODE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn enable(&mut self) -> ENABLE_W<3> {
ENABLE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "CORDIC Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"]
pub struct CR_SPEC;
impl crate::RegisterSpec for CR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr::R](R) reader structure"]
impl crate::Readable for CR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"]
impl crate::Writable for CR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SR (r) register accessor: an alias for `Reg<SR_SPEC>`"]
pub type SR = crate::Reg<sr::SR_SPEC>;
#[doc = "CORDIC Status Register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub struct R(crate::R<SR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `BSY` reader - "]
pub type BSY_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn bsy(&self) -> BSY_R {
BSY_R::new((self.bits & 1) != 0)
}
}
#[doc = "CORDIC Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"]
pub struct SR_SPEC;
impl crate::RegisterSpec for SR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [sr::R](R) reader structure"]
impl crate::Readable for SR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "CRC"]
pub struct CRC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for CRC {}
impl CRC {
#[doc = r"Pointer to the register block"]
pub const PTR: *const crc::RegisterBlock = 0x4002_3000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const crc::RegisterBlock {
Self::PTR
}
}
impl Deref for CRC {
type Target = crc::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for CRC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CRC").finish()
}
}
#[doc = "CRC"]
pub mod crc {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - CRC data register"]
pub dr: DR,
#[doc = "0x04 - CRC independent data register"]
pub idr: IDR,
#[doc = "0x08 - CRC Control Register"]
pub cr: CR,
#[doc = "0x0c - CRC initial value register"]
pub ivr: IVR,
#[doc = "0x10 - CRC polynomial register"]
pub pr: PR,
}
#[doc = "DR (rw) register accessor: an alias for `Reg<DR_SPEC>`"]
pub type DR = crate::Reg<dr::DR_SPEC>;
#[doc = "CRC data register"]
pub mod dr {
#[doc = "Register `DR` reader"]
pub struct R(crate::R<DR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DR` writer"]
pub struct W(crate::W<DR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DR` reader - "]
pub type DR_R = crate::FieldReader<u32, u32>;
#[doc = "Field `DR` writer - "]
pub type DR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn dr(&self) -> DR_R {
DR_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn dr(&mut self) -> DR_W<0> {
DR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "CRC data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](index.html) module"]
pub struct DR_SPEC;
impl crate::RegisterSpec for DR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dr::R](R) reader structure"]
impl crate::Readable for DR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dr::W](W) writer structure"]
impl crate::Writable for DR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DR to value 0xffff_ffff"]
impl crate::Resettable for DR_SPEC {
const RESET_VALUE: Self::Ux = 0xffff_ffff;
}
}
#[doc = "IDR (rw) register accessor: an alias for `Reg<IDR_SPEC>`"]
pub type IDR = crate::Reg<idr::IDR_SPEC>;
#[doc = "CRC independent data register"]
pub mod idr {
#[doc = "Register `IDR` reader"]
pub struct R(crate::R<IDR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IDR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IDR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IDR` writer"]
pub struct W(crate::W<IDR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IDR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IDR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `IDR` reader - "]
pub type IDR_R = crate::FieldReader<u32, u32>;
#[doc = "Field `IDR` writer - "]
pub type IDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IDR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn idr(&self) -> IDR_R {
IDR_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn idr(&mut self) -> IDR_W<0> {
IDR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "CRC independent data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"]
pub struct IDR_SPEC;
impl crate::RegisterSpec for IDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [idr::R](R) reader structure"]
impl crate::Readable for IDR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"]
impl crate::Writable for IDR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IDR to value 0"]
impl crate::Resettable for IDR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CR (rw) register accessor: an alias for `Reg<CR_SPEC>`"]
pub type CR = crate::Reg<cr::CR_SPEC>;
#[doc = "CRC Control Register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub struct R(crate::R<CR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR` writer"]
pub struct W(crate::W<CR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RST` writer - "]
pub type RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `RI` reader - "]
pub type RI_R = crate::BitReader<bool>;
#[doc = "Field `RI` writer - "]
pub type RI_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `BEI` reader - "]
pub type BEI_R = crate::BitReader<bool>;
#[doc = "Field `BEI` writer - "]
pub type BEI_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `BEO` reader - "]
pub type BEO_R = crate::BitReader<bool>;
#[doc = "Field `BEO` writer - "]
pub type BEO_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `RO` reader - "]
pub type RO_R = crate::BitReader<bool>;
#[doc = "Field `RO` writer - "]
pub type RO_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `PWIDTH` reader - "]
pub type PWIDTH_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PWIDTH` writer - "]
pub type PWIDTH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bit 1"]
#[inline(always)]
pub fn ri(&self) -> RI_R {
RI_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn bei(&self) -> BEI_R {
BEI_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn beo(&self) -> BEO_R {
BEO_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn ro(&self) -> RO_R {
RO_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn pwidth(&self) -> PWIDTH_R {
PWIDTH_R::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn rst(&mut self) -> RST_W<0> {
RST_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn ri(&mut self) -> RI_W<1> {
RI_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn bei(&mut self) -> BEI_W<4> {
BEI_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn beo(&mut self) -> BEO_W<5> {
BEO_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn ro(&mut self) -> RO_W<6> {
RO_W::new(self)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn pwidth(&mut self) -> PWIDTH_W<14> {
PWIDTH_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "CRC Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"]
pub struct CR_SPEC;
impl crate::RegisterSpec for CR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr::R](R) reader structure"]
impl crate::Readable for CR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"]
impl crate::Writable for CR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "IVR (rw) register accessor: an alias for `Reg<IVR_SPEC>`"]
pub type IVR = crate::Reg<ivr::IVR_SPEC>;
#[doc = "CRC initial value register"]
pub mod ivr {
#[doc = "Register `IVR` reader"]
pub struct R(crate::R<IVR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IVR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IVR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IVR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IVR` writer"]
pub struct W(crate::W<IVR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IVR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IVR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IVR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `IVR` reader - "]
pub type IVR_R = crate::FieldReader<u32, u32>;
#[doc = "Field `IVR` writer - "]
pub type IVR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IVR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn ivr(&self) -> IVR_R {
IVR_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn ivr(&mut self) -> IVR_W<0> {
IVR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "CRC initial value register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ivr](index.html) module"]
pub struct IVR_SPEC;
impl crate::RegisterSpec for IVR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ivr::R](R) reader structure"]
impl crate::Readable for IVR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ivr::W](W) writer structure"]
impl crate::Writable for IVR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IVR to value 0xffff_ffff"]
impl crate::Resettable for IVR_SPEC {
const RESET_VALUE: Self::Ux = 0xffff_ffff;
}
}
#[doc = "PR (rw) register accessor: an alias for `Reg<PR_SPEC>`"]
pub type PR = crate::Reg<pr::PR_SPEC>;
#[doc = "CRC polynomial register"]
pub mod pr {
#[doc = "Register `PR` reader"]
pub struct R(crate::R<PR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PR` writer"]
pub struct W(crate::W<PR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PR` reader - "]
pub type PR_R = crate::FieldReader<u32, u32>;
#[doc = "Field `PR` writer - "]
pub type PR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn pr(&self) -> PR_R {
PR_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn pr(&mut self) -> PR_W<0> {
PR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "CRC polynomial register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pr](index.html) module"]
pub struct PR_SPEC;
impl crate::RegisterSpec for PR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [pr::R](R) reader structure"]
impl crate::Readable for PR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pr::W](W) writer structure"]
impl crate::Writable for PR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PR to value 0x04c1_1db7"]
impl crate::Resettable for PR_SPEC {
const RESET_VALUE: Self::Ux = 0x04c1_1db7;
}
}
}
#[doc = "CRS"]
pub struct CRS {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for CRS {}
impl CRS {
#[doc = r"Pointer to the register block"]
pub const PTR: *const crs::RegisterBlock = 0x4000_6c00 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const crs::RegisterBlock {
Self::PTR
}
}
impl Deref for CRS {
type Target = crs::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for CRS {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CRS").finish()
}
}
#[doc = "CRS"]
pub mod crs {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - CRS Control Register"]
pub cr: CR,
#[doc = "0x04 - CRS Configuration Register"]
pub cfgr: CFGR,
#[doc = "0x08 - CRS Interrupt Status Register"]
pub l_sr: L_SR,
#[doc = "0x0c - CRS Interrupt Flag Clear Register"]
pub l_cr: L_CR,
}
#[doc = "CR (rw) register accessor: an alias for `Reg<CR_SPEC>`"]
pub type CR = crate::Reg<cr::CR_SPEC>;
#[doc = "CRS Control Register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub struct R(crate::R<CR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR` writer"]
pub struct W(crate::W<CR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SYNCOKIE` reader - "]
pub type SYNCOKIE_R = crate::BitReader<bool>;
#[doc = "Field `SYNCOKIE` writer - "]
pub type SYNCOKIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `SYNCWARNIE` reader - "]
pub type SYNCWARNIE_R = crate::BitReader<bool>;
#[doc = "Field `SYNCWARNIE` writer - "]
pub type SYNCWARNIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `ERRIE` reader - "]
pub type ERRIE_R = crate::BitReader<bool>;
#[doc = "Field `ERRIE` writer - "]
pub type ERRIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `ESYNCIE` reader - "]
pub type ESYNCIE_R = crate::BitReader<bool>;
#[doc = "Field `ESYNCIE` writer - "]
pub type ESYNCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `CEN` reader - "]
pub type CEN_R = crate::BitReader<bool>;
#[doc = "Field `CEN` writer - "]
pub type CEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `AUTOTRIMEN` reader - "]
pub type AUTOTRIMEN_R = crate::BitReader<bool>;
#[doc = "Field `AUTOTRIMEN` writer - "]
pub type AUTOTRIMEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `SWSYNC` reader - "]
pub type SWSYNC_R = crate::BitReader<bool>;
#[doc = "Field `SWSYNC` writer - "]
pub type SWSYNC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `TRIM` reader - "]
pub type TRIM_R = crate::FieldReader<u16, u16>;
#[doc = "Field `TRIM` writer - "]
pub type TRIM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u16, u16, 10, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn syncokie(&self) -> SYNCOKIE_R {
SYNCOKIE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn syncwarnie(&self) -> SYNCWARNIE_R {
SYNCWARNIE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn errie(&self) -> ERRIE_R {
ERRIE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn esyncie(&self) -> ESYNCIE_R {
ESYNCIE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn cen(&self) -> CEN_R {
CEN_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn autotrimen(&self) -> AUTOTRIMEN_R {
AUTOTRIMEN_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn swsync(&self) -> SWSYNC_R {
SWSYNC_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:17"]
#[inline(always)]
pub fn trim(&self) -> TRIM_R {
TRIM_R::new(((self.bits >> 8) & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn syncokie(&mut self) -> SYNCOKIE_W<0> {
SYNCOKIE_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn syncwarnie(&mut self) -> SYNCWARNIE_W<1> {
SYNCWARNIE_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn errie(&mut self) -> ERRIE_W<2> {
ERRIE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn esyncie(&mut self) -> ESYNCIE_W<3> {
ESYNCIE_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn cen(&mut self) -> CEN_W<5> {
CEN_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn autotrimen(&mut self) -> AUTOTRIMEN_W<6> {
AUTOTRIMEN_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn swsync(&mut self) -> SWSYNC_W<7> {
SWSYNC_W::new(self)
}
#[doc = "Bits 8:17"]
#[inline(always)]
#[must_use]
pub fn trim(&mut self) -> TRIM_W<8> {
TRIM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "CRS Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"]
pub struct CR_SPEC;
impl crate::RegisterSpec for CR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr::R](R) reader structure"]
impl crate::Readable for CR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"]
impl crate::Writable for CR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR to value 0x0002_0000"]
impl crate::Resettable for CR_SPEC {
const RESET_VALUE: Self::Ux = 0x0002_0000;
}
}
#[doc = "CFGR (rw) register accessor: an alias for `Reg<CFGR_SPEC>`"]
pub type CFGR = crate::Reg<cfgr::CFGR_SPEC>;
#[doc = "CRS Configuration Register"]
pub mod cfgr {
#[doc = "Register `CFGR` reader"]
pub struct R(crate::R<CFGR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CFGR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CFGR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CFGR` writer"]
pub struct W(crate::W<CFGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CFGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CFGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RELOAD` reader - "]
pub type RELOAD_R = crate::FieldReader<u16, u16>;
#[doc = "Field `RELOAD` writer - "]
pub type RELOAD_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CFGR_SPEC, u16, u16, 16, O>;
#[doc = "Field `FELIM` reader - "]
pub type FELIM_R = crate::FieldReader<u8, u8>;
#[doc = "Field `FELIM` writer - "]
pub type FELIM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR_SPEC, u8, u8, 8, O>;
#[doc = "Field `SYNCDIV` reader - "]
pub type SYNCDIV_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SYNCDIV` writer - "]
pub type SYNCDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR_SPEC, u8, u8, 3, O>;
#[doc = "Field `SYNCSRC` reader - "]
pub type SYNCSRC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SYNCSRC` writer - "]
pub type SYNCSRC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR_SPEC, u8, u8, 2, O>;
#[doc = "Field `SYNCPOL` reader - "]
pub type SYNCPOL_R = crate::BitReader<bool>;
#[doc = "Field `SYNCPOL` writer - "]
pub type SYNCPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn reload(&self) -> RELOAD_R {
RELOAD_R::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:23"]
#[inline(always)]
pub fn felim(&self) -> FELIM_R {
FELIM_R::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:26"]
#[inline(always)]
pub fn syncdiv(&self) -> SYNCDIV_R {
SYNCDIV_R::new(((self.bits >> 24) & 7) as u8)
}
#[doc = "Bits 28:29"]
#[inline(always)]
pub fn syncsrc(&self) -> SYNCSRC_R {
SYNCSRC_R::new(((self.bits >> 28) & 3) as u8)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn syncpol(&self) -> SYNCPOL_R {
SYNCPOL_R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn reload(&mut self) -> RELOAD_W<0> {
RELOAD_W::new(self)
}
#[doc = "Bits 16:23"]
#[inline(always)]
#[must_use]
pub fn felim(&mut self) -> FELIM_W<16> {
FELIM_W::new(self)
}
#[doc = "Bits 24:26"]
#[inline(always)]
#[must_use]
pub fn syncdiv(&mut self) -> SYNCDIV_W<24> {
SYNCDIV_W::new(self)
}
#[doc = "Bits 28:29"]
#[inline(always)]
#[must_use]
pub fn syncsrc(&mut self) -> SYNCSRC_W<28> {
SYNCSRC_W::new(self)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn syncpol(&mut self) -> SYNCPOL_W<31> {
SYNCPOL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "CRS Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr](index.html) module"]
pub struct CFGR_SPEC;
impl crate::RegisterSpec for CFGR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cfgr::R](R) reader structure"]
impl crate::Readable for CFGR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfgr::W](W) writer structure"]
impl crate::Writable for CFGR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CFGR to value 0x2022_bb7f"]
impl crate::Resettable for CFGR_SPEC {
const RESET_VALUE: Self::Ux = 0x2022_bb7f;
}
}
#[doc = "lSR (r) register accessor: an alias for `Reg<L_SR_SPEC>`"]
pub type L_SR = crate::Reg<l_sr::L_SR_SPEC>;
#[doc = "CRS Interrupt Status Register"]
pub mod l_sr {
#[doc = "Register `lSR` reader"]
pub struct R(crate::R<L_SR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<L_SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<L_SR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<L_SR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `SYNCOKF` reader - "]
pub type SYNCOKF_R = crate::BitReader<bool>;
#[doc = "Field `SYNCWARNF` reader - "]
pub type SYNCWARNF_R = crate::BitReader<bool>;
#[doc = "Field `ERRF` reader - "]
pub type ERRF_R = crate::BitReader<bool>;
#[doc = "Field `ESYNCF` reader - "]
pub type ESYNCF_R = crate::BitReader<bool>;
#[doc = "Field `SYNCERR` reader - "]
pub type SYNCERR_R = crate::BitReader<bool>;
#[doc = "Field `SYNCMISS` reader - "]
pub type SYNCMISS_R = crate::BitReader<bool>;
#[doc = "Field `TRIMOVF` reader - "]
pub type TRIMOVF_R = crate::BitReader<bool>;
#[doc = "Field `FEDIR` reader - "]
pub type FEDIR_R = crate::BitReader<bool>;
#[doc = "Field `FECAP` reader - "]
pub type FECAP_R = crate::FieldReader<u16, u16>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn syncokf(&self) -> SYNCOKF_R {
SYNCOKF_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn syncwarnf(&self) -> SYNCWARNF_R {
SYNCWARNF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn errf(&self) -> ERRF_R {
ERRF_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn esyncf(&self) -> ESYNCF_R {
ESYNCF_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn syncerr(&self) -> SYNCERR_R {
SYNCERR_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn syncmiss(&self) -> SYNCMISS_R {
SYNCMISS_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn trimovf(&self) -> TRIMOVF_R {
TRIMOVF_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn fedir(&self) -> FEDIR_R {
FEDIR_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn fecap(&self) -> FECAP_R {
FECAP_R::new(((self.bits >> 16) & 0xffff) as u16)
}
}
#[doc = "CRS Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [l_sr](index.html) module"]
pub struct L_SR_SPEC;
impl crate::RegisterSpec for L_SR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [l_sr::R](R) reader structure"]
impl crate::Readable for L_SR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets lSR to value 0"]
impl crate::Resettable for L_SR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "lCR (w) register accessor: an alias for `Reg<L_CR_SPEC>`"]
pub type L_CR = crate::Reg<l_cr::L_CR_SPEC>;
#[doc = "CRS Interrupt Flag Clear Register"]
pub mod l_cr {
#[doc = "Register `lCR` writer"]
pub struct W(crate::W<L_CR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<L_CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<L_CR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<L_CR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SYNCOKC` writer - "]
pub type SYNCOKC_W<'a, const O: u8> = crate::BitWriter<'a, u32, L_CR_SPEC, bool, O>;
#[doc = "Field `SYNCWARNC` writer - "]
pub type SYNCWARNC_W<'a, const O: u8> = crate::BitWriter<'a, u32, L_CR_SPEC, bool, O>;
#[doc = "Field `ERRC` writer - "]
pub type ERRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, L_CR_SPEC, bool, O>;
#[doc = "Field `ESYNCC` writer - "]
pub type ESYNCC_W<'a, const O: u8> = crate::BitWriter<'a, u32, L_CR_SPEC, bool, O>;
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn syncokc(&mut self) -> SYNCOKC_W<0> {
SYNCOKC_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn syncwarnc(&mut self) -> SYNCWARNC_W<1> {
SYNCWARNC_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn errc(&mut self) -> ERRC_W<2> {
ERRC_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn esyncc(&mut self) -> ESYNCC_W<3> {
ESYNCC_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "CRS Interrupt Flag Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [l_cr](index.html) module"]
pub struct L_CR_SPEC;
impl crate::RegisterSpec for L_CR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [l_cr::W](W) writer structure"]
impl crate::Writable for L_CR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets lCR to value 0"]
impl crate::Resettable for L_CR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "DAC"]
pub struct DAC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for DAC {}
impl DAC {
#[doc = r"Pointer to the register block"]
pub const PTR: *const dac::RegisterBlock = 0x4000_7400 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const dac::RegisterBlock {
Self::PTR
}
}
impl Deref for DAC {
type Target = dac::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for DAC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DAC").finish()
}
}
#[doc = "DAC"]
pub mod dac {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - DAC Control Register"]
pub cr: CR,
#[doc = "0x04 - DAC Software Trigger Register"]
pub swtrigr: SWTRIGR,
#[doc = "0x08 - 12-Bit Right-Justified Data Holding Register for DAC Channel 1"]
pub dhr12r1: DHR12R1,
#[doc = "0x0c - 12-Bit Left-Justified Data Holding Register for DAC Channel 1"]
pub dhr12l1: DHR12L1,
#[doc = "0x10 - 8-Bit Right-Justified Data Holding Register for DAC Channel 1"]
pub dhr8r1: DHR8R1,
#[doc = "0x14 - 12-Bit Right-Justified Data Holding Register for DAC Channel 2"]
pub dhr12r2: DHR12R2,
#[doc = "0x18 - 12-Bit Left-Justified Data Holding Register for DAC Channel 2"]
pub dhr12l2: DHR12L2,
#[doc = "0x1c - 8-Bit Right-Justified Data Holding Register for DAC Channel 2"]
pub dhr8r2: DHR8R2,
#[doc = "0x20 - 12-Bit Right-Justified Data Holding Registers for Dual DACs"]
pub dhr12rd: DHR12RD,
#[doc = "0x24 - 12-Bit Left-Justified Data Holding Registers for Dual DACs"]
pub dhr12ld: DHR12LD,
#[doc = "0x28 - 8-Bit Right-Justified Data Holding Registers for Dual DACs"]
pub dhr8rd: DHR8RD,
#[doc = "0x2c - DAC Channel 1 Data Output Register"]
pub dor1: DOR1,
#[doc = "0x30 - DAC Channel 2 Data Output Register"]
pub dor2: DOR2,
}
#[doc = "CR (rw) register accessor: an alias for `Reg<CR_SPEC>`"]
pub type CR = crate::Reg<cr::CR_SPEC>;
#[doc = "DAC Control Register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub struct R(crate::R<CR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR` writer"]
pub struct W(crate::W<CR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EN1` reader - "]
pub type EN1_R = crate::BitReader<bool>;
#[doc = "Field `EN1` writer - "]
pub type EN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `BOFF1` reader - "]
pub type BOFF1_R = crate::BitReader<bool>;
#[doc = "Field `BOFF1` writer - "]
pub type BOFF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `TEN1` reader - "]
pub type TEN1_R = crate::BitReader<bool>;
#[doc = "Field `TEN1` writer - "]
pub type TEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `WAVE1` reader - "]
pub type WAVE1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `WAVE1` writer - "]
pub type WAVE1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, u8, 2, O>;
#[doc = "Field `MAMP1` reader - "]
pub type MAMP1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MAMP1` writer - "]
pub type MAMP1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, u8, 4, O>;
#[doc = "Field `DMA_EN1` reader - "]
pub type DMA_EN1_R = crate::BitReader<bool>;
#[doc = "Field `DMA_EN1` writer - "]
pub type DMA_EN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `OE_EN1` reader - "]
pub type OE_EN1_R = crate::BitReader<bool>;
#[doc = "Field `OE_EN1` writer - "]
pub type OE_EN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `EN2` reader - "]
pub type EN2_R = crate::BitReader<bool>;
#[doc = "Field `EN2` writer - "]
pub type EN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `BOFF2` reader - "]
pub type BOFF2_R = crate::BitReader<bool>;
#[doc = "Field `BOFF2` writer - "]
pub type BOFF2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `TEN2` reader - "]
pub type TEN2_R = crate::BitReader<bool>;
#[doc = "Field `TEN2` writer - "]
pub type TEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `WAVE2` reader - "]
pub type WAVE2_R = crate::FieldReader<u8, u8>;
#[doc = "Field `WAVE2` writer - "]
pub type WAVE2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, u8, 2, O>;
#[doc = "Field `MAMP2` reader - "]
pub type MAMP2_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MAMP2` writer - "]
pub type MAMP2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, u8, 4, O>;
#[doc = "Field `DMA_EN2` reader - "]
pub type DMA_EN2_R = crate::BitReader<bool>;
#[doc = "Field `DMA_EN2` writer - "]
pub type DMA_EN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `OE2_EN` reader - "]
pub type OE2_EN_R = crate::BitReader<bool>;
#[doc = "Field `OE2_EN` writer - "]
pub type OE2_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn en1(&self) -> EN1_R {
EN1_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn boff1(&self) -> BOFF1_R {
BOFF1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn ten1(&self) -> TEN1_R {
TEN1_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn wave1(&self) -> WAVE1_R {
WAVE1_R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:11"]
#[inline(always)]
pub fn mamp1(&self) -> MAMP1_R {
MAMP1_R::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn dma_en1(&self) -> DMA_EN1_R {
DMA_EN1_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn oe_en1(&self) -> OE_EN1_R {
OE_EN1_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn en2(&self) -> EN2_R {
EN2_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn boff2(&self) -> BOFF2_R {
BOFF2_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn ten2(&self) -> TEN2_R {
TEN2_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn wave2(&self) -> WAVE2_R {
WAVE2_R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bits 24:27"]
#[inline(always)]
pub fn mamp2(&self) -> MAMP2_R {
MAMP2_R::new(((self.bits >> 24) & 0x0f) as u8)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn dma_en2(&self) -> DMA_EN2_R {
DMA_EN2_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29"]
#[inline(always)]
pub fn oe2_en(&self) -> OE2_EN_R {
OE2_EN_R::new(((self.bits >> 29) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn en1(&mut self) -> EN1_W<0> {
EN1_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn boff1(&mut self) -> BOFF1_W<1> {
BOFF1_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn ten1(&mut self) -> TEN1_W<2> {
TEN1_W::new(self)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn wave1(&mut self) -> WAVE1_W<6> {
WAVE1_W::new(self)
}
#[doc = "Bits 8:11"]
#[inline(always)]
#[must_use]
pub fn mamp1(&mut self) -> MAMP1_W<8> {
MAMP1_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn dma_en1(&mut self) -> DMA_EN1_W<12> {
DMA_EN1_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn oe_en1(&mut self) -> OE_EN1_W<13> {
OE_EN1_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn en2(&mut self) -> EN2_W<16> {
EN2_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn boff2(&mut self) -> BOFF2_W<17> {
BOFF2_W::new(self)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn ten2(&mut self) -> TEN2_W<18> {
TEN2_W::new(self)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn wave2(&mut self) -> WAVE2_W<22> {
WAVE2_W::new(self)
}
#[doc = "Bits 24:27"]
#[inline(always)]
#[must_use]
pub fn mamp2(&mut self) -> MAMP2_W<24> {
MAMP2_W::new(self)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn dma_en2(&mut self) -> DMA_EN2_W<28> {
DMA_EN2_W::new(self)
}
#[doc = "Bit 29"]
#[inline(always)]
#[must_use]
pub fn oe2_en(&mut self) -> OE2_EN_W<29> {
OE2_EN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DAC Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"]
pub struct CR_SPEC;
impl crate::RegisterSpec for CR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr::R](R) reader structure"]
impl crate::Readable for CR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"]
impl crate::Writable for CR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SWTRIGR (w) register accessor: an alias for `Reg<SWTRIGR_SPEC>`"]
pub type SWTRIGR = crate::Reg<swtrigr::SWTRIGR_SPEC>;
#[doc = "DAC Software Trigger Register"]
pub mod swtrigr {
#[doc = "Register `SWTRIGR` writer"]
pub struct W(crate::W<SWTRIGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SWTRIGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SWTRIGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SWTRIGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SW_TRIG1` writer - "]
pub type SW_TRIG1_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGR_SPEC, bool, O>;
#[doc = "Field `SW_TRIG2` writer - "]
pub type SW_TRIG2_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGR_SPEC, bool, O>;
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn sw_trig1(&mut self) -> SW_TRIG1_W<0> {
SW_TRIG1_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn sw_trig2(&mut self) -> SW_TRIG2_W<1> {
SW_TRIG2_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DAC Software Trigger Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrigr](index.html) module"]
pub struct SWTRIGR_SPEC;
impl crate::RegisterSpec for SWTRIGR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [swtrigr::W](W) writer structure"]
impl crate::Writable for SWTRIGR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SWTRIGR to value 0"]
impl crate::Resettable for SWTRIGR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DHR12R1 (rw) register accessor: an alias for `Reg<DHR12R1_SPEC>`"]
pub type DHR12R1 = crate::Reg<dhr12r1::DHR12R1_SPEC>;
#[doc = "12-Bit Right-Justified Data Holding Register for DAC Channel 1"]
pub mod dhr12r1 {
#[doc = "Register `DHR12R1` reader"]
pub struct R(crate::R<DHR12R1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DHR12R1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DHR12R1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DHR12R1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DHR12R1` writer"]
pub struct W(crate::W<DHR12R1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DHR12R1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DHR12R1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DHR12R1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DACC1DHR` reader - "]
pub type DACC1DHR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `DACC1DHR` writer - "]
pub type DACC1DHR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DHR12R1_SPEC, u16, u16, 12, O>;
impl R {
#[doc = "Bits 0:11"]
#[inline(always)]
pub fn dacc1dhr(&self) -> DACC1DHR_R {
DACC1DHR_R::new((self.bits & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:11"]
#[inline(always)]
#[must_use]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<0> {
DACC1DHR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "12-Bit Right-Justified Data Holding Register for DAC Channel 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dhr12r1](index.html) module"]
pub struct DHR12R1_SPEC;
impl crate::RegisterSpec for DHR12R1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dhr12r1::R](R) reader structure"]
impl crate::Readable for DHR12R1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dhr12r1::W](W) writer structure"]
impl crate::Writable for DHR12R1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DHR12R1 to value 0"]
impl crate::Resettable for DHR12R1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DHR12L1 (rw) register accessor: an alias for `Reg<DHR12L1_SPEC>`"]
pub type DHR12L1 = crate::Reg<dhr12l1::DHR12L1_SPEC>;
#[doc = "12-Bit Left-Justified Data Holding Register for DAC Channel 1"]
pub mod dhr12l1 {
#[doc = "Register `DHR12L1` reader"]
pub struct R(crate::R<DHR12L1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DHR12L1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DHR12L1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DHR12L1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DHR12L1` writer"]
pub struct W(crate::W<DHR12L1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DHR12L1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DHR12L1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DHR12L1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DACC1DHR` reader - "]
pub type DACC1DHR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `DACC1DHR` writer - "]
pub type DACC1DHR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DHR12L1_SPEC, u16, u16, 12, O>;
impl R {
#[doc = "Bits 4:15"]
#[inline(always)]
pub fn dacc1dhr(&self) -> DACC1DHR_R {
DACC1DHR_R::new(((self.bits >> 4) & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 4:15"]
#[inline(always)]
#[must_use]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<4> {
DACC1DHR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "12-Bit Left-Justified Data Holding Register for DAC Channel 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dhr12l1](index.html) module"]
pub struct DHR12L1_SPEC;
impl crate::RegisterSpec for DHR12L1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dhr12l1::R](R) reader structure"]
impl crate::Readable for DHR12L1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dhr12l1::W](W) writer structure"]
impl crate::Writable for DHR12L1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DHR12L1 to value 0"]
impl crate::Resettable for DHR12L1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DHR8R1 (rw) register accessor: an alias for `Reg<DHR8R1_SPEC>`"]
pub type DHR8R1 = crate::Reg<dhr8r1::DHR8R1_SPEC>;
#[doc = "8-Bit Right-Justified Data Holding Register for DAC Channel 1"]
pub mod dhr8r1 {
#[doc = "Register `DHR8R1` reader"]
pub struct R(crate::R<DHR8R1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DHR8R1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DHR8R1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DHR8R1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DHR8R1` writer"]
pub struct W(crate::W<DHR8R1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DHR8R1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DHR8R1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DHR8R1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DACC1DHR` reader - "]
pub type DACC1DHR_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DACC1DHR` writer - "]
pub type DACC1DHR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DHR8R1_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn dacc1dhr(&self) -> DACC1DHR_R {
DACC1DHR_R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<0> {
DACC1DHR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "8-Bit Right-Justified Data Holding Register for DAC Channel 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dhr8r1](index.html) module"]
pub struct DHR8R1_SPEC;
impl crate::RegisterSpec for DHR8R1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dhr8r1::R](R) reader structure"]
impl crate::Readable for DHR8R1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dhr8r1::W](W) writer structure"]
impl crate::Writable for DHR8R1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DHR8R1 to value 0"]
impl crate::Resettable for DHR8R1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DHR12R2 (rw) register accessor: an alias for `Reg<DHR12R2_SPEC>`"]
pub type DHR12R2 = crate::Reg<dhr12r2::DHR12R2_SPEC>;
#[doc = "12-Bit Right-Justified Data Holding Register for DAC Channel 2"]
pub mod dhr12r2 {
#[doc = "Register `DHR12R2` reader"]
pub struct R(crate::R<DHR12R2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DHR12R2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DHR12R2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DHR12R2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DHR12R2` writer"]
pub struct W(crate::W<DHR12R2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DHR12R2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DHR12R2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DHR12R2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DACC2DHR` reader - "]
pub type DACC2DHR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `DACC2DHR` writer - "]
pub type DACC2DHR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DHR12R2_SPEC, u16, u16, 12, O>;
impl R {
#[doc = "Bits 0:11"]
#[inline(always)]
pub fn dacc2dhr(&self) -> DACC2DHR_R {
DACC2DHR_R::new((self.bits & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:11"]
#[inline(always)]
#[must_use]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<0> {
DACC2DHR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "12-Bit Right-Justified Data Holding Register for DAC Channel 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dhr12r2](index.html) module"]
pub struct DHR12R2_SPEC;
impl crate::RegisterSpec for DHR12R2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dhr12r2::R](R) reader structure"]
impl crate::Readable for DHR12R2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dhr12r2::W](W) writer structure"]
impl crate::Writable for DHR12R2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DHR12R2 to value 0"]
impl crate::Resettable for DHR12R2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DHR12L2 (rw) register accessor: an alias for `Reg<DHR12L2_SPEC>`"]
pub type DHR12L2 = crate::Reg<dhr12l2::DHR12L2_SPEC>;
#[doc = "12-Bit Left-Justified Data Holding Register for DAC Channel 2"]
pub mod dhr12l2 {
#[doc = "Register `DHR12L2` reader"]
pub struct R(crate::R<DHR12L2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DHR12L2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DHR12L2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DHR12L2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DHR12L2` writer"]
pub struct W(crate::W<DHR12L2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DHR12L2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DHR12L2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DHR12L2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DACC2DHR` reader - "]
pub type DACC2DHR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `DACC2DHR` writer - "]
pub type DACC2DHR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DHR12L2_SPEC, u16, u16, 12, O>;
impl R {
#[doc = "Bits 4:15"]
#[inline(always)]
pub fn dacc2dhr(&self) -> DACC2DHR_R {
DACC2DHR_R::new(((self.bits >> 4) & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 4:15"]
#[inline(always)]
#[must_use]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<4> {
DACC2DHR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "12-Bit Left-Justified Data Holding Register for DAC Channel 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dhr12l2](index.html) module"]
pub struct DHR12L2_SPEC;
impl crate::RegisterSpec for DHR12L2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dhr12l2::R](R) reader structure"]
impl crate::Readable for DHR12L2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dhr12l2::W](W) writer structure"]
impl crate::Writable for DHR12L2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DHR12L2 to value 0"]
impl crate::Resettable for DHR12L2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DHR8R2 (rw) register accessor: an alias for `Reg<DHR8R2_SPEC>`"]
pub type DHR8R2 = crate::Reg<dhr8r2::DHR8R2_SPEC>;
#[doc = "8-Bit Right-Justified Data Holding Register for DAC Channel 2"]
pub mod dhr8r2 {
#[doc = "Register `DHR8R2` reader"]
pub struct R(crate::R<DHR8R2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DHR8R2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DHR8R2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DHR8R2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DHR8R2` writer"]
pub struct W(crate::W<DHR8R2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DHR8R2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DHR8R2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DHR8R2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DACC2DHR` reader - "]
pub type DACC2DHR_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DACC2DHR` writer - "]
pub type DACC2DHR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DHR8R2_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn dacc2dhr(&self) -> DACC2DHR_R {
DACC2DHR_R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<0> {
DACC2DHR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "8-Bit Right-Justified Data Holding Register for DAC Channel 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dhr8r2](index.html) module"]
pub struct DHR8R2_SPEC;
impl crate::RegisterSpec for DHR8R2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dhr8r2::R](R) reader structure"]
impl crate::Readable for DHR8R2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dhr8r2::W](W) writer structure"]
impl crate::Writable for DHR8R2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DHR8R2 to value 0"]
impl crate::Resettable for DHR8R2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DHR12RD (rw) register accessor: an alias for `Reg<DHR12RD_SPEC>`"]
pub type DHR12RD = crate::Reg<dhr12rd::DHR12RD_SPEC>;
#[doc = "12-Bit Right-Justified Data Holding Registers for Dual DACs"]
pub mod dhr12rd {
#[doc = "Register `DHR12RD` reader"]
pub struct R(crate::R<DHR12RD_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DHR12RD_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DHR12RD_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DHR12RD_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DHR12RD` writer"]
pub struct W(crate::W<DHR12RD_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DHR12RD_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DHR12RD_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DHR12RD_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DACC1DHR` reader - "]
pub type DACC1DHR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `DACC1DHR` writer - "]
pub type DACC1DHR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DHR12RD_SPEC, u16, u16, 12, O>;
#[doc = "Field `DACC2DHR` reader - "]
pub type DACC2DHR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `DACC2DHR` writer - "]
pub type DACC2DHR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DHR12RD_SPEC, u16, u16, 12, O>;
impl R {
#[doc = "Bits 0:11"]
#[inline(always)]
pub fn dacc1dhr(&self) -> DACC1DHR_R {
DACC1DHR_R::new((self.bits & 0x0fff) as u16)
}
#[doc = "Bits 16:27"]
#[inline(always)]
pub fn dacc2dhr(&self) -> DACC2DHR_R {
DACC2DHR_R::new(((self.bits >> 16) & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:11"]
#[inline(always)]
#[must_use]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<0> {
DACC1DHR_W::new(self)
}
#[doc = "Bits 16:27"]
#[inline(always)]
#[must_use]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<16> {
DACC2DHR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "12-Bit Right-Justified Data Holding Registers for Dual DACs\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dhr12rd](index.html) module"]
pub struct DHR12RD_SPEC;
impl crate::RegisterSpec for DHR12RD_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dhr12rd::R](R) reader structure"]
impl crate::Readable for DHR12RD_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dhr12rd::W](W) writer structure"]
impl crate::Writable for DHR12RD_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DHR12RD to value 0"]
impl crate::Resettable for DHR12RD_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DHR12LD (rw) register accessor: an alias for `Reg<DHR12LD_SPEC>`"]
pub type DHR12LD = crate::Reg<dhr12ld::DHR12LD_SPEC>;
#[doc = "12-Bit Left-Justified Data Holding Registers for Dual DACs"]
pub mod dhr12ld {
#[doc = "Register `DHR12LD` reader"]
pub struct R(crate::R<DHR12LD_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DHR12LD_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DHR12LD_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DHR12LD_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DHR12LD` writer"]
pub struct W(crate::W<DHR12LD_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DHR12LD_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DHR12LD_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DHR12LD_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DACC1DHR` reader - "]
pub type DACC1DHR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `DACC1DHR` writer - "]
pub type DACC1DHR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DHR12LD_SPEC, u16, u16, 12, O>;
#[doc = "Field `DACC2DHR` reader - "]
pub type DACC2DHR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `DACC2DHR` writer - "]
pub type DACC2DHR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DHR12LD_SPEC, u16, u16, 12, O>;
impl R {
#[doc = "Bits 4:15"]
#[inline(always)]
pub fn dacc1dhr(&self) -> DACC1DHR_R {
DACC1DHR_R::new(((self.bits >> 4) & 0x0fff) as u16)
}
#[doc = "Bits 20:31"]
#[inline(always)]
pub fn dacc2dhr(&self) -> DACC2DHR_R {
DACC2DHR_R::new(((self.bits >> 20) & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 4:15"]
#[inline(always)]
#[must_use]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<4> {
DACC1DHR_W::new(self)
}
#[doc = "Bits 20:31"]
#[inline(always)]
#[must_use]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<20> {
DACC2DHR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "12-Bit Left-Justified Data Holding Registers for Dual DACs\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dhr12ld](index.html) module"]
pub struct DHR12LD_SPEC;
impl crate::RegisterSpec for DHR12LD_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dhr12ld::R](R) reader structure"]
impl crate::Readable for DHR12LD_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dhr12ld::W](W) writer structure"]
impl crate::Writable for DHR12LD_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DHR12LD to value 0"]
impl crate::Resettable for DHR12LD_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DHR8RD (rw) register accessor: an alias for `Reg<DHR8RD_SPEC>`"]
pub type DHR8RD = crate::Reg<dhr8rd::DHR8RD_SPEC>;
#[doc = "8-Bit Right-Justified Data Holding Registers for Dual DACs"]
pub mod dhr8rd {
#[doc = "Register `DHR8RD` reader"]
pub struct R(crate::R<DHR8RD_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DHR8RD_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DHR8RD_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DHR8RD_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DHR8RD` writer"]
pub struct W(crate::W<DHR8RD_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DHR8RD_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DHR8RD_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DHR8RD_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DACC1DHR` reader - "]
pub type DACC1DHR_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DACC1DHR` writer - "]
pub type DACC1DHR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DHR8RD_SPEC, u8, u8, 8, O>;
#[doc = "Field `DACC2DHR` reader - "]
pub type DACC2DHR_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DACC2DHR` writer - "]
pub type DACC2DHR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DHR8RD_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn dacc1dhr(&self) -> DACC1DHR_R {
DACC1DHR_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15"]
#[inline(always)]
pub fn dacc2dhr(&self) -> DACC2DHR_R {
DACC2DHR_R::new(((self.bits >> 8) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn dacc1dhr(&mut self) -> DACC1DHR_W<0> {
DACC1DHR_W::new(self)
}
#[doc = "Bits 8:15"]
#[inline(always)]
#[must_use]
pub fn dacc2dhr(&mut self) -> DACC2DHR_W<8> {
DACC2DHR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "8-Bit Right-Justified Data Holding Registers for Dual DACs\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dhr8rd](index.html) module"]
pub struct DHR8RD_SPEC;
impl crate::RegisterSpec for DHR8RD_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dhr8rd::R](R) reader structure"]
impl crate::Readable for DHR8RD_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dhr8rd::W](W) writer structure"]
impl crate::Writable for DHR8RD_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DHR8RD to value 0"]
impl crate::Resettable for DHR8RD_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DOR1 (rw) register accessor: an alias for `Reg<DOR1_SPEC>`"]
pub type DOR1 = crate::Reg<dor1::DOR1_SPEC>;
#[doc = "DAC Channel 1 Data Output Register"]
pub mod dor1 {
#[doc = "Register `DOR1` reader"]
pub struct R(crate::R<DOR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DOR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DOR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DOR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DOR1` writer"]
pub struct W(crate::W<DOR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DOR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DOR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DOR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DACC1DOR` reader - "]
pub type DACC1DOR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `DACC1DOR` writer - "]
pub type DACC1DOR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DOR1_SPEC, u16, u16, 12, O>;
impl R {
#[doc = "Bits 0:11"]
#[inline(always)]
pub fn dacc1dor(&self) -> DACC1DOR_R {
DACC1DOR_R::new((self.bits & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:11"]
#[inline(always)]
#[must_use]
pub fn dacc1dor(&mut self) -> DACC1DOR_W<0> {
DACC1DOR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DAC Channel 1 Data Output Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dor1](index.html) module"]
pub struct DOR1_SPEC;
impl crate::RegisterSpec for DOR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dor1::R](R) reader structure"]
impl crate::Readable for DOR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dor1::W](W) writer structure"]
impl crate::Writable for DOR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DOR1 to value 0"]
impl crate::Resettable for DOR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DOR2 (rw) register accessor: an alias for `Reg<DOR2_SPEC>`"]
pub type DOR2 = crate::Reg<dor2::DOR2_SPEC>;
#[doc = "DAC Channel 2 Data Output Register"]
pub mod dor2 {
#[doc = "Register `DOR2` reader"]
pub struct R(crate::R<DOR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DOR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DOR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DOR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DOR2` writer"]
pub struct W(crate::W<DOR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DOR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DOR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DOR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DACC2DOR` reader - "]
pub type DACC2DOR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `DACC2DOR` writer - "]
pub type DACC2DOR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DOR2_SPEC, u16, u16, 12, O>;
impl R {
#[doc = "Bits 0:11"]
#[inline(always)]
pub fn dacc2dor(&self) -> DACC2DOR_R {
DACC2DOR_R::new((self.bits & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:11"]
#[inline(always)]
#[must_use]
pub fn dacc2dor(&mut self) -> DACC2DOR_W<0> {
DACC2DOR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DAC Channel 2 Data Output Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dor2](index.html) module"]
pub struct DOR2_SPEC;
impl crate::RegisterSpec for DOR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dor2::R](R) reader structure"]
impl crate::Readable for DOR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dor2::W](W) writer structure"]
impl crate::Writable for DOR2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DOR2 to value 0"]
impl crate::Resettable for DOR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "DBGMCU"]
pub struct DBGMCU {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for DBGMCU {}
impl DBGMCU {
#[doc = r"Pointer to the register block"]
pub const PTR: *const dbgmcu::RegisterBlock = 0x4000_7080 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const dbgmcu::RegisterBlock {
Self::PTR
}
}
impl Deref for DBGMCU {
type Target = dbgmcu::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for DBGMCU {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DBGMCU").finish()
}
}
#[doc = "DBGMCU"]
pub mod dbgmcu {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - MCU_IDCODE register"]
pub idcode: IDCODE,
#[doc = "0x04 - DEBUG control register"]
pub cr: CR,
}
#[doc = "IDCODE (r) register accessor: an alias for `Reg<IDCODE_SPEC>`"]
pub type IDCODE = crate::Reg<idcode::IDCODE_SPEC>;
#[doc = "MCU_IDCODE register"]
pub mod idcode {
#[doc = "Register `IDCODE` reader"]
pub struct R(crate::R<IDCODE_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IDCODE_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IDCODE_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IDCODE_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `DEV_ID` reader - "]
pub type DEV_ID_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn dev_id(&self) -> DEV_ID_R {
DEV_ID_R::new(self.bits)
}
}
#[doc = "MCU_IDCODE register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idcode](index.html) module"]
pub struct IDCODE_SPEC;
impl crate::RegisterSpec for IDCODE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [idcode::R](R) reader structure"]
impl crate::Readable for IDCODE_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets IDCODE to value 0x4d4d_0800"]
impl crate::Resettable for IDCODE_SPEC {
const RESET_VALUE: Self::Ux = 0x4d4d_0800;
}
}
#[doc = "CR (rw) register accessor: an alias for `Reg<CR_SPEC>`"]
pub type CR = crate::Reg<cr::CR_SPEC>;
#[doc = "DEBUG control register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub struct R(crate::R<CR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR` writer"]
pub struct W(crate::W<CR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `debug_stop_for_ldo` reader - "]
pub type DEBUG_STOP_FOR_LDO_R = crate::BitReader<bool>;
#[doc = "Field `debug_stop_for_ldo` writer - "]
pub type DEBUG_STOP_FOR_LDO_W<'a, const O: u8> =
crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `trace_ioen` reader - "]
pub type TRACE_IOEN_R = crate::BitReader<bool>;
#[doc = "Field `trace_ioen` writer - "]
pub type TRACE_IOEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `trace_mode` reader - "]
pub type TRACE_MODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `trace_mode` writer - "]
pub type TRACE_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, u8, 2, O>;
#[doc = "Field `debug_iwdg_stop` reader - "]
pub type DEBUG_IWDG_STOP_R = crate::BitReader<bool>;
#[doc = "Field `debug_iwdg_stop` writer - "]
pub type DEBUG_IWDG_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `debug_wwdg_stop` reader - "]
pub type DEBUG_WWDG_STOP_R = crate::BitReader<bool>;
#[doc = "Field `debug_wwdg_stop` writer - "]
pub type DEBUG_WWDG_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `debug_tim1_stop` reader - "]
pub type DEBUG_TIM1_STOP_R = crate::BitReader<bool>;
#[doc = "Field `debug_tim1_stop` writer - "]
pub type DEBUG_TIM1_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `debug_tim2_stop` reader - "]
pub type DEBUG_TIM2_STOP_R = crate::BitReader<bool>;
#[doc = "Field `debug_tim2_stop` writer - "]
pub type DEBUG_TIM2_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `debug_tim3_stop` reader - "]
pub type DEBUG_TIM3_STOP_R = crate::BitReader<bool>;
#[doc = "Field `debug_tim3_stop` writer - "]
pub type DEBUG_TIM3_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `debug_tim4_stop` reader - "]
pub type DEBUG_TIM4_STOP_R = crate::BitReader<bool>;
#[doc = "Field `debug_tim4_stop` writer - "]
pub type DEBUG_TIM4_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `debug_tim8_stop` reader - "]
pub type DEBUG_TIM8_STOP_R = crate::BitReader<bool>;
#[doc = "Field `debug_tim8_stop` writer - "]
pub type DEBUG_TIM8_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `debug_tim5_stop` reader - "]
pub type DEBUG_TIM5_STOP_R = crate::BitReader<bool>;
#[doc = "Field `debug_tim5_stop` writer - "]
pub type DEBUG_TIM5_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `debug_tim6_stop` reader - "]
pub type DEBUG_TIM6_STOP_R = crate::BitReader<bool>;
#[doc = "Field `debug_tim6_stop` writer - "]
pub type DEBUG_TIM6_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `debug_tim7_stop` reader - "]
pub type DEBUG_TIM7_STOP_R = crate::BitReader<bool>;
#[doc = "Field `debug_tim7_stop` writer - "]
pub type DEBUG_TIM7_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
impl R {
#[doc = "Bit 3"]
#[inline(always)]
pub fn debug_stop_for_ldo(&self) -> DEBUG_STOP_FOR_LDO_R {
DEBUG_STOP_FOR_LDO_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn trace_ioen(&self) -> TRACE_IOEN_R {
TRACE_IOEN_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn trace_mode(&self) -> TRACE_MODE_R {
TRACE_MODE_R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn debug_iwdg_stop(&self) -> DEBUG_IWDG_STOP_R {
DEBUG_IWDG_STOP_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn debug_wwdg_stop(&self) -> DEBUG_WWDG_STOP_R {
DEBUG_WWDG_STOP_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn debug_tim1_stop(&self) -> DEBUG_TIM1_STOP_R {
DEBUG_TIM1_STOP_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn debug_tim2_stop(&self) -> DEBUG_TIM2_STOP_R {
DEBUG_TIM2_STOP_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn debug_tim3_stop(&self) -> DEBUG_TIM3_STOP_R {
DEBUG_TIM3_STOP_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn debug_tim4_stop(&self) -> DEBUG_TIM4_STOP_R {
DEBUG_TIM4_STOP_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn debug_tim8_stop(&self) -> DEBUG_TIM8_STOP_R {
DEBUG_TIM8_STOP_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn debug_tim5_stop(&self) -> DEBUG_TIM5_STOP_R {
DEBUG_TIM5_STOP_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn debug_tim6_stop(&self) -> DEBUG_TIM6_STOP_R {
DEBUG_TIM6_STOP_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn debug_tim7_stop(&self) -> DEBUG_TIM7_STOP_R {
DEBUG_TIM7_STOP_R::new(((self.bits >> 20) & 1) != 0)
}
}
impl W {
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn debug_stop_for_ldo(&mut self) -> DEBUG_STOP_FOR_LDO_W<3> {
DEBUG_STOP_FOR_LDO_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<5> {
TRACE_IOEN_W::new(self)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn trace_mode(&mut self) -> TRACE_MODE_W<6> {
TRACE_MODE_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn debug_iwdg_stop(&mut self) -> DEBUG_IWDG_STOP_W<8> {
DEBUG_IWDG_STOP_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn debug_wwdg_stop(&mut self) -> DEBUG_WWDG_STOP_W<9> {
DEBUG_WWDG_STOP_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn debug_tim1_stop(&mut self) -> DEBUG_TIM1_STOP_W<10> {
DEBUG_TIM1_STOP_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn debug_tim2_stop(&mut self) -> DEBUG_TIM2_STOP_W<11> {
DEBUG_TIM2_STOP_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn debug_tim3_stop(&mut self) -> DEBUG_TIM3_STOP_W<12> {
DEBUG_TIM3_STOP_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn debug_tim4_stop(&mut self) -> DEBUG_TIM4_STOP_W<13> {
DEBUG_TIM4_STOP_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn debug_tim8_stop(&mut self) -> DEBUG_TIM8_STOP_W<17> {
DEBUG_TIM8_STOP_W::new(self)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn debug_tim5_stop(&mut self) -> DEBUG_TIM5_STOP_W<18> {
DEBUG_TIM5_STOP_W::new(self)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn debug_tim6_stop(&mut self) -> DEBUG_TIM6_STOP_W<19> {
DEBUG_TIM6_STOP_W::new(self)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn debug_tim7_stop(&mut self) -> DEBUG_TIM7_STOP_W<20> {
DEBUG_TIM7_STOP_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DEBUG control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"]
pub struct CR_SPEC;
impl crate::RegisterSpec for CR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr::R](R) reader structure"]
impl crate::Readable for CR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"]
impl crate::Writable for CR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "DMA1"]
pub struct DMA1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for DMA1 {}
impl DMA1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const dma1::RegisterBlock = 0x4002_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const dma1::RegisterBlock {
Self::PTR
}
}
impl Deref for DMA1 {
type Target = dma1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for DMA1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DMA1").finish()
}
}
#[doc = "DMA1"]
pub mod dma1 {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - DMA Interrupt Status Register"]
pub isr: ISR,
#[doc = "0x04 - DMA Interrupt Flag Clear Register"]
pub ifcr: IFCR,
#[doc = "0x08 - DMA Channel 1 Configuration Register"]
pub ccr1: CCR1,
#[doc = "0x0c - DMA Channel 1 Transfer Number Register"]
pub cndtr1: CNDTR1,
#[doc = "0x10 - DMA Channel 1 Peripheral Address Register"]
pub cpar1: CPAR1,
#[doc = "0x14 - DMA Channel 1 Memory Address Register"]
pub cmar1: CMAR1,
_reserved6: [u8; 0x04],
#[doc = "0x1c - DMA Channel 1 Configuration Register"]
pub ccr2: CCR2,
#[doc = "0x20 - DMA Channel 1 Transfer Number Register"]
pub cndtr2: CNDTR2,
#[doc = "0x24 - DMA Channel 1 Peripheral Address Register"]
pub cpar2: CPAR2,
#[doc = "0x28 - DMA Channel 1 Memory Address Register"]
pub cmar2: CMAR2,
_reserved10: [u8; 0x04],
#[doc = "0x30 - DMA Channel 1 Configuration Register"]
pub ccr3: CCR3,
#[doc = "0x34 - DMA Channel 1 Transfer Number Register"]
pub cndtr3: CNDTR3,
#[doc = "0x38 - DMA Channel 1 Peripheral Address Register"]
pub cpar3: CPAR3,
#[doc = "0x3c - DMA Channel 1 Memory Address Register"]
pub cmar3: CMAR3,
_reserved14: [u8; 0x04],
#[doc = "0x44 - DMA Channel 1 Configuration Register"]
pub ccr4: CCR4,
#[doc = "0x48 - DMA Channel 1 Transfer Number Register"]
pub cndtr4: CNDTR4,
#[doc = "0x4c - DMA Channel 1 Peripheral Address Register"]
pub cpar4: CPAR4,
#[doc = "0x50 - DMA Channel 1 Memory Address Register"]
pub cmar4: CMAR4,
_reserved18: [u8; 0x04],
#[doc = "0x58 - DMA Channel 1 Configuration Register"]
pub ccr5: CCR5,
#[doc = "0x5c - DMA Channel 1 Transfer Number Register"]
pub cndtr5: CNDTR5,
#[doc = "0x60 - DMA Channel 1 Peripheral Address Register"]
pub cpar5: CPAR5,
#[doc = "0x64 - DMA Channel 1 Memory Address Register"]
pub cmar5: CMAR5,
_reserved22: [u8; 0x04],
#[doc = "0x6c - DMA Channel 1 Configuration Register"]
pub ccr6: CCR6,
#[doc = "0x70 - DMA Channel 1 Transfer Number Register"]
pub cndtr6: CNDTR6,
#[doc = "0x74 - DMA Channel 1 Peripheral Address Register"]
pub cpar6: CPAR6,
#[doc = "0x78 - DMA Channel 1 Memory Address Register"]
pub cmar6: CMAR6,
_reserved26: [u8; 0x04],
#[doc = "0x80 - DMA Channel 1 Configuration Register"]
pub ccr7: CCR7,
#[doc = "0x84 - DMA Channel 1 Transfer Number Register"]
pub cndtr7: CNDTR7,
#[doc = "0x88 - DMA Channel 1 Peripheral Address Register"]
pub cpar7: CPAR7,
#[doc = "0x8c - DMA Channel 1 Memory Address Register"]
pub cmar7: CMAR7,
_reserved30: [u8; 0x04],
#[doc = "0x94 - DMA Channel 1 Configuration Register"]
pub ccr8: CCR8,
#[doc = "0x98 - DMA Channel 1 Transfer Number Register"]
pub cndtr8: CNDTR8,
#[doc = "0x9c - DMA Channel 1 Peripheral Address Register"]
pub cpar8: CPAR8,
#[doc = "0xa0 - DMA Channel 1 Memory Address Register"]
pub cmar8: CMAR8,
}
#[doc = "ISR (r) register accessor: an alias for `Reg<ISR_SPEC>`"]
pub type ISR = crate::Reg<isr::ISR_SPEC>;
#[doc = "DMA Interrupt Status Register"]
pub mod isr {
#[doc = "Register `ISR` reader"]
pub struct R(crate::R<ISR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ISR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ISR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ISR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `GIF1` reader - "]
pub type GIF1_R = crate::BitReader<bool>;
#[doc = "Field `TCIF1` reader - "]
pub type TCIF1_R = crate::BitReader<bool>;
#[doc = "Field `HTIF1` reader - "]
pub type HTIF1_R = crate::BitReader<bool>;
#[doc = "Field `TEIF1` reader - "]
pub type TEIF1_R = crate::BitReader<bool>;
#[doc = "Field `GIF2` reader - "]
pub type GIF2_R = crate::BitReader<bool>;
#[doc = "Field `TCIF2` reader - "]
pub type TCIF2_R = crate::BitReader<bool>;
#[doc = "Field `HTIF2` reader - "]
pub type HTIF2_R = crate::BitReader<bool>;
#[doc = "Field `TEIF2` reader - "]
pub type TEIF2_R = crate::BitReader<bool>;
#[doc = "Field `GIF3` reader - "]
pub type GIF3_R = crate::BitReader<bool>;
#[doc = "Field `TCIF3` reader - "]
pub type TCIF3_R = crate::BitReader<bool>;
#[doc = "Field `HTIF3` reader - "]
pub type HTIF3_R = crate::BitReader<bool>;
#[doc = "Field `TEIF3` reader - "]
pub type TEIF3_R = crate::BitReader<bool>;
#[doc = "Field `GIF4` reader - "]
pub type GIF4_R = crate::BitReader<bool>;
#[doc = "Field `TCIF4` reader - "]
pub type TCIF4_R = crate::BitReader<bool>;
#[doc = "Field `HTIF4` reader - "]
pub type HTIF4_R = crate::BitReader<bool>;
#[doc = "Field `TEIF4` reader - "]
pub type TEIF4_R = crate::BitReader<bool>;
#[doc = "Field `GIF5` reader - "]
pub type GIF5_R = crate::BitReader<bool>;
#[doc = "Field `TCIF5` reader - "]
pub type TCIF5_R = crate::BitReader<bool>;
#[doc = "Field `HTIF5` reader - "]
pub type HTIF5_R = crate::BitReader<bool>;
#[doc = "Field `TEIF5` reader - "]
pub type TEIF5_R = crate::BitReader<bool>;
#[doc = "Field `GIF6` reader - "]
pub type GIF6_R = crate::BitReader<bool>;
#[doc = "Field `TCIF6` reader - "]
pub type TCIF6_R = crate::BitReader<bool>;
#[doc = "Field `HTIF6` reader - "]
pub type HTIF6_R = crate::BitReader<bool>;
#[doc = "Field `TEIF6` reader - "]
pub type TEIF6_R = crate::BitReader<bool>;
#[doc = "Field `GIF7` reader - "]
pub type GIF7_R = crate::BitReader<bool>;
#[doc = "Field `TCIF7` reader - "]
pub type TCIF7_R = crate::BitReader<bool>;
#[doc = "Field `HTIF7` reader - "]
pub type HTIF7_R = crate::BitReader<bool>;
#[doc = "Field `TEIF7` reader - "]
pub type TEIF7_R = crate::BitReader<bool>;
#[doc = "Field `GIF8` reader - "]
pub type GIF8_R = crate::BitReader<bool>;
#[doc = "Field `TCIF8` reader - "]
pub type TCIF8_R = crate::BitReader<bool>;
#[doc = "Field `HTIF8` reader - "]
pub type HTIF8_R = crate::BitReader<bool>;
#[doc = "Field `TEIF8` reader - "]
pub type TEIF8_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn gif1(&self) -> GIF1_R {
GIF1_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn tcif1(&self) -> TCIF1_R {
TCIF1_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn htif1(&self) -> HTIF1_R {
HTIF1_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn teif1(&self) -> TEIF1_R {
TEIF1_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn gif2(&self) -> GIF2_R {
GIF2_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn tcif2(&self) -> TCIF2_R {
TCIF2_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn htif2(&self) -> HTIF2_R {
HTIF2_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn teif2(&self) -> TEIF2_R {
TEIF2_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn gif3(&self) -> GIF3_R {
GIF3_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn tcif3(&self) -> TCIF3_R {
TCIF3_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn htif3(&self) -> HTIF3_R {
HTIF3_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn teif3(&self) -> TEIF3_R {
TEIF3_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn gif4(&self) -> GIF4_R {
GIF4_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn tcif4(&self) -> TCIF4_R {
TCIF4_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn htif4(&self) -> HTIF4_R {
HTIF4_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn teif4(&self) -> TEIF4_R {
TEIF4_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn gif5(&self) -> GIF5_R {
GIF5_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn tcif5(&self) -> TCIF5_R {
TCIF5_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn htif5(&self) -> HTIF5_R {
HTIF5_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn teif5(&self) -> TEIF5_R {
TEIF5_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn gif6(&self) -> GIF6_R {
GIF6_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn tcif6(&self) -> TCIF6_R {
TCIF6_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn htif6(&self) -> HTIF6_R {
HTIF6_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23"]
#[inline(always)]
pub fn teif6(&self) -> TEIF6_R {
TEIF6_R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn gif7(&self) -> GIF7_R {
GIF7_R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn tcif7(&self) -> TCIF7_R {
TCIF7_R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26"]
#[inline(always)]
pub fn htif7(&self) -> HTIF7_R {
HTIF7_R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27"]
#[inline(always)]
pub fn teif7(&self) -> TEIF7_R {
TEIF7_R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn gif8(&self) -> GIF8_R {
GIF8_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29"]
#[inline(always)]
pub fn tcif8(&self) -> TCIF8_R {
TCIF8_R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn htif8(&self) -> HTIF8_R {
HTIF8_R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn teif8(&self) -> TEIF8_R {
TEIF8_R::new(((self.bits >> 31) & 1) != 0)
}
}
#[doc = "DMA Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](index.html) module"]
pub struct ISR_SPEC;
impl crate::RegisterSpec for ISR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [isr::R](R) reader structure"]
impl crate::Readable for ISR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets ISR to value 0"]
impl crate::Resettable for ISR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "IFCR (w) register accessor: an alias for `Reg<IFCR_SPEC>`"]
pub type IFCR = crate::Reg<ifcr::IFCR_SPEC>;
#[doc = "DMA Interrupt Flag Clear Register"]
pub mod ifcr {
#[doc = "Register `IFCR` writer"]
pub struct W(crate::W<IFCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IFCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IFCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IFCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CGIF1` writer - "]
pub type CGIF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CTCIF1` writer - "]
pub type CTCIF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CHTIF1` writer - "]
pub type CHTIF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CTEIF1` writer - "]
pub type CTEIF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CGIF2` writer - "]
pub type CGIF2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CTCIF2` writer - "]
pub type CTCIF2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CHTIF2` writer - "]
pub type CHTIF2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CTEIF2` writer - "]
pub type CTEIF2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CGIF3` writer - "]
pub type CGIF3_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CTCIF3` writer - "]
pub type CTCIF3_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CHTIF3` writer - "]
pub type CHTIF3_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CTEIF3` writer - "]
pub type CTEIF3_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CGIF4` writer - "]
pub type CGIF4_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CTCIF4` writer - "]
pub type CTCIF4_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CHTIF4` writer - "]
pub type CHTIF4_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CTEIF4` writer - "]
pub type CTEIF4_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CGIF5` writer - "]
pub type CGIF5_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CTCIF5` writer - "]
pub type CTCIF5_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CHTIF5` writer - "]
pub type CHTIF5_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CTEIF5` writer - "]
pub type CTEIF5_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CGIF6` writer - "]
pub type CGIF6_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CTCIF6` writer - "]
pub type CTCIF6_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CHTIF6` writer - "]
pub type CHTIF6_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CTEIF6` writer - "]
pub type CTEIF6_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CGIF7` writer - "]
pub type CGIF7_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CTCIF7` writer - "]
pub type CTCIF7_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CHTIF7` writer - "]
pub type CHTIF7_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CTEIF7` writer - "]
pub type CTEIF7_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CGIF8` writer - "]
pub type CGIF8_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CTCIF8` writer - "]
pub type CTCIF8_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CHTIF8` writer - "]
pub type CHTIF8_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
#[doc = "Field `CTEIF8` writer - "]
pub type CTEIF8_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, bool, O>;
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn cgif1(&mut self) -> CGIF1_W<0> {
CGIF1_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn ctcif1(&mut self) -> CTCIF1_W<1> {
CTCIF1_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn chtif1(&mut self) -> CHTIF1_W<2> {
CHTIF1_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn cteif1(&mut self) -> CTEIF1_W<3> {
CTEIF1_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn cgif2(&mut self) -> CGIF2_W<4> {
CGIF2_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn ctcif2(&mut self) -> CTCIF2_W<5> {
CTCIF2_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn chtif2(&mut self) -> CHTIF2_W<6> {
CHTIF2_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn cteif2(&mut self) -> CTEIF2_W<7> {
CTEIF2_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn cgif3(&mut self) -> CGIF3_W<8> {
CGIF3_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ctcif3(&mut self) -> CTCIF3_W<9> {
CTCIF3_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn chtif3(&mut self) -> CHTIF3_W<10> {
CHTIF3_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn cteif3(&mut self) -> CTEIF3_W<11> {
CTEIF3_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn cgif4(&mut self) -> CGIF4_W<12> {
CGIF4_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn ctcif4(&mut self) -> CTCIF4_W<13> {
CTCIF4_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn chtif4(&mut self) -> CHTIF4_W<14> {
CHTIF4_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn cteif4(&mut self) -> CTEIF4_W<15> {
CTEIF4_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn cgif5(&mut self) -> CGIF5_W<16> {
CGIF5_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn ctcif5(&mut self) -> CTCIF5_W<17> {
CTCIF5_W::new(self)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn chtif5(&mut self) -> CHTIF5_W<18> {
CHTIF5_W::new(self)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn cteif5(&mut self) -> CTEIF5_W<19> {
CTEIF5_W::new(self)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn cgif6(&mut self) -> CGIF6_W<20> {
CGIF6_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn ctcif6(&mut self) -> CTCIF6_W<21> {
CTCIF6_W::new(self)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn chtif6(&mut self) -> CHTIF6_W<22> {
CHTIF6_W::new(self)
}
#[doc = "Bit 23"]
#[inline(always)]
#[must_use]
pub fn cteif6(&mut self) -> CTEIF6_W<23> {
CTEIF6_W::new(self)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn cgif7(&mut self) -> CGIF7_W<24> {
CGIF7_W::new(self)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn ctcif7(&mut self) -> CTCIF7_W<25> {
CTCIF7_W::new(self)
}
#[doc = "Bit 26"]
#[inline(always)]
#[must_use]
pub fn chtif7(&mut self) -> CHTIF7_W<26> {
CHTIF7_W::new(self)
}
#[doc = "Bit 27"]
#[inline(always)]
#[must_use]
pub fn cteif7(&mut self) -> CTEIF7_W<27> {
CTEIF7_W::new(self)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn cgif8(&mut self) -> CGIF8_W<28> {
CGIF8_W::new(self)
}
#[doc = "Bit 29"]
#[inline(always)]
#[must_use]
pub fn ctcif8(&mut self) -> CTCIF8_W<29> {
CTCIF8_W::new(self)
}
#[doc = "Bit 30"]
#[inline(always)]
#[must_use]
pub fn chtif8(&mut self) -> CHTIF8_W<30> {
CHTIF8_W::new(self)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn cteif8(&mut self) -> CTEIF8_W<31> {
CTEIF8_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA Interrupt Flag Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifcr](index.html) module"]
pub struct IFCR_SPEC;
impl crate::RegisterSpec for IFCR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [ifcr::W](W) writer structure"]
impl crate::Writable for IFCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IFCR to value 0"]
impl crate::Resettable for IFCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCR1 (rw) register accessor: an alias for `Reg<CCR1_SPEC>`"]
pub type CCR1 = crate::Reg<ccr1::CCR1_SPEC>;
#[doc = "DMA Channel 1 Configuration Register"]
pub mod ccr1 {
#[doc = "Register `CCR1` reader"]
pub struct R(crate::R<CCR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCR1` writer"]
pub struct W(crate::W<CCR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EN` reader - "]
pub type EN_R = crate::BitReader<bool>;
#[doc = "Field `EN` writer - "]
pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR1_SPEC, bool, O>;
#[doc = "Field `TCIE` reader - "]
pub type TCIE_R = crate::BitReader<bool>;
#[doc = "Field `TCIE` writer - "]
pub type TCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR1_SPEC, bool, O>;
#[doc = "Field `HTIE` reader - "]
pub type HTIE_R = crate::BitReader<bool>;
#[doc = "Field `HTIE` writer - "]
pub type HTIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR1_SPEC, bool, O>;
#[doc = "Field `TEIE` reader - "]
pub type TEIE_R = crate::BitReader<bool>;
#[doc = "Field `TEIE` writer - "]
pub type TEIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR1_SPEC, bool, O>;
#[doc = "Field `DIR` reader - "]
pub type DIR_R = crate::BitReader<bool>;
#[doc = "Field `DIR` writer - "]
pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR1_SPEC, bool, O>;
#[doc = "Field `CIRC` reader - "]
pub type CIRC_R = crate::BitReader<bool>;
#[doc = "Field `CIRC` writer - "]
pub type CIRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR1_SPEC, bool, O>;
#[doc = "Field `PINC` reader - "]
pub type PINC_R = crate::BitReader<bool>;
#[doc = "Field `PINC` writer - "]
pub type PINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR1_SPEC, bool, O>;
#[doc = "Field `MINC` reader - "]
pub type MINC_R = crate::BitReader<bool>;
#[doc = "Field `MINC` writer - "]
pub type MINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR1_SPEC, bool, O>;
#[doc = "Field `PSIZE` reader - "]
pub type PSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PSIZE` writer - "]
pub type PSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCR1_SPEC, u8, u8, 2, O>;
#[doc = "Field `MSIZE` reader - "]
pub type MSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MSIZE` writer - "]
pub type MSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCR1_SPEC, u8, u8, 2, O>;
#[doc = "Field `PL` reader - "]
pub type PL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PL` writer - "]
pub type PL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCR1_SPEC, u8, u8, 2, O>;
#[doc = "Field `MEM2MEM` reader - "]
pub type MEM2MEM_R = crate::BitReader<bool>;
#[doc = "Field `MEM2MEM` writer - "]
pub type MEM2MEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR1_SPEC, bool, O>;
#[doc = "Field `ARE` reader - "]
pub type ARE_R = crate::BitReader<bool>;
#[doc = "Field `ARE` writer - "]
pub type ARE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR1_SPEC, bool, O>;
#[doc = "Field `Burst_en` reader - "]
pub type BURST_EN_R = crate::BitReader<bool>;
#[doc = "Field `Burst_en` writer - "]
pub type BURST_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR1_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn en(&self) -> EN_R {
EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn tcie(&self) -> TCIE_R {
TCIE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn htie(&self) -> HTIE_R {
HTIE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn teie(&self) -> TEIE_R {
TEIE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn dir(&self) -> DIR_R {
DIR_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn circ(&self) -> CIRC_R {
CIRC_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn pinc(&self) -> PINC_R {
PINC_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn minc(&self) -> MINC_R {
MINC_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn psize(&self) -> PSIZE_R {
PSIZE_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11"]
#[inline(always)]
pub fn msize(&self) -> MSIZE_R {
MSIZE_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13"]
#[inline(always)]
pub fn pl(&self) -> PL_R {
PL_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn mem2mem(&self) -> MEM2MEM_R {
MEM2MEM_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn are(&self) -> ARE_R {
ARE_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn burst_en(&self) -> BURST_EN_R {
BURST_EN_R::new(((self.bits >> 16) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn en(&mut self) -> EN_W<0> {
EN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TCIE_W<1> {
TCIE_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn htie(&mut self) -> HTIE_W<2> {
HTIE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn teie(&mut self) -> TEIE_W<3> {
TEIE_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DIR_W<4> {
DIR_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn circ(&mut self) -> CIRC_W<5> {
CIRC_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn pinc(&mut self) -> PINC_W<6> {
PINC_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn minc(&mut self) -> MINC_W<7> {
MINC_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn psize(&mut self) -> PSIZE_W<8> {
PSIZE_W::new(self)
}
#[doc = "Bits 10:11"]
#[inline(always)]
#[must_use]
pub fn msize(&mut self) -> MSIZE_W<10> {
MSIZE_W::new(self)
}
#[doc = "Bits 12:13"]
#[inline(always)]
#[must_use]
pub fn pl(&mut self) -> PL_W<12> {
PL_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn mem2mem(&mut self) -> MEM2MEM_W<14> {
MEM2MEM_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn are(&mut self) -> ARE_W<15> {
ARE_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn burst_en(&mut self) -> BURST_EN_W<16> {
BURST_EN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA Channel 1 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr1](index.html) module"]
pub struct CCR1_SPEC;
impl crate::RegisterSpec for CCR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccr1::R](R) reader structure"]
impl crate::Readable for CCR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccr1::W](W) writer structure"]
impl crate::Writable for CCR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCR1 to value 0"]
impl crate::Resettable for CCR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CNDTR1 (rw) register accessor: an alias for `Reg<CNDTR1_SPEC>`"]
pub type CNDTR1 = crate::Reg<cndtr1::CNDTR1_SPEC>;
#[doc = "DMA Channel 1 Transfer Number Register"]
pub mod cndtr1 {
#[doc = "Register `CNDTR1` reader"]
pub struct R(crate::R<CNDTR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CNDTR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CNDTR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CNDTR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CNDTR1` writer"]
pub struct W(crate::W<CNDTR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CNDTR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CNDTR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CNDTR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `NDT` reader - "]
pub type NDT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `NDT` writer - "]
pub type NDT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNDTR1_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn ndt(&self) -> NDT_R {
NDT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn ndt(&mut self) -> NDT_W<0> {
NDT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA Channel 1 Transfer Number Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cndtr1](index.html) module"]
pub struct CNDTR1_SPEC;
impl crate::RegisterSpec for CNDTR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cndtr1::R](R) reader structure"]
impl crate::Readable for CNDTR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cndtr1::W](W) writer structure"]
impl crate::Writable for CNDTR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CNDTR1 to value 0"]
impl crate::Resettable for CNDTR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CPAR1 (rw) register accessor: an alias for `Reg<CPAR1_SPEC>`"]
pub type CPAR1 = crate::Reg<cpar1::CPAR1_SPEC>;
#[doc = "DMA Channel 1 Peripheral Address Register"]
pub mod cpar1 {
#[doc = "Register `CPAR1` reader"]
pub struct R(crate::R<CPAR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CPAR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CPAR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CPAR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CPAR1` writer"]
pub struct W(crate::W<CPAR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CPAR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CPAR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CPAR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PA` reader - "]
pub type PA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `PA` writer - "]
pub type PA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CPAR1_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn pa(&self) -> PA_R {
PA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn pa(&mut self) -> PA_W<0> {
PA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA Channel 1 Peripheral Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpar1](index.html) module"]
pub struct CPAR1_SPEC;
impl crate::RegisterSpec for CPAR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cpar1::R](R) reader structure"]
impl crate::Readable for CPAR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cpar1::W](W) writer structure"]
impl crate::Writable for CPAR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CPAR1 to value 0"]
impl crate::Resettable for CPAR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CMAR1 (rw) register accessor: an alias for `Reg<CMAR1_SPEC>`"]
pub type CMAR1 = crate::Reg<cmar1::CMAR1_SPEC>;
#[doc = "DMA Channel 1 Memory Address Register"]
pub mod cmar1 {
#[doc = "Register `CMAR1` reader"]
pub struct R(crate::R<CMAR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CMAR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CMAR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CMAR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CMAR1` writer"]
pub struct W(crate::W<CMAR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CMAR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CMAR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CMAR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MA` reader - "]
pub type MA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `MA` writer - "]
pub type MA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMAR1_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn ma(&self) -> MA_R {
MA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn ma(&mut self) -> MA_W<0> {
MA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA Channel 1 Memory Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmar1](index.html) module"]
pub struct CMAR1_SPEC;
impl crate::RegisterSpec for CMAR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cmar1::R](R) reader structure"]
impl crate::Readable for CMAR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cmar1::W](W) writer structure"]
impl crate::Writable for CMAR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CMAR1 to value 0"]
impl crate::Resettable for CMAR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
pub use ccr1 as ccr2;
pub use ccr1 as ccr3;
pub use ccr1 as ccr4;
pub use ccr1 as ccr5;
pub use ccr1 as ccr6;
pub use ccr1 as ccr7;
pub use ccr1 as ccr8;
pub use cmar1 as cmar2;
pub use cmar1 as cmar3;
pub use cmar1 as cmar4;
pub use cmar1 as cmar5;
pub use cmar1 as cmar6;
pub use cmar1 as cmar7;
pub use cmar1 as cmar8;
pub use cndtr1 as cndtr2;
pub use cndtr1 as cndtr3;
pub use cndtr1 as cndtr4;
pub use cndtr1 as cndtr5;
pub use cndtr1 as cndtr6;
pub use cndtr1 as cndtr7;
pub use cndtr1 as cndtr8;
pub use cpar1 as cpar2;
pub use cpar1 as cpar3;
pub use cpar1 as cpar4;
pub use cpar1 as cpar5;
pub use cpar1 as cpar6;
pub use cpar1 as cpar7;
pub use cpar1 as cpar8;
pub use CCR1 as CCR2;
pub use CCR1 as CCR3;
pub use CCR1 as CCR4;
pub use CCR1 as CCR5;
pub use CCR1 as CCR6;
pub use CCR1 as CCR7;
pub use CCR1 as CCR8;
pub use CMAR1 as CMAR2;
pub use CMAR1 as CMAR3;
pub use CMAR1 as CMAR4;
pub use CMAR1 as CMAR5;
pub use CMAR1 as CMAR6;
pub use CMAR1 as CMAR7;
pub use CMAR1 as CMAR8;
pub use CNDTR1 as CNDTR2;
pub use CNDTR1 as CNDTR3;
pub use CNDTR1 as CNDTR4;
pub use CNDTR1 as CNDTR5;
pub use CNDTR1 as CNDTR6;
pub use CNDTR1 as CNDTR7;
pub use CNDTR1 as CNDTR8;
pub use CPAR1 as CPAR2;
pub use CPAR1 as CPAR3;
pub use CPAR1 as CPAR4;
pub use CPAR1 as CPAR5;
pub use CPAR1 as CPAR6;
pub use CPAR1 as CPAR7;
pub use CPAR1 as CPAR8;
}
#[doc = "DMA2"]
pub struct DMA2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for DMA2 {}
impl DMA2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const dma1::RegisterBlock = 0x4002_0400 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const dma1::RegisterBlock {
Self::PTR
}
}
impl Deref for DMA2 {
type Target = dma1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for DMA2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DMA2").finish()
}
}
#[doc = "DMA2"]
pub use self::dma1 as dma2;
#[doc = "ENET"]
pub struct ENET {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for ENET {}
impl ENET {
#[doc = r"Pointer to the register block"]
pub const PTR: *const enet::RegisterBlock = 0x4002_8000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const enet::RegisterBlock {
Self::PTR
}
}
impl Deref for ENET {
type Target = enet::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for ENET {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("ENET").finish()
}
}
#[doc = "ENET"]
pub mod enet {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - MAC Control Register"]
pub maccr: MACCR,
#[doc = "0x04 - MAC Address Filtering Control Register"]
pub macafr: MACAFR,
#[doc = "0x08 - MAC HASH table high register"]
pub machthr: MACHTHR,
#[doc = "0x0c - MAC HASH table low register"]
pub machtlr: MACHTLR,
#[doc = "0x10 - MAC SMI Address Register"]
pub macsmiar: MACSMIAR,
#[doc = "0x14 - MAC SMI Data Register"]
pub macsmidr: MACSMIDR,
#[doc = "0x18 - MAC Flow Control Register"]
pub macfcr: MACFCR,
#[doc = "0x1c - MAC VLAN TAG Receive Register"]
pub macvltrr: MACVLTRR,
_reserved8: [u8; 0x04],
#[doc = "0x24 - MAC Status Register"]
pub macsr: MACSR,
#[doc = "0x28 - MAC Remote Wakeup Frame Filter Register"]
pub pmtrwfr: PMTRWFR,
#[doc = "0x2c - MAC PMT Control Register"]
pub pmtcr: PMTCR,
_reserved11: [u8; 0x08],
#[doc = "0x38 - MAC Interrupt Status Register"]
pub macisr: MACISR,
#[doc = "0x3c - MAC Interrupt Mask Register"]
pub macimr: MACIMR,
#[doc = "0x40 - MAC Filter Address High Register 0"]
pub macahr0: MACAHR0,
#[doc = "0x44 - MAC Filter Address Low Register 0"]
pub macalr0: MACALR0,
#[doc = "0x48 - MAC Filter Address High Register 0"]
pub macahr1: MACAHR1,
#[doc = "0x4c - MAC Filter Address Low Register 0"]
pub macalr1: MACALR1,
#[doc = "0x50 - MAC Filter Address High Register 0"]
pub macahr2: MACAHR2,
#[doc = "0x54 - MAC Filter Address Low Register 0"]
pub macalr2: MACALR2,
#[doc = "0x58 - MAC Filter Address High Register 0"]
pub macahr3: MACAHR3,
#[doc = "0x5c - MAC Filter Address Low Register 0"]
pub macalr3: MACALR3,
#[doc = "0x60 - MAC Filter Address High Register 0"]
pub macahr4: MACAHR4,
#[doc = "0x64 - MAC Filter Address Low Register 0"]
pub macalr4: MACALR4,
#[doc = "0x68 - MAC Filter Address High Register 0"]
pub macahr5: MACAHR5,
#[doc = "0x6c - MAC Filter Address Low Register 0"]
pub macalr5: MACALR5,
_reserved25: [u8; 0x90],
#[doc = "0x100 - MMC Control Register"]
pub mmccr: MMCCR,
#[doc = "0x104 - MMC Receive Status Register"]
pub mmcrsr: MMCRSR,
#[doc = "0x108 - MMC Transmit Status Register"]
pub mmctsr: MMCTSR,
#[doc = "0x10c - MMC receive interrupt register"]
pub mmcrir: MMCRIR,
#[doc = "0x110 - MMC Transmit Interrupt Register"]
pub mmctir: MMCTIR,
_reserved30: [u8; 0x38],
#[doc = "0x14c - MMC sends a good frame statistics register after a single collision error"]
pub mmctgscr: MMCTGSCR,
#[doc = "0x150 - MMC sends good frame statistics register after multiple collision errors"]
pub mmctgmcr: MMCTGMCR,
_reserved32: [u8; 0x14],
#[doc = "0x168 - MMC sends good frame pass statistics register"]
pub mmctgr: MMCTGR,
_reserved33: [u8; 0x28],
#[doc = "0x194 - MMC CRC Error Received Frame Statistics Register"]
pub mmcrcrcer: MMCRCRCER,
#[doc = "0x198 - MMC Alignment Error Received Frame Statistics Register"]
pub mmcralier: MMCRALIER,
_reserved35: [u8; 0x28],
#[doc = "0x1c4 - MMC Receive Unicast Good Frame Statistics Register"]
pub mmcrugr: MMCRUGR,
_reserved36: [u8; 0x03bc],
#[doc = "0x584 - MAC VLAN TAG send register"]
pub macvlttr: MACVLTTR,
#[doc = "0x588 - MAC VLAN HASH Table Register"]
pub macvlhtr: MACVLHTR,
_reserved38: [u8; 0x0174],
#[doc = "0x700 - PTP Control Register"]
pub ptpcr: PTPCR,
#[doc = "0x704 - PTP subsecond adder register"]
pub ptpnsar: PTPNSAR,
#[doc = "0x708 - PTP System Second Register"]
pub ptpsbsr: PTPSBSR,
#[doc = "0x70c - PTP System Subsecond Register"]
pub ptpsnsr: PTPSNSR,
#[doc = "0x710 - PTP Update Seconds Register"]
pub ptpubsr: PTPUBSR,
#[doc = "0x714 - PTP update subsecond register"]
pub ptpunsr: PTPUNSR,
#[doc = "0x718 - PTP Basic Addend Register"]
pub ptpbsar: PTPBSAR,
#[doc = "0x71c - PTP Target Seconds Register 0"]
pub ptptbsr: PTPTBSR,
#[doc = "0x720 - PTP Target Subsecond Register 0"]
pub ptptnsr: PTPTNSR,
_reserved47: [u8; 0x04],
#[doc = "0x728 - PTP Status Register"]
pub ptpsr: PTPSR,
#[doc = "0x72c - PTP PPS Control Register"]
pub ptpppsr: PTPPPSR,
_reserved49: [u8; 0x08d0],
#[doc = "0x1000 - DMA bus control register"]
pub dmabsr: DMABSR,
#[doc = "0x1004 - DMA transmit polling register"]
pub dmatxpdr: DMATXPDR,
#[doc = "0x1008 - DMA Receive Polling Register"]
pub dmarxpdr: DMARXPDR,
#[doc = "0x100c - DMA Receive Descriptor Address Register"]
pub dmarxdsar: DMARXDSAR,
#[doc = "0x1010 - DMA transmit descriptor address register"]
pub dmatxdsar: DMATXDSAR,
#[doc = "0x1014 - DMA status register"]
pub dmasr: DMASR,
#[doc = "0x1018 - DMA work mode register"]
pub dmamdr: DMAMDR,
#[doc = "0x101c - DMA Interrupt Register"]
pub dmair: DMAIR,
#[doc = "0x1020 - DMA Frame Loss Statistics Register"]
pub dmaflcr: DMAFLCR,
#[doc = "0x1024 - DMA Watchdog Timing Register"]
pub dmawdtr: DMAWDTR,
_reserved59: [u8; 0x20],
#[doc = "0x1048 - DMA current transmit descriptor address register"]
pub dmacurtxdsar: DMACURTXDSAR,
#[doc = "0x104c - DMA current receive descriptor address register"]
pub dmacurrxdsar: DMACURRXDSAR,
#[doc = "0x1050 - DMA current send buffer address register"]
pub dmacurtxbfar: DMACURTXBFAR,
#[doc = "0x1054 - DMA current receive buffer address register"]
pub dmacurrxbfar: DMACURRXBFAR,
}
#[doc = "MACSMIAR (rw) register accessor: an alias for `Reg<MACSMIAR_SPEC>`"]
pub type MACSMIAR = crate::Reg<macsmiar::MACSMIAR_SPEC>;
#[doc = "MAC SMI Address Register"]
pub mod macsmiar {
#[doc = "Register `MACSMIAR` reader"]
pub struct R(crate::R<MACSMIAR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MACSMIAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MACSMIAR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MACSMIAR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MACSMIAR` writer"]
pub struct W(crate::W<MACSMIAR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MACSMIAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MACSMIAR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MACSMIAR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SMIBY` reader - "]
pub type SMIBY_R = crate::BitReader<bool>;
#[doc = "Field `SMIBY` writer - "]
pub type SMIBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACSMIAR_SPEC, bool, O>;
#[doc = "Field `SMIWR` reader - "]
pub type SMIWR_R = crate::BitReader<bool>;
#[doc = "Field `SMIWR` writer - "]
pub type SMIWR_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACSMIAR_SPEC, bool, O>;
#[doc = "Field `SMICLK` reader - "]
pub type SMICLK_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMICLK` writer - "]
pub type SMICLK_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, MACSMIAR_SPEC, u8, u8, 4, O>;
#[doc = "Field `SMIREG` reader - "]
pub type SMIREG_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMIREG` writer - "]
pub type SMIREG_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, MACSMIAR_SPEC, u8, u8, 5, O>;
#[doc = "Field `SMIADD` reader - "]
pub type SMIADD_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMIADD` writer - "]
pub type SMIADD_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, MACSMIAR_SPEC, u8, u8, 5, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn smiby(&self) -> SMIBY_R {
SMIBY_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn smiwr(&self) -> SMIWR_R {
SMIWR_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:5"]
#[inline(always)]
pub fn smiclk(&self) -> SMICLK_R {
SMICLK_R::new(((self.bits >> 2) & 0x0f) as u8)
}
#[doc = "Bits 6:10"]
#[inline(always)]
pub fn smireg(&self) -> SMIREG_R {
SMIREG_R::new(((self.bits >> 6) & 0x1f) as u8)
}
#[doc = "Bits 11:15"]
#[inline(always)]
pub fn smiadd(&self) -> SMIADD_R {
SMIADD_R::new(((self.bits >> 11) & 0x1f) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn smiby(&mut self) -> SMIBY_W<0> {
SMIBY_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn smiwr(&mut self) -> SMIWR_W<1> {
SMIWR_W::new(self)
}
#[doc = "Bits 2:5"]
#[inline(always)]
#[must_use]
pub fn smiclk(&mut self) -> SMICLK_W<2> {
SMICLK_W::new(self)
}
#[doc = "Bits 6:10"]
#[inline(always)]
#[must_use]
pub fn smireg(&mut self) -> SMIREG_W<6> {
SMIREG_W::new(self)
}
#[doc = "Bits 11:15"]
#[inline(always)]
#[must_use]
pub fn smiadd(&mut self) -> SMIADD_W<11> {
SMIADD_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MAC SMI Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [macsmiar](index.html) module"]
pub struct MACSMIAR_SPEC;
impl crate::RegisterSpec for MACSMIAR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [macsmiar::R](R) reader structure"]
impl crate::Readable for MACSMIAR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [macsmiar::W](W) writer structure"]
impl crate::Writable for MACSMIAR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MACSMIAR to value 0"]
impl crate::Resettable for MACSMIAR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MACSMIDR (rw) register accessor: an alias for `Reg<MACSMIDR_SPEC>`"]
pub type MACSMIDR = crate::Reg<macsmidr::MACSMIDR_SPEC>;
#[doc = "MAC SMI Data Register"]
pub mod macsmidr {
#[doc = "Register `MACSMIDR` reader"]
pub struct R(crate::R<MACSMIDR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MACSMIDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MACSMIDR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MACSMIDR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MACSMIDR` writer"]
pub struct W(crate::W<MACSMIDR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MACSMIDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MACSMIDR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MACSMIDR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SMIDATA` reader - "]
pub type SMIDATA_R = crate::FieldReader<u16, u16>;
#[doc = "Field `SMIDATA` writer - "]
pub type SMIDATA_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, MACSMIDR_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn smidata(&self) -> SMIDATA_R {
SMIDATA_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn smidata(&mut self) -> SMIDATA_W<0> {
SMIDATA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MAC SMI Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [macsmidr](index.html) module"]
pub struct MACSMIDR_SPEC;
impl crate::RegisterSpec for MACSMIDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [macsmidr::R](R) reader structure"]
impl crate::Readable for MACSMIDR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [macsmidr::W](W) writer structure"]
impl crate::Writable for MACSMIDR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MACSMIDR to value 0"]
impl crate::Resettable for MACSMIDR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MACCR (rw) register accessor: an alias for `Reg<MACCR_SPEC>`"]
pub type MACCR = crate::Reg<maccr::MACCR_SPEC>;
#[doc = "MAC Control Register"]
pub mod maccr {
#[doc = "Register `MACCR` reader"]
pub struct R(crate::R<MACCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MACCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MACCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MACCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MACCR` writer"]
pub struct W(crate::W<MACCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MACCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MACCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MACCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RE` reader - "]
pub type RE_R = crate::BitReader<bool>;
#[doc = "Field `RE` writer - "]
pub type RE_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACCR_SPEC, bool, O>;
#[doc = "Field `TE` reader - "]
pub type TE_R = crate::BitReader<bool>;
#[doc = "Field `TE` writer - "]
pub type TE_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACCR_SPEC, bool, O>;
#[doc = "Field `DLYC` reader - "]
pub type DLYC_R = crate::BitReader<bool>;
#[doc = "Field `DLYC` writer - "]
pub type DLYC_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACCR_SPEC, bool, O>;
#[doc = "Field `BL` reader - "]
pub type BL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `BL` writer - "]
pub type BL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MACCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `APCS` reader - "]
pub type APCS_R = crate::BitReader<bool>;
#[doc = "Field `APCS` writer - "]
pub type APCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACCR_SPEC, bool, O>;
#[doc = "Field `RETY` reader - "]
pub type RETY_R = crate::BitReader<bool>;
#[doc = "Field `RETY` writer - "]
pub type RETY_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACCR_SPEC, bool, O>;
#[doc = "Field `IPCO` reader - "]
pub type IPCO_R = crate::BitReader<bool>;
#[doc = "Field `IPCO` writer - "]
pub type IPCO_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACCR_SPEC, bool, O>;
#[doc = "Field `DM` reader - "]
pub type DM_R = crate::BitReader<bool>;
#[doc = "Field `DM` writer - "]
pub type DM_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACCR_SPEC, bool, O>;
#[doc = "Field `LM` reader - "]
pub type LM_R = crate::BitReader<bool>;
#[doc = "Field `LM` writer - "]
pub type LM_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACCR_SPEC, bool, O>;
#[doc = "Field `RDIS` reader - "]
pub type RDIS_R = crate::BitReader<bool>;
#[doc = "Field `RDIS` writer - "]
pub type RDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACCR_SPEC, bool, O>;
#[doc = "Field `MCRS` reader - "]
pub type MCRS_R = crate::BitReader<bool>;
#[doc = "Field `MCRS` writer - "]
pub type MCRS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACCR_SPEC, bool, O>;
#[doc = "Field `IFG` reader - "]
pub type IFG_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IFG` writer - "]
pub type IFG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MACCR_SPEC, u8, u8, 3, O>;
#[doc = "Field `JAB` reader - "]
pub type JAB_R = crate::BitReader<bool>;
#[doc = "Field `JAB` writer - "]
pub type JAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACCR_SPEC, bool, O>;
#[doc = "Field `WDT` reader - "]
pub type WDT_R = crate::BitReader<bool>;
#[doc = "Field `WDT` writer - "]
pub type WDT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACCR_SPEC, bool, O>;
#[doc = "Field `CST` reader - "]
pub type CST_R = crate::BitReader<bool>;
#[doc = "Field `CST` writer - "]
pub type CST_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACCR_SPEC, bool, O>;
#[doc = "Field `SAIRC` reader - "]
pub type SAIRC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SAIRC` writer - "]
pub type SAIRC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MACCR_SPEC, u8, u8, 4, O>;
impl R {
#[doc = "Bit 2"]
#[inline(always)]
pub fn re(&self) -> RE_R {
RE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn te(&self) -> TE_R {
TE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn dlyc(&self) -> DLYC_R {
DLYC_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6"]
#[inline(always)]
pub fn bl(&self) -> BL_R {
BL_R::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn apcs(&self) -> APCS_R {
APCS_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn rety(&self) -> RETY_R {
RETY_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn ipco(&self) -> IPCO_R {
IPCO_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn dm(&self) -> DM_R {
DM_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn lm(&self) -> LM_R {
LM_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn rdis(&self) -> RDIS_R {
RDIS_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn mcrs(&self) -> MCRS_R {
MCRS_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 17:19"]
#[inline(always)]
pub fn ifg(&self) -> IFG_R {
IFG_R::new(((self.bits >> 17) & 7) as u8)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn jab(&self) -> JAB_R {
JAB_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23"]
#[inline(always)]
pub fn wdt(&self) -> WDT_R {
WDT_R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn cst(&self) -> CST_R {
CST_R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bits 28:31"]
#[inline(always)]
pub fn sairc(&self) -> SAIRC_R {
SAIRC_R::new(((self.bits >> 28) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn re(&mut self) -> RE_W<2> {
RE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn te(&mut self) -> TE_W<3> {
TE_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn dlyc(&mut self) -> DLYC_W<4> {
DLYC_W::new(self)
}
#[doc = "Bits 5:6"]
#[inline(always)]
#[must_use]
pub fn bl(&mut self) -> BL_W<5> {
BL_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn apcs(&mut self) -> APCS_W<7> {
APCS_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn rety(&mut self) -> RETY_W<9> {
RETY_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn ipco(&mut self) -> IPCO_W<10> {
IPCO_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn dm(&mut self) -> DM_W<11> {
DM_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn lm(&mut self) -> LM_W<12> {
LM_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn rdis(&mut self) -> RDIS_W<13> {
RDIS_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn mcrs(&mut self) -> MCRS_W<16> {
MCRS_W::new(self)
}
#[doc = "Bits 17:19"]
#[inline(always)]
#[must_use]
pub fn ifg(&mut self) -> IFG_W<17> {
IFG_W::new(self)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn jab(&mut self) -> JAB_W<22> {
JAB_W::new(self)
}
#[doc = "Bit 23"]
#[inline(always)]
#[must_use]
pub fn wdt(&mut self) -> WDT_W<23> {
WDT_W::new(self)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn cst(&mut self) -> CST_W<25> {
CST_W::new(self)
}
#[doc = "Bits 28:31"]
#[inline(always)]
#[must_use]
pub fn sairc(&mut self) -> SAIRC_W<28> {
SAIRC_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MAC Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maccr](index.html) module"]
pub struct MACCR_SPEC;
impl crate::RegisterSpec for MACCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [maccr::R](R) reader structure"]
impl crate::Readable for MACCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [maccr::W](W) writer structure"]
impl crate::Writable for MACCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MACCR to value 0x8000"]
impl crate::Resettable for MACCR_SPEC {
const RESET_VALUE: Self::Ux = 0x8000;
}
}
#[doc = "MACSR (r) register accessor: an alias for `Reg<MACSR_SPEC>`"]
pub type MACSR = crate::Reg<macsr::MACSR_SPEC>;
#[doc = "MAC Status Register"]
pub mod macsr {
#[doc = "Register `MACSR` reader"]
pub struct R(crate::R<MACSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MACSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MACSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MACSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `MRE` reader - "]
pub type MRE_R = crate::BitReader<bool>;
#[doc = "Field `MRS` reader - "]
pub type MRS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `RXFWA` reader - "]
pub type RXFWA_R = crate::BitReader<bool>;
#[doc = "Field `RXFRS` reader - "]
pub type RXFRS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `RXFL` reader - "]
pub type RXFL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MTE` reader - "]
pub type MTE_R = crate::BitReader<bool>;
#[doc = "Field `MTS` reader - "]
pub type MTS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MTP` reader - "]
pub type MTP_R = crate::BitReader<bool>;
#[doc = "Field `TXFRS` reader - "]
pub type TXFRS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TXFWA` reader - "]
pub type TXFWA_R = crate::BitReader<bool>;
#[doc = "Field `TXFNE` reader - "]
pub type TXFNE_R = crate::BitReader<bool>;
#[doc = "Field `TXFF` reader - "]
pub type TXFF_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn mre(&self) -> MRE_R {
MRE_R::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2"]
#[inline(always)]
pub fn mrs(&self) -> MRS_R {
MRS_R::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn rxfwa(&self) -> RXFWA_R {
RXFWA_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6"]
#[inline(always)]
pub fn rxfrs(&self) -> RXFRS_R {
RXFRS_R::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn rxfl(&self) -> RXFL_R {
RXFL_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn mte(&self) -> MTE_R {
MTE_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 17:18"]
#[inline(always)]
pub fn mts(&self) -> MTS_R {
MTS_R::new(((self.bits >> 17) & 3) as u8)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn mtp(&self) -> MTP_R {
MTP_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bits 20:21"]
#[inline(always)]
pub fn txfrs(&self) -> TXFRS_R {
TXFRS_R::new(((self.bits >> 20) & 3) as u8)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn txfwa(&self) -> TXFWA_R {
TXFWA_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn txfne(&self) -> TXFNE_R {
TXFNE_R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn txff(&self) -> TXFF_R {
TXFF_R::new(((self.bits >> 25) & 1) != 0)
}
}
#[doc = "MAC Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [macsr](index.html) module"]
pub struct MACSR_SPEC;
impl crate::RegisterSpec for MACSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [macsr::R](R) reader structure"]
impl crate::Readable for MACSR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets MACSR to value 0"]
impl crate::Resettable for MACSR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MACFCR (rw) register accessor: an alias for `Reg<MACFCR_SPEC>`"]
pub type MACFCR = crate::Reg<macfcr::MACFCR_SPEC>;
#[doc = "MAC Flow Control Register"]
pub mod macfcr {
#[doc = "Register `MACFCR` reader"]
pub struct R(crate::R<MACFCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MACFCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MACFCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MACFCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MACFCR` writer"]
pub struct W(crate::W<MACFCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MACFCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MACFCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MACFCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `FCBBPA` reader - "]
pub type FCBBPA_R = crate::BitReader<bool>;
#[doc = "Field `FCBBPA` writer - "]
pub type FCBBPA_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACFCR_SPEC, bool, O>;
#[doc = "Field `FTE` reader - "]
pub type FTE_R = crate::BitReader<bool>;
#[doc = "Field `FTE` writer - "]
pub type FTE_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACFCR_SPEC, bool, O>;
#[doc = "Field `FRE` reader - "]
pub type FRE_R = crate::BitReader<bool>;
#[doc = "Field `FRE` writer - "]
pub type FRE_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACFCR_SPEC, bool, O>;
#[doc = "Field `UPF` reader - "]
pub type UPF_R = crate::BitReader<bool>;
#[doc = "Field `UPF` writer - "]
pub type UPF_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACFCR_SPEC, bool, O>;
#[doc = "Field `PLT` reader - "]
pub type PLT_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PLT` writer - "]
pub type PLT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MACFCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `DZQP` reader - "]
pub type DZQP_R = crate::BitReader<bool>;
#[doc = "Field `DZQP` writer - "]
pub type DZQP_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACFCR_SPEC, bool, O>;
#[doc = "Field `PSET` reader - "]
pub type PSET_R = crate::FieldReader<u16, u16>;
#[doc = "Field `PSET` writer - "]
pub type PSET_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, MACFCR_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn fcbbpa(&self) -> FCBBPA_R {
FCBBPA_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn fte(&self) -> FTE_R {
FTE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn fre(&self) -> FRE_R {
FRE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn upf(&self) -> UPF_R {
UPF_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:5"]
#[inline(always)]
pub fn plt(&self) -> PLT_R {
PLT_R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn dzqp(&self) -> DZQP_R {
DZQP_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn pset(&self) -> PSET_R {
PSET_R::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn fcbbpa(&mut self) -> FCBBPA_W<0> {
FCBBPA_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn fte(&mut self) -> FTE_W<1> {
FTE_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn fre(&mut self) -> FRE_W<2> {
FRE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn upf(&mut self) -> UPF_W<3> {
UPF_W::new(self)
}
#[doc = "Bits 4:5"]
#[inline(always)]
#[must_use]
pub fn plt(&mut self) -> PLT_W<4> {
PLT_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn dzqp(&mut self) -> DZQP_W<7> {
DZQP_W::new(self)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn pset(&mut self) -> PSET_W<16> {
PSET_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MAC Flow Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [macfcr](index.html) module"]
pub struct MACFCR_SPEC;
impl crate::RegisterSpec for MACFCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [macfcr::R](R) reader structure"]
impl crate::Readable for MACFCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [macfcr::W](W) writer structure"]
impl crate::Writable for MACFCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MACFCR to value 0"]
impl crate::Resettable for MACFCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MACISR (r) register accessor: an alias for `Reg<MACISR_SPEC>`"]
pub type MACISR = crate::Reg<macisr::MACISR_SPEC>;
#[doc = "MAC Interrupt Status Register"]
pub mod macisr {
#[doc = "Register `MACISR` reader"]
pub struct R(crate::R<MACISR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MACISR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MACISR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MACISR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `PMTIS` reader - "]
pub type PMTIS_R = crate::BitReader<bool>;
#[doc = "Field `MMCIS` reader - "]
pub type MMCIS_R = crate::BitReader<bool>;
#[doc = "Field `MMCRXIS` reader - "]
pub type MMCRXIS_R = crate::BitReader<bool>;
#[doc = "Field `MMCTXIS` reader - "]
pub type MMCTXIS_R = crate::BitReader<bool>;
#[doc = "Field `PTPIS` reader - "]
pub type PTPIS_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 3"]
#[inline(always)]
pub fn pmtis(&self) -> PMTIS_R {
PMTIS_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn mmcis(&self) -> MMCIS_R {
MMCIS_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn mmcrxis(&self) -> MMCRXIS_R {
MMCRXIS_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn mmctxis(&self) -> MMCTXIS_R {
MMCTXIS_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ptpis(&self) -> PTPIS_R {
PTPIS_R::new(((self.bits >> 9) & 1) != 0)
}
}
#[doc = "MAC Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [macisr](index.html) module"]
pub struct MACISR_SPEC;
impl crate::RegisterSpec for MACISR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [macisr::R](R) reader structure"]
impl crate::Readable for MACISR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets MACISR to value 0"]
impl crate::Resettable for MACISR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MACIMR (rw) register accessor: an alias for `Reg<MACIMR_SPEC>`"]
pub type MACIMR = crate::Reg<macimr::MACIMR_SPEC>;
#[doc = "MAC Interrupt Mask Register"]
pub mod macimr {
#[doc = "Register `MACIMR` reader"]
pub struct R(crate::R<MACIMR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MACIMR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MACIMR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MACIMR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MACIMR` writer"]
pub struct W(crate::W<MACIMR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MACIMR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MACIMR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MACIMR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PMTIM` reader - "]
pub type PMTIM_R = crate::BitReader<bool>;
#[doc = "Field `PMTIM` writer - "]
pub type PMTIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACIMR_SPEC, bool, O>;
#[doc = "Field `PTPIM` reader - "]
pub type PTPIM_R = crate::BitReader<bool>;
#[doc = "Field `PTPIM` writer - "]
pub type PTPIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACIMR_SPEC, bool, O>;
impl R {
#[doc = "Bit 3"]
#[inline(always)]
pub fn pmtim(&self) -> PMTIM_R {
PMTIM_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ptpim(&self) -> PTPIM_R {
PTPIM_R::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn pmtim(&mut self) -> PMTIM_W<3> {
PMTIM_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ptpim(&mut self) -> PTPIM_W<9> {
PTPIM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MAC Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [macimr](index.html) module"]
pub struct MACIMR_SPEC;
impl crate::RegisterSpec for MACIMR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [macimr::R](R) reader structure"]
impl crate::Readable for MACIMR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [macimr::W](W) writer structure"]
impl crate::Writable for MACIMR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MACIMR to value 0"]
impl crate::Resettable for MACIMR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MACAFR (rw) register accessor: an alias for `Reg<MACAFR_SPEC>`"]
pub type MACAFR = crate::Reg<macafr::MACAFR_SPEC>;
#[doc = "MAC Address Filtering Control Register"]
pub mod macafr {
#[doc = "Register `MACAFR` reader"]
pub struct R(crate::R<MACAFR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MACAFR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MACAFR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MACAFR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MACAFR` writer"]
pub struct W(crate::W<MACAFR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MACAFR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MACAFR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MACAFR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PM` reader - "]
pub type PM_R = crate::BitReader<bool>;
#[doc = "Field `PM` writer - "]
pub type PM_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACAFR_SPEC, bool, O>;
#[doc = "Field `HU` reader - "]
pub type HU_R = crate::BitReader<bool>;
#[doc = "Field `HU` writer - "]
pub type HU_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACAFR_SPEC, bool, O>;
#[doc = "Field `HM` reader - "]
pub type HM_R = crate::BitReader<bool>;
#[doc = "Field `HM` writer - "]
pub type HM_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACAFR_SPEC, bool, O>;
#[doc = "Field `DAIF` reader - "]
pub type DAIF_R = crate::BitReader<bool>;
#[doc = "Field `DAIF` writer - "]
pub type DAIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACAFR_SPEC, bool, O>;
#[doc = "Field `MCF` reader - "]
pub type MCF_R = crate::BitReader<bool>;
#[doc = "Field `MCF` writer - "]
pub type MCF_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACAFR_SPEC, bool, O>;
#[doc = "Field `BCF` reader - "]
pub type BCF_R = crate::BitReader<bool>;
#[doc = "Field `BCF` writer - "]
pub type BCF_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACAFR_SPEC, bool, O>;
#[doc = "Field `PCF` reader - "]
pub type PCF_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PCF` writer - "]
pub type PCF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MACAFR_SPEC, u8, u8, 2, O>;
#[doc = "Field `SAIF` reader - "]
pub type SAIF_R = crate::BitReader<bool>;
#[doc = "Field `SAIF` writer - "]
pub type SAIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACAFR_SPEC, bool, O>;
#[doc = "Field `SAF` reader - "]
pub type SAF_R = crate::BitReader<bool>;
#[doc = "Field `SAF` writer - "]
pub type SAF_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACAFR_SPEC, bool, O>;
#[doc = "Field `HPF` reader - "]
pub type HPF_R = crate::BitReader<bool>;
#[doc = "Field `HPF` writer - "]
pub type HPF_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACAFR_SPEC, bool, O>;
#[doc = "Field `VLTF` reader - "]
pub type VLTF_R = crate::BitReader<bool>;
#[doc = "Field `VLTF` writer - "]
pub type VLTF_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACAFR_SPEC, bool, O>;
#[doc = "Field `DNTU` reader - "]
pub type DNTU_R = crate::BitReader<bool>;
#[doc = "Field `DNTU` writer - "]
pub type DNTU_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACAFR_SPEC, bool, O>;
#[doc = "Field `RALL` reader - "]
pub type RALL_R = crate::BitReader<bool>;
#[doc = "Field `RALL` writer - "]
pub type RALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACAFR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pm(&self) -> PM_R {
PM_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn hu(&self) -> HU_R {
HU_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn hm(&self) -> HM_R {
HM_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn daif(&self) -> DAIF_R {
DAIF_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn mcf(&self) -> MCF_R {
MCF_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn bcf(&self) -> BCF_R {
BCF_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn pcf(&self) -> PCF_R {
PCF_R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn saif(&self) -> SAIF_R {
SAIF_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn saf(&self) -> SAF_R {
SAF_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn hpf(&self) -> HPF_R {
HPF_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn vltf(&self) -> VLTF_R {
VLTF_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn dntu(&self) -> DNTU_R {
DNTU_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn rall(&self) -> RALL_R {
RALL_R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pm(&mut self) -> PM_W<0> {
PM_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn hu(&mut self) -> HU_W<1> {
HU_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn hm(&mut self) -> HM_W<2> {
HM_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn daif(&mut self) -> DAIF_W<3> {
DAIF_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn mcf(&mut self) -> MCF_W<4> {
MCF_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn bcf(&mut self) -> BCF_W<5> {
BCF_W::new(self)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn pcf(&mut self) -> PCF_W<6> {
PCF_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn saif(&mut self) -> SAIF_W<8> {
SAIF_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn saf(&mut self) -> SAF_W<9> {
SAF_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn hpf(&mut self) -> HPF_W<10> {
HPF_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn vltf(&mut self) -> VLTF_W<16> {
VLTF_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn dntu(&mut self) -> DNTU_W<21> {
DNTU_W::new(self)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn rall(&mut self) -> RALL_W<31> {
RALL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MAC Address Filtering Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [macafr](index.html) module"]
pub struct MACAFR_SPEC;
impl crate::RegisterSpec for MACAFR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [macafr::R](R) reader structure"]
impl crate::Readable for MACAFR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [macafr::W](W) writer structure"]
impl crate::Writable for MACAFR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MACAFR to value 0"]
impl crate::Resettable for MACAFR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MACAHR0 (rw) register accessor: an alias for `Reg<MACAHR0_SPEC>`"]
pub type MACAHR0 = crate::Reg<macahr0::MACAHR0_SPEC>;
#[doc = "MAC Filter Address High Register 0"]
pub mod macahr0 {
#[doc = "Register `MACAHR0` reader"]
pub struct R(crate::R<MACAHR0_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MACAHR0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MACAHR0_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MACAHR0_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MACAHR0` writer"]
pub struct W(crate::W<MACAHR0_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MACAHR0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MACAHR0_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MACAHR0_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MACADDH` reader - "]
pub type MACADDH_R = crate::FieldReader<u16, u16>;
#[doc = "Field `MACADDH` writer - "]
pub type MACADDH_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, MACAHR0_SPEC, u16, u16, 16, O>;
#[doc = "Field `MBYTEC` reader - "]
pub type MBYTEC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MBYTEC` writer - "]
pub type MBYTEC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, MACAHR0_SPEC, u8, u8, 6, O>;
#[doc = "Field `SELE` reader - "]
pub type SELE_R = crate::BitReader<bool>;
#[doc = "Field `SELE` writer - "]
pub type SELE_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACAHR0_SPEC, bool, O>;
#[doc = "Field `ADDE` reader - "]
pub type ADDE_R = crate::BitReader<bool>;
#[doc = "Field `ADDE` writer - "]
pub type ADDE_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACAHR0_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn macaddh(&self) -> MACADDH_R {
MACADDH_R::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 24:29"]
#[inline(always)]
pub fn mbytec(&self) -> MBYTEC_R {
MBYTEC_R::new(((self.bits >> 24) & 0x3f) as u8)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn sele(&self) -> SELE_R {
SELE_R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn adde(&self) -> ADDE_R {
ADDE_R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn macaddh(&mut self) -> MACADDH_W<0> {
MACADDH_W::new(self)
}
#[doc = "Bits 24:29"]
#[inline(always)]
#[must_use]
pub fn mbytec(&mut self) -> MBYTEC_W<24> {
MBYTEC_W::new(self)
}
#[doc = "Bit 30"]
#[inline(always)]
#[must_use]
pub fn sele(&mut self) -> SELE_W<30> {
SELE_W::new(self)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn adde(&mut self) -> ADDE_W<31> {
ADDE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MAC Filter Address High Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [macahr0](index.html) module"]
pub struct MACAHR0_SPEC;
impl crate::RegisterSpec for MACAHR0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [macahr0::R](R) reader structure"]
impl crate::Readable for MACAHR0_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [macahr0::W](W) writer structure"]
impl crate::Writable for MACAHR0_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MACAHR0 to value 0x8000_ffff"]
impl crate::Resettable for MACAHR0_SPEC {
const RESET_VALUE: Self::Ux = 0x8000_ffff;
}
}
#[doc = "MACALR0 (rw) register accessor: an alias for `Reg<MACALR0_SPEC>`"]
pub type MACALR0 = crate::Reg<macalr0::MACALR0_SPEC>;
#[doc = "MAC Filter Address Low Register 0"]
pub mod macalr0 {
#[doc = "Register `MACALR0` reader"]
pub struct R(crate::R<MACALR0_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MACALR0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MACALR0_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MACALR0_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MACALR0` writer"]
pub struct W(crate::W<MACALR0_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MACALR0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MACALR0_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MACALR0_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MACADDL` reader - "]
pub type MACADDL_R = crate::FieldReader<u32, u32>;
#[doc = "Field `MACADDL` writer - "]
pub type MACADDL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, MACALR0_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn macaddl(&self) -> MACADDL_R {
MACADDL_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn macaddl(&mut self) -> MACADDL_W<0> {
MACADDL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MAC Filter Address Low Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [macalr0](index.html) module"]
pub struct MACALR0_SPEC;
impl crate::RegisterSpec for MACALR0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [macalr0::R](R) reader structure"]
impl crate::Readable for MACALR0_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [macalr0::W](W) writer structure"]
impl crate::Writable for MACALR0_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MACALR0 to value 0xffff_ffff"]
impl crate::Resettable for MACALR0_SPEC {
const RESET_VALUE: Self::Ux = 0xffff_ffff;
}
}
pub use macahr0 as macahr1;
pub use macahr0 as macahr2;
pub use macahr0 as macahr3;
pub use macahr0 as macahr4;
pub use macahr0 as macahr5;
pub use macalr0 as macalr1;
pub use macalr0 as macalr2;
pub use macalr0 as macalr3;
pub use macalr0 as macalr4;
pub use macalr0 as macalr5;
pub use MACAHR0 as MACAHR1;
pub use MACAHR0 as MACAHR2;
pub use MACAHR0 as MACAHR3;
pub use MACAHR0 as MACAHR4;
pub use MACAHR0 as MACAHR5;
pub use MACALR0 as MACALR1;
pub use MACALR0 as MACALR2;
pub use MACALR0 as MACALR3;
pub use MACALR0 as MACALR4;
pub use MACALR0 as MACALR5;
#[doc = "MACHTHR (rw) register accessor: an alias for `Reg<MACHTHR_SPEC>`"]
pub type MACHTHR = crate::Reg<machthr::MACHTHR_SPEC>;
#[doc = "MAC HASH table high register"]
pub mod machthr {
#[doc = "Register `MACHTHR` reader"]
pub struct R(crate::R<MACHTHR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MACHTHR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MACHTHR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MACHTHR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MACHTHR` writer"]
pub struct W(crate::W<MACHTHR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MACHTHR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MACHTHR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MACHTHR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MACHTABH` reader - "]
pub type MACHTABH_R = crate::FieldReader<u32, u32>;
#[doc = "Field `MACHTABH` writer - "]
pub type MACHTABH_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, MACHTHR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn machtabh(&self) -> MACHTABH_R {
MACHTABH_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn machtabh(&mut self) -> MACHTABH_W<0> {
MACHTABH_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MAC HASH table high register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [machthr](index.html) module"]
pub struct MACHTHR_SPEC;
impl crate::RegisterSpec for MACHTHR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [machthr::R](R) reader structure"]
impl crate::Readable for MACHTHR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [machthr::W](W) writer structure"]
impl crate::Writable for MACHTHR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MACHTHR to value 0"]
impl crate::Resettable for MACHTHR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MACHTLR (rw) register accessor: an alias for `Reg<MACHTLR_SPEC>`"]
pub type MACHTLR = crate::Reg<machtlr::MACHTLR_SPEC>;
#[doc = "MAC HASH table low register"]
pub mod machtlr {
#[doc = "Register `MACHTLR` reader"]
pub struct R(crate::R<MACHTLR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MACHTLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MACHTLR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MACHTLR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MACHTLR` writer"]
pub struct W(crate::W<MACHTLR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MACHTLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MACHTLR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MACHTLR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MACHTABL` reader - "]
pub type MACHTABL_R = crate::FieldReader<u32, u32>;
#[doc = "Field `MACHTABL` writer - "]
pub type MACHTABL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, MACHTLR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn machtabl(&self) -> MACHTABL_R {
MACHTABL_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn machtabl(&mut self) -> MACHTABL_W<0> {
MACHTABL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MAC HASH table low register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [machtlr](index.html) module"]
pub struct MACHTLR_SPEC;
impl crate::RegisterSpec for MACHTLR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [machtlr::R](R) reader structure"]
impl crate::Readable for MACHTLR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [machtlr::W](W) writer structure"]
impl crate::Writable for MACHTLR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MACHTLR to value 0"]
impl crate::Resettable for MACHTLR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MACVLTTR (rw) register accessor: an alias for `Reg<MACVLTTR_SPEC>`"]
pub type MACVLTTR = crate::Reg<macvlttr::MACVLTTR_SPEC>;
#[doc = "MAC VLAN TAG send register"]
pub mod macvlttr {
#[doc = "Register `MACVLTTR` reader"]
pub struct R(crate::R<MACVLTTR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MACVLTTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MACVLTTR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MACVLTTR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MACVLTTR` writer"]
pub struct W(crate::W<MACVLTTR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MACVLTTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MACVLTTR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MACVLTTR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `VLANV` reader - "]
pub type VLANV_R = crate::FieldReader<u16, u16>;
#[doc = "Field `VLANV` writer - "]
pub type VLANV_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, MACVLTTR_SPEC, u16, u16, 16, O>;
#[doc = "Field `VLANC` reader - "]
pub type VLANC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `VLANC` writer - "]
pub type VLANC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, MACVLTTR_SPEC, u8, u8, 2, O>;
#[doc = "Field `VLANS` reader - "]
pub type VLANS_R = crate::BitReader<bool>;
#[doc = "Field `VLANS` writer - "]
pub type VLANS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACVLTTR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn vlanv(&self) -> VLANV_R {
VLANV_R::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:17"]
#[inline(always)]
pub fn vlanc(&self) -> VLANC_R {
VLANC_R::new(((self.bits >> 16) & 3) as u8)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn vlans(&self) -> VLANS_R {
VLANS_R::new(((self.bits >> 18) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn vlanv(&mut self) -> VLANV_W<0> {
VLANV_W::new(self)
}
#[doc = "Bits 16:17"]
#[inline(always)]
#[must_use]
pub fn vlanc(&mut self) -> VLANC_W<16> {
VLANC_W::new(self)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn vlans(&mut self) -> VLANS_W<18> {
VLANS_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MAC VLAN TAG send register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [macvlttr](index.html) module"]
pub struct MACVLTTR_SPEC;
impl crate::RegisterSpec for MACVLTTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [macvlttr::R](R) reader structure"]
impl crate::Readable for MACVLTTR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [macvlttr::W](W) writer structure"]
impl crate::Writable for MACVLTTR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MACVLTTR to value 0"]
impl crate::Resettable for MACVLTTR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MACVLTRR (rw) register accessor: an alias for `Reg<MACVLTRR_SPEC>`"]
pub type MACVLTRR = crate::Reg<macvltrr::MACVLTRR_SPEC>;
#[doc = "MAC VLAN TAG Receive Register"]
pub mod macvltrr {
#[doc = "Register `MACVLTRR` reader"]
pub struct R(crate::R<MACVLTRR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MACVLTRR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MACVLTRR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MACVLTRR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MACVLTRR` writer"]
pub struct W(crate::W<MACVLTRR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MACVLTRR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MACVLTRR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MACVLTRR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `VLFLT` reader - "]
pub type VLFLT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `VLFLT` writer - "]
pub type VLFLT_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, MACVLTRR_SPEC, u16, u16, 16, O>;
#[doc = "Field `VTSEL` reader - "]
pub type VTSEL_R = crate::BitReader<bool>;
#[doc = "Field `VTSEL` writer - "]
pub type VTSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACVLTRR_SPEC, bool, O>;
#[doc = "Field `VTIM` reader - "]
pub type VTIM_R = crate::BitReader<bool>;
#[doc = "Field `VTIM` writer - "]
pub type VTIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACVLTRR_SPEC, bool, O>;
#[doc = "Field `VTHM` reader - "]
pub type VTHM_R = crate::BitReader<bool>;
#[doc = "Field `VTHM` writer - "]
pub type VTHM_W<'a, const O: u8> = crate::BitWriter<'a, u32, MACVLTRR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn vlflt(&self) -> VLFLT_R {
VLFLT_R::new((self.bits & 0xffff) as u16)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn vtsel(&self) -> VTSEL_R {
VTSEL_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn vtim(&self) -> VTIM_R {
VTIM_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn vthm(&self) -> VTHM_R {
VTHM_R::new(((self.bits >> 19) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn vlflt(&mut self) -> VLFLT_W<0> {
VLFLT_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn vtsel(&mut self) -> VTSEL_W<16> {
VTSEL_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn vtim(&mut self) -> VTIM_W<17> {
VTIM_W::new(self)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn vthm(&mut self) -> VTHM_W<19> {
VTHM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MAC VLAN TAG Receive Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [macvltrr](index.html) module"]
pub struct MACVLTRR_SPEC;
impl crate::RegisterSpec for MACVLTRR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [macvltrr::R](R) reader structure"]
impl crate::Readable for MACVLTRR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [macvltrr::W](W) writer structure"]
impl crate::Writable for MACVLTRR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MACVLTRR to value 0"]
impl crate::Resettable for MACVLTRR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MACVLHTR (rw) register accessor: an alias for `Reg<MACVLHTR_SPEC>`"]
pub type MACVLHTR = crate::Reg<macvlhtr::MACVLHTR_SPEC>;
#[doc = "MAC VLAN HASH Table Register"]
pub mod macvlhtr {
#[doc = "Register `MACVLHTR` reader"]
pub struct R(crate::R<MACVLHTR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MACVLHTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MACVLHTR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MACVLHTR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MACVLHTR` writer"]
pub struct W(crate::W<MACVLHTR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MACVLHTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MACVLHTR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MACVLHTR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `VLHTAB` reader - "]
pub type VLHTAB_R = crate::FieldReader<u16, u16>;
#[doc = "Field `VLHTAB` writer - "]
pub type VLHTAB_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, MACVLHTR_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn vlhtab(&self) -> VLHTAB_R {
VLHTAB_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn vlhtab(&mut self) -> VLHTAB_W<0> {
VLHTAB_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MAC VLAN HASH Table Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [macvlhtr](index.html) module"]
pub struct MACVLHTR_SPEC;
impl crate::RegisterSpec for MACVLHTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [macvlhtr::R](R) reader structure"]
impl crate::Readable for MACVLHTR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [macvlhtr::W](W) writer structure"]
impl crate::Writable for MACVLHTR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MACVLHTR to value 0"]
impl crate::Resettable for MACVLHTR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMAMDR (rw) register accessor: an alias for `Reg<DMAMDR_SPEC>`"]
pub type DMAMDR = crate::Reg<dmamdr::DMAMDR_SPEC>;
#[doc = "DMA work mode register"]
pub mod dmamdr {
#[doc = "Register `DMAMDR` reader"]
pub struct R(crate::R<DMAMDR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMAMDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMAMDR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMAMDR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DMAMDR` writer"]
pub struct W(crate::W<DMAMDR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DMAMDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DMAMDR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DMAMDR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `STR` reader - "]
pub type STR_R = crate::BitReader<bool>;
#[doc = "Field `STR` writer - "]
pub type STR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAMDR_SPEC, bool, O>;
#[doc = "Field `OSF` reader - "]
pub type OSF_R = crate::BitReader<bool>;
#[doc = "Field `OSF` writer - "]
pub type OSF_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAMDR_SPEC, bool, O>;
#[doc = "Field `RTC` reader - "]
pub type RTC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `RTC` writer - "]
pub type RTC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMAMDR_SPEC, u8, u8, 2, O>;
#[doc = "Field `DGF` reader - "]
pub type DGF_R = crate::BitReader<bool>;
#[doc = "Field `DGF` writer - "]
pub type DGF_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAMDR_SPEC, bool, O>;
#[doc = "Field `FUF` reader - "]
pub type FUF_R = crate::BitReader<bool>;
#[doc = "Field `FUF` writer - "]
pub type FUF_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAMDR_SPEC, bool, O>;
#[doc = "Field `FEF` reader - "]
pub type FEF_R = crate::BitReader<bool>;
#[doc = "Field `FEF` writer - "]
pub type FEF_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAMDR_SPEC, bool, O>;
#[doc = "Field `STT` reader - "]
pub type STT_R = crate::BitReader<bool>;
#[doc = "Field `STT` writer - "]
pub type STT_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAMDR_SPEC, bool, O>;
#[doc = "Field `TTC` reader - "]
pub type TTC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TTC` writer - "]
pub type TTC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMAMDR_SPEC, u8, u8, 3, O>;
#[doc = "Field `FTF` reader - "]
pub type FTF_R = crate::BitReader<bool>;
#[doc = "Field `FTF` writer - "]
pub type FTF_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAMDR_SPEC, bool, O>;
#[doc = "Field `TSF` reader - "]
pub type TSF_R = crate::BitReader<bool>;
#[doc = "Field `TSF` writer - "]
pub type TSF_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAMDR_SPEC, bool, O>;
#[doc = "Field `DFRF` reader - "]
pub type DFRF_R = crate::BitReader<bool>;
#[doc = "Field `DFRF` writer - "]
pub type DFRF_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAMDR_SPEC, bool, O>;
#[doc = "Field `RSF` reader - "]
pub type RSF_R = crate::BitReader<bool>;
#[doc = "Field `RSF` writer - "]
pub type RSF_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAMDR_SPEC, bool, O>;
#[doc = "Field `DTCOE` reader - "]
pub type DTCOE_R = crate::BitReader<bool>;
#[doc = "Field `DTCOE` writer - "]
pub type DTCOE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAMDR_SPEC, bool, O>;
impl R {
#[doc = "Bit 1"]
#[inline(always)]
pub fn str(&self) -> STR_R {
STR_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn osf(&self) -> OSF_R {
OSF_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 3:4"]
#[inline(always)]
pub fn rtc(&self) -> RTC_R {
RTC_R::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn dgf(&self) -> DGF_R {
DGF_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn fuf(&self) -> FUF_R {
FUF_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn fef(&self) -> FEF_R {
FEF_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn stt(&self) -> STT_R {
STT_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bits 14:16"]
#[inline(always)]
pub fn ttc(&self) -> TTC_R {
TTC_R::new(((self.bits >> 14) & 7) as u8)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn ftf(&self) -> FTF_R {
FTF_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn tsf(&self) -> TSF_R {
TSF_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn dfrf(&self) -> DFRF_R {
DFRF_R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn rsf(&self) -> RSF_R {
RSF_R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26"]
#[inline(always)]
pub fn dtcoe(&self) -> DTCOE_R {
DTCOE_R::new(((self.bits >> 26) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn str(&mut self) -> STR_W<1> {
STR_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn osf(&mut self) -> OSF_W<2> {
OSF_W::new(self)
}
#[doc = "Bits 3:4"]
#[inline(always)]
#[must_use]
pub fn rtc(&mut self) -> RTC_W<3> {
RTC_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn dgf(&mut self) -> DGF_W<5> {
DGF_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn fuf(&mut self) -> FUF_W<6> {
FUF_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn fef(&mut self) -> FEF_W<7> {
FEF_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn stt(&mut self) -> STT_W<13> {
STT_W::new(self)
}
#[doc = "Bits 14:16"]
#[inline(always)]
#[must_use]
pub fn ttc(&mut self) -> TTC_W<14> {
TTC_W::new(self)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn ftf(&mut self) -> FTF_W<20> {
FTF_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn tsf(&mut self) -> TSF_W<21> {
TSF_W::new(self)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn dfrf(&mut self) -> DFRF_W<24> {
DFRF_W::new(self)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn rsf(&mut self) -> RSF_W<25> {
RSF_W::new(self)
}
#[doc = "Bit 26"]
#[inline(always)]
#[must_use]
pub fn dtcoe(&mut self) -> DTCOE_W<26> {
DTCOE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA work mode register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmamdr](index.html) module"]
pub struct DMAMDR_SPEC;
impl crate::RegisterSpec for DMAMDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dmamdr::R](R) reader structure"]
impl crate::Readable for DMAMDR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dmamdr::W](W) writer structure"]
impl crate::Writable for DMAMDR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DMAMDR to value 0"]
impl crate::Resettable for DMAMDR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMABSR (rw) register accessor: an alias for `Reg<DMABSR_SPEC>`"]
pub type DMABSR = crate::Reg<dmabsr::DMABSR_SPEC>;
#[doc = "DMA bus control register"]
pub mod dmabsr {
#[doc = "Register `DMABSR` reader"]
pub struct R(crate::R<DMABSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMABSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMABSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMABSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DMABSR` writer"]
pub struct W(crate::W<DMABSR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DMABSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DMABSR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DMABSR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SR` reader - "]
pub type SR_R = crate::BitReader<bool>;
#[doc = "Field `SR` writer - "]
pub type SR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMABSR_SPEC, bool, O>;
#[doc = "Field `DMAA` reader - "]
pub type DMAA_R = crate::BitReader<bool>;
#[doc = "Field `DMAA` writer - "]
pub type DMAA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMABSR_SPEC, bool, O>;
#[doc = "Field `DSL` reader - "]
pub type DSL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DSL` writer - "]
pub type DSL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMABSR_SPEC, u8, u8, 5, O>;
#[doc = "Field `DSEN` reader - "]
pub type DSEN_R = crate::BitReader<bool>;
#[doc = "Field `DSEN` writer - "]
pub type DSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMABSR_SPEC, bool, O>;
#[doc = "Field `TPBL` reader - "]
pub type TPBL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TPBL` writer - "]
pub type TPBL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMABSR_SPEC, u8, u8, 6, O>;
#[doc = "Field `FTPR` reader - "]
pub type FTPR_R = crate::FieldReader<u8, u8>;
#[doc = "Field `FTPR` writer - "]
pub type FTPR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMABSR_SPEC, u8, u8, 2, O>;
#[doc = "Field `FBST` reader - "]
pub type FBST_R = crate::BitReader<bool>;
#[doc = "Field `FBST` writer - "]
pub type FBST_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMABSR_SPEC, bool, O>;
#[doc = "Field `RPBL` reader - "]
pub type RPBL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `RPBL` writer - "]
pub type RPBL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMABSR_SPEC, u8, u8, 6, O>;
#[doc = "Field `SPBL` reader - "]
pub type SPBL_R = crate::BitReader<bool>;
#[doc = "Field `SPBL` writer - "]
pub type SPBL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMABSR_SPEC, bool, O>;
#[doc = "Field `MPBL` reader - "]
pub type MPBL_R = crate::BitReader<bool>;
#[doc = "Field `MPBL` writer - "]
pub type MPBL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMABSR_SPEC, bool, O>;
#[doc = "Field `AAL` reader - "]
pub type AAL_R = crate::BitReader<bool>;
#[doc = "Field `AAL` writer - "]
pub type AAL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMABSR_SPEC, bool, O>;
#[doc = "Field `MBST` reader - "]
pub type MBST_R = crate::BitReader<bool>;
#[doc = "Field `MBST` writer - "]
pub type MBST_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMABSR_SPEC, bool, O>;
#[doc = "Field `TXPR` reader - "]
pub type TXPR_R = crate::BitReader<bool>;
#[doc = "Field `TXPR` writer - "]
pub type TXPR_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMABSR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn sr(&self) -> SR_R {
SR_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn dmaa(&self) -> DMAA_R {
DMAA_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:6"]
#[inline(always)]
pub fn dsl(&self) -> DSL_R {
DSL_R::new(((self.bits >> 2) & 0x1f) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn dsen(&self) -> DSEN_R {
DSEN_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:13"]
#[inline(always)]
pub fn tpbl(&self) -> TPBL_R {
TPBL_R::new(((self.bits >> 8) & 0x3f) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn ftpr(&self) -> FTPR_R {
FTPR_R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn fbst(&self) -> FBST_R {
FBST_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 17:22"]
#[inline(always)]
pub fn rpbl(&self) -> RPBL_R {
RPBL_R::new(((self.bits >> 17) & 0x3f) as u8)
}
#[doc = "Bit 23"]
#[inline(always)]
pub fn spbl(&self) -> SPBL_R {
SPBL_R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn mpbl(&self) -> MPBL_R {
MPBL_R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn aal(&self) -> AAL_R {
AAL_R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26"]
#[inline(always)]
pub fn mbst(&self) -> MBST_R {
MBST_R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27"]
#[inline(always)]
pub fn txpr(&self) -> TXPR_R {
TXPR_R::new(((self.bits >> 27) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn sr(&mut self) -> SR_W<0> {
SR_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn dmaa(&mut self) -> DMAA_W<1> {
DMAA_W::new(self)
}
#[doc = "Bits 2:6"]
#[inline(always)]
#[must_use]
pub fn dsl(&mut self) -> DSL_W<2> {
DSL_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn dsen(&mut self) -> DSEN_W<7> {
DSEN_W::new(self)
}
#[doc = "Bits 8:13"]
#[inline(always)]
#[must_use]
pub fn tpbl(&mut self) -> TPBL_W<8> {
TPBL_W::new(self)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn ftpr(&mut self) -> FTPR_W<14> {
FTPR_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn fbst(&mut self) -> FBST_W<16> {
FBST_W::new(self)
}
#[doc = "Bits 17:22"]
#[inline(always)]
#[must_use]
pub fn rpbl(&mut self) -> RPBL_W<17> {
RPBL_W::new(self)
}
#[doc = "Bit 23"]
#[inline(always)]
#[must_use]
pub fn spbl(&mut self) -> SPBL_W<23> {
SPBL_W::new(self)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn mpbl(&mut self) -> MPBL_W<24> {
MPBL_W::new(self)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn aal(&mut self) -> AAL_W<25> {
AAL_W::new(self)
}
#[doc = "Bit 26"]
#[inline(always)]
#[must_use]
pub fn mbst(&mut self) -> MBST_W<26> {
MBST_W::new(self)
}
#[doc = "Bit 27"]
#[inline(always)]
#[must_use]
pub fn txpr(&mut self) -> TXPR_W<27> {
TXPR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA bus control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmabsr](index.html) module"]
pub struct DMABSR_SPEC;
impl crate::RegisterSpec for DMABSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dmabsr::R](R) reader structure"]
impl crate::Readable for DMABSR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dmabsr::W](W) writer structure"]
impl crate::Writable for DMABSR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DMABSR to value 0x0002_0101"]
impl crate::Resettable for DMABSR_SPEC {
const RESET_VALUE: Self::Ux = 0x0002_0101;
}
}
#[doc = "DMASR (r) register accessor: an alias for `Reg<DMASR_SPEC>`"]
pub type DMASR = crate::Reg<dmasr::DMASR_SPEC>;
#[doc = "DMA status register"]
pub mod dmasr {
#[doc = "Register `DMASR` reader"]
pub struct R(crate::R<DMASR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMASR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMASR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMASR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `TCS` reader - "]
pub type TCS_R = crate::BitReader<bool>;
#[doc = "Field `TSS` reader - "]
pub type TSS_R = crate::BitReader<bool>;
#[doc = "Field `TUS` reader - "]
pub type TUS_R = crate::BitReader<bool>;
#[doc = "Field `TJS` reader - "]
pub type TJS_R = crate::BitReader<bool>;
#[doc = "Field `OVS` reader - "]
pub type OVS_R = crate::BitReader<bool>;
#[doc = "Field `UNS` reader - "]
pub type UNS_R = crate::BitReader<bool>;
#[doc = "Field `RCS` reader - "]
pub type RCS_R = crate::BitReader<bool>;
#[doc = "Field `RUS` reader - "]
pub type RUS_R = crate::BitReader<bool>;
#[doc = "Field `RSS` reader - "]
pub type RSS_R = crate::BitReader<bool>;
#[doc = "Field `RWS` reader - "]
pub type RWS_R = crate::BitReader<bool>;
#[doc = "Field `ETS` reader - "]
pub type ETS_R = crate::BitReader<bool>;
#[doc = "Field `FBS` reader - "]
pub type FBS_R = crate::BitReader<bool>;
#[doc = "Field `ERS` reader - "]
pub type ERS_R = crate::BitReader<bool>;
#[doc = "Field `AIS` reader - "]
pub type AIS_R = crate::BitReader<bool>;
#[doc = "Field `NIS` reader - "]
pub type NIS_R = crate::BitReader<bool>;
#[doc = "Field `RPS` reader - "]
pub type RPS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TPS` reader - "]
pub type TPS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EBUS` reader - "]
pub type EBUS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MMCS` reader - "]
pub type MMCS_R = crate::BitReader<bool>;
#[doc = "Field `PMTS` reader - "]
pub type PMTS_R = crate::BitReader<bool>;
#[doc = "Field `PTPS` reader - "]
pub type PTPS_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn tcs(&self) -> TCS_R {
TCS_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn tss(&self) -> TSS_R {
TSS_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn tus(&self) -> TUS_R {
TUS_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn tjs(&self) -> TJS_R {
TJS_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn ovs(&self) -> OVS_R {
OVS_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn uns(&self) -> UNS_R {
UNS_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn rcs(&self) -> RCS_R {
RCS_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn rus(&self) -> RUS_R {
RUS_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rss(&self) -> RSS_R {
RSS_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn rws(&self) -> RWS_R {
RWS_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn ets(&self) -> ETS_R {
ETS_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn fbs(&self) -> FBS_R {
FBS_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn ers(&self) -> ERS_R {
ERS_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn ais(&self) -> AIS_R {
AIS_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn nis(&self) -> NIS_R {
NIS_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 17:19"]
#[inline(always)]
pub fn rps(&self) -> RPS_R {
RPS_R::new(((self.bits >> 17) & 7) as u8)
}
#[doc = "Bits 20:22"]
#[inline(always)]
pub fn tps(&self) -> TPS_R {
TPS_R::new(((self.bits >> 20) & 7) as u8)
}
#[doc = "Bits 23:25"]
#[inline(always)]
pub fn ebus(&self) -> EBUS_R {
EBUS_R::new(((self.bits >> 23) & 7) as u8)
}
#[doc = "Bit 27"]
#[inline(always)]
pub fn mmcs(&self) -> MMCS_R {
MMCS_R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn pmts(&self) -> PMTS_R {
PMTS_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29"]
#[inline(always)]
pub fn ptps(&self) -> PTPS_R {
PTPS_R::new(((self.bits >> 29) & 1) != 0)
}
}
#[doc = "DMA status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmasr](index.html) module"]
pub struct DMASR_SPEC;
impl crate::RegisterSpec for DMASR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dmasr::R](R) reader structure"]
impl crate::Readable for DMASR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets DMASR to value 0"]
impl crate::Resettable for DMASR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMAIR (rw) register accessor: an alias for `Reg<DMAIR_SPEC>`"]
pub type DMAIR = crate::Reg<dmair::DMAIR_SPEC>;
#[doc = "DMA Interrupt Register"]
pub mod dmair {
#[doc = "Register `DMAIR` reader"]
pub struct R(crate::R<DMAIR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMAIR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMAIR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMAIR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DMAIR` writer"]
pub struct W(crate::W<DMAIR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DMAIR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DMAIR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DMAIR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TCE` reader - "]
pub type TCE_R = crate::BitReader<bool>;
#[doc = "Field `TCE` writer - "]
pub type TCE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAIR_SPEC, bool, O>;
#[doc = "Field `TSE` reader - "]
pub type TSE_R = crate::BitReader<bool>;
#[doc = "Field `TSE` writer - "]
pub type TSE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAIR_SPEC, bool, O>;
#[doc = "Field `TUE` reader - "]
pub type TUE_R = crate::BitReader<bool>;
#[doc = "Field `TUE` writer - "]
pub type TUE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAIR_SPEC, bool, O>;
#[doc = "Field `TJE` reader - "]
pub type TJE_R = crate::BitReader<bool>;
#[doc = "Field `TJE` writer - "]
pub type TJE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAIR_SPEC, bool, O>;
#[doc = "Field `OVE` reader - "]
pub type OVE_R = crate::BitReader<bool>;
#[doc = "Field `OVE` writer - "]
pub type OVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAIR_SPEC, bool, O>;
#[doc = "Field `UNE` reader - "]
pub type UNE_R = crate::BitReader<bool>;
#[doc = "Field `UNE` writer - "]
pub type UNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAIR_SPEC, bool, O>;
#[doc = "Field `RCE` reader - "]
pub type RCE_R = crate::BitReader<bool>;
#[doc = "Field `RCE` writer - "]
pub type RCE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAIR_SPEC, bool, O>;
#[doc = "Field `RUE` reader - "]
pub type RUE_R = crate::BitReader<bool>;
#[doc = "Field `RUE` writer - "]
pub type RUE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAIR_SPEC, bool, O>;
#[doc = "Field `RSE` reader - "]
pub type RSE_R = crate::BitReader<bool>;
#[doc = "Field `RSE` writer - "]
pub type RSE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAIR_SPEC, bool, O>;
#[doc = "Field `RWE` reader - "]
pub type RWE_R = crate::BitReader<bool>;
#[doc = "Field `RWE` writer - "]
pub type RWE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAIR_SPEC, bool, O>;
#[doc = "Field `ETE` reader - "]
pub type ETE_R = crate::BitReader<bool>;
#[doc = "Field `ETE` writer - "]
pub type ETE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAIR_SPEC, bool, O>;
#[doc = "Field `FBE` reader - "]
pub type FBE_R = crate::BitReader<bool>;
#[doc = "Field `FBE` writer - "]
pub type FBE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAIR_SPEC, bool, O>;
#[doc = "Field `ERE` reader - "]
pub type ERE_R = crate::BitReader<bool>;
#[doc = "Field `ERE` writer - "]
pub type ERE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAIR_SPEC, bool, O>;
#[doc = "Field `AIE` reader - "]
pub type AIE_R = crate::BitReader<bool>;
#[doc = "Field `AIE` writer - "]
pub type AIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAIR_SPEC, bool, O>;
#[doc = "Field `NIE` reader - "]
pub type NIE_R = crate::BitReader<bool>;
#[doc = "Field `NIE` writer - "]
pub type NIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMAIR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn tce(&self) -> TCE_R {
TCE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn tse(&self) -> TSE_R {
TSE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn tue(&self) -> TUE_R {
TUE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn tje(&self) -> TJE_R {
TJE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn ove(&self) -> OVE_R {
OVE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn une(&self) -> UNE_R {
UNE_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn rce(&self) -> RCE_R {
RCE_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn rue(&self) -> RUE_R {
RUE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rse(&self) -> RSE_R {
RSE_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn rwe(&self) -> RWE_R {
RWE_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn ete(&self) -> ETE_R {
ETE_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn fbe(&self) -> FBE_R {
FBE_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn ere(&self) -> ERE_R {
ERE_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn aie(&self) -> AIE_R {
AIE_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn nie(&self) -> NIE_R {
NIE_R::new(((self.bits >> 16) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn tce(&mut self) -> TCE_W<0> {
TCE_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn tse(&mut self) -> TSE_W<1> {
TSE_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn tue(&mut self) -> TUE_W<2> {
TUE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn tje(&mut self) -> TJE_W<3> {
TJE_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn ove(&mut self) -> OVE_W<4> {
OVE_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn une(&mut self) -> UNE_W<5> {
UNE_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn rce(&mut self) -> RCE_W<6> {
RCE_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn rue(&mut self) -> RUE_W<7> {
RUE_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rse(&mut self) -> RSE_W<8> {
RSE_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn rwe(&mut self) -> RWE_W<9> {
RWE_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn ete(&mut self) -> ETE_W<10> {
ETE_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn fbe(&mut self) -> FBE_W<13> {
FBE_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn ere(&mut self) -> ERE_W<14> {
ERE_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn aie(&mut self) -> AIE_W<15> {
AIE_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn nie(&mut self) -> NIE_W<16> {
NIE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmair](index.html) module"]
pub struct DMAIR_SPEC;
impl crate::RegisterSpec for DMAIR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dmair::R](R) reader structure"]
impl crate::Readable for DMAIR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dmair::W](W) writer structure"]
impl crate::Writable for DMAIR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DMAIR to value 0"]
impl crate::Resettable for DMAIR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMAFLCR (r) register accessor: an alias for `Reg<DMAFLCR_SPEC>`"]
pub type DMAFLCR = crate::Reg<dmaflcr::DMAFLCR_SPEC>;
#[doc = "DMA Frame Loss Statistics Register"]
pub mod dmaflcr {
#[doc = "Register `DMAFLCR` reader"]
pub struct R(crate::R<DMAFLCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMAFLCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMAFLCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMAFLCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `BUAC` reader - \n\nThe field is **cleared** (set to zero) following a read operation."]
pub type BUAC_R = crate::FieldReader<u16, u16>;
#[doc = "Field `BUAF` reader - "]
pub type BUAF_R = crate::BitReader<bool>;
#[doc = "Field `OVFC` reader - \n\nThe field is **cleared** (set to zero) following a read operation."]
pub type OVFC_R = crate::FieldReader<u16, u16>;
#[doc = "Field `OVFF` reader - "]
pub type OVFF_R = crate::BitReader<bool>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn buac(&self) -> BUAC_R {
BUAC_R::new((self.bits & 0xffff) as u16)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn buaf(&self) -> BUAF_R {
BUAF_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 17:27"]
#[inline(always)]
pub fn ovfc(&self) -> OVFC_R {
OVFC_R::new(((self.bits >> 17) & 0x07ff) as u16)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn ovff(&self) -> OVFF_R {
OVFF_R::new(((self.bits >> 28) & 1) != 0)
}
}
#[doc = "DMA Frame Loss Statistics Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmaflcr](index.html) module"]
pub struct DMAFLCR_SPEC;
impl crate::RegisterSpec for DMAFLCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dmaflcr::R](R) reader structure"]
impl crate::Readable for DMAFLCR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets DMAFLCR to value 0"]
impl crate::Resettable for DMAFLCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMAWDTR (rw) register accessor: an alias for `Reg<DMAWDTR_SPEC>`"]
pub type DMAWDTR = crate::Reg<dmawdtr::DMAWDTR_SPEC>;
#[doc = "DMA Watchdog Timing Register"]
pub mod dmawdtr {
#[doc = "Register `DMAWDTR` reader"]
pub struct R(crate::R<DMAWDTR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMAWDTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMAWDTR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMAWDTR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DMAWDTR` writer"]
pub struct W(crate::W<DMAWDTR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DMAWDTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DMAWDTR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DMAWDTR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RIWT` reader - "]
pub type RIWT_R = crate::FieldReader<u32, u32>;
#[doc = "Field `RIWT` writer - "]
pub type RIWT_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DMAWDTR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn riwt(&self) -> RIWT_R {
RIWT_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn riwt(&mut self) -> RIWT_W<0> {
RIWT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA Watchdog Timing Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmawdtr](index.html) module"]
pub struct DMAWDTR_SPEC;
impl crate::RegisterSpec for DMAWDTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dmawdtr::R](R) reader structure"]
impl crate::Readable for DMAWDTR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dmawdtr::W](W) writer structure"]
impl crate::Writable for DMAWDTR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DMAWDTR to value 0"]
impl crate::Resettable for DMAWDTR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMARXPDR (rw) register accessor: an alias for `Reg<DMARXPDR_SPEC>`"]
pub type DMARXPDR = crate::Reg<dmarxpdr::DMARXPDR_SPEC>;
#[doc = "DMA Receive Polling Register"]
pub mod dmarxpdr {
#[doc = "Register `DMARXPDR` reader"]
pub struct R(crate::R<DMARXPDR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMARXPDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMARXPDR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMARXPDR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DMARXPDR` writer"]
pub struct W(crate::W<DMARXPDR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DMARXPDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DMARXPDR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DMARXPDR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RXPD` reader - "]
pub type RXPD_R = crate::FieldReader<u32, u32>;
#[doc = "Field `RXPD` writer - "]
pub type RXPD_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DMARXPDR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rxpd(&self) -> RXPD_R {
RXPD_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rxpd(&mut self) -> RXPD_W<0> {
RXPD_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA Receive Polling Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmarxpdr](index.html) module"]
pub struct DMARXPDR_SPEC;
impl crate::RegisterSpec for DMARXPDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dmarxpdr::R](R) reader structure"]
impl crate::Readable for DMARXPDR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dmarxpdr::W](W) writer structure"]
impl crate::Writable for DMARXPDR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DMARXPDR to value 0"]
impl crate::Resettable for DMARXPDR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMATXPDR (rw) register accessor: an alias for `Reg<DMATXPDR_SPEC>`"]
pub type DMATXPDR = crate::Reg<dmatxpdr::DMATXPDR_SPEC>;
#[doc = "DMA transmit polling register"]
pub mod dmatxpdr {
#[doc = "Register `DMATXPDR` reader"]
pub struct R(crate::R<DMATXPDR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMATXPDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMATXPDR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMATXPDR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DMATXPDR` writer"]
pub struct W(crate::W<DMATXPDR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DMATXPDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DMATXPDR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DMATXPDR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TXPD` reader - "]
pub type TXPD_R = crate::FieldReader<u32, u32>;
#[doc = "Field `TXPD` writer - "]
pub type TXPD_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DMATXPDR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn txpd(&self) -> TXPD_R {
TXPD_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn txpd(&mut self) -> TXPD_W<0> {
TXPD_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA transmit polling register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmatxpdr](index.html) module"]
pub struct DMATXPDR_SPEC;
impl crate::RegisterSpec for DMATXPDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dmatxpdr::R](R) reader structure"]
impl crate::Readable for DMATXPDR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dmatxpdr::W](W) writer structure"]
impl crate::Writable for DMATXPDR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DMATXPDR to value 0"]
impl crate::Resettable for DMATXPDR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMARXDSAR (rw) register accessor: an alias for `Reg<DMARXDSAR_SPEC>`"]
pub type DMARXDSAR = crate::Reg<dmarxdsar::DMARXDSAR_SPEC>;
#[doc = "DMA Receive Descriptor Address Register"]
pub mod dmarxdsar {
#[doc = "Register `DMARXDSAR` reader"]
pub struct R(crate::R<DMARXDSAR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMARXDSAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMARXDSAR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMARXDSAR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DMARXDSAR` writer"]
pub struct W(crate::W<DMARXDSAR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DMARXDSAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DMARXDSAR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DMARXDSAR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RXDSA` reader - "]
pub type RXDSA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `RXDSA` writer - "]
pub type RXDSA_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DMARXDSAR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rxdsa(&self) -> RXDSA_R {
RXDSA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rxdsa(&mut self) -> RXDSA_W<0> {
RXDSA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA Receive Descriptor Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmarxdsar](index.html) module"]
pub struct DMARXDSAR_SPEC;
impl crate::RegisterSpec for DMARXDSAR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dmarxdsar::R](R) reader structure"]
impl crate::Readable for DMARXDSAR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dmarxdsar::W](W) writer structure"]
impl crate::Writable for DMARXDSAR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DMARXDSAR to value 0"]
impl crate::Resettable for DMARXDSAR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMATXDSAR (rw) register accessor: an alias for `Reg<DMATXDSAR_SPEC>`"]
pub type DMATXDSAR = crate::Reg<dmatxdsar::DMATXDSAR_SPEC>;
#[doc = "DMA transmit descriptor address register"]
pub mod dmatxdsar {
#[doc = "Register `DMATXDSAR` reader"]
pub struct R(crate::R<DMATXDSAR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMATXDSAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMATXDSAR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMATXDSAR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DMATXDSAR` writer"]
pub struct W(crate::W<DMATXDSAR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DMATXDSAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DMATXDSAR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DMATXDSAR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TXDSA` reader - "]
pub type TXDSA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `TXDSA` writer - "]
pub type TXDSA_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DMATXDSAR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn txdsa(&self) -> TXDSA_R {
TXDSA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn txdsa(&mut self) -> TXDSA_W<0> {
TXDSA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA transmit descriptor address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmatxdsar](index.html) module"]
pub struct DMATXDSAR_SPEC;
impl crate::RegisterSpec for DMATXDSAR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dmatxdsar::R](R) reader structure"]
impl crate::Readable for DMATXDSAR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dmatxdsar::W](W) writer structure"]
impl crate::Writable for DMATXDSAR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DMATXDSAR to value 0"]
impl crate::Resettable for DMATXDSAR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMACURRXDSAR (r) register accessor: an alias for `Reg<DMACURRXDSAR_SPEC>`"]
pub type DMACURRXDSAR = crate::Reg<dmacurrxdsar::DMACURRXDSAR_SPEC>;
#[doc = "DMA current receive descriptor address register"]
pub mod dmacurrxdsar {
#[doc = "Register `DMACURRXDSAR` reader"]
pub struct R(crate::R<DMACURRXDSAR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMACURRXDSAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMACURRXDSAR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMACURRXDSAR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `CURRXDSA` reader - "]
pub type CURRXDSA_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn currxdsa(&self) -> CURRXDSA_R {
CURRXDSA_R::new(self.bits)
}
}
#[doc = "DMA current receive descriptor address register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacurrxdsar](index.html) module"]
pub struct DMACURRXDSAR_SPEC;
impl crate::RegisterSpec for DMACURRXDSAR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dmacurrxdsar::R](R) reader structure"]
impl crate::Readable for DMACURRXDSAR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets DMACURRXDSAR to value 0"]
impl crate::Resettable for DMACURRXDSAR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMACURTXDSAR (r) register accessor: an alias for `Reg<DMACURTXDSAR_SPEC>`"]
pub type DMACURTXDSAR = crate::Reg<dmacurtxdsar::DMACURTXDSAR_SPEC>;
#[doc = "DMA current transmit descriptor address register"]
pub mod dmacurtxdsar {
#[doc = "Register `DMACURTXDSAR` reader"]
pub struct R(crate::R<DMACURTXDSAR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMACURTXDSAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMACURTXDSAR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMACURTXDSAR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `CURTXDSA` reader - "]
pub type CURTXDSA_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn curtxdsa(&self) -> CURTXDSA_R {
CURTXDSA_R::new(self.bits)
}
}
#[doc = "DMA current transmit descriptor address register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacurtxdsar](index.html) module"]
pub struct DMACURTXDSAR_SPEC;
impl crate::RegisterSpec for DMACURTXDSAR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dmacurtxdsar::R](R) reader structure"]
impl crate::Readable for DMACURTXDSAR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets DMACURTXDSAR to value 0"]
impl crate::Resettable for DMACURTXDSAR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMACURRXBFAR (r) register accessor: an alias for `Reg<DMACURRXBFAR_SPEC>`"]
pub type DMACURRXBFAR = crate::Reg<dmacurrxbfar::DMACURRXBFAR_SPEC>;
#[doc = "DMA current receive buffer address register"]
pub mod dmacurrxbfar {
#[doc = "Register `DMACURRXBFAR` reader"]
pub struct R(crate::R<DMACURRXBFAR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMACURRXBFAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMACURRXBFAR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMACURRXBFAR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `CURRXBFA` reader - "]
pub type CURRXBFA_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn currxbfa(&self) -> CURRXBFA_R {
CURRXBFA_R::new(self.bits)
}
}
#[doc = "DMA current receive buffer address register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacurrxbfar](index.html) module"]
pub struct DMACURRXBFAR_SPEC;
impl crate::RegisterSpec for DMACURRXBFAR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dmacurrxbfar::R](R) reader structure"]
impl crate::Readable for DMACURRXBFAR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets DMACURRXBFAR to value 0"]
impl crate::Resettable for DMACURRXBFAR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMACURTXBFAR (r) register accessor: an alias for `Reg<DMACURTXBFAR_SPEC>`"]
pub type DMACURTXBFAR = crate::Reg<dmacurtxbfar::DMACURTXBFAR_SPEC>;
#[doc = "DMA current send buffer address register"]
pub mod dmacurtxbfar {
#[doc = "Register `DMACURTXBFAR` reader"]
pub struct R(crate::R<DMACURTXBFAR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMACURTXBFAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMACURTXBFAR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMACURTXBFAR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `CURTXBFA` reader - "]
pub type CURTXBFA_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn curtxbfa(&self) -> CURTXBFA_R {
CURTXBFA_R::new(self.bits)
}
}
#[doc = "DMA current send buffer address register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacurtxbfar](index.html) module"]
pub struct DMACURTXBFAR_SPEC;
impl crate::RegisterSpec for DMACURTXBFAR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dmacurtxbfar::R](R) reader structure"]
impl crate::Readable for DMACURTXBFAR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets DMACURTXBFAR to value 0"]
impl crate::Resettable for DMACURTXBFAR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PTPCR (rw) register accessor: an alias for `Reg<PTPCR_SPEC>`"]
pub type PTPCR = crate::Reg<ptpcr::PTPCR_SPEC>;
#[doc = "PTP Control Register"]
pub mod ptpcr {
#[doc = "Register `PTPCR` reader"]
pub struct R(crate::R<PTPCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PTPCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PTPCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PTPCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PTPCR` writer"]
pub struct W(crate::W<PTPCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PTPCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PTPCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PTPCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PTPEN` writer - "]
pub type PTPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PTPCR_SPEC, bool, O>;
#[doc = "Field `PTPCS` reader - "]
pub type PTPCS_R = crate::BitReader<bool>;
#[doc = "Field `PTPCS` writer - "]
pub type PTPCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, PTPCR_SPEC, bool, O>;
#[doc = "Field `PTPINI` reader - "]
pub type PTPINI_R = crate::BitReader<bool>;
#[doc = "Field `PTPINI` writer - "]
pub type PTPINI_W<'a, const O: u8> = crate::BitWriter<'a, u32, PTPCR_SPEC, bool, O>;
#[doc = "Field `PTPUP` reader - "]
pub type PTPUP_R = crate::BitReader<bool>;
#[doc = "Field `PTPUP` writer - "]
pub type PTPUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PTPCR_SPEC, bool, O>;
#[doc = "Field `PTPINT` reader - "]
pub type PTPINT_R = crate::BitReader<bool>;
#[doc = "Field `PTPINT` writer - "]
pub type PTPINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, PTPCR_SPEC, bool, O>;
#[doc = "Field `PTPADUP` reader - "]
pub type PTPADUP_R = crate::BitReader<bool>;
#[doc = "Field `PTPADUP` writer - "]
pub type PTPADUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PTPCR_SPEC, bool, O>;
#[doc = "Field `PTPEALL` reader - "]
pub type PTPEALL_R = crate::BitReader<bool>;
#[doc = "Field `PTPEALL` writer - "]
pub type PTPEALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, PTPCR_SPEC, bool, O>;
#[doc = "Field `PTPNSS` reader - "]
pub type PTPNSS_R = crate::BitReader<bool>;
#[doc = "Field `PTPNSS` writer - "]
pub type PTPNSS_W<'a, const O: u8> = crate::BitWriter<'a, u32, PTPCR_SPEC, bool, O>;
#[doc = "Field `PTPVER` reader - "]
pub type PTPVER_R = crate::BitReader<bool>;
#[doc = "Field `PTPVER` writer - "]
pub type PTPVER_W<'a, const O: u8> = crate::BitWriter<'a, u32, PTPCR_SPEC, bool, O>;
#[doc = "Field `PTPETH` reader - "]
pub type PTPETH_R = crate::BitReader<bool>;
#[doc = "Field `PTPETH` writer - "]
pub type PTPETH_W<'a, const O: u8> = crate::BitWriter<'a, u32, PTPCR_SPEC, bool, O>;
#[doc = "Field `PTPIPV6` reader - "]
pub type PTPIPV6_R = crate::BitReader<bool>;
#[doc = "Field `PTPIPV6` writer - "]
pub type PTPIPV6_W<'a, const O: u8> = crate::BitWriter<'a, u32, PTPCR_SPEC, bool, O>;
#[doc = "Field `PTPIPV4` reader - "]
pub type PTPIPV4_R = crate::BitReader<bool>;
#[doc = "Field `PTPIPV4` writer - "]
pub type PTPIPV4_W<'a, const O: u8> = crate::BitWriter<'a, u32, PTPCR_SPEC, bool, O>;
#[doc = "Field `PTPTYPS` reader - "]
pub type PTPTYPS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PTPTYPS` writer - "]
pub type PTPTYPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTPCR_SPEC, u8, u8, 4, O>;
#[doc = "Field `PTPDAF` reader - "]
pub type PTPDAF_R = crate::BitReader<bool>;
#[doc = "Field `PTPDAF` writer - "]
pub type PTPDAF_W<'a, const O: u8> = crate::BitWriter<'a, u32, PTPCR_SPEC, bool, O>;
impl R {
#[doc = "Bit 1"]
#[inline(always)]
pub fn ptpcs(&self) -> PTPCS_R {
PTPCS_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn ptpini(&self) -> PTPINI_R {
PTPINI_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn ptpup(&self) -> PTPUP_R {
PTPUP_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn ptpint(&self) -> PTPINT_R {
PTPINT_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn ptpadup(&self) -> PTPADUP_R {
PTPADUP_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn ptpeall(&self) -> PTPEALL_R {
PTPEALL_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ptpnss(&self) -> PTPNSS_R {
PTPNSS_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn ptpver(&self) -> PTPVER_R {
PTPVER_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn ptpeth(&self) -> PTPETH_R {
PTPETH_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn ptpipv6(&self) -> PTPIPV6_R {
PTPIPV6_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn ptpipv4(&self) -> PTPIPV4_R {
PTPIPV4_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bits 14:17"]
#[inline(always)]
pub fn ptptyps(&self) -> PTPTYPS_R {
PTPTYPS_R::new(((self.bits >> 14) & 0x0f) as u8)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn ptpdaf(&self) -> PTPDAF_R {
PTPDAF_R::new(((self.bits >> 18) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn ptpen(&mut self) -> PTPEN_W<0> {
PTPEN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn ptpcs(&mut self) -> PTPCS_W<1> {
PTPCS_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn ptpini(&mut self) -> PTPINI_W<2> {
PTPINI_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn ptpup(&mut self) -> PTPUP_W<3> {
PTPUP_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn ptpint(&mut self) -> PTPINT_W<4> {
PTPINT_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn ptpadup(&mut self) -> PTPADUP_W<5> {
PTPADUP_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn ptpeall(&mut self) -> PTPEALL_W<8> {
PTPEALL_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ptpnss(&mut self) -> PTPNSS_W<9> {
PTPNSS_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn ptpver(&mut self) -> PTPVER_W<10> {
PTPVER_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn ptpeth(&mut self) -> PTPETH_W<11> {
PTPETH_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn ptpipv6(&mut self) -> PTPIPV6_W<12> {
PTPIPV6_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn ptpipv4(&mut self) -> PTPIPV4_W<13> {
PTPIPV4_W::new(self)
}
#[doc = "Bits 14:17"]
#[inline(always)]
#[must_use]
pub fn ptptyps(&mut self) -> PTPTYPS_W<14> {
PTPTYPS_W::new(self)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn ptpdaf(&mut self) -> PTPDAF_W<18> {
PTPDAF_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "PTP Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptpcr](index.html) module"]
pub struct PTPCR_SPEC;
impl crate::RegisterSpec for PTPCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ptpcr::R](R) reader structure"]
impl crate::Readable for PTPCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ptpcr::W](W) writer structure"]
impl crate::Writable for PTPCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PTPCR to value 0x2000"]
impl crate::Resettable for PTPCR_SPEC {
const RESET_VALUE: Self::Ux = 0x2000;
}
}
#[doc = "PTPSR (rw) register accessor: an alias for `Reg<PTPSR_SPEC>`"]
pub type PTPSR = crate::Reg<ptpsr::PTPSR_SPEC>;
#[doc = "PTP Status Register"]
pub mod ptpsr {
#[doc = "Register `PTPSR` reader"]
pub struct R(crate::R<PTPSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PTPSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PTPSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PTPSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PTPSR` writer"]
pub struct W(crate::W<PTPSR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PTPSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PTPSR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PTPSR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TSOVF` reader - \n\nThe field is **cleared** (set to zero) following a read operation."]
pub type TSOVF_R = crate::BitReader<bool>;
#[doc = "Field `TSTA0` reader - \n\nThe field is **cleared** (set to zero) following a read operation."]
pub type TSTA0_R = crate::BitReader<bool>;
#[doc = "Field `TSER0` reader - \n\nThe field is **cleared** (set to zero) following a read operation."]
pub type TSER0_R = crate::BitReader<bool>;
#[doc = "Field `TSTA1` reader - \n\nThe field is **cleared** (set to zero) following a read operation."]
pub type TSTA1_R = crate::BitReader<bool>;
#[doc = "Field `TSER1` reader - \n\nThe field is **cleared** (set to zero) following a read operation."]
pub type TSER1_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn tsovf(&self) -> TSOVF_R {
TSOVF_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn tsta0(&self) -> TSTA0_R {
TSTA0_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn tser0(&self) -> TSER0_R {
TSER0_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn tsta1(&self) -> TSTA1_R {
TSTA1_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn tser1(&self) -> TSER1_R {
TSER1_R::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "PTP Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptpsr](index.html) module"]
pub struct PTPSR_SPEC;
impl crate::RegisterSpec for PTPSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ptpsr::R](R) reader structure"]
impl crate::Readable for PTPSR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ptpsr::W](W) writer structure"]
impl crate::Writable for PTPSR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PTPSR to value 0"]
impl crate::Resettable for PTPSR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PTPBSAR (rw) register accessor: an alias for `Reg<PTPBSAR_SPEC>`"]
pub type PTPBSAR = crate::Reg<ptpbsar::PTPBSAR_SPEC>;
#[doc = "PTP Basic Addend Register"]
pub mod ptpbsar {
#[doc = "Register `PTPBSAR` reader"]
pub struct R(crate::R<PTPBSAR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PTPBSAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PTPBSAR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PTPBSAR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PTPBSAR` writer"]
pub struct W(crate::W<PTPBSAR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PTPBSAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PTPBSAR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PTPBSAR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `BSADD` reader - "]
pub type BSADD_R = crate::FieldReader<u32, u32>;
#[doc = "Field `BSADD` writer - "]
pub type BSADD_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PTPBSAR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn bsadd(&self) -> BSADD_R {
BSADD_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn bsadd(&mut self) -> BSADD_W<0> {
BSADD_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "PTP Basic Addend Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptpbsar](index.html) module"]
pub struct PTPBSAR_SPEC;
impl crate::RegisterSpec for PTPBSAR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ptpbsar::R](R) reader structure"]
impl crate::Readable for PTPBSAR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ptpbsar::W](W) writer structure"]
impl crate::Writable for PTPBSAR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PTPBSAR to value 0"]
impl crate::Resettable for PTPBSAR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PTPNSAR (rw) register accessor: an alias for `Reg<PTPNSAR_SPEC>`"]
pub type PTPNSAR = crate::Reg<ptpnsar::PTPNSAR_SPEC>;
#[doc = "PTP subsecond adder register"]
pub mod ptpnsar {
#[doc = "Register `PTPNSAR` reader"]
pub struct R(crate::R<PTPNSAR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PTPNSAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PTPNSAR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PTPNSAR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PTPNSAR` writer"]
pub struct W(crate::W<PTPNSAR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PTPNSAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PTPNSAR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PTPNSAR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `NSADD` reader - "]
pub type NSADD_R = crate::FieldReader<u8, u8>;
#[doc = "Field `NSADD` writer - "]
pub type NSADD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTPNSAR_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn nsadd(&self) -> NSADD_R {
NSADD_R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn nsadd(&mut self) -> NSADD_W<0> {
NSADD_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "PTP subsecond adder register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptpnsar](index.html) module"]
pub struct PTPNSAR_SPEC;
impl crate::RegisterSpec for PTPNSAR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ptpnsar::R](R) reader structure"]
impl crate::Readable for PTPNSAR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ptpnsar::W](W) writer structure"]
impl crate::Writable for PTPNSAR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PTPNSAR to value 0"]
impl crate::Resettable for PTPNSAR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PTPSBSR (r) register accessor: an alias for `Reg<PTPSBSR_SPEC>`"]
pub type PTPSBSR = crate::Reg<ptpsbsr::PTPSBSR_SPEC>;
#[doc = "PTP System Second Register"]
pub mod ptpsbsr {
#[doc = "Register `PTPSBSR` reader"]
pub struct R(crate::R<PTPSBSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PTPSBSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PTPSBSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PTPSBSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `SBSEC` reader - "]
pub type SBSEC_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn sbsec(&self) -> SBSEC_R {
SBSEC_R::new(self.bits)
}
}
#[doc = "PTP System Second Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptpsbsr](index.html) module"]
pub struct PTPSBSR_SPEC;
impl crate::RegisterSpec for PTPSBSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ptpsbsr::R](R) reader structure"]
impl crate::Readable for PTPSBSR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets PTPSBSR to value 0"]
impl crate::Resettable for PTPSBSR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PTPSNSR (r) register accessor: an alias for `Reg<PTPSNSR_SPEC>`"]
pub type PTPSNSR = crate::Reg<ptpsnsr::PTPSNSR_SPEC>;
#[doc = "PTP System Subsecond Register"]
pub mod ptpsnsr {
#[doc = "Register `PTPSNSR` reader"]
pub struct R(crate::R<PTPSNSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PTPSNSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PTPSNSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PTPSNSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `SNSEC` reader - "]
pub type SNSEC_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:30"]
#[inline(always)]
pub fn snsec(&self) -> SNSEC_R {
SNSEC_R::new(self.bits & 0x7fff_ffff)
}
}
#[doc = "PTP System Subsecond Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptpsnsr](index.html) module"]
pub struct PTPSNSR_SPEC;
impl crate::RegisterSpec for PTPSNSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ptpsnsr::R](R) reader structure"]
impl crate::Readable for PTPSNSR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets PTPSNSR to value 0"]
impl crate::Resettable for PTPSNSR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PTPUBSR (rw) register accessor: an alias for `Reg<PTPUBSR_SPEC>`"]
pub type PTPUBSR = crate::Reg<ptpubsr::PTPUBSR_SPEC>;
#[doc = "PTP Update Seconds Register"]
pub mod ptpubsr {
#[doc = "Register `PTPUBSR` reader"]
pub struct R(crate::R<PTPUBSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PTPUBSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PTPUBSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PTPUBSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PTPUBSR` writer"]
pub struct W(crate::W<PTPUBSR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PTPUBSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PTPUBSR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PTPUBSR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `UBSEC` reader - "]
pub type UBSEC_R = crate::FieldReader<u32, u32>;
#[doc = "Field `UBSEC` writer - "]
pub type UBSEC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PTPUBSR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn ubsec(&self) -> UBSEC_R {
UBSEC_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn ubsec(&mut self) -> UBSEC_W<0> {
UBSEC_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "PTP Update Seconds Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptpubsr](index.html) module"]
pub struct PTPUBSR_SPEC;
impl crate::RegisterSpec for PTPUBSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ptpubsr::R](R) reader structure"]
impl crate::Readable for PTPUBSR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ptpubsr::W](W) writer structure"]
impl crate::Writable for PTPUBSR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PTPUBSR to value 0"]
impl crate::Resettable for PTPUBSR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PTPUNSR (rw) register accessor: an alias for `Reg<PTPUNSR_SPEC>`"]
pub type PTPUNSR = crate::Reg<ptpunsr::PTPUNSR_SPEC>;
#[doc = "PTP update subsecond register"]
pub mod ptpunsr {
#[doc = "Register `PTPUNSR` reader"]
pub struct R(crate::R<PTPUNSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PTPUNSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PTPUNSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PTPUNSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PTPUNSR` writer"]
pub struct W(crate::W<PTPUNSR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PTPUNSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PTPUNSR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PTPUNSR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `UNSEC` reader - "]
pub type UNSEC_R = crate::FieldReader<u32, u32>;
#[doc = "Field `UNSEC` writer - "]
pub type UNSEC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PTPUNSR_SPEC, u32, u32, 31, O>;
#[doc = "Field `UPNSEC` reader - "]
pub type UPNSEC_R = crate::BitReader<bool>;
#[doc = "Field `UPNSEC` writer - "]
pub type UPNSEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, PTPUNSR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:30"]
#[inline(always)]
pub fn unsec(&self) -> UNSEC_R {
UNSEC_R::new(self.bits & 0x7fff_ffff)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn upnsec(&self) -> UPNSEC_R {
UPNSEC_R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:30"]
#[inline(always)]
#[must_use]
pub fn unsec(&mut self) -> UNSEC_W<0> {
UNSEC_W::new(self)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn upnsec(&mut self) -> UPNSEC_W<31> {
UPNSEC_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "PTP update subsecond register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptpunsr](index.html) module"]
pub struct PTPUNSR_SPEC;
impl crate::RegisterSpec for PTPUNSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ptpunsr::R](R) reader structure"]
impl crate::Readable for PTPUNSR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ptpunsr::W](W) writer structure"]
impl crate::Writable for PTPUNSR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PTPUNSR to value 0"]
impl crate::Resettable for PTPUNSR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PTPTBSR (rw) register accessor: an alias for `Reg<PTPTBSR_SPEC>`"]
pub type PTPTBSR = crate::Reg<ptptbsr::PTPTBSR_SPEC>;
#[doc = "PTP Target Seconds Register 0"]
pub mod ptptbsr {
#[doc = "Register `PTPTBSR` reader"]
pub struct R(crate::R<PTPTBSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PTPTBSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PTPTBSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PTPTBSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PTPTBSR` writer"]
pub struct W(crate::W<PTPTBSR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PTPTBSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PTPTBSR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PTPTBSR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TBSEC` reader - "]
pub type TBSEC_R = crate::FieldReader<u32, u32>;
#[doc = "Field `TBSEC` writer - "]
pub type TBSEC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PTPTBSR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn tbsec(&self) -> TBSEC_R {
TBSEC_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn tbsec(&mut self) -> TBSEC_W<0> {
TBSEC_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "PTP Target Seconds Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptptbsr](index.html) module"]
pub struct PTPTBSR_SPEC;
impl crate::RegisterSpec for PTPTBSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ptptbsr::R](R) reader structure"]
impl crate::Readable for PTPTBSR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ptptbsr::W](W) writer structure"]
impl crate::Writable for PTPTBSR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PTPTBSR to value 0"]
impl crate::Resettable for PTPTBSR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PTPTNSR (rw) register accessor: an alias for `Reg<PTPTNSR_SPEC>`"]
pub type PTPTNSR = crate::Reg<ptptnsr::PTPTNSR_SPEC>;
#[doc = "PTP Target Subsecond Register 0"]
pub mod ptptnsr {
#[doc = "Register `PTPTNSR` reader"]
pub struct R(crate::R<PTPTNSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PTPTNSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PTPTNSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PTPTNSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PTPTNSR` writer"]
pub struct W(crate::W<PTPTNSR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PTPTNSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PTPTNSR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PTPTNSR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TNSEC` reader - "]
pub type TNSEC_R = crate::FieldReader<u32, u32>;
#[doc = "Field `TNSEC` writer - "]
pub type TNSEC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PTPTNSR_SPEC, u32, u32, 31, O>;
impl R {
#[doc = "Bits 0:30"]
#[inline(always)]
pub fn tnsec(&self) -> TNSEC_R {
TNSEC_R::new(self.bits & 0x7fff_ffff)
}
}
impl W {
#[doc = "Bits 0:30"]
#[inline(always)]
#[must_use]
pub fn tnsec(&mut self) -> TNSEC_W<0> {
TNSEC_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "PTP Target Subsecond Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptptnsr](index.html) module"]
pub struct PTPTNSR_SPEC;
impl crate::RegisterSpec for PTPTNSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ptptnsr::R](R) reader structure"]
impl crate::Readable for PTPTNSR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ptptnsr::W](W) writer structure"]
impl crate::Writable for PTPTNSR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PTPTNSR to value 0"]
impl crate::Resettable for PTPTNSR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PTPPPSR (rw) register accessor: an alias for `Reg<PTPPPSR_SPEC>`"]
pub type PTPPPSR = crate::Reg<ptpppsr::PTPPPSR_SPEC>;
#[doc = "PTP PPS Control Register"]
pub mod ptpppsr {
#[doc = "Register `PTPPPSR` reader"]
pub struct R(crate::R<PTPPPSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PTPPPSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PTPPPSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PTPPPSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PTPPPSR` writer"]
pub struct W(crate::W<PTPPPSR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PTPPPSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PTPPPSR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PTPPPSR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PPSOUT0` reader - "]
pub type PPSOUT0_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PPSOUT0` writer - "]
pub type PPSOUT0_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PTPPPSR_SPEC, u8, u8, 4, O>;
#[doc = "Field `PPSOMD` reader - "]
pub type PPSOMD_R = crate::BitReader<bool>;
#[doc = "Field `PPSOMD` writer - "]
pub type PPSOMD_W<'a, const O: u8> = crate::BitWriter<'a, u32, PTPPPSR_SPEC, bool, O>;
#[doc = "Field `TTSEL0` reader - "]
pub type TTSEL0_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TTSEL0` writer - "]
pub type TTSEL0_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PTPPPSR_SPEC, u8, u8, 2, O>;
#[doc = "Field `PPSOUT1` reader - "]
pub type PPSOUT1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PPSOUT1` writer - "]
pub type PPSOUT1_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PTPPPSR_SPEC, u8, u8, 3, O>;
#[doc = "Field `TTSEL1` reader - "]
pub type TTSEL1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TTSEL1` writer - "]
pub type TTSEL1_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PTPPPSR_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn ppsout0(&self) -> PPSOUT0_R {
PPSOUT0_R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn ppsomd(&self) -> PPSOMD_R {
PPSOMD_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6"]
#[inline(always)]
pub fn ttsel0(&self) -> TTSEL0_R {
TTSEL0_R::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bits 8:10"]
#[inline(always)]
pub fn ppsout1(&self) -> PPSOUT1_R {
PPSOUT1_R::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bits 13:14"]
#[inline(always)]
pub fn ttsel1(&self) -> TTSEL1_R {
TTSEL1_R::new(((self.bits >> 13) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn ppsout0(&mut self) -> PPSOUT0_W<0> {
PPSOUT0_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn ppsomd(&mut self) -> PPSOMD_W<4> {
PPSOMD_W::new(self)
}
#[doc = "Bits 5:6"]
#[inline(always)]
#[must_use]
pub fn ttsel0(&mut self) -> TTSEL0_W<5> {
TTSEL0_W::new(self)
}
#[doc = "Bits 8:10"]
#[inline(always)]
#[must_use]
pub fn ppsout1(&mut self) -> PPSOUT1_W<8> {
PPSOUT1_W::new(self)
}
#[doc = "Bits 13:14"]
#[inline(always)]
#[must_use]
pub fn ttsel1(&mut self) -> TTSEL1_W<13> {
TTSEL1_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "PTP PPS Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptpppsr](index.html) module"]
pub struct PTPPPSR_SPEC;
impl crate::RegisterSpec for PTPPPSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ptpppsr::R](R) reader structure"]
impl crate::Readable for PTPPPSR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ptpppsr::W](W) writer structure"]
impl crate::Writable for PTPPPSR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PTPPPSR to value 0"]
impl crate::Resettable for PTPPPSR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PMTCR (rw) register accessor: an alias for `Reg<PMTCR_SPEC>`"]
pub type PMTCR = crate::Reg<pmtcr::PMTCR_SPEC>;
#[doc = "MAC PMT Control Register"]
pub mod pmtcr {
#[doc = "Register `PMTCR` reader"]
pub struct R(crate::R<PMTCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PMTCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PMTCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PMTCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PMTCR` writer"]
pub struct W(crate::W<PMTCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PMTCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PMTCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PMTCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PWDN` reader - "]
pub type PWDN_R = crate::BitReader<bool>;
#[doc = "Field `PWDN` writer - "]
pub type PWDN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PMTCR_SPEC, bool, O>;
#[doc = "Field `MPEN` reader - "]
pub type MPEN_R = crate::BitReader<bool>;
#[doc = "Field `MPEN` writer - "]
pub type MPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PMTCR_SPEC, bool, O>;
#[doc = "Field `WKEN` reader - "]
pub type WKEN_R = crate::BitReader<bool>;
#[doc = "Field `WKEN` writer - "]
pub type WKEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PMTCR_SPEC, bool, O>;
#[doc = "Field `MPFR` reader - \n\nThe field is **cleared** (set to zero) following a read operation."]
pub type MPFR_R = crate::BitReader<bool>;
#[doc = "Field `WKFR` reader - \n\nThe field is **cleared** (set to zero) following a read operation."]
pub type WKFR_R = crate::BitReader<bool>;
#[doc = "Field `GLUB` reader - "]
pub type GLUB_R = crate::BitReader<bool>;
#[doc = "Field `GLUB` writer - "]
pub type GLUB_W<'a, const O: u8> = crate::BitWriter<'a, u32, PMTCR_SPEC, bool, O>;
#[doc = "Field `RTWKTR` reader - "]
pub type RTWKTR_R = crate::BitReader<bool>;
#[doc = "Field `RTWKTR` writer - "]
pub type RTWKTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, PMTCR_SPEC, bool, O>;
#[doc = "Field `RTWKPT` reader - "]
pub type RTWKPT_R = crate::FieldReader<u8, u8>;
#[doc = "Field `RTWKPT` writer - "]
pub type RTWKPT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PMTCR_SPEC, u8, u8, 3, O>;
#[doc = "Field `RTWKFR` reader - "]
pub type RTWKFR_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pwdn(&self) -> PWDN_R {
PWDN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn mpen(&self) -> MPEN_R {
MPEN_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn wken(&self) -> WKEN_R {
WKEN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn mpfr(&self) -> MPFR_R {
MPFR_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn wkfr(&self) -> WKFR_R {
WKFR_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn glub(&self) -> GLUB_R {
GLUB_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn rtwktr(&self) -> RTWKTR_R {
RTWKTR_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 24:26"]
#[inline(always)]
pub fn rtwkpt(&self) -> RTWKPT_R {
RTWKPT_R::new(((self.bits >> 24) & 7) as u8)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn rtwkfr(&self) -> RTWKFR_R {
RTWKFR_R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pwdn(&mut self) -> PWDN_W<0> {
PWDN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn mpen(&mut self) -> MPEN_W<1> {
MPEN_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn wken(&mut self) -> WKEN_W<2> {
WKEN_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn glub(&mut self) -> GLUB_W<9> {
GLUB_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn rtwktr(&mut self) -> RTWKTR_W<10> {
RTWKTR_W::new(self)
}
#[doc = "Bits 24:26"]
#[inline(always)]
#[must_use]
pub fn rtwkpt(&mut self) -> RTWKPT_W<24> {
RTWKPT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MAC PMT Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmtcr](index.html) module"]
pub struct PMTCR_SPEC;
impl crate::RegisterSpec for PMTCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [pmtcr::R](R) reader structure"]
impl crate::Readable for PMTCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pmtcr::W](W) writer structure"]
impl crate::Writable for PMTCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PMTCR to value 0"]
impl crate::Resettable for PMTCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PMTRWFR (rw) register accessor: an alias for `Reg<PMTRWFR_SPEC>`"]
pub type PMTRWFR = crate::Reg<pmtrwfr::PMTRWFR_SPEC>;
#[doc = "MAC Remote Wakeup Frame Filter Register"]
pub mod pmtrwfr {
#[doc = "Register `PMTRWFR` reader"]
pub struct R(crate::R<PMTRWFR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PMTRWFR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PMTRWFR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PMTRWFR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PMTRWFR` writer"]
pub struct W(crate::W<PMTRWFR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PMTRWFR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PMTRWFR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PMTRWFR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RTWKFLT` reader - "]
pub type RTWKFLT_R = crate::FieldReader<u32, u32>;
#[doc = "Field `RTWKFLT` writer - "]
pub type RTWKFLT_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PMTRWFR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rtwkflt(&self) -> RTWKFLT_R {
RTWKFLT_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rtwkflt(&mut self) -> RTWKFLT_W<0> {
RTWKFLT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MAC Remote Wakeup Frame Filter Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmtrwfr](index.html) module"]
pub struct PMTRWFR_SPEC;
impl crate::RegisterSpec for PMTRWFR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [pmtrwfr::R](R) reader structure"]
impl crate::Readable for PMTRWFR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pmtrwfr::W](W) writer structure"]
impl crate::Writable for PMTRWFR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PMTRWFR to value 0"]
impl crate::Resettable for PMTRWFR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MMCCR (rw) register accessor: an alias for `Reg<MMCCR_SPEC>`"]
pub type MMCCR = crate::Reg<mmccr::MMCCR_SPEC>;
#[doc = "MMC Control Register"]
pub mod mmccr {
#[doc = "Register `MMCCR` reader"]
pub struct R(crate::R<MMCCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MMCCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MMCCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MMCCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MMCCR` writer"]
pub struct W(crate::W<MMCCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MMCCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MMCCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MMCCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CRST` reader - "]
pub type CRST_R = crate::BitReader<bool>;
#[doc = "Field `CRST` writer - "]
pub type CRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, MMCCR_SPEC, bool, O>;
#[doc = "Field `COSR` reader - "]
pub type COSR_R = crate::BitReader<bool>;
#[doc = "Field `COSR` writer - "]
pub type COSR_W<'a, const O: u8> = crate::BitWriter<'a, u32, MMCCR_SPEC, bool, O>;
#[doc = "Field `CRRST` reader - "]
pub type CRRST_R = crate::BitReader<bool>;
#[doc = "Field `CRRST` writer - "]
pub type CRRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, MMCCR_SPEC, bool, O>;
#[doc = "Field `CFIX` reader - "]
pub type CFIX_R = crate::BitReader<bool>;
#[doc = "Field `CFIX` writer - "]
pub type CFIX_W<'a, const O: u8> = crate::BitWriter<'a, u32, MMCCR_SPEC, bool, O>;
#[doc = "Field `CPSET` reader - "]
pub type CPSET_R = crate::BitReader<bool>;
#[doc = "Field `CPSET` writer - "]
pub type CPSET_W<'a, const O: u8> = crate::BitWriter<'a, u32, MMCCR_SPEC, bool, O>;
#[doc = "Field `CPSEL` reader - "]
pub type CPSEL_R = crate::BitReader<bool>;
#[doc = "Field `CPSEL` writer - "]
pub type CPSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, MMCCR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn crst(&self) -> CRST_R {
CRST_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn cosr(&self) -> COSR_R {
COSR_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn crrst(&self) -> CRRST_R {
CRRST_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn cfix(&self) -> CFIX_R {
CFIX_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn cpset(&self) -> CPSET_R {
CPSET_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn cpsel(&self) -> CPSEL_R {
CPSEL_R::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn crst(&mut self) -> CRST_W<0> {
CRST_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn cosr(&mut self) -> COSR_W<1> {
COSR_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn crrst(&mut self) -> CRRST_W<2> {
CRRST_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn cfix(&mut self) -> CFIX_W<3> {
CFIX_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn cpset(&mut self) -> CPSET_W<4> {
CPSET_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn cpsel(&mut self) -> CPSEL_W<5> {
CPSEL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MMC Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmccr](index.html) module"]
pub struct MMCCR_SPEC;
impl crate::RegisterSpec for MMCCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [mmccr::R](R) reader structure"]
impl crate::Readable for MMCCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [mmccr::W](W) writer structure"]
impl crate::Writable for MMCCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MMCCR to value 0"]
impl crate::Resettable for MMCCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MMCRSR (r) register accessor: an alias for `Reg<MMCRSR_SPEC>`"]
pub type MMCRSR = crate::Reg<mmcrsr::MMCRSR_SPEC>;
#[doc = "MMC Receive Status Register"]
pub mod mmcrsr {
#[doc = "Register `MMCRSR` reader"]
pub struct R(crate::R<MMCRSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MMCRSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MMCRSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MMCRSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `RCRCEIS` reader - "]
pub type RCRCEIS_R = crate::BitReader<bool>;
#[doc = "Field `RALIEIS` reader - "]
pub type RALIEIS_R = crate::BitReader<bool>;
#[doc = "Field `RUGIS` reader - "]
pub type RUGIS_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 5"]
#[inline(always)]
pub fn rcrceis(&self) -> RCRCEIS_R {
RCRCEIS_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn ralieis(&self) -> RALIEIS_R {
RALIEIS_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn rugis(&self) -> RUGIS_R {
RUGIS_R::new(((self.bits >> 17) & 1) != 0)
}
}
#[doc = "MMC Receive Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmcrsr](index.html) module"]
pub struct MMCRSR_SPEC;
impl crate::RegisterSpec for MMCRSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [mmcrsr::R](R) reader structure"]
impl crate::Readable for MMCRSR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets MMCRSR to value 0"]
impl crate::Resettable for MMCRSR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MMCTSR (r) register accessor: an alias for `Reg<MMCTSR_SPEC>`"]
pub type MMCTSR = crate::Reg<mmctsr::MMCTSR_SPEC>;
#[doc = "MMC Transmit Status Register"]
pub mod mmctsr {
#[doc = "Register `MMCTSR` reader"]
pub struct R(crate::R<MMCTSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MMCTSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MMCTSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MMCTSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `TGSCIS` reader - "]
pub type TGSCIS_R = crate::BitReader<bool>;
#[doc = "Field `TGMCIS` reader - "]
pub type TGMCIS_R = crate::BitReader<bool>;
#[doc = "Field `TAGIS` reader - "]
pub type TAGIS_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 14"]
#[inline(always)]
pub fn tgscis(&self) -> TGSCIS_R {
TGSCIS_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn tgmcis(&self) -> TGMCIS_R {
TGMCIS_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn tagis(&self) -> TAGIS_R {
TAGIS_R::new(((self.bits >> 21) & 1) != 0)
}
}
#[doc = "MMC Transmit Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmctsr](index.html) module"]
pub struct MMCTSR_SPEC;
impl crate::RegisterSpec for MMCTSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [mmctsr::R](R) reader structure"]
impl crate::Readable for MMCTSR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets MMCTSR to value 0"]
impl crate::Resettable for MMCTSR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MMCRIR (rw) register accessor: an alias for `Reg<MMCRIR_SPEC>`"]
pub type MMCRIR = crate::Reg<mmcrir::MMCRIR_SPEC>;
#[doc = "MMC receive interrupt register"]
pub mod mmcrir {
#[doc = "Register `MMCRIR` reader"]
pub struct R(crate::R<MMCRIR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MMCRIR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MMCRIR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MMCRIR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MMCRIR` writer"]
pub struct W(crate::W<MMCRIR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MMCRIR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MMCRIR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MMCRIR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RCRCEIM` reader - "]
pub type RCRCEIM_R = crate::BitReader<bool>;
#[doc = "Field `RCRCEIM` writer - "]
pub type RCRCEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, MMCRIR_SPEC, bool, O>;
#[doc = "Field `RALIEIM` reader - "]
pub type RALIEIM_R = crate::BitReader<bool>;
#[doc = "Field `RALIEIM` writer - "]
pub type RALIEIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, MMCRIR_SPEC, bool, O>;
#[doc = "Field `RUGIM` reader - "]
pub type RUGIM_R = crate::BitReader<bool>;
#[doc = "Field `RUGIM` writer - "]
pub type RUGIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, MMCRIR_SPEC, bool, O>;
impl R {
#[doc = "Bit 5"]
#[inline(always)]
pub fn rcrceim(&self) -> RCRCEIM_R {
RCRCEIM_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn ralieim(&self) -> RALIEIM_R {
RALIEIM_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn rugim(&self) -> RUGIM_R {
RUGIM_R::new(((self.bits >> 17) & 1) != 0)
}
}
impl W {
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rcrceim(&mut self) -> RCRCEIM_W<5> {
RCRCEIM_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn ralieim(&mut self) -> RALIEIM_W<6> {
RALIEIM_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn rugim(&mut self) -> RUGIM_W<17> {
RUGIM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MMC receive interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmcrir](index.html) module"]
pub struct MMCRIR_SPEC;
impl crate::RegisterSpec for MMCRIR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [mmcrir::R](R) reader structure"]
impl crate::Readable for MMCRIR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [mmcrir::W](W) writer structure"]
impl crate::Writable for MMCRIR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MMCRIR to value 0"]
impl crate::Resettable for MMCRIR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MMCTIR (rw) register accessor: an alias for `Reg<MMCTIR_SPEC>`"]
pub type MMCTIR = crate::Reg<mmctir::MMCTIR_SPEC>;
#[doc = "MMC Transmit Interrupt Register"]
pub mod mmctir {
#[doc = "Register `MMCTIR` reader"]
pub struct R(crate::R<MMCTIR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MMCTIR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MMCTIR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MMCTIR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MMCTIR` writer"]
pub struct W(crate::W<MMCTIR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MMCTIR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MMCTIR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MMCTIR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TGSCIM` reader - "]
pub type TGSCIM_R = crate::BitReader<bool>;
#[doc = "Field `TGSCIM` writer - "]
pub type TGSCIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, MMCTIR_SPEC, bool, O>;
#[doc = "Field `TGMCIM` reader - "]
pub type TGMCIM_R = crate::BitReader<bool>;
#[doc = "Field `TGMCIM` writer - "]
pub type TGMCIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, MMCTIR_SPEC, bool, O>;
#[doc = "Field `TAGIM` reader - "]
pub type TAGIM_R = crate::BitReader<bool>;
#[doc = "Field `TAGIM` writer - "]
pub type TAGIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, MMCTIR_SPEC, bool, O>;
impl R {
#[doc = "Bit 14"]
#[inline(always)]
pub fn tgscim(&self) -> TGSCIM_R {
TGSCIM_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn tgmcim(&self) -> TGMCIM_R {
TGMCIM_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn tagim(&self) -> TAGIM_R {
TAGIM_R::new(((self.bits >> 21) & 1) != 0)
}
}
impl W {
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn tgscim(&mut self) -> TGSCIM_W<14> {
TGSCIM_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn tgmcim(&mut self) -> TGMCIM_W<15> {
TGMCIM_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn tagim(&mut self) -> TAGIM_W<21> {
TAGIM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "MMC Transmit Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmctir](index.html) module"]
pub struct MMCTIR_SPEC;
impl crate::RegisterSpec for MMCTIR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [mmctir::R](R) reader structure"]
impl crate::Readable for MMCTIR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [mmctir::W](W) writer structure"]
impl crate::Writable for MMCTIR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MMCTIR to value 0"]
impl crate::Resettable for MMCTIR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MMCRUGR (r) register accessor: an alias for `Reg<MMCRUGR_SPEC>`"]
pub type MMCRUGR = crate::Reg<mmcrugr::MMCRUGR_SPEC>;
#[doc = "MMC Receive Unicast Good Frame Statistics Register"]
pub mod mmcrugr {
#[doc = "Register `MMCRUGR` reader"]
pub struct R(crate::R<MMCRUGR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MMCRUGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MMCRUGR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MMCRUGR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `MMCRUG` reader - "]
pub type MMCRUG_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn mmcrug(&self) -> MMCRUG_R {
MMCRUG_R::new(self.bits)
}
}
#[doc = "MMC Receive Unicast Good Frame Statistics Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmcrugr](index.html) module"]
pub struct MMCRUGR_SPEC;
impl crate::RegisterSpec for MMCRUGR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [mmcrugr::R](R) reader structure"]
impl crate::Readable for MMCRUGR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets MMCRUGR to value 0"]
impl crate::Resettable for MMCRUGR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MMCRALIER (r) register accessor: an alias for `Reg<MMCRALIER_SPEC>`"]
pub type MMCRALIER = crate::Reg<mmcralier::MMCRALIER_SPEC>;
#[doc = "MMC Alignment Error Received Frame Statistics Register"]
pub mod mmcralier {
#[doc = "Register `MMCRALIER` reader"]
pub struct R(crate::R<MMCRALIER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MMCRALIER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MMCRALIER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MMCRALIER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `RALIE` reader - "]
pub type RALIE_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn ralie(&self) -> RALIE_R {
RALIE_R::new(self.bits)
}
}
#[doc = "MMC Alignment Error Received Frame Statistics Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmcralier](index.html) module"]
pub struct MMCRALIER_SPEC;
impl crate::RegisterSpec for MMCRALIER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [mmcralier::R](R) reader structure"]
impl crate::Readable for MMCRALIER_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets MMCRALIER to value 0"]
impl crate::Resettable for MMCRALIER_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MMCRCRCER (r) register accessor: an alias for `Reg<MMCRCRCER_SPEC>`"]
pub type MMCRCRCER = crate::Reg<mmcrcrcer::MMCRCRCER_SPEC>;
#[doc = "MMC CRC Error Received Frame Statistics Register"]
pub mod mmcrcrcer {
#[doc = "Register `MMCRCRCER` reader"]
pub struct R(crate::R<MMCRCRCER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MMCRCRCER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MMCRCRCER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MMCRCRCER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `RCRCE` reader - "]
pub type RCRCE_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rcrce(&self) -> RCRCE_R {
RCRCE_R::new(self.bits)
}
}
#[doc = "MMC CRC Error Received Frame Statistics Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmcrcrcer](index.html) module"]
pub struct MMCRCRCER_SPEC;
impl crate::RegisterSpec for MMCRCRCER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [mmcrcrcer::R](R) reader structure"]
impl crate::Readable for MMCRCRCER_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets MMCRCRCER to value 0"]
impl crate::Resettable for MMCRCRCER_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MMCTGR (r) register accessor: an alias for `Reg<MMCTGR_SPEC>`"]
pub type MMCTGR = crate::Reg<mmctgr::MMCTGR_SPEC>;
#[doc = "MMC sends good frame pass statistics register"]
pub mod mmctgr {
#[doc = "Register `MMCTGR` reader"]
pub struct R(crate::R<MMCTGR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MMCTGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MMCTGR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MMCTGR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `MMCTG` reader - "]
pub type MMCTG_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn mmctg(&self) -> MMCTG_R {
MMCTG_R::new(self.bits)
}
}
#[doc = "MMC sends good frame pass statistics register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmctgr](index.html) module"]
pub struct MMCTGR_SPEC;
impl crate::RegisterSpec for MMCTGR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [mmctgr::R](R) reader structure"]
impl crate::Readable for MMCTGR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets MMCTGR to value 0"]
impl crate::Resettable for MMCTGR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MMCTGSCR (r) register accessor: an alias for `Reg<MMCTGSCR_SPEC>`"]
pub type MMCTGSCR = crate::Reg<mmctgscr::MMCTGSCR_SPEC>;
#[doc = "MMC sends a good frame statistics register after a single collision error"]
pub mod mmctgscr {
#[doc = "Register `MMCTGSCR` reader"]
pub struct R(crate::R<MMCTGSCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MMCTGSCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MMCTGSCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MMCTGSCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `TGSC` reader - "]
pub type TGSC_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn tgsc(&self) -> TGSC_R {
TGSC_R::new(self.bits)
}
}
#[doc = "MMC sends a good frame statistics register after a single collision error\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmctgscr](index.html) module"]
pub struct MMCTGSCR_SPEC;
impl crate::RegisterSpec for MMCTGSCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [mmctgscr::R](R) reader structure"]
impl crate::Readable for MMCTGSCR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets MMCTGSCR to value 0"]
impl crate::Resettable for MMCTGSCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MMCTGMCR (r) register accessor: an alias for `Reg<MMCTGMCR_SPEC>`"]
pub type MMCTGMCR = crate::Reg<mmctgmcr::MMCTGMCR_SPEC>;
#[doc = "MMC sends good frame statistics register after multiple collision errors"]
pub mod mmctgmcr {
#[doc = "Register `MMCTGMCR` reader"]
pub struct R(crate::R<MMCTGMCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MMCTGMCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MMCTGMCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MMCTGMCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `TGMC` reader - "]
pub type TGMC_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn tgmc(&self) -> TGMC_R {
TGMC_R::new(self.bits)
}
}
#[doc = "MMC sends good frame statistics register after multiple collision errors\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmctgmcr](index.html) module"]
pub struct MMCTGMCR_SPEC;
impl crate::RegisterSpec for MMCTGMCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [mmctgmcr::R](R) reader structure"]
impl crate::Readable for MMCTGMCR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets MMCTGMCR to value 0"]
impl crate::Resettable for MMCTGMCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "EXTI"]
pub struct EXTI {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for EXTI {}
impl EXTI {
#[doc = r"Pointer to the register block"]
pub const PTR: *const exti::RegisterBlock = 0x4001_0400 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const exti::RegisterBlock {
Self::PTR
}
}
impl Deref for EXTI {
type Target = exti::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for EXTI {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("EXTI").finish()
}
}
#[doc = "EXTI"]
pub mod exti {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - interrupt mask register"]
pub imr: IMR,
#[doc = "0x04 - event mask register"]
pub emr: EMR,
#[doc = "0x08 - Rising edge trigger select register"]
pub rtsr: RTSR,
#[doc = "0x0c - Falling edge trigger select register"]
pub ftsr: FTSR,
#[doc = "0x10 - Software Interrupt Event Register"]
pub swier: SWIER,
#[doc = "0x14 - pending register"]
pub pr: PR,
}
#[doc = "IMR (rw) register accessor: an alias for `Reg<IMR_SPEC>`"]
pub type IMR = crate::Reg<imr::IMR_SPEC>;
#[doc = "interrupt mask register"]
pub mod imr {
#[doc = "Register `IMR` reader"]
pub struct R(crate::R<IMR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IMR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IMR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IMR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IMR` writer"]
pub struct W(crate::W<IMR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IMR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IMR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IMR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `IMR` reader - "]
pub type IMR_R = crate::FieldReader<u32, u32>;
#[doc = "Field `IMR` writer - "]
pub type IMR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IMR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn imr(&self) -> IMR_R {
IMR_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn imr(&mut self) -> IMR_W<0> {
IMR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"]
pub struct IMR_SPEC;
impl crate::RegisterSpec for IMR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [imr::R](R) reader structure"]
impl crate::Readable for IMR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [imr::W](W) writer structure"]
impl crate::Writable for IMR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IMR to value 0"]
impl crate::Resettable for IMR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "EMR (rw) register accessor: an alias for `Reg<EMR_SPEC>`"]
pub type EMR = crate::Reg<emr::EMR_SPEC>;
#[doc = "event mask register"]
pub mod emr {
#[doc = "Register `EMR` reader"]
pub struct R(crate::R<EMR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<EMR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<EMR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<EMR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `EMR` writer"]
pub struct W(crate::W<EMR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<EMR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<EMR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<EMR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EMR` reader - "]
pub type EMR_R = crate::FieldReader<u32, u32>;
#[doc = "Field `EMR` writer - "]
pub type EMR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EMR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn emr(&self) -> EMR_R {
EMR_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn emr(&mut self) -> EMR_W<0> {
EMR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "event mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [emr](index.html) module"]
pub struct EMR_SPEC;
impl crate::RegisterSpec for EMR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [emr::R](R) reader structure"]
impl crate::Readable for EMR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [emr::W](W) writer structure"]
impl crate::Writable for EMR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets EMR to value 0"]
impl crate::Resettable for EMR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RTSR (rw) register accessor: an alias for `Reg<RTSR_SPEC>`"]
pub type RTSR = crate::Reg<rtsr::RTSR_SPEC>;
#[doc = "Rising edge trigger select register"]
pub mod rtsr {
#[doc = "Register `RTSR` reader"]
pub struct R(crate::R<RTSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RTSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RTSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RTSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `RTSR` writer"]
pub struct W(crate::W<RTSR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<RTSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<RTSR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<RTSR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TR` reader - "]
pub type TR_R = crate::FieldReader<u32, u32>;
#[doc = "Field `TR` writer - "]
pub type TR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RTSR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn tr(&self) -> TR_R {
TR_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn tr(&mut self) -> TR_W<0> {
TR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Rising edge trigger select register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtsr](index.html) module"]
pub struct RTSR_SPEC;
impl crate::RegisterSpec for RTSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rtsr::R](R) reader structure"]
impl crate::Readable for RTSR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [rtsr::W](W) writer structure"]
impl crate::Writable for RTSR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets RTSR to value 0"]
impl crate::Resettable for RTSR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "FTSR (rw) register accessor: an alias for `Reg<FTSR_SPEC>`"]
pub type FTSR = crate::Reg<ftsr::FTSR_SPEC>;
#[doc = "Falling edge trigger select register"]
pub mod ftsr {
#[doc = "Register `FTSR` reader"]
pub struct R(crate::R<FTSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FTSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FTSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FTSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FTSR` writer"]
pub struct W(crate::W<FTSR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FTSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FTSR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FTSR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TR` reader - "]
pub type TR_R = crate::FieldReader<u32, u32>;
#[doc = "Field `TR` writer - "]
pub type TR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FTSR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn tr(&self) -> TR_R {
TR_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn tr(&mut self) -> TR_W<0> {
TR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Falling edge trigger select register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ftsr](index.html) module"]
pub struct FTSR_SPEC;
impl crate::RegisterSpec for FTSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ftsr::R](R) reader structure"]
impl crate::Readable for FTSR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ftsr::W](W) writer structure"]
impl crate::Writable for FTSR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FTSR to value 0"]
impl crate::Resettable for FTSR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SWIER (rw) register accessor: an alias for `Reg<SWIER_SPEC>`"]
pub type SWIER = crate::Reg<swier::SWIER_SPEC>;
#[doc = "Software Interrupt Event Register"]
pub mod swier {
#[doc = "Register `SWIER` reader"]
pub struct R(crate::R<SWIER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SWIER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SWIER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SWIER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SWIER` writer"]
pub struct W(crate::W<SWIER_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SWIER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SWIER_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SWIER_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SWIER` reader - "]
pub type SWIER_R = crate::FieldReader<u32, u32>;
#[doc = "Field `SWIER` writer - "]
pub type SWIER_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SWIER_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn swier(&self) -> SWIER_R {
SWIER_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn swier(&mut self) -> SWIER_W<0> {
SWIER_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Software Interrupt Event Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swier](index.html) module"]
pub struct SWIER_SPEC;
impl crate::RegisterSpec for SWIER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [swier::R](R) reader structure"]
impl crate::Readable for SWIER_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [swier::W](W) writer structure"]
impl crate::Writable for SWIER_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SWIER to value 0"]
impl crate::Resettable for SWIER_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PR (rw) register accessor: an alias for `Reg<PR_SPEC>`"]
pub type PR = crate::Reg<pr::PR_SPEC>;
#[doc = "pending register"]
pub mod pr {
#[doc = "Register `PR` reader"]
pub struct R(crate::R<PR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PR` writer"]
pub struct W(crate::W<PR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PR` reader - "]
pub type PR_R = crate::FieldReader<u32, u32>;
#[doc = "Field `PR` writer - "]
pub type PR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn pr(&self) -> PR_R {
PR_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn pr(&mut self) -> PR_W<0> {
PR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "pending register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pr](index.html) module"]
pub struct PR_SPEC;
impl crate::RegisterSpec for PR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [pr::R](R) reader structure"]
impl crate::Readable for PR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pr::W](W) writer structure"]
impl crate::Writable for PR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff_ffff;
}
#[doc = "`reset()` method sets PR to value 0"]
impl crate::Resettable for PR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "FLASH"]
pub struct FLASH {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for FLASH {}
impl FLASH {
#[doc = r"Pointer to the register block"]
pub const PTR: *const flash::RegisterBlock = 0x4002_2000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const flash::RegisterBlock {
Self::PTR
}
}
impl Deref for FLASH {
type Target = flash::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for FLASH {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLASH").finish()
}
}
#[doc = "FLASH"]
pub mod flash {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Flash Access Control Register"]
pub acr: ACR,
#[doc = "0x04 - FPEC key register"]
pub keyr: KEYR,
#[doc = "0x08 - Flash OPTKEY register"]
pub optkeyr: OPTKEYR,
#[doc = "0x0c - Flash Status Register"]
pub sr: SR,
#[doc = "0x10 - Flash Control Register"]
pub cr: CR,
#[doc = "0x14 - Flash Address Register"]
pub ar: AR,
_reserved6: [u8; 0x04],
#[doc = "0x1c - option byte register"]
pub obr: OBR,
#[doc = "0x20 - write protection register"]
pub wrpr0: WRPR0,
#[doc = "0x24 - write protection register"]
pub wrpr1: WRPR1,
}
#[doc = "ACR (rw) register accessor: an alias for `Reg<ACR_SPEC>`"]
pub type ACR = crate::Reg<acr::ACR_SPEC>;
#[doc = "Flash Access Control Register"]
pub mod acr {
#[doc = "Register `ACR` reader"]
pub struct R(crate::R<ACR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ACR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ACR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ACR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ACR` writer"]
pub struct W(crate::W<ACR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ACR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ACR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ACR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `LATENCY` reader - "]
pub type LATENCY_R = crate::FieldReader<u8, u8>;
#[doc = "Field `LATENCY` writer - "]
pub type LATENCY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ACR_SPEC, u8, u8, 3, O>;
#[doc = "Field `PRFTBE` reader - "]
pub type PRFTBE_R = crate::BitReader<bool>;
#[doc = "Field `PRFTBE` writer - "]
pub type PRFTBE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ACR_SPEC, bool, O>;
#[doc = "Field `PRFTBS` reader - "]
pub type PRFTBS_R = crate::BitReader<bool>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn latency(&self) -> LATENCY_R {
LATENCY_R::new((self.bits & 7) as u8)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn prftbe(&self) -> PRFTBE_R {
PRFTBE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn prftbs(&self) -> PRFTBS_R {
PRFTBS_R::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2"]
#[inline(always)]
#[must_use]
pub fn latency(&mut self) -> LATENCY_W<0> {
LATENCY_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn prftbe(&mut self) -> PRFTBE_W<4> {
PRFTBE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Flash Access Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [acr](index.html) module"]
pub struct ACR_SPEC;
impl crate::RegisterSpec for ACR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [acr::R](R) reader structure"]
impl crate::Readable for ACR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [acr::W](W) writer structure"]
impl crate::Writable for ACR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ACR to value 0x38"]
impl crate::Resettable for ACR_SPEC {
const RESET_VALUE: Self::Ux = 0x38;
}
}
#[doc = "KEYR (w) register accessor: an alias for `Reg<KEYR_SPEC>`"]
pub type KEYR = crate::Reg<keyr::KEYR_SPEC>;
#[doc = "FPEC key register"]
pub mod keyr {
#[doc = "Register `KEYR` writer"]
pub struct W(crate::W<KEYR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<KEYR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<KEYR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<KEYR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `FKEYR` writer - "]
pub type FKEYR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, KEYR_SPEC, u32, u32, 32, O>;
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn fkeyr(&mut self) -> FKEYR_W<0> {
FKEYR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "FPEC key register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [keyr](index.html) module"]
pub struct KEYR_SPEC;
impl crate::RegisterSpec for KEYR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [keyr::W](W) writer structure"]
impl crate::Writable for KEYR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets KEYR to value 0"]
impl crate::Resettable for KEYR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "OPTKEYR (w) register accessor: an alias for `Reg<OPTKEYR_SPEC>`"]
pub type OPTKEYR = crate::Reg<optkeyr::OPTKEYR_SPEC>;
#[doc = "Flash OPTKEY register"]
pub mod optkeyr {
#[doc = "Register `OPTKEYR` writer"]
pub struct W(crate::W<OPTKEYR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<OPTKEYR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<OPTKEYR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<OPTKEYR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `OPTKEYR` writer - "]
pub type OPTKEYR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, OPTKEYR_SPEC, u32, u32, 32, O>;
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn optkeyr(&mut self) -> OPTKEYR_W<0> {
OPTKEYR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Flash OPTKEY register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [optkeyr](index.html) module"]
pub struct OPTKEYR_SPEC;
impl crate::RegisterSpec for OPTKEYR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [optkeyr::W](W) writer structure"]
impl crate::Writable for OPTKEYR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets OPTKEYR to value 0"]
impl crate::Resettable for OPTKEYR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SR (rw) register accessor: an alias for `Reg<SR_SPEC>`"]
pub type SR = crate::Reg<sr::SR_SPEC>;
#[doc = "Flash Status Register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub struct R(crate::R<SR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SR` writer"]
pub struct W(crate::W<SR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `BSY` reader - "]
pub type BSY_R = crate::BitReader<bool>;
#[doc = "Field `PGERR` reader - "]
pub type PGERR_R = crate::BitReader<bool>;
#[doc = "Field `PGERR` writer - "]
pub type PGERR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `WRPRTERR` reader - "]
pub type WRPRTERR_R = crate::BitReader<bool>;
#[doc = "Field `WRPRTERR` writer - "]
pub type WRPRTERR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `EOP` reader - "]
pub type EOP_R = crate::BitReader<bool>;
#[doc = "Field `EOP` writer - "]
pub type EOP_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, SR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn bsy(&self) -> BSY_R {
BSY_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn pgerr(&self) -> PGERR_R {
PGERR_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn wrprterr(&self) -> WRPRTERR_R {
WRPRTERR_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn eop(&self) -> EOP_R {
EOP_R::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn pgerr(&mut self) -> PGERR_W<2> {
PGERR_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn wrprterr(&mut self) -> WRPRTERR_W<4> {
WRPRTERR_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn eop(&mut self) -> EOP_W<5> {
EOP_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Flash Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"]
pub struct SR_SPEC;
impl crate::RegisterSpec for SR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [sr::R](R) reader structure"]
impl crate::Readable for SR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [sr::W](W) writer structure"]
impl crate::Writable for SR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x34;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CR (rw) register accessor: an alias for `Reg<CR_SPEC>`"]
pub type CR = crate::Reg<cr::CR_SPEC>;
#[doc = "Flash Control Register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub struct R(crate::R<CR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR` writer"]
pub struct W(crate::W<CR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PG` reader - "]
pub type PG_R = crate::BitReader<bool>;
#[doc = "Field `PG` writer - "]
pub type PG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `PER` reader - "]
pub type PER_R = crate::BitReader<bool>;
#[doc = "Field `PER` writer - "]
pub type PER_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `MER` reader - "]
pub type MER_R = crate::BitReader<bool>;
#[doc = "Field `MER` writer - "]
pub type MER_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `OPTPG` reader - "]
pub type OPTPG_R = crate::BitReader<bool>;
#[doc = "Field `OPTPG` writer - "]
pub type OPTPG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `OPTER` reader - "]
pub type OPTER_R = crate::BitReader<bool>;
#[doc = "Field `OPTER` writer - "]
pub type OPTER_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `STRT` reader - "]
pub type STRT_R = crate::BitReader<bool>;
#[doc = "Field `STRT` writer - "]
pub type STRT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `LOCK` reader - "]
pub type LOCK_R = crate::BitReader<bool>;
#[doc = "Field `LOCK` writer - "]
pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `OPTWRE` reader - "]
pub type OPTWRE_R = crate::BitReader<bool>;
#[doc = "Field `OPTWRE` writer - "]
pub type OPTWRE_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, CR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pg(&self) -> PG_R {
PG_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn per(&self) -> PER_R {
PER_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn mer(&self) -> MER_R {
MER_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn optpg(&self) -> OPTPG_R {
OPTPG_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn opter(&self) -> OPTER_R {
OPTER_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn strt(&self) -> STRT_R {
STRT_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn lock(&self) -> LOCK_R {
LOCK_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn optwre(&self) -> OPTWRE_R {
OPTWRE_R::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pg(&mut self) -> PG_W<0> {
PG_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn per(&mut self) -> PER_W<1> {
PER_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn mer(&mut self) -> MER_W<2> {
MER_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn optpg(&mut self) -> OPTPG_W<4> {
OPTPG_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn opter(&mut self) -> OPTER_W<5> {
OPTER_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn strt(&mut self) -> STRT_W<6> {
STRT_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn lock(&mut self) -> LOCK_W<7> {
LOCK_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn optwre(&mut self) -> OPTWRE_W<9> {
OPTWRE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Flash Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"]
pub struct CR_SPEC;
impl crate::RegisterSpec for CR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr::R](R) reader structure"]
impl crate::Readable for CR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"]
impl crate::Writable for CR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0200;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR to value 0x80"]
impl crate::Resettable for CR_SPEC {
const RESET_VALUE: Self::Ux = 0x80;
}
}
#[doc = "AR (w) register accessor: an alias for `Reg<AR_SPEC>`"]
pub type AR = crate::Reg<ar::AR_SPEC>;
#[doc = "Flash Address Register"]
pub mod ar {
#[doc = "Register `AR` writer"]
pub struct W(crate::W<AR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<AR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<AR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<AR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `FAR` writer - "]
pub type FAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, AR_SPEC, u32, u32, 32, O>;
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn far(&mut self) -> FAR_W<0> {
FAR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Flash Address Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ar](index.html) module"]
pub struct AR_SPEC;
impl crate::RegisterSpec for AR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [ar::W](W) writer structure"]
impl crate::Writable for AR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets AR to value 0"]
impl crate::Resettable for AR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "OBR (r) register accessor: an alias for `Reg<OBR_SPEC>`"]
pub type OBR = crate::Reg<obr::OBR_SPEC>;
#[doc = "option byte register"]
pub mod obr {
#[doc = "Register `OBR` reader"]
pub struct R(crate::R<OBR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<OBR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<OBR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<OBR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `OPTERR` reader - "]
pub type OPTERR_R = crate::BitReader<bool>;
#[doc = "Field `RDPRT` reader - "]
pub type RDPRT_R = crate::BitReader<bool>;
#[doc = "Field `WDG_SW` reader - "]
pub type WDG_SW_R = crate::BitReader<bool>;
#[doc = "Field `nRST_STOP` reader - "]
pub type N_RST_STOP_R = crate::BitReader<bool>;
#[doc = "Field `nRST_STDBY` reader - "]
pub type N_RST_STDBY_R = crate::BitReader<bool>;
#[doc = "Field `Data0` reader - "]
pub type DATA0_R = crate::FieldReader<u8, u8>;
#[doc = "Field `Data1` reader - "]
pub type DATA1_R = crate::FieldReader<u8, u8>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn opterr(&self) -> OPTERR_R {
OPTERR_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rdprt(&self) -> RDPRT_R {
RDPRT_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn wdg_sw(&self) -> WDG_SW_R {
WDG_SW_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn n_rst_stop(&self) -> N_RST_STOP_R {
N_RST_STOP_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn n_rst_stdby(&self) -> N_RST_STDBY_R {
N_RST_STDBY_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 10:17"]
#[inline(always)]
pub fn data0(&self) -> DATA0_R {
DATA0_R::new(((self.bits >> 10) & 0xff) as u8)
}
#[doc = "Bits 18:25"]
#[inline(always)]
pub fn data1(&self) -> DATA1_R {
DATA1_R::new(((self.bits >> 18) & 0xff) as u8)
}
}
#[doc = "option byte register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [obr](index.html) module"]
pub struct OBR_SPEC;
impl crate::RegisterSpec for OBR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [obr::R](R) reader structure"]
impl crate::Readable for OBR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets OBR to value 0x03ff_fc1e"]
impl crate::Resettable for OBR_SPEC {
const RESET_VALUE: Self::Ux = 0x03ff_fc1e;
}
}
#[doc = "WRPR0 (r) register accessor: an alias for `Reg<WRPR0_SPEC>`"]
pub type WRPR0 = crate::Reg<wrpr0::WRPR0_SPEC>;
#[doc = "write protection register"]
pub mod wrpr0 {
#[doc = "Register `WRPR0` reader"]
pub struct R(crate::R<WRPR0_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<WRPR0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<WRPR0_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<WRPR0_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `WRP` reader - "]
pub type WRP_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn wrp(&self) -> WRP_R {
WRP_R::new(self.bits)
}
}
#[doc = "write protection register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrpr0](index.html) module"]
pub struct WRPR0_SPEC;
impl crate::RegisterSpec for WRPR0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [wrpr0::R](R) reader structure"]
impl crate::Readable for WRPR0_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets WRPR0 to value 0xffff_ffff"]
impl crate::Resettable for WRPR0_SPEC {
const RESET_VALUE: Self::Ux = 0xffff_ffff;
}
}
#[doc = "WRPR1 (r) register accessor: an alias for `Reg<WRPR1_SPEC>`"]
pub type WRPR1 = crate::Reg<wrpr1::WRPR1_SPEC>;
#[doc = "write protection register"]
pub mod wrpr1 {
#[doc = "Register `WRPR1` reader"]
pub struct R(crate::R<WRPR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<WRPR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<WRPR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<WRPR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `WRP` reader - "]
pub type WRP_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn wrp(&self) -> WRP_R {
WRP_R::new(self.bits)
}
}
#[doc = "write protection register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrpr1](index.html) module"]
pub struct WRPR1_SPEC;
impl crate::RegisterSpec for WRPR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [wrpr1::R](R) reader structure"]
impl crate::Readable for WRPR1_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets WRPR1 to value 0xffff_ffff"]
impl crate::Resettable for WRPR1_SPEC {
const RESET_VALUE: Self::Ux = 0xffff_ffff;
}
}
}
#[doc = "FLEXCAN1"]
pub struct FLEXCAN1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for FLEXCAN1 {}
impl FLEXCAN1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const flexcan1::RegisterBlock = 0x4000_c000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const flexcan1::RegisterBlock {
Self::PTR
}
}
impl Deref for FLEXCAN1 {
type Target = flexcan1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for FLEXCAN1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLEXCAN1").finish()
}
}
#[doc = "FLEXCAN1"]
pub mod flexcan1 {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Module configuration register"]
pub mcr: MCR,
#[doc = "0x04 - Control 1 register"]
pub ctrl1: CTRL1,
#[doc = "0x08 - Free running timer register"]
pub timer: TIMER,
_reserved3: [u8; 0x04],
#[doc = "0x10 - Rx mailbox global mask register"]
pub rxmgmask: RXMGMASK,
#[doc = "0x14 - Rx 14 mask register"]
pub rx14mask: RX14MASK,
#[doc = "0x18 - Rx 15 mask register"]
pub rx15mask: RX15MASK,
#[doc = "0x1c - Error count register"]
pub ecr: ECR,
#[doc = "0x20 - Error and status 1 register"]
pub esr1: ESR1,
_reserved8: [u8; 0x04],
#[doc = "0x28 - Interrupt mask 1 register"]
pub imask1: IMASK1,
_reserved9: [u8; 0x04],
#[doc = "0x30 - Interrupt flag 1 register"]
pub iflag1: IFLAG1,
#[doc = "0x34 - Control 2 register"]
pub ctrl2: CTRL2,
#[doc = "0x38 - Error and status 2 register"]
pub esr2: ESR2,
_reserved12: [u8; 0x08],
#[doc = "0x44 - CRC register"]
pub crcr: CRCR,
#[doc = "0x48 - Rx FIFO global mask register"]
pub rxfgmask: RXFGMASK,
#[doc = "0x4c - Rx FIFO information register"]
pub rxfir: RXFIR,
#[doc = "0x50 - CAN bit timing register"]
pub cbt: CBT,
_reserved16: [u8; 0x2c],
#[doc = "0x80 - Message Buffer 0 CS Register..Message Buffer 15 CS Register"]
pub cs0: CS0,
#[doc = "0x84 - Message Buffer 0 ID Register..Message Buffer 15 ID Register"]
pub id0: ID0,
#[doc = "0x88 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register"]
pub word0: WORD0,
#[doc = "0x8c - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register"]
pub word1: WORD1,
#[doc = "0x90 - Message Buffer 0 CS Register..Message Buffer 15 CS Register"]
pub cs1: CS1,
#[doc = "0x94 - Message Buffer 0 ID Register..Message Buffer 15 ID Register"]
pub id1: ID1,
#[doc = "0x98 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register"]
pub word01: WORD01,
#[doc = "0x9c - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register"]
pub word11: WORD11,
#[doc = "0xa0 - Message Buffer 0 CS Register..Message Buffer 15 CS Register"]
pub cs2: CS2,
#[doc = "0xa4 - Message Buffer 0 ID Register..Message Buffer 15 ID Register"]
pub id2: ID2,
#[doc = "0xa8 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register"]
pub word02: WORD02,
#[doc = "0xac - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register"]
pub word12: WORD12,
#[doc = "0xb0 - Message Buffer 0 CS Register..Message Buffer 15 CS Register"]
pub cs3: CS3,
#[doc = "0xb4 - Message Buffer 0 ID Register..Message Buffer 15 ID Register"]
pub id3: ID3,
#[doc = "0xb8 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register"]
pub word03: WORD03,
#[doc = "0xbc - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register"]
pub word13: WORD13,
#[doc = "0xc0 - Message Buffer 0 CS Register..Message Buffer 15 CS Register"]
pub cs4: CS4,
#[doc = "0xc4 - Message Buffer 0 ID Register..Message Buffer 15 ID Register"]
pub id4: ID4,
#[doc = "0xc8 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register"]
pub word04: WORD04,
#[doc = "0xcc - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register"]
pub word14: WORD14,
#[doc = "0xd0 - Message Buffer 0 CS Register..Message Buffer 15 CS Register"]
pub cs5: CS5,
#[doc = "0xd4 - Message Buffer 0 ID Register..Message Buffer 15 ID Register"]
pub id5: ID5,
#[doc = "0xd8 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register"]
pub word05: WORD05,
#[doc = "0xdc - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register"]
pub word15: WORD15,
#[doc = "0xe0 - Message Buffer 0 CS Register..Message Buffer 15 CS Register"]
pub cs6: CS6,
#[doc = "0xe4 - Message Buffer 0 ID Register..Message Buffer 15 ID Register"]
pub id6: ID6,
#[doc = "0xe8 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register"]
pub word06: WORD06,
#[doc = "0xec - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register"]
pub word16: WORD16,
#[doc = "0xf0 - Message Buffer 0 CS Register..Message Buffer 15 CS Register"]
pub cs7: CS7,
#[doc = "0xf4 - Message Buffer 0 ID Register..Message Buffer 15 ID Register"]
pub id7: ID7,
#[doc = "0xf8 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register"]
pub word07: WORD07,
#[doc = "0xfc - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register"]
pub word17: WORD17,
#[doc = "0x100 - Message Buffer 0 CS Register..Message Buffer 15 CS Register"]
pub cs8: CS8,
#[doc = "0x104 - Message Buffer 0 ID Register..Message Buffer 15 ID Register"]
pub id8: ID8,
#[doc = "0x108 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register"]
pub word08: WORD08,
#[doc = "0x10c - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register"]
pub word18: WORD18,
#[doc = "0x110 - Message Buffer 0 CS Register..Message Buffer 15 CS Register"]
pub cs9: CS9,
#[doc = "0x114 - Message Buffer 0 ID Register..Message Buffer 15 ID Register"]
pub id9: ID9,
#[doc = "0x118 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register"]
pub word09: WORD09,
#[doc = "0x11c - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register"]
pub word19: WORD19,
#[doc = "0x120 - Message Buffer 0 CS Register..Message Buffer 15 CS Register"]
pub cs10: CS10,
#[doc = "0x124 - Message Buffer 0 ID Register..Message Buffer 15 ID Register"]
pub id10: ID10,
#[doc = "0x128 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register"]
pub word010: WORD010,
#[doc = "0x12c - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register"]
pub word110: WORD110,
#[doc = "0x130 - Message Buffer 0 CS Register..Message Buffer 15 CS Register"]
pub cs11: CS11,
#[doc = "0x134 - Message Buffer 0 ID Register..Message Buffer 15 ID Register"]
pub id11: ID11,
#[doc = "0x138 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register"]
pub word011: WORD011,
#[doc = "0x13c - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register"]
pub word111: WORD111,
#[doc = "0x140 - Message Buffer 0 CS Register..Message Buffer 15 CS Register"]
pub cs12: CS12,
#[doc = "0x144 - Message Buffer 0 ID Register..Message Buffer 15 ID Register"]
pub id12: ID12,
#[doc = "0x148 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register"]
pub word012: WORD012,
#[doc = "0x14c - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register"]
pub word112: WORD112,
#[doc = "0x150 - Message Buffer 0 CS Register..Message Buffer 15 CS Register"]
pub cs13: CS13,
#[doc = "0x154 - Message Buffer 0 ID Register..Message Buffer 15 ID Register"]
pub id13: ID13,
#[doc = "0x158 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register"]
pub word013: WORD013,
#[doc = "0x15c - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register"]
pub word113: WORD113,
#[doc = "0x160 - Message Buffer 0 CS Register..Message Buffer 15 CS Register"]
pub cs14: CS14,
#[doc = "0x164 - Message Buffer 0 ID Register..Message Buffer 15 ID Register"]
pub id14: ID14,
#[doc = "0x168 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register"]
pub word014: WORD014,
#[doc = "0x16c - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register"]
pub word114: WORD114,
#[doc = "0x170 - Message Buffer 0 CS Register..Message Buffer 15 CS Register"]
pub cs15: CS15,
#[doc = "0x174 - Message Buffer 0 ID Register..Message Buffer 15 ID Register"]
pub id15: ID15,
#[doc = "0x178 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register"]
pub word015: WORD015,
#[doc = "0x17c - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register"]
pub word115: WORD115,
_reserved80: [u8; 0x0700],
#[doc = "0x880 - R0 single mask register"]
pub rximr0: RXIMR0,
#[doc = "0x884 - R0 single mask register"]
pub rximr1: RXIMR1,
#[doc = "0x888 - R0 single mask register"]
pub rximr2: RXIMR2,
#[doc = "0x88c - R0 single mask register"]
pub rximr3: RXIMR3,
#[doc = "0x890 - R0 single mask register"]
pub rximr4: RXIMR4,
#[doc = "0x894 - R0 single mask register"]
pub rximr5: RXIMR5,
#[doc = "0x898 - R0 single mask register"]
pub rximr6: RXIMR6,
#[doc = "0x89c - R0 single mask register"]
pub rximr7: RXIMR7,
#[doc = "0x8a0 - R0 single mask register"]
pub rximr8: RXIMR8,
#[doc = "0x8a4 - R0 single mask register"]
pub rximr9: RXIMR9,
#[doc = "0x8a8 - R0 single mask register"]
pub rximr10: RXIMR10,
#[doc = "0x8ac - R0 single mask register"]
pub rximr11: RXIMR11,
#[doc = "0x8b0 - R0 single mask register"]
pub rximr12: RXIMR12,
#[doc = "0x8b4 - R0 single mask register"]
pub rximr13: RXIMR13,
#[doc = "0x8b8 - R0 single mask register"]
pub rximr14: RXIMR14,
#[doc = "0x8bc - R0 single mask register"]
pub rximr15: RXIMR15,
}
#[doc = "MCR (rw) register accessor: an alias for `Reg<MCR_SPEC>`"]
pub type MCR = crate::Reg<mcr::MCR_SPEC>;
#[doc = "Module configuration register"]
pub mod mcr {
#[doc = "Register `MCR` reader"]
pub struct R(crate::R<MCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MCR` writer"]
pub struct W(crate::W<MCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MAXMB` reader - "]
pub type MAXMB_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MAXMB` writer - "]
pub type MAXMB_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MCR_SPEC, u8, u8, 7, O>;
#[doc = "Field `IDAM` reader - "]
pub type IDAM_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IDAM` writer - "]
pub type IDAM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `LPRIOEN` reader - "]
pub type LPRIOEN_R = crate::BitReader<bool>;
#[doc = "Field `LPRIOEN` writer - "]
pub type LPRIOEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>;
#[doc = "Field `DMA` reader - "]
pub type DMA_R = crate::BitReader<bool>;
#[doc = "Field `DMA` writer - "]
pub type DMA_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>;
#[doc = "Field `IRMQ` reader - "]
pub type IRMQ_R = crate::BitReader<bool>;
#[doc = "Field `IRMQ` writer - "]
pub type IRMQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>;
#[doc = "Field `SRXDIS` reader - "]
pub type SRXDIS_R = crate::BitReader<bool>;
#[doc = "Field `SRXDIS` writer - "]
pub type SRXDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>;
#[doc = "Field `WAKSRC` reader - "]
pub type WAKSRC_R = crate::BitReader<bool>;
#[doc = "Field `WAKSRC` writer - "]
pub type WAKSRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>;
#[doc = "Field `LPMACK` reader - "]
pub type LPMACK_R = crate::BitReader<bool>;
#[doc = "Field `WRNEN` reader - "]
pub type WRNEN_R = crate::BitReader<bool>;
#[doc = "Field `WRNEN` writer - "]
pub type WRNEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>;
#[doc = "Field `SLFWAK` reader - "]
pub type SLFWAK_R = crate::BitReader<bool>;
#[doc = "Field `SLFWAK` writer - "]
pub type SLFWAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>;
#[doc = "Field `SUPV` reader - "]
pub type SUPV_R = crate::BitReader<bool>;
#[doc = "Field `SUPV` writer - "]
pub type SUPV_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>;
#[doc = "Field `FRZACK` reader - "]
pub type FRZACK_R = crate::BitReader<bool>;
#[doc = "Field `SOFTRST` reader - "]
pub type SOFTRST_R = crate::BitReader<bool>;
#[doc = "Field `SOFTRST` writer - "]
pub type SOFTRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>;
#[doc = "Field `NOTRDY` reader - "]
pub type NOTRDY_R = crate::BitReader<bool>;
#[doc = "Field `HALT` reader - "]
pub type HALT_R = crate::BitReader<bool>;
#[doc = "Field `HALT` writer - "]
pub type HALT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>;
#[doc = "Field `RFEN` reader - "]
pub type RFEN_R = crate::BitReader<bool>;
#[doc = "Field `RFEN` writer - "]
pub type RFEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>;
#[doc = "Field `FRZ` reader - "]
pub type FRZ_R = crate::BitReader<bool>;
#[doc = "Field `FRZ` writer - "]
pub type FRZ_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>;
#[doc = "Field `MDIS` reader - "]
pub type MDIS_R = crate::BitReader<bool>;
#[doc = "Field `MDIS` writer - "]
pub type MDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:6"]
#[inline(always)]
pub fn maxmb(&self) -> MAXMB_R {
MAXMB_R::new((self.bits & 0x7f) as u8)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn idam(&self) -> IDAM_R {
IDAM_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn lprioen(&self) -> LPRIOEN_R {
LPRIOEN_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn dma(&self) -> DMA_R {
DMA_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn irmq(&self) -> IRMQ_R {
IRMQ_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn srxdis(&self) -> SRXDIS_R {
SRXDIS_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn waksrc(&self) -> WAKSRC_R {
WAKSRC_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn lpmack(&self) -> LPMACK_R {
LPMACK_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn wrnen(&self) -> WRNEN_R {
WRNEN_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn slfwak(&self) -> SLFWAK_R {
SLFWAK_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23"]
#[inline(always)]
pub fn supv(&self) -> SUPV_R {
SUPV_R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn frzack(&self) -> FRZACK_R {
FRZACK_R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn softrst(&self) -> SOFTRST_R {
SOFTRST_R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 27"]
#[inline(always)]
pub fn notrdy(&self) -> NOTRDY_R {
NOTRDY_R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn halt(&self) -> HALT_R {
HALT_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29"]
#[inline(always)]
pub fn rfen(&self) -> RFEN_R {
RFEN_R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn frz(&self) -> FRZ_R {
FRZ_R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn mdis(&self) -> MDIS_R {
MDIS_R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:6"]
#[inline(always)]
#[must_use]
pub fn maxmb(&mut self) -> MAXMB_W<0> {
MAXMB_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn idam(&mut self) -> IDAM_W<8> {
IDAM_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn lprioen(&mut self) -> LPRIOEN_W<13> {
LPRIOEN_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn dma(&mut self) -> DMA_W<15> {
DMA_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn irmq(&mut self) -> IRMQ_W<16> {
IRMQ_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn srxdis(&mut self) -> SRXDIS_W<17> {
SRXDIS_W::new(self)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn waksrc(&mut self) -> WAKSRC_W<19> {
WAKSRC_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn wrnen(&mut self) -> WRNEN_W<21> {
WRNEN_W::new(self)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn slfwak(&mut self) -> SLFWAK_W<22> {
SLFWAK_W::new(self)
}
#[doc = "Bit 23"]
#[inline(always)]
#[must_use]
pub fn supv(&mut self) -> SUPV_W<23> {
SUPV_W::new(self)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn softrst(&mut self) -> SOFTRST_W<25> {
SOFTRST_W::new(self)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn halt(&mut self) -> HALT_W<28> {
HALT_W::new(self)
}
#[doc = "Bit 29"]
#[inline(always)]
#[must_use]
pub fn rfen(&mut self) -> RFEN_W<29> {
RFEN_W::new(self)
}
#[doc = "Bit 30"]
#[inline(always)]
#[must_use]
pub fn frz(&mut self) -> FRZ_W<30> {
FRZ_W::new(self)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn mdis(&mut self) -> MDIS_W<31> {
MDIS_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Module configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcr](index.html) module"]
pub struct MCR_SPEC;
impl crate::RegisterSpec for MCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [mcr::R](R) reader structure"]
impl crate::Readable for MCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [mcr::W](W) writer structure"]
impl crate::Writable for MCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MCR to value 0"]
impl crate::Resettable for MCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CTRL1 (rw) register accessor: an alias for `Reg<CTRL1_SPEC>`"]
pub type CTRL1 = crate::Reg<ctrl1::CTRL1_SPEC>;
#[doc = "Control 1 register"]
pub mod ctrl1 {
#[doc = "Register `CTRL1` reader"]
pub struct R(crate::R<CTRL1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CTRL1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CTRL1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CTRL1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CTRL1` writer"]
pub struct W(crate::W<CTRL1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CTRL1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CTRL1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CTRL1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PROPSEG` reader - "]
pub type PROPSEG_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PROPSEG` writer - "]
pub type PROPSEG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL1_SPEC, u8, u8, 3, O>;
#[doc = "Field `LOM` reader - "]
pub type LOM_R = crate::BitReader<bool>;
#[doc = "Field `LOM` writer - "]
pub type LOM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL1_SPEC, bool, O>;
#[doc = "Field `LBUF` reader - "]
pub type LBUF_R = crate::BitReader<bool>;
#[doc = "Field `LBUF` writer - "]
pub type LBUF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL1_SPEC, bool, O>;
#[doc = "Field `TSYN` reader - "]
pub type TSYN_R = crate::BitReader<bool>;
#[doc = "Field `TSYN` writer - "]
pub type TSYN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL1_SPEC, bool, O>;
#[doc = "Field `BOFFREC` reader - "]
pub type BOFFREC_R = crate::BitReader<bool>;
#[doc = "Field `BOFFREC` writer - "]
pub type BOFFREC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL1_SPEC, bool, O>;
#[doc = "Field `SMP` reader - "]
pub type SMP_R = crate::BitReader<bool>;
#[doc = "Field `SMP` writer - "]
pub type SMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL1_SPEC, bool, O>;
#[doc = "Field `RWRNMSK` reader - "]
pub type RWRNMSK_R = crate::BitReader<bool>;
#[doc = "Field `RWRNMSK` writer - "]
pub type RWRNMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL1_SPEC, bool, O>;
#[doc = "Field `TWRNMSK` reader - "]
pub type TWRNMSK_R = crate::BitReader<bool>;
#[doc = "Field `TWRNMSK` writer - "]
pub type TWRNMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL1_SPEC, bool, O>;
#[doc = "Field `LPB` reader - "]
pub type LPB_R = crate::BitReader<bool>;
#[doc = "Field `LPB` writer - "]
pub type LPB_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL1_SPEC, bool, O>;
#[doc = "Field `CLKSRC` reader - "]
pub type CLKSRC_R = crate::BitReader<bool>;
#[doc = "Field `CLKSRC` writer - "]
pub type CLKSRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL1_SPEC, bool, O>;
#[doc = "Field `ERRMSK` reader - "]
pub type ERRMSK_R = crate::BitReader<bool>;
#[doc = "Field `ERRMSK` writer - "]
pub type ERRMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL1_SPEC, bool, O>;
#[doc = "Field `BOFFMSK` reader - "]
pub type BOFFMSK_R = crate::BitReader<bool>;
#[doc = "Field `BOFFMSK` writer - "]
pub type BOFFMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL1_SPEC, bool, O>;
#[doc = "Field `PSEG2` reader - "]
pub type PSEG2_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PSEG2` writer - "]
pub type PSEG2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL1_SPEC, u8, u8, 3, O>;
#[doc = "Field `PSEG1` reader - "]
pub type PSEG1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PSEG1` writer - "]
pub type PSEG1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL1_SPEC, u8, u8, 3, O>;
#[doc = "Field `RJW` reader - "]
pub type RJW_R = crate::FieldReader<u8, u8>;
#[doc = "Field `RJW` writer - "]
pub type RJW_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL1_SPEC, u8, u8, 2, O>;
#[doc = "Field `PRESDIV` reader - "]
pub type PRESDIV_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PRESDIV` writer - "]
pub type PRESDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL1_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn propseg(&self) -> PROPSEG_R {
PROPSEG_R::new((self.bits & 7) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn lom(&self) -> LOM_R {
LOM_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn lbuf(&self) -> LBUF_R {
LBUF_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn tsyn(&self) -> TSYN_R {
TSYN_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn boffrec(&self) -> BOFFREC_R {
BOFFREC_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn smp(&self) -> SMP_R {
SMP_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn rwrnmsk(&self) -> RWRNMSK_R {
RWRNMSK_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn twrnmsk(&self) -> TWRNMSK_R {
TWRNMSK_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn lpb(&self) -> LPB_R {
LPB_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn clksrc(&self) -> CLKSRC_R {
CLKSRC_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn errmsk(&self) -> ERRMSK_R {
ERRMSK_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn boffmsk(&self) -> BOFFMSK_R {
BOFFMSK_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:18"]
#[inline(always)]
pub fn pseg2(&self) -> PSEG2_R {
PSEG2_R::new(((self.bits >> 16) & 7) as u8)
}
#[doc = "Bits 19:21"]
#[inline(always)]
pub fn pseg1(&self) -> PSEG1_R {
PSEG1_R::new(((self.bits >> 19) & 7) as u8)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn rjw(&self) -> RJW_R {
RJW_R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn presdiv(&self) -> PRESDIV_R {
PRESDIV_R::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:2"]
#[inline(always)]
#[must_use]
pub fn propseg(&mut self) -> PROPSEG_W<0> {
PROPSEG_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn lom(&mut self) -> LOM_W<3> {
LOM_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn lbuf(&mut self) -> LBUF_W<4> {
LBUF_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn tsyn(&mut self) -> TSYN_W<5> {
TSYN_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn boffrec(&mut self) -> BOFFREC_W<6> {
BOFFREC_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn smp(&mut self) -> SMP_W<7> {
SMP_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn rwrnmsk(&mut self) -> RWRNMSK_W<10> {
RWRNMSK_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn twrnmsk(&mut self) -> TWRNMSK_W<11> {
TWRNMSK_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn lpb(&mut self) -> LPB_W<12> {
LPB_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn clksrc(&mut self) -> CLKSRC_W<13> {
CLKSRC_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn errmsk(&mut self) -> ERRMSK_W<14> {
ERRMSK_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn boffmsk(&mut self) -> BOFFMSK_W<15> {
BOFFMSK_W::new(self)
}
#[doc = "Bits 16:18"]
#[inline(always)]
#[must_use]
pub fn pseg2(&mut self) -> PSEG2_W<16> {
PSEG2_W::new(self)
}
#[doc = "Bits 19:21"]
#[inline(always)]
#[must_use]
pub fn pseg1(&mut self) -> PSEG1_W<19> {
PSEG1_W::new(self)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn rjw(&mut self) -> RJW_W<22> {
RJW_W::new(self)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn presdiv(&mut self) -> PRESDIV_W<24> {
PRESDIV_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Control 1 register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl1](index.html) module"]
pub struct CTRL1_SPEC;
impl crate::RegisterSpec for CTRL1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ctrl1::R](R) reader structure"]
impl crate::Readable for CTRL1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ctrl1::W](W) writer structure"]
impl crate::Writable for CTRL1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CTRL1 to value 0"]
impl crate::Resettable for CTRL1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "TIMER (rw) register accessor: an alias for `Reg<TIMER_SPEC>`"]
pub type TIMER = crate::Reg<timer::TIMER_SPEC>;
#[doc = "Free running timer register"]
pub mod timer {
#[doc = "Register `TIMER` reader"]
pub struct R(crate::R<TIMER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<TIMER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<TIMER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<TIMER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `TIMER` writer"]
pub struct W(crate::W<TIMER_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<TIMER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<TIMER_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<TIMER_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TIMER` reader - "]
pub type TIMER_R = crate::FieldReader<u16, u16>;
#[doc = "Field `TIMER` writer - "]
pub type TIMER_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, TIMER_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn timer(&self) -> TIMER_R {
TIMER_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn timer(&mut self) -> TIMER_W<0> {
TIMER_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Free running timer register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [timer](index.html) module"]
pub struct TIMER_SPEC;
impl crate::RegisterSpec for TIMER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [timer::R](R) reader structure"]
impl crate::Readable for TIMER_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [timer::W](W) writer structure"]
impl crate::Writable for TIMER_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets TIMER to value 0"]
impl crate::Resettable for TIMER_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RXMGMASK (rw) register accessor: an alias for `Reg<RXMGMASK_SPEC>`"]
pub type RXMGMASK = crate::Reg<rxmgmask::RXMGMASK_SPEC>;
#[doc = "Rx mailbox global mask register"]
pub mod rxmgmask {
#[doc = "Register `RXMGMASK` reader"]
pub struct R(crate::R<RXMGMASK_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RXMGMASK_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RXMGMASK_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RXMGMASK_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `RXMGMASK` writer"]
pub struct W(crate::W<RXMGMASK_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<RXMGMASK_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<RXMGMASK_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<RXMGMASK_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MG` reader - "]
pub type MG_R = crate::FieldReader<u32, u32>;
#[doc = "Field `MG` writer - "]
pub type MG_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, RXMGMASK_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn mg(&self) -> MG_R {
MG_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn mg(&mut self) -> MG_W<0> {
MG_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Rx mailbox global mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxmgmask](index.html) module"]
pub struct RXMGMASK_SPEC;
impl crate::RegisterSpec for RXMGMASK_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rxmgmask::R](R) reader structure"]
impl crate::Readable for RXMGMASK_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [rxmgmask::W](W) writer structure"]
impl crate::Writable for RXMGMASK_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets RXMGMASK to value 0"]
impl crate::Resettable for RXMGMASK_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RX14MASK (rw) register accessor: an alias for `Reg<RX14MASK_SPEC>`"]
pub type RX14MASK = crate::Reg<rx14mask::RX14MASK_SPEC>;
#[doc = "Rx 14 mask register"]
pub mod rx14mask {
#[doc = "Register `RX14MASK` reader"]
pub struct R(crate::R<RX14MASK_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RX14MASK_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RX14MASK_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RX14MASK_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `RX14MASK` writer"]
pub struct W(crate::W<RX14MASK_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<RX14MASK_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<RX14MASK_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<RX14MASK_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RX14M` reader - "]
pub type RX14M_R = crate::FieldReader<u32, u32>;
#[doc = "Field `RX14M` writer - "]
pub type RX14M_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, RX14MASK_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rx14m(&self) -> RX14M_R {
RX14M_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rx14m(&mut self) -> RX14M_W<0> {
RX14M_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Rx 14 mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx14mask](index.html) module"]
pub struct RX14MASK_SPEC;
impl crate::RegisterSpec for RX14MASK_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rx14mask::R](R) reader structure"]
impl crate::Readable for RX14MASK_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [rx14mask::W](W) writer structure"]
impl crate::Writable for RX14MASK_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets RX14MASK to value 0"]
impl crate::Resettable for RX14MASK_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RX15MASK (rw) register accessor: an alias for `Reg<RX15MASK_SPEC>`"]
pub type RX15MASK = crate::Reg<rx15mask::RX15MASK_SPEC>;
#[doc = "Rx 15 mask register"]
pub mod rx15mask {
#[doc = "Register `RX15MASK` reader"]
pub struct R(crate::R<RX15MASK_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RX15MASK_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RX15MASK_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RX15MASK_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `RX15MASK` writer"]
pub struct W(crate::W<RX15MASK_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<RX15MASK_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<RX15MASK_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<RX15MASK_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RX15M` reader - "]
pub type RX15M_R = crate::FieldReader<u32, u32>;
#[doc = "Field `RX15M` writer - "]
pub type RX15M_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, RX15MASK_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rx15m(&self) -> RX15M_R {
RX15M_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn rx15m(&mut self) -> RX15M_W<0> {
RX15M_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Rx 15 mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx15mask](index.html) module"]
pub struct RX15MASK_SPEC;
impl crate::RegisterSpec for RX15MASK_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rx15mask::R](R) reader structure"]
impl crate::Readable for RX15MASK_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [rx15mask::W](W) writer structure"]
impl crate::Writable for RX15MASK_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets RX15MASK to value 0"]
impl crate::Resettable for RX15MASK_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ECR (rw) register accessor: an alias for `Reg<ECR_SPEC>`"]
pub type ECR = crate::Reg<ecr::ECR_SPEC>;
#[doc = "Error count register"]
pub mod ecr {
#[doc = "Register `ECR` reader"]
pub struct R(crate::R<ECR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ECR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ECR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ECR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ECR` writer"]
pub struct W(crate::W<ECR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ECR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ECR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ECR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TXERRCNT` reader - "]
pub type TXERRCNT_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TXERRCNT` writer - "]
pub type TXERRCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ECR_SPEC, u8, u8, 8, O>;
#[doc = "Field `RXERRCNT` reader - "]
pub type RXERRCNT_R = crate::FieldReader<u8, u8>;
#[doc = "Field `RXERRCNT` writer - "]
pub type RXERRCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ECR_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn txerrcnt(&self) -> TXERRCNT_R {
TXERRCNT_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15"]
#[inline(always)]
pub fn rxerrcnt(&self) -> RXERRCNT_R {
RXERRCNT_R::new(((self.bits >> 8) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn txerrcnt(&mut self) -> TXERRCNT_W<0> {
TXERRCNT_W::new(self)
}
#[doc = "Bits 8:15"]
#[inline(always)]
#[must_use]
pub fn rxerrcnt(&mut self) -> RXERRCNT_W<8> {
RXERRCNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Error count register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ecr](index.html) module"]
pub struct ECR_SPEC;
impl crate::RegisterSpec for ECR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ecr::R](R) reader structure"]
impl crate::Readable for ECR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ecr::W](W) writer structure"]
impl crate::Writable for ECR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ECR to value 0"]
impl crate::Resettable for ECR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ESR1 (rw) register accessor: an alias for `Reg<ESR1_SPEC>`"]
pub type ESR1 = crate::Reg<esr1::ESR1_SPEC>;
#[doc = "Error and status 1 register"]
pub mod esr1 {
#[doc = "Register `ESR1` reader"]
pub struct R(crate::R<ESR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ESR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ESR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ESR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ESR1` writer"]
pub struct W(crate::W<ESR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ESR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ESR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ESR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `WAKINT` reader - "]
pub type WAKINT_R = crate::BitReader<bool>;
#[doc = "Field `WAKINT` writer - "]
pub type WAKINT_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ESR1_SPEC, bool, O>;
#[doc = "Field `ERRINT` reader - "]
pub type ERRINT_R = crate::BitReader<bool>;
#[doc = "Field `ERRINT` writer - "]
pub type ERRINT_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ESR1_SPEC, bool, O>;
#[doc = "Field `BOFFINT` reader - "]
pub type BOFFINT_R = crate::BitReader<bool>;
#[doc = "Field `BOFFINT` writer - "]
pub type BOFFINT_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ESR1_SPEC, bool, O>;
#[doc = "Field `RX` reader - "]
pub type RX_R = crate::BitReader<bool>;
#[doc = "Field `FLTCONF` reader - "]
pub type FLTCONF_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TX` reader - "]
pub type TX_R = crate::BitReader<bool>;
#[doc = "Field `IDLE` reader - "]
pub type IDLE_R = crate::BitReader<bool>;
#[doc = "Field `RXWRN` reader - "]
pub type RXWRN_R = crate::BitReader<bool>;
#[doc = "Field `TXWRN` reader - "]
pub type TXWRN_R = crate::BitReader<bool>;
#[doc = "Field `STFERR` reader - "]
pub type STFERR_R = crate::BitReader<bool>;
#[doc = "Field `FRMERR` reader - "]
pub type FRMERR_R = crate::BitReader<bool>;
#[doc = "Field `CRCERR` reader - "]
pub type CRCERR_R = crate::BitReader<bool>;
#[doc = "Field `ACKERR` reader - "]
pub type ACKERR_R = crate::BitReader<bool>;
#[doc = "Field `BIT0ERR` reader - "]
pub type BIT0ERR_R = crate::BitReader<bool>;
#[doc = "Field `BIT1ERR` reader - "]
pub type BIT1ERR_R = crate::BitReader<bool>;
#[doc = "Field `RWRNINT` reader - "]
pub type RWRNINT_R = crate::BitReader<bool>;
#[doc = "Field `RWRNINT` writer - "]
pub type RWRNINT_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ESR1_SPEC, bool, O>;
#[doc = "Field `TWRNINT` reader - "]
pub type TWRNINT_R = crate::BitReader<bool>;
#[doc = "Field `TWRNINT` writer - "]
pub type TWRNINT_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ESR1_SPEC, bool, O>;
#[doc = "Field `SYNCH` reader - "]
pub type SYNCH_R = crate::BitReader<bool>;
#[doc = "Field `BOFFDONEINT` reader - "]
pub type BOFFDONEINT_R = crate::BitReader<bool>;
#[doc = "Field `BOFFDONEINT` writer - "]
pub type BOFFDONEINT_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ESR1_SPEC, bool, O>;
#[doc = "Field `ERROVR` reader - "]
pub type ERROVR_R = crate::BitReader<bool>;
#[doc = "Field `ERROVR` writer - "]
pub type ERROVR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, ESR1_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn wakint(&self) -> WAKINT_R {
WAKINT_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn errint(&self) -> ERRINT_R {
ERRINT_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn boffint(&self) -> BOFFINT_R {
BOFFINT_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rx(&self) -> RX_R {
RX_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:5"]
#[inline(always)]
pub fn fltconf(&self) -> FLTCONF_R {
FLTCONF_R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tx(&self) -> TX_R {
TX_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn idle(&self) -> IDLE_R {
IDLE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rxwrn(&self) -> RXWRN_R {
RXWRN_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn txwrn(&self) -> TXWRN_R {
TXWRN_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn stferr(&self) -> STFERR_R {
STFERR_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn frmerr(&self) -> FRMERR_R {
FRMERR_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn crcerr(&self) -> CRCERR_R {
CRCERR_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn ackerr(&self) -> ACKERR_R {
ACKERR_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn bit0err(&self) -> BIT0ERR_R {
BIT0ERR_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn bit1err(&self) -> BIT1ERR_R {
BIT1ERR_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn rwrnint(&self) -> RWRNINT_R {
RWRNINT_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn twrnint(&self) -> TWRNINT_R {
TWRNINT_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn synch(&self) -> SYNCH_R {
SYNCH_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn boffdoneint(&self) -> BOFFDONEINT_R {
BOFFDONEINT_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn errovr(&self) -> ERROVR_R {
ERROVR_R::new(((self.bits >> 21) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn wakint(&mut self) -> WAKINT_W<0> {
WAKINT_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn errint(&mut self) -> ERRINT_W<1> {
ERRINT_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn boffint(&mut self) -> BOFFINT_W<2> {
BOFFINT_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn rwrnint(&mut self) -> RWRNINT_W<16> {
RWRNINT_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn twrnint(&mut self) -> TWRNINT_W<17> {
TWRNINT_W::new(self)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn boffdoneint(&mut self) -> BOFFDONEINT_W<19> {
BOFFDONEINT_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn errovr(&mut self) -> ERROVR_W<21> {
ERROVR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Error and status 1 register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [esr1](index.html) module"]
pub struct ESR1_SPEC;
impl crate::RegisterSpec for ESR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [esr1::R](R) reader structure"]
impl crate::Readable for ESR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [esr1::W](W) writer structure"]
impl crate::Writable for ESR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x002b_0007;
}
#[doc = "`reset()` method sets ESR1 to value 0"]
impl crate::Resettable for ESR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "IMASK1 (rw) register accessor: an alias for `Reg<IMASK1_SPEC>`"]
pub type IMASK1 = crate::Reg<imask1::IMASK1_SPEC>;
#[doc = "Interrupt mask 1 register"]
pub mod imask1 {
#[doc = "Register `IMASK1` reader"]
pub struct R(crate::R<IMASK1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IMASK1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IMASK1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IMASK1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IMASK1` writer"]
pub struct W(crate::W<IMASK1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IMASK1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IMASK1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IMASK1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `BUF15TO0M` reader - "]
pub type BUF15TO0M_R = crate::FieldReader<u16, u16>;
#[doc = "Field `BUF15TO0M` writer - "]
pub type BUF15TO0M_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, IMASK1_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn buf15to0m(&self) -> BUF15TO0M_R {
BUF15TO0M_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn buf15to0m(&mut self) -> BUF15TO0M_W<0> {
BUF15TO0M_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Interrupt mask 1 register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imask1](index.html) module"]
pub struct IMASK1_SPEC;
impl crate::RegisterSpec for IMASK1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [imask1::R](R) reader structure"]
impl crate::Readable for IMASK1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [imask1::W](W) writer structure"]
impl crate::Writable for IMASK1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IMASK1 to value 0"]
impl crate::Resettable for IMASK1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "IFLAG1 (rw) register accessor: an alias for `Reg<IFLAG1_SPEC>`"]
pub type IFLAG1 = crate::Reg<iflag1::IFLAG1_SPEC>;
#[doc = "Interrupt flag 1 register"]
pub mod iflag1 {
#[doc = "Register `IFLAG1` reader"]
pub struct R(crate::R<IFLAG1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IFLAG1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IFLAG1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IFLAG1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IFLAG1` writer"]
pub struct W(crate::W<IFLAG1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IFLAG1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IFLAG1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IFLAG1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `BUF0I` reader - "]
pub type BUF0I_R = crate::BitReader<bool>;
#[doc = "Field `BUF0I` writer - "]
pub type BUF0I_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, IFLAG1_SPEC, bool, O>;
#[doc = "Field `BUF4TO1I` reader - "]
pub type BUF4TO1I_R = crate::FieldReader<u8, u8>;
#[doc = "Field `BUF4TO1I` writer - "]
pub type BUF4TO1I_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, IFLAG1_SPEC, u8, u8, 4, O>;
#[doc = "Field `BUF5I` reader - "]
pub type BUF5I_R = crate::BitReader<bool>;
#[doc = "Field `BUF5I` writer - "]
pub type BUF5I_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, IFLAG1_SPEC, bool, O>;
#[doc = "Field `BUF6I` reader - "]
pub type BUF6I_R = crate::BitReader<bool>;
#[doc = "Field `BUF6I` writer - "]
pub type BUF6I_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, IFLAG1_SPEC, bool, O>;
#[doc = "Field `BUF7I` reader - "]
pub type BUF7I_R = crate::BitReader<bool>;
#[doc = "Field `BUF7I` writer - "]
pub type BUF7I_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, IFLAG1_SPEC, bool, O>;
#[doc = "Field `BUF15TO8I` reader - "]
pub type BUF15TO8I_R = crate::FieldReader<u8, u8>;
#[doc = "Field `BUF15TO8I` writer - "]
pub type BUF15TO8I_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, IFLAG1_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn buf0i(&self) -> BUF0I_R {
BUF0I_R::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:4"]
#[inline(always)]
pub fn buf4to1i(&self) -> BUF4TO1I_R {
BUF4TO1I_R::new(((self.bits >> 1) & 0x0f) as u8)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn buf5i(&self) -> BUF5I_R {
BUF5I_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn buf6i(&self) -> BUF6I_R {
BUF6I_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn buf7i(&self) -> BUF7I_R {
BUF7I_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:15"]
#[inline(always)]
pub fn buf15to8i(&self) -> BUF15TO8I_R {
BUF15TO8I_R::new(((self.bits >> 8) & 0xff) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn buf0i(&mut self) -> BUF0I_W<0> {
BUF0I_W::new(self)
}
#[doc = "Bits 1:4"]
#[inline(always)]
#[must_use]
pub fn buf4to1i(&mut self) -> BUF4TO1I_W<1> {
BUF4TO1I_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn buf5i(&mut self) -> BUF5I_W<5> {
BUF5I_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn buf6i(&mut self) -> BUF6I_W<6> {
BUF6I_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn buf7i(&mut self) -> BUF7I_W<7> {
BUF7I_W::new(self)
}
#[doc = "Bits 8:15"]
#[inline(always)]
#[must_use]
pub fn buf15to8i(&mut self) -> BUF15TO8I_W<8> {
BUF15TO8I_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Interrupt flag 1 register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iflag1](index.html) module"]
pub struct IFLAG1_SPEC;
impl crate::RegisterSpec for IFLAG1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [iflag1::R](R) reader structure"]
impl crate::Readable for IFLAG1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [iflag1::W](W) writer structure"]
impl crate::Writable for IFLAG1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xffff;
}
#[doc = "`reset()` method sets IFLAG1 to value 0"]
impl crate::Resettable for IFLAG1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CTRL2 (rw) register accessor: an alias for `Reg<CTRL2_SPEC>`"]
pub type CTRL2 = crate::Reg<ctrl2::CTRL2_SPEC>;
#[doc = "Control 2 register"]
pub mod ctrl2 {
#[doc = "Register `CTRL2` reader"]
pub struct R(crate::R<CTRL2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CTRL2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CTRL2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CTRL2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CTRL2` writer"]
pub struct W(crate::W<CTRL2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CTRL2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CTRL2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CTRL2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EACEN` reader - "]
pub type EACEN_R = crate::BitReader<bool>;
#[doc = "Field `EACEN` writer - "]
pub type EACEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL2_SPEC, bool, O>;
#[doc = "Field `RRS` reader - "]
pub type RRS_R = crate::BitReader<bool>;
#[doc = "Field `RRS` writer - "]
pub type RRS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL2_SPEC, bool, O>;
#[doc = "Field `MRP` reader - "]
pub type MRP_R = crate::BitReader<bool>;
#[doc = "Field `MRP` writer - "]
pub type MRP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL2_SPEC, bool, O>;
#[doc = "Field `TASD` reader - "]
pub type TASD_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TASD` writer - "]
pub type TASD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL2_SPEC, u8, u8, 5, O>;
#[doc = "Field `RFFN` reader - "]
pub type RFFN_R = crate::FieldReader<u8, u8>;
#[doc = "Field `RFFN` writer - "]
pub type RFFN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL2_SPEC, u8, u8, 4, O>;
#[doc = "Field `BOFFDONEMSK` reader - "]
pub type BOFFDONEMSK_R = crate::BitReader<bool>;
#[doc = "Field `BOFFDONEMSK` writer - "]
pub type BOFFDONEMSK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL2_SPEC, bool, O>;
impl R {
#[doc = "Bit 16"]
#[inline(always)]
pub fn eacen(&self) -> EACEN_R {
EACEN_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn rrs(&self) -> RRS_R {
RRS_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn mrp(&self) -> MRP_R {
MRP_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bits 19:23"]
#[inline(always)]
pub fn tasd(&self) -> TASD_R {
TASD_R::new(((self.bits >> 19) & 0x1f) as u8)
}
#[doc = "Bits 24:27"]
#[inline(always)]
pub fn rffn(&self) -> RFFN_R {
RFFN_R::new(((self.bits >> 24) & 0x0f) as u8)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn boffdonemsk(&self) -> BOFFDONEMSK_R {
BOFFDONEMSK_R::new(((self.bits >> 30) & 1) != 0)
}
}
impl W {
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn eacen(&mut self) -> EACEN_W<16> {
EACEN_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn rrs(&mut self) -> RRS_W<17> {
RRS_W::new(self)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn mrp(&mut self) -> MRP_W<18> {
MRP_W::new(self)
}
#[doc = "Bits 19:23"]
#[inline(always)]
#[must_use]
pub fn tasd(&mut self) -> TASD_W<19> {
TASD_W::new(self)
}
#[doc = "Bits 24:27"]
#[inline(always)]
#[must_use]
pub fn rffn(&mut self) -> RFFN_W<24> {
RFFN_W::new(self)
}
#[doc = "Bit 30"]
#[inline(always)]
#[must_use]
pub fn boffdonemsk(&mut self) -> BOFFDONEMSK_W<30> {
BOFFDONEMSK_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Control 2 register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl2](index.html) module"]
pub struct CTRL2_SPEC;
impl crate::RegisterSpec for CTRL2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ctrl2::R](R) reader structure"]
impl crate::Readable for CTRL2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ctrl2::W](W) writer structure"]
impl crate::Writable for CTRL2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CTRL2 to value 0"]
impl crate::Resettable for CTRL2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ESR2 (r) register accessor: an alias for `Reg<ESR2_SPEC>`"]
pub type ESR2 = crate::Reg<esr2::ESR2_SPEC>;
#[doc = "Error and status 2 register"]
pub mod esr2 {
#[doc = "Register `ESR2` reader"]
pub struct R(crate::R<ESR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ESR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ESR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ESR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `IMB` reader - "]
pub type IMB_R = crate::BitReader<bool>;
#[doc = "Field `VPS` reader - "]
pub type VPS_R = crate::BitReader<bool>;
#[doc = "Field `LPTM` reader - "]
pub type LPTM_R = crate::FieldReader<u8, u8>;
impl R {
#[doc = "Bit 13"]
#[inline(always)]
pub fn imb(&self) -> IMB_R {
IMB_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn vps(&self) -> VPS_R {
VPS_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bits 16:22"]
#[inline(always)]
pub fn lptm(&self) -> LPTM_R {
LPTM_R::new(((self.bits >> 16) & 0x7f) as u8)
}
}
#[doc = "Error and status 2 register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [esr2](index.html) module"]
pub struct ESR2_SPEC;
impl crate::RegisterSpec for ESR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [esr2::R](R) reader structure"]
impl crate::Readable for ESR2_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets ESR2 to value 0"]
impl crate::Resettable for ESR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CRCR (r) register accessor: an alias for `Reg<CRCR_SPEC>`"]
pub type CRCR = crate::Reg<crcr::CRCR_SPEC>;
#[doc = "CRC register"]
pub mod crcr {
#[doc = "Register `CRCR` reader"]
pub struct R(crate::R<CRCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CRCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CRCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CRCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `TXCRC` reader - "]
pub type TXCRC_R = crate::FieldReader<u16, u16>;
#[doc = "Field `MBCRC` reader - "]
pub type MBCRC_R = crate::FieldReader<u8, u8>;
impl R {
#[doc = "Bits 0:14"]
#[inline(always)]
pub fn txcrc(&self) -> TXCRC_R {
TXCRC_R::new((self.bits & 0x7fff) as u16)
}
#[doc = "Bits 16:22"]
#[inline(always)]
pub fn mbcrc(&self) -> MBCRC_R {
MBCRC_R::new(((self.bits >> 16) & 0x7f) as u8)
}
}
#[doc = "CRC register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcr](index.html) module"]
pub struct CRCR_SPEC;
impl crate::RegisterSpec for CRCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [crcr::R](R) reader structure"]
impl crate::Readable for CRCR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets CRCR to value 0"]
impl crate::Resettable for CRCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RXFGMASK (rw) register accessor: an alias for `Reg<RXFGMASK_SPEC>`"]
pub type RXFGMASK = crate::Reg<rxfgmask::RXFGMASK_SPEC>;
#[doc = "Rx FIFO global mask register"]
pub mod rxfgmask {
#[doc = "Register `RXFGMASK` reader"]
pub struct R(crate::R<RXFGMASK_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RXFGMASK_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RXFGMASK_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RXFGMASK_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `RXFGMASK` writer"]
pub struct W(crate::W<RXFGMASK_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<RXFGMASK_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<RXFGMASK_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<RXFGMASK_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `FGM` reader - "]
pub type FGM_R = crate::FieldReader<u32, u32>;
#[doc = "Field `FGM` writer - "]
pub type FGM_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, RXFGMASK_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn fgm(&self) -> FGM_R {
FGM_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn fgm(&mut self) -> FGM_W<0> {
FGM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Rx FIFO global mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxfgmask](index.html) module"]
pub struct RXFGMASK_SPEC;
impl crate::RegisterSpec for RXFGMASK_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rxfgmask::R](R) reader structure"]
impl crate::Readable for RXFGMASK_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [rxfgmask::W](W) writer structure"]
impl crate::Writable for RXFGMASK_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets RXFGMASK to value 0"]
impl crate::Resettable for RXFGMASK_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RXFIR (r) register accessor: an alias for `Reg<RXFIR_SPEC>`"]
pub type RXFIR = crate::Reg<rxfir::RXFIR_SPEC>;
#[doc = "Rx FIFO information register"]
pub mod rxfir {
#[doc = "Register `RXFIR` reader"]
pub struct R(crate::R<RXFIR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RXFIR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RXFIR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RXFIR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `IDHIT` reader - "]
pub type IDHIT_R = crate::FieldReader<u16, u16>;
impl R {
#[doc = "Bits 0:8"]
#[inline(always)]
pub fn idhit(&self) -> IDHIT_R {
IDHIT_R::new((self.bits & 0x01ff) as u16)
}
}
#[doc = "Rx FIFO information register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxfir](index.html) module"]
pub struct RXFIR_SPEC;
impl crate::RegisterSpec for RXFIR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rxfir::R](R) reader structure"]
impl crate::Readable for RXFIR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets RXFIR to value 0"]
impl crate::Resettable for RXFIR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CBT (rw) register accessor: an alias for `Reg<CBT_SPEC>`"]
pub type CBT = crate::Reg<cbt::CBT_SPEC>;
#[doc = "CAN bit timing register"]
pub mod cbt {
#[doc = "Register `CBT` reader"]
pub struct R(crate::R<CBT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CBT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CBT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CBT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CBT` writer"]
pub struct W(crate::W<CBT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CBT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CBT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CBT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EPSEG2` reader - "]
pub type EPSEG2_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EPSEG2` writer - "]
pub type EPSEG2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CBT_SPEC, u8, u8, 5, O>;
#[doc = "Field `EPSEG1` reader - "]
pub type EPSEG1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EPSEG1` writer - "]
pub type EPSEG1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CBT_SPEC, u8, u8, 5, O>;
#[doc = "Field `EPROPSEG` reader - "]
pub type EPROPSEG_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EPROPSEG` writer - "]
pub type EPROPSEG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CBT_SPEC, u8, u8, 6, O>;
#[doc = "Field `ERJW` reader - "]
pub type ERJW_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ERJW` writer - "]
pub type ERJW_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CBT_SPEC, u8, u8, 5, O>;
#[doc = "Field `EPRESDIV` reader - "]
pub type EPRESDIV_R = crate::FieldReader<u16, u16>;
#[doc = "Field `EPRESDIV` writer - "]
pub type EPRESDIV_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CBT_SPEC, u16, u16, 10, O>;
#[doc = "Field `BTF` reader - "]
pub type BTF_R = crate::BitReader<bool>;
#[doc = "Field `BTF` writer - "]
pub type BTF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CBT_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:4"]
#[inline(always)]
pub fn epseg2(&self) -> EPSEG2_R {
EPSEG2_R::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 5:9"]
#[inline(always)]
pub fn epseg1(&self) -> EPSEG1_R {
EPSEG1_R::new(((self.bits >> 5) & 0x1f) as u8)
}
#[doc = "Bits 10:15"]
#[inline(always)]
pub fn epropseg(&self) -> EPROPSEG_R {
EPROPSEG_R::new(((self.bits >> 10) & 0x3f) as u8)
}
#[doc = "Bits 16:20"]
#[inline(always)]
pub fn erjw(&self) -> ERJW_R {
ERJW_R::new(((self.bits >> 16) & 0x1f) as u8)
}
#[doc = "Bits 21:30"]
#[inline(always)]
pub fn epresdiv(&self) -> EPRESDIV_R {
EPRESDIV_R::new(((self.bits >> 21) & 0x03ff) as u16)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn btf(&self) -> BTF_R {
BTF_R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4"]
#[inline(always)]
#[must_use]
pub fn epseg2(&mut self) -> EPSEG2_W<0> {
EPSEG2_W::new(self)
}
#[doc = "Bits 5:9"]
#[inline(always)]
#[must_use]
pub fn epseg1(&mut self) -> EPSEG1_W<5> {
EPSEG1_W::new(self)
}
#[doc = "Bits 10:15"]
#[inline(always)]
#[must_use]
pub fn epropseg(&mut self) -> EPROPSEG_W<10> {
EPROPSEG_W::new(self)
}
#[doc = "Bits 16:20"]
#[inline(always)]
#[must_use]
pub fn erjw(&mut self) -> ERJW_W<16> {
ERJW_W::new(self)
}
#[doc = "Bits 21:30"]
#[inline(always)]
#[must_use]
pub fn epresdiv(&mut self) -> EPRESDIV_W<21> {
EPRESDIV_W::new(self)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn btf(&mut self) -> BTF_W<31> {
BTF_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "CAN bit timing register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cbt](index.html) module"]
pub struct CBT_SPEC;
impl crate::RegisterSpec for CBT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cbt::R](R) reader structure"]
impl crate::Readable for CBT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cbt::W](W) writer structure"]
impl crate::Writable for CBT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CBT to value 0"]
impl crate::Resettable for CBT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CS0 (rw) register accessor: an alias for `Reg<CS0_SPEC>`"]
pub type CS0 = crate::Reg<cs0::CS0_SPEC>;
#[doc = "Message Buffer 0 CS Register..Message Buffer 15 CS Register"]
pub mod cs0 {
#[doc = "Register `CS0` reader"]
pub struct R(crate::R<CS0_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CS0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CS0_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CS0_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CS0` writer"]
pub struct W(crate::W<CS0_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CS0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CS0_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CS0_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TIMESTAMP` reader - "]
pub type TIMESTAMP_R = crate::FieldReader<u16, u16>;
#[doc = "Field `TIMESTAMP` writer - "]
pub type TIMESTAMP_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CS0_SPEC, u16, u16, 16, O>;
#[doc = "Field `DLC` reader - "]
pub type DLC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DLC` writer - "]
pub type DLC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS0_SPEC, u8, u8, 4, O>;
#[doc = "Field `RTR` reader - "]
pub type RTR_R = crate::BitReader<bool>;
#[doc = "Field `RTR` writer - "]
pub type RTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS0_SPEC, bool, O>;
#[doc = "Field `IDE` reader - "]
pub type IDE_R = crate::BitReader<bool>;
#[doc = "Field `IDE` writer - "]
pub type IDE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS0_SPEC, bool, O>;
#[doc = "Field `SRR` reader - "]
pub type SRR_R = crate::BitReader<bool>;
#[doc = "Field `SRR` writer - "]
pub type SRR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CS0_SPEC, bool, O>;
#[doc = "Field `CODE` reader - "]
pub type CODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CODE` writer - "]
pub type CODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CS0_SPEC, u8, u8, 4, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn timestamp(&self) -> TIMESTAMP_R {
TIMESTAMP_R::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:19"]
#[inline(always)]
pub fn dlc(&self) -> DLC_R {
DLC_R::new(((self.bits >> 16) & 0x0f) as u8)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn rtr(&self) -> RTR_R {
RTR_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn ide(&self) -> IDE_R {
IDE_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn srr(&self) -> SRR_R {
SRR_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bits 24:27"]
#[inline(always)]
pub fn code(&self) -> CODE_R {
CODE_R::new(((self.bits >> 24) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn timestamp(&mut self) -> TIMESTAMP_W<0> {
TIMESTAMP_W::new(self)
}
#[doc = "Bits 16:19"]
#[inline(always)]
#[must_use]
pub fn dlc(&mut self) -> DLC_W<16> {
DLC_W::new(self)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn rtr(&mut self) -> RTR_W<20> {
RTR_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn ide(&mut self) -> IDE_W<21> {
IDE_W::new(self)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn srr(&mut self) -> SRR_W<22> {
SRR_W::new(self)
}
#[doc = "Bits 24:27"]
#[inline(always)]
#[must_use]
pub fn code(&mut self) -> CODE_W<24> {
CODE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Message Buffer 0 CS Register..Message Buffer 15 CS Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cs0](index.html) module"]
pub struct CS0_SPEC;
impl crate::RegisterSpec for CS0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cs0::R](R) reader structure"]
impl crate::Readable for CS0_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cs0::W](W) writer structure"]
impl crate::Writable for CS0_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CS0 to value 0"]
impl crate::Resettable for CS0_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ID0 (rw) register accessor: an alias for `Reg<ID0_SPEC>`"]
pub type ID0 = crate::Reg<id0::ID0_SPEC>;
#[doc = "Message Buffer 0 ID Register..Message Buffer 15 ID Register"]
pub mod id0 {
#[doc = "Register `ID0` reader"]
pub struct R(crate::R<ID0_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ID0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ID0_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ID0_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ID0` writer"]
pub struct W(crate::W<ID0_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ID0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ID0_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ID0_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EXT` reader - "]
pub type EXT_R = crate::FieldReader<u32, u32>;
#[doc = "Field `EXT` writer - "]
pub type EXT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ID0_SPEC, u32, u32, 18, O>;
#[doc = "Field `STD` reader - "]
pub type STD_R = crate::FieldReader<u16, u16>;
#[doc = "Field `STD` writer - "]
pub type STD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ID0_SPEC, u16, u16, 11, O>;
#[doc = "Field `PRIO` reader - "]
pub type PRIO_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PRIO` writer - "]
pub type PRIO_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ID0_SPEC, u8, u8, 3, O>;
impl R {
#[doc = "Bits 0:17"]
#[inline(always)]
pub fn ext(&self) -> EXT_R {
EXT_R::new(self.bits & 0x0003_ffff)
}
#[doc = "Bits 18:28"]
#[inline(always)]
pub fn std(&self) -> STD_R {
STD_R::new(((self.bits >> 18) & 0x07ff) as u16)
}
#[doc = "Bits 29:31"]
#[inline(always)]
pub fn prio(&self) -> PRIO_R {
PRIO_R::new(((self.bits >> 29) & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:17"]
#[inline(always)]
#[must_use]
pub fn ext(&mut self) -> EXT_W<0> {
EXT_W::new(self)
}
#[doc = "Bits 18:28"]
#[inline(always)]
#[must_use]
pub fn std(&mut self) -> STD_W<18> {
STD_W::new(self)
}
#[doc = "Bits 29:31"]
#[inline(always)]
#[must_use]
pub fn prio(&mut self) -> PRIO_W<29> {
PRIO_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Message Buffer 0 ID Register..Message Buffer 15 ID Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [id0](index.html) module"]
pub struct ID0_SPEC;
impl crate::RegisterSpec for ID0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [id0::R](R) reader structure"]
impl crate::Readable for ID0_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [id0::W](W) writer structure"]
impl crate::Writable for ID0_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ID0 to value 0"]
impl crate::Resettable for ID0_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "WORD0 (rw) register accessor: an alias for `Reg<WORD0_SPEC>`"]
pub type WORD0 = crate::Reg<word0::WORD0_SPEC>;
#[doc = "Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register"]
pub mod word0 {
#[doc = "Register `WORD0` reader"]
pub struct R(crate::R<WORD0_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<WORD0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<WORD0_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<WORD0_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `WORD0` writer"]
pub struct W(crate::W<WORD0_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<WORD0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<WORD0_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<WORD0_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `BYTE3` reader - "]
pub type BYTE3_R = crate::FieldReader<u8, u8>;
#[doc = "Field `BYTE3` writer - "]
pub type BYTE3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WORD0_SPEC, u8, u8, 8, O>;
#[doc = "Field `BYTE2` reader - "]
pub type BYTE2_R = crate::FieldReader<u8, u8>;
#[doc = "Field `BYTE2` writer - "]
pub type BYTE2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WORD0_SPEC, u8, u8, 8, O>;
#[doc = "Field `BYTE1` reader - "]
pub type BYTE1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `BYTE1` writer - "]
pub type BYTE1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WORD0_SPEC, u8, u8, 6, O>;
#[doc = "Field `BYTE0` reader - "]
pub type BYTE0_R = crate::FieldReader<u8, u8>;
#[doc = "Field `BYTE0` writer - "]
pub type BYTE0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WORD0_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn byte3(&self) -> BYTE3_R {
BYTE3_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15"]
#[inline(always)]
pub fn byte2(&self) -> BYTE2_R {
BYTE2_R::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:21"]
#[inline(always)]
pub fn byte1(&self) -> BYTE1_R {
BYTE1_R::new(((self.bits >> 16) & 0x3f) as u8)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn byte0(&self) -> BYTE0_R {
BYTE0_R::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn byte3(&mut self) -> BYTE3_W<0> {
BYTE3_W::new(self)
}
#[doc = "Bits 8:15"]
#[inline(always)]
#[must_use]
pub fn byte2(&mut self) -> BYTE2_W<8> {
BYTE2_W::new(self)
}
#[doc = "Bits 16:21"]
#[inline(always)]
#[must_use]
pub fn byte1(&mut self) -> BYTE1_W<16> {
BYTE1_W::new(self)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn byte0(&mut self) -> BYTE0_W<24> {
BYTE0_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [word0](index.html) module"]
pub struct WORD0_SPEC;
impl crate::RegisterSpec for WORD0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [word0::R](R) reader structure"]
impl crate::Readable for WORD0_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [word0::W](W) writer structure"]
impl crate::Writable for WORD0_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets WORD0 to value 0"]
impl crate::Resettable for WORD0_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "WORD1 (rw) register accessor: an alias for `Reg<WORD1_SPEC>`"]
pub type WORD1 = crate::Reg<word1::WORD1_SPEC>;
#[doc = "Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register"]
pub mod word1 {
#[doc = "Register `WORD1` reader"]
pub struct R(crate::R<WORD1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<WORD1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<WORD1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<WORD1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `WORD1` writer"]
pub struct W(crate::W<WORD1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<WORD1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<WORD1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<WORD1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `BYTE7` reader - "]
pub type BYTE7_R = crate::FieldReader<u8, u8>;
#[doc = "Field `BYTE7` writer - "]
pub type BYTE7_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WORD1_SPEC, u8, u8, 8, O>;
#[doc = "Field `BYTE6` reader - "]
pub type BYTE6_R = crate::FieldReader<u8, u8>;
#[doc = "Field `BYTE6` writer - "]
pub type BYTE6_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WORD1_SPEC, u8, u8, 8, O>;
#[doc = "Field `BYTE5` reader - "]
pub type BYTE5_R = crate::FieldReader<u8, u8>;
#[doc = "Field `BYTE5` writer - "]
pub type BYTE5_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WORD1_SPEC, u8, u8, 6, O>;
#[doc = "Field `BYTE4` reader - "]
pub type BYTE4_R = crate::FieldReader<u8, u8>;
#[doc = "Field `BYTE4` writer - "]
pub type BYTE4_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WORD1_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn byte7(&self) -> BYTE7_R {
BYTE7_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15"]
#[inline(always)]
pub fn byte6(&self) -> BYTE6_R {
BYTE6_R::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:21"]
#[inline(always)]
pub fn byte5(&self) -> BYTE5_R {
BYTE5_R::new(((self.bits >> 16) & 0x3f) as u8)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn byte4(&self) -> BYTE4_R {
BYTE4_R::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn byte7(&mut self) -> BYTE7_W<0> {
BYTE7_W::new(self)
}
#[doc = "Bits 8:15"]
#[inline(always)]
#[must_use]
pub fn byte6(&mut self) -> BYTE6_W<8> {
BYTE6_W::new(self)
}
#[doc = "Bits 16:21"]
#[inline(always)]
#[must_use]
pub fn byte5(&mut self) -> BYTE5_W<16> {
BYTE5_W::new(self)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn byte4(&mut self) -> BYTE4_W<24> {
BYTE4_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [word1](index.html) module"]
pub struct WORD1_SPEC;
impl crate::RegisterSpec for WORD1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [word1::R](R) reader structure"]
impl crate::Readable for WORD1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [word1::W](W) writer structure"]
impl crate::Writable for WORD1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets WORD1 to value 0"]
impl crate::Resettable for WORD1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
pub use cs0 as cs1;
pub use cs0 as cs2;
pub use cs0 as cs3;
pub use cs0 as cs4;
pub use cs0 as cs5;
pub use cs0 as cs6;
pub use cs0 as cs7;
pub use cs0 as cs8;
pub use cs0 as cs9;
pub use cs0 as cs10;
pub use cs0 as cs11;
pub use cs0 as cs12;
pub use cs0 as cs13;
pub use cs0 as cs14;
pub use cs0 as cs15;
pub use id0 as id1;
pub use id0 as id2;
pub use id0 as id3;
pub use id0 as id4;
pub use id0 as id5;
pub use id0 as id6;
pub use id0 as id7;
pub use id0 as id8;
pub use id0 as id9;
pub use id0 as id10;
pub use id0 as id11;
pub use id0 as id12;
pub use id0 as id13;
pub use id0 as id14;
pub use id0 as id15;
pub use word0 as word01;
pub use word0 as word02;
pub use word0 as word03;
pub use word0 as word04;
pub use word0 as word05;
pub use word0 as word06;
pub use word0 as word07;
pub use word0 as word08;
pub use word0 as word09;
pub use word0 as word010;
pub use word0 as word011;
pub use word0 as word012;
pub use word0 as word013;
pub use word0 as word014;
pub use word0 as word015;
pub use word1 as word11;
pub use word1 as word12;
pub use word1 as word13;
pub use word1 as word14;
pub use word1 as word15;
pub use word1 as word16;
pub use word1 as word17;
pub use word1 as word18;
pub use word1 as word19;
pub use word1 as word110;
pub use word1 as word111;
pub use word1 as word112;
pub use word1 as word113;
pub use word1 as word114;
pub use word1 as word115;
pub use CS0 as CS1;
pub use CS0 as CS2;
pub use CS0 as CS3;
pub use CS0 as CS4;
pub use CS0 as CS5;
pub use CS0 as CS6;
pub use CS0 as CS7;
pub use CS0 as CS8;
pub use CS0 as CS9;
pub use CS0 as CS10;
pub use CS0 as CS11;
pub use CS0 as CS12;
pub use CS0 as CS13;
pub use CS0 as CS14;
pub use CS0 as CS15;
pub use ID0 as ID1;
pub use ID0 as ID2;
pub use ID0 as ID3;
pub use ID0 as ID4;
pub use ID0 as ID5;
pub use ID0 as ID6;
pub use ID0 as ID7;
pub use ID0 as ID8;
pub use ID0 as ID9;
pub use ID0 as ID10;
pub use ID0 as ID11;
pub use ID0 as ID12;
pub use ID0 as ID13;
pub use ID0 as ID14;
pub use ID0 as ID15;
pub use WORD0 as WORD01;
pub use WORD0 as WORD02;
pub use WORD0 as WORD03;
pub use WORD0 as WORD04;
pub use WORD0 as WORD05;
pub use WORD0 as WORD06;
pub use WORD0 as WORD07;
pub use WORD0 as WORD08;
pub use WORD0 as WORD09;
pub use WORD0 as WORD010;
pub use WORD0 as WORD011;
pub use WORD0 as WORD012;
pub use WORD0 as WORD013;
pub use WORD0 as WORD014;
pub use WORD0 as WORD015;
pub use WORD1 as WORD11;
pub use WORD1 as WORD12;
pub use WORD1 as WORD13;
pub use WORD1 as WORD14;
pub use WORD1 as WORD15;
pub use WORD1 as WORD16;
pub use WORD1 as WORD17;
pub use WORD1 as WORD18;
pub use WORD1 as WORD19;
pub use WORD1 as WORD110;
pub use WORD1 as WORD111;
pub use WORD1 as WORD112;
pub use WORD1 as WORD113;
pub use WORD1 as WORD114;
pub use WORD1 as WORD115;
#[doc = "RXIMR0 (rw) register accessor: an alias for `Reg<RXIMR0_SPEC>`"]
pub type RXIMR0 = crate::Reg<rximr0::RXIMR0_SPEC>;
#[doc = "R0 single mask register"]
pub mod rximr0 {
#[doc = "Register `RXIMR0` reader"]
pub struct R(crate::R<RXIMR0_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RXIMR0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RXIMR0_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RXIMR0_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `RXIMR0` writer"]
pub struct W(crate::W<RXIMR0_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<RXIMR0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<RXIMR0_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<RXIMR0_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MI` reader - "]
pub type MI_R = crate::FieldReader<u32, u32>;
#[doc = "Field `MI` writer - "]
pub type MI_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RXIMR0_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn mi(&self) -> MI_R {
MI_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn mi(&mut self) -> MI_W<0> {
MI_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "R0 single mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rximr0](index.html) module"]
pub struct RXIMR0_SPEC;
impl crate::RegisterSpec for RXIMR0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rximr0::R](R) reader structure"]
impl crate::Readable for RXIMR0_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [rximr0::W](W) writer structure"]
impl crate::Writable for RXIMR0_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets RXIMR0 to value 0"]
impl crate::Resettable for RXIMR0_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
pub use rximr0 as rximr1;
pub use rximr0 as rximr2;
pub use rximr0 as rximr3;
pub use rximr0 as rximr4;
pub use rximr0 as rximr5;
pub use rximr0 as rximr6;
pub use rximr0 as rximr7;
pub use rximr0 as rximr8;
pub use rximr0 as rximr9;
pub use rximr0 as rximr10;
pub use rximr0 as rximr11;
pub use rximr0 as rximr12;
pub use rximr0 as rximr13;
pub use rximr0 as rximr14;
pub use rximr0 as rximr15;
pub use RXIMR0 as RXIMR1;
pub use RXIMR0 as RXIMR2;
pub use RXIMR0 as RXIMR3;
pub use RXIMR0 as RXIMR4;
pub use RXIMR0 as RXIMR5;
pub use RXIMR0 as RXIMR6;
pub use RXIMR0 as RXIMR7;
pub use RXIMR0 as RXIMR8;
pub use RXIMR0 as RXIMR9;
pub use RXIMR0 as RXIMR10;
pub use RXIMR0 as RXIMR11;
pub use RXIMR0 as RXIMR12;
pub use RXIMR0 as RXIMR13;
pub use RXIMR0 as RXIMR14;
pub use RXIMR0 as RXIMR15;
}
#[doc = "FLEXCAN2"]
pub struct FLEXCAN2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for FLEXCAN2 {}
impl FLEXCAN2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const flexcan1::RegisterBlock = 0x4001_8000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const flexcan1::RegisterBlock {
Self::PTR
}
}
impl Deref for FLEXCAN2 {
type Target = flexcan1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for FLEXCAN2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FLEXCAN2").finish()
}
}
#[doc = "FLEXCAN2"]
pub use self::flexcan1 as flexcan2;
#[doc = "FSMC"]
pub struct FSMC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for FSMC {}
impl FSMC {
#[doc = r"Pointer to the register block"]
pub const PTR: *const fsmc::RegisterBlock = 0xa000_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const fsmc::RegisterBlock {
Self::PTR
}
}
impl Deref for FSMC {
type Target = fsmc::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for FSMC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("FSMC").finish()
}
}
#[doc = "FSMC"]
pub mod fsmc {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
_reserved0: [u8; 0x54],
#[doc = "0x54 - Memory Mask Register 0"]
pub smskr0: SMSKR0,
#[doc = "0x58 - Memory Mask Register 0"]
pub smskr1: SMSKR1,
#[doc = "0x5c - Memory Mask Register 0"]
pub smskr2: SMSKR2,
#[doc = "0x60 - Memory Mask Register 0"]
pub smskr3: SMSKR3,
_reserved4: [u8; 0x30],
#[doc = "0x94 - Memory Timing Register 0"]
pub smtmgr_set0: SMTMGR_SET0,
#[doc = "0x98 - Memory Timing Register 0"]
pub smtmgr_set1: SMTMGR_SET1,
#[doc = "0x9c - Memory Timing Register 0"]
pub smtmgr_set2: SMTMGR_SET2,
_reserved7: [u8; 0x04],
#[doc = "0xa4 - memory control register"]
pub smctlr: SMCTLR,
}
#[doc = "SMSKR0 (rw) register accessor: an alias for `Reg<SMSKR0_SPEC>`"]
pub type SMSKR0 = crate::Reg<smskr0::SMSKR0_SPEC>;
#[doc = "Memory Mask Register 0"]
pub mod smskr0 {
#[doc = "Register `SMSKR0` reader"]
pub struct R(crate::R<SMSKR0_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SMSKR0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SMSKR0_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SMSKR0_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SMSKR0` writer"]
pub struct W(crate::W<SMSKR0_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SMSKR0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SMSKR0_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SMSKR0_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MEM_SIZE` reader - "]
pub type MEM_SIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MEM_SIZE` writer - "]
pub type MEM_SIZE_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SMSKR0_SPEC, u8, u8, 5, O>;
#[doc = "Field `MEM_TYPE` reader - "]
pub type MEM_TYPE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MEM_TYPE` writer - "]
pub type MEM_TYPE_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SMSKR0_SPEC, u8, u8, 3, O>;
#[doc = "Field `REG_SELECT` reader - "]
pub type REG_SELECT_R = crate::FieldReader<u8, u8>;
#[doc = "Field `REG_SELECT` writer - "]
pub type REG_SELECT_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SMSKR0_SPEC, u8, u8, 3, O>;
impl R {
#[doc = "Bits 0:4"]
#[inline(always)]
pub fn mem_size(&self) -> MEM_SIZE_R {
MEM_SIZE_R::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 5:7"]
#[inline(always)]
pub fn mem_type(&self) -> MEM_TYPE_R {
MEM_TYPE_R::new(((self.bits >> 5) & 7) as u8)
}
#[doc = "Bits 8:10"]
#[inline(always)]
pub fn reg_select(&self) -> REG_SELECT_R {
REG_SELECT_R::new(((self.bits >> 8) & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:4"]
#[inline(always)]
#[must_use]
pub fn mem_size(&mut self) -> MEM_SIZE_W<0> {
MEM_SIZE_W::new(self)
}
#[doc = "Bits 5:7"]
#[inline(always)]
#[must_use]
pub fn mem_type(&mut self) -> MEM_TYPE_W<5> {
MEM_TYPE_W::new(self)
}
#[doc = "Bits 8:10"]
#[inline(always)]
#[must_use]
pub fn reg_select(&mut self) -> REG_SELECT_W<8> {
REG_SELECT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Memory Mask Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smskr0](index.html) module"]
pub struct SMSKR0_SPEC;
impl crate::RegisterSpec for SMSKR0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [smskr0::R](R) reader structure"]
impl crate::Readable for SMSKR0_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [smskr0::W](W) writer structure"]
impl crate::Writable for SMSKR0_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SMSKR0 to value 0x024b"]
impl crate::Resettable for SMSKR0_SPEC {
const RESET_VALUE: Self::Ux = 0x024b;
}
}
pub use smskr0 as smskr1;
pub use smskr0 as smskr2;
pub use smskr0 as smskr3;
pub use SMSKR0 as SMSKR1;
pub use SMSKR0 as SMSKR2;
pub use SMSKR0 as SMSKR3;
#[doc = "SMTMGR_SET0 (rw) register accessor: an alias for `Reg<SMTMGR_SET0_SPEC>`"]
pub type SMTMGR_SET0 = crate::Reg<smtmgr_set0::SMTMGR_SET0_SPEC>;
#[doc = "Memory Timing Register 0"]
pub mod smtmgr_set0 {
#[doc = "Register `SMTMGR_SET0` reader"]
pub struct R(crate::R<SMTMGR_SET0_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SMTMGR_SET0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SMTMGR_SET0_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SMTMGR_SET0_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SMTMGR_SET0` writer"]
pub struct W(crate::W<SMTMGR_SET0_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SMTMGR_SET0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SMTMGR_SET0_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SMTMGR_SET0_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `t_rc` reader - "]
pub type T_RC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `t_rc` writer - "]
pub type T_RC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SMTMGR_SET0_SPEC, u8, u8, 6, O>;
#[doc = "Field `t_as` reader - "]
pub type T_AS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `t_as` writer - "]
pub type T_AS_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SMTMGR_SET0_SPEC, u8, u8, 2, O>;
#[doc = "Field `t_wr` reader - "]
pub type T_WR_R = crate::FieldReader<u8, u8>;
#[doc = "Field `t_wr` writer - "]
pub type T_WR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SMTMGR_SET0_SPEC, u8, u8, 2, O>;
#[doc = "Field `t_wp` reader - "]
pub type T_WP_R = crate::FieldReader<u8, u8>;
#[doc = "Field `t_wp` writer - "]
pub type T_WP_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SMTMGR_SET0_SPEC, u8, u8, 6, O>;
#[doc = "Field `READY_MODE` reader - "]
pub type READY_MODE_R = crate::BitReader<bool>;
#[doc = "Field `READY_MODE` writer - "]
pub type READY_MODE_W<'a, const O: u8> =
crate::BitWriter<'a, u32, SMTMGR_SET0_SPEC, bool, O>;
#[doc = "Field `SM_READ_PIPE` reader - "]
pub type SM_READ_PIPE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SM_READ_PIPE` writer - "]
pub type SM_READ_PIPE_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SMTMGR_SET0_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn t_rc(&self) -> T_RC_R {
T_RC_R::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn t_as(&self) -> T_AS_R {
T_AS_R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn t_wr(&self) -> T_WR_R {
T_WR_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:15"]
#[inline(always)]
pub fn t_wp(&self) -> T_WP_R {
T_WP_R::new(((self.bits >> 10) & 0x3f) as u8)
}
#[doc = "Bit 26"]
#[inline(always)]
pub fn ready_mode(&self) -> READY_MODE_R {
READY_MODE_R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bits 28:29"]
#[inline(always)]
pub fn sm_read_pipe(&self) -> SM_READ_PIPE_R {
SM_READ_PIPE_R::new(((self.bits >> 28) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn t_rc(&mut self) -> T_RC_W<0> {
T_RC_W::new(self)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn t_as(&mut self) -> T_AS_W<6> {
T_AS_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn t_wr(&mut self) -> T_WR_W<8> {
T_WR_W::new(self)
}
#[doc = "Bits 10:15"]
#[inline(always)]
#[must_use]
pub fn t_wp(&mut self) -> T_WP_W<10> {
T_WP_W::new(self)
}
#[doc = "Bit 26"]
#[inline(always)]
#[must_use]
pub fn ready_mode(&mut self) -> READY_MODE_W<26> {
READY_MODE_W::new(self)
}
#[doc = "Bits 28:29"]
#[inline(always)]
#[must_use]
pub fn sm_read_pipe(&mut self) -> SM_READ_PIPE_W<28> {
SM_READ_PIPE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Memory Timing Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smtmgr_set0](index.html) module"]
pub struct SMTMGR_SET0_SPEC;
impl crate::RegisterSpec for SMTMGR_SET0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [smtmgr_set0::R](R) reader structure"]
impl crate::Readable for SMTMGR_SET0_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [smtmgr_set0::W](W) writer structure"]
impl crate::Writable for SMTMGR_SET0_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SMTMGR_SET0 to value 0x0401_0441"]
impl crate::Resettable for SMTMGR_SET0_SPEC {
const RESET_VALUE: Self::Ux = 0x0401_0441;
}
}
pub use smtmgr_set0 as smtmgr_set1;
pub use smtmgr_set0 as smtmgr_set2;
pub use SMTMGR_SET0 as SMTMGR_SET1;
pub use SMTMGR_SET0 as SMTMGR_SET2;
#[doc = "SMCTLR (rw) register accessor: an alias for `Reg<SMCTLR_SPEC>`"]
pub type SMCTLR = crate::Reg<smctlr::SMCTLR_SPEC>;
#[doc = "memory control register"]
pub mod smctlr {
#[doc = "Register `SMCTLR` reader"]
pub struct R(crate::R<SMCTLR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SMCTLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SMCTLR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SMCTLR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SMCTLR` writer"]
pub struct W(crate::W<SMCTLR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SMCTLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SMCTLR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SMCTLR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `FLASHRP` reader - "]
pub type FLASHRP_R = crate::BitReader<bool>;
#[doc = "Field `FLASHRP` writer - "]
pub type FLASHRP_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMCTLR_SPEC, bool, O>;
#[doc = "Field `SMDW0` reader - "]
pub type SMDW0_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMDW0` writer - "]
pub type SMDW0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SMCTLR_SPEC, u8, u8, 3, O>;
#[doc = "Field `SMDW1` reader - "]
pub type SMDW1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMDW1` writer - "]
pub type SMDW1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SMCTLR_SPEC, u8, u8, 3, O>;
#[doc = "Field `SMDW2` reader - "]
pub type SMDW2_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMDW2` writer - "]
pub type SMDW2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SMCTLR_SPEC, u8, u8, 3, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn flashrp(&self) -> FLASHRP_R {
FLASHRP_R::new((self.bits & 1) != 0)
}
#[doc = "Bits 7:9"]
#[inline(always)]
pub fn smdw0(&self) -> SMDW0_R {
SMDW0_R::new(((self.bits >> 7) & 7) as u8)
}
#[doc = "Bits 10:12"]
#[inline(always)]
pub fn smdw1(&self) -> SMDW1_R {
SMDW1_R::new(((self.bits >> 10) & 7) as u8)
}
#[doc = "Bits 13:15"]
#[inline(always)]
pub fn smdw2(&self) -> SMDW2_R {
SMDW2_R::new(((self.bits >> 13) & 7) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn flashrp(&mut self) -> FLASHRP_W<0> {
FLASHRP_W::new(self)
}
#[doc = "Bits 7:9"]
#[inline(always)]
#[must_use]
pub fn smdw0(&mut self) -> SMDW0_W<7> {
SMDW0_W::new(self)
}
#[doc = "Bits 10:12"]
#[inline(always)]
#[must_use]
pub fn smdw1(&mut self) -> SMDW1_W<10> {
SMDW1_W::new(self)
}
#[doc = "Bits 13:15"]
#[inline(always)]
#[must_use]
pub fn smdw2(&mut self) -> SMDW2_W<13> {
SMDW2_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "memory control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smctlr](index.html) module"]
pub struct SMCTLR_SPEC;
impl crate::RegisterSpec for SMCTLR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [smctlr::R](R) reader structure"]
impl crate::Readable for SMCTLR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [smctlr::W](W) writer structure"]
impl crate::Writable for SMCTLR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SMCTLR to value 0"]
impl crate::Resettable for SMCTLR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "GPIOA"]
pub struct GPIOA {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOA {}
impl GPIOA {
#[doc = r"Pointer to the register block"]
pub const PTR: *const gpioa::RegisterBlock = 0x4004_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const gpioa::RegisterBlock {
Self::PTR
}
}
impl Deref for GPIOA {
type Target = gpioa::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for GPIOA {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOA").finish()
}
}
#[doc = "GPIOA"]
pub mod gpioa {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Port Configuration Low Register"]
pub crl: CRL,
#[doc = "0x04 - Port Configuration High Register"]
pub crh: CRH,
#[doc = "0x08 - Port Input Data Register"]
pub idr: IDR,
#[doc = "0x0c - PORT OUTPUT DATA REGISTER"]
pub odr: ODR,
#[doc = "0x10 - Port Set/Clear Register"]
pub bsrr: BSRR,
#[doc = "0x14 - Port Bit Clear Register"]
pub brr: BRR,
#[doc = "0x18 - Port Configuration Lock Register"]
pub lckr: LCKR,
#[doc = "0x1c - PORT OUTPUT OPEN DRAIN CONTROL REGISTER"]
pub dcr: DCR,
#[doc = "0x20 - Port alternate function low-order register"]
pub afrl: AFRL,
#[doc = "0x24 - Port alternate function high-order register"]
pub afrh: AFRH,
}
#[doc = "CRL (rw) register accessor: an alias for `Reg<CRL_SPEC>`"]
pub type CRL = crate::Reg<crl::CRL_SPEC>;
#[doc = "Port Configuration Low Register"]
pub mod crl {
#[doc = "Register `CRL` reader"]
pub struct R(crate::R<CRL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CRL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CRL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CRL` writer"]
pub struct W(crate::W<CRL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CRL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CRL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MODE0` reader - "]
pub type MODE0_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MODE0` writer - "]
pub type MODE0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRL_SPEC, u8, u8, 2, O>;
#[doc = "Field `CNF0` reader - "]
pub type CNF0_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNF0` writer - "]
pub type CNF0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRL_SPEC, u8, u8, 2, O>;
#[doc = "Field `MODE1` reader - "]
pub type MODE1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MODE1` writer - "]
pub type MODE1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRL_SPEC, u8, u8, 2, O>;
#[doc = "Field `CNF1` reader - "]
pub type CNF1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNF1` writer - "]
pub type CNF1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRL_SPEC, u8, u8, 2, O>;
#[doc = "Field `MODE2` reader - "]
pub type MODE2_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MODE2` writer - "]
pub type MODE2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRL_SPEC, u8, u8, 2, O>;
#[doc = "Field `CNF2` reader - "]
pub type CNF2_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNF2` writer - "]
pub type CNF2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRL_SPEC, u8, u8, 2, O>;
#[doc = "Field `MODE3` reader - "]
pub type MODE3_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MODE3` writer - "]
pub type MODE3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRL_SPEC, u8, u8, 2, O>;
#[doc = "Field `CNF3` reader - "]
pub type CNF3_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNF3` writer - "]
pub type CNF3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRL_SPEC, u8, u8, 2, O>;
#[doc = "Field `MODE4` reader - "]
pub type MODE4_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MODE4` writer - "]
pub type MODE4_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRL_SPEC, u8, u8, 2, O>;
#[doc = "Field `CNF4` reader - "]
pub type CNF4_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNF4` writer - "]
pub type CNF4_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRL_SPEC, u8, u8, 2, O>;
#[doc = "Field `MODE5` reader - "]
pub type MODE5_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MODE5` writer - "]
pub type MODE5_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRL_SPEC, u8, u8, 2, O>;
#[doc = "Field `CNF5` reader - "]
pub type CNF5_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNF5` writer - "]
pub type CNF5_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRL_SPEC, u8, u8, 2, O>;
#[doc = "Field `MODE6` reader - "]
pub type MODE6_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MODE6` writer - "]
pub type MODE6_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRL_SPEC, u8, u8, 2, O>;
#[doc = "Field `CNF6` reader - "]
pub type CNF6_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNF6` writer - "]
pub type CNF6_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRL_SPEC, u8, u8, 2, O>;
#[doc = "Field `MODE7` reader - "]
pub type MODE7_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MODE7` writer - "]
pub type MODE7_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRL_SPEC, u8, u8, 2, O>;
#[doc = "Field `CNF7` reader - "]
pub type CNF7_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNF7` writer - "]
pub type CNF7_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRL_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn mode0(&self) -> MODE0_R {
MODE0_R::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3"]
#[inline(always)]
pub fn cnf0(&self) -> CNF0_R {
CNF0_R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:5"]
#[inline(always)]
pub fn mode1(&self) -> MODE1_R {
MODE1_R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn cnf1(&self) -> CNF1_R {
CNF1_R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn mode2(&self) -> MODE2_R {
MODE2_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11"]
#[inline(always)]
pub fn cnf2(&self) -> CNF2_R {
CNF2_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13"]
#[inline(always)]
pub fn mode3(&self) -> MODE3_R {
MODE3_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn cnf3(&self) -> CNF3_R {
CNF3_R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:17"]
#[inline(always)]
pub fn mode4(&self) -> MODE4_R {
MODE4_R::new(((self.bits >> 16) & 3) as u8)
}
#[doc = "Bits 18:19"]
#[inline(always)]
pub fn cnf4(&self) -> CNF4_R {
CNF4_R::new(((self.bits >> 18) & 3) as u8)
}
#[doc = "Bits 20:21"]
#[inline(always)]
pub fn mode5(&self) -> MODE5_R {
MODE5_R::new(((self.bits >> 20) & 3) as u8)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn cnf5(&self) -> CNF5_R {
CNF5_R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bits 24:25"]
#[inline(always)]
pub fn mode6(&self) -> MODE6_R {
MODE6_R::new(((self.bits >> 24) & 3) as u8)
}
#[doc = "Bits 26:27"]
#[inline(always)]
pub fn cnf6(&self) -> CNF6_R {
CNF6_R::new(((self.bits >> 26) & 3) as u8)
}
#[doc = "Bits 28:29"]
#[inline(always)]
pub fn mode7(&self) -> MODE7_R {
MODE7_R::new(((self.bits >> 28) & 3) as u8)
}
#[doc = "Bits 30:31"]
#[inline(always)]
pub fn cnf7(&self) -> CNF7_R {
CNF7_R::new(((self.bits >> 30) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn mode0(&mut self) -> MODE0_W<0> {
MODE0_W::new(self)
}
#[doc = "Bits 2:3"]
#[inline(always)]
#[must_use]
pub fn cnf0(&mut self) -> CNF0_W<2> {
CNF0_W::new(self)
}
#[doc = "Bits 4:5"]
#[inline(always)]
#[must_use]
pub fn mode1(&mut self) -> MODE1_W<4> {
MODE1_W::new(self)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn cnf1(&mut self) -> CNF1_W<6> {
CNF1_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn mode2(&mut self) -> MODE2_W<8> {
MODE2_W::new(self)
}
#[doc = "Bits 10:11"]
#[inline(always)]
#[must_use]
pub fn cnf2(&mut self) -> CNF2_W<10> {
CNF2_W::new(self)
}
#[doc = "Bits 12:13"]
#[inline(always)]
#[must_use]
pub fn mode3(&mut self) -> MODE3_W<12> {
MODE3_W::new(self)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn cnf3(&mut self) -> CNF3_W<14> {
CNF3_W::new(self)
}
#[doc = "Bits 16:17"]
#[inline(always)]
#[must_use]
pub fn mode4(&mut self) -> MODE4_W<16> {
MODE4_W::new(self)
}
#[doc = "Bits 18:19"]
#[inline(always)]
#[must_use]
pub fn cnf4(&mut self) -> CNF4_W<18> {
CNF4_W::new(self)
}
#[doc = "Bits 20:21"]
#[inline(always)]
#[must_use]
pub fn mode5(&mut self) -> MODE5_W<20> {
MODE5_W::new(self)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn cnf5(&mut self) -> CNF5_W<22> {
CNF5_W::new(self)
}
#[doc = "Bits 24:25"]
#[inline(always)]
#[must_use]
pub fn mode6(&mut self) -> MODE6_W<24> {
MODE6_W::new(self)
}
#[doc = "Bits 26:27"]
#[inline(always)]
#[must_use]
pub fn cnf6(&mut self) -> CNF6_W<26> {
CNF6_W::new(self)
}
#[doc = "Bits 28:29"]
#[inline(always)]
#[must_use]
pub fn mode7(&mut self) -> MODE7_W<28> {
MODE7_W::new(self)
}
#[doc = "Bits 30:31"]
#[inline(always)]
#[must_use]
pub fn cnf7(&mut self) -> CNF7_W<30> {
CNF7_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Port Configuration Low Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crl](index.html) module"]
pub struct CRL_SPEC;
impl crate::RegisterSpec for CRL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [crl::R](R) reader structure"]
impl crate::Readable for CRL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [crl::W](W) writer structure"]
impl crate::Writable for CRL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CRL to value 0x4444_4444"]
impl crate::Resettable for CRL_SPEC {
const RESET_VALUE: Self::Ux = 0x4444_4444;
}
}
#[doc = "CRH (rw) register accessor: an alias for `Reg<CRH_SPEC>`"]
pub type CRH = crate::Reg<crh::CRH_SPEC>;
#[doc = "Port Configuration High Register"]
pub mod crh {
#[doc = "Register `CRH` reader"]
pub struct R(crate::R<CRH_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CRH_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CRH_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CRH_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CRH` writer"]
pub struct W(crate::W<CRH_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CRH_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CRH_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CRH_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MODE8` reader - "]
pub type MODE8_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MODE8` writer - "]
pub type MODE8_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRH_SPEC, u8, u8, 2, O>;
#[doc = "Field `CNF8` reader - "]
pub type CNF8_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNF8` writer - "]
pub type CNF8_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRH_SPEC, u8, u8, 2, O>;
#[doc = "Field `MODE9` reader - "]
pub type MODE9_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MODE9` writer - "]
pub type MODE9_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRH_SPEC, u8, u8, 2, O>;
#[doc = "Field `CNF9` reader - "]
pub type CNF9_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNF9` writer - "]
pub type CNF9_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRH_SPEC, u8, u8, 2, O>;
#[doc = "Field `MODE10` reader - "]
pub type MODE10_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MODE10` writer - "]
pub type MODE10_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRH_SPEC, u8, u8, 2, O>;
#[doc = "Field `CNF10` reader - "]
pub type CNF10_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNF10` writer - "]
pub type CNF10_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRH_SPEC, u8, u8, 2, O>;
#[doc = "Field `MODE11` reader - "]
pub type MODE11_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MODE11` writer - "]
pub type MODE11_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRH_SPEC, u8, u8, 2, O>;
#[doc = "Field `CNF11` reader - "]
pub type CNF11_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNF11` writer - "]
pub type CNF11_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRH_SPEC, u8, u8, 2, O>;
#[doc = "Field `MODE12` reader - "]
pub type MODE12_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MODE12` writer - "]
pub type MODE12_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRH_SPEC, u8, u8, 2, O>;
#[doc = "Field `CNF12` reader - "]
pub type CNF12_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNF12` writer - "]
pub type CNF12_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRH_SPEC, u8, u8, 2, O>;
#[doc = "Field `MODE13` reader - "]
pub type MODE13_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MODE13` writer - "]
pub type MODE13_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRH_SPEC, u8, u8, 2, O>;
#[doc = "Field `CNF13` reader - "]
pub type CNF13_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNF13` writer - "]
pub type CNF13_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRH_SPEC, u8, u8, 2, O>;
#[doc = "Field `MODE14` reader - "]
pub type MODE14_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MODE14` writer - "]
pub type MODE14_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRH_SPEC, u8, u8, 2, O>;
#[doc = "Field `CNF14` reader - "]
pub type CNF14_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNF14` writer - "]
pub type CNF14_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRH_SPEC, u8, u8, 2, O>;
#[doc = "Field `MODE15` reader - "]
pub type MODE15_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MODE15` writer - "]
pub type MODE15_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRH_SPEC, u8, u8, 2, O>;
#[doc = "Field `CNF15` reader - "]
pub type CNF15_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNF15` writer - "]
pub type CNF15_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CRH_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn mode8(&self) -> MODE8_R {
MODE8_R::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3"]
#[inline(always)]
pub fn cnf8(&self) -> CNF8_R {
CNF8_R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:5"]
#[inline(always)]
pub fn mode9(&self) -> MODE9_R {
MODE9_R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn cnf9(&self) -> CNF9_R {
CNF9_R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn mode10(&self) -> MODE10_R {
MODE10_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11"]
#[inline(always)]
pub fn cnf10(&self) -> CNF10_R {
CNF10_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13"]
#[inline(always)]
pub fn mode11(&self) -> MODE11_R {
MODE11_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn cnf11(&self) -> CNF11_R {
CNF11_R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:17"]
#[inline(always)]
pub fn mode12(&self) -> MODE12_R {
MODE12_R::new(((self.bits >> 16) & 3) as u8)
}
#[doc = "Bits 18:19"]
#[inline(always)]
pub fn cnf12(&self) -> CNF12_R {
CNF12_R::new(((self.bits >> 18) & 3) as u8)
}
#[doc = "Bits 20:21"]
#[inline(always)]
pub fn mode13(&self) -> MODE13_R {
MODE13_R::new(((self.bits >> 20) & 3) as u8)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn cnf13(&self) -> CNF13_R {
CNF13_R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bits 24:25"]
#[inline(always)]
pub fn mode14(&self) -> MODE14_R {
MODE14_R::new(((self.bits >> 24) & 3) as u8)
}
#[doc = "Bits 26:27"]
#[inline(always)]
pub fn cnf14(&self) -> CNF14_R {
CNF14_R::new(((self.bits >> 26) & 3) as u8)
}
#[doc = "Bits 28:29"]
#[inline(always)]
pub fn mode15(&self) -> MODE15_R {
MODE15_R::new(((self.bits >> 28) & 3) as u8)
}
#[doc = "Bits 30:31"]
#[inline(always)]
pub fn cnf15(&self) -> CNF15_R {
CNF15_R::new(((self.bits >> 30) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn mode8(&mut self) -> MODE8_W<0> {
MODE8_W::new(self)
}
#[doc = "Bits 2:3"]
#[inline(always)]
#[must_use]
pub fn cnf8(&mut self) -> CNF8_W<2> {
CNF8_W::new(self)
}
#[doc = "Bits 4:5"]
#[inline(always)]
#[must_use]
pub fn mode9(&mut self) -> MODE9_W<4> {
MODE9_W::new(self)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn cnf9(&mut self) -> CNF9_W<6> {
CNF9_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn mode10(&mut self) -> MODE10_W<8> {
MODE10_W::new(self)
}
#[doc = "Bits 10:11"]
#[inline(always)]
#[must_use]
pub fn cnf10(&mut self) -> CNF10_W<10> {
CNF10_W::new(self)
}
#[doc = "Bits 12:13"]
#[inline(always)]
#[must_use]
pub fn mode11(&mut self) -> MODE11_W<12> {
MODE11_W::new(self)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn cnf11(&mut self) -> CNF11_W<14> {
CNF11_W::new(self)
}
#[doc = "Bits 16:17"]
#[inline(always)]
#[must_use]
pub fn mode12(&mut self) -> MODE12_W<16> {
MODE12_W::new(self)
}
#[doc = "Bits 18:19"]
#[inline(always)]
#[must_use]
pub fn cnf12(&mut self) -> CNF12_W<18> {
CNF12_W::new(self)
}
#[doc = "Bits 20:21"]
#[inline(always)]
#[must_use]
pub fn mode13(&mut self) -> MODE13_W<20> {
MODE13_W::new(self)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn cnf13(&mut self) -> CNF13_W<22> {
CNF13_W::new(self)
}
#[doc = "Bits 24:25"]
#[inline(always)]
#[must_use]
pub fn mode14(&mut self) -> MODE14_W<24> {
MODE14_W::new(self)
}
#[doc = "Bits 26:27"]
#[inline(always)]
#[must_use]
pub fn cnf14(&mut self) -> CNF14_W<26> {
CNF14_W::new(self)
}
#[doc = "Bits 28:29"]
#[inline(always)]
#[must_use]
pub fn mode15(&mut self) -> MODE15_W<28> {
MODE15_W::new(self)
}
#[doc = "Bits 30:31"]
#[inline(always)]
#[must_use]
pub fn cnf15(&mut self) -> CNF15_W<30> {
CNF15_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Port Configuration High Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crh](index.html) module"]
pub struct CRH_SPEC;
impl crate::RegisterSpec for CRH_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [crh::R](R) reader structure"]
impl crate::Readable for CRH_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [crh::W](W) writer structure"]
impl crate::Writable for CRH_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CRH to value 0x4444_4444"]
impl crate::Resettable for CRH_SPEC {
const RESET_VALUE: Self::Ux = 0x4444_4444;
}
}
#[doc = "IDR (r) register accessor: an alias for `Reg<IDR_SPEC>`"]
pub type IDR = crate::Reg<idr::IDR_SPEC>;
#[doc = "Port Input Data Register"]
pub mod idr {
#[doc = "Register `IDR` reader"]
pub struct R(crate::R<IDR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IDR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IDR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `IDRY` reader - "]
pub type IDRY_R = crate::FieldReader<u16, u16>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn idry(&self) -> IDRY_R {
IDRY_R::new((self.bits & 0xffff) as u16)
}
}
#[doc = "Port Input Data Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"]
pub struct IDR_SPEC;
impl crate::RegisterSpec for IDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [idr::R](R) reader structure"]
impl crate::Readable for IDR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets IDR to value 0"]
impl crate::Resettable for IDR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ODR (rw) register accessor: an alias for `Reg<ODR_SPEC>`"]
pub type ODR = crate::Reg<odr::ODR_SPEC>;
#[doc = "PORT OUTPUT DATA REGISTER"]
pub mod odr {
#[doc = "Register `ODR` reader"]
pub struct R(crate::R<ODR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ODR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ODR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ODR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ODR` writer"]
pub struct W(crate::W<ODR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ODR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ODR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ODR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `ODRY` reader - "]
pub type ODRY_R = crate::FieldReader<u16, u16>;
#[doc = "Field `ODRY` writer - "]
pub type ODRY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ODR_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn odry(&self) -> ODRY_R {
ODRY_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn odry(&mut self) -> ODRY_W<0> {
ODRY_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "PORT OUTPUT DATA REGISTER\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [odr](index.html) module"]
pub struct ODR_SPEC;
impl crate::RegisterSpec for ODR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [odr::R](R) reader structure"]
impl crate::Readable for ODR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [odr::W](W) writer structure"]
impl crate::Writable for ODR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ODR to value 0"]
impl crate::Resettable for ODR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "BSRR (w) register accessor: an alias for `Reg<BSRR_SPEC>`"]
pub type BSRR = crate::Reg<bsrr::BSRR_SPEC>;
#[doc = "Port Set/Clear Register"]
pub mod bsrr {
#[doc = "Register `BSRR` writer"]
pub struct W(crate::W<BSRR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<BSRR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<BSRR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<BSRR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `BSy` writer - "]
pub type BSY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BSRR_SPEC, u16, u16, 16, O>;
#[doc = "Field `BRy` writer - "]
pub type BRY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BSRR_SPEC, u16, u16, 16, O>;
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn bsy(&mut self) -> BSY_W<0> {
BSY_W::new(self)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn bry(&mut self) -> BRY_W<16> {
BRY_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Port Set/Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bsrr](index.html) module"]
pub struct BSRR_SPEC;
impl crate::RegisterSpec for BSRR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [bsrr::W](W) writer structure"]
impl crate::Writable for BSRR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets BSRR to value 0"]
impl crate::Resettable for BSRR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "BRR (w) register accessor: an alias for `Reg<BRR_SPEC>`"]
pub type BRR = crate::Reg<brr::BRR_SPEC>;
#[doc = "Port Bit Clear Register"]
pub mod brr {
#[doc = "Register `BRR` writer"]
pub struct W(crate::W<BRR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<BRR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<BRR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<BRR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `BRy` writer - "]
pub type BRY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BRR_SPEC, u16, u16, 16, O>;
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn bry(&mut self) -> BRY_W<0> {
BRY_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Port Bit Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [brr](index.html) module"]
pub struct BRR_SPEC;
impl crate::RegisterSpec for BRR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [brr::W](W) writer structure"]
impl crate::Writable for BRR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets BRR to value 0"]
impl crate::Resettable for BRR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "LCKR (rw) register accessor: an alias for `Reg<LCKR_SPEC>`"]
pub type LCKR = crate::Reg<lckr::LCKR_SPEC>;
#[doc = "Port Configuration Lock Register"]
pub mod lckr {
#[doc = "Register `LCKR` reader"]
pub struct R(crate::R<LCKR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<LCKR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<LCKR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<LCKR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `LCKR` writer"]
pub struct W(crate::W<LCKR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<LCKR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<LCKR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<LCKR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `LCKy` writer - "]
pub type LCKY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LCKR_SPEC, u16, u16, 16, O>;
#[doc = "Field `LCKK` reader - "]
pub type LCKK_R = crate::BitReader<bool>;
#[doc = "Field `LCKK` writer - "]
pub type LCKK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LCKR_SPEC, bool, O>;
impl R {
#[doc = "Bit 16"]
#[inline(always)]
pub fn lckk(&self) -> LCKK_R {
LCKK_R::new(((self.bits >> 16) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn lcky(&mut self) -> LCKY_W<0> {
LCKY_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn lckk(&mut self) -> LCKK_W<16> {
LCKK_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Port Configuration Lock Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lckr](index.html) module"]
pub struct LCKR_SPEC;
impl crate::RegisterSpec for LCKR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [lckr::R](R) reader structure"]
impl crate::Readable for LCKR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [lckr::W](W) writer structure"]
impl crate::Writable for LCKR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets LCKR to value 0"]
impl crate::Resettable for LCKR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DCR (rw) register accessor: an alias for `Reg<DCR_SPEC>`"]
pub type DCR = crate::Reg<dcr::DCR_SPEC>;
#[doc = "PORT OUTPUT OPEN DRAIN CONTROL REGISTER"]
pub mod dcr {
#[doc = "Register `DCR` reader"]
pub struct R(crate::R<DCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DCR` writer"]
pub struct W(crate::W<DCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PX0` reader - "]
pub type PX0_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PX0` writer - "]
pub type PX0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `PX15_PX1` reader - "]
pub type PX15_PX1_R = crate::FieldReader<u32, u32>;
#[doc = "Field `PX15_PX1` writer - "]
pub type PX15_PX1_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DCR_SPEC, u32, u32, 30, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn px0(&self) -> PX0_R {
PX0_R::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:31"]
#[inline(always)]
pub fn px15_px1(&self) -> PX15_PX1_R {
PX15_PX1_R::new((self.bits >> 2) & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn px0(&mut self) -> PX0_W<0> {
PX0_W::new(self)
}
#[doc = "Bits 2:31"]
#[inline(always)]
#[must_use]
pub fn px15_px1(&mut self) -> PX15_PX1_W<2> {
PX15_PX1_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "PORT OUTPUT OPEN DRAIN CONTROL REGISTER\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcr](index.html) module"]
pub struct DCR_SPEC;
impl crate::RegisterSpec for DCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dcr::R](R) reader structure"]
impl crate::Readable for DCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dcr::W](W) writer structure"]
impl crate::Writable for DCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DCR to value 0"]
impl crate::Resettable for DCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "AFRL (rw) register accessor: an alias for `Reg<AFRL_SPEC>`"]
pub type AFRL = crate::Reg<afrl::AFRL_SPEC>;
#[doc = "Port alternate function low-order register"]
pub mod afrl {
#[doc = "Register `AFRL` reader"]
pub struct R(crate::R<AFRL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<AFRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<AFRL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<AFRL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `AFRL` writer"]
pub struct W(crate::W<AFRL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<AFRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<AFRL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<AFRL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `AFRy` reader - "]
pub type AFRY_R = crate::FieldReader<u32, u32>;
#[doc = "Field `AFRy` writer - "]
pub type AFRY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, AFRL_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn afry(&self) -> AFRY_R {
AFRY_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn afry(&mut self) -> AFRY_W<0> {
AFRY_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Port alternate function low-order register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [afrl](index.html) module"]
pub struct AFRL_SPEC;
impl crate::RegisterSpec for AFRL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [afrl::R](R) reader structure"]
impl crate::Readable for AFRL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [afrl::W](W) writer structure"]
impl crate::Writable for AFRL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets AFRL to value 0xffff_ffff"]
impl crate::Resettable for AFRL_SPEC {
const RESET_VALUE: Self::Ux = 0xffff_ffff;
}
}
#[doc = "AFRH (rw) register accessor: an alias for `Reg<AFRH_SPEC>`"]
pub type AFRH = crate::Reg<afrh::AFRH_SPEC>;
#[doc = "Port alternate function high-order register"]
pub mod afrh {
#[doc = "Register `AFRH` reader"]
pub struct R(crate::R<AFRH_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<AFRH_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<AFRH_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<AFRH_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `AFRH` writer"]
pub struct W(crate::W<AFRH_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<AFRH_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<AFRH_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<AFRH_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `AFRy` reader - "]
pub type AFRY_R = crate::FieldReader<u32, u32>;
#[doc = "Field `AFRy` writer - "]
pub type AFRY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, AFRH_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn afry(&self) -> AFRY_R {
AFRY_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn afry(&mut self) -> AFRY_W<0> {
AFRY_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Port alternate function high-order register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [afrh](index.html) module"]
pub struct AFRH_SPEC;
impl crate::RegisterSpec for AFRH_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [afrh::R](R) reader structure"]
impl crate::Readable for AFRH_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [afrh::W](W) writer structure"]
impl crate::Writable for AFRH_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets AFRH to value 0xffff_ffff"]
impl crate::Resettable for AFRH_SPEC {
const RESET_VALUE: Self::Ux = 0xffff_ffff;
}
}
}
#[doc = "GPIOB"]
pub struct GPIOB {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOB {}
impl GPIOB {
#[doc = r"Pointer to the register block"]
pub const PTR: *const gpioa::RegisterBlock = 0x4004_0400 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const gpioa::RegisterBlock {
Self::PTR
}
}
impl Deref for GPIOB {
type Target = gpioa::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for GPIOB {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOB").finish()
}
}
#[doc = "GPIOB"]
pub use self::gpioa as gpiob;
#[doc = "GPIOC"]
pub struct GPIOC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOC {}
impl GPIOC {
#[doc = r"Pointer to the register block"]
pub const PTR: *const gpioa::RegisterBlock = 0x4004_0800 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const gpioa::RegisterBlock {
Self::PTR
}
}
impl Deref for GPIOC {
type Target = gpioa::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for GPIOC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOC").finish()
}
}
#[doc = "GPIOC"]
pub use self::gpioa as gpioc;
#[doc = "GPIOD"]
pub struct GPIOD {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOD {}
impl GPIOD {
#[doc = r"Pointer to the register block"]
pub const PTR: *const gpioa::RegisterBlock = 0x4004_0c00 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const gpioa::RegisterBlock {
Self::PTR
}
}
impl Deref for GPIOD {
type Target = gpioa::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for GPIOD {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOD").finish()
}
}
#[doc = "GPIOD"]
pub use self::gpioa as gpiod;
#[doc = "GPIOE"]
pub struct GPIOE {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOE {}
impl GPIOE {
#[doc = r"Pointer to the register block"]
pub const PTR: *const gpioa::RegisterBlock = 0x4004_1000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const gpioa::RegisterBlock {
Self::PTR
}
}
impl Deref for GPIOE {
type Target = gpioa::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for GPIOE {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOE").finish()
}
}
#[doc = "GPIOE"]
pub use self::gpioa as gpioe;
#[doc = "GPIOF"]
pub struct GPIOF {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOF {}
impl GPIOF {
#[doc = r"Pointer to the register block"]
pub const PTR: *const gpioa::RegisterBlock = 0x4004_1400 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const gpioa::RegisterBlock {
Self::PTR
}
}
impl Deref for GPIOF {
type Target = gpioa::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for GPIOF {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOF").finish()
}
}
#[doc = "GPIOF"]
pub use self::gpioa as gpiof;
#[doc = "GPIOG"]
pub struct GPIOG {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOG {}
impl GPIOG {
#[doc = r"Pointer to the register block"]
pub const PTR: *const gpioa::RegisterBlock = 0x4004_1800 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const gpioa::RegisterBlock {
Self::PTR
}
}
impl Deref for GPIOG {
type Target = gpioa::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for GPIOG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOG").finish()
}
}
#[doc = "GPIOG"]
pub use self::gpioa as gpiog;
#[doc = "GPIOH"]
pub struct GPIOH {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOH {}
impl GPIOH {
#[doc = r"Pointer to the register block"]
pub const PTR: *const gpioa::RegisterBlock = 0x4004_1c00 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const gpioa::RegisterBlock {
Self::PTR
}
}
impl Deref for GPIOH {
type Target = gpioa::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for GPIOH {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOH").finish()
}
}
#[doc = "GPIOH"]
pub use self::gpioa as gpioh;
#[doc = "GPIOI"]
pub struct GPIOI {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOI {}
impl GPIOI {
#[doc = r"Pointer to the register block"]
pub const PTR: *const gpioa::RegisterBlock = 0x4004_2000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const gpioa::RegisterBlock {
Self::PTR
}
}
impl Deref for GPIOI {
type Target = gpioa::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for GPIOI {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("GPIOI").finish()
}
}
#[doc = "GPIOI"]
pub use self::gpioa as gpioi;
#[doc = "I2C1"]
pub struct I2C1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for I2C1 {}
impl I2C1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const i2c1::RegisterBlock = 0x4000_5400 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const i2c1::RegisterBlock {
Self::PTR
}
}
impl Deref for I2C1 {
type Target = i2c1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for I2C1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C1").finish()
}
}
#[doc = "I2C1"]
pub mod i2c1 {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - control register"]
pub cr: CR,
#[doc = "0x04 - target address register"]
pub tar: TAR,
#[doc = "0x08 - slave address register"]
pub sar: SAR,
_reserved3: [u8; 0x04],
#[doc = "0x10 - Data Command Register"]
pub dr: DR,
#[doc = "0x14 - Standard Mode Clock High Count Register"]
pub sshr: SSHR,
#[doc = "0x18 - Standard Mode Clock Low Count Register"]
pub sslr: SSLR,
#[doc = "0x1c - Fast/Super Fast Mode Clock High Count Register"]
pub fshr: FSHR,
#[doc = "0x20 - Fast/Super Fast Mode Clock Low Count Register"]
pub fslr: FSLR,
_reserved8: [u8; 0x08],
#[doc = "0x2c - Interrupt Status Register"]
pub isr: ISR,
#[doc = "0x30 - interrupt mask register"]
pub imr: IMR,
#[doc = "0x34 - RAW interrupt register"]
pub rawisr: RAWISR,
#[doc = "0x38 - receive threshold register"]
pub rxtlr: RXTLR,
#[doc = "0x3c - Transmit Threshold Register"]
pub txtlr: TXTLR,
#[doc = "0x40 - Combined and Independent Interrupt Clear Registers"]
pub icr: ICR,
#[doc = "0x44 - Clear the RX_UNDER interrupt register"]
pub rx_under: RX_UNDER,
#[doc = "0x48 - Clear the RX_OVER interrupt register"]
pub rx_over: RX_OVER,
#[doc = "0x4c - Clear the TX_OVER interrupt register"]
pub tx_over: TX_OVER,
#[doc = "0x50 - Clear the RD_REQ interrupt register"]
pub rd_req: RD_REQ,
#[doc = "0x54 - Clear the TX_ABRT interrupt register"]
pub tx_abrt: TX_ABRT,
#[doc = "0x58 - Clear the RX_DONE interrupt register"]
pub rx_done: RX_DONE,
#[doc = "0x5c - Clear the ACTIVITY interrupt register"]
pub activ: ACTIV,
#[doc = "0x60 - Clear the STOP_DET interrupt register"]
pub stop: STOP,
#[doc = "0x64 - Clear the START_DET interrupt register"]
pub start: START,
#[doc = "0x68 - Clear the GEN_CALL interrupt register"]
pub gc: GC,
#[doc = "0x6c - enable register"]
pub enr: ENR,
#[doc = "0x70 - status register"]
pub sr: SR,
#[doc = "0x74 - Transmit buffer level register"]
pub txflr: TXFLR,
#[doc = "0x78 - Receive buffer level register"]
pub rxflr: RXFLR,
#[doc = "0x7c - SDA hold time register"]
pub hold: HOLD,
#[doc = "0x80 - Transfer Abort Source Register"]
pub tx_abrt_src: TX_ABRT_SRC,
#[doc = "0x84 - Slave Receive NACK Register"]
pub slv_nack: SLV_NACK,
#[doc = "0x88 - DMA Control Register"]
pub dma: DMA,
_reserved32: [u8; 0x08],
#[doc = "0x94 - SDA setup time register"]
pub setup: SETUP,
#[doc = "0x98 - General Call ACK Register"]
pub gcr: GCR,
#[doc = "0x9c - ENABLE Status Register"]
pub en_sr: EN_SR,
#[doc = "0xa0 - filter register"]
pub spklen: SPKLEN,
_reserved36: [u8; 0x08],
#[doc = "0xac - SCL Low Timeout Register"]
pub scl_tmo: SCL_TMO,
#[doc = "0xb0 - SDA Low Timeout Register"]
pub sda_tmo: SDA_TMO,
#[doc = "0xb4 - Clear the SCL_STUCK interrupt register"]
pub scl_stuck: SCL_STUCK,
_reserved39: [u8; 0x04],
#[doc = "0xbc - SMBus Slave Clock Stretching Timeout Register"]
pub smb_sext: SMB_SEXT,
#[doc = "0xc0 - SMBus Master Clock Stretching Timeout Register"]
pub smb_mext: SMB_MEXT,
#[doc = "0xc4 - SMBus Bus Idle Count Register"]
pub smb_idle: SMB_IDLE,
#[doc = "0xc8 - SMBus Interrupt Status Register"]
pub smb_isr: SMB_ISR,
#[doc = "0xcc - SMBus Interrupt Mask Register"]
pub smb_imr: SMB_IMR,
#[doc = "0xd0 - SMBus RAW Interrupt Register"]
pub smb_rawisr: SMB_RAWISR,
#[doc = "0xd4 - SMBus Combined and Independent Interrupt Clear Registers"]
pub smb_icr: SMB_ICR,
#[doc = "0xd8 - Optional Slave Address Register"]
pub opt_sar: OPT_SAR,
#[doc = "0xdc - SMBus UDID LSB Register"]
pub smb_udid_lsb: SMB_UDID_LSB,
#[doc = "0xe0 - SMBus UDID MSB Register 0"]
pub smb_udid_msb0: SMB_UDID_MSB0,
#[doc = "0xe4 - SMBus UDID MSB Register 1"]
pub smb_udid_msb1: SMB_UDID_MSB1,
#[doc = "0xe8 - SMBus UDID MSB Register 2"]
pub smb_udid_msb2: SMB_UDID_MSB2,
#[doc = "0xec - Slave Address Mask Register"]
pub slvmask: SLVMASK,
#[doc = "0xf0 - Slave Receive Address Register"]
pub slvrcvaddr: SLVRCVADDR,
}
#[doc = "CR (rw) register accessor: an alias for `Reg<CR_SPEC>`"]
pub type CR = crate::Reg<cr::CR_SPEC>;
#[doc = "control register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub struct R(crate::R<CR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR` writer"]
pub struct W(crate::W<CR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MASTER` reader - "]
pub type MASTER_R = crate::BitReader<bool>;
#[doc = "Field `MASTER` writer - "]
pub type MASTER_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `SPEED` reader - "]
pub type SPEED_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SPEED` writer - "]
pub type SPEED_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, u8, 2, O>;
#[doc = "Field `SLAVE10` reader - "]
pub type SLAVE10_R = crate::BitReader<bool>;
#[doc = "Field `SLAVE10` writer - "]
pub type SLAVE10_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `MASTER10` reader - "]
pub type MASTER10_R = crate::BitReader<bool>;
#[doc = "Field `MASTER10` writer - "]
pub type MASTER10_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `REPEN` reader - "]
pub type REPEN_R = crate::BitReader<bool>;
#[doc = "Field `REPEN` writer - "]
pub type REPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `DISSLAVE` reader - "]
pub type DISSLAVE_R = crate::BitReader<bool>;
#[doc = "Field `DISSLAVE` writer - "]
pub type DISSLAVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `STOPINT` reader - "]
pub type STOPINT_R = crate::BitReader<bool>;
#[doc = "Field `STOPINT` writer - "]
pub type STOPINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `EMPINT` reader - "]
pub type EMPINT_R = crate::BitReader<bool>;
#[doc = "Field `EMPINT` writer - "]
pub type EMPINT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `STOP` reader - "]
pub type STOP_R = crate::BitReader<bool>;
#[doc = "Field `STOP` writer - "]
pub type STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `RESTART` reader - "]
pub type RESTART_R = crate::BitReader<bool>;
#[doc = "Field `RESTART` writer - "]
pub type RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `SLV_TX_ABRT_DIS` reader - "]
pub type SLV_TX_ABRT_DIS_R = crate::BitReader<bool>;
#[doc = "Field `SLV_TX_ABRT_DIS` writer - "]
pub type SLV_TX_ABRT_DIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `PAD_SEL` reader - "]
pub type PAD_SEL_R = crate::BitReader<bool>;
#[doc = "Field `PAD_SEL` writer - "]
pub type PAD_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `OPT_SAR_EN` reader - "]
pub type OPT_SAR_EN_R = crate::BitReader<bool>;
#[doc = "Field `OPT_SAR_EN` writer - "]
pub type OPT_SAR_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `SMB_SLV_QC_EN` reader - "]
pub type SMB_SLV_QC_EN_R = crate::BitReader<bool>;
#[doc = "Field `SMB_SLV_QC_EN` writer - "]
pub type SMB_SLV_QC_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `SMB_ARP_EN` reader - "]
pub type SMB_ARP_EN_R = crate::BitReader<bool>;
#[doc = "Field `SMB_ARP_EN` writer - "]
pub type SMB_ARP_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `SMB_PSA_EN` reader - "]
pub type SMB_PSA_EN_R = crate::BitReader<bool>;
#[doc = "Field `SMB_PSA_EN` writer - "]
pub type SMB_PSA_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `STOP_DET_MST_ACT` reader - "]
pub type STOP_DET_MST_ACT_R = crate::BitReader<bool>;
#[doc = "Field `STOP_DET_MST_ACT` writer - "]
pub type STOP_DET_MST_ACT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `BUS_CLR` reader - "]
pub type BUS_CLR_R = crate::BitReader<bool>;
#[doc = "Field `BUS_CLR` writer - "]
pub type BUS_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `RX_FULL_HLD` reader - "]
pub type RX_FULL_HLD_R = crate::BitReader<bool>;
#[doc = "Field `RX_FULL_HLD` writer - "]
pub type RX_FULL_HLD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn master(&self) -> MASTER_R {
MASTER_R::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2"]
#[inline(always)]
pub fn speed(&self) -> SPEED_R {
SPEED_R::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn slave10(&self) -> SLAVE10_R {
SLAVE10_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn master10(&self) -> MASTER10_R {
MASTER10_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn repen(&self) -> REPEN_R {
REPEN_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn disslave(&self) -> DISSLAVE_R {
DISSLAVE_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn stopint(&self) -> STOPINT_R {
STOPINT_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn empint(&self) -> EMPINT_R {
EMPINT_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn stop(&self) -> STOP_R {
STOP_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn restart(&self) -> RESTART_R {
RESTART_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn slv_tx_abrt_dis(&self) -> SLV_TX_ABRT_DIS_R {
SLV_TX_ABRT_DIS_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn pad_sel(&self) -> PAD_SEL_R {
PAD_SEL_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn opt_sar_en(&self) -> OPT_SAR_EN_R {
OPT_SAR_EN_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn smb_slv_qc_en(&self) -> SMB_SLV_QC_EN_R {
SMB_SLV_QC_EN_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn smb_arp_en(&self) -> SMB_ARP_EN_R {
SMB_ARP_EN_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn smb_psa_en(&self) -> SMB_PSA_EN_R {
SMB_PSA_EN_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn stop_det_mst_act(&self) -> STOP_DET_MST_ACT_R {
STOP_DET_MST_ACT_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn bus_clr(&self) -> BUS_CLR_R {
BUS_CLR_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn rx_full_hld(&self) -> RX_FULL_HLD_R {
RX_FULL_HLD_R::new(((self.bits >> 22) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn master(&mut self) -> MASTER_W<0> {
MASTER_W::new(self)
}
#[doc = "Bits 1:2"]
#[inline(always)]
#[must_use]
pub fn speed(&mut self) -> SPEED_W<1> {
SPEED_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn slave10(&mut self) -> SLAVE10_W<3> {
SLAVE10_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn master10(&mut self) -> MASTER10_W<4> {
MASTER10_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn repen(&mut self) -> REPEN_W<5> {
REPEN_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn disslave(&mut self) -> DISSLAVE_W<6> {
DISSLAVE_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn stopint(&mut self) -> STOPINT_W<7> {
STOPINT_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn empint(&mut self) -> EMPINT_W<8> {
EMPINT_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn stop(&mut self) -> STOP_W<9> {
STOP_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn restart(&mut self) -> RESTART_W<10> {
RESTART_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn slv_tx_abrt_dis(&mut self) -> SLV_TX_ABRT_DIS_W<11> {
SLV_TX_ABRT_DIS_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn pad_sel(&mut self) -> PAD_SEL_W<12> {
PAD_SEL_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn opt_sar_en(&mut self) -> OPT_SAR_EN_W<16> {
OPT_SAR_EN_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn smb_slv_qc_en(&mut self) -> SMB_SLV_QC_EN_W<17> {
SMB_SLV_QC_EN_W::new(self)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn smb_arp_en(&mut self) -> SMB_ARP_EN_W<18> {
SMB_ARP_EN_W::new(self)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn smb_psa_en(&mut self) -> SMB_PSA_EN_W<19> {
SMB_PSA_EN_W::new(self)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn stop_det_mst_act(&mut self) -> STOP_DET_MST_ACT_W<20> {
STOP_DET_MST_ACT_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn bus_clr(&mut self) -> BUS_CLR_W<21> {
BUS_CLR_W::new(self)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn rx_full_hld(&mut self) -> RX_FULL_HLD_W<22> {
RX_FULL_HLD_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"]
pub struct CR_SPEC;
impl crate::RegisterSpec for CR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr::R](R) reader structure"]
impl crate::Readable for CR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"]
impl crate::Writable for CR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR to value 0x65"]
impl crate::Resettable for CR_SPEC {
const RESET_VALUE: Self::Ux = 0x65;
}
}
#[doc = "TAR (rw) register accessor: an alias for `Reg<TAR_SPEC>`"]
pub type TAR = crate::Reg<tar::TAR_SPEC>;
#[doc = "target address register"]
pub mod tar {
#[doc = "Register `TAR` reader"]
pub struct R(crate::R<TAR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<TAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<TAR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<TAR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `TAR` writer"]
pub struct W(crate::W<TAR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<TAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<TAR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<TAR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `ADDR` reader - "]
pub type ADDR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `ADDR` writer - "]
pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TAR_SPEC, u16, u16, 10, O>;
#[doc = "Field `GC` reader - "]
pub type GC_R = crate::BitReader<bool>;
#[doc = "Field `GC` writer - "]
pub type GC_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAR_SPEC, bool, O>;
#[doc = "Field `SPECIAL` reader - "]
pub type SPECIAL_R = crate::BitReader<bool>;
#[doc = "Field `SPECIAL` writer - "]
pub type SPECIAL_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAR_SPEC, bool, O>;
#[doc = "Field `SMB_QC` reader - "]
pub type SMB_QC_R = crate::BitReader<bool>;
#[doc = "Field `SMB_QC` writer - "]
pub type SMB_QC_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:9"]
#[inline(always)]
pub fn addr(&self) -> ADDR_R {
ADDR_R::new((self.bits & 0x03ff) as u16)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn gc(&self) -> GC_R {
GC_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn special(&self) -> SPECIAL_R {
SPECIAL_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn smb_qc(&self) -> SMB_QC_R {
SMB_QC_R::new(((self.bits >> 16) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:9"]
#[inline(always)]
#[must_use]
pub fn addr(&mut self) -> ADDR_W<0> {
ADDR_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn gc(&mut self) -> GC_W<10> {
GC_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn special(&mut self) -> SPECIAL_W<11> {
SPECIAL_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn smb_qc(&mut self) -> SMB_QC_W<16> {
SMB_QC_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "target address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tar](index.html) module"]
pub struct TAR_SPEC;
impl crate::RegisterSpec for TAR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [tar::R](R) reader structure"]
impl crate::Readable for TAR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [tar::W](W) writer structure"]
impl crate::Writable for TAR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets TAR to value 0x55"]
impl crate::Resettable for TAR_SPEC {
const RESET_VALUE: Self::Ux = 0x55;
}
}
#[doc = "SAR (rw) register accessor: an alias for `Reg<SAR_SPEC>`"]
pub type SAR = crate::Reg<sar::SAR_SPEC>;
#[doc = "slave address register"]
pub mod sar {
#[doc = "Register `SAR` reader"]
pub struct R(crate::R<SAR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SAR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SAR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SAR` writer"]
pub struct W(crate::W<SAR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SAR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SAR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `ADDR` reader - "]
pub type ADDR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `ADDR` writer - "]
pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SAR_SPEC, u16, u16, 10, O>;
impl R {
#[doc = "Bits 0:9"]
#[inline(always)]
pub fn addr(&self) -> ADDR_R {
ADDR_R::new((self.bits & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:9"]
#[inline(always)]
#[must_use]
pub fn addr(&mut self) -> ADDR_W<0> {
ADDR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "slave address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sar](index.html) module"]
pub struct SAR_SPEC;
impl crate::RegisterSpec for SAR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [sar::R](R) reader structure"]
impl crate::Readable for SAR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [sar::W](W) writer structure"]
impl crate::Writable for SAR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SAR to value 0x55"]
impl crate::Resettable for SAR_SPEC {
const RESET_VALUE: Self::Ux = 0x55;
}
}
#[doc = "DR (rw) register accessor: an alias for `Reg<DR_SPEC>`"]
pub type DR = crate::Reg<dr::DR_SPEC>;
#[doc = "Data Command Register"]
pub mod dr {
#[doc = "Register `DR` reader"]
pub struct R(crate::R<DR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DR` writer"]
pub struct W(crate::W<DR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DAT` reader - "]
pub type DAT_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DAT` writer - "]
pub type DAT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DR_SPEC, u8, u8, 8, O>;
#[doc = "Field `CMD` writer - "]
pub type CMD_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>;
#[doc = "Field `FIRST_DATA` reader - "]
pub type FIRST_DATA_R = crate::BitReader<bool>;
#[doc = "Field `FIRST_DATA` writer - "]
pub type FIRST_DATA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn dat(&self) -> DAT_R {
DAT_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn first_data(&self) -> FIRST_DATA_R {
FIRST_DATA_R::new(((self.bits >> 11) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn dat(&mut self) -> DAT_W<0> {
DAT_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn cmd(&mut self) -> CMD_W<8> {
CMD_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn first_data(&mut self) -> FIRST_DATA_W<11> {
FIRST_DATA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Data Command Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](index.html) module"]
pub struct DR_SPEC;
impl crate::RegisterSpec for DR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dr::R](R) reader structure"]
impl crate::Readable for DR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dr::W](W) writer structure"]
impl crate::Writable for DR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DR to value 0"]
impl crate::Resettable for DR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SSHR (rw) register accessor: an alias for `Reg<SSHR_SPEC>`"]
pub type SSHR = crate::Reg<sshr::SSHR_SPEC>;
#[doc = "Standard Mode Clock High Count Register"]
pub mod sshr {
#[doc = "Register `SSHR` reader"]
pub struct R(crate::R<SSHR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SSHR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SSHR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SSHR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SSHR` writer"]
pub struct W(crate::W<SSHR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SSHR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SSHR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SSHR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CNT` reader - "]
pub type CNT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CNT` writer - "]
pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SSHR_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn cnt(&self) -> CNT_R {
CNT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CNT_W<0> {
CNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Standard Mode Clock High Count Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sshr](index.html) module"]
pub struct SSHR_SPEC;
impl crate::RegisterSpec for SSHR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [sshr::R](R) reader structure"]
impl crate::Readable for SSHR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [sshr::W](W) writer structure"]
impl crate::Writable for SSHR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SSHR to value 0x0190"]
impl crate::Resettable for SSHR_SPEC {
const RESET_VALUE: Self::Ux = 0x0190;
}
}
#[doc = "SSLR (rw) register accessor: an alias for `Reg<SSLR_SPEC>`"]
pub type SSLR = crate::Reg<sslr::SSLR_SPEC>;
#[doc = "Standard Mode Clock Low Count Register"]
pub mod sslr {
#[doc = "Register `SSLR` reader"]
pub struct R(crate::R<SSLR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SSLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SSLR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SSLR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SSLR` writer"]
pub struct W(crate::W<SSLR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SSLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SSLR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SSLR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CNT` reader - "]
pub type CNT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CNT` writer - "]
pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SSLR_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn cnt(&self) -> CNT_R {
CNT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CNT_W<0> {
CNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Standard Mode Clock Low Count Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sslr](index.html) module"]
pub struct SSLR_SPEC;
impl crate::RegisterSpec for SSLR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [sslr::R](R) reader structure"]
impl crate::Readable for SSLR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [sslr::W](W) writer structure"]
impl crate::Writable for SSLR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SSLR to value 0x01d6"]
impl crate::Resettable for SSLR_SPEC {
const RESET_VALUE: Self::Ux = 0x01d6;
}
}
#[doc = "FSHR (rw) register accessor: an alias for `Reg<FSHR_SPEC>`"]
pub type FSHR = crate::Reg<fshr::FSHR_SPEC>;
#[doc = "Fast/Super Fast Mode Clock High Count Register"]
pub mod fshr {
#[doc = "Register `FSHR` reader"]
pub struct R(crate::R<FSHR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSHR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSHR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSHR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSHR` writer"]
pub struct W(crate::W<FSHR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSHR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSHR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSHR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CNT` reader - "]
pub type CNT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CNT` writer - "]
pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FSHR_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn cnt(&self) -> CNT_R {
CNT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CNT_W<0> {
CNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Fast/Super Fast Mode Clock High Count Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fshr](index.html) module"]
pub struct FSHR_SPEC;
impl crate::RegisterSpec for FSHR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fshr::R](R) reader structure"]
impl crate::Readable for FSHR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fshr::W](W) writer structure"]
impl crate::Writable for FSHR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSHR to value 0x3c"]
impl crate::Resettable for FSHR_SPEC {
const RESET_VALUE: Self::Ux = 0x3c;
}
}
#[doc = "FSLR (rw) register accessor: an alias for `Reg<FSLR_SPEC>`"]
pub type FSLR = crate::Reg<fslr::FSLR_SPEC>;
#[doc = "Fast/Super Fast Mode Clock Low Count Register"]
pub mod fslr {
#[doc = "Register `FSLR` reader"]
pub struct R(crate::R<FSLR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSLR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSLR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSLR` writer"]
pub struct W(crate::W<FSLR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSLR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSLR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CNT` reader - "]
pub type CNT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CNT` writer - "]
pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FSLR_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn cnt(&self) -> CNT_R {
CNT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CNT_W<0> {
CNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Fast/Super Fast Mode Clock Low Count Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fslr](index.html) module"]
pub struct FSLR_SPEC;
impl crate::RegisterSpec for FSLR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fslr::R](R) reader structure"]
impl crate::Readable for FSLR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fslr::W](W) writer structure"]
impl crate::Writable for FSLR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSLR to value 0x82"]
impl crate::Resettable for FSLR_SPEC {
const RESET_VALUE: Self::Ux = 0x82;
}
}
#[doc = "ISR (r) register accessor: an alias for `Reg<ISR_SPEC>`"]
pub type ISR = crate::Reg<isr::ISR_SPEC>;
#[doc = "Interrupt Status Register"]
pub mod isr {
#[doc = "Register `ISR` reader"]
pub struct R(crate::R<ISR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ISR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ISR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ISR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `R_RX_UNDER` reader - "]
pub type R_RX_UNDER_R = crate::BitReader<bool>;
#[doc = "Field `R_RX_OVER` reader - "]
pub type R_RX_OVER_R = crate::BitReader<bool>;
#[doc = "Field `R_RX_FULL` reader - "]
pub type R_RX_FULL_R = crate::BitReader<bool>;
#[doc = "Field `R_TX_OVER` reader - "]
pub type R_TX_OVER_R = crate::BitReader<bool>;
#[doc = "Field `R_TX_EMPTY` reader - "]
pub type R_TX_EMPTY_R = crate::BitReader<bool>;
#[doc = "Field `R_RD_REQ` reader - "]
pub type R_RD_REQ_R = crate::BitReader<bool>;
#[doc = "Field `R_TX_ABRT` reader - "]
pub type R_TX_ABRT_R = crate::BitReader<bool>;
#[doc = "Field `R_RX_DONE` reader - "]
pub type R_RX_DONE_R = crate::BitReader<bool>;
#[doc = "Field `R_ACTIV` reader - "]
pub type R_ACTIV_R = crate::BitReader<bool>;
#[doc = "Field `R_STOP` reader - "]
pub type R_STOP_R = crate::BitReader<bool>;
#[doc = "Field `R_START` reader - "]
pub type R_START_R = crate::BitReader<bool>;
#[doc = "Field `R_GC` reader - "]
pub type R_GC_R = crate::BitReader<bool>;
#[doc = "Field `R_MST_ON_HOLD` reader - "]
pub type R_MST_ON_HOLD_R = crate::BitReader<bool>;
#[doc = "Field `R_SCL_STUCK_AT_LOW` reader - "]
pub type R_SCL_STUCK_AT_LOW_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn r_rx_under(&self) -> R_RX_UNDER_R {
R_RX_UNDER_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn r_rx_over(&self) -> R_RX_OVER_R {
R_RX_OVER_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn r_rx_full(&self) -> R_RX_FULL_R {
R_RX_FULL_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn r_tx_over(&self) -> R_TX_OVER_R {
R_TX_OVER_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn r_tx_empty(&self) -> R_TX_EMPTY_R {
R_TX_EMPTY_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn r_rd_req(&self) -> R_RD_REQ_R {
R_RD_REQ_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn r_tx_abrt(&self) -> R_TX_ABRT_R {
R_TX_ABRT_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn r_rx_done(&self) -> R_RX_DONE_R {
R_RX_DONE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn r_activ(&self) -> R_ACTIV_R {
R_ACTIV_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn r_stop(&self) -> R_STOP_R {
R_STOP_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn r_start(&self) -> R_START_R {
R_START_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn r_gc(&self) -> R_GC_R {
R_GC_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn r_mst_on_hold(&self) -> R_MST_ON_HOLD_R {
R_MST_ON_HOLD_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn r_scl_stuck_at_low(&self) -> R_SCL_STUCK_AT_LOW_R {
R_SCL_STUCK_AT_LOW_R::new(((self.bits >> 14) & 1) != 0)
}
}
#[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](index.html) module"]
pub struct ISR_SPEC;
impl crate::RegisterSpec for ISR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [isr::R](R) reader structure"]
impl crate::Readable for ISR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets ISR to value 0"]
impl crate::Resettable for ISR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "IMR (rw) register accessor: an alias for `Reg<IMR_SPEC>`"]
pub type IMR = crate::Reg<imr::IMR_SPEC>;
#[doc = "interrupt mask register"]
pub mod imr {
#[doc = "Register `IMR` reader"]
pub struct R(crate::R<IMR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IMR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IMR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IMR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IMR` writer"]
pub struct W(crate::W<IMR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IMR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IMR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IMR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `M_RX_UNDER` reader - "]
pub type M_RX_UNDER_R = crate::BitReader<bool>;
#[doc = "Field `M_RX_UNDER` writer - "]
pub type M_RX_UNDER_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMR_SPEC, bool, O>;
#[doc = "Field `M_RX_OVER` reader - "]
pub type M_RX_OVER_R = crate::BitReader<bool>;
#[doc = "Field `M_RX_OVER` writer - "]
pub type M_RX_OVER_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMR_SPEC, bool, O>;
#[doc = "Field `M_RX_FULL` reader - "]
pub type M_RX_FULL_R = crate::BitReader<bool>;
#[doc = "Field `M_RX_FULL` writer - "]
pub type M_RX_FULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMR_SPEC, bool, O>;
#[doc = "Field `M_TX_OVER` reader - "]
pub type M_TX_OVER_R = crate::BitReader<bool>;
#[doc = "Field `M_TX_OVER` writer - "]
pub type M_TX_OVER_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMR_SPEC, bool, O>;
#[doc = "Field `M_TX_EMPTY` reader - "]
pub type M_TX_EMPTY_R = crate::BitReader<bool>;
#[doc = "Field `M_TX_EMPTY` writer - "]
pub type M_TX_EMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMR_SPEC, bool, O>;
#[doc = "Field `M_RD_REQ` reader - "]
pub type M_RD_REQ_R = crate::BitReader<bool>;
#[doc = "Field `M_RD_REQ` writer - "]
pub type M_RD_REQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMR_SPEC, bool, O>;
#[doc = "Field `M_TX_ABRT` reader - "]
pub type M_TX_ABRT_R = crate::BitReader<bool>;
#[doc = "Field `M_TX_ABRT` writer - "]
pub type M_TX_ABRT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMR_SPEC, bool, O>;
#[doc = "Field `M_RX_DONE` reader - "]
pub type M_RX_DONE_R = crate::BitReader<bool>;
#[doc = "Field `M_RX_DONE` writer - "]
pub type M_RX_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMR_SPEC, bool, O>;
#[doc = "Field `M_ACTIV` reader - "]
pub type M_ACTIV_R = crate::BitReader<bool>;
#[doc = "Field `M_ACTIV` writer - "]
pub type M_ACTIV_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMR_SPEC, bool, O>;
#[doc = "Field `M_STOP` reader - "]
pub type M_STOP_R = crate::BitReader<bool>;
#[doc = "Field `M_STOP` writer - "]
pub type M_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMR_SPEC, bool, O>;
#[doc = "Field `M_START` reader - "]
pub type M_START_R = crate::BitReader<bool>;
#[doc = "Field `M_START` writer - "]
pub type M_START_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMR_SPEC, bool, O>;
#[doc = "Field `M_GC` reader - "]
pub type M_GC_R = crate::BitReader<bool>;
#[doc = "Field `M_GC` writer - "]
pub type M_GC_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMR_SPEC, bool, O>;
#[doc = "Field `M_MST_ON_HOLD` reader - "]
pub type M_MST_ON_HOLD_R = crate::BitReader<bool>;
#[doc = "Field `M_MST_ON_HOLD` writer - "]
pub type M_MST_ON_HOLD_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMR_SPEC, bool, O>;
#[doc = "Field `M_SCL_STUCK` reader - "]
pub type M_SCL_STUCK_R = crate::BitReader<bool>;
#[doc = "Field `M_SCL_STUCK` writer - "]
pub type M_SCL_STUCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn m_rx_under(&self) -> M_RX_UNDER_R {
M_RX_UNDER_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn m_rx_over(&self) -> M_RX_OVER_R {
M_RX_OVER_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn m_rx_full(&self) -> M_RX_FULL_R {
M_RX_FULL_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn m_tx_over(&self) -> M_TX_OVER_R {
M_TX_OVER_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn m_tx_empty(&self) -> M_TX_EMPTY_R {
M_TX_EMPTY_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn m_rd_req(&self) -> M_RD_REQ_R {
M_RD_REQ_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn m_tx_abrt(&self) -> M_TX_ABRT_R {
M_TX_ABRT_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn m_rx_done(&self) -> M_RX_DONE_R {
M_RX_DONE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn m_activ(&self) -> M_ACTIV_R {
M_ACTIV_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn m_stop(&self) -> M_STOP_R {
M_STOP_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn m_start(&self) -> M_START_R {
M_START_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn m_gc(&self) -> M_GC_R {
M_GC_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn m_mst_on_hold(&self) -> M_MST_ON_HOLD_R {
M_MST_ON_HOLD_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn m_scl_stuck(&self) -> M_SCL_STUCK_R {
M_SCL_STUCK_R::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn m_rx_under(&mut self) -> M_RX_UNDER_W<0> {
M_RX_UNDER_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn m_rx_over(&mut self) -> M_RX_OVER_W<1> {
M_RX_OVER_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn m_rx_full(&mut self) -> M_RX_FULL_W<2> {
M_RX_FULL_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn m_tx_over(&mut self) -> M_TX_OVER_W<3> {
M_TX_OVER_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn m_tx_empty(&mut self) -> M_TX_EMPTY_W<4> {
M_TX_EMPTY_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn m_rd_req(&mut self) -> M_RD_REQ_W<5> {
M_RD_REQ_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn m_tx_abrt(&mut self) -> M_TX_ABRT_W<6> {
M_TX_ABRT_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn m_rx_done(&mut self) -> M_RX_DONE_W<7> {
M_RX_DONE_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn m_activ(&mut self) -> M_ACTIV_W<8> {
M_ACTIV_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn m_stop(&mut self) -> M_STOP_W<9> {
M_STOP_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn m_start(&mut self) -> M_START_W<10> {
M_START_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn m_gc(&mut self) -> M_GC_W<11> {
M_GC_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn m_mst_on_hold(&mut self) -> M_MST_ON_HOLD_W<13> {
M_MST_ON_HOLD_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn m_scl_stuck(&mut self) -> M_SCL_STUCK_W<14> {
M_SCL_STUCK_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "interrupt mask register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"]
pub struct IMR_SPEC;
impl crate::RegisterSpec for IMR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [imr::R](R) reader structure"]
impl crate::Readable for IMR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [imr::W](W) writer structure"]
impl crate::Writable for IMR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IMR to value 0x48ff"]
impl crate::Resettable for IMR_SPEC {
const RESET_VALUE: Self::Ux = 0x48ff;
}
}
#[doc = "RAWISR (r) register accessor: an alias for `Reg<RAWISR_SPEC>`"]
pub type RAWISR = crate::Reg<rawisr::RAWISR_SPEC>;
#[doc = "RAW interrupt register"]
pub mod rawisr {
#[doc = "Register `RAWISR` reader"]
pub struct R(crate::R<RAWISR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RAWISR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RAWISR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RAWISR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `RX_UNDER` reader - "]
pub type RX_UNDER_R = crate::BitReader<bool>;
#[doc = "Field `RX_OVER` reader - "]
pub type RX_OVER_R = crate::BitReader<bool>;
#[doc = "Field `RX_FULL` reader - "]
pub type RX_FULL_R = crate::BitReader<bool>;
#[doc = "Field `TX_OVER` reader - "]
pub type TX_OVER_R = crate::BitReader<bool>;
#[doc = "Field `TX_EMPTY` reader - "]
pub type TX_EMPTY_R = crate::BitReader<bool>;
#[doc = "Field `RD_REQ` reader - "]
pub type RD_REQ_R = crate::BitReader<bool>;
#[doc = "Field `TX_ABRT` reader - "]
pub type TX_ABRT_R = crate::BitReader<bool>;
#[doc = "Field `RX_DONE` reader - "]
pub type RX_DONE_R = crate::BitReader<bool>;
#[doc = "Field `ACTIV` reader - "]
pub type ACTIV_R = crate::BitReader<bool>;
#[doc = "Field `STOP` reader - "]
pub type STOP_R = crate::BitReader<bool>;
#[doc = "Field `START` reader - "]
pub type START_R = crate::BitReader<bool>;
#[doc = "Field `GC` reader - "]
pub type GC_R = crate::BitReader<bool>;
#[doc = "Field `MST_ON_HOLD` reader - "]
pub type MST_ON_HOLD_R = crate::BitReader<bool>;
#[doc = "Field `SCL_STUCK` reader - "]
pub type SCL_STUCK_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn rx_under(&self) -> RX_UNDER_R {
RX_UNDER_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rx_over(&self) -> RX_OVER_R {
RX_OVER_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn rx_full(&self) -> RX_FULL_R {
RX_FULL_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn tx_over(&self) -> TX_OVER_R {
TX_OVER_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn tx_empty(&self) -> TX_EMPTY_R {
TX_EMPTY_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rd_req(&self) -> RD_REQ_R {
RD_REQ_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tx_abrt(&self) -> TX_ABRT_R {
TX_ABRT_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn rx_done(&self) -> RX_DONE_R {
RX_DONE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn activ(&self) -> ACTIV_R {
ACTIV_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn stop(&self) -> STOP_R {
STOP_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn start(&self) -> START_R {
START_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn gc(&self) -> GC_R {
GC_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn mst_on_hold(&self) -> MST_ON_HOLD_R {
MST_ON_HOLD_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn scl_stuck(&self) -> SCL_STUCK_R {
SCL_STUCK_R::new(((self.bits >> 14) & 1) != 0)
}
}
#[doc = "RAW interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rawisr](index.html) module"]
pub struct RAWISR_SPEC;
impl crate::RegisterSpec for RAWISR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rawisr::R](R) reader structure"]
impl crate::Readable for RAWISR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets RAWISR to value 0"]
impl crate::Resettable for RAWISR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RXTLR (rw) register accessor: an alias for `Reg<RXTLR_SPEC>`"]
pub type RXTLR = crate::Reg<rxtlr::RXTLR_SPEC>;
#[doc = "receive threshold register"]
pub mod rxtlr {
#[doc = "Register `RXTLR` reader"]
pub struct R(crate::R<RXTLR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RXTLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RXTLR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RXTLR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `RXTLR` writer"]
pub struct W(crate::W<RXTLR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<RXTLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<RXTLR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<RXTLR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TL` reader - "]
pub type TL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TL` writer - "]
pub type TL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RXTLR_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn tl(&self) -> TL_R {
TL_R::new((self.bits & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn tl(&mut self) -> TL_W<0> {
TL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "receive threshold register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxtlr](index.html) module"]
pub struct RXTLR_SPEC;
impl crate::RegisterSpec for RXTLR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rxtlr::R](R) reader structure"]
impl crate::Readable for RXTLR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [rxtlr::W](W) writer structure"]
impl crate::Writable for RXTLR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets RXTLR to value 0"]
impl crate::Resettable for RXTLR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "TXTLR (rw) register accessor: an alias for `Reg<TXTLR_SPEC>`"]
pub type TXTLR = crate::Reg<txtlr::TXTLR_SPEC>;
#[doc = "Transmit Threshold Register"]
pub mod txtlr {
#[doc = "Register `TXTLR` reader"]
pub struct R(crate::R<TXTLR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<TXTLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<TXTLR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<TXTLR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `TXTLR` writer"]
pub struct W(crate::W<TXTLR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<TXTLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<TXTLR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<TXTLR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TL` reader - "]
pub type TL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TL` writer - "]
pub type TL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TXTLR_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn tl(&self) -> TL_R {
TL_R::new((self.bits & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn tl(&mut self) -> TL_W<0> {
TL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Transmit Threshold Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txtlr](index.html) module"]
pub struct TXTLR_SPEC;
impl crate::RegisterSpec for TXTLR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [txtlr::R](R) reader structure"]
impl crate::Readable for TXTLR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [txtlr::W](W) writer structure"]
impl crate::Writable for TXTLR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets TXTLR to value 0"]
impl crate::Resettable for TXTLR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ICR (r) register accessor: an alias for `Reg<ICR_SPEC>`"]
pub type ICR = crate::Reg<icr::ICR_SPEC>;
#[doc = "Combined and Independent Interrupt Clear Registers"]
pub mod icr {
#[doc = "Register `ICR` reader"]
pub struct R(crate::R<ICR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ICR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ICR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ICR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `ICR` reader - "]
pub type ICR_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn icr(&self) -> ICR_R {
ICR_R::new((self.bits & 1) != 0)
}
}
#[doc = "Combined and Independent Interrupt Clear Registers\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](index.html) module"]
pub struct ICR_SPEC;
impl crate::RegisterSpec for ICR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [icr::R](R) reader structure"]
impl crate::Readable for ICR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets ICR to value 0"]
impl crate::Resettable for ICR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RX_UNDER (r) register accessor: an alias for `Reg<RX_UNDER_SPEC>`"]
pub type RX_UNDER = crate::Reg<rx_under::RX_UNDER_SPEC>;
#[doc = "Clear the RX_UNDER interrupt register"]
pub mod rx_under {
#[doc = "Register `RX_UNDER` reader"]
pub struct R(crate::R<RX_UNDER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RX_UNDER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RX_UNDER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RX_UNDER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `RX_UNDER` reader - "]
pub type RX_UNDER_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn rx_under(&self) -> RX_UNDER_R {
RX_UNDER_R::new((self.bits & 1) != 0)
}
}
#[doc = "Clear the RX_UNDER interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx_under](index.html) module"]
pub struct RX_UNDER_SPEC;
impl crate::RegisterSpec for RX_UNDER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rx_under::R](R) reader structure"]
impl crate::Readable for RX_UNDER_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets RX_UNDER to value 0"]
impl crate::Resettable for RX_UNDER_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RX_OVER (r) register accessor: an alias for `Reg<RX_OVER_SPEC>`"]
pub type RX_OVER = crate::Reg<rx_over::RX_OVER_SPEC>;
#[doc = "Clear the RX_OVER interrupt register"]
pub mod rx_over {
#[doc = "Register `RX_OVER` reader"]
pub struct R(crate::R<RX_OVER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RX_OVER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RX_OVER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RX_OVER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `RX_OVER` reader - "]
pub type RX_OVER_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn rx_over(&self) -> RX_OVER_R {
RX_OVER_R::new((self.bits & 1) != 0)
}
}
#[doc = "Clear the RX_OVER interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx_over](index.html) module"]
pub struct RX_OVER_SPEC;
impl crate::RegisterSpec for RX_OVER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rx_over::R](R) reader structure"]
impl crate::Readable for RX_OVER_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets RX_OVER to value 0"]
impl crate::Resettable for RX_OVER_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "TX_OVER (r) register accessor: an alias for `Reg<TX_OVER_SPEC>`"]
pub type TX_OVER = crate::Reg<tx_over::TX_OVER_SPEC>;
#[doc = "Clear the TX_OVER interrupt register"]
pub mod tx_over {
#[doc = "Register `TX_OVER` reader"]
pub struct R(crate::R<TX_OVER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<TX_OVER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<TX_OVER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<TX_OVER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `TX_OVER` reader - "]
pub type TX_OVER_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn tx_over(&self) -> TX_OVER_R {
TX_OVER_R::new((self.bits & 1) != 0)
}
}
#[doc = "Clear the TX_OVER interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx_over](index.html) module"]
pub struct TX_OVER_SPEC;
impl crate::RegisterSpec for TX_OVER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [tx_over::R](R) reader structure"]
impl crate::Readable for TX_OVER_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets TX_OVER to value 0"]
impl crate::Resettable for TX_OVER_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RD_REQ (r) register accessor: an alias for `Reg<RD_REQ_SPEC>`"]
pub type RD_REQ = crate::Reg<rd_req::RD_REQ_SPEC>;
#[doc = "Clear the RD_REQ interrupt register"]
pub mod rd_req {
#[doc = "Register `RD_REQ` reader"]
pub struct R(crate::R<RD_REQ_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RD_REQ_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RD_REQ_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RD_REQ_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `RD_REQ` reader - "]
pub type RD_REQ_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn rd_req(&self) -> RD_REQ_R {
RD_REQ_R::new((self.bits & 1) != 0)
}
}
#[doc = "Clear the RD_REQ interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rd_req](index.html) module"]
pub struct RD_REQ_SPEC;
impl crate::RegisterSpec for RD_REQ_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rd_req::R](R) reader structure"]
impl crate::Readable for RD_REQ_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets RD_REQ to value 0"]
impl crate::Resettable for RD_REQ_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "TX_ABRT (r) register accessor: an alias for `Reg<TX_ABRT_SPEC>`"]
pub type TX_ABRT = crate::Reg<tx_abrt::TX_ABRT_SPEC>;
#[doc = "Clear the TX_ABRT interrupt register"]
pub mod tx_abrt {
#[doc = "Register `TX_ABRT` reader"]
pub struct R(crate::R<TX_ABRT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<TX_ABRT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<TX_ABRT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<TX_ABRT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `TX_ABRT` reader - "]
pub type TX_ABRT_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn tx_abrt(&self) -> TX_ABRT_R {
TX_ABRT_R::new((self.bits & 1) != 0)
}
}
#[doc = "Clear the TX_ABRT interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx_abrt](index.html) module"]
pub struct TX_ABRT_SPEC;
impl crate::RegisterSpec for TX_ABRT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [tx_abrt::R](R) reader structure"]
impl crate::Readable for TX_ABRT_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets TX_ABRT to value 0"]
impl crate::Resettable for TX_ABRT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RX_DONE (r) register accessor: an alias for `Reg<RX_DONE_SPEC>`"]
pub type RX_DONE = crate::Reg<rx_done::RX_DONE_SPEC>;
#[doc = "Clear the RX_DONE interrupt register"]
pub mod rx_done {
#[doc = "Register `RX_DONE` reader"]
pub struct R(crate::R<RX_DONE_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RX_DONE_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RX_DONE_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RX_DONE_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `RX_DONE` reader - "]
pub type RX_DONE_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn rx_done(&self) -> RX_DONE_R {
RX_DONE_R::new((self.bits & 1) != 0)
}
}
#[doc = "Clear the RX_DONE interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rx_done](index.html) module"]
pub struct RX_DONE_SPEC;
impl crate::RegisterSpec for RX_DONE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rx_done::R](R) reader structure"]
impl crate::Readable for RX_DONE_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets RX_DONE to value 0"]
impl crate::Resettable for RX_DONE_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ACTIV (r) register accessor: an alias for `Reg<ACTIV_SPEC>`"]
pub type ACTIV = crate::Reg<activ::ACTIV_SPEC>;
#[doc = "Clear the ACTIVITY interrupt register"]
pub mod activ {
#[doc = "Register `ACTIV` reader"]
pub struct R(crate::R<ACTIV_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ACTIV_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ACTIV_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ACTIV_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `ACTIV` reader - "]
pub type ACTIV_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn activ(&self) -> ACTIV_R {
ACTIV_R::new((self.bits & 1) != 0)
}
}
#[doc = "Clear the ACTIVITY interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [activ](index.html) module"]
pub struct ACTIV_SPEC;
impl crate::RegisterSpec for ACTIV_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [activ::R](R) reader structure"]
impl crate::Readable for ACTIV_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets ACTIV to value 0"]
impl crate::Resettable for ACTIV_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "STOP (r) register accessor: an alias for `Reg<STOP_SPEC>`"]
pub type STOP = crate::Reg<stop::STOP_SPEC>;
#[doc = "Clear the STOP_DET interrupt register"]
pub mod stop {
#[doc = "Register `STOP` reader"]
pub struct R(crate::R<STOP_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<STOP_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<STOP_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<STOP_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `STOP` reader - "]
pub type STOP_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn stop(&self) -> STOP_R {
STOP_R::new((self.bits & 1) != 0)
}
}
#[doc = "Clear the STOP_DET interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stop](index.html) module"]
pub struct STOP_SPEC;
impl crate::RegisterSpec for STOP_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [stop::R](R) reader structure"]
impl crate::Readable for STOP_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets STOP to value 0"]
impl crate::Resettable for STOP_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "START (r) register accessor: an alias for `Reg<START_SPEC>`"]
pub type START = crate::Reg<start::START_SPEC>;
#[doc = "Clear the START_DET interrupt register"]
pub mod start {
#[doc = "Register `START` reader"]
pub struct R(crate::R<START_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<START_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<START_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<START_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `START` reader - "]
pub type START_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn start(&self) -> START_R {
START_R::new((self.bits & 1) != 0)
}
}
#[doc = "Clear the START_DET interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [start](index.html) module"]
pub struct START_SPEC;
impl crate::RegisterSpec for START_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [start::R](R) reader structure"]
impl crate::Readable for START_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets START to value 0"]
impl crate::Resettable for START_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "GC (r) register accessor: an alias for `Reg<GC_SPEC>`"]
pub type GC = crate::Reg<gc::GC_SPEC>;
#[doc = "Clear the GEN_CALL interrupt register"]
pub mod gc {
#[doc = "Register `GC` reader"]
pub struct R(crate::R<GC_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<GC_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<GC_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<GC_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `GC` reader - "]
pub type GC_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn gc(&self) -> GC_R {
GC_R::new((self.bits & 1) != 0)
}
}
#[doc = "Clear the GEN_CALL interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gc](index.html) module"]
pub struct GC_SPEC;
impl crate::RegisterSpec for GC_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [gc::R](R) reader structure"]
impl crate::Readable for GC_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets GC to value 0"]
impl crate::Resettable for GC_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ENR (rw) register accessor: an alias for `Reg<ENR_SPEC>`"]
pub type ENR = crate::Reg<enr::ENR_SPEC>;
#[doc = "enable register"]
pub mod enr {
#[doc = "Register `ENR` reader"]
pub struct R(crate::R<ENR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ENR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ENR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ENR` writer"]
pub struct W(crate::W<ENR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ENR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ENR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `ENABLE` reader - "]
pub type ENABLE_R = crate::BitReader<bool>;
#[doc = "Field `ENABLE` writer - "]
pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENR_SPEC, bool, O>;
#[doc = "Field `ABORT` reader - "]
pub type ABORT_R = crate::BitReader<bool>;
#[doc = "Field `ABORT` writer - "]
pub type ABORT_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENR_SPEC, bool, O>;
#[doc = "Field `TX_CMD_BLOCK` reader - "]
pub type TX_CMD_BLOCK_R = crate::BitReader<bool>;
#[doc = "Field `TX_CMD_BLOCK` writer - "]
pub type TX_CMD_BLOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENR_SPEC, bool, O>;
#[doc = "Field `SDA_RCV_EN` reader - "]
pub type SDA_RCV_EN_R = crate::BitReader<bool>;
#[doc = "Field `SDA_RCV_EN` writer - "]
pub type SDA_RCV_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENR_SPEC, bool, O>;
#[doc = "Field `SMB_CLK_RST` reader - "]
pub type SMB_CLK_RST_R = crate::BitReader<bool>;
#[doc = "Field `SMB_CLK_RST` writer - "]
pub type SMB_CLK_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENR_SPEC, bool, O>;
#[doc = "Field `SMB_ALT_EN` reader - "]
pub type SMB_ALT_EN_R = crate::BitReader<bool>;
#[doc = "Field `SMB_ALT_EN` writer - "]
pub type SMB_ALT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn enable(&self) -> ENABLE_R {
ENABLE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn abort(&self) -> ABORT_R {
ABORT_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn tx_cmd_block(&self) -> TX_CMD_BLOCK_R {
TX_CMD_BLOCK_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn sda_rcv_en(&self) -> SDA_RCV_EN_R {
SDA_RCV_EN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn smb_clk_rst(&self) -> SMB_CLK_RST_R {
SMB_CLK_RST_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn smb_alt_en(&self) -> SMB_ALT_EN_R {
SMB_ALT_EN_R::new(((self.bits >> 18) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn enable(&mut self) -> ENABLE_W<0> {
ENABLE_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn abort(&mut self) -> ABORT_W<1> {
ABORT_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn tx_cmd_block(&mut self) -> TX_CMD_BLOCK_W<2> {
TX_CMD_BLOCK_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn sda_rcv_en(&mut self) -> SDA_RCV_EN_W<3> {
SDA_RCV_EN_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn smb_clk_rst(&mut self) -> SMB_CLK_RST_W<16> {
SMB_CLK_RST_W::new(self)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn smb_alt_en(&mut self) -> SMB_ALT_EN_W<18> {
SMB_ALT_EN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enr](index.html) module"]
pub struct ENR_SPEC;
impl crate::RegisterSpec for ENR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [enr::R](R) reader structure"]
impl crate::Readable for ENR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [enr::W](W) writer structure"]
impl crate::Writable for ENR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ENR to value 0"]
impl crate::Resettable for ENR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SR (r) register accessor: an alias for `Reg<SR_SPEC>`"]
pub type SR = crate::Reg<sr::SR_SPEC>;
#[doc = "status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub struct R(crate::R<SR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `ACTIV` reader - "]
pub type ACTIV_R = crate::BitReader<bool>;
#[doc = "Field `TFNF` reader - "]
pub type TFNF_R = crate::BitReader<bool>;
#[doc = "Field `TFE` reader - "]
pub type TFE_R = crate::BitReader<bool>;
#[doc = "Field `RFNE` reader - "]
pub type RFNE_R = crate::BitReader<bool>;
#[doc = "Field `RFF` reader - "]
pub type RFF_R = crate::BitReader<bool>;
#[doc = "Field `MST_ACTIV` reader - "]
pub type MST_ACTIV_R = crate::BitReader<bool>;
#[doc = "Field `SLV_ACTIV` reader - "]
pub type SLV_ACTIV_R = crate::BitReader<bool>;
#[doc = "Field `MST_HOLD_TX_EMPTY` reader - "]
pub type MST_HOLD_TX_EMPTY_R = crate::BitReader<bool>;
#[doc = "Field `MST_HOLD_RX_FULL` reader - "]
pub type MST_HOLD_RX_FULL_R = crate::BitReader<bool>;
#[doc = "Field `SLV_HOLD_TX_EMPTY` reader - "]
pub type SLV_HOLD_TX_EMPTY_R = crate::BitReader<bool>;
#[doc = "Field `SLV_HOLD_RX_FULL` reader - "]
pub type SLV_HOLD_RX_FULL_R = crate::BitReader<bool>;
#[doc = "Field `SDA_NOT_RECOVERED` reader - "]
pub type SDA_NOT_RECOVERED_R = crate::BitReader<bool>;
#[doc = "Field `SMB_QC` reader - "]
pub type SMB_QC_R = crate::BitReader<bool>;
#[doc = "Field `SMB_SLV_AV` reader - "]
pub type SMB_SLV_AV_R = crate::BitReader<bool>;
#[doc = "Field `SMB_SLV_AR` reader - "]
pub type SMB_SLV_AR_R = crate::BitReader<bool>;
#[doc = "Field `SMB_ALT` reader - "]
pub type SMB_ALT_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn activ(&self) -> ACTIV_R {
ACTIV_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn tfnf(&self) -> TFNF_R {
TFNF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn tfe(&self) -> TFE_R {
TFE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rfne(&self) -> RFNE_R {
RFNE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn rff(&self) -> RFF_R {
RFF_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn mst_activ(&self) -> MST_ACTIV_R {
MST_ACTIV_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn slv_activ(&self) -> SLV_ACTIV_R {
SLV_ACTIV_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn mst_hold_tx_empty(&self) -> MST_HOLD_TX_EMPTY_R {
MST_HOLD_TX_EMPTY_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn mst_hold_rx_full(&self) -> MST_HOLD_RX_FULL_R {
MST_HOLD_RX_FULL_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn slv_hold_tx_empty(&self) -> SLV_HOLD_TX_EMPTY_R {
SLV_HOLD_TX_EMPTY_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn slv_hold_rx_full(&self) -> SLV_HOLD_RX_FULL_R {
SLV_HOLD_RX_FULL_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn sda_not_recovered(&self) -> SDA_NOT_RECOVERED_R {
SDA_NOT_RECOVERED_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn smb_qc(&self) -> SMB_QC_R {
SMB_QC_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn smb_slv_av(&self) -> SMB_SLV_AV_R {
SMB_SLV_AV_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn smb_slv_ar(&self) -> SMB_SLV_AR_R {
SMB_SLV_AR_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn smb_alt(&self) -> SMB_ALT_R {
SMB_ALT_R::new(((self.bits >> 20) & 1) != 0)
}
}
#[doc = "status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"]
pub struct SR_SPEC;
impl crate::RegisterSpec for SR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [sr::R](R) reader structure"]
impl crate::Readable for SR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets SR to value 0x06"]
impl crate::Resettable for SR_SPEC {
const RESET_VALUE: Self::Ux = 0x06;
}
}
#[doc = "TXFLR (r) register accessor: an alias for `Reg<TXFLR_SPEC>`"]
pub type TXFLR = crate::Reg<txflr::TXFLR_SPEC>;
#[doc = "Transmit buffer level register"]
pub mod txflr {
#[doc = "Register `TXFLR` reader"]
pub struct R(crate::R<TXFLR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<TXFLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<TXFLR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<TXFLR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `CNT` reader - "]
pub type CNT_R = crate::FieldReader<u8, u8>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn cnt(&self) -> CNT_R {
CNT_R::new((self.bits & 7) as u8)
}
}
#[doc = "Transmit buffer level register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txflr](index.html) module"]
pub struct TXFLR_SPEC;
impl crate::RegisterSpec for TXFLR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [txflr::R](R) reader structure"]
impl crate::Readable for TXFLR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets TXFLR to value 0"]
impl crate::Resettable for TXFLR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RXFLR (r) register accessor: an alias for `Reg<RXFLR_SPEC>`"]
pub type RXFLR = crate::Reg<rxflr::RXFLR_SPEC>;
#[doc = "Receive buffer level register"]
pub mod rxflr {
#[doc = "Register `RXFLR` reader"]
pub struct R(crate::R<RXFLR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RXFLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RXFLR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RXFLR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `CNT` reader - "]
pub type CNT_R = crate::FieldReader<u8, u8>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn cnt(&self) -> CNT_R {
CNT_R::new((self.bits & 7) as u8)
}
}
#[doc = "Receive buffer level register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxflr](index.html) module"]
pub struct RXFLR_SPEC;
impl crate::RegisterSpec for RXFLR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rxflr::R](R) reader structure"]
impl crate::Readable for RXFLR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets RXFLR to value 0"]
impl crate::Resettable for RXFLR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "HOLD (rw) register accessor: an alias for `Reg<HOLD_SPEC>`"]
pub type HOLD = crate::Reg<hold::HOLD_SPEC>;
#[doc = "SDA hold time register"]
pub mod hold {
#[doc = "Register `HOLD` reader"]
pub struct R(crate::R<HOLD_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<HOLD_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<HOLD_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<HOLD_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `HOLD` writer"]
pub struct W(crate::W<HOLD_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<HOLD_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<HOLD_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<HOLD_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TX_HOLD` reader - "]
pub type TX_HOLD_R = crate::FieldReader<u16, u16>;
#[doc = "Field `TX_HOLD` writer - "]
pub type TX_HOLD_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, HOLD_SPEC, u16, u16, 16, O>;
#[doc = "Field `RX_HOLD` reader - "]
pub type RX_HOLD_R = crate::FieldReader<u8, u8>;
#[doc = "Field `RX_HOLD` writer - "]
pub type RX_HOLD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HOLD_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn tx_hold(&self) -> TX_HOLD_R {
TX_HOLD_R::new((self.bits & 0xffff) as u16)
}
#[doc = "Bits 16:23"]
#[inline(always)]
pub fn rx_hold(&self) -> RX_HOLD_R {
RX_HOLD_R::new(((self.bits >> 16) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn tx_hold(&mut self) -> TX_HOLD_W<0> {
TX_HOLD_W::new(self)
}
#[doc = "Bits 16:23"]
#[inline(always)]
#[must_use]
pub fn rx_hold(&mut self) -> RX_HOLD_W<16> {
RX_HOLD_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "SDA hold time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hold](index.html) module"]
pub struct HOLD_SPEC;
impl crate::RegisterSpec for HOLD_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [hold::R](R) reader structure"]
impl crate::Readable for HOLD_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [hold::W](W) writer structure"]
impl crate::Writable for HOLD_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets HOLD to value 0x01"]
impl crate::Resettable for HOLD_SPEC {
const RESET_VALUE: Self::Ux = 0x01;
}
}
#[doc = "TX_ABRT_SRC (r) register accessor: an alias for `Reg<TX_ABRT_SRC_SPEC>`"]
pub type TX_ABRT_SRC = crate::Reg<tx_abrt_src::TX_ABRT_SRC_SPEC>;
#[doc = "Transfer Abort Source Register"]
pub mod tx_abrt_src {
#[doc = "Register `TX_ABRT_SRC` reader"]
pub struct R(crate::R<TX_ABRT_SRC_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<TX_ABRT_SRC_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<TX_ABRT_SRC_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<TX_ABRT_SRC_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `7ADDR_NOACK` reader - "]
pub type _7ADDR_NOACK_R = crate::BitReader<bool>;
#[doc = "Field `10ADDR1_NOACK` reader - "]
pub type _10ADDR1_NOACK_R = crate::BitReader<bool>;
#[doc = "Field `10ADDR2_NOACK` reader - "]
pub type _10ADDR2_NOACK_R = crate::BitReader<bool>;
#[doc = "Field `TXDATA_NOACK` reader - "]
pub type TXDATA_NOACK_R = crate::BitReader<bool>;
#[doc = "Field `GC_NOACK` reader - "]
pub type GC_NOACK_R = crate::BitReader<bool>;
#[doc = "Field `GC_READ` reader - "]
pub type GC_READ_R = crate::BitReader<bool>;
#[doc = "Field `SBYTE_ACKDET` reader - "]
pub type SBYTE_ACKDET_R = crate::BitReader<bool>;
#[doc = "Field `SBYTE_NORSTRT` reader - "]
pub type SBYTE_NORSTRT_R = crate::BitReader<bool>;
#[doc = "Field `10B_RD_NORSTRT` reader - "]
pub type _10B_RD_NORSTRT_R = crate::BitReader<bool>;
#[doc = "Field `MST_DIS` reader - "]
pub type MST_DIS_R = crate::BitReader<bool>;
#[doc = "Field `LOST` reader - "]
pub type LOST_R = crate::BitReader<bool>;
#[doc = "Field `SLVFLUSH_TXFIFO` reader - "]
pub type SLVFLUSH_TXFIFO_R = crate::BitReader<bool>;
#[doc = "Field `SLV_ARBLOST` reader - "]
pub type SLV_ARBLOST_R = crate::BitReader<bool>;
#[doc = "Field `SLVRD_INTX` reader - "]
pub type SLVRD_INTX_R = crate::BitReader<bool>;
#[doc = "Field `USER_ABRT` reader - "]
pub type USER_ABRT_R = crate::BitReader<bool>;
#[doc = "Field `SDA_LOW` reader - "]
pub type SDA_LOW_R = crate::BitReader<bool>;
#[doc = "Field `TX_FLUSH_CNT` reader - "]
pub type TX_FLUSH_CNT_R = crate::FieldReader<u16, u16>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn _7addr_noack(&self) -> _7ADDR_NOACK_R {
_7ADDR_NOACK_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn _10addr1_noack(&self) -> _10ADDR1_NOACK_R {
_10ADDR1_NOACK_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn _10addr2_noack(&self) -> _10ADDR2_NOACK_R {
_10ADDR2_NOACK_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn txdata_noack(&self) -> TXDATA_NOACK_R {
TXDATA_NOACK_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn gc_noack(&self) -> GC_NOACK_R {
GC_NOACK_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn gc_read(&self) -> GC_READ_R {
GC_READ_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn sbyte_ackdet(&self) -> SBYTE_ACKDET_R {
SBYTE_ACKDET_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn sbyte_norstrt(&self) -> SBYTE_NORSTRT_R {
SBYTE_NORSTRT_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn _10b_rd_norstrt(&self) -> _10B_RD_NORSTRT_R {
_10B_RD_NORSTRT_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn mst_dis(&self) -> MST_DIS_R {
MST_DIS_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn lost(&self) -> LOST_R {
LOST_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn slvflush_txfifo(&self) -> SLVFLUSH_TXFIFO_R {
SLVFLUSH_TXFIFO_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn slv_arblost(&self) -> SLV_ARBLOST_R {
SLV_ARBLOST_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn slvrd_intx(&self) -> SLVRD_INTX_R {
SLVRD_INTX_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn user_abrt(&self) -> USER_ABRT_R {
USER_ABRT_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn sda_low(&self) -> SDA_LOW_R {
SDA_LOW_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bits 23:31"]
#[inline(always)]
pub fn tx_flush_cnt(&self) -> TX_FLUSH_CNT_R {
TX_FLUSH_CNT_R::new(((self.bits >> 23) & 0x01ff) as u16)
}
}
#[doc = "Transfer Abort Source Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tx_abrt_src](index.html) module"]
pub struct TX_ABRT_SRC_SPEC;
impl crate::RegisterSpec for TX_ABRT_SRC_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [tx_abrt_src::R](R) reader structure"]
impl crate::Readable for TX_ABRT_SRC_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets TX_ABRT_SRC to value 0"]
impl crate::Resettable for TX_ABRT_SRC_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SLV_NACK (rw) register accessor: an alias for `Reg<SLV_NACK_SPEC>`"]
pub type SLV_NACK = crate::Reg<slv_nack::SLV_NACK_SPEC>;
#[doc = "Slave Receive NACK Register"]
pub mod slv_nack {
#[doc = "Register `SLV_NACK` reader"]
pub struct R(crate::R<SLV_NACK_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SLV_NACK_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SLV_NACK_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SLV_NACK_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SLV_NACK` writer"]
pub struct W(crate::W<SLV_NACK_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SLV_NACK_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SLV_NACK_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SLV_NACK_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `NACK` reader - "]
pub type NACK_R = crate::BitReader<bool>;
#[doc = "Field `NACK` writer - "]
pub type NACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, SLV_NACK_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn nack(&self) -> NACK_R {
NACK_R::new((self.bits & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn nack(&mut self) -> NACK_W<0> {
NACK_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Slave Receive NACK Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slv_nack](index.html) module"]
pub struct SLV_NACK_SPEC;
impl crate::RegisterSpec for SLV_NACK_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [slv_nack::R](R) reader structure"]
impl crate::Readable for SLV_NACK_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [slv_nack::W](W) writer structure"]
impl crate::Writable for SLV_NACK_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SLV_NACK to value 0"]
impl crate::Resettable for SLV_NACK_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMA (rw) register accessor: an alias for `Reg<DMA_SPEC>`"]
pub type DMA = crate::Reg<dma::DMA_SPEC>;
#[doc = "DMA Control Register"]
pub mod dma {
#[doc = "Register `DMA` reader"]
pub struct R(crate::R<DMA_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMA_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMA_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMA_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DMA` writer"]
pub struct W(crate::W<DMA_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DMA_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DMA_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DMA_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RXEN` reader - "]
pub type RXEN_R = crate::BitReader<bool>;
#[doc = "Field `RXEN` writer - "]
pub type RXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMA_SPEC, bool, O>;
#[doc = "Field `TXEN` reader - "]
pub type TXEN_R = crate::BitReader<bool>;
#[doc = "Field `TXEN` writer - "]
pub type TXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMA_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn rxen(&self) -> RXEN_R {
RXEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn txen(&self) -> TXEN_R {
TXEN_R::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn rxen(&mut self) -> RXEN_W<0> {
RXEN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn txen(&mut self) -> TXEN_W<1> {
TXEN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma](index.html) module"]
pub struct DMA_SPEC;
impl crate::RegisterSpec for DMA_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dma::R](R) reader structure"]
impl crate::Readable for DMA_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dma::W](W) writer structure"]
impl crate::Writable for DMA_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DMA to value 0"]
impl crate::Resettable for DMA_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SETUP (rw) register accessor: an alias for `Reg<SETUP_SPEC>`"]
pub type SETUP = crate::Reg<setup::SETUP_SPEC>;
#[doc = "SDA setup time register"]
pub mod setup {
#[doc = "Register `SETUP` reader"]
pub struct R(crate::R<SETUP_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SETUP_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SETUP_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SETUP_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SETUP` writer"]
pub struct W(crate::W<SETUP_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SETUP_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SETUP_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SETUP_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CNT` reader - "]
pub type CNT_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNT` writer - "]
pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SETUP_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn cnt(&self) -> CNT_R {
CNT_R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CNT_W<0> {
CNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "SDA setup time register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [setup](index.html) module"]
pub struct SETUP_SPEC;
impl crate::RegisterSpec for SETUP_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [setup::R](R) reader structure"]
impl crate::Readable for SETUP_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [setup::W](W) writer structure"]
impl crate::Writable for SETUP_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SETUP to value 0x64"]
impl crate::Resettable for SETUP_SPEC {
const RESET_VALUE: Self::Ux = 0x64;
}
}
#[doc = "GCR (rw) register accessor: an alias for `Reg<GCR_SPEC>`"]
pub type GCR = crate::Reg<gcr::GCR_SPEC>;
#[doc = "General Call ACK Register"]
pub mod gcr {
#[doc = "Register `GCR` reader"]
pub struct R(crate::R<GCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<GCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<GCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<GCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `GCR` writer"]
pub struct W(crate::W<GCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<GCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<GCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<GCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `GC` reader - "]
pub type GC_R = crate::BitReader<bool>;
#[doc = "Field `GC` writer - "]
pub type GC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn gc(&self) -> GC_R {
GC_R::new((self.bits & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn gc(&mut self) -> GC_W<0> {
GC_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "General Call ACK Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gcr](index.html) module"]
pub struct GCR_SPEC;
impl crate::RegisterSpec for GCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [gcr::R](R) reader structure"]
impl crate::Readable for GCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [gcr::W](W) writer structure"]
impl crate::Writable for GCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets GCR to value 0x01"]
impl crate::Resettable for GCR_SPEC {
const RESET_VALUE: Self::Ux = 0x01;
}
}
#[doc = "EN_SR (r) register accessor: an alias for `Reg<EN_SR_SPEC>`"]
pub type EN_SR = crate::Reg<en_sr::EN_SR_SPEC>;
#[doc = "ENABLE Status Register"]
pub mod en_sr {
#[doc = "Register `EN_SR` reader"]
pub struct R(crate::R<EN_SR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<EN_SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<EN_SR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<EN_SR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `IC_EN` reader - "]
pub type IC_EN_R = crate::BitReader<bool>;
#[doc = "Field `SLV_DIS_WHILE_BUSY` reader - "]
pub type SLV_DIS_WHILE_BUSY_R = crate::BitReader<bool>;
#[doc = "Field `SLV_RX_DATA_LOST` reader - "]
pub type SLV_RX_DATA_LOST_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn ic_en(&self) -> IC_EN_R {
IC_EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn slv_dis_while_busy(&self) -> SLV_DIS_WHILE_BUSY_R {
SLV_DIS_WHILE_BUSY_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn slv_rx_data_lost(&self) -> SLV_RX_DATA_LOST_R {
SLV_RX_DATA_LOST_R::new(((self.bits >> 2) & 1) != 0)
}
}
#[doc = "ENABLE Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [en_sr](index.html) module"]
pub struct EN_SR_SPEC;
impl crate::RegisterSpec for EN_SR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [en_sr::R](R) reader structure"]
impl crate::Readable for EN_SR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets EN_SR to value 0"]
impl crate::Resettable for EN_SR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SPKLEN (rw) register accessor: an alias for `Reg<SPKLEN_SPEC>`"]
pub type SPKLEN = crate::Reg<spklen::SPKLEN_SPEC>;
#[doc = "filter register"]
pub mod spklen {
#[doc = "Register `SPKLEN` reader"]
pub struct R(crate::R<SPKLEN_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SPKLEN_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SPKLEN_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SPKLEN_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SPKLEN` writer"]
pub struct W(crate::W<SPKLEN_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SPKLEN_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SPKLEN_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SPKLEN_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SPKLEN` reader - "]
pub type SPKLEN_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SPKLEN` writer - "]
pub type SPKLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SPKLEN_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn spklen(&self) -> SPKLEN_R {
SPKLEN_R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn spklen(&mut self) -> SPKLEN_W<0> {
SPKLEN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "filter register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spklen](index.html) module"]
pub struct SPKLEN_SPEC;
impl crate::RegisterSpec for SPKLEN_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [spklen::R](R) reader structure"]
impl crate::Readable for SPKLEN_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [spklen::W](W) writer structure"]
impl crate::Writable for SPKLEN_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SPKLEN to value 0x05"]
impl crate::Resettable for SPKLEN_SPEC {
const RESET_VALUE: Self::Ux = 0x05;
}
}
#[doc = "SCL_TMO (rw) register accessor: an alias for `Reg<SCL_TMO_SPEC>`"]
pub type SCL_TMO = crate::Reg<scl_tmo::SCL_TMO_SPEC>;
#[doc = "SCL Low Timeout Register"]
pub mod scl_tmo {
#[doc = "Register `SCL_TMO` reader"]
pub struct R(crate::R<SCL_TMO_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SCL_TMO_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SCL_TMO_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SCL_TMO_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SCL_TMO` writer"]
pub struct W(crate::W<SCL_TMO_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SCL_TMO_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SCL_TMO_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SCL_TMO_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SCL_TIMEOUT` reader - "]
pub type SCL_TIMEOUT_R = crate::FieldReader<u32, u32>;
#[doc = "Field `SCL_TIMEOUT` writer - "]
pub type SCL_TIMEOUT_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SCL_TMO_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn scl_timeout(&self) -> SCL_TIMEOUT_R {
SCL_TIMEOUT_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn scl_timeout(&mut self) -> SCL_TIMEOUT_W<0> {
SCL_TIMEOUT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "SCL Low Timeout Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scl_tmo](index.html) module"]
pub struct SCL_TMO_SPEC;
impl crate::RegisterSpec for SCL_TMO_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [scl_tmo::R](R) reader structure"]
impl crate::Readable for SCL_TMO_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [scl_tmo::W](W) writer structure"]
impl crate::Writable for SCL_TMO_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SCL_TMO to value 0xffff_ffff"]
impl crate::Resettable for SCL_TMO_SPEC {
const RESET_VALUE: Self::Ux = 0xffff_ffff;
}
}
#[doc = "SDA_TMO (rw) register accessor: an alias for `Reg<SDA_TMO_SPEC>`"]
pub type SDA_TMO = crate::Reg<sda_tmo::SDA_TMO_SPEC>;
#[doc = "SDA Low Timeout Register"]
pub mod sda_tmo {
#[doc = "Register `SDA_TMO` reader"]
pub struct R(crate::R<SDA_TMO_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SDA_TMO_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SDA_TMO_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SDA_TMO_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SDA_TMO` writer"]
pub struct W(crate::W<SDA_TMO_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SDA_TMO_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SDA_TMO_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SDA_TMO_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SDA_TIMEOUT` reader - "]
pub type SDA_TIMEOUT_R = crate::FieldReader<u32, u32>;
#[doc = "Field `SDA_TIMEOUT` writer - "]
pub type SDA_TIMEOUT_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SDA_TMO_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn sda_timeout(&self) -> SDA_TIMEOUT_R {
SDA_TIMEOUT_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn sda_timeout(&mut self) -> SDA_TIMEOUT_W<0> {
SDA_TIMEOUT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "SDA Low Timeout Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sda_tmo](index.html) module"]
pub struct SDA_TMO_SPEC;
impl crate::RegisterSpec for SDA_TMO_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [sda_tmo::R](R) reader structure"]
impl crate::Readable for SDA_TMO_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [sda_tmo::W](W) writer structure"]
impl crate::Writable for SDA_TMO_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SDA_TMO to value 0xffff_ffff"]
impl crate::Resettable for SDA_TMO_SPEC {
const RESET_VALUE: Self::Ux = 0xffff_ffff;
}
}
#[doc = "SCL_STUCK (r) register accessor: an alias for `Reg<SCL_STUCK_SPEC>`"]
pub type SCL_STUCK = crate::Reg<scl_stuck::SCL_STUCK_SPEC>;
#[doc = "Clear the SCL_STUCK interrupt register"]
pub mod scl_stuck {
#[doc = "Register `SCL_STUCK` reader"]
pub struct R(crate::R<SCL_STUCK_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SCL_STUCK_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SCL_STUCK_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SCL_STUCK_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `SCL_STUCK` reader - "]
pub type SCL_STUCK_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn scl_stuck(&self) -> SCL_STUCK_R {
SCL_STUCK_R::new((self.bits & 1) != 0)
}
}
#[doc = "Clear the SCL_STUCK interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scl_stuck](index.html) module"]
pub struct SCL_STUCK_SPEC;
impl crate::RegisterSpec for SCL_STUCK_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [scl_stuck::R](R) reader structure"]
impl crate::Readable for SCL_STUCK_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets SCL_STUCK to value 0"]
impl crate::Resettable for SCL_STUCK_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SMB_SEXT (rw) register accessor: an alias for `Reg<SMB_SEXT_SPEC>`"]
pub type SMB_SEXT = crate::Reg<smb_sext::SMB_SEXT_SPEC>;
#[doc = "SMBus Slave Clock Stretching Timeout Register"]
pub mod smb_sext {
#[doc = "Register `SMB_SEXT` reader"]
pub struct R(crate::R<SMB_SEXT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SMB_SEXT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SMB_SEXT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SMB_SEXT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SMB_SEXT` writer"]
pub struct W(crate::W<SMB_SEXT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SMB_SEXT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SMB_SEXT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SMB_SEXT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SMB_SEXT` reader - "]
pub type SMB_SEXT_R = crate::FieldReader<u32, u32>;
#[doc = "Field `SMB_SEXT` writer - "]
pub type SMB_SEXT_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SMB_SEXT_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn smb_sext(&self) -> SMB_SEXT_R {
SMB_SEXT_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn smb_sext(&mut self) -> SMB_SEXT_W<0> {
SMB_SEXT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "SMBus Slave Clock Stretching Timeout Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smb_sext](index.html) module"]
pub struct SMB_SEXT_SPEC;
impl crate::RegisterSpec for SMB_SEXT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [smb_sext::R](R) reader structure"]
impl crate::Readable for SMB_SEXT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [smb_sext::W](W) writer structure"]
impl crate::Writable for SMB_SEXT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SMB_SEXT to value 0xffff_ffff"]
impl crate::Resettable for SMB_SEXT_SPEC {
const RESET_VALUE: Self::Ux = 0xffff_ffff;
}
}
#[doc = "SMB_MEXT (rw) register accessor: an alias for `Reg<SMB_MEXT_SPEC>`"]
pub type SMB_MEXT = crate::Reg<smb_mext::SMB_MEXT_SPEC>;
#[doc = "SMBus Master Clock Stretching Timeout Register"]
pub mod smb_mext {
#[doc = "Register `SMB_MEXT` reader"]
pub struct R(crate::R<SMB_MEXT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SMB_MEXT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SMB_MEXT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SMB_MEXT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SMB_MEXT` writer"]
pub struct W(crate::W<SMB_MEXT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SMB_MEXT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SMB_MEXT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SMB_MEXT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SMB_MEXT` reader - "]
pub type SMB_MEXT_R = crate::FieldReader<u32, u32>;
#[doc = "Field `SMB_MEXT` writer - "]
pub type SMB_MEXT_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SMB_MEXT_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn smb_mext(&self) -> SMB_MEXT_R {
SMB_MEXT_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn smb_mext(&mut self) -> SMB_MEXT_W<0> {
SMB_MEXT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "SMBus Master Clock Stretching Timeout Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smb_mext](index.html) module"]
pub struct SMB_MEXT_SPEC;
impl crate::RegisterSpec for SMB_MEXT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [smb_mext::R](R) reader structure"]
impl crate::Readable for SMB_MEXT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [smb_mext::W](W) writer structure"]
impl crate::Writable for SMB_MEXT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SMB_MEXT to value 0xffff_ffff"]
impl crate::Resettable for SMB_MEXT_SPEC {
const RESET_VALUE: Self::Ux = 0xffff_ffff;
}
}
#[doc = "SMB_IDLE (rw) register accessor: an alias for `Reg<SMB_IDLE_SPEC>`"]
pub type SMB_IDLE = crate::Reg<smb_idle::SMB_IDLE_SPEC>;
#[doc = "SMBus Bus Idle Count Register"]
pub mod smb_idle {
#[doc = "Register `SMB_IDLE` reader"]
pub struct R(crate::R<SMB_IDLE_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SMB_IDLE_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SMB_IDLE_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SMB_IDLE_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SMB_IDLE` writer"]
pub struct W(crate::W<SMB_IDLE_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SMB_IDLE_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SMB_IDLE_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SMB_IDLE_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SMB_IDLE_CNT` reader - "]
pub type SMB_IDLE_CNT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `SMB_IDLE_CNT` writer - "]
pub type SMB_IDLE_CNT_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SMB_IDLE_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn smb_idle_cnt(&self) -> SMB_IDLE_CNT_R {
SMB_IDLE_CNT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn smb_idle_cnt(&mut self) -> SMB_IDLE_CNT_W<0> {
SMB_IDLE_CNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "SMBus Bus Idle Count Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smb_idle](index.html) module"]
pub struct SMB_IDLE_SPEC;
impl crate::RegisterSpec for SMB_IDLE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [smb_idle::R](R) reader structure"]
impl crate::Readable for SMB_IDLE_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [smb_idle::W](W) writer structure"]
impl crate::Writable for SMB_IDLE_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SMB_IDLE to value 0xffff"]
impl crate::Resettable for SMB_IDLE_SPEC {
const RESET_VALUE: Self::Ux = 0xffff;
}
}
#[doc = "SMB_ISR (r) register accessor: an alias for `Reg<SMB_ISR_SPEC>`"]
pub type SMB_ISR = crate::Reg<smb_isr::SMB_ISR_SPEC>;
#[doc = "SMBus Interrupt Status Register"]
pub mod smb_isr {
#[doc = "Register `SMB_ISR` reader"]
pub struct R(crate::R<SMB_ISR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SMB_ISR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SMB_ISR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SMB_ISR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `R_SLV_TMO` reader - "]
pub type R_SLV_TMO_R = crate::BitReader<bool>;
#[doc = "Field `R_MST_TMO` reader - "]
pub type R_MST_TMO_R = crate::BitReader<bool>;
#[doc = "Field `R_ARP_QUICK` reader - "]
pub type R_ARP_QUICK_R = crate::BitReader<bool>;
#[doc = "Field `R_ARP_NOTIFY` reader - "]
pub type R_ARP_NOTIFY_R = crate::BitReader<bool>;
#[doc = "Field `R_ARP_PRE` reader - "]
pub type R_ARP_PRE_R = crate::BitReader<bool>;
#[doc = "Field `R_ARP_RST` reader - "]
pub type R_ARP_RST_R = crate::BitReader<bool>;
#[doc = "Field `R_ARP_UDID` reader - "]
pub type R_ARP_UDID_R = crate::BitReader<bool>;
#[doc = "Field `R_ARP_ASSGN` reader - "]
pub type R_ARP_ASSGN_R = crate::BitReader<bool>;
#[doc = "Field `R_PEC_NACK` reader - "]
pub type R_PEC_NACK_R = crate::BitReader<bool>;
#[doc = "Field `R_SMB_ALT` reader - "]
pub type R_SMB_ALT_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn r_slv_tmo(&self) -> R_SLV_TMO_R {
R_SLV_TMO_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn r_mst_tmo(&self) -> R_MST_TMO_R {
R_MST_TMO_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn r_arp_quick(&self) -> R_ARP_QUICK_R {
R_ARP_QUICK_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn r_arp_notify(&self) -> R_ARP_NOTIFY_R {
R_ARP_NOTIFY_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn r_arp_pre(&self) -> R_ARP_PRE_R {
R_ARP_PRE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn r_arp_rst(&self) -> R_ARP_RST_R {
R_ARP_RST_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn r_arp_udid(&self) -> R_ARP_UDID_R {
R_ARP_UDID_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn r_arp_assgn(&self) -> R_ARP_ASSGN_R {
R_ARP_ASSGN_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn r_pec_nack(&self) -> R_PEC_NACK_R {
R_PEC_NACK_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn r_smb_alt(&self) -> R_SMB_ALT_R {
R_SMB_ALT_R::new(((self.bits >> 10) & 1) != 0)
}
}
#[doc = "SMBus Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smb_isr](index.html) module"]
pub struct SMB_ISR_SPEC;
impl crate::RegisterSpec for SMB_ISR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [smb_isr::R](R) reader structure"]
impl crate::Readable for SMB_ISR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets SMB_ISR to value 0"]
impl crate::Resettable for SMB_ISR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SMB_IMR (r) register accessor: an alias for `Reg<SMB_IMR_SPEC>`"]
pub type SMB_IMR = crate::Reg<smb_imr::SMB_IMR_SPEC>;
#[doc = "SMBus Interrupt Mask Register"]
pub mod smb_imr {
#[doc = "Register `SMB_IMR` reader"]
pub struct R(crate::R<SMB_IMR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SMB_IMR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SMB_IMR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SMB_IMR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `M_SLV_TMO` reader - "]
pub type M_SLV_TMO_R = crate::BitReader<bool>;
#[doc = "Field `M_MST_TMO` reader - "]
pub type M_MST_TMO_R = crate::BitReader<bool>;
#[doc = "Field `M_ARP_QUICK` reader - "]
pub type M_ARP_QUICK_R = crate::BitReader<bool>;
#[doc = "Field `M_ARP_NOTIFY` reader - "]
pub type M_ARP_NOTIFY_R = crate::BitReader<bool>;
#[doc = "Field `M_ARP_PRE` reader - "]
pub type M_ARP_PRE_R = crate::BitReader<bool>;
#[doc = "Field `M_ARP_RST` reader - "]
pub type M_ARP_RST_R = crate::BitReader<bool>;
#[doc = "Field `M_ARP_UDID` reader - "]
pub type M_ARP_UDID_R = crate::BitReader<bool>;
#[doc = "Field `M_ARP_ASSGN` reader - "]
pub type M_ARP_ASSGN_R = crate::BitReader<bool>;
#[doc = "Field `M_PEC_NACK` reader - "]
pub type M_PEC_NACK_R = crate::BitReader<bool>;
#[doc = "Field `M_SMB_ALT` reader - "]
pub type M_SMB_ALT_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn m_slv_tmo(&self) -> M_SLV_TMO_R {
M_SLV_TMO_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn m_mst_tmo(&self) -> M_MST_TMO_R {
M_MST_TMO_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn m_arp_quick(&self) -> M_ARP_QUICK_R {
M_ARP_QUICK_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn m_arp_notify(&self) -> M_ARP_NOTIFY_R {
M_ARP_NOTIFY_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn m_arp_pre(&self) -> M_ARP_PRE_R {
M_ARP_PRE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn m_arp_rst(&self) -> M_ARP_RST_R {
M_ARP_RST_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn m_arp_udid(&self) -> M_ARP_UDID_R {
M_ARP_UDID_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn m_arp_assgn(&self) -> M_ARP_ASSGN_R {
M_ARP_ASSGN_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn m_pec_nack(&self) -> M_PEC_NACK_R {
M_PEC_NACK_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn m_smb_alt(&self) -> M_SMB_ALT_R {
M_SMB_ALT_R::new(((self.bits >> 10) & 1) != 0)
}
}
#[doc = "SMBus Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smb_imr](index.html) module"]
pub struct SMB_IMR_SPEC;
impl crate::RegisterSpec for SMB_IMR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [smb_imr::R](R) reader structure"]
impl crate::Readable for SMB_IMR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets SMB_IMR to value 0x07ff"]
impl crate::Resettable for SMB_IMR_SPEC {
const RESET_VALUE: Self::Ux = 0x07ff;
}
}
#[doc = "SMB_RAWISR (w) register accessor: an alias for `Reg<SMB_RAWISR_SPEC>`"]
pub type SMB_RAWISR = crate::Reg<smb_rawisr::SMB_RAWISR_SPEC>;
#[doc = "SMBus RAW Interrupt Register"]
pub mod smb_rawisr {
#[doc = "Register `SMB_RAWISR` writer"]
pub struct W(crate::W<SMB_RAWISR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SMB_RAWISR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SMB_RAWISR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SMB_RAWISR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SLV_TMO` writer - "]
pub type SLV_TMO_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMB_RAWISR_SPEC, bool, O>;
#[doc = "Field `MST_TMO` writer - "]
pub type MST_TMO_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMB_RAWISR_SPEC, bool, O>;
#[doc = "Field `ARP_QUICK` writer - "]
pub type ARP_QUICK_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMB_RAWISR_SPEC, bool, O>;
#[doc = "Field `ARP_NOTIFY` writer - "]
pub type ARP_NOTIFY_W<'a, const O: u8> =
crate::BitWriter<'a, u32, SMB_RAWISR_SPEC, bool, O>;
#[doc = "Field `ARP_PRE` writer - "]
pub type ARP_PRE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMB_RAWISR_SPEC, bool, O>;
#[doc = "Field `ARP_RST` writer - "]
pub type ARP_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMB_RAWISR_SPEC, bool, O>;
#[doc = "Field `ARP_UDID` writer - "]
pub type ARP_UDID_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMB_RAWISR_SPEC, bool, O>;
#[doc = "Field `ARP_ASSGN` writer - "]
pub type ARP_ASSGN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMB_RAWISR_SPEC, bool, O>;
#[doc = "Field `PEC_NACK` writer - "]
pub type PEC_NACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMB_RAWISR_SPEC, bool, O>;
#[doc = "Field `SMB_ALT` writer - "]
pub type SMB_ALT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMB_RAWISR_SPEC, bool, O>;
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn slv_tmo(&mut self) -> SLV_TMO_W<0> {
SLV_TMO_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn mst_tmo(&mut self) -> MST_TMO_W<1> {
MST_TMO_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn arp_quick(&mut self) -> ARP_QUICK_W<2> {
ARP_QUICK_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn arp_notify(&mut self) -> ARP_NOTIFY_W<3> {
ARP_NOTIFY_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn arp_pre(&mut self) -> ARP_PRE_W<4> {
ARP_PRE_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn arp_rst(&mut self) -> ARP_RST_W<5> {
ARP_RST_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn arp_udid(&mut self) -> ARP_UDID_W<6> {
ARP_UDID_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn arp_assgn(&mut self) -> ARP_ASSGN_W<7> {
ARP_ASSGN_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn pec_nack(&mut self) -> PEC_NACK_W<8> {
PEC_NACK_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn smb_alt(&mut self) -> SMB_ALT_W<10> {
SMB_ALT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "SMBus RAW Interrupt Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smb_rawisr](index.html) module"]
pub struct SMB_RAWISR_SPEC;
impl crate::RegisterSpec for SMB_RAWISR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [smb_rawisr::W](W) writer structure"]
impl crate::Writable for SMB_RAWISR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SMB_RAWISR to value 0"]
impl crate::Resettable for SMB_RAWISR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SMB_ICR (w) register accessor: an alias for `Reg<SMB_ICR_SPEC>`"]
pub type SMB_ICR = crate::Reg<smb_icr::SMB_ICR_SPEC>;
#[doc = "SMBus Combined and Independent Interrupt Clear Registers"]
pub mod smb_icr {
#[doc = "Register `SMB_ICR` writer"]
pub struct W(crate::W<SMB_ICR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SMB_ICR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SMB_ICR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SMB_ICR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CLR_SLV_TMO` writer - "]
pub type CLR_SLV_TMO_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMB_ICR_SPEC, bool, O>;
#[doc = "Field `CLR_MST_TMO` writer - "]
pub type CLR_MST_TMO_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMB_ICR_SPEC, bool, O>;
#[doc = "Field `CLR_ARP_QUICK` writer - "]
pub type CLR_ARP_QUICK_W<'a, const O: u8> =
crate::BitWriter<'a, u32, SMB_ICR_SPEC, bool, O>;
#[doc = "Field `CLR_ARP_NOTIFY` writer - "]
pub type CLR_ARP_NOTIFY_W<'a, const O: u8> =
crate::BitWriter<'a, u32, SMB_ICR_SPEC, bool, O>;
#[doc = "Field `CLR_ARP_PRE` writer - "]
pub type CLR_ARP_PRE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMB_ICR_SPEC, bool, O>;
#[doc = "Field `CLR_ARP_RST` writer - "]
pub type CLR_ARP_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMB_ICR_SPEC, bool, O>;
#[doc = "Field `CLR_ARP_UDID` writer - "]
pub type CLR_ARP_UDID_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMB_ICR_SPEC, bool, O>;
#[doc = "Field `CLR_ARP_ASSGN` writer - "]
pub type CLR_ARP_ASSGN_W<'a, const O: u8> =
crate::BitWriter<'a, u32, SMB_ICR_SPEC, bool, O>;
#[doc = "Field `CLR_PEC_NACK` writer - "]
pub type CLR_PEC_NACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMB_ICR_SPEC, bool, O>;
#[doc = "Field `CLR_SMB_ALT` writer - "]
pub type CLR_SMB_ALT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMB_ICR_SPEC, bool, O>;
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn clr_slv_tmo(&mut self) -> CLR_SLV_TMO_W<0> {
CLR_SLV_TMO_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn clr_mst_tmo(&mut self) -> CLR_MST_TMO_W<1> {
CLR_MST_TMO_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn clr_arp_quick(&mut self) -> CLR_ARP_QUICK_W<2> {
CLR_ARP_QUICK_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn clr_arp_notify(&mut self) -> CLR_ARP_NOTIFY_W<3> {
CLR_ARP_NOTIFY_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn clr_arp_pre(&mut self) -> CLR_ARP_PRE_W<4> {
CLR_ARP_PRE_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn clr_arp_rst(&mut self) -> CLR_ARP_RST_W<5> {
CLR_ARP_RST_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn clr_arp_udid(&mut self) -> CLR_ARP_UDID_W<6> {
CLR_ARP_UDID_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn clr_arp_assgn(&mut self) -> CLR_ARP_ASSGN_W<7> {
CLR_ARP_ASSGN_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn clr_pec_nack(&mut self) -> CLR_PEC_NACK_W<8> {
CLR_PEC_NACK_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn clr_smb_alt(&mut self) -> CLR_SMB_ALT_W<10> {
CLR_SMB_ALT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "SMBus Combined and Independent Interrupt Clear Registers\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smb_icr](index.html) module"]
pub struct SMB_ICR_SPEC;
impl crate::RegisterSpec for SMB_ICR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [smb_icr::W](W) writer structure"]
impl crate::Writable for SMB_ICR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SMB_ICR to value 0"]
impl crate::Resettable for SMB_ICR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "OPT_SAR (rw) register accessor: an alias for `Reg<OPT_SAR_SPEC>`"]
pub type OPT_SAR = crate::Reg<opt_sar::OPT_SAR_SPEC>;
#[doc = "Optional Slave Address Register"]
pub mod opt_sar {
#[doc = "Register `OPT_SAR` reader"]
pub struct R(crate::R<OPT_SAR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<OPT_SAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<OPT_SAR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<OPT_SAR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `OPT_SAR` writer"]
pub struct W(crate::W<OPT_SAR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<OPT_SAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<OPT_SAR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<OPT_SAR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `ADDR` reader - "]
pub type ADDR_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ADDR` writer - "]
pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OPT_SAR_SPEC, u8, u8, 7, O>;
impl R {
#[doc = "Bits 0:6"]
#[inline(always)]
pub fn addr(&self) -> ADDR_R {
ADDR_R::new((self.bits & 0x7f) as u8)
}
}
impl W {
#[doc = "Bits 0:6"]
#[inline(always)]
#[must_use]
pub fn addr(&mut self) -> ADDR_W<0> {
ADDR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Optional Slave Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [opt_sar](index.html) module"]
pub struct OPT_SAR_SPEC;
impl crate::RegisterSpec for OPT_SAR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [opt_sar::R](R) reader structure"]
impl crate::Readable for OPT_SAR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [opt_sar::W](W) writer structure"]
impl crate::Writable for OPT_SAR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets OPT_SAR to value 0"]
impl crate::Resettable for OPT_SAR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SMB_UDID_LSB (rw) register accessor: an alias for `Reg<SMB_UDID_LSB_SPEC>`"]
pub type SMB_UDID_LSB = crate::Reg<smb_udid_lsb::SMB_UDID_LSB_SPEC>;
#[doc = "SMBus UDID LSB Register"]
pub mod smb_udid_lsb {
#[doc = "Register `SMB_UDID_LSB` reader"]
pub struct R(crate::R<SMB_UDID_LSB_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SMB_UDID_LSB_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SMB_UDID_LSB_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SMB_UDID_LSB_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SMB_UDID_LSB` writer"]
pub struct W(crate::W<SMB_UDID_LSB_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SMB_UDID_LSB_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SMB_UDID_LSB_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SMB_UDID_LSB_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SMB_UDID_LSB` reader - "]
pub type SMB_UDID_LSB_R = crate::FieldReader<u32, u32>;
#[doc = "Field `SMB_UDID_LSB` writer - "]
pub type SMB_UDID_LSB_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SMB_UDID_LSB_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn smb_udid_lsb(&self) -> SMB_UDID_LSB_R {
SMB_UDID_LSB_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn smb_udid_lsb(&mut self) -> SMB_UDID_LSB_W<0> {
SMB_UDID_LSB_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "SMBus UDID LSB Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smb_udid_lsb](index.html) module"]
pub struct SMB_UDID_LSB_SPEC;
impl crate::RegisterSpec for SMB_UDID_LSB_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [smb_udid_lsb::R](R) reader structure"]
impl crate::Readable for SMB_UDID_LSB_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [smb_udid_lsb::W](W) writer structure"]
impl crate::Writable for SMB_UDID_LSB_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SMB_UDID_LSB to value 0xffff_ffff"]
impl crate::Resettable for SMB_UDID_LSB_SPEC {
const RESET_VALUE: Self::Ux = 0xffff_ffff;
}
}
#[doc = "SMB_UDID_MSB0 (rw) register accessor: an alias for `Reg<SMB_UDID_MSB0_SPEC>`"]
pub type SMB_UDID_MSB0 = crate::Reg<smb_udid_msb0::SMB_UDID_MSB0_SPEC>;
#[doc = "SMBus UDID MSB Register 0"]
pub mod smb_udid_msb0 {
#[doc = "Register `SMB_UDID_MSB0` reader"]
pub struct R(crate::R<SMB_UDID_MSB0_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SMB_UDID_MSB0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SMB_UDID_MSB0_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SMB_UDID_MSB0_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SMB_UDID_MSB0` writer"]
pub struct W(crate::W<SMB_UDID_MSB0_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SMB_UDID_MSB0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SMB_UDID_MSB0_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SMB_UDID_MSB0_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SMB_UDID_MSB0` reader - "]
pub type SMB_UDID_MSB0_R = crate::FieldReader<u32, u32>;
#[doc = "Field `SMB_UDID_MSB0` writer - "]
pub type SMB_UDID_MSB0_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SMB_UDID_MSB0_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn smb_udid_msb0(&self) -> SMB_UDID_MSB0_R {
SMB_UDID_MSB0_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn smb_udid_msb0(&mut self) -> SMB_UDID_MSB0_W<0> {
SMB_UDID_MSB0_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "SMBus UDID MSB Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smb_udid_msb0](index.html) module"]
pub struct SMB_UDID_MSB0_SPEC;
impl crate::RegisterSpec for SMB_UDID_MSB0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [smb_udid_msb0::R](R) reader structure"]
impl crate::Readable for SMB_UDID_MSB0_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [smb_udid_msb0::W](W) writer structure"]
impl crate::Writable for SMB_UDID_MSB0_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SMB_UDID_MSB0 to value 0"]
impl crate::Resettable for SMB_UDID_MSB0_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SMB_UDID_MSB1 (rw) register accessor: an alias for `Reg<SMB_UDID_MSB1_SPEC>`"]
pub type SMB_UDID_MSB1 = crate::Reg<smb_udid_msb1::SMB_UDID_MSB1_SPEC>;
#[doc = "SMBus UDID MSB Register 1"]
pub mod smb_udid_msb1 {
#[doc = "Register `SMB_UDID_MSB1` reader"]
pub struct R(crate::R<SMB_UDID_MSB1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SMB_UDID_MSB1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SMB_UDID_MSB1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SMB_UDID_MSB1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SMB_UDID_MSB1` writer"]
pub struct W(crate::W<SMB_UDID_MSB1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SMB_UDID_MSB1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SMB_UDID_MSB1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SMB_UDID_MSB1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SMB_UDID_MSB1` reader - "]
pub type SMB_UDID_MSB1_R = crate::FieldReader<u32, u32>;
#[doc = "Field `SMB_UDID_MSB1` writer - "]
pub type SMB_UDID_MSB1_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SMB_UDID_MSB1_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn smb_udid_msb1(&self) -> SMB_UDID_MSB1_R {
SMB_UDID_MSB1_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn smb_udid_msb1(&mut self) -> SMB_UDID_MSB1_W<0> {
SMB_UDID_MSB1_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "SMBus UDID MSB Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smb_udid_msb1](index.html) module"]
pub struct SMB_UDID_MSB1_SPEC;
impl crate::RegisterSpec for SMB_UDID_MSB1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [smb_udid_msb1::R](R) reader structure"]
impl crate::Readable for SMB_UDID_MSB1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [smb_udid_msb1::W](W) writer structure"]
impl crate::Writable for SMB_UDID_MSB1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SMB_UDID_MSB1 to value 0"]
impl crate::Resettable for SMB_UDID_MSB1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SMB_UDID_MSB2 (rw) register accessor: an alias for `Reg<SMB_UDID_MSB2_SPEC>`"]
pub type SMB_UDID_MSB2 = crate::Reg<smb_udid_msb2::SMB_UDID_MSB2_SPEC>;
#[doc = "SMBus UDID MSB Register 2"]
pub mod smb_udid_msb2 {
#[doc = "Register `SMB_UDID_MSB2` reader"]
pub struct R(crate::R<SMB_UDID_MSB2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SMB_UDID_MSB2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SMB_UDID_MSB2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SMB_UDID_MSB2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SMB_UDID_MSB2` writer"]
pub struct W(crate::W<SMB_UDID_MSB2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SMB_UDID_MSB2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SMB_UDID_MSB2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SMB_UDID_MSB2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SMB_UDID_MSB2` reader - "]
pub type SMB_UDID_MSB2_R = crate::FieldReader<u32, u32>;
#[doc = "Field `SMB_UDID_MSB2` writer - "]
pub type SMB_UDID_MSB2_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SMB_UDID_MSB2_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn smb_udid_msb2(&self) -> SMB_UDID_MSB2_R {
SMB_UDID_MSB2_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn smb_udid_msb2(&mut self) -> SMB_UDID_MSB2_W<0> {
SMB_UDID_MSB2_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "SMBus UDID MSB Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smb_udid_msb2](index.html) module"]
pub struct SMB_UDID_MSB2_SPEC;
impl crate::RegisterSpec for SMB_UDID_MSB2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [smb_udid_msb2::R](R) reader structure"]
impl crate::Readable for SMB_UDID_MSB2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [smb_udid_msb2::W](W) writer structure"]
impl crate::Writable for SMB_UDID_MSB2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SMB_UDID_MSB2 to value 0"]
impl crate::Resettable for SMB_UDID_MSB2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SLVMASK (rw) register accessor: an alias for `Reg<SLVMASK_SPEC>`"]
pub type SLVMASK = crate::Reg<slvmask::SLVMASK_SPEC>;
#[doc = "Slave Address Mask Register"]
pub mod slvmask {
#[doc = "Register `SLVMASK` reader"]
pub struct R(crate::R<SLVMASK_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SLVMASK_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SLVMASK_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SLVMASK_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SLVMASK` writer"]
pub struct W(crate::W<SLVMASK_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SLVMASK_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SLVMASK_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SLVMASK_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MASK` reader - "]
pub type MASK_R = crate::FieldReader<u16, u16>;
#[doc = "Field `MASK` writer - "]
pub type MASK_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SLVMASK_SPEC, u16, u16, 10, O>;
impl R {
#[doc = "Bits 0:9"]
#[inline(always)]
pub fn mask(&self) -> MASK_R {
MASK_R::new((self.bits & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:9"]
#[inline(always)]
#[must_use]
pub fn mask(&mut self) -> MASK_W<0> {
MASK_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Slave Address Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slvmask](index.html) module"]
pub struct SLVMASK_SPEC;
impl crate::RegisterSpec for SLVMASK_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [slvmask::R](R) reader structure"]
impl crate::Readable for SLVMASK_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [slvmask::W](W) writer structure"]
impl crate::Writable for SLVMASK_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SLVMASK to value 0x03ff"]
impl crate::Resettable for SLVMASK_SPEC {
const RESET_VALUE: Self::Ux = 0x03ff;
}
}
#[doc = "SLVRCVADDR (r) register accessor: an alias for `Reg<SLVRCVADDR_SPEC>`"]
pub type SLVRCVADDR = crate::Reg<slvrcvaddr::SLVRCVADDR_SPEC>;
#[doc = "Slave Receive Address Register"]
pub mod slvrcvaddr {
#[doc = "Register `SLVRCVADDR` reader"]
pub struct R(crate::R<SLVRCVADDR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SLVRCVADDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SLVRCVADDR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SLVRCVADDR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `ADDR` reader - "]
pub type ADDR_R = crate::FieldReader<u16, u16>;
impl R {
#[doc = "Bits 0:9"]
#[inline(always)]
pub fn addr(&self) -> ADDR_R {
ADDR_R::new((self.bits & 0x03ff) as u16)
}
}
#[doc = "Slave Receive Address Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slvrcvaddr](index.html) module"]
pub struct SLVRCVADDR_SPEC;
impl crate::RegisterSpec for SLVRCVADDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [slvrcvaddr::R](R) reader structure"]
impl crate::Readable for SLVRCVADDR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets SLVRCVADDR to value 0"]
impl crate::Resettable for SLVRCVADDR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "I2C2"]
pub struct I2C2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for I2C2 {}
impl I2C2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const i2c1::RegisterBlock = 0x4000_5800 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const i2c1::RegisterBlock {
Self::PTR
}
}
impl Deref for I2C2 {
type Target = i2c1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for I2C2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2C2").finish()
}
}
#[doc = "I2C2"]
pub use self::i2c1 as i2c2;
#[doc = "IWDG"]
pub struct IWDG {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for IWDG {}
impl IWDG {
#[doc = r"Pointer to the register block"]
pub const PTR: *const iwdg::RegisterBlock = 0x4000_3000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const iwdg::RegisterBlock {
Self::PTR
}
}
impl Deref for IWDG {
type Target = iwdg::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for IWDG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("IWDG").finish()
}
}
#[doc = "IWDG"]
pub mod iwdg {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - key register"]
pub kr: KR,
#[doc = "0x04 - Prescaler register"]
pub pr: PR,
#[doc = "0x08 - reload register"]
pub rlr: RLR,
#[doc = "0x0c - status register"]
pub sr: SR,
#[doc = "0x10 - control register"]
pub cr: CR,
#[doc = "0x14 - Interrupt Generation Register"]
pub igen: IGEN,
#[doc = "0x18 - count register"]
pub cnt: CNT,
#[doc = "0x1c - Frequency division count register"]
pub ps: PS,
}
#[doc = "KR (w) register accessor: an alias for `Reg<KR_SPEC>`"]
pub type KR = crate::Reg<kr::KR_SPEC>;
#[doc = "key register"]
pub mod kr {
#[doc = "Register `KR` writer"]
pub struct W(crate::W<KR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<KR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<KR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<KR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `KEY` writer - "]
pub type KEY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, KR_SPEC, u16, u16, 16, O>;
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn key(&mut self) -> KEY_W<0> {
KEY_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "key register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [kr](index.html) module"]
pub struct KR_SPEC;
impl crate::RegisterSpec for KR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [kr::W](W) writer structure"]
impl crate::Writable for KR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets KR to value 0"]
impl crate::Resettable for KR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PR (rw) register accessor: an alias for `Reg<PR_SPEC>`"]
pub type PR = crate::Reg<pr::PR_SPEC>;
#[doc = "Prescaler register"]
pub mod pr {
#[doc = "Register `PR` reader"]
pub struct R(crate::R<PR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PR` writer"]
pub struct W(crate::W<PR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PR` reader - "]
pub type PR_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PR` writer - "]
pub type PR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PR_SPEC, u8, u8, 3, O>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn pr(&self) -> PR_R {
PR_R::new((self.bits & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:2"]
#[inline(always)]
#[must_use]
pub fn pr(&mut self) -> PR_W<0> {
PR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Prescaler register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pr](index.html) module"]
pub struct PR_SPEC;
impl crate::RegisterSpec for PR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [pr::R](R) reader structure"]
impl crate::Readable for PR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pr::W](W) writer structure"]
impl crate::Writable for PR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PR to value 0"]
impl crate::Resettable for PR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RLR (rw) register accessor: an alias for `Reg<RLR_SPEC>`"]
pub type RLR = crate::Reg<rlr::RLR_SPEC>;
#[doc = "reload register"]
pub mod rlr {
#[doc = "Register `RLR` reader"]
pub struct R(crate::R<RLR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RLR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RLR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `RLR` writer"]
pub struct W(crate::W<RLR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<RLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<RLR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<RLR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RL` reader - "]
pub type RL_R = crate::FieldReader<u16, u16>;
#[doc = "Field `RL` writer - "]
pub type RL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RLR_SPEC, u16, u16, 12, O>;
impl R {
#[doc = "Bits 0:11"]
#[inline(always)]
pub fn rl(&self) -> RL_R {
RL_R::new((self.bits & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:11"]
#[inline(always)]
#[must_use]
pub fn rl(&mut self) -> RL_W<0> {
RL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "reload register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rlr](index.html) module"]
pub struct RLR_SPEC;
impl crate::RegisterSpec for RLR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rlr::R](R) reader structure"]
impl crate::Readable for RLR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [rlr::W](W) writer structure"]
impl crate::Writable for RLR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets RLR to value 0x0fff"]
impl crate::Resettable for RLR_SPEC {
const RESET_VALUE: Self::Ux = 0x0fff;
}
}
#[doc = "SR (r) register accessor: an alias for `Reg<SR_SPEC>`"]
pub type SR = crate::Reg<sr::SR_SPEC>;
#[doc = "status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub struct R(crate::R<SR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `PVU` reader - "]
pub type PVU_R = crate::BitReader<bool>;
#[doc = "Field `RVU` reader - "]
pub type RVU_R = crate::BitReader<bool>;
#[doc = "Field `IVU` reader - "]
pub type IVU_R = crate::BitReader<bool>;
#[doc = "Field `UPDATE` reader - "]
pub type UPDATE_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pvu(&self) -> PVU_R {
PVU_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rvu(&self) -> RVU_R {
RVU_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn ivu(&self) -> IVU_R {
IVU_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn update(&self) -> UPDATE_R {
UPDATE_R::new(((self.bits >> 3) & 1) != 0)
}
}
#[doc = "status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"]
pub struct SR_SPEC;
impl crate::RegisterSpec for SR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [sr::R](R) reader structure"]
impl crate::Readable for SR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CR (rw) register accessor: an alias for `Reg<CR_SPEC>`"]
pub type CR = crate::Reg<cr::CR_SPEC>;
#[doc = "control register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub struct R(crate::R<CR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR` writer"]
pub struct W(crate::W<CR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `IRQ_SEL` reader - "]
pub type IRQ_SEL_R = crate::BitReader<bool>;
#[doc = "Field `IRQ_SEL` writer - "]
pub type IRQ_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `IRQ_CLR` reader - "]
pub type IRQ_CLR_R = crate::BitReader<bool>;
#[doc = "Field `IRQ_CLR` writer - "]
pub type IRQ_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn irq_sel(&self) -> IRQ_SEL_R {
IRQ_SEL_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn irq_clr(&self) -> IRQ_CLR_R {
IRQ_CLR_R::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn irq_sel(&mut self) -> IRQ_SEL_W<0> {
IRQ_SEL_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn irq_clr(&mut self) -> IRQ_CLR_W<1> {
IRQ_CLR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"]
pub struct CR_SPEC;
impl crate::RegisterSpec for CR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr::R](R) reader structure"]
impl crate::Readable for CR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"]
impl crate::Writable for CR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "IGEN (rw) register accessor: an alias for `Reg<IGEN_SPEC>`"]
pub type IGEN = crate::Reg<igen::IGEN_SPEC>;
#[doc = "Interrupt Generation Register"]
pub mod igen {
#[doc = "Register `IGEN` reader"]
pub struct R(crate::R<IGEN_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IGEN_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IGEN_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IGEN_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IGEN` writer"]
pub struct W(crate::W<IGEN_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IGEN_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IGEN_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IGEN_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `IGEN` reader - "]
pub type IGEN_R = crate::FieldReader<u16, u16>;
#[doc = "Field `IGEN` writer - "]
pub type IGEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IGEN_SPEC, u16, u16, 12, O>;
impl R {
#[doc = "Bits 0:11"]
#[inline(always)]
pub fn igen(&self) -> IGEN_R {
IGEN_R::new((self.bits & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:11"]
#[inline(always)]
#[must_use]
pub fn igen(&mut self) -> IGEN_W<0> {
IGEN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Interrupt Generation Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [igen](index.html) module"]
pub struct IGEN_SPEC;
impl crate::RegisterSpec for IGEN_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [igen::R](R) reader structure"]
impl crate::Readable for IGEN_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [igen::W](W) writer structure"]
impl crate::Writable for IGEN_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IGEN to value 0x0fff"]
impl crate::Resettable for IGEN_SPEC {
const RESET_VALUE: Self::Ux = 0x0fff;
}
}
#[doc = "CNT (r) register accessor: an alias for `Reg<CNT_SPEC>`"]
pub type CNT = crate::Reg<cnt::CNT_SPEC>;
#[doc = "count register"]
pub mod cnt {
#[doc = "Register `CNT` reader"]
pub struct R(crate::R<CNT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CNT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CNT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CNT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `IWDG_CNT` reader - "]
pub type IWDG_CNT_R = crate::FieldReader<u16, u16>;
impl R {
#[doc = "Bits 0:11"]
#[inline(always)]
pub fn iwdg_cnt(&self) -> IWDG_CNT_R {
IWDG_CNT_R::new((self.bits & 0x0fff) as u16)
}
}
#[doc = "count register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnt](index.html) module"]
pub struct CNT_SPEC;
impl crate::RegisterSpec for CNT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cnt::R](R) reader structure"]
impl crate::Readable for CNT_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets CNT to value 0"]
impl crate::Resettable for CNT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PS (r) register accessor: an alias for `Reg<PS_SPEC>`"]
pub type PS = crate::Reg<ps::PS_SPEC>;
#[doc = "Frequency division count register"]
pub mod ps {
#[doc = "Register `PS` reader"]
pub struct R(crate::R<PS_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PS_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PS_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PS_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `IWDG_PS` reader - "]
pub type IWDG_PS_R = crate::FieldReader<u8, u8>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn iwdg_ps(&self) -> IWDG_PS_R {
IWDG_PS_R::new((self.bits & 0xff) as u8)
}
}
#[doc = "Frequency division count register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ps](index.html) module"]
pub struct PS_SPEC;
impl crate::RegisterSpec for PS_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ps::R](R) reader structure"]
impl crate::Readable for PS_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets PS to value 0x01"]
impl crate::Resettable for PS_SPEC {
const RESET_VALUE: Self::Ux = 0x01;
}
}
}
#[doc = "LPT"]
pub struct LPT {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for LPT {}
impl LPT {
#[doc = r"Pointer to the register block"]
pub const PTR: *const lpt::RegisterBlock = 0x4001_d000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const lpt::RegisterBlock {
Self::PTR
}
}
impl Deref for LPT {
type Target = lpt::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for LPT {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("LPT").finish()
}
}
#[doc = "LPT"]
pub mod lpt {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - LPTIM Configuration Register"]
pub cfg: CFG,
#[doc = "0x04 - LPTIM Interrupt Enable Register"]
pub ie: IE,
#[doc = "0x08 - LPTIM Interrupt Flag Register"]
pub if_: IF,
#[doc = "0x0c - LPTIM Control Register"]
pub ctrl: CTRL,
#[doc = "0x10 - LPTIM count register"]
pub cnt: CNT,
#[doc = "0x14 - LPTIM Compare Value Register"]
pub cmp: CMP,
#[doc = "0x18 - LPTIM target value register"]
pub target: TARGET,
}
#[doc = "CFG (rw) register accessor: an alias for `Reg<CFG_SPEC>`"]
pub type CFG = crate::Reg<cfg::CFG_SPEC>;
#[doc = "LPTIM Configuration Register"]
pub mod cfg {
#[doc = "Register `CFG` reader"]
pub struct R(crate::R<CFG_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CFG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CFG_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CFG_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CFG` writer"]
pub struct W(crate::W<CFG_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CFG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CFG_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CFG_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MODE` reader - "]
pub type MODE_R = crate::BitReader<bool>;
#[doc = "Field `MODE` writer - "]
pub type MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_SPEC, bool, O>;
#[doc = "Field `TMODE` reader - "]
pub type TMODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TMODE` writer - "]
pub type TMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFG_SPEC, u8, u8, 2, O>;
#[doc = "Field `PWM` reader - "]
pub type PWM_R = crate::BitReader<bool>;
#[doc = "Field `PWM` writer - "]
pub type PWM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_SPEC, bool, O>;
#[doc = "Field `POLARITY` reader - "]
pub type POLARITY_R = crate::BitReader<bool>;
#[doc = "Field `POLARITY` writer - "]
pub type POLARITY_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_SPEC, bool, O>;
#[doc = "Field `TRIGSEL` reader - "]
pub type TRIGSEL_R = crate::BitReader<bool>;
#[doc = "Field `TRIGSEL` writer - "]
pub type TRIGSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_SPEC, bool, O>;
#[doc = "Field `TRIGCFG` reader - "]
pub type TRIGCFG_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TRIGCFG` writer - "]
pub type TRIGCFG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFG_SPEC, u8, u8, 2, O>;
#[doc = "Field `DICSEL` reader - "]
pub type DICSEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DICSEL` writer - "]
pub type DICSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFG_SPEC, u8, u8, 3, O>;
#[doc = "Field `FTLEN` reader - "]
pub type FTLEN_R = crate::BitReader<bool>;
#[doc = "Field `FTLEN` writer - "]
pub type FTLEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFG_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn mode(&self) -> MODE_R {
MODE_R::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2"]
#[inline(always)]
pub fn tmode(&self) -> TMODE_R {
TMODE_R::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn pwm(&self) -> PWM_R {
PWM_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn polarity(&self) -> POLARITY_R {
POLARITY_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn trigsel(&self) -> TRIGSEL_R {
TRIGSEL_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn trigcfg(&self) -> TRIGCFG_R {
TRIGCFG_R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:10"]
#[inline(always)]
pub fn dicsel(&self) -> DICSEL_R {
DICSEL_R::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn ftlen(&self) -> FTLEN_R {
FTLEN_R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> MODE_W<0> {
MODE_W::new(self)
}
#[doc = "Bits 1:2"]
#[inline(always)]
#[must_use]
pub fn tmode(&mut self) -> TMODE_W<1> {
TMODE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn pwm(&mut self) -> PWM_W<3> {
PWM_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn polarity(&mut self) -> POLARITY_W<4> {
POLARITY_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn trigsel(&mut self) -> TRIGSEL_W<5> {
TRIGSEL_W::new(self)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn trigcfg(&mut self) -> TRIGCFG_W<6> {
TRIGCFG_W::new(self)
}
#[doc = "Bits 8:10"]
#[inline(always)]
#[must_use]
pub fn dicsel(&mut self) -> DICSEL_W<8> {
DICSEL_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn ftlen(&mut self) -> FTLEN_W<15> {
FTLEN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "LPTIM Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFG_SPEC;
impl crate::RegisterSpec for CFG_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cfg::R](R) reader structure"]
impl crate::Readable for CFG_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfg::W](W) writer structure"]
impl crate::Writable for CFG_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CFG to value 0"]
impl crate::Resettable for CFG_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "IE (rw) register accessor: an alias for `Reg<IE_SPEC>`"]
pub type IE = crate::Reg<ie::IE_SPEC>;
#[doc = "LPTIM Interrupt Enable Register"]
pub mod ie {
#[doc = "Register `IE` reader"]
pub struct R(crate::R<IE_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IE_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IE_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IE_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IE` writer"]
pub struct W(crate::W<IE_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IE_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IE_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IE_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `OVIE` reader - "]
pub type OVIE_R = crate::BitReader<bool>;
#[doc = "Field `OVIE` writer - "]
pub type OVIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IE_SPEC, bool, O>;
#[doc = "Field `TRIGIE` reader - "]
pub type TRIGIE_R = crate::BitReader<bool>;
#[doc = "Field `TRIGIE` writer - "]
pub type TRIGIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IE_SPEC, bool, O>;
#[doc = "Field `COMPIE` reader - "]
pub type COMPIE_R = crate::BitReader<bool>;
#[doc = "Field `COMPIE` writer - "]
pub type COMPIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IE_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn ovie(&self) -> OVIE_R {
OVIE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn trigie(&self) -> TRIGIE_R {
TRIGIE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn compie(&self) -> COMPIE_R {
COMPIE_R::new(((self.bits >> 2) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn ovie(&mut self) -> OVIE_W<0> {
OVIE_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn trigie(&mut self) -> TRIGIE_W<1> {
TRIGIE_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn compie(&mut self) -> COMPIE_W<2> {
COMPIE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "LPTIM Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ie](index.html) module"]
pub struct IE_SPEC;
impl crate::RegisterSpec for IE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ie::R](R) reader structure"]
impl crate::Readable for IE_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ie::W](W) writer structure"]
impl crate::Writable for IE_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IE to value 0"]
impl crate::Resettable for IE_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "IF (rw) register accessor: an alias for `Reg<IF_SPEC>`"]
pub type IF = crate::Reg<if_::IF_SPEC>;
#[doc = "LPTIM Interrupt Flag Register"]
pub mod if_ {
#[doc = "Register `IF` reader"]
pub struct R(crate::R<IF_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IF_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IF_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IF_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IF` writer"]
pub struct W(crate::W<IF_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IF_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IF_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IF_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `OVIF` reader - "]
pub type OVIF_R = crate::BitReader<bool>;
#[doc = "Field `OVIF` writer - "]
pub type OVIF_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, IF_SPEC, bool, O>;
#[doc = "Field `TRIGIF` reader - "]
pub type TRIGIF_R = crate::BitReader<bool>;
#[doc = "Field `TRIGIF` writer - "]
pub type TRIGIF_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, IF_SPEC, bool, O>;
#[doc = "Field `COMPIF` reader - "]
pub type COMPIF_R = crate::BitReader<bool>;
#[doc = "Field `COMPIF` writer - "]
pub type COMPIF_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, IF_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn ovif(&self) -> OVIF_R {
OVIF_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn trigif(&self) -> TRIGIF_R {
TRIGIF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn compif(&self) -> COMPIF_R {
COMPIF_R::new(((self.bits >> 2) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn ovif(&mut self) -> OVIF_W<0> {
OVIF_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn trigif(&mut self) -> TRIGIF_W<1> {
TRIGIF_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn compif(&mut self) -> COMPIF_W<2> {
COMPIF_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "LPTIM Interrupt Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [if_](index.html) module"]
pub struct IF_SPEC;
impl crate::RegisterSpec for IF_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [if_::R](R) reader structure"]
impl crate::Readable for IF_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [if_::W](W) writer structure"]
impl crate::Writable for IF_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x07;
}
#[doc = "`reset()` method sets IF to value 0"]
impl crate::Resettable for IF_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CTRL (rw) register accessor: an alias for `Reg<CTRL_SPEC>`"]
pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
#[doc = "LPTIM Control Register"]
pub mod ctrl {
#[doc = "Register `CTRL` reader"]
pub struct R(crate::R<CTRL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CTRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CTRL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CTRL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CTRL` writer"]
pub struct W(crate::W<CTRL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CTRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CTRL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CTRL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `LPTEN` reader - "]
pub type LPTEN_R = crate::BitReader<bool>;
#[doc = "Field `LPTEN` writer - "]
pub type LPTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn lpten(&self) -> LPTEN_R {
LPTEN_R::new((self.bits & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn lpten(&mut self) -> LPTEN_W<0> {
LPTEN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "LPTIM Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
pub struct CTRL_SPEC;
impl crate::RegisterSpec for CTRL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
impl crate::Readable for CTRL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
impl crate::Writable for CTRL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CTRL to value 0"]
impl crate::Resettable for CTRL_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CNT (rw) register accessor: an alias for `Reg<CNT_SPEC>`"]
pub type CNT = crate::Reg<cnt::CNT_SPEC>;
#[doc = "LPTIM count register"]
pub mod cnt {
#[doc = "Register `CNT` reader"]
pub struct R(crate::R<CNT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CNT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CNT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CNT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CNT` writer"]
pub struct W(crate::W<CNT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CNT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CNT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CNT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CNT` reader - "]
pub type CNT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CNT` writer - "]
pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNT_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn cnt(&self) -> CNT_R {
CNT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CNT_W<0> {
CNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "LPTIM count register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnt](index.html) module"]
pub struct CNT_SPEC;
impl crate::RegisterSpec for CNT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cnt::R](R) reader structure"]
impl crate::Readable for CNT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cnt::W](W) writer structure"]
impl crate::Writable for CNT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CNT to value 0"]
impl crate::Resettable for CNT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CMP (rw) register accessor: an alias for `Reg<CMP_SPEC>`"]
pub type CMP = crate::Reg<cmp::CMP_SPEC>;
#[doc = "LPTIM Compare Value Register"]
pub mod cmp {
#[doc = "Register `CMP` reader"]
pub struct R(crate::R<CMP_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CMP_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CMP_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CMP_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CMP` writer"]
pub struct W(crate::W<CMP_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CMP_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CMP_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CMP_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `COMPARE_REG` reader - "]
pub type COMPARE_REG_R = crate::FieldReader<u16, u16>;
#[doc = "Field `COMPARE_REG` writer - "]
pub type COMPARE_REG_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CMP_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn compare_reg(&self) -> COMPARE_REG_R {
COMPARE_REG_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn compare_reg(&mut self) -> COMPARE_REG_W<0> {
COMPARE_REG_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "LPTIM Compare Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmp](index.html) module"]
pub struct CMP_SPEC;
impl crate::RegisterSpec for CMP_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cmp::R](R) reader structure"]
impl crate::Readable for CMP_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cmp::W](W) writer structure"]
impl crate::Writable for CMP_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CMP to value 0"]
impl crate::Resettable for CMP_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "TARGET (rw) register accessor: an alias for `Reg<TARGET_SPEC>`"]
pub type TARGET = crate::Reg<target::TARGET_SPEC>;
#[doc = "LPTIM target value register"]
pub mod target {
#[doc = "Register `TARGET` reader"]
pub struct R(crate::R<TARGET_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<TARGET_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<TARGET_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<TARGET_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `TARGET` writer"]
pub struct W(crate::W<TARGET_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<TARGET_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<TARGET_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<TARGET_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TARGET_REG` reader - "]
pub type TARGET_REG_R = crate::FieldReader<u16, u16>;
#[doc = "Field `TARGET_REG` writer - "]
pub type TARGET_REG_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, TARGET_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn target_reg(&self) -> TARGET_REG_R {
TARGET_REG_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn target_reg(&mut self) -> TARGET_REG_W<0> {
TARGET_REG_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "LPTIM target value register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [target](index.html) module"]
pub struct TARGET_SPEC;
impl crate::RegisterSpec for TARGET_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [target::R](R) reader structure"]
impl crate::Readable for TARGET_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [target::W](W) writer structure"]
impl crate::Writable for TARGET_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets TARGET to value 0"]
impl crate::Resettable for TARGET_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "LPU"]
pub struct LPU {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for LPU {}
impl LPU {
#[doc = r"Pointer to the register block"]
pub const PTR: *const lpu::RegisterBlock = 0x4001_0800 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const lpu::RegisterBlock {
Self::PTR
}
}
impl Deref for LPU {
type Target = lpu::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for LPU {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("LPU").finish()
}
}
#[doc = "LPU"]
pub mod lpu {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - LPUART Baud Rate Register"]
pub lpubaud: LPUBAUD,
#[doc = "0x04 - LPUART Baud Rate Modulation Control Register"]
pub modu: MODU,
#[doc = "0x08 - LPUART Interrupt Flag Register"]
pub lpuif: LPUIF,
#[doc = "0x0c - LPUART Status Register"]
pub lpusta: LPUSTA,
#[doc = "0x10 - LPUART Control Register"]
pub lpucon: LPUCON,
#[doc = "0x14 - LPUART transmit and receive enable register"]
pub lpuen: LPUEN,
#[doc = "0x18 - LPUART receive data register"]
pub lpurxd: LPURXD,
#[doc = "0x1c - LPUART transmit data register"]
pub lputxd: LPUTXD,
#[doc = "0x20 - LPUART data match register"]
pub compare: COMPARE,
#[doc = "0x24 - LPUART Wakeup Register"]
pub wkcke: WKCKE,
}
#[doc = "LPUBAUD (rw) register accessor: an alias for `Reg<LPUBAUD_SPEC>`"]
pub type LPUBAUD = crate::Reg<lpubaud::LPUBAUD_SPEC>;
#[doc = "LPUART Baud Rate Register"]
pub mod lpubaud {
#[doc = "Register `LPUBAUD` reader"]
pub struct R(crate::R<LPUBAUD_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<LPUBAUD_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<LPUBAUD_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<LPUBAUD_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `LPUBAUD` writer"]
pub struct W(crate::W<LPUBAUD_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<LPUBAUD_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<LPUBAUD_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<LPUBAUD_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `BAUD` reader - "]
pub type BAUD_R = crate::FieldReader<u8, u8>;
#[doc = "Field `BAUD` writer - "]
pub type BAUD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LPUBAUD_SPEC, u8, u8, 3, O>;
#[doc = "Field `BREN` reader - "]
pub type BREN_R = crate::BitReader<bool>;
#[doc = "Field `BREN` writer - "]
pub type BREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LPUBAUD_SPEC, bool, O>;
#[doc = "Field `BR` reader - "]
pub type BR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `BR` writer - "]
pub type BR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LPUBAUD_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn baud(&self) -> BAUD_R {
BAUD_R::new((self.bits & 7) as u8)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn bren(&self) -> BREN_R {
BREN_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 16:31"]
#[inline(always)]
pub fn br(&self) -> BR_R {
BR_R::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:2"]
#[inline(always)]
#[must_use]
pub fn baud(&mut self) -> BAUD_W<0> {
BAUD_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn bren(&mut self) -> BREN_W<8> {
BREN_W::new(self)
}
#[doc = "Bits 16:31"]
#[inline(always)]
#[must_use]
pub fn br(&mut self) -> BR_W<16> {
BR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "LPUART Baud Rate Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lpubaud](index.html) module"]
pub struct LPUBAUD_SPEC;
impl crate::RegisterSpec for LPUBAUD_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [lpubaud::R](R) reader structure"]
impl crate::Readable for LPUBAUD_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [lpubaud::W](W) writer structure"]
impl crate::Writable for LPUBAUD_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets LPUBAUD to value 0"]
impl crate::Resettable for LPUBAUD_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MODU (rw) register accessor: an alias for `Reg<MODU_SPEC>`"]
pub type MODU = crate::Reg<modu::MODU_SPEC>;
#[doc = "LPUART Baud Rate Modulation Control Register"]
pub mod modu {
#[doc = "Register `MODU` reader"]
pub struct R(crate::R<MODU_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MODU_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MODU_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MODU_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MODU` writer"]
pub struct W(crate::W<MODU_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MODU_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MODU_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MODU_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MCTL` reader - "]
pub type MCTL_R = crate::FieldReader<u16, u16>;
#[doc = "Field `MCTL` writer - "]
pub type MCTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MODU_SPEC, u16, u16, 12, O>;
impl R {
#[doc = "Bits 0:11"]
#[inline(always)]
pub fn mctl(&self) -> MCTL_R {
MCTL_R::new((self.bits & 0x0fff) as u16)
}
}
impl W {
#[doc = "Bits 0:11"]
#[inline(always)]
#[must_use]
pub fn mctl(&mut self) -> MCTL_W<0> {
MCTL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "LPUART Baud Rate Modulation Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [modu](index.html) module"]
pub struct MODU_SPEC;
impl crate::RegisterSpec for MODU_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [modu::R](R) reader structure"]
impl crate::Readable for MODU_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [modu::W](W) writer structure"]
impl crate::Writable for MODU_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MODU to value 0"]
impl crate::Resettable for MODU_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "LPUIF (rw) register accessor: an alias for `Reg<LPUIF_SPEC>`"]
pub type LPUIF = crate::Reg<lpuif::LPUIF_SPEC>;
#[doc = "LPUART Interrupt Flag Register"]
pub mod lpuif {
#[doc = "Register `LPUIF` reader"]
pub struct R(crate::R<LPUIF_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<LPUIF_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<LPUIF_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<LPUIF_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `LPUIF` writer"]
pub struct W(crate::W<LPUIF_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<LPUIF_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<LPUIF_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<LPUIF_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RXIF` reader - "]
pub type RXIF_R = crate::BitReader<bool>;
#[doc = "Field `RXIF` writer - "]
pub type RXIF_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, LPUIF_SPEC, bool, O>;
#[doc = "Field `TXIF` reader - "]
pub type TXIF_R = crate::BitReader<bool>;
#[doc = "Field `TXIF` writer - "]
pub type TXIF_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, LPUIF_SPEC, bool, O>;
#[doc = "Field `RXNEGIF` reader - "]
pub type RXNEGIF_R = crate::BitReader<bool>;
#[doc = "Field `RXNEGIF` writer - "]
pub type RXNEGIF_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, LPUIF_SPEC, bool, O>;
#[doc = "Field `TC_IF` reader - "]
pub type TC_IF_R = crate::BitReader<bool>;
#[doc = "Field `TC_IF` writer - "]
pub type TC_IF_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, LPUIF_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn rxif(&self) -> RXIF_R {
RXIF_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn txif(&self) -> TXIF_R {
TXIF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn rxnegif(&self) -> RXNEGIF_R {
RXNEGIF_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn tc_if(&self) -> TC_IF_R {
TC_IF_R::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn rxif(&mut self) -> RXIF_W<0> {
RXIF_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn txif(&mut self) -> TXIF_W<1> {
TXIF_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn rxnegif(&mut self) -> RXNEGIF_W<2> {
RXNEGIF_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn tc_if(&mut self) -> TC_IF_W<3> {
TC_IF_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "LPUART Interrupt Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lpuif](index.html) module"]
pub struct LPUIF_SPEC;
impl crate::RegisterSpec for LPUIF_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [lpuif::R](R) reader structure"]
impl crate::Readable for LPUIF_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [lpuif::W](W) writer structure"]
impl crate::Writable for LPUIF_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0f;
}
#[doc = "`reset()` method sets LPUIF to value 0x02"]
impl crate::Resettable for LPUIF_SPEC {
const RESET_VALUE: Self::Ux = 0x02;
}
}
#[doc = "LPUSTA (rw) register accessor: an alias for `Reg<LPUSTA_SPEC>`"]
pub type LPUSTA = crate::Reg<lpusta::LPUSTA_SPEC>;
#[doc = "LPUART Status Register"]
pub mod lpusta {
#[doc = "Register `LPUSTA` reader"]
pub struct R(crate::R<LPUSTA_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<LPUSTA_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<LPUSTA_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<LPUSTA_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `LPUSTA` writer"]
pub struct W(crate::W<LPUSTA_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<LPUSTA_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<LPUSTA_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<LPUSTA_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RXOV` reader - "]
pub type RXOV_R = crate::BitReader<bool>;
#[doc = "Field `RXOV` writer - "]
pub type RXOV_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, LPUSTA_SPEC, bool, O>;
#[doc = "Field `FERR` reader - "]
pub type FERR_R = crate::BitReader<bool>;
#[doc = "Field `FERR` writer - "]
pub type FERR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, LPUSTA_SPEC, bool, O>;
#[doc = "Field `MATCH` reader - "]
pub type MATCH_R = crate::BitReader<bool>;
#[doc = "Field `MATCH` writer - "]
pub type MATCH_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, LPUSTA_SPEC, bool, O>;
#[doc = "Field `RXF` reader - "]
pub type RXF_R = crate::BitReader<bool>;
#[doc = "Field `TXE` reader - "]
pub type TXE_R = crate::BitReader<bool>;
#[doc = "Field `TC` reader - "]
pub type TC_R = crate::BitReader<bool>;
#[doc = "Field `PERR` reader - "]
pub type PERR_R = crate::BitReader<bool>;
#[doc = "Field `PERR` writer - "]
pub type PERR_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, LPUSTA_SPEC, bool, O>;
#[doc = "Field `START` reader - "]
pub type START_R = crate::BitReader<bool>;
#[doc = "Field `START` writer - "]
pub type START_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, LPUSTA_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn rxov(&self) -> RXOV_R {
RXOV_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn ferr(&self) -> FERR_R {
FERR_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn match_(&self) -> MATCH_R {
MATCH_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rxf(&self) -> RXF_R {
RXF_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn txe(&self) -> TXE_R {
TXE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn tc(&self) -> TC_R {
TC_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn perr(&self) -> PERR_R {
PERR_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn start(&self) -> START_R {
START_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn rxov(&mut self) -> RXOV_W<0> {
RXOV_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn ferr(&mut self) -> FERR_W<1> {
FERR_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn match_(&mut self) -> MATCH_W<2> {
MATCH_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn perr(&mut self) -> PERR_W<6> {
PERR_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn start(&mut self) -> START_W<7> {
START_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "LPUART Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lpusta](index.html) module"]
pub struct LPUSTA_SPEC;
impl crate::RegisterSpec for LPUSTA_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [lpusta::R](R) reader structure"]
impl crate::Readable for LPUSTA_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [lpusta::W](W) writer structure"]
impl crate::Writable for LPUSTA_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xc7;
}
#[doc = "`reset()` method sets LPUSTA to value 0x30"]
impl crate::Resettable for LPUSTA_SPEC {
const RESET_VALUE: Self::Ux = 0x30;
}
}
#[doc = "LPUCON (rw) register accessor: an alias for `Reg<LPUCON_SPEC>`"]
pub type LPUCON = crate::Reg<lpucon::LPUCON_SPEC>;
#[doc = "LPUART Control Register"]
pub mod lpucon {
#[doc = "Register `LPUCON` reader"]
pub struct R(crate::R<LPUCON_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<LPUCON_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<LPUCON_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<LPUCON_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `LPUCON` writer"]
pub struct W(crate::W<LPUCON_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<LPUCON_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<LPUCON_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<LPUCON_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RXIE` reader - "]
pub type RXIE_R = crate::BitReader<bool>;
#[doc = "Field `RXIE` writer - "]
pub type RXIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, LPUCON_SPEC, bool, O>;
#[doc = "Field `NEDET` reader - "]
pub type NEDET_R = crate::BitReader<bool>;
#[doc = "Field `NEDET` writer - "]
pub type NEDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, LPUCON_SPEC, bool, O>;
#[doc = "Field `TXIE` reader - "]
pub type TXIE_R = crate::BitReader<bool>;
#[doc = "Field `TXIE` writer - "]
pub type TXIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, LPUCON_SPEC, bool, O>;
#[doc = "Field `TCIE` reader - "]
pub type TCIE_R = crate::BitReader<bool>;
#[doc = "Field `TCIE` writer - "]
pub type TCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, LPUCON_SPEC, bool, O>;
#[doc = "Field `ERRIE` reader - "]
pub type ERRIE_R = crate::BitReader<bool>;
#[doc = "Field `ERRIE` writer - "]
pub type ERRIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, LPUCON_SPEC, bool, O>;
#[doc = "Field `RXEV` reader - "]
pub type RXEV_R = crate::FieldReader<u8, u8>;
#[doc = "Field `RXEV` writer - "]
pub type RXEV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LPUCON_SPEC, u8, u8, 2, O>;
#[doc = "Field `DL` reader - "]
pub type DL_R = crate::BitReader<bool>;
#[doc = "Field `DL` writer - "]
pub type DL_W<'a, const O: u8> = crate::BitWriter<'a, u32, LPUCON_SPEC, bool, O>;
#[doc = "Field `SL` reader - "]
pub type SL_R = crate::BitReader<bool>;
#[doc = "Field `SL` writer - "]
pub type SL_W<'a, const O: u8> = crate::BitWriter<'a, u32, LPUCON_SPEC, bool, O>;
#[doc = "Field `PTYP` reader - "]
pub type PTYP_R = crate::BitReader<bool>;
#[doc = "Field `PTYP` writer - "]
pub type PTYP_W<'a, const O: u8> = crate::BitWriter<'a, u32, LPUCON_SPEC, bool, O>;
#[doc = "Field `PAREN` reader - "]
pub type PAREN_R = crate::BitReader<bool>;
#[doc = "Field `PAREN` writer - "]
pub type PAREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LPUCON_SPEC, bool, O>;
#[doc = "Field `RXPOL` reader - "]
pub type RXPOL_R = crate::BitReader<bool>;
#[doc = "Field `RXPOL` writer - "]
pub type RXPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, LPUCON_SPEC, bool, O>;
#[doc = "Field `TXPOL` reader - "]
pub type TXPOL_R = crate::BitReader<bool>;
#[doc = "Field `TXPOL` writer - "]
pub type TXPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, LPUCON_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn rxie(&self) -> RXIE_R {
RXIE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn nedet(&self) -> NEDET_R {
NEDET_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn txie(&self) -> TXIE_R {
TXIE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn tcie(&self) -> TCIE_R {
TCIE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn errie(&self) -> ERRIE_R {
ERRIE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6"]
#[inline(always)]
pub fn rxev(&self) -> RXEV_R {
RXEV_R::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn dl(&self) -> DL_R {
DL_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn sl(&self) -> SL_R {
SL_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ptyp(&self) -> PTYP_R {
PTYP_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn paren(&self) -> PAREN_R {
PAREN_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn rxpol(&self) -> RXPOL_R {
RXPOL_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn txpol(&self) -> TXPOL_R {
TXPOL_R::new(((self.bits >> 12) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn rxie(&mut self) -> RXIE_W<0> {
RXIE_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn nedet(&mut self) -> NEDET_W<1> {
NEDET_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn txie(&mut self) -> TXIE_W<2> {
TXIE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn tcie(&mut self) -> TCIE_W<3> {
TCIE_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn errie(&mut self) -> ERRIE_W<4> {
ERRIE_W::new(self)
}
#[doc = "Bits 5:6"]
#[inline(always)]
#[must_use]
pub fn rxev(&mut self) -> RXEV_W<5> {
RXEV_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn dl(&mut self) -> DL_W<7> {
DL_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn sl(&mut self) -> SL_W<8> {
SL_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ptyp(&mut self) -> PTYP_W<9> {
PTYP_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn paren(&mut self) -> PAREN_W<10> {
PAREN_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn rxpol(&mut self) -> RXPOL_W<11> {
RXPOL_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn txpol(&mut self) -> TXPOL_W<12> {
TXPOL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "LPUART Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lpucon](index.html) module"]
pub struct LPUCON_SPEC;
impl crate::RegisterSpec for LPUCON_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [lpucon::R](R) reader structure"]
impl crate::Readable for LPUCON_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [lpucon::W](W) writer structure"]
impl crate::Writable for LPUCON_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets LPUCON to value 0"]
impl crate::Resettable for LPUCON_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "LPUEN (rw) register accessor: an alias for `Reg<LPUEN_SPEC>`"]
pub type LPUEN = crate::Reg<lpuen::LPUEN_SPEC>;
#[doc = "LPUART transmit and receive enable register"]
pub mod lpuen {
#[doc = "Register `LPUEN` reader"]
pub struct R(crate::R<LPUEN_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<LPUEN_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<LPUEN_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<LPUEN_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `LPUEN` writer"]
pub struct W(crate::W<LPUEN_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<LPUEN_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<LPUEN_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<LPUEN_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TXEN` reader - "]
pub type TXEN_R = crate::BitReader<bool>;
#[doc = "Field `TXEN` writer - "]
pub type TXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LPUEN_SPEC, bool, O>;
#[doc = "Field `RXEN` reader - "]
pub type RXEN_R = crate::BitReader<bool>;
#[doc = "Field `RXEN` writer - "]
pub type RXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, LPUEN_SPEC, bool, O>;
#[doc = "Field `DMAT` reader - "]
pub type DMAT_R = crate::BitReader<bool>;
#[doc = "Field `DMAT` writer - "]
pub type DMAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, LPUEN_SPEC, bool, O>;
#[doc = "Field `DMAR` reader - "]
pub type DMAR_R = crate::BitReader<bool>;
#[doc = "Field `DMAR` writer - "]
pub type DMAR_W<'a, const O: u8> = crate::BitWriter<'a, u32, LPUEN_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn txen(&self) -> TXEN_R {
TXEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rxen(&self) -> RXEN_R {
RXEN_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn dmat(&self) -> DMAT_R {
DMAT_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn dmar(&self) -> DMAR_R {
DMAR_R::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn txen(&mut self) -> TXEN_W<0> {
TXEN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn rxen(&mut self) -> RXEN_W<1> {
RXEN_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn dmat(&mut self) -> DMAT_W<2> {
DMAT_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn dmar(&mut self) -> DMAR_W<3> {
DMAR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "LPUART transmit and receive enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lpuen](index.html) module"]
pub struct LPUEN_SPEC;
impl crate::RegisterSpec for LPUEN_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [lpuen::R](R) reader structure"]
impl crate::Readable for LPUEN_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [lpuen::W](W) writer structure"]
impl crate::Writable for LPUEN_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets LPUEN to value 0"]
impl crate::Resettable for LPUEN_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "LPURXD (r) register accessor: an alias for `Reg<LPURXD_SPEC>`"]
pub type LPURXD = crate::Reg<lpurxd::LPURXD_SPEC>;
#[doc = "LPUART receive data register"]
pub mod lpurxd {
#[doc = "Register `LPURXD` reader"]
pub struct R(crate::R<LPURXD_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<LPURXD_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<LPURXD_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<LPURXD_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `DATA` reader - "]
pub type DATA_R = crate::FieldReader<u8, u8>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn data(&self) -> DATA_R {
DATA_R::new((self.bits & 0xff) as u8)
}
}
#[doc = "LPUART receive data register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lpurxd](index.html) module"]
pub struct LPURXD_SPEC;
impl crate::RegisterSpec for LPURXD_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [lpurxd::R](R) reader structure"]
impl crate::Readable for LPURXD_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets LPURXD to value 0"]
impl crate::Resettable for LPURXD_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "LPUTXD (w) register accessor: an alias for `Reg<LPUTXD_SPEC>`"]
pub type LPUTXD = crate::Reg<lputxd::LPUTXD_SPEC>;
#[doc = "LPUART transmit data register"]
pub mod lputxd {
#[doc = "Register `LPUTXD` writer"]
pub struct W(crate::W<LPUTXD_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<LPUTXD_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<LPUTXD_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<LPUTXD_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DATA` writer - "]
pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LPUTXD_SPEC, u8, u8, 8, O>;
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn data(&mut self) -> DATA_W<0> {
DATA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "LPUART transmit data register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lputxd](index.html) module"]
pub struct LPUTXD_SPEC;
impl crate::RegisterSpec for LPUTXD_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [lputxd::W](W) writer structure"]
impl crate::Writable for LPUTXD_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets LPUTXD to value 0"]
impl crate::Resettable for LPUTXD_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "COMPARE (rw) register accessor: an alias for `Reg<COMPARE_SPEC>`"]
pub type COMPARE = crate::Reg<compare::COMPARE_SPEC>;
#[doc = "LPUART data match register"]
pub mod compare {
#[doc = "Register `COMPARE` reader"]
pub struct R(crate::R<COMPARE_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<COMPARE_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<COMPARE_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<COMPARE_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `COMPARE` writer"]
pub struct W(crate::W<COMPARE_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<COMPARE_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<COMPARE_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<COMPARE_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `COMPARE` reader - "]
pub type COMPARE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `COMPARE` writer - "]
pub type COMPARE_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, COMPARE_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn compare(&self) -> COMPARE_R {
COMPARE_R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn compare(&mut self) -> COMPARE_W<0> {
COMPARE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "LPUART data match register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [compare](index.html) module"]
pub struct COMPARE_SPEC;
impl crate::RegisterSpec for COMPARE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [compare::R](R) reader structure"]
impl crate::Readable for COMPARE_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [compare::W](W) writer structure"]
impl crate::Writable for COMPARE_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets COMPARE to value 0"]
impl crate::Resettable for COMPARE_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "WKCKE (rw) register accessor: an alias for `Reg<WKCKE_SPEC>`"]
pub type WKCKE = crate::Reg<wkcke::WKCKE_SPEC>;
#[doc = "LPUART Wakeup Register"]
pub mod wkcke {
#[doc = "Register `WKCKE` reader"]
pub struct R(crate::R<WKCKE_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<WKCKE_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<WKCKE_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<WKCKE_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `WKCKE` writer"]
pub struct W(crate::W<WKCKE_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<WKCKE_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<WKCKE_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<WKCKE_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `WKCKE` reader - "]
pub type WKCKE_R = crate::BitReader<bool>;
#[doc = "Field `WKCKE` writer - "]
pub type WKCKE_W<'a, const O: u8> = crate::BitWriter<'a, u32, WKCKE_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn wkcke(&self) -> WKCKE_R {
WKCKE_R::new((self.bits & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn wkcke(&mut self) -> WKCKE_W<0> {
WKCKE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "LPUART Wakeup Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wkcke](index.html) module"]
pub struct WKCKE_SPEC;
impl crate::RegisterSpec for WKCKE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [wkcke::R](R) reader structure"]
impl crate::Readable for WKCKE_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [wkcke::W](W) writer structure"]
impl crate::Writable for WKCKE_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets WKCKE to value 0"]
impl crate::Resettable for WKCKE_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "MDS"]
pub struct MDS {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for MDS {}
impl MDS {
#[doc = r"Pointer to the register block"]
pub const PTR: *const mds::RegisterBlock = 0x4001_fc00 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const mds::RegisterBlock {
Self::PTR
}
}
impl Deref for MDS {
type Target = mds::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for MDS {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("MDS").finish()
}
}
#[doc = "MDS"]
pub mod mds {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Trigger Channel 1 Control Register"]
pub trig1cr: TRIG1CR,
#[doc = "0x04 - Trigger Channel 1 Control Register"]
pub trig2cr: TRIG2CR,
#[doc = "0x08 - Trigger Channel 1 Control Register"]
pub trig3cr: TRIG3CR,
#[doc = "0x0c - Trigger Channel 1 Control Register"]
pub trig4cr: TRIG4CR,
#[doc = "0x10 - Trigger Channel 1 Control Register"]
pub trig5cr: TRIG5CR,
#[doc = "0x14 - Trigger Channel 1 Control Register"]
pub trig6cr: TRIG6CR,
#[doc = "0x18 - Trigger Channel 1 Control Register"]
pub trig7cr: TRIG7CR,
#[doc = "0x1c - Trigger Channel 1 Control Register"]
pub trig8cr: TRIG8CR,
_reserved8: [u8; 0x60],
#[doc = "0x80 - Trigger channel CLU1 logic operation input control register"]
pub trig_clu1sel: TRIG_CLU1SEL,
#[doc = "0x84 - Trigger channel CLU1 logic operation input control register"]
pub trig_clu2sel: TRIG_CLU2SEL,
#[doc = "0x88 - Trigger channel CLU1 logic operation input control register"]
pub trig_clu3sel: TRIG_CLU3SEL,
#[doc = "0x8c - Trigger channel CLU1 logic operation input control register"]
pub trig_clu4sel: TRIG_CLU4SEL,
_reserved12: [u8; 0x30],
#[doc = "0xc0 - Trigger Control Register"]
pub trig_clu1cfg: TRIG_CLU1CFG,
_reserved13: [u8; 0x38],
#[doc = "0xfc - Software Trigger Control Register"]
pub swtrig: SWTRIG,
#[doc = "0x100 - Connect Channel 1 Control Register"]
pub conn1cr: CONN1CR,
#[doc = "0x104 - Connect Channel 1 Control Register"]
pub conn2cr: CONN2CR,
#[doc = "0x108 - Connect Channel 1 Control Register"]
pub conn3cr: CONN3CR,
#[doc = "0x10c - Connect Channel 1 Control Register"]
pub conn4cr: CONN4CR,
#[doc = "0x110 - Connect Channel 1 Control Register"]
pub conn5cr: CONN5CR,
#[doc = "0x114 - Connect Channel 1 Control Register"]
pub conn6cr: CONN6CR,
#[doc = "0x118 - Connect Channel 1 Control Register"]
pub conn7cr: CONN7CR,
_reserved21: [u8; 0x64],
#[doc = "0x180 - Connection channel CLU1 logic operation input control register"]
pub conn_clu1sel: CONN_CLU1SEL,
#[doc = "0x184 - Connection channel CLU1 logic operation input control register"]
pub conn_clu2sel: CONN_CLU2SEL,
#[doc = "0x188 - Connection channel CLU1 logic operation input control register"]
pub conn_clu3sel: CONN_CLU3SEL,
#[doc = "0x18c - Connection channel CLU1 logic operation input control register"]
pub conn_clu4sel: CONN_CLU4SEL,
_reserved25: [u8; 0x30],
#[doc = "0x1c0 - Connection Channel CLU1 Logic Operation Configuration Register"]
pub conn_clu1cfg: CONN_CLU1CFG,
#[doc = "0x1c4 - Connection Channel CLU1 Logic Operation Configuration Register"]
pub conn_clu2cfg: CONN_CLU2CFG,
#[doc = "0x1c8 - Connection Channel CLU1 Logic Operation Configuration Register"]
pub conn_clu3cfg: CONN_CLU3CFG,
#[doc = "0x1cc - Connection Channel CLU1 Logic Operation Configuration Register"]
pub conn_clu4cfg: CONN_CLU4CFG,
}
#[doc = "TRIG1CR (rw) register accessor: an alias for `Reg<TRIG1CR_SPEC>`"]
pub type TRIG1CR = crate::Reg<trig1cr::TRIG1CR_SPEC>;
#[doc = "Trigger Channel 1 Control Register"]
pub mod trig1cr {
#[doc = "Register `TRIG1CR` reader"]
pub struct R(crate::R<TRIG1CR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<TRIG1CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<TRIG1CR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<TRIG1CR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `TRIG1CR` writer"]
pub struct W(crate::W<TRIG1CR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<TRIG1CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<TRIG1CR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<TRIG1CR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TRGSEL` reader - "]
pub type TRGSEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TRGSEL` writer - "]
pub type TRGSEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, TRIG1CR_SPEC, u8, u8, 6, O>;
#[doc = "Field `CLUEN` reader - "]
pub type CLUEN_R = crate::BitReader<bool>;
#[doc = "Field `CLUEN` writer - "]
pub type CLUEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, TRIG1CR_SPEC, bool, O>;
#[doc = "Field `CLUSEL` reader - "]
pub type CLUSEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLUSEL` writer - "]
pub type CLUSEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, TRIG1CR_SPEC, u8, u8, 2, O>;
#[doc = "Field `EDGESEL` reader - "]
pub type EDGESEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EDGESEL` writer - "]
pub type EDGESEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, TRIG1CR_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn trgsel(&self) -> TRGSEL_R {
TRGSEL_R::new((self.bits & 0x3f) as u8)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn cluen(&self) -> CLUEN_R {
CLUEN_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 17:18"]
#[inline(always)]
pub fn clusel(&self) -> CLUSEL_R {
CLUSEL_R::new(((self.bits >> 17) & 3) as u8)
}
#[doc = "Bits 24:25"]
#[inline(always)]
pub fn edgesel(&self) -> EDGESEL_R {
EDGESEL_R::new(((self.bits >> 24) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn trgsel(&mut self) -> TRGSEL_W<0> {
TRGSEL_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn cluen(&mut self) -> CLUEN_W<16> {
CLUEN_W::new(self)
}
#[doc = "Bits 17:18"]
#[inline(always)]
#[must_use]
pub fn clusel(&mut self) -> CLUSEL_W<17> {
CLUSEL_W::new(self)
}
#[doc = "Bits 24:25"]
#[inline(always)]
#[must_use]
pub fn edgesel(&mut self) -> EDGESEL_W<24> {
EDGESEL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Trigger Channel 1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [trig1cr](index.html) module"]
pub struct TRIG1CR_SPEC;
impl crate::RegisterSpec for TRIG1CR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [trig1cr::R](R) reader structure"]
impl crate::Readable for TRIG1CR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [trig1cr::W](W) writer structure"]
impl crate::Writable for TRIG1CR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets TRIG1CR to value 0"]
impl crate::Resettable for TRIG1CR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
pub use trig1cr as trig2cr;
pub use trig1cr as trig3cr;
pub use trig1cr as trig4cr;
pub use trig1cr as trig5cr;
pub use trig1cr as trig6cr;
pub use trig1cr as trig7cr;
pub use trig1cr as trig8cr;
pub use TRIG1CR as TRIG2CR;
pub use TRIG1CR as TRIG3CR;
pub use TRIG1CR as TRIG4CR;
pub use TRIG1CR as TRIG5CR;
pub use TRIG1CR as TRIG6CR;
pub use TRIG1CR as TRIG7CR;
pub use TRIG1CR as TRIG8CR;
#[doc = "TRIG_CLU1SEL (rw) register accessor: an alias for `Reg<TRIG_CLU1SEL_SPEC>`"]
pub type TRIG_CLU1SEL = crate::Reg<trig_clu1sel::TRIG_CLU1SEL_SPEC>;
#[doc = "Trigger channel CLU1 logic operation input control register"]
pub mod trig_clu1sel {
#[doc = "Register `TRIG_CLU1SEL` reader"]
pub struct R(crate::R<TRIG_CLU1SEL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<TRIG_CLU1SEL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<TRIG_CLU1SEL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<TRIG_CLU1SEL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `TRIG_CLU1SEL` writer"]
pub struct W(crate::W<TRIG_CLU1SEL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<TRIG_CLU1SEL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<TRIG_CLU1SEL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<TRIG_CLU1SEL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CLUIN0_SEL` reader - "]
pub type CLUIN0_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLUIN0_SEL` writer - "]
pub type CLUIN0_SEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, TRIG_CLU1SEL_SPEC, u8, u8, 8, O>;
#[doc = "Field `CLUIN1_SEL` reader - "]
pub type CLUIN1_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLUIN1_SEL` writer - "]
pub type CLUIN1_SEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, TRIG_CLU1SEL_SPEC, u8, u8, 8, O>;
#[doc = "Field `CLUIN2_SEL` reader - "]
pub type CLUIN2_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLUIN2_SEL` writer - "]
pub type CLUIN2_SEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, TRIG_CLU1SEL_SPEC, u8, u8, 8, O>;
#[doc = "Field `CLUIN3_SEL` reader - "]
pub type CLUIN3_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLUIN3_SEL` writer - "]
pub type CLUIN3_SEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, TRIG_CLU1SEL_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn cluin0_sel(&self) -> CLUIN0_SEL_R {
CLUIN0_SEL_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15"]
#[inline(always)]
pub fn cluin1_sel(&self) -> CLUIN1_SEL_R {
CLUIN1_SEL_R::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23"]
#[inline(always)]
pub fn cluin2_sel(&self) -> CLUIN2_SEL_R {
CLUIN2_SEL_R::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn cluin3_sel(&self) -> CLUIN3_SEL_R {
CLUIN3_SEL_R::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn cluin0_sel(&mut self) -> CLUIN0_SEL_W<0> {
CLUIN0_SEL_W::new(self)
}
#[doc = "Bits 8:15"]
#[inline(always)]
#[must_use]
pub fn cluin1_sel(&mut self) -> CLUIN1_SEL_W<8> {
CLUIN1_SEL_W::new(self)
}
#[doc = "Bits 16:23"]
#[inline(always)]
#[must_use]
pub fn cluin2_sel(&mut self) -> CLUIN2_SEL_W<16> {
CLUIN2_SEL_W::new(self)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn cluin3_sel(&mut self) -> CLUIN3_SEL_W<24> {
CLUIN3_SEL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Trigger channel CLU1 logic operation input control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [trig_clu1sel](index.html) module"]
pub struct TRIG_CLU1SEL_SPEC;
impl crate::RegisterSpec for TRIG_CLU1SEL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [trig_clu1sel::R](R) reader structure"]
impl crate::Readable for TRIG_CLU1SEL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [trig_clu1sel::W](W) writer structure"]
impl crate::Writable for TRIG_CLU1SEL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets TRIG_CLU1SEL to value 0"]
impl crate::Resettable for TRIG_CLU1SEL_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
pub use trig_clu1sel as trig_clu2sel;
pub use trig_clu1sel as trig_clu3sel;
pub use trig_clu1sel as trig_clu4sel;
pub use TRIG_CLU1SEL as TRIG_CLU2SEL;
pub use TRIG_CLU1SEL as TRIG_CLU3SEL;
pub use TRIG_CLU1SEL as TRIG_CLU4SEL;
#[doc = "TRIG_CLU1CFG (rw) register accessor: an alias for `Reg<TRIG_CLU1CFG_SPEC>`"]
pub type TRIG_CLU1CFG = crate::Reg<trig_clu1cfg::TRIG_CLU1CFG_SPEC>;
#[doc = "Trigger Control Register"]
pub mod trig_clu1cfg {
#[doc = "Register `TRIG_CLU1CFG` reader"]
pub struct R(crate::R<TRIG_CLU1CFG_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<TRIG_CLU1CFG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<TRIG_CLU1CFG_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<TRIG_CLU1CFG_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `TRIG_CLU1CFG` writer"]
pub struct W(crate::W<TRIG_CLU1CFG_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<TRIG_CLU1CFG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<TRIG_CLU1CFG_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<TRIG_CLU1CFG_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CLUIN0_ED ` reader - "]
pub type CLUIN0_ED_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLUIN0_ED ` writer - "]
pub type CLUIN0_ED_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, TRIG_CLU1CFG_SPEC, u8, u8, 2, O>;
#[doc = "Field `CLUIN1_ED ` reader - "]
pub type CLUIN1_ED_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLUIN1_ED ` writer - "]
pub type CLUIN1_ED_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, TRIG_CLU1CFG_SPEC, u8, u8, 2, O>;
#[doc = "Field `CLUIN2_ED ` reader - "]
pub type CLUIN2_ED_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLUIN2_ED ` writer - "]
pub type CLUIN2_ED_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, TRIG_CLU1CFG_SPEC, u8, u8, 2, O>;
#[doc = "Field `CLUIN3_ED ` reader - "]
pub type CLUIN3_ED_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLUIN3_ED ` writer - "]
pub type CLUIN3_ED_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, TRIG_CLU1CFG_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn cluin0_ed(&self) -> CLUIN0_ED_R {
CLUIN0_ED_R::new((self.bits & 3) as u8)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn cluin1_ed(&self) -> CLUIN1_ED_R {
CLUIN1_ED_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 16:17"]
#[inline(always)]
pub fn cluin2_ed(&self) -> CLUIN2_ED_R {
CLUIN2_ED_R::new(((self.bits >> 16) & 3) as u8)
}
#[doc = "Bits 24:25"]
#[inline(always)]
pub fn cluin3_ed(&self) -> CLUIN3_ED_R {
CLUIN3_ED_R::new(((self.bits >> 24) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn cluin0_ed(&mut self) -> CLUIN0_ED_W<0> {
CLUIN0_ED_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn cluin1_ed(&mut self) -> CLUIN1_ED_W<8> {
CLUIN1_ED_W::new(self)
}
#[doc = "Bits 16:17"]
#[inline(always)]
#[must_use]
pub fn cluin2_ed(&mut self) -> CLUIN2_ED_W<16> {
CLUIN2_ED_W::new(self)
}
#[doc = "Bits 24:25"]
#[inline(always)]
#[must_use]
pub fn cluin3_ed(&mut self) -> CLUIN3_ED_W<24> {
CLUIN3_ED_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Trigger Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [trig_clu1cfg](index.html) module"]
pub struct TRIG_CLU1CFG_SPEC;
impl crate::RegisterSpec for TRIG_CLU1CFG_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [trig_clu1cfg::R](R) reader structure"]
impl crate::Readable for TRIG_CLU1CFG_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [trig_clu1cfg::W](W) writer structure"]
impl crate::Writable for TRIG_CLU1CFG_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets TRIG_CLU1CFG to value 0"]
impl crate::Resettable for TRIG_CLU1CFG_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SWTRIG (w) register accessor: an alias for `Reg<SWTRIG_SPEC>`"]
pub type SWTRIG = crate::Reg<swtrig::SWTRIG_SPEC>;
#[doc = "Software Trigger Control Register"]
pub mod swtrig {
#[doc = "Register `SWTRIG` writer"]
pub struct W(crate::W<SWTRIG_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SWTRIG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SWTRIG_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SWTRIG_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SW_TRIG` writer - "]
pub type SW_TRIG_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIG_SPEC, bool, O>;
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn sw_trig(&mut self) -> SW_TRIG_W<0> {
SW_TRIG_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Software Trigger Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrig](index.html) module"]
pub struct SWTRIG_SPEC;
impl crate::RegisterSpec for SWTRIG_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [swtrig::W](W) writer structure"]
impl crate::Writable for SWTRIG_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SWTRIG to value 0"]
impl crate::Resettable for SWTRIG_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CONN1CR (rw) register accessor: an alias for `Reg<CONN1CR_SPEC>`"]
pub type CONN1CR = crate::Reg<conn1cr::CONN1CR_SPEC>;
#[doc = "Connect Channel 1 Control Register"]
pub mod conn1cr {
#[doc = "Register `CONN1CR` reader"]
pub struct R(crate::R<CONN1CR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CONN1CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CONN1CR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CONN1CR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CONN1CR` writer"]
pub struct W(crate::W<CONN1CR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CONN1CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CONN1CR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CONN1CR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TRGSEL` reader - "]
pub type TRGSEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TRGSEL` writer - "]
pub type TRGSEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CONN1CR_SPEC, u8, u8, 6, O>;
#[doc = "Field `CLUEN` reader - "]
pub type CLUEN_R = crate::BitReader<bool>;
#[doc = "Field `CLUEN` writer - "]
pub type CLUEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONN1CR_SPEC, bool, O>;
#[doc = "Field `CLUSEL` reader - "]
pub type CLUSEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLUSEL` writer - "]
pub type CLUSEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CONN1CR_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn trgsel(&self) -> TRGSEL_R {
TRGSEL_R::new((self.bits & 0x3f) as u8)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn cluen(&self) -> CLUEN_R {
CLUEN_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 17:18"]
#[inline(always)]
pub fn clusel(&self) -> CLUSEL_R {
CLUSEL_R::new(((self.bits >> 17) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn trgsel(&mut self) -> TRGSEL_W<0> {
TRGSEL_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn cluen(&mut self) -> CLUEN_W<16> {
CLUEN_W::new(self)
}
#[doc = "Bits 17:18"]
#[inline(always)]
#[must_use]
pub fn clusel(&mut self) -> CLUSEL_W<17> {
CLUSEL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Connect Channel 1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [conn1cr](index.html) module"]
pub struct CONN1CR_SPEC;
impl crate::RegisterSpec for CONN1CR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [conn1cr::R](R) reader structure"]
impl crate::Readable for CONN1CR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [conn1cr::W](W) writer structure"]
impl crate::Writable for CONN1CR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CONN1CR to value 0"]
impl crate::Resettable for CONN1CR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
pub use conn1cr as conn2cr;
pub use conn1cr as conn3cr;
pub use conn1cr as conn4cr;
pub use conn1cr as conn5cr;
pub use conn1cr as conn6cr;
pub use conn1cr as conn7cr;
pub use CONN1CR as CONN2CR;
pub use CONN1CR as CONN3CR;
pub use CONN1CR as CONN4CR;
pub use CONN1CR as CONN5CR;
pub use CONN1CR as CONN6CR;
pub use CONN1CR as CONN7CR;
#[doc = "CONN_CLU1SEL (rw) register accessor: an alias for `Reg<CONN_CLU1SEL_SPEC>`"]
pub type CONN_CLU1SEL = crate::Reg<conn_clu1sel::CONN_CLU1SEL_SPEC>;
#[doc = "Connection channel CLU1 logic operation input control register"]
pub mod conn_clu1sel {
#[doc = "Register `CONN_CLU1SEL` reader"]
pub struct R(crate::R<CONN_CLU1SEL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CONN_CLU1SEL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CONN_CLU1SEL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CONN_CLU1SEL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CONN_CLU1SEL` writer"]
pub struct W(crate::W<CONN_CLU1SEL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CONN_CLU1SEL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CONN_CLU1SEL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CONN_CLU1SEL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CLUIN0_SEL` reader - "]
pub type CLUIN0_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLUIN0_SEL` writer - "]
pub type CLUIN0_SEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CONN_CLU1SEL_SPEC, u8, u8, 8, O>;
#[doc = "Field `CLUIN1_SEL` reader - "]
pub type CLUIN1_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLUIN1_SEL` writer - "]
pub type CLUIN1_SEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CONN_CLU1SEL_SPEC, u8, u8, 8, O>;
#[doc = "Field `CLUIN2_SEL` reader - "]
pub type CLUIN2_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLUIN2_SEL` writer - "]
pub type CLUIN2_SEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CONN_CLU1SEL_SPEC, u8, u8, 8, O>;
#[doc = "Field `CLUIN3_SEL` reader - "]
pub type CLUIN3_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLUIN3_SEL` writer - "]
pub type CLUIN3_SEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CONN_CLU1SEL_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn cluin0_sel(&self) -> CLUIN0_SEL_R {
CLUIN0_SEL_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15"]
#[inline(always)]
pub fn cluin1_sel(&self) -> CLUIN1_SEL_R {
CLUIN1_SEL_R::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23"]
#[inline(always)]
pub fn cluin2_sel(&self) -> CLUIN2_SEL_R {
CLUIN2_SEL_R::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31"]
#[inline(always)]
pub fn cluin3_sel(&self) -> CLUIN3_SEL_R {
CLUIN3_SEL_R::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn cluin0_sel(&mut self) -> CLUIN0_SEL_W<0> {
CLUIN0_SEL_W::new(self)
}
#[doc = "Bits 8:15"]
#[inline(always)]
#[must_use]
pub fn cluin1_sel(&mut self) -> CLUIN1_SEL_W<8> {
CLUIN1_SEL_W::new(self)
}
#[doc = "Bits 16:23"]
#[inline(always)]
#[must_use]
pub fn cluin2_sel(&mut self) -> CLUIN2_SEL_W<16> {
CLUIN2_SEL_W::new(self)
}
#[doc = "Bits 24:31"]
#[inline(always)]
#[must_use]
pub fn cluin3_sel(&mut self) -> CLUIN3_SEL_W<24> {
CLUIN3_SEL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Connection channel CLU1 logic operation input control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [conn_clu1sel](index.html) module"]
pub struct CONN_CLU1SEL_SPEC;
impl crate::RegisterSpec for CONN_CLU1SEL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [conn_clu1sel::R](R) reader structure"]
impl crate::Readable for CONN_CLU1SEL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [conn_clu1sel::W](W) writer structure"]
impl crate::Writable for CONN_CLU1SEL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CONN_CLU1SEL to value 0"]
impl crate::Resettable for CONN_CLU1SEL_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
pub use conn_clu1sel as conn_clu2sel;
pub use conn_clu1sel as conn_clu3sel;
pub use conn_clu1sel as conn_clu4sel;
pub use CONN_CLU1SEL as CONN_CLU2SEL;
pub use CONN_CLU1SEL as CONN_CLU3SEL;
pub use CONN_CLU1SEL as CONN_CLU4SEL;
#[doc = "CONN_CLU1CFG (rw) register accessor: an alias for `Reg<CONN_CLU1CFG_SPEC>`"]
pub type CONN_CLU1CFG = crate::Reg<conn_clu1cfg::CONN_CLU1CFG_SPEC>;
#[doc = "Connection Channel CLU1 Logic Operation Configuration Register"]
pub mod conn_clu1cfg {
#[doc = "Register `CONN_CLU1CFG` reader"]
pub struct R(crate::R<CONN_CLU1CFG_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CONN_CLU1CFG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CONN_CLU1CFG_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CONN_CLU1CFG_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CONN_CLU1CFG` writer"]
pub struct W(crate::W<CONN_CLU1CFG_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CONN_CLU1CFG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CONN_CLU1CFG_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CONN_CLU1CFG_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CLMODE` reader - "]
pub type CLMODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLMODE` writer - "]
pub type CLMODE_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CONN_CLU1CFG_SPEC, u8, u8, 2, O>;
#[doc = "Field `INV0` reader - "]
pub type INV0_R = crate::BitReader<bool>;
#[doc = "Field `INV0` writer - "]
pub type INV0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONN_CLU1CFG_SPEC, bool, O>;
#[doc = "Field `INV1` reader - "]
pub type INV1_R = crate::BitReader<bool>;
#[doc = "Field `INV1` writer - "]
pub type INV1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONN_CLU1CFG_SPEC, bool, O>;
#[doc = "Field `INV2` reader - "]
pub type INV2_R = crate::BitReader<bool>;
#[doc = "Field `INV2` writer - "]
pub type INV2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONN_CLU1CFG_SPEC, bool, O>;
#[doc = "Field `INV3` reader - "]
pub type INV3_R = crate::BitReader<bool>;
#[doc = "Field `INV3` writer - "]
pub type INV3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONN_CLU1CFG_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn clmode(&self) -> CLMODE_R {
CLMODE_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn inv0(&self) -> INV0_R {
INV0_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn inv1(&self) -> INV1_R {
INV1_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn inv2(&self) -> INV2_R {
INV2_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn inv3(&self) -> INV3_R {
INV3_R::new(((self.bits >> 11) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn clmode(&mut self) -> CLMODE_W<0> {
CLMODE_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn inv0(&mut self) -> INV0_W<8> {
INV0_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn inv1(&mut self) -> INV1_W<9> {
INV1_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn inv2(&mut self) -> INV2_W<10> {
INV2_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn inv3(&mut self) -> INV3_W<11> {
INV3_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Connection Channel CLU1 Logic Operation Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [conn_clu1cfg](index.html) module"]
pub struct CONN_CLU1CFG_SPEC;
impl crate::RegisterSpec for CONN_CLU1CFG_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [conn_clu1cfg::R](R) reader structure"]
impl crate::Readable for CONN_CLU1CFG_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [conn_clu1cfg::W](W) writer structure"]
impl crate::Writable for CONN_CLU1CFG_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CONN_CLU1CFG to value 0"]
impl crate::Resettable for CONN_CLU1CFG_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
pub use conn_clu1cfg as conn_clu2cfg;
pub use conn_clu1cfg as conn_clu3cfg;
pub use conn_clu1cfg as conn_clu4cfg;
pub use CONN_CLU1CFG as CONN_CLU2CFG;
pub use CONN_CLU1CFG as CONN_CLU3CFG;
pub use CONN_CLU1CFG as CONN_CLU4CFG;
}
#[doc = "PWR"]
pub struct PWR {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for PWR {}
impl PWR {
#[doc = r"Pointer to the register block"]
pub const PTR: *const pwr::RegisterBlock = 0x4000_7000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const pwr::RegisterBlock {
Self::PTR
}
}
impl Deref for PWR {
type Target = pwr::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for PWR {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("PWR").finish()
}
}
#[doc = "PWR"]
pub mod pwr {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Power Control Register 1"]
pub cr1: CR1,
#[doc = "0x04 - Power Control Status Register"]
pub csr: CSR,
#[doc = "0x08 - Power Control Register 2"]
pub cr2: CR2,
#[doc = "0x0c - Power Control Register 3"]
pub cr3: CR3,
#[doc = "0x10 - Power Control Register 4"]
pub cr4: CR4,
#[doc = "0x14 - Power Control Register 5"]
pub cr5: CR5,
#[doc = "0x18 - Power Control Register 6"]
pub cr6: CR6,
#[doc = "0x1c - Power Status Register"]
pub sr: SR,
#[doc = "0x20 - Power Status Clear Register"]
pub scr: SCR,
#[doc = "0x24 - Power Configuration Register"]
pub cfgr: CFGR,
}
#[doc = "CR1 (rw) register accessor: an alias for `Reg<CR1_SPEC>`"]
pub type CR1 = crate::Reg<cr1::CR1_SPEC>;
#[doc = "Power Control Register 1"]
pub mod cr1 {
#[doc = "Register `CR1` reader"]
pub struct R(crate::R<CR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR1` writer"]
pub struct W(crate::W<CR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `LPDS` reader - "]
pub type LPDS_R = crate::BitReader<bool>;
#[doc = "Field `LPDS` writer - "]
pub type LPDS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `PDDS` reader - "]
pub type PDDS_R = crate::BitReader<bool>;
#[doc = "Field `PDDS` writer - "]
pub type PDDS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `CSBF` writer - "]
pub type CSBF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `LPR` reader - "]
pub type LPR_R = crate::BitReader<bool>;
#[doc = "Field `LPR` writer - "]
pub type LPR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `VOS` reader - "]
pub type VOS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `VOS` writer - "]
pub type VOS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR1_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn lpds(&self) -> LPDS_R {
LPDS_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn pdds(&self) -> PDDS_R {
PDDS_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn lpr(&self) -> LPR_R {
LPR_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn vos(&self) -> VOS_R {
VOS_R::new(((self.bits >> 14) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn lpds(&mut self) -> LPDS_W<0> {
LPDS_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn pdds(&mut self) -> PDDS_W<1> {
PDDS_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn csbf(&mut self) -> CSBF_W<3> {
CSBF_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn lpr(&mut self) -> LPR_W<13> {
LPR_W::new(self)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn vos(&mut self) -> VOS_W<14> {
VOS_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Power Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr1](index.html) module"]
pub struct CR1_SPEC;
impl crate::RegisterSpec for CR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr1::R](R) reader structure"]
impl crate::Readable for CR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr1::W](W) writer structure"]
impl crate::Writable for CR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for CR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CSR (r) register accessor: an alias for `Reg<CSR_SPEC>`"]
pub type CSR = crate::Reg<csr::CSR_SPEC>;
#[doc = "Power Control Status Register"]
pub mod csr {
#[doc = "Register `CSR` reader"]
pub struct R(crate::R<CSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `SBF` reader - "]
pub type SBF_R = crate::BitReader<bool>;
#[doc = "Field `VOSRDY` reader - "]
pub type VOSRDY_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 1"]
#[inline(always)]
pub fn sbf(&self) -> SBF_R {
SBF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn vosrdy(&self) -> VOSRDY_R {
VOSRDY_R::new(((self.bits >> 14) & 1) != 0)
}
}
#[doc = "Power Control Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"]
pub struct CSR_SPEC;
impl crate::RegisterSpec for CSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [csr::R](R) reader structure"]
impl crate::Readable for CSR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets CSR to value 0"]
impl crate::Resettable for CSR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CR2 (rw) register accessor: an alias for `Reg<CR2_SPEC>`"]
pub type CR2 = crate::Reg<cr2::CR2_SPEC>;
#[doc = "Power Control Register 2"]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub struct R(crate::R<CR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR2` writer"]
pub struct W(crate::W<CR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EWUP` reader - "]
pub type EWUP_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EWUP` writer - "]
pub type EWUP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR2_SPEC, u8, u8, 6, O>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn ewup(&self) -> EWUP_R {
EWUP_R::new((self.bits & 0x3f) as u8)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn ewup(&mut self) -> EWUP_W<0> {
EWUP_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Power Control Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr2](index.html) module"]
pub struct CR2_SPEC;
impl crate::RegisterSpec for CR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr2::R](R) reader structure"]
impl crate::Readable for CR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr2::W](W) writer structure"]
impl crate::Writable for CR2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for CR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CR3 (rw) register accessor: an alias for `Reg<CR3_SPEC>`"]
pub type CR3 = crate::Reg<cr3::CR3_SPEC>;
#[doc = "Power Control Register 3"]
pub mod cr3 {
#[doc = "Register `CR3` reader"]
pub struct R(crate::R<CR3_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR3_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR3_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR3` writer"]
pub struct W(crate::W<CR3_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR3_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR3_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `WP` reader - "]
pub type WP_R = crate::FieldReader<u8, u8>;
#[doc = "Field `WP` writer - "]
pub type WP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR3_SPEC, u8, u8, 6, O>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn wp(&self) -> WP_R {
WP_R::new((self.bits & 0x3f) as u8)
}
}
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn wp(&mut self) -> WP_W<0> {
WP_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Power Control Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr3](index.html) module"]
pub struct CR3_SPEC;
impl crate::RegisterSpec for CR3_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr3::R](R) reader structure"]
impl crate::Readable for CR3_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr3::W](W) writer structure"]
impl crate::Writable for CR3_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR3 to value 0"]
impl crate::Resettable for CR3_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CR4 (rw) register accessor: an alias for `Reg<CR4_SPEC>`"]
pub type CR4 = crate::Reg<cr4::CR4_SPEC>;
#[doc = "Power Control Register 4"]
pub mod cr4 {
#[doc = "Register `CR4` reader"]
pub struct R(crate::R<CR4_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR4_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR4_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR4_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR4` writer"]
pub struct W(crate::W<CR4_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR4_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR4_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR4_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `FILTSEL0` reader - "]
pub type FILTSEL0_R = crate::FieldReader<u8, u8>;
#[doc = "Field `FILTSEL0` writer - "]
pub type FILTSEL0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR4_SPEC, u8, u8, 2, O>;
#[doc = "Field `FILTE0` reader - "]
pub type FILTE0_R = crate::FieldReader<u8, u8>;
#[doc = "Field `FILTE0` writer - "]
pub type FILTE0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR4_SPEC, u8, u8, 2, O>;
#[doc = "Field `FILTF0` reader - "]
pub type FILTF0_R = crate::BitReader<bool>;
#[doc = "Field `FILTF0` writer - "]
pub type FILTF0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR4_SPEC, bool, O>;
#[doc = "Field `FILTCNT0` reader - "]
pub type FILTCNT0_R = crate::FieldReader<u8, u8>;
#[doc = "Field `FILTCNT0` writer - "]
pub type FILTCNT0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR4_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn filtsel0(&self) -> FILTSEL0_R {
FILTSEL0_R::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3"]
#[inline(always)]
pub fn filte0(&self) -> FILTE0_R {
FILTE0_R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn filtf0(&self) -> FILTF0_R {
FILTF0_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 8:15"]
#[inline(always)]
pub fn filtcnt0(&self) -> FILTCNT0_R {
FILTCNT0_R::new(((self.bits >> 8) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn filtsel0(&mut self) -> FILTSEL0_W<0> {
FILTSEL0_W::new(self)
}
#[doc = "Bits 2:3"]
#[inline(always)]
#[must_use]
pub fn filte0(&mut self) -> FILTE0_W<2> {
FILTE0_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn filtf0(&mut self) -> FILTF0_W<4> {
FILTF0_W::new(self)
}
#[doc = "Bits 8:15"]
#[inline(always)]
#[must_use]
pub fn filtcnt0(&mut self) -> FILTCNT0_W<8> {
FILTCNT0_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Power Control Register 4\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr4](index.html) module"]
pub struct CR4_SPEC;
impl crate::RegisterSpec for CR4_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr4::R](R) reader structure"]
impl crate::Readable for CR4_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr4::W](W) writer structure"]
impl crate::Writable for CR4_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR4 to value 0x0f00"]
impl crate::Resettable for CR4_SPEC {
const RESET_VALUE: Self::Ux = 0x0f00;
}
}
#[doc = "CR5 (rw) register accessor: an alias for `Reg<CR5_SPEC>`"]
pub type CR5 = crate::Reg<cr5::CR5_SPEC>;
#[doc = "Power Control Register 5"]
pub mod cr5 {
#[doc = "Register `CR5` reader"]
pub struct R(crate::R<CR5_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR5_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR5_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR5_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR5` writer"]
pub struct W(crate::W<CR5_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR5_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR5_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR5_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `FILTSEL1` reader - "]
pub type FILTSEL1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `FILTSEL1` writer - "]
pub type FILTSEL1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR5_SPEC, u8, u8, 2, O>;
#[doc = "Field `FILTE1` reader - "]
pub type FILTE1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `FILTE1` writer - "]
pub type FILTE1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR5_SPEC, u8, u8, 2, O>;
#[doc = "Field `FILTF1` reader - "]
pub type FILTF1_R = crate::BitReader<bool>;
#[doc = "Field `FILTF1` writer - "]
pub type FILTF1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR5_SPEC, bool, O>;
#[doc = "Field `FILTCNT1` reader - "]
pub type FILTCNT1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `FILTCNT1` writer - "]
pub type FILTCNT1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR5_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn filtsel1(&self) -> FILTSEL1_R {
FILTSEL1_R::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3"]
#[inline(always)]
pub fn filte1(&self) -> FILTE1_R {
FILTE1_R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn filtf1(&self) -> FILTF1_R {
FILTF1_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 8:15"]
#[inline(always)]
pub fn filtcnt1(&self) -> FILTCNT1_R {
FILTCNT1_R::new(((self.bits >> 8) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn filtsel1(&mut self) -> FILTSEL1_W<0> {
FILTSEL1_W::new(self)
}
#[doc = "Bits 2:3"]
#[inline(always)]
#[must_use]
pub fn filte1(&mut self) -> FILTE1_W<2> {
FILTE1_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn filtf1(&mut self) -> FILTF1_W<4> {
FILTF1_W::new(self)
}
#[doc = "Bits 8:15"]
#[inline(always)]
#[must_use]
pub fn filtcnt1(&mut self) -> FILTCNT1_W<8> {
FILTCNT1_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Power Control Register 5\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr5](index.html) module"]
pub struct CR5_SPEC;
impl crate::RegisterSpec for CR5_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr5::R](R) reader structure"]
impl crate::Readable for CR5_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr5::W](W) writer structure"]
impl crate::Writable for CR5_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR5 to value 0x0f00"]
impl crate::Resettable for CR5_SPEC {
const RESET_VALUE: Self::Ux = 0x0f00;
}
}
#[doc = "CR6 (rw) register accessor: an alias for `Reg<CR6_SPEC>`"]
pub type CR6 = crate::Reg<cr6::CR6_SPEC>;
#[doc = "Power Control Register 6"]
pub mod cr6 {
#[doc = "Register `CR6` reader"]
pub struct R(crate::R<CR6_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR6_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR6_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR6_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR6` writer"]
pub struct W(crate::W<CR6_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR6_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR6_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR6_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `STDBY_FS_WK` reader - "]
pub type STDBY_FS_WK_R = crate::FieldReader<u8, u8>;
#[doc = "Field `STDBY_FS_WK` writer - "]
pub type STDBY_FS_WK_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CR6_SPEC, u8, u8, 3, O>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn stdby_fs_wk(&self) -> STDBY_FS_WK_R {
STDBY_FS_WK_R::new((self.bits & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:2"]
#[inline(always)]
#[must_use]
pub fn stdby_fs_wk(&mut self) -> STDBY_FS_WK_W<0> {
STDBY_FS_WK_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Power Control Register 6\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr6](index.html) module"]
pub struct CR6_SPEC;
impl crate::RegisterSpec for CR6_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr6::R](R) reader structure"]
impl crate::Readable for CR6_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr6::W](W) writer structure"]
impl crate::Writable for CR6_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR6 to value 0"]
impl crate::Resettable for CR6_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SR (r) register accessor: an alias for `Reg<SR_SPEC>`"]
pub type SR = crate::Reg<sr::SR_SPEC>;
#[doc = "Power Status Register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub struct R(crate::R<SR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `WUF` reader - "]
pub type WUF_R = crate::FieldReader<u8, u8>;
impl R {
#[doc = "Bits 0:5"]
#[inline(always)]
pub fn wuf(&self) -> WUF_R {
WUF_R::new((self.bits & 0x3f) as u8)
}
}
#[doc = "Power Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"]
pub struct SR_SPEC;
impl crate::RegisterSpec for SR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [sr::R](R) reader structure"]
impl crate::Readable for SR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SCR (w) register accessor: an alias for `Reg<SCR_SPEC>`"]
pub type SCR = crate::Reg<scr::SCR_SPEC>;
#[doc = "Power Status Clear Register"]
pub mod scr {
#[doc = "Register `SCR` writer"]
pub struct W(crate::W<SCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CWUF` writer - "]
pub type CWUF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SCR_SPEC, u8, u8, 6, O>;
impl W {
#[doc = "Bits 0:5"]
#[inline(always)]
#[must_use]
pub fn cwuf(&mut self) -> CWUF_W<0> {
CWUF_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Power Status Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"]
pub struct SCR_SPEC;
impl crate::RegisterSpec for SCR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"]
impl crate::Writable for SCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SCR to value 0"]
impl crate::Resettable for SCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CFGR (rw) register accessor: an alias for `Reg<CFGR_SPEC>`"]
pub type CFGR = crate::Reg<cfgr::CFGR_SPEC>;
#[doc = "Power Configuration Register"]
pub mod cfgr {
#[doc = "Register `CFGR` reader"]
pub struct R(crate::R<CFGR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CFGR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CFGR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CFGR` writer"]
pub struct W(crate::W<CFGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CFGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CFGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `LSICALSEL` writer - "]
pub type LSICALSEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CFGR_SPEC, u8, u8, 5, O>;
#[doc = "Field `LSICAL` reader - "]
pub type LSICAL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `LSICAL` writer - "]
pub type LSICAL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR_SPEC, u8, u8, 5, O>;
impl R {
#[doc = "Bits 5:9"]
#[inline(always)]
pub fn lsical(&self) -> LSICAL_R {
LSICAL_R::new(((self.bits >> 5) & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:4"]
#[inline(always)]
#[must_use]
pub fn lsicalsel(&mut self) -> LSICALSEL_W<0> {
LSICALSEL_W::new(self)
}
#[doc = "Bits 5:9"]
#[inline(always)]
#[must_use]
pub fn lsical(&mut self) -> LSICAL_W<5> {
LSICAL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Power Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr](index.html) module"]
pub struct CFGR_SPEC;
impl crate::RegisterSpec for CFGR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cfgr::R](R) reader structure"]
impl crate::Readable for CFGR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfgr::W](W) writer structure"]
impl crate::Writable for CFGR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CFGR to value 0x0160"]
impl crate::Resettable for CFGR_SPEC {
const RESET_VALUE: Self::Ux = 0x0160;
}
}
}
#[doc = "QSPI"]
pub struct QSPI {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for QSPI {}
impl QSPI {
#[doc = r"Pointer to the register block"]
pub const PTR: *const qspi::RegisterBlock = 0xa000_1000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const qspi::RegisterBlock {
Self::PTR
}
}
impl Deref for QSPI {
type Target = qspi::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for QSPI {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("QSPI").finish()
}
}
#[doc = "QSPI"]
pub mod qspi {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - control register"]
pub cr: CR,
#[doc = "0x04 - status register"]
pub sr: SR,
#[doc = "0x08 - Direct Mode Control Register"]
pub dmcr: DMCR,
#[doc = "0x0c - Indirect Mode Control Register"]
pub imcr: IMCR,
#[doc = "0x10 - Direct Mode Interactive Byte Register"]
pub dabr: DABR,
#[doc = "0x14 - Indirect Mode Interactive Byte Register"]
pub iabr: IABR,
#[doc = "0x18 - Indirect Mode Address Register"]
pub iadr: IADR,
#[doc = "0x1c - Indirect Mode Data FIFO Register"]
pub idfr: IDFR,
#[doc = "0x20 - Indirect Mode Data Length Register"]
pub idlr: IDLR,
#[doc = "0x24 - Indirect Mode Wait Count Register"]
pub iwcr: IWCR,
#[doc = "0x28 - Interrupt DMA Enable Register"]
pub ider: IDER,
}
#[doc = "CR (rw) register accessor: an alias for `Reg<CR_SPEC>`"]
pub type CR = crate::Reg<cr::CR_SPEC>;
#[doc = "control register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub struct R(crate::R<CR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR` writer"]
pub struct W(crate::W<CR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `OPMODE` reader - "]
pub type OPMODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OPMODE` writer - "]
pub type OPMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, u8, 2, O>;
#[doc = "Field `SCKMODE` reader - "]
pub type SCKMODE_R = crate::BitReader<bool>;
#[doc = "Field `SCKMODE` writer - "]
pub type SCKMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `XIPMODE` reader - "]
pub type XIPMODE_R = crate::BitReader<bool>;
#[doc = "Field `XIPMODE` writer - "]
pub type XIPMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `CSRHT` reader - "]
pub type CSRHT_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CSRHT` writer - "]
pub type CSRHT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, u8, 3, O>;
#[doc = "Field `SCKDIV` reader - "]
pub type SCKDIV_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SCKDIV` writer - "]
pub type SCKDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, u8, 6, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn opmode(&self) -> OPMODE_R {
OPMODE_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn sckmode(&self) -> SCKMODE_R {
SCKMODE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn xipmode(&self) -> XIPMODE_R {
XIPMODE_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 16:18"]
#[inline(always)]
pub fn csrht(&self) -> CSRHT_R {
CSRHT_R::new(((self.bits >> 16) & 7) as u8)
}
#[doc = "Bits 24:29"]
#[inline(always)]
pub fn sckdiv(&self) -> SCKDIV_R {
SCKDIV_R::new(((self.bits >> 24) & 0x3f) as u8)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn opmode(&mut self) -> OPMODE_W<0> {
OPMODE_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn sckmode(&mut self) -> SCKMODE_W<4> {
SCKMODE_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn xipmode(&mut self) -> XIPMODE_W<5> {
XIPMODE_W::new(self)
}
#[doc = "Bits 16:18"]
#[inline(always)]
#[must_use]
pub fn csrht(&mut self) -> CSRHT_W<16> {
CSRHT_W::new(self)
}
#[doc = "Bits 24:29"]
#[inline(always)]
#[must_use]
pub fn sckdiv(&mut self) -> SCKDIV_W<24> {
SCKDIV_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"]
pub struct CR_SPEC;
impl crate::RegisterSpec for CR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr::R](R) reader structure"]
impl crate::Readable for CR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"]
impl crate::Writable for CR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR to value 0x0307_1b00"]
impl crate::Resettable for CR_SPEC {
const RESET_VALUE: Self::Ux = 0x0307_1b00;
}
}
#[doc = "SR (r) register accessor: an alias for `Reg<SR_SPEC>`"]
pub type SR = crate::Reg<sr::SR_SPEC>;
#[doc = "status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub struct R(crate::R<SR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `CUROP` reader - "]
pub type CUROP_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OPCRCF` reader - "]
pub type OPCRCF_R = crate::BitReader<bool>;
#[doc = "Field `TCF` reader - "]
pub type TCF_R = crate::BitReader<bool>;
#[doc = "Field `BUSY` reader - "]
pub type BUSY_R = crate::BitReader<bool>;
#[doc = "Field `XIPST` reader - "]
pub type XIPST_R = crate::BitReader<bool>;
#[doc = "Field `EMPTY` reader - "]
pub type EMPTY_R = crate::BitReader<bool>;
#[doc = "Field `FULL` reader - "]
pub type FULL_R = crate::BitReader<bool>;
#[doc = "Field `LEVEL` reader - "]
pub type LEVEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DEPTH` reader - "]
pub type DEPTH_R = crate::FieldReader<u8, u8>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn curop(&self) -> CUROP_R {
CUROP_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn opcrcf(&self) -> OPCRCF_R {
OPCRCF_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn tcf(&self) -> TCF_R {
TCF_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn busy(&self) -> BUSY_R {
BUSY_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn xipst(&self) -> XIPST_R {
XIPST_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn empty(&self) -> EMPTY_R {
EMPTY_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn full(&self) -> FULL_R {
FULL_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 12:15"]
#[inline(always)]
pub fn level(&self) -> LEVEL_R {
LEVEL_R::new(((self.bits >> 12) & 0x0f) as u8)
}
#[doc = "Bits 24:27"]
#[inline(always)]
pub fn depth(&self) -> DEPTH_R {
DEPTH_R::new(((self.bits >> 24) & 0x0f) as u8)
}
}
#[doc = "status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"]
pub struct SR_SPEC;
impl crate::RegisterSpec for SR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [sr::R](R) reader structure"]
impl crate::Readable for SR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets SR to value 0x0800_0104"]
impl crate::Resettable for SR_SPEC {
const RESET_VALUE: Self::Ux = 0x0800_0104;
}
}
#[doc = "IDER (rw) register accessor: an alias for `Reg<IDER_SPEC>`"]
pub type IDER = crate::Reg<ider::IDER_SPEC>;
#[doc = "Interrupt DMA Enable Register"]
pub mod ider {
#[doc = "Register `IDER` reader"]
pub struct R(crate::R<IDER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IDER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IDER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IDER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IDER` writer"]
pub struct W(crate::W<IDER_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IDER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IDER_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IDER_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TCFINTEN` reader - "]
pub type TCFINTEN_R = crate::BitReader<bool>;
#[doc = "Field `TCFINTEN` writer - "]
pub type TCFINTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDER_SPEC, bool, O>;
#[doc = "Field `EMPTYINTEN` reader - "]
pub type EMPTYINTEN_R = crate::BitReader<bool>;
#[doc = "Field `EMPTYINTEN` writer - "]
pub type EMPTYINTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDER_SPEC, bool, O>;
#[doc = "Field `FULLINTEN` reader - "]
pub type FULLINTEN_R = crate::BitReader<bool>;
#[doc = "Field `FULLINTEN` writer - "]
pub type FULLINTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDER_SPEC, bool, O>;
#[doc = "Field `TCFDMAEN` reader - "]
pub type TCFDMAEN_R = crate::BitReader<bool>;
#[doc = "Field `TCFDMAEN` writer - "]
pub type TCFDMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDER_SPEC, bool, O>;
#[doc = "Field `EMPTYDMAEN` reader - "]
pub type EMPTYDMAEN_R = crate::BitReader<bool>;
#[doc = "Field `EMPTYDMAEN` writer - "]
pub type EMPTYDMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDER_SPEC, bool, O>;
#[doc = "Field `FULLDMAEN` reader - "]
pub type FULLDMAEN_R = crate::BitReader<bool>;
#[doc = "Field `FULLDMAEN` writer - "]
pub type FULLDMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDER_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn tcfinten(&self) -> TCFINTEN_R {
TCFINTEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn emptyinten(&self) -> EMPTYINTEN_R {
EMPTYINTEN_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn fullinten(&self) -> FULLINTEN_R {
FULLINTEN_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn tcfdmaen(&self) -> TCFDMAEN_R {
TCFDMAEN_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn emptydmaen(&self) -> EMPTYDMAEN_R {
EMPTYDMAEN_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn fulldmaen(&self) -> FULLDMAEN_R {
FULLDMAEN_R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn tcfinten(&mut self) -> TCFINTEN_W<0> {
TCFINTEN_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn emptyinten(&mut self) -> EMPTYINTEN_W<6> {
EMPTYINTEN_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn fullinten(&mut self) -> FULLINTEN_W<7> {
FULLINTEN_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn tcfdmaen(&mut self) -> TCFDMAEN_W<8> {
TCFDMAEN_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn emptydmaen(&mut self) -> EMPTYDMAEN_W<14> {
EMPTYDMAEN_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn fulldmaen(&mut self) -> FULLDMAEN_W<15> {
FULLDMAEN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Interrupt DMA Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ider](index.html) module"]
pub struct IDER_SPEC;
impl crate::RegisterSpec for IDER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ider::R](R) reader structure"]
impl crate::Readable for IDER_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ider::W](W) writer structure"]
impl crate::Writable for IDER_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IDER to value 0"]
impl crate::Resettable for IDER_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMCR (rw) register accessor: an alias for `Reg<DMCR_SPEC>`"]
pub type DMCR = crate::Reg<dmcr::DMCR_SPEC>;
#[doc = "Direct Mode Control Register"]
pub mod dmcr {
#[doc = "Register `DMCR` reader"]
pub struct R(crate::R<DMCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DMCR` writer"]
pub struct W(crate::W<DMCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DMCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DMCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DMCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `INST` reader - "]
pub type INST_R = crate::FieldReader<u8, u8>;
#[doc = "Field `INST` writer - "]
pub type INST_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMCR_SPEC, u8, u8, 8, O>;
#[doc = "Field `IMODE` reader - "]
pub type IMODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IMODE` writer - "]
pub type IMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `ADMODE` reader - "]
pub type ADMODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ADMODE` writer - "]
pub type ADMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `ADSIZE` reader - "]
pub type ADSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ADSIZE` writer - "]
pub type ADSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `ABMODE` reader - "]
pub type ABMODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ABMODE` writer - "]
pub type ABMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `ABSIZE` reader - "]
pub type ABSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ABSIZE` writer - "]
pub type ABSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `DMODE` reader - "]
pub type DMODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DMODE` writer - "]
pub type DMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `DSIZE` reader - "]
pub type DSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DSIZE` writer - "]
pub type DSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `RXDLY` reader - "]
pub type RXDLY_R = crate::FieldReader<u8, u8>;
#[doc = "Field `RXDLY` writer - "]
pub type RXDLY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `NUMDC` reader - "]
pub type NUMDC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `NUMDC` writer - "]
pub type NUMDC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMCR_SPEC, u8, u8, 5, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn inst(&self) -> INST_R {
INST_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn imode(&self) -> IMODE_R {
IMODE_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11"]
#[inline(always)]
pub fn admode(&self) -> ADMODE_R {
ADMODE_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13"]
#[inline(always)]
pub fn adsize(&self) -> ADSIZE_R {
ADSIZE_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn abmode(&self) -> ABMODE_R {
ABMODE_R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:17"]
#[inline(always)]
pub fn absize(&self) -> ABSIZE_R {
ABSIZE_R::new(((self.bits >> 16) & 3) as u8)
}
#[doc = "Bits 18:19"]
#[inline(always)]
pub fn dmode(&self) -> DMODE_R {
DMODE_R::new(((self.bits >> 18) & 3) as u8)
}
#[doc = "Bits 20:21"]
#[inline(always)]
pub fn dsize(&self) -> DSIZE_R {
DSIZE_R::new(((self.bits >> 20) & 3) as u8)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn rxdly(&self) -> RXDLY_R {
RXDLY_R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bits 24:28"]
#[inline(always)]
pub fn numdc(&self) -> NUMDC_R {
NUMDC_R::new(((self.bits >> 24) & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn inst(&mut self) -> INST_W<0> {
INST_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn imode(&mut self) -> IMODE_W<8> {
IMODE_W::new(self)
}
#[doc = "Bits 10:11"]
#[inline(always)]
#[must_use]
pub fn admode(&mut self) -> ADMODE_W<10> {
ADMODE_W::new(self)
}
#[doc = "Bits 12:13"]
#[inline(always)]
#[must_use]
pub fn adsize(&mut self) -> ADSIZE_W<12> {
ADSIZE_W::new(self)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn abmode(&mut self) -> ABMODE_W<14> {
ABMODE_W::new(self)
}
#[doc = "Bits 16:17"]
#[inline(always)]
#[must_use]
pub fn absize(&mut self) -> ABSIZE_W<16> {
ABSIZE_W::new(self)
}
#[doc = "Bits 18:19"]
#[inline(always)]
#[must_use]
pub fn dmode(&mut self) -> DMODE_W<18> {
DMODE_W::new(self)
}
#[doc = "Bits 20:21"]
#[inline(always)]
#[must_use]
pub fn dsize(&mut self) -> DSIZE_W<20> {
DSIZE_W::new(self)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn rxdly(&mut self) -> RXDLY_W<22> {
RXDLY_W::new(self)
}
#[doc = "Bits 24:28"]
#[inline(always)]
#[must_use]
pub fn numdc(&mut self) -> NUMDC_W<24> {
NUMDC_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Direct Mode Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmcr](index.html) module"]
pub struct DMCR_SPEC;
impl crate::RegisterSpec for DMCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dmcr::R](R) reader structure"]
impl crate::Readable for DMCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dmcr::W](W) writer structure"]
impl crate::Writable for DMCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DMCR to value 0x0034_2503"]
impl crate::Resettable for DMCR_SPEC {
const RESET_VALUE: Self::Ux = 0x0034_2503;
}
}
#[doc = "DABR (rw) register accessor: an alias for `Reg<DABR_SPEC>`"]
pub type DABR = crate::Reg<dabr::DABR_SPEC>;
#[doc = "Direct Mode Interactive Byte Register"]
pub mod dabr {
#[doc = "Register `DABR` reader"]
pub struct R(crate::R<DABR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DABR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DABR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DABR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DABR` writer"]
pub struct W(crate::W<DABR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DABR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DABR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DABR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DALT` reader - "]
pub type DALT_R = crate::FieldReader<u32, u32>;
#[doc = "Field `DALT` writer - "]
pub type DALT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DABR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn dalt(&self) -> DALT_R {
DALT_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn dalt(&mut self) -> DALT_W<0> {
DALT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Direct Mode Interactive Byte Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dabr](index.html) module"]
pub struct DABR_SPEC;
impl crate::RegisterSpec for DABR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dabr::R](R) reader structure"]
impl crate::Readable for DABR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dabr::W](W) writer structure"]
impl crate::Writable for DABR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DABR to value 0"]
impl crate::Resettable for DABR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "IMCR (rw) register accessor: an alias for `Reg<IMCR_SPEC>`"]
pub type IMCR = crate::Reg<imcr::IMCR_SPEC>;
#[doc = "Indirect Mode Control Register"]
pub mod imcr {
#[doc = "Register `IMCR` reader"]
pub struct R(crate::R<IMCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IMCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IMCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IMCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IMCR` writer"]
pub struct W(crate::W<IMCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IMCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IMCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IMCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `INST` reader - "]
pub type INST_R = crate::FieldReader<u8, u8>;
#[doc = "Field `INST` writer - "]
pub type INST_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IMCR_SPEC, u8, u8, 8, O>;
#[doc = "Field `IMODE` reader - "]
pub type IMODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IMODE` writer - "]
pub type IMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `ADMODE` reader - "]
pub type ADMODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ADMODE` writer - "]
pub type ADMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `ADSIZE` reader - "]
pub type ADSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ADSIZE` writer - "]
pub type ADSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `ABMODE` reader - "]
pub type ABMODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ABMODE` writer - "]
pub type ABMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `ABSIZE` reader - "]
pub type ABSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ABSIZE` writer - "]
pub type ABSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `DMODE` reader - "]
pub type DMODE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DMODE` writer - "]
pub type DMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `DSIZE` reader - "]
pub type DSIZE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DSIZE` writer - "]
pub type DSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `RXDLY` reader - "]
pub type RXDLY_R = crate::FieldReader<u8, u8>;
#[doc = "Field `RXDLY` writer - "]
pub type RXDLY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `NUMDC` reader - "]
pub type NUMDC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `NUMDC` writer - "]
pub type NUMDC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IMCR_SPEC, u8, u8, 5, O>;
#[doc = "Field `XIPIM` reader - "]
pub type XIPIM_R = crate::BitReader<bool>;
#[doc = "Field `XIPIM` writer - "]
pub type XIPIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMCR_SPEC, bool, O>;
#[doc = "Field `IDMODE` reader - "]
pub type IDMODE_R = crate::BitReader<bool>;
#[doc = "Field `IDMODE` writer - "]
pub type IDMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMCR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn inst(&self) -> INST_R {
INST_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn imode(&self) -> IMODE_R {
IMODE_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11"]
#[inline(always)]
pub fn admode(&self) -> ADMODE_R {
ADMODE_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13"]
#[inline(always)]
pub fn adsize(&self) -> ADSIZE_R {
ADSIZE_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15"]
#[inline(always)]
pub fn abmode(&self) -> ABMODE_R {
ABMODE_R::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:17"]
#[inline(always)]
pub fn absize(&self) -> ABSIZE_R {
ABSIZE_R::new(((self.bits >> 16) & 3) as u8)
}
#[doc = "Bits 18:19"]
#[inline(always)]
pub fn dmode(&self) -> DMODE_R {
DMODE_R::new(((self.bits >> 18) & 3) as u8)
}
#[doc = "Bits 20:21"]
#[inline(always)]
pub fn dsize(&self) -> DSIZE_R {
DSIZE_R::new(((self.bits >> 20) & 3) as u8)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn rxdly(&self) -> RXDLY_R {
RXDLY_R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bits 24:28"]
#[inline(always)]
pub fn numdc(&self) -> NUMDC_R {
NUMDC_R::new(((self.bits >> 24) & 0x1f) as u8)
}
#[doc = "Bit 29"]
#[inline(always)]
pub fn xipim(&self) -> XIPIM_R {
XIPIM_R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn idmode(&self) -> IDMODE_R {
IDMODE_R::new(((self.bits >> 30) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn inst(&mut self) -> INST_W<0> {
INST_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn imode(&mut self) -> IMODE_W<8> {
IMODE_W::new(self)
}
#[doc = "Bits 10:11"]
#[inline(always)]
#[must_use]
pub fn admode(&mut self) -> ADMODE_W<10> {
ADMODE_W::new(self)
}
#[doc = "Bits 12:13"]
#[inline(always)]
#[must_use]
pub fn adsize(&mut self) -> ADSIZE_W<12> {
ADSIZE_W::new(self)
}
#[doc = "Bits 14:15"]
#[inline(always)]
#[must_use]
pub fn abmode(&mut self) -> ABMODE_W<14> {
ABMODE_W::new(self)
}
#[doc = "Bits 16:17"]
#[inline(always)]
#[must_use]
pub fn absize(&mut self) -> ABSIZE_W<16> {
ABSIZE_W::new(self)
}
#[doc = "Bits 18:19"]
#[inline(always)]
#[must_use]
pub fn dmode(&mut self) -> DMODE_W<18> {
DMODE_W::new(self)
}
#[doc = "Bits 20:21"]
#[inline(always)]
#[must_use]
pub fn dsize(&mut self) -> DSIZE_W<20> {
DSIZE_W::new(self)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn rxdly(&mut self) -> RXDLY_W<22> {
RXDLY_W::new(self)
}
#[doc = "Bits 24:28"]
#[inline(always)]
#[must_use]
pub fn numdc(&mut self) -> NUMDC_W<24> {
NUMDC_W::new(self)
}
#[doc = "Bit 29"]
#[inline(always)]
#[must_use]
pub fn xipim(&mut self) -> XIPIM_W<29> {
XIPIM_W::new(self)
}
#[doc = "Bit 30"]
#[inline(always)]
#[must_use]
pub fn idmode(&mut self) -> IDMODE_W<30> {
IDMODE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Indirect Mode Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imcr](index.html) module"]
pub struct IMCR_SPEC;
impl crate::RegisterSpec for IMCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [imcr::R](R) reader structure"]
impl crate::Readable for IMCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [imcr::W](W) writer structure"]
impl crate::Writable for IMCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IMCR to value 0x0034_2500"]
impl crate::Resettable for IMCR_SPEC {
const RESET_VALUE: Self::Ux = 0x0034_2500;
}
}
#[doc = "IABR (rw) register accessor: an alias for `Reg<IABR_SPEC>`"]
pub type IABR = crate::Reg<iabr::IABR_SPEC>;
#[doc = "Indirect Mode Interactive Byte Register"]
pub mod iabr {
#[doc = "Register `IABR` reader"]
pub struct R(crate::R<IABR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IABR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IABR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IABR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IABR` writer"]
pub struct W(crate::W<IABR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IABR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IABR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IABR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `IALT` reader - "]
pub type IALT_R = crate::FieldReader<u32, u32>;
#[doc = "Field `IALT` writer - "]
pub type IALT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IABR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn ialt(&self) -> IALT_R {
IALT_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn ialt(&mut self) -> IALT_W<0> {
IALT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Indirect Mode Interactive Byte Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iabr](index.html) module"]
pub struct IABR_SPEC;
impl crate::RegisterSpec for IABR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [iabr::R](R) reader structure"]
impl crate::Readable for IABR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [iabr::W](W) writer structure"]
impl crate::Writable for IABR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IABR to value 0"]
impl crate::Resettable for IABR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "IADR (rw) register accessor: an alias for `Reg<IADR_SPEC>`"]
pub type IADR = crate::Reg<iadr::IADR_SPEC>;
#[doc = "Indirect Mode Address Register"]
pub mod iadr {
#[doc = "Register `IADR` reader"]
pub struct R(crate::R<IADR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IADR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IADR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IADR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IADR` writer"]
pub struct W(crate::W<IADR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IADR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IADR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IADR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `IADDR` reader - "]
pub type IADDR_R = crate::FieldReader<u32, u32>;
#[doc = "Field `IADDR` writer - "]
pub type IADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IADR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn iaddr(&self) -> IADDR_R {
IADDR_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn iaddr(&mut self) -> IADDR_W<0> {
IADDR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Indirect Mode Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iadr](index.html) module"]
pub struct IADR_SPEC;
impl crate::RegisterSpec for IADR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [iadr::R](R) reader structure"]
impl crate::Readable for IADR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [iadr::W](W) writer structure"]
impl crate::Writable for IADR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IADR to value 0"]
impl crate::Resettable for IADR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "IDFR (rw) register accessor: an alias for `Reg<IDFR_SPEC>`"]
pub type IDFR = crate::Reg<idfr::IDFR_SPEC>;
#[doc = "Indirect Mode Data FIFO Register"]
pub mod idfr {
#[doc = "Register `IDFR` reader"]
pub struct R(crate::R<IDFR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IDFR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IDFR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IDFR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IDFR` writer"]
pub struct W(crate::W<IDFR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IDFR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IDFR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IDFR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `IDATA` reader - "]
pub type IDATA_R = crate::FieldReader<u32, u32>;
#[doc = "Field `IDATA` writer - "]
pub type IDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IDFR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn idata(&self) -> IDATA_R {
IDATA_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn idata(&mut self) -> IDATA_W<0> {
IDATA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Indirect Mode Data FIFO Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idfr](index.html) module"]
pub struct IDFR_SPEC;
impl crate::RegisterSpec for IDFR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [idfr::R](R) reader structure"]
impl crate::Readable for IDFR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [idfr::W](W) writer structure"]
impl crate::Writable for IDFR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IDFR to value 0"]
impl crate::Resettable for IDFR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "IDLR (rw) register accessor: an alias for `Reg<IDLR_SPEC>`"]
pub type IDLR = crate::Reg<idlr::IDLR_SPEC>;
#[doc = "Indirect Mode Data Length Register"]
pub mod idlr {
#[doc = "Register `IDLR` reader"]
pub struct R(crate::R<IDLR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IDLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IDLR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IDLR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IDLR` writer"]
pub struct W(crate::W<IDLR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IDLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IDLR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IDLR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `IDLEN` reader - "]
pub type IDLEN_R = crate::FieldReader<u32, u32>;
#[doc = "Field `IDLEN` writer - "]
pub type IDLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IDLR_SPEC, u32, u32, 20, O>;
impl R {
#[doc = "Bits 0:19"]
#[inline(always)]
pub fn idlen(&self) -> IDLEN_R {
IDLEN_R::new(self.bits & 0x000f_ffff)
}
}
impl W {
#[doc = "Bits 0:19"]
#[inline(always)]
#[must_use]
pub fn idlen(&mut self) -> IDLEN_W<0> {
IDLEN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Indirect Mode Data Length Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idlr](index.html) module"]
pub struct IDLR_SPEC;
impl crate::RegisterSpec for IDLR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [idlr::R](R) reader structure"]
impl crate::Readable for IDLR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [idlr::W](W) writer structure"]
impl crate::Writable for IDLR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IDLR to value 0"]
impl crate::Resettable for IDLR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "IWCR (rw) register accessor: an alias for `Reg<IWCR_SPEC>`"]
pub type IWCR = crate::Reg<iwcr::IWCR_SPEC>;
#[doc = "Indirect Mode Wait Count Register"]
pub mod iwcr {
#[doc = "Register `IWCR` reader"]
pub struct R(crate::R<IWCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IWCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IWCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IWCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IWCR` writer"]
pub struct W(crate::W<IWCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IWCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IWCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IWCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `IWCNT` reader - "]
pub type IWCNT_R = crate::FieldReader<u32, u32>;
#[doc = "Field `IWCNT` writer - "]
pub type IWCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IWCR_SPEC, u32, u32, 30, O>;
impl R {
#[doc = "Bits 0:29"]
#[inline(always)]
pub fn iwcnt(&self) -> IWCNT_R {
IWCNT_R::new(self.bits & 0x3fff_ffff)
}
}
impl W {
#[doc = "Bits 0:29"]
#[inline(always)]
#[must_use]
pub fn iwcnt(&mut self) -> IWCNT_W<0> {
IWCNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Indirect Mode Wait Count Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iwcr](index.html) module"]
pub struct IWCR_SPEC;
impl crate::RegisterSpec for IWCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [iwcr::R](R) reader structure"]
impl crate::Readable for IWCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [iwcr::W](W) writer structure"]
impl crate::Writable for IWCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IWCR to value 0"]
impl crate::Resettable for IWCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "RCC"]
pub struct RCC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for RCC {}
impl RCC {
#[doc = r"Pointer to the register block"]
pub const PTR: *const rcc::RegisterBlock = 0x4002_1000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const rcc::RegisterBlock {
Self::PTR
}
}
impl Deref for RCC {
type Target = rcc::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for RCC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RCC").finish()
}
}
#[doc = "RCC"]
pub mod rcc {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - clock control register"]
pub cr: CR,
#[doc = "0x04 - Clock Configuration Register"]
pub cfgr: CFGR,
#[doc = "0x08 - clock interrupt register"]
pub cir: CIR,
_reserved3: [u8; 0x08],
#[doc = "0x14 - AHB1 Peripheral Reset Register"]
pub ahb1rstr: AHB1RSTR,
#[doc = "0x18 - APB2 Peripheral Reset Register"]
pub apb2rstr: APB2RSTR,
#[doc = "0x1c - APB1 Peripheral Reset Register"]
pub apb1rstr: APB1RSTR,
_reserved6: [u8; 0x08],
#[doc = "0x28 - AHB1 peripheral clock enable register"]
pub ahb1enr: AHB1ENR,
#[doc = "0x2c - APB2 Peripheral Clock Enable Register"]
pub apb2enr: APB2ENR,
#[doc = "0x30 - APB1 Peripheral Clock Enable Register"]
pub apb1enr: APB1ENR,
#[doc = "0x34 - Backup Domain Control Register"]
pub bdcr: BDCR,
#[doc = "0x38 - Control Status Register"]
pub csr: CSR,
#[doc = "0x3c - System Configuration Register"]
pub syscfg: SYSCFG,
#[doc = "0x40 - Clock Configuration Register 2"]
pub cfgr2: CFGR2,
_reserved13: [u8; 0x04],
#[doc = "0x48 - PLL1 Configuration Register"]
pub pll1cfgr: PLL1CFGR,
#[doc = "0x4c - PLL2 Configuration Register"]
pub pll2cfgr: PLL2CFGR,
_reserved15: [u8; 0x10],
#[doc = "0x60 - ADC1 Configuration Register"]
pub adc1cfgr: ADC1CFGR,
#[doc = "0x64 - ADC2 Configuration Register"]
pub adc2cfgr: ADC2CFGR,
_reserved17: [u8; 0x08],
#[doc = "0x70 - DAC Configuration Register"]
pub daccfgr: DACCFGR,
_reserved18: [u8; 0x04],
#[doc = "0x78 - FSMC Configuration Register"]
pub fsmccfgr: FSMCCFGR,
#[doc = "0x7c - TPIU configuration register"]
pub tpiucfgr: TPIUCFGR,
}
#[doc = "CR (rw) register accessor: an alias for `Reg<CR_SPEC>`"]
pub type CR = crate::Reg<cr::CR_SPEC>;
#[doc = "clock control register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub struct R(crate::R<CR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR` writer"]
pub struct W(crate::W<CR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `HSION` reader - "]
pub type HSION_R = crate::BitReader<bool>;
#[doc = "Field `HSION` writer - "]
pub type HSION_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `HSIRDY` reader - "]
pub type HSIRDY_R = crate::BitReader<bool>;
#[doc = "Field `HSE_LPF_BYP` reader - "]
pub type HSE_LPF_BYP_R = crate::BitReader<bool>;
#[doc = "Field `HSE_LPF_BYP` writer - "]
pub type HSE_LPF_BYP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `HSE_LPF_SEL` reader - "]
pub type HSE_LPF_SEL_R = crate::BitReader<bool>;
#[doc = "Field `HSE_LPF_SEL` writer - "]
pub type HSE_LPF_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `HSE_DEGLITCH_BYP` reader - "]
pub type HSE_DEGLITCH_BYP_R = crate::BitReader<bool>;
#[doc = "Field `HSE_DEGLITCH_BYP` writer - "]
pub type HSE_DEGLITCH_BYP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `HSE_DEGLITCH_SEL` reader - "]
pub type HSE_DEGLITCH_SEL_R = crate::BitReader<bool>;
#[doc = "Field `HSE_DEGLITCH_SEL` writer - "]
pub type HSE_DEGLITCH_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `HSE_OUTPUTSEL` reader - "]
pub type HSE_OUTPUTSEL_R = crate::BitReader<bool>;
#[doc = "Field `HSE_OUTPUTSEL` writer - "]
pub type HSE_OUTPUTSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `HSE_DR` reader - "]
pub type HSE_DR_R = crate::FieldReader<u8, u8>;
#[doc = "Field `HSE_DR` writer - "]
pub type HSE_DR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, u8, 2, O>;
#[doc = "Field `HSIDIV` reader - "]
pub type HSIDIV_R = crate::FieldReader<u8, u8>;
#[doc = "Field `HSIDIV` writer - "]
pub type HSIDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, u8, 3, O>;
#[doc = "Field `HSEON` reader - "]
pub type HSEON_R = crate::BitReader<bool>;
#[doc = "Field `HSEON` writer - "]
pub type HSEON_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `HSERDY` reader - "]
pub type HSERDY_R = crate::BitReader<bool>;
#[doc = "Field `HSEBYP` reader - "]
pub type HSEBYP_R = crate::BitReader<bool>;
#[doc = "Field `HSEBYP` writer - "]
pub type HSEBYP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `CSSON` reader - "]
pub type CSSON_R = crate::BitReader<bool>;
#[doc = "Field `CSSON` writer - "]
pub type CSSON_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `HSE_AACSEL` reader - "]
pub type HSE_AACSEL_R = crate::BitReader<bool>;
#[doc = "Field `HSE_AACSEL` writer - "]
pub type HSE_AACSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `HSE_IB` reader - "]
pub type HSE_IB_R = crate::FieldReader<u8, u8>;
#[doc = "Field `HSE_IB` writer - "]
pub type HSE_IB_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, u8, 2, O>;
#[doc = "Field `PLL1ON` reader - "]
pub type PLL1ON_R = crate::BitReader<bool>;
#[doc = "Field `PLL1ON` writer - "]
pub type PLL1ON_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `PLL1RDY` reader - "]
pub type PLL1RDY_R = crate::BitReader<bool>;
#[doc = "Field `PLL2ON` reader - "]
pub type PLL2ON_R = crate::BitReader<bool>;
#[doc = "Field `PLL2ON` writer - "]
pub type PLL2ON_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
#[doc = "Field `PLL2RDY` reader - "]
pub type PLL2RDY_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn hsion(&self) -> HSION_R {
HSION_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn hsirdy(&self) -> HSIRDY_R {
HSIRDY_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn hse_lpf_byp(&self) -> HSE_LPF_BYP_R {
HSE_LPF_BYP_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn hse_lpf_sel(&self) -> HSE_LPF_SEL_R {
HSE_LPF_SEL_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn hse_deglitch_byp(&self) -> HSE_DEGLITCH_BYP_R {
HSE_DEGLITCH_BYP_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn hse_deglitch_sel(&self) -> HSE_DEGLITCH_SEL_R {
HSE_DEGLITCH_SEL_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn hse_outputsel(&self) -> HSE_OUTPUTSEL_R {
HSE_OUTPUTSEL_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:10"]
#[inline(always)]
pub fn hse_dr(&self) -> HSE_DR_R {
HSE_DR_R::new(((self.bits >> 9) & 3) as u8)
}
#[doc = "Bits 11:13"]
#[inline(always)]
pub fn hsidiv(&self) -> HSIDIV_R {
HSIDIV_R::new(((self.bits >> 11) & 7) as u8)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn hseon(&self) -> HSEON_R {
HSEON_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn hserdy(&self) -> HSERDY_R {
HSERDY_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn hsebyp(&self) -> HSEBYP_R {
HSEBYP_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn csson(&self) -> CSSON_R {
CSSON_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn hse_aacsel(&self) -> HSE_AACSEL_R {
HSE_AACSEL_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn hse_ib(&self) -> HSE_IB_R {
HSE_IB_R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn pll1on(&self) -> PLL1ON_R {
PLL1ON_R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn pll1rdy(&self) -> PLL1RDY_R {
PLL1RDY_R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn pll2on(&self) -> PLL2ON_R {
PLL2ON_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29"]
#[inline(always)]
pub fn pll2rdy(&self) -> PLL2RDY_R {
PLL2RDY_R::new(((self.bits >> 29) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn hsion(&mut self) -> HSION_W<0> {
HSION_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn hse_lpf_byp(&mut self) -> HSE_LPF_BYP_W<4> {
HSE_LPF_BYP_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn hse_lpf_sel(&mut self) -> HSE_LPF_SEL_W<5> {
HSE_LPF_SEL_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn hse_deglitch_byp(&mut self) -> HSE_DEGLITCH_BYP_W<6> {
HSE_DEGLITCH_BYP_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn hse_deglitch_sel(&mut self) -> HSE_DEGLITCH_SEL_W<7> {
HSE_DEGLITCH_SEL_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn hse_outputsel(&mut self) -> HSE_OUTPUTSEL_W<8> {
HSE_OUTPUTSEL_W::new(self)
}
#[doc = "Bits 9:10"]
#[inline(always)]
#[must_use]
pub fn hse_dr(&mut self) -> HSE_DR_W<9> {
HSE_DR_W::new(self)
}
#[doc = "Bits 11:13"]
#[inline(always)]
#[must_use]
pub fn hsidiv(&mut self) -> HSIDIV_W<11> {
HSIDIV_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn hseon(&mut self) -> HSEON_W<16> {
HSEON_W::new(self)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn hsebyp(&mut self) -> HSEBYP_W<18> {
HSEBYP_W::new(self)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn csson(&mut self) -> CSSON_W<19> {
CSSON_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn hse_aacsel(&mut self) -> HSE_AACSEL_W<21> {
HSE_AACSEL_W::new(self)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn hse_ib(&mut self) -> HSE_IB_W<22> {
HSE_IB_W::new(self)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn pll1on(&mut self) -> PLL1ON_W<24> {
PLL1ON_W::new(self)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn pll2on(&mut self) -> PLL2ON_W<28> {
PLL2ON_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "clock control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"]
pub struct CR_SPEC;
impl crate::RegisterSpec for CR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr::R](R) reader structure"]
impl crate::Readable for CR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"]
impl crate::Writable for CR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR to value 0x0040_0221"]
impl crate::Resettable for CR_SPEC {
const RESET_VALUE: Self::Ux = 0x0040_0221;
}
}
#[doc = "CFGR (rw) register accessor: an alias for `Reg<CFGR_SPEC>`"]
pub type CFGR = crate::Reg<cfgr::CFGR_SPEC>;
#[doc = "Clock Configuration Register"]
pub mod cfgr {
#[doc = "Register `CFGR` reader"]
pub struct R(crate::R<CFGR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CFGR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CFGR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CFGR` writer"]
pub struct W(crate::W<CFGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CFGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CFGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SW` reader - "]
pub type SW_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SW` writer - "]
pub type SW_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR_SPEC, u8, u8, 2, O>;
#[doc = "Field `SWS` reader - "]
pub type SWS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `HPRE` reader - "]
pub type HPRE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `HPRE` writer - "]
pub type HPRE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR_SPEC, u8, u8, 4, O>;
#[doc = "Field `PPRE1` reader - "]
pub type PPRE1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PPRE1` writer - "]
pub type PPRE1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR_SPEC, u8, u8, 3, O>;
#[doc = "Field `PPRE2` reader - "]
pub type PPRE2_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PPRE2` writer - "]
pub type PPRE2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR_SPEC, u8, u8, 3, O>;
#[doc = "Field `ADC1CLKSEL` reader - "]
pub type ADC1CLKSEL_R = crate::BitReader<bool>;
#[doc = "Field `ADC1CLKSEL` writer - "]
pub type ADC1CLKSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR_SPEC, bool, O>;
#[doc = "Field `ADC2CLKSEL` reader - "]
pub type ADC2CLKSEL_R = crate::BitReader<bool>;
#[doc = "Field `ADC2CLKSEL` writer - "]
pub type ADC2CLKSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR_SPEC, bool, O>;
#[doc = "Field `USBCLKSEL` reader - "]
pub type USBCLKSEL_R = crate::BitReader<bool>;
#[doc = "Field `USBCLKSEL` writer - "]
pub type USBCLKSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR_SPEC, bool, O>;
#[doc = "Field `USBPRE` reader - "]
pub type USBPRE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `USBPRE` writer - "]
pub type USBPRE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR_SPEC, u8, u8, 2, O>;
#[doc = "Field `MCO` reader - "]
pub type MCO_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MCO` writer - "]
pub type MCO_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR_SPEC, u8, u8, 4, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn sw(&self) -> SW_R {
SW_R::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3"]
#[inline(always)]
pub fn sws(&self) -> SWS_R {
SWS_R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn hpre(&self) -> HPRE_R {
HPRE_R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:10"]
#[inline(always)]
pub fn ppre1(&self) -> PPRE1_R {
PPRE1_R::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bits 11:13"]
#[inline(always)]
pub fn ppre2(&self) -> PPRE2_R {
PPRE2_R::new(((self.bits >> 11) & 7) as u8)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn adc1clksel(&self) -> ADC1CLKSEL_R {
ADC1CLKSEL_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn adc2clksel(&self) -> ADC2CLKSEL_R {
ADC2CLKSEL_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn usbclksel(&self) -> USBCLKSEL_R {
USBCLKSEL_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bits 22:23"]
#[inline(always)]
pub fn usbpre(&self) -> USBPRE_R {
USBPRE_R::new(((self.bits >> 22) & 3) as u8)
}
#[doc = "Bits 24:27"]
#[inline(always)]
pub fn mco(&self) -> MCO_R {
MCO_R::new(((self.bits >> 24) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn sw(&mut self) -> SW_W<0> {
SW_W::new(self)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn hpre(&mut self) -> HPRE_W<4> {
HPRE_W::new(self)
}
#[doc = "Bits 8:10"]
#[inline(always)]
#[must_use]
pub fn ppre1(&mut self) -> PPRE1_W<8> {
PPRE1_W::new(self)
}
#[doc = "Bits 11:13"]
#[inline(always)]
#[must_use]
pub fn ppre2(&mut self) -> PPRE2_W<11> {
PPRE2_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn adc1clksel(&mut self) -> ADC1CLKSEL_W<16> {
ADC1CLKSEL_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn adc2clksel(&mut self) -> ADC2CLKSEL_W<17> {
ADC2CLKSEL_W::new(self)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn usbclksel(&mut self) -> USBCLKSEL_W<19> {
USBCLKSEL_W::new(self)
}
#[doc = "Bits 22:23"]
#[inline(always)]
#[must_use]
pub fn usbpre(&mut self) -> USBPRE_W<22> {
USBPRE_W::new(self)
}
#[doc = "Bits 24:27"]
#[inline(always)]
#[must_use]
pub fn mco(&mut self) -> MCO_W<24> {
MCO_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Clock Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr](index.html) module"]
pub struct CFGR_SPEC;
impl crate::RegisterSpec for CFGR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cfgr::R](R) reader structure"]
impl crate::Readable for CFGR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfgr::W](W) writer structure"]
impl crate::Writable for CFGR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CFGR to value 0"]
impl crate::Resettable for CFGR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CIR (rw) register accessor: an alias for `Reg<CIR_SPEC>`"]
pub type CIR = crate::Reg<cir::CIR_SPEC>;
#[doc = "clock interrupt register"]
pub mod cir {
#[doc = "Register `CIR` reader"]
pub struct R(crate::R<CIR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CIR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CIR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CIR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CIR` writer"]
pub struct W(crate::W<CIR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CIR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CIR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CIR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `LSIRDYF` reader - "]
pub type LSIRDYF_R = crate::BitReader<bool>;
#[doc = "Field `LSERDYF` reader - "]
pub type LSERDYF_R = crate::BitReader<bool>;
#[doc = "Field `HSIRDYF` reader - "]
pub type HSIRDYF_R = crate::BitReader<bool>;
#[doc = "Field `HSERDYF` reader - "]
pub type HSERDYF_R = crate::BitReader<bool>;
#[doc = "Field `PLL1RDYF` reader - "]
pub type PLL1RDYF_R = crate::BitReader<bool>;
#[doc = "Field `PLL2RDYF` reader - "]
pub type PLL2RDYF_R = crate::BitReader<bool>;
#[doc = "Field `CSSF` reader - "]
pub type CSSF_R = crate::BitReader<bool>;
#[doc = "Field `LSIRDYIE` reader - "]
pub type LSIRDYIE_R = crate::BitReader<bool>;
#[doc = "Field `LSIRDYIE` writer - "]
pub type LSIRDYIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CIR_SPEC, bool, O>;
#[doc = "Field `LSERDYIE` reader - "]
pub type LSERDYIE_R = crate::BitReader<bool>;
#[doc = "Field `LSERDYIE` writer - "]
pub type LSERDYIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CIR_SPEC, bool, O>;
#[doc = "Field `HSIRDYIE` reader - "]
pub type HSIRDYIE_R = crate::BitReader<bool>;
#[doc = "Field `HSIRDYIE` writer - "]
pub type HSIRDYIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CIR_SPEC, bool, O>;
#[doc = "Field `HSERDYIE` reader - "]
pub type HSERDYIE_R = crate::BitReader<bool>;
#[doc = "Field `HSERDYIE` writer - "]
pub type HSERDYIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CIR_SPEC, bool, O>;
#[doc = "Field `PLL1RDYIE` reader - "]
pub type PLL1RDYIE_R = crate::BitReader<bool>;
#[doc = "Field `PLL1RDYIE` writer - "]
pub type PLL1RDYIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CIR_SPEC, bool, O>;
#[doc = "Field `PLL2RDYIE` reader - "]
pub type PLL2RDYIE_R = crate::BitReader<bool>;
#[doc = "Field `PLL2RDYIE` writer - "]
pub type PLL2RDYIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CIR_SPEC, bool, O>;
#[doc = "Field `LSIRDYC` reader - "]
pub type LSIRDYC_R = crate::BitReader<bool>;
#[doc = "Field `LSIRDYC` writer - "]
pub type LSIRDYC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CIR_SPEC, bool, O>;
#[doc = "Field `LSERDYC` reader - "]
pub type LSERDYC_R = crate::BitReader<bool>;
#[doc = "Field `LSERDYC` writer - "]
pub type LSERDYC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CIR_SPEC, bool, O>;
#[doc = "Field `HSIRDYC` reader - "]
pub type HSIRDYC_R = crate::BitReader<bool>;
#[doc = "Field `HSIRDYC` writer - "]
pub type HSIRDYC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CIR_SPEC, bool, O>;
#[doc = "Field `HSERDYC` reader - "]
pub type HSERDYC_R = crate::BitReader<bool>;
#[doc = "Field `HSERDYC` writer - "]
pub type HSERDYC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CIR_SPEC, bool, O>;
#[doc = "Field `PLL1RDYC` reader - "]
pub type PLL1RDYC_R = crate::BitReader<bool>;
#[doc = "Field `PLL1RDYC` writer - "]
pub type PLL1RDYC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CIR_SPEC, bool, O>;
#[doc = "Field `PLL2RDYC` reader - "]
pub type PLL2RDYC_R = crate::BitReader<bool>;
#[doc = "Field `PLL2RDYC` writer - "]
pub type PLL2RDYC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CIR_SPEC, bool, O>;
#[doc = "Field `CSSC` reader - "]
pub type CSSC_R = crate::BitReader<bool>;
#[doc = "Field `CSSC` writer - "]
pub type CSSC_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, CIR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn lsirdyf(&self) -> LSIRDYF_R {
LSIRDYF_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn lserdyf(&self) -> LSERDYF_R {
LSERDYF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn hsirdyf(&self) -> HSIRDYF_R {
HSIRDYF_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn hserdyf(&self) -> HSERDYF_R {
HSERDYF_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn pll1rdyf(&self) -> PLL1RDYF_R {
PLL1RDYF_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn pll2rdyf(&self) -> PLL2RDYF_R {
PLL2RDYF_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn cssf(&self) -> CSSF_R {
CSSF_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn lsirdyie(&self) -> LSIRDYIE_R {
LSIRDYIE_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn lserdyie(&self) -> LSERDYIE_R {
LSERDYIE_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn hsirdyie(&self) -> HSIRDYIE_R {
HSIRDYIE_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn hserdyie(&self) -> HSERDYIE_R {
HSERDYIE_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn pll1rdyie(&self) -> PLL1RDYIE_R {
PLL1RDYIE_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn pll2rdyie(&self) -> PLL2RDYIE_R {
PLL2RDYIE_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn lsirdyc(&self) -> LSIRDYC_R {
LSIRDYC_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn lserdyc(&self) -> LSERDYC_R {
LSERDYC_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn hsirdyc(&self) -> HSIRDYC_R {
HSIRDYC_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn hserdyc(&self) -> HSERDYC_R {
HSERDYC_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn pll1rdyc(&self) -> PLL1RDYC_R {
PLL1RDYC_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn pll2rdyc(&self) -> PLL2RDYC_R {
PLL2RDYC_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 23"]
#[inline(always)]
pub fn cssc(&self) -> CSSC_R {
CSSC_R::new(((self.bits >> 23) & 1) != 0)
}
}
impl W {
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn lsirdyie(&mut self) -> LSIRDYIE_W<8> {
LSIRDYIE_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn lserdyie(&mut self) -> LSERDYIE_W<9> {
LSERDYIE_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn hsirdyie(&mut self) -> HSIRDYIE_W<10> {
HSIRDYIE_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn hserdyie(&mut self) -> HSERDYIE_W<11> {
HSERDYIE_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn pll1rdyie(&mut self) -> PLL1RDYIE_W<12> {
PLL1RDYIE_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn pll2rdyie(&mut self) -> PLL2RDYIE_W<13> {
PLL2RDYIE_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn lsirdyc(&mut self) -> LSIRDYC_W<16> {
LSIRDYC_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn lserdyc(&mut self) -> LSERDYC_W<17> {
LSERDYC_W::new(self)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn hsirdyc(&mut self) -> HSIRDYC_W<18> {
HSIRDYC_W::new(self)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn hserdyc(&mut self) -> HSERDYC_W<19> {
HSERDYC_W::new(self)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn pll1rdyc(&mut self) -> PLL1RDYC_W<20> {
PLL1RDYC_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn pll2rdyc(&mut self) -> PLL2RDYC_W<21> {
PLL2RDYC_W::new(self)
}
#[doc = "Bit 23"]
#[inline(always)]
#[must_use]
pub fn cssc(&mut self) -> CSSC_W<23> {
CSSC_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "clock interrupt register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cir](index.html) module"]
pub struct CIR_SPEC;
impl crate::RegisterSpec for CIR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cir::R](R) reader structure"]
impl crate::Readable for CIR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cir::W](W) writer structure"]
impl crate::Writable for CIR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x00bf_0000;
}
#[doc = "`reset()` method sets CIR to value 0"]
impl crate::Resettable for CIR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "AHB1RSTR (rw) register accessor: an alias for `Reg<AHB1RSTR_SPEC>`"]
pub type AHB1RSTR = crate::Reg<ahb1rstr::AHB1RSTR_SPEC>;
#[doc = "AHB1 Peripheral Reset Register"]
pub mod ahb1rstr {
#[doc = "Register `AHB1RSTR` reader"]
pub struct R(crate::R<AHB1RSTR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<AHB1RSTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<AHB1RSTR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<AHB1RSTR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `AHB1RSTR` writer"]
pub struct W(crate::W<AHB1RSTR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<AHB1RSTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<AHB1RSTR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<AHB1RSTR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `GPIOA` reader - "]
pub type GPIOA_R = crate::BitReader<bool>;
#[doc = "Field `GPIOA` writer - "]
pub type GPIOA_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1RSTR_SPEC, bool, O>;
#[doc = "Field `GPIOB` reader - "]
pub type GPIOB_R = crate::BitReader<bool>;
#[doc = "Field `GPIOB` writer - "]
pub type GPIOB_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1RSTR_SPEC, bool, O>;
#[doc = "Field `GPIOC` reader - "]
pub type GPIOC_R = crate::BitReader<bool>;
#[doc = "Field `GPIOC` writer - "]
pub type GPIOC_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1RSTR_SPEC, bool, O>;
#[doc = "Field `GPIOD` reader - "]
pub type GPIOD_R = crate::BitReader<bool>;
#[doc = "Field `GPIOD` writer - "]
pub type GPIOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1RSTR_SPEC, bool, O>;
#[doc = "Field `GPIOE` reader - "]
pub type GPIOE_R = crate::BitReader<bool>;
#[doc = "Field `GPIOE` writer - "]
pub type GPIOE_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1RSTR_SPEC, bool, O>;
#[doc = "Field `GPIOF` reader - "]
pub type GPIOF_R = crate::BitReader<bool>;
#[doc = "Field `GPIOF` writer - "]
pub type GPIOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1RSTR_SPEC, bool, O>;
#[doc = "Field `GPIOG` reader - "]
pub type GPIOG_R = crate::BitReader<bool>;
#[doc = "Field `GPIOG` writer - "]
pub type GPIOG_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1RSTR_SPEC, bool, O>;
#[doc = "Field `GPIOH` reader - "]
pub type GPIOH_R = crate::BitReader<bool>;
#[doc = "Field `GPIOH` writer - "]
pub type GPIOH_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1RSTR_SPEC, bool, O>;
#[doc = "Field `GPIOI` reader - "]
pub type GPIOI_R = crate::BitReader<bool>;
#[doc = "Field `GPIOI` writer - "]
pub type GPIOI_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1RSTR_SPEC, bool, O>;
#[doc = "Field `CRC` reader - "]
pub type CRC_R = crate::BitReader<bool>;
#[doc = "Field `CRC` writer - "]
pub type CRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1RSTR_SPEC, bool, O>;
#[doc = "Field `CORDIC` reader - "]
pub type CORDIC_R = crate::BitReader<bool>;
#[doc = "Field `CORDIC` writer - "]
pub type CORDIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1RSTR_SPEC, bool, O>;
#[doc = "Field `ENET` reader - "]
pub type ENET_R = crate::BitReader<bool>;
#[doc = "Field `ENET` writer - "]
pub type ENET_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1RSTR_SPEC, bool, O>;
#[doc = "Field `DMA1` reader - "]
pub type DMA1_R = crate::BitReader<bool>;
#[doc = "Field `DMA1` writer - "]
pub type DMA1_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1RSTR_SPEC, bool, O>;
#[doc = "Field `DMA2` reader - "]
pub type DMA2_R = crate::BitReader<bool>;
#[doc = "Field `DMA2` writer - "]
pub type DMA2_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1RSTR_SPEC, bool, O>;
#[doc = "Field `USBFS` reader - "]
pub type USBFS_R = crate::BitReader<bool>;
#[doc = "Field `USBFS` writer - "]
pub type USBFS_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1RSTR_SPEC, bool, O>;
#[doc = "Field `FSMC` reader - "]
pub type FSMC_R = crate::BitReader<bool>;
#[doc = "Field `FSMC` writer - "]
pub type FSMC_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1RSTR_SPEC, bool, O>;
#[doc = "Field `QSPI` reader - "]
pub type QSPI_R = crate::BitReader<bool>;
#[doc = "Field `QSPI` writer - "]
pub type QSPI_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1RSTR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn gpioa(&self) -> GPIOA_R {
GPIOA_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn gpiob(&self) -> GPIOB_R {
GPIOB_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn gpioc(&self) -> GPIOC_R {
GPIOC_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn gpiod(&self) -> GPIOD_R {
GPIOD_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn gpioe(&self) -> GPIOE_R {
GPIOE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn gpiof(&self) -> GPIOF_R {
GPIOF_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn gpiog(&self) -> GPIOG_R {
GPIOG_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn gpioh(&self) -> GPIOH_R {
GPIOH_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn gpioi(&self) -> GPIOI_R {
GPIOI_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn crc(&self) -> CRC_R {
CRC_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn cordic(&self) -> CORDIC_R {
CORDIC_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn enet(&self) -> ENET_R {
ENET_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn dma1(&self) -> DMA1_R {
DMA1_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn dma2(&self) -> DMA2_R {
DMA2_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn usbfs(&self) -> USBFS_R {
USBFS_R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn fsmc(&self) -> FSMC_R {
FSMC_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn qspi(&self) -> QSPI_R {
QSPI_R::new(((self.bits >> 30) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn gpioa(&mut self) -> GPIOA_W<0> {
GPIOA_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn gpiob(&mut self) -> GPIOB_W<1> {
GPIOB_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn gpioc(&mut self) -> GPIOC_W<2> {
GPIOC_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn gpiod(&mut self) -> GPIOD_W<3> {
GPIOD_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn gpioe(&mut self) -> GPIOE_W<4> {
GPIOE_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn gpiof(&mut self) -> GPIOF_W<5> {
GPIOF_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn gpiog(&mut self) -> GPIOG_W<6> {
GPIOG_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn gpioh(&mut self) -> GPIOH_W<7> {
GPIOH_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn gpioi(&mut self) -> GPIOI_W<8> {
GPIOI_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn crc(&mut self) -> CRC_W<12> {
CRC_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn cordic(&mut self) -> CORDIC_W<15> {
CORDIC_W::new(self)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn enet(&mut self) -> ENET_W<19> {
ENET_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn dma1(&mut self) -> DMA1_W<21> {
DMA1_W::new(self)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn dma2(&mut self) -> DMA2_W<22> {
DMA2_W::new(self)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn usbfs(&mut self) -> USBFS_W<24> {
USBFS_W::new(self)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn fsmc(&mut self) -> FSMC_W<28> {
FSMC_W::new(self)
}
#[doc = "Bit 30"]
#[inline(always)]
#[must_use]
pub fn qspi(&mut self) -> QSPI_W<30> {
QSPI_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "AHB1 Peripheral Reset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahb1rstr](index.html) module"]
pub struct AHB1RSTR_SPEC;
impl crate::RegisterSpec for AHB1RSTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ahb1rstr::R](R) reader structure"]
impl crate::Readable for AHB1RSTR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ahb1rstr::W](W) writer structure"]
impl crate::Writable for AHB1RSTR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets AHB1RSTR to value 0"]
impl crate::Resettable for AHB1RSTR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "APB2RSTR (rw) register accessor: an alias for `Reg<APB2RSTR_SPEC>`"]
pub type APB2RSTR = crate::Reg<apb2rstr::APB2RSTR_SPEC>;
#[doc = "APB2 Peripheral Reset Register"]
pub mod apb2rstr {
#[doc = "Register `APB2RSTR` reader"]
pub struct R(crate::R<APB2RSTR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<APB2RSTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<APB2RSTR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<APB2RSTR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `APB2RSTR` writer"]
pub struct W(crate::W<APB2RSTR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<APB2RSTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<APB2RSTR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<APB2RSTR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TIM1` reader - "]
pub type TIM1_R = crate::BitReader<bool>;
#[doc = "Field `TIM1` writer - "]
pub type TIM1_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2RSTR_SPEC, bool, O>;
#[doc = "Field `TIM8` reader - "]
pub type TIM8_R = crate::BitReader<bool>;
#[doc = "Field `TIM8` writer - "]
pub type TIM8_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2RSTR_SPEC, bool, O>;
#[doc = "Field `UART1` reader - "]
pub type UART1_R = crate::BitReader<bool>;
#[doc = "Field `UART1` writer - "]
pub type UART1_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2RSTR_SPEC, bool, O>;
#[doc = "Field `UART6` reader - "]
pub type UART6_R = crate::BitReader<bool>;
#[doc = "Field `UART6` writer - "]
pub type UART6_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2RSTR_SPEC, bool, O>;
#[doc = "Field `ADC1` reader - "]
pub type ADC1_R = crate::BitReader<bool>;
#[doc = "Field `ADC1` writer - "]
pub type ADC1_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2RSTR_SPEC, bool, O>;
#[doc = "Field `ADC2` reader - "]
pub type ADC2_R = crate::BitReader<bool>;
#[doc = "Field `ADC2` writer - "]
pub type ADC2_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2RSTR_SPEC, bool, O>;
#[doc = "Field `SPI1` reader - "]
pub type SPI1_R = crate::BitReader<bool>;
#[doc = "Field `SPI1` writer - "]
pub type SPI1_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2RSTR_SPEC, bool, O>;
#[doc = "Field `SYSCFG` reader - "]
pub type SYSCFG_R = crate::BitReader<bool>;
#[doc = "Field `SYSCFG` writer - "]
pub type SYSCFG_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2RSTR_SPEC, bool, O>;
#[doc = "Field `COMP` reader - "]
pub type COMP_R = crate::BitReader<bool>;
#[doc = "Field `COMP` writer - "]
pub type COMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2RSTR_SPEC, bool, O>;
#[doc = "Field `FLEXCAN2` reader - "]
pub type FLEXCAN2_R = crate::BitReader<bool>;
#[doc = "Field `FLEXCAN2` writer - "]
pub type FLEXCAN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2RSTR_SPEC, bool, O>;
#[doc = "Field `MINDSWITCH` reader - "]
pub type MINDSWITCH_R = crate::BitReader<bool>;
#[doc = "Field `MINDSWITCH` writer - "]
pub type MINDSWITCH_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2RSTR_SPEC, bool, O>;
#[doc = "Field `LPTIM` reader - "]
pub type LPTIM_R = crate::BitReader<bool>;
#[doc = "Field `LPTIM` writer - "]
pub type LPTIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2RSTR_SPEC, bool, O>;
#[doc = "Field `LPUART` reader - "]
pub type LPUART_R = crate::BitReader<bool>;
#[doc = "Field `LPUART` writer - "]
pub type LPUART_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2RSTR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn tim1(&self) -> TIM1_R {
TIM1_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn tim8(&self) -> TIM8_R {
TIM8_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn uart1(&self) -> UART1_R {
UART1_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn uart6(&self) -> UART6_R {
UART6_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn adc1(&self) -> ADC1_R {
ADC1_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn adc2(&self) -> ADC2_R {
ADC2_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn spi1(&self) -> SPI1_R {
SPI1_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn syscfg(&self) -> SYSCFG_R {
SYSCFG_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn comp(&self) -> COMP_R {
COMP_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn flexcan2(&self) -> FLEXCAN2_R {
FLEXCAN2_R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn mindswitch(&self) -> MINDSWITCH_R {
MINDSWITCH_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn lptim(&self) -> LPTIM_R {
LPTIM_R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn lpuart(&self) -> LPUART_R {
LPUART_R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn tim1(&mut self) -> TIM1_W<0> {
TIM1_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn tim8(&mut self) -> TIM8_W<1> {
TIM8_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn uart1(&mut self) -> UART1_W<4> {
UART1_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn uart6(&mut self) -> UART6_W<5> {
UART6_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn adc1(&mut self) -> ADC1_W<8> {
ADC1_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn adc2(&mut self) -> ADC2_W<9> {
ADC2_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn spi1(&mut self) -> SPI1_W<12> {
SPI1_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn syscfg(&mut self) -> SYSCFG_W<14> {
SYSCFG_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn comp(&mut self) -> COMP_W<15> {
COMP_W::new(self)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn flexcan2(&mut self) -> FLEXCAN2_W<24> {
FLEXCAN2_W::new(self)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn mindswitch(&mut self) -> MINDSWITCH_W<28> {
MINDSWITCH_W::new(self)
}
#[doc = "Bit 30"]
#[inline(always)]
#[must_use]
pub fn lptim(&mut self) -> LPTIM_W<30> {
LPTIM_W::new(self)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn lpuart(&mut self) -> LPUART_W<31> {
LPUART_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "APB2 Peripheral Reset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apb2rstr](index.html) module"]
pub struct APB2RSTR_SPEC;
impl crate::RegisterSpec for APB2RSTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [apb2rstr::R](R) reader structure"]
impl crate::Readable for APB2RSTR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [apb2rstr::W](W) writer structure"]
impl crate::Writable for APB2RSTR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets APB2RSTR to value 0"]
impl crate::Resettable for APB2RSTR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "APB1RSTR (rw) register accessor: an alias for `Reg<APB1RSTR_SPEC>`"]
pub type APB1RSTR = crate::Reg<apb1rstr::APB1RSTR_SPEC>;
#[doc = "APB1 Peripheral Reset Register"]
pub mod apb1rstr {
#[doc = "Register `APB1RSTR` reader"]
pub struct R(crate::R<APB1RSTR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<APB1RSTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<APB1RSTR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<APB1RSTR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `APB1RSTR` writer"]
pub struct W(crate::W<APB1RSTR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<APB1RSTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<APB1RSTR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<APB1RSTR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TIM2` reader - "]
pub type TIM2_R = crate::BitReader<bool>;
#[doc = "Field `TIM2` writer - "]
pub type TIM2_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `TIM3` reader - "]
pub type TIM3_R = crate::BitReader<bool>;
#[doc = "Field `TIM3` writer - "]
pub type TIM3_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `TIM4` reader - "]
pub type TIM4_R = crate::BitReader<bool>;
#[doc = "Field `TIM4` writer - "]
pub type TIM4_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `TIM5` reader - "]
pub type TIM5_R = crate::BitReader<bool>;
#[doc = "Field `TIM5` writer - "]
pub type TIM5_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `TIM6` reader - "]
pub type TIM6_R = crate::BitReader<bool>;
#[doc = "Field `TIM6` writer - "]
pub type TIM6_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `TIM7` reader - "]
pub type TIM7_R = crate::BitReader<bool>;
#[doc = "Field `TIM7` writer - "]
pub type TIM7_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `WWDG` reader - "]
pub type WWDG_R = crate::BitReader<bool>;
#[doc = "Field `WWDG` writer - "]
pub type WWDG_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `SPI2` reader - "]
pub type SPI2_R = crate::BitReader<bool>;
#[doc = "Field `SPI2` writer - "]
pub type SPI2_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `SPI3` reader - "]
pub type SPI3_R = crate::BitReader<bool>;
#[doc = "Field `SPI3` writer - "]
pub type SPI3_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `UART2` reader - "]
pub type UART2_R = crate::BitReader<bool>;
#[doc = "Field `UART2` writer - "]
pub type UART2_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `UART3` reader - "]
pub type UART3_R = crate::BitReader<bool>;
#[doc = "Field `UART3` writer - "]
pub type UART3_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `UART4` reader - "]
pub type UART4_R = crate::BitReader<bool>;
#[doc = "Field `UART4` writer - "]
pub type UART4_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `UART5` reader - "]
pub type UART5_R = crate::BitReader<bool>;
#[doc = "Field `UART5` writer - "]
pub type UART5_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `I2C1` reader - "]
pub type I2C1_R = crate::BitReader<bool>;
#[doc = "Field `I2C1` writer - "]
pub type I2C1_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `I2C2` reader - "]
pub type I2C2_R = crate::BitReader<bool>;
#[doc = "Field `I2C2` writer - "]
pub type I2C2_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `CRS` reader - "]
pub type CRS_R = crate::BitReader<bool>;
#[doc = "Field `CRS` writer - "]
pub type CRS_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `FLEXCAN1` reader - "]
pub type FLEXCAN1_R = crate::BitReader<bool>;
#[doc = "Field `FLEXCAN1` writer - "]
pub type FLEXCAN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `DBG` reader - "]
pub type DBG_R = crate::BitReader<bool>;
#[doc = "Field `DBG` writer - "]
pub type DBG_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `BKP` reader - "]
pub type BKP_R = crate::BitReader<bool>;
#[doc = "Field `BKP` writer - "]
pub type BKP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `PWR` reader - "]
pub type PWR_R = crate::BitReader<bool>;
#[doc = "Field `PWR` writer - "]
pub type PWR_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `DAC` reader - "]
pub type DAC_R = crate::BitReader<bool>;
#[doc = "Field `DAC` writer - "]
pub type DAC_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
#[doc = "Field `UART7` reader - "]
pub type UART7_R = crate::BitReader<bool>;
#[doc = "Field `UART7` writer - "]
pub type UART7_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1RSTR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn tim2(&self) -> TIM2_R {
TIM2_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn tim3(&self) -> TIM3_R {
TIM3_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn tim4(&self) -> TIM4_R {
TIM4_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn tim5(&self) -> TIM5_R {
TIM5_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn tim6(&self) -> TIM6_R {
TIM6_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn tim7(&self) -> TIM7_R {
TIM7_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn wwdg(&self) -> WWDG_R {
WWDG_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn spi2(&self) -> SPI2_R {
SPI2_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn spi3(&self) -> SPI3_R {
SPI3_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn uart2(&self) -> UART2_R {
UART2_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn uart3(&self) -> UART3_R {
UART3_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn uart4(&self) -> UART4_R {
UART4_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn uart5(&self) -> UART5_R {
UART5_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn i2c1(&self) -> I2C1_R {
I2C1_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn i2c2(&self) -> I2C2_R {
I2C2_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn crs(&self) -> CRS_R {
CRS_R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn flexcan1(&self) -> FLEXCAN1_R {
FLEXCAN1_R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26"]
#[inline(always)]
pub fn dbg(&self) -> DBG_R {
DBG_R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27"]
#[inline(always)]
pub fn bkp(&self) -> BKP_R {
BKP_R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn pwr(&self) -> PWR_R {
PWR_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29"]
#[inline(always)]
pub fn dac(&self) -> DAC_R {
DAC_R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn uart7(&self) -> UART7_R {
UART7_R::new(((self.bits >> 30) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn tim2(&mut self) -> TIM2_W<0> {
TIM2_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn tim3(&mut self) -> TIM3_W<1> {
TIM3_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn tim4(&mut self) -> TIM4_W<2> {
TIM4_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn tim5(&mut self) -> TIM5_W<3> {
TIM5_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn tim6(&mut self) -> TIM6_W<4> {
TIM6_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn tim7(&mut self) -> TIM7_W<5> {
TIM7_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn wwdg(&mut self) -> WWDG_W<11> {
WWDG_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn spi2(&mut self) -> SPI2_W<14> {
SPI2_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn spi3(&mut self) -> SPI3_W<15> {
SPI3_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn uart2(&mut self) -> UART2_W<17> {
UART2_W::new(self)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn uart3(&mut self) -> UART3_W<18> {
UART3_W::new(self)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn uart4(&mut self) -> UART4_W<19> {
UART4_W::new(self)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn uart5(&mut self) -> UART5_W<20> {
UART5_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn i2c1(&mut self) -> I2C1_W<21> {
I2C1_W::new(self)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn i2c2(&mut self) -> I2C2_W<22> {
I2C2_W::new(self)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn crs(&mut self) -> CRS_W<24> {
CRS_W::new(self)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn flexcan1(&mut self) -> FLEXCAN1_W<25> {
FLEXCAN1_W::new(self)
}
#[doc = "Bit 26"]
#[inline(always)]
#[must_use]
pub fn dbg(&mut self) -> DBG_W<26> {
DBG_W::new(self)
}
#[doc = "Bit 27"]
#[inline(always)]
#[must_use]
pub fn bkp(&mut self) -> BKP_W<27> {
BKP_W::new(self)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn pwr(&mut self) -> PWR_W<28> {
PWR_W::new(self)
}
#[doc = "Bit 29"]
#[inline(always)]
#[must_use]
pub fn dac(&mut self) -> DAC_W<29> {
DAC_W::new(self)
}
#[doc = "Bit 30"]
#[inline(always)]
#[must_use]
pub fn uart7(&mut self) -> UART7_W<30> {
UART7_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "APB1 Peripheral Reset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apb1rstr](index.html) module"]
pub struct APB1RSTR_SPEC;
impl crate::RegisterSpec for APB1RSTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [apb1rstr::R](R) reader structure"]
impl crate::Readable for APB1RSTR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [apb1rstr::W](W) writer structure"]
impl crate::Writable for APB1RSTR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets APB1RSTR to value 0"]
impl crate::Resettable for APB1RSTR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "AHB1ENR (rw) register accessor: an alias for `Reg<AHB1ENR_SPEC>`"]
pub type AHB1ENR = crate::Reg<ahb1enr::AHB1ENR_SPEC>;
#[doc = "AHB1 peripheral clock enable register"]
pub mod ahb1enr {
#[doc = "Register `AHB1ENR` reader"]
pub struct R(crate::R<AHB1ENR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<AHB1ENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<AHB1ENR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<AHB1ENR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `AHB1ENR` writer"]
pub struct W(crate::W<AHB1ENR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<AHB1ENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<AHB1ENR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<AHB1ENR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `GPIOA` reader - "]
pub type GPIOA_R = crate::BitReader<bool>;
#[doc = "Field `GPIOA` writer - "]
pub type GPIOA_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `GPIOB` reader - "]
pub type GPIOB_R = crate::BitReader<bool>;
#[doc = "Field `GPIOB` writer - "]
pub type GPIOB_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `GPIOC` reader - "]
pub type GPIOC_R = crate::BitReader<bool>;
#[doc = "Field `GPIOC` writer - "]
pub type GPIOC_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `GPIOD` reader - "]
pub type GPIOD_R = crate::BitReader<bool>;
#[doc = "Field `GPIOD` writer - "]
pub type GPIOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `GPIOE` reader - "]
pub type GPIOE_R = crate::BitReader<bool>;
#[doc = "Field `GPIOE` writer - "]
pub type GPIOE_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `GPIOF` reader - "]
pub type GPIOF_R = crate::BitReader<bool>;
#[doc = "Field `GPIOF` writer - "]
pub type GPIOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `GPIOG` reader - "]
pub type GPIOG_R = crate::BitReader<bool>;
#[doc = "Field `GPIOG` writer - "]
pub type GPIOG_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `GPIOH` reader - "]
pub type GPIOH_R = crate::BitReader<bool>;
#[doc = "Field `GPIOH` writer - "]
pub type GPIOH_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `GPIOI` reader - "]
pub type GPIOI_R = crate::BitReader<bool>;
#[doc = "Field `GPIOI` writer - "]
pub type GPIOI_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `CRC` reader - "]
pub type CRC_R = crate::BitReader<bool>;
#[doc = "Field `CRC` writer - "]
pub type CRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `FLASH` reader - "]
pub type FLASH_R = crate::BitReader<bool>;
#[doc = "Field `FLASH` writer - "]
pub type FLASH_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `SRAM` reader - "]
pub type SRAM_R = crate::BitReader<bool>;
#[doc = "Field `SRAM` writer - "]
pub type SRAM_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `CORDIC` reader - "]
pub type CORDIC_R = crate::BitReader<bool>;
#[doc = "Field `CORDIC` writer - "]
pub type CORDIC_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `ITCM` reader - "]
pub type ITCM_R = crate::BitReader<bool>;
#[doc = "Field `ITCM` writer - "]
pub type ITCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `DTCM` reader - "]
pub type DTCM_R = crate::BitReader<bool>;
#[doc = "Field `DTCM` writer - "]
pub type DTCM_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `ENET` reader - "]
pub type ENET_R = crate::BitReader<bool>;
#[doc = "Field `ENET` writer - "]
pub type ENET_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `DMA1` reader - "]
pub type DMA1_R = crate::BitReader<bool>;
#[doc = "Field `DMA1` writer - "]
pub type DMA1_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `DMA2` reader - "]
pub type DMA2_R = crate::BitReader<bool>;
#[doc = "Field `DMA2` writer - "]
pub type DMA2_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `USBOTGFS` reader - "]
pub type USBOTGFS_R = crate::BitReader<bool>;
#[doc = "Field `USBOTGFS` writer - "]
pub type USBOTGFS_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `FSMC` reader - "]
pub type FSMC_R = crate::BitReader<bool>;
#[doc = "Field `FSMC` writer - "]
pub type FSMC_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
#[doc = "Field `QSPI` reader - "]
pub type QSPI_R = crate::BitReader<bool>;
#[doc = "Field `QSPI` writer - "]
pub type QSPI_W<'a, const O: u8> = crate::BitWriter<'a, u32, AHB1ENR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn gpioa(&self) -> GPIOA_R {
GPIOA_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn gpiob(&self) -> GPIOB_R {
GPIOB_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn gpioc(&self) -> GPIOC_R {
GPIOC_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn gpiod(&self) -> GPIOD_R {
GPIOD_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn gpioe(&self) -> GPIOE_R {
GPIOE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn gpiof(&self) -> GPIOF_R {
GPIOF_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn gpiog(&self) -> GPIOG_R {
GPIOG_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn gpioh(&self) -> GPIOH_R {
GPIOH_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn gpioi(&self) -> GPIOI_R {
GPIOI_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn crc(&self) -> CRC_R {
CRC_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn flash(&self) -> FLASH_R {
FLASH_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn sram(&self) -> SRAM_R {
SRAM_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn cordic(&self) -> CORDIC_R {
CORDIC_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn itcm(&self) -> ITCM_R {
ITCM_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn dtcm(&self) -> DTCM_R {
DTCM_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn enet(&self) -> ENET_R {
ENET_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn dma1(&self) -> DMA1_R {
DMA1_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn dma2(&self) -> DMA2_R {
DMA2_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn usbotgfs(&self) -> USBOTGFS_R {
USBOTGFS_R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn fsmc(&self) -> FSMC_R {
FSMC_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn qspi(&self) -> QSPI_R {
QSPI_R::new(((self.bits >> 30) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn gpioa(&mut self) -> GPIOA_W<0> {
GPIOA_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn gpiob(&mut self) -> GPIOB_W<1> {
GPIOB_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn gpioc(&mut self) -> GPIOC_W<2> {
GPIOC_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn gpiod(&mut self) -> GPIOD_W<3> {
GPIOD_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn gpioe(&mut self) -> GPIOE_W<4> {
GPIOE_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn gpiof(&mut self) -> GPIOF_W<5> {
GPIOF_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn gpiog(&mut self) -> GPIOG_W<6> {
GPIOG_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn gpioh(&mut self) -> GPIOH_W<7> {
GPIOH_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn gpioi(&mut self) -> GPIOI_W<8> {
GPIOI_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn crc(&mut self) -> CRC_W<12> {
CRC_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn flash(&mut self) -> FLASH_W<13> {
FLASH_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn sram(&mut self) -> SRAM_W<14> {
SRAM_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn cordic(&mut self) -> CORDIC_W<15> {
CORDIC_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn itcm(&mut self) -> ITCM_W<16> {
ITCM_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn dtcm(&mut self) -> DTCM_W<17> {
DTCM_W::new(self)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn enet(&mut self) -> ENET_W<19> {
ENET_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn dma1(&mut self) -> DMA1_W<21> {
DMA1_W::new(self)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn dma2(&mut self) -> DMA2_W<22> {
DMA2_W::new(self)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn usbotgfs(&mut self) -> USBOTGFS_W<24> {
USBOTGFS_W::new(self)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn fsmc(&mut self) -> FSMC_W<28> {
FSMC_W::new(self)
}
#[doc = "Bit 30"]
#[inline(always)]
#[must_use]
pub fn qspi(&mut self) -> QSPI_W<30> {
QSPI_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "AHB1 peripheral clock enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahb1enr](index.html) module"]
pub struct AHB1ENR_SPEC;
impl crate::RegisterSpec for AHB1ENR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ahb1enr::R](R) reader structure"]
impl crate::Readable for AHB1ENR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ahb1enr::W](W) writer structure"]
impl crate::Writable for AHB1ENR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets AHB1ENR to value 0x0003_6000"]
impl crate::Resettable for AHB1ENR_SPEC {
const RESET_VALUE: Self::Ux = 0x0003_6000;
}
}
#[doc = "APB2ENR (rw) register accessor: an alias for `Reg<APB2ENR_SPEC>`"]
pub type APB2ENR = crate::Reg<apb2enr::APB2ENR_SPEC>;
#[doc = "APB2 Peripheral Clock Enable Register"]
pub mod apb2enr {
#[doc = "Register `APB2ENR` reader"]
pub struct R(crate::R<APB2ENR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<APB2ENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<APB2ENR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<APB2ENR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `APB2ENR` writer"]
pub struct W(crate::W<APB2ENR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<APB2ENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<APB2ENR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<APB2ENR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TIM1` reader - "]
pub type TIM1_R = crate::BitReader<bool>;
#[doc = "Field `TIM1` writer - "]
pub type TIM1_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2ENR_SPEC, bool, O>;
#[doc = "Field `TIM8` reader - "]
pub type TIM8_R = crate::BitReader<bool>;
#[doc = "Field `TIM8` writer - "]
pub type TIM8_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2ENR_SPEC, bool, O>;
#[doc = "Field `UART1` reader - "]
pub type UART1_R = crate::BitReader<bool>;
#[doc = "Field `UART1` writer - "]
pub type UART1_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2ENR_SPEC, bool, O>;
#[doc = "Field `UART6` reader - "]
pub type UART6_R = crate::BitReader<bool>;
#[doc = "Field `UART6` writer - "]
pub type UART6_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2ENR_SPEC, bool, O>;
#[doc = "Field `ADC1` reader - "]
pub type ADC1_R = crate::BitReader<bool>;
#[doc = "Field `ADC1` writer - "]
pub type ADC1_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2ENR_SPEC, bool, O>;
#[doc = "Field `ADC2` reader - "]
pub type ADC2_R = crate::BitReader<bool>;
#[doc = "Field `ADC2` writer - "]
pub type ADC2_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2ENR_SPEC, bool, O>;
#[doc = "Field `SPI1` reader - "]
pub type SPI1_R = crate::BitReader<bool>;
#[doc = "Field `SPI1` writer - "]
pub type SPI1_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2ENR_SPEC, bool, O>;
#[doc = "Field `SYSCFG` reader - "]
pub type SYSCFG_R = crate::BitReader<bool>;
#[doc = "Field `SYSCFG` writer - "]
pub type SYSCFG_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2ENR_SPEC, bool, O>;
#[doc = "Field `COMP` reader - "]
pub type COMP_R = crate::BitReader<bool>;
#[doc = "Field `COMP` writer - "]
pub type COMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2ENR_SPEC, bool, O>;
#[doc = "Field `FLEXCAN2` reader - "]
pub type FLEXCAN2_R = crate::BitReader<bool>;
#[doc = "Field `FLEXCAN2` writer - "]
pub type FLEXCAN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2ENR_SPEC, bool, O>;
#[doc = "Field `MINDSWITCH` reader - "]
pub type MINDSWITCH_R = crate::BitReader<bool>;
#[doc = "Field `MINDSWITCH` writer - "]
pub type MINDSWITCH_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2ENR_SPEC, bool, O>;
#[doc = "Field `LPTIM` reader - "]
pub type LPTIM_R = crate::BitReader<bool>;
#[doc = "Field `LPTIM` writer - "]
pub type LPTIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2ENR_SPEC, bool, O>;
#[doc = "Field `LPUART` reader - "]
pub type LPUART_R = crate::BitReader<bool>;
#[doc = "Field `LPUART` writer - "]
pub type LPUART_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB2ENR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn tim1(&self) -> TIM1_R {
TIM1_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn tim8(&self) -> TIM8_R {
TIM8_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn uart1(&self) -> UART1_R {
UART1_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn uart6(&self) -> UART6_R {
UART6_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn adc1(&self) -> ADC1_R {
ADC1_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn adc2(&self) -> ADC2_R {
ADC2_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn spi1(&self) -> SPI1_R {
SPI1_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn syscfg(&self) -> SYSCFG_R {
SYSCFG_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn comp(&self) -> COMP_R {
COMP_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn flexcan2(&self) -> FLEXCAN2_R {
FLEXCAN2_R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn mindswitch(&self) -> MINDSWITCH_R {
MINDSWITCH_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn lptim(&self) -> LPTIM_R {
LPTIM_R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn lpuart(&self) -> LPUART_R {
LPUART_R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn tim1(&mut self) -> TIM1_W<0> {
TIM1_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn tim8(&mut self) -> TIM8_W<1> {
TIM8_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn uart1(&mut self) -> UART1_W<4> {
UART1_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn uart6(&mut self) -> UART6_W<5> {
UART6_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn adc1(&mut self) -> ADC1_W<8> {
ADC1_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn adc2(&mut self) -> ADC2_W<9> {
ADC2_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn spi1(&mut self) -> SPI1_W<12> {
SPI1_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn syscfg(&mut self) -> SYSCFG_W<14> {
SYSCFG_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn comp(&mut self) -> COMP_W<15> {
COMP_W::new(self)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn flexcan2(&mut self) -> FLEXCAN2_W<24> {
FLEXCAN2_W::new(self)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn mindswitch(&mut self) -> MINDSWITCH_W<28> {
MINDSWITCH_W::new(self)
}
#[doc = "Bit 30"]
#[inline(always)]
#[must_use]
pub fn lptim(&mut self) -> LPTIM_W<30> {
LPTIM_W::new(self)
}
#[doc = "Bit 31"]
#[inline(always)]
#[must_use]
pub fn lpuart(&mut self) -> LPUART_W<31> {
LPUART_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "APB2 Peripheral Clock Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apb2enr](index.html) module"]
pub struct APB2ENR_SPEC;
impl crate::RegisterSpec for APB2ENR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [apb2enr::R](R) reader structure"]
impl crate::Readable for APB2ENR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [apb2enr::W](W) writer structure"]
impl crate::Writable for APB2ENR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets APB2ENR to value 0"]
impl crate::Resettable for APB2ENR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "APB1ENR (rw) register accessor: an alias for `Reg<APB1ENR_SPEC>`"]
pub type APB1ENR = crate::Reg<apb1enr::APB1ENR_SPEC>;
#[doc = "APB1 Peripheral Clock Enable Register"]
pub mod apb1enr {
#[doc = "Register `APB1ENR` reader"]
pub struct R(crate::R<APB1ENR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<APB1ENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<APB1ENR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<APB1ENR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `APB1ENR` writer"]
pub struct W(crate::W<APB1ENR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<APB1ENR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<APB1ENR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<APB1ENR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TIM2` reader - "]
pub type TIM2_R = crate::BitReader<bool>;
#[doc = "Field `TIM2` writer - "]
pub type TIM2_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `TIM3` reader - "]
pub type TIM3_R = crate::BitReader<bool>;
#[doc = "Field `TIM3` writer - "]
pub type TIM3_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `TIM4` reader - "]
pub type TIM4_R = crate::BitReader<bool>;
#[doc = "Field `TIM4` writer - "]
pub type TIM4_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `TIM5` reader - "]
pub type TIM5_R = crate::BitReader<bool>;
#[doc = "Field `TIM5` writer - "]
pub type TIM5_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `TIM6` reader - "]
pub type TIM6_R = crate::BitReader<bool>;
#[doc = "Field `TIM6` writer - "]
pub type TIM6_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `TIM7` reader - "]
pub type TIM7_R = crate::BitReader<bool>;
#[doc = "Field `TIM7` writer - "]
pub type TIM7_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `WWDG` reader - "]
pub type WWDG_R = crate::BitReader<bool>;
#[doc = "Field `WWDG` writer - "]
pub type WWDG_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `SPI2` reader - "]
pub type SPI2_R = crate::BitReader<bool>;
#[doc = "Field `SPI2` writer - "]
pub type SPI2_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `SPI3` reader - "]
pub type SPI3_R = crate::BitReader<bool>;
#[doc = "Field `SPI3` writer - "]
pub type SPI3_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `UART2` reader - "]
pub type UART2_R = crate::BitReader<bool>;
#[doc = "Field `UART2` writer - "]
pub type UART2_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `UART3` reader - "]
pub type UART3_R = crate::BitReader<bool>;
#[doc = "Field `UART3` writer - "]
pub type UART3_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `UART4` reader - "]
pub type UART4_R = crate::BitReader<bool>;
#[doc = "Field `UART4` writer - "]
pub type UART4_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `UART5` reader - "]
pub type UART5_R = crate::BitReader<bool>;
#[doc = "Field `UART5` writer - "]
pub type UART5_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `I2C1` reader - "]
pub type I2C1_R = crate::BitReader<bool>;
#[doc = "Field `I2C1` writer - "]
pub type I2C1_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `I2C2` reader - "]
pub type I2C2_R = crate::BitReader<bool>;
#[doc = "Field `I2C2` writer - "]
pub type I2C2_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `CRS` reader - "]
pub type CRS_R = crate::BitReader<bool>;
#[doc = "Field `CRS` writer - "]
pub type CRS_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `FLEXCAN1` reader - "]
pub type FLEXCAN1_R = crate::BitReader<bool>;
#[doc = "Field `FLEXCAN1` writer - "]
pub type FLEXCAN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `BKP` reader - "]
pub type BKP_R = crate::BitReader<bool>;
#[doc = "Field `BKP` writer - "]
pub type BKP_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `PWR_DBG` reader - "]
pub type PWR_DBG_R = crate::BitReader<bool>;
#[doc = "Field `PWR_DBG` writer - "]
pub type PWR_DBG_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `DAC` reader - "]
pub type DAC_R = crate::BitReader<bool>;
#[doc = "Field `DAC` writer - "]
pub type DAC_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
#[doc = "Field `UART7` reader - "]
pub type UART7_R = crate::BitReader<bool>;
#[doc = "Field `UART7` writer - "]
pub type UART7_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB1ENR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn tim2(&self) -> TIM2_R {
TIM2_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn tim3(&self) -> TIM3_R {
TIM3_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn tim4(&self) -> TIM4_R {
TIM4_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn tim5(&self) -> TIM5_R {
TIM5_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn tim6(&self) -> TIM6_R {
TIM6_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn tim7(&self) -> TIM7_R {
TIM7_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn wwdg(&self) -> WWDG_R {
WWDG_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn spi2(&self) -> SPI2_R {
SPI2_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn spi3(&self) -> SPI3_R {
SPI3_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn uart2(&self) -> UART2_R {
UART2_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn uart3(&self) -> UART3_R {
UART3_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn uart4(&self) -> UART4_R {
UART4_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn uart5(&self) -> UART5_R {
UART5_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn i2c1(&self) -> I2C1_R {
I2C1_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn i2c2(&self) -> I2C2_R {
I2C2_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn crs(&self) -> CRS_R {
CRS_R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn flexcan1(&self) -> FLEXCAN1_R {
FLEXCAN1_R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 27"]
#[inline(always)]
pub fn bkp(&self) -> BKP_R {
BKP_R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn pwr_dbg(&self) -> PWR_DBG_R {
PWR_DBG_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29"]
#[inline(always)]
pub fn dac(&self) -> DAC_R {
DAC_R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn uart7(&self) -> UART7_R {
UART7_R::new(((self.bits >> 30) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn tim2(&mut self) -> TIM2_W<0> {
TIM2_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn tim3(&mut self) -> TIM3_W<1> {
TIM3_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn tim4(&mut self) -> TIM4_W<2> {
TIM4_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn tim5(&mut self) -> TIM5_W<3> {
TIM5_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn tim6(&mut self) -> TIM6_W<4> {
TIM6_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn tim7(&mut self) -> TIM7_W<5> {
TIM7_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn wwdg(&mut self) -> WWDG_W<11> {
WWDG_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn spi2(&mut self) -> SPI2_W<14> {
SPI2_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn spi3(&mut self) -> SPI3_W<15> {
SPI3_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn uart2(&mut self) -> UART2_W<17> {
UART2_W::new(self)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn uart3(&mut self) -> UART3_W<18> {
UART3_W::new(self)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn uart4(&mut self) -> UART4_W<19> {
UART4_W::new(self)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn uart5(&mut self) -> UART5_W<20> {
UART5_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn i2c1(&mut self) -> I2C1_W<21> {
I2C1_W::new(self)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn i2c2(&mut self) -> I2C2_W<22> {
I2C2_W::new(self)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn crs(&mut self) -> CRS_W<24> {
CRS_W::new(self)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn flexcan1(&mut self) -> FLEXCAN1_W<25> {
FLEXCAN1_W::new(self)
}
#[doc = "Bit 27"]
#[inline(always)]
#[must_use]
pub fn bkp(&mut self) -> BKP_W<27> {
BKP_W::new(self)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn pwr_dbg(&mut self) -> PWR_DBG_W<28> {
PWR_DBG_W::new(self)
}
#[doc = "Bit 29"]
#[inline(always)]
#[must_use]
pub fn dac(&mut self) -> DAC_W<29> {
DAC_W::new(self)
}
#[doc = "Bit 30"]
#[inline(always)]
#[must_use]
pub fn uart7(&mut self) -> UART7_W<30> {
UART7_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "APB1 Peripheral Clock Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apb1enr](index.html) module"]
pub struct APB1ENR_SPEC;
impl crate::RegisterSpec for APB1ENR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [apb1enr::R](R) reader structure"]
impl crate::Readable for APB1ENR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [apb1enr::W](W) writer structure"]
impl crate::Writable for APB1ENR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets APB1ENR to value 0"]
impl crate::Resettable for APB1ENR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "BDCR (rw) register accessor: an alias for `Reg<BDCR_SPEC>`"]
pub type BDCR = crate::Reg<bdcr::BDCR_SPEC>;
#[doc = "Backup Domain Control Register"]
pub mod bdcr {
#[doc = "Register `BDCR` reader"]
pub struct R(crate::R<BDCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<BDCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<BDCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<BDCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `BDCR` writer"]
pub struct W(crate::W<BDCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<BDCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<BDCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<BDCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `LSEON` reader - "]
pub type LSEON_R = crate::BitReader<bool>;
#[doc = "Field `LSEON` writer - "]
pub type LSEON_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDCR_SPEC, bool, O>;
#[doc = "Field `LSERDY` reader - "]
pub type LSERDY_R = crate::BitReader<bool>;
#[doc = "Field `LSERDY` writer - "]
pub type LSERDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDCR_SPEC, bool, O>;
#[doc = "Field `LSEBYP` reader - "]
pub type LSEBYP_R = crate::BitReader<bool>;
#[doc = "Field `LSEBYP` writer - "]
pub type LSEBYP_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDCR_SPEC, bool, O>;
#[doc = "Field `RTCSEL` reader - "]
pub type RTCSEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `RTCSEL` writer - "]
pub type RTCSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BDCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `RTCEN` reader - "]
pub type RTCEN_R = crate::BitReader<bool>;
#[doc = "Field `RTCEN` writer - "]
pub type RTCEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDCR_SPEC, bool, O>;
#[doc = "Field `BDRST` reader - "]
pub type BDRST_R = crate::BitReader<bool>;
#[doc = "Field `BDRST` writer - "]
pub type BDRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDCR_SPEC, bool, O>;
#[doc = "Field `DBP` reader - "]
pub type DBP_R = crate::BitReader<bool>;
#[doc = "Field `DBP` writer - "]
pub type DBP_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDCR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn lseon(&self) -> LSEON_R {
LSEON_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn lserdy(&self) -> LSERDY_R {
LSERDY_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn lsebyp(&self) -> LSEBYP_R {
LSEBYP_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn rtcsel(&self) -> RTCSEL_R {
RTCSEL_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn rtcen(&self) -> RTCEN_R {
RTCEN_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn bdrst(&self) -> BDRST_R {
BDRST_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn dbp(&self) -> DBP_R {
DBP_R::new(((self.bits >> 24) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn lseon(&mut self) -> LSEON_W<0> {
LSEON_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn lserdy(&mut self) -> LSERDY_W<1> {
LSERDY_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn lsebyp(&mut self) -> LSEBYP_W<2> {
LSEBYP_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn rtcsel(&mut self) -> RTCSEL_W<8> {
RTCSEL_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn rtcen(&mut self) -> RTCEN_W<15> {
RTCEN_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn bdrst(&mut self) -> BDRST_W<16> {
BDRST_W::new(self)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn dbp(&mut self) -> DBP_W<24> {
DBP_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Backup Domain Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bdcr](index.html) module"]
pub struct BDCR_SPEC;
impl crate::RegisterSpec for BDCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [bdcr::R](R) reader structure"]
impl crate::Readable for BDCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [bdcr::W](W) writer structure"]
impl crate::Writable for BDCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets BDCR to value 0"]
impl crate::Resettable for BDCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CSR (rw) register accessor: an alias for `Reg<CSR_SPEC>`"]
pub type CSR = crate::Reg<csr::CSR_SPEC>;
#[doc = "Control Status Register"]
pub mod csr {
#[doc = "Register `CSR` reader"]
pub struct R(crate::R<CSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CSR` writer"]
pub struct W(crate::W<CSR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CSR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CSR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `LSION` reader - "]
pub type LSION_R = crate::BitReader<bool>;
#[doc = "Field `LSION` writer - "]
pub type LSION_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
#[doc = "Field `LSIRDY` reader - "]
pub type LSIRDY_R = crate::BitReader<bool>;
#[doc = "Field `LSI_OE` reader - "]
pub type LSI_OE_R = crate::BitReader<bool>;
#[doc = "Field `LSI_OE` writer - "]
pub type LSI_OE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
#[doc = "Field `PVDRSTEN` reader - "]
pub type PVDRSTEN_R = crate::BitReader<bool>;
#[doc = "Field `PVDRSTEN` writer - "]
pub type PVDRSTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
#[doc = "Field `LOCKUPEN` reader - "]
pub type LOCKUPEN_R = crate::BitReader<bool>;
#[doc = "Field `LOCKUPEN` writer - "]
pub type LOCKUPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
#[doc = "Field `PVDRSTF` reader - "]
pub type PVDRSTF_R = crate::BitReader<bool>;
#[doc = "Field `LOCKUPF` reader - "]
pub type LOCKUPF_R = crate::BitReader<bool>;
#[doc = "Field `LOCKUPF` writer - "]
pub type LOCKUPF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
#[doc = "Field `RMVF` reader - "]
pub type RMVF_R = crate::BitReader<bool>;
#[doc = "Field `RMVF` writer - "]
pub type RMVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
#[doc = "Field `PINRSTF` reader - "]
pub type PINRSTF_R = crate::BitReader<bool>;
#[doc = "Field `PORRSTF` reader - "]
pub type PORRSTF_R = crate::BitReader<bool>;
#[doc = "Field `SFTRSTF` reader - "]
pub type SFTRSTF_R = crate::BitReader<bool>;
#[doc = "Field `IWDGRSTF` reader - "]
pub type IWDGRSTF_R = crate::BitReader<bool>;
#[doc = "Field `WWDGRSTF` reader - "]
pub type WWDGRSTF_R = crate::BitReader<bool>;
#[doc = "Field `LPWRRSTF` reader - "]
pub type LPWRRSTF_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn lsion(&self) -> LSION_R {
LSION_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn lsirdy(&self) -> LSIRDY_R {
LSIRDY_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn lsi_oe(&self) -> LSI_OE_R {
LSI_OE_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn pvdrsten(&self) -> PVDRSTEN_R {
PVDRSTEN_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn lockupen(&self) -> LOCKUPEN_R {
LOCKUPEN_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn pvdrstf(&self) -> PVDRSTF_R {
PVDRSTF_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23"]
#[inline(always)]
pub fn lockupf(&self) -> LOCKUPF_R {
LOCKUPF_R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24"]
#[inline(always)]
pub fn rmvf(&self) -> RMVF_R {
RMVF_R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 26"]
#[inline(always)]
pub fn pinrstf(&self) -> PINRSTF_R {
PINRSTF_R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27"]
#[inline(always)]
pub fn porrstf(&self) -> PORRSTF_R {
PORRSTF_R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn sftrstf(&self) -> SFTRSTF_R {
SFTRSTF_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29"]
#[inline(always)]
pub fn iwdgrstf(&self) -> IWDGRSTF_R {
IWDGRSTF_R::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30"]
#[inline(always)]
pub fn wwdgrstf(&self) -> WWDGRSTF_R {
WWDGRSTF_R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31"]
#[inline(always)]
pub fn lpwrrstf(&self) -> LPWRRSTF_R {
LPWRRSTF_R::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn lsion(&mut self) -> LSION_W<0> {
LSION_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn lsi_oe(&mut self) -> LSI_OE_W<5> {
LSI_OE_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn pvdrsten(&mut self) -> PVDRSTEN_W<6> {
PVDRSTEN_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn lockupen(&mut self) -> LOCKUPEN_W<7> {
LOCKUPEN_W::new(self)
}
#[doc = "Bit 23"]
#[inline(always)]
#[must_use]
pub fn lockupf(&mut self) -> LOCKUPF_W<23> {
LOCKUPF_W::new(self)
}
#[doc = "Bit 24"]
#[inline(always)]
#[must_use]
pub fn rmvf(&mut self) -> RMVF_W<24> {
RMVF_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Control Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"]
pub struct CSR_SPEC;
impl crate::RegisterSpec for CSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [csr::R](R) reader structure"]
impl crate::Readable for CSR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"]
impl crate::Writable for CSR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CSR to value 0x0c00_0000"]
impl crate::Resettable for CSR_SPEC {
const RESET_VALUE: Self::Ux = 0x0c00_0000;
}
}
#[doc = "SYSCFG (rw) register accessor: an alias for `Reg<SYSCFG_SPEC>`"]
pub type SYSCFG = crate::Reg<syscfg::SYSCFG_SPEC>;
#[doc = "System Configuration Register"]
pub mod syscfg {
#[doc = "Register `SYSCFG` reader"]
pub struct R(crate::R<SYSCFG_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SYSCFG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SYSCFG_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SYSCFG_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SYSCFG` writer"]
pub struct W(crate::W<SYSCFG_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SYSCFG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SYSCFG_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SYSCFG_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PROG_CHECK_EN` reader - "]
pub type PROG_CHECK_EN_R = crate::BitReader<bool>;
#[doc = "Field `SECTOR_1K_CFG` reader - "]
pub type SECTOR_1K_CFG_R = crate::BitReader<bool>;
#[doc = "Field `HSE_RFB_SEL` reader - "]
pub type HSE_RFB_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `HSE_RFB_SEL` writer - "]
pub type HSE_RFB_SEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, SYSCFG_SPEC, u8, u8, 2, O>;
#[doc = "Field `HSELPFEN` reader - "]
pub type HSELPFEN_R = crate::BitReader<bool>;
#[doc = "Field `HSELPFEN` writer - "]
pub type HSELPFEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SYSCFG_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn prog_check_en(&self) -> PROG_CHECK_EN_R {
PROG_CHECK_EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn sector_1k_cfg(&self) -> SECTOR_1K_CFG_R {
SECTOR_1K_CFG_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn hse_rfb_sel(&self) -> HSE_RFB_SEL_R {
HSE_RFB_SEL_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn hselpfen(&self) -> HSELPFEN_R {
HSELPFEN_R::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn hse_rfb_sel(&mut self) -> HSE_RFB_SEL_W<8> {
HSE_RFB_SEL_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn hselpfen(&mut self) -> HSELPFEN_W<14> {
HSELPFEN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "System Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syscfg](index.html) module"]
pub struct SYSCFG_SPEC;
impl crate::RegisterSpec for SYSCFG_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [syscfg::R](R) reader structure"]
impl crate::Readable for SYSCFG_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [syscfg::W](W) writer structure"]
impl crate::Writable for SYSCFG_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SYSCFG to value 0x0101"]
impl crate::Resettable for SYSCFG_SPEC {
const RESET_VALUE: Self::Ux = 0x0101;
}
}
#[doc = "CFGR2 (rw) register accessor: an alias for `Reg<CFGR2_SPEC>`"]
pub type CFGR2 = crate::Reg<cfgr2::CFGR2_SPEC>;
#[doc = "Clock Configuration Register 2"]
pub mod cfgr2 {
#[doc = "Register `CFGR2` reader"]
pub struct R(crate::R<CFGR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CFGR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CFGR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CFGR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CFGR2` writer"]
pub struct W(crate::W<CFGR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CFGR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CFGR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CFGR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TIMADV_CKSEL` reader - "]
pub type TIMADV_CKSEL_R = crate::BitReader<bool>;
#[doc = "Field `TIMADV_CKSEL` writer - "]
pub type TIMADV_CKSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
#[doc = "Field `TIMADV_PRE` reader - "]
pub type TIMADV_PRE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TIMADV_PRE` writer - "]
pub type TIMADV_PRE_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CFGR2_SPEC, u8, u8, 3, O>;
#[doc = "Field `APB1_CLK_HV_PRE` reader - "]
pub type APB1_CLK_HV_PRE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `APB1_CLK_HV_PRE` writer - "]
pub type APB1_CLK_HV_PRE_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CFGR2_SPEC, u8, u8, 4, O>;
#[doc = "Field `MCO_PRE` reader - "]
pub type MCO_PRE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MCO_PRE` writer - "]
pub type MCO_PRE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR2_SPEC, u8, u8, 4, O>;
#[doc = "Field `LPUARTCLKSEL` reader - "]
pub type LPUARTCLKSEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `LPUARTCLKSEL` writer - "]
pub type LPUARTCLKSEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CFGR2_SPEC, u8, u8, 2, O>;
#[doc = "Field `LPTIMCLKSEL` reader - "]
pub type LPTIMCLKSEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `LPTIMCLKSEL` writer - "]
pub type LPTIMCLKSEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CFGR2_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn timadv_cksel(&self) -> TIMADV_CKSEL_R {
TIMADV_CKSEL_R::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:3"]
#[inline(always)]
pub fn timadv_pre(&self) -> TIMADV_PRE_R {
TIMADV_PRE_R::new(((self.bits >> 1) & 7) as u8)
}
#[doc = "Bits 16:19"]
#[inline(always)]
pub fn apb1_clk_hv_pre(&self) -> APB1_CLK_HV_PRE_R {
APB1_CLK_HV_PRE_R::new(((self.bits >> 16) & 0x0f) as u8)
}
#[doc = "Bits 20:23"]
#[inline(always)]
pub fn mco_pre(&self) -> MCO_PRE_R {
MCO_PRE_R::new(((self.bits >> 20) & 0x0f) as u8)
}
#[doc = "Bits 26:27"]
#[inline(always)]
pub fn lpuartclksel(&self) -> LPUARTCLKSEL_R {
LPUARTCLKSEL_R::new(((self.bits >> 26) & 3) as u8)
}
#[doc = "Bits 29:30"]
#[inline(always)]
pub fn lptimclksel(&self) -> LPTIMCLKSEL_R {
LPTIMCLKSEL_R::new(((self.bits >> 29) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn timadv_cksel(&mut self) -> TIMADV_CKSEL_W<0> {
TIMADV_CKSEL_W::new(self)
}
#[doc = "Bits 1:3"]
#[inline(always)]
#[must_use]
pub fn timadv_pre(&mut self) -> TIMADV_PRE_W<1> {
TIMADV_PRE_W::new(self)
}
#[doc = "Bits 16:19"]
#[inline(always)]
#[must_use]
pub fn apb1_clk_hv_pre(&mut self) -> APB1_CLK_HV_PRE_W<16> {
APB1_CLK_HV_PRE_W::new(self)
}
#[doc = "Bits 20:23"]
#[inline(always)]
#[must_use]
pub fn mco_pre(&mut self) -> MCO_PRE_W<20> {
MCO_PRE_W::new(self)
}
#[doc = "Bits 26:27"]
#[inline(always)]
#[must_use]
pub fn lpuartclksel(&mut self) -> LPUARTCLKSEL_W<26> {
LPUARTCLKSEL_W::new(self)
}
#[doc = "Bits 29:30"]
#[inline(always)]
#[must_use]
pub fn lptimclksel(&mut self) -> LPTIMCLKSEL_W<29> {
LPTIMCLKSEL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Clock Configuration Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr2](index.html) module"]
pub struct CFGR2_SPEC;
impl crate::RegisterSpec for CFGR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cfgr2::R](R) reader structure"]
impl crate::Readable for CFGR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfgr2::W](W) writer structure"]
impl crate::Writable for CFGR2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CFGR2 to value 0x4003_0000"]
impl crate::Resettable for CFGR2_SPEC {
const RESET_VALUE: Self::Ux = 0x4003_0000;
}
}
#[doc = "PLL1CFGR (rw) register accessor: an alias for `Reg<PLL1CFGR_SPEC>`"]
pub type PLL1CFGR = crate::Reg<pll1cfgr::PLL1CFGR_SPEC>;
#[doc = "PLL1 Configuration Register"]
pub mod pll1cfgr {
#[doc = "Register `PLL1CFGR` reader"]
pub struct R(crate::R<PLL1CFGR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PLL1CFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PLL1CFGR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PLL1CFGR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PLL1CFGR` writer"]
pub struct W(crate::W<PLL1CFGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PLL1CFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PLL1CFGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PLL1CFGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PLL1SRC` reader - "]
pub type PLL1SRC_R = crate::BitReader<bool>;
#[doc = "Field `PLL1SRC` writer - "]
pub type PLL1SRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, PLL1CFGR_SPEC, bool, O>;
#[doc = "Field `PLL1XTPRE` reader - "]
pub type PLL1XTPRE_R = crate::BitReader<bool>;
#[doc = "Field `PLL1XTPRE` writer - "]
pub type PLL1XTPRE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PLL1CFGR_SPEC, bool, O>;
#[doc = "Field `PLL1_ICTRL` reader - "]
pub type PLL1_ICTRL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PLL1_ICTRL` writer - "]
pub type PLL1_ICTRL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PLL1CFGR_SPEC, u8, u8, 2, O>;
#[doc = "Field `PLL1_LDS` reader - "]
pub type PLL1_LDS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PLL1_LDS` writer - "]
pub type PLL1_LDS_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PLL1CFGR_SPEC, u8, u8, 3, O>;
#[doc = "Field `PLL1DIV` reader - "]
pub type PLL1DIV_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PLL1DIV` writer - "]
pub type PLL1DIV_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PLL1CFGR_SPEC, u8, u8, 3, O>;
#[doc = "Field `PLL1MUL` reader - "]
pub type PLL1MUL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PLL1MUL` writer - "]
pub type PLL1MUL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PLL1CFGR_SPEC, u8, u8, 7, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pll1src(&self) -> PLL1SRC_R {
PLL1SRC_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn pll1xtpre(&self) -> PLL1XTPRE_R {
PLL1XTPRE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:3"]
#[inline(always)]
pub fn pll1_ictrl(&self) -> PLL1_ICTRL_R {
PLL1_ICTRL_R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn pll1_lds(&self) -> PLL1_LDS_R {
PLL1_LDS_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bits 8:10"]
#[inline(always)]
pub fn pll1div(&self) -> PLL1DIV_R {
PLL1DIV_R::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bits 16:22"]
#[inline(always)]
pub fn pll1mul(&self) -> PLL1MUL_R {
PLL1MUL_R::new(((self.bits >> 16) & 0x7f) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pll1src(&mut self) -> PLL1SRC_W<0> {
PLL1SRC_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn pll1xtpre(&mut self) -> PLL1XTPRE_W<1> {
PLL1XTPRE_W::new(self)
}
#[doc = "Bits 2:3"]
#[inline(always)]
#[must_use]
pub fn pll1_ictrl(&mut self) -> PLL1_ICTRL_W<2> {
PLL1_ICTRL_W::new(self)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn pll1_lds(&mut self) -> PLL1_LDS_W<4> {
PLL1_LDS_W::new(self)
}
#[doc = "Bits 8:10"]
#[inline(always)]
#[must_use]
pub fn pll1div(&mut self) -> PLL1DIV_W<8> {
PLL1DIV_W::new(self)
}
#[doc = "Bits 16:22"]
#[inline(always)]
#[must_use]
pub fn pll1mul(&mut self) -> PLL1MUL_W<16> {
PLL1MUL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "PLL1 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll1cfgr](index.html) module"]
pub struct PLL1CFGR_SPEC;
impl crate::RegisterSpec for PLL1CFGR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [pll1cfgr::R](R) reader structure"]
impl crate::Readable for PLL1CFGR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pll1cfgr::W](W) writer structure"]
impl crate::Writable for PLL1CFGR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PLL1CFGR to value 0"]
impl crate::Resettable for PLL1CFGR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PLL2CFGR (rw) register accessor: an alias for `Reg<PLL2CFGR_SPEC>`"]
pub type PLL2CFGR = crate::Reg<pll2cfgr::PLL2CFGR_SPEC>;
#[doc = "PLL2 Configuration Register"]
pub mod pll2cfgr {
#[doc = "Register `PLL2CFGR` reader"]
pub struct R(crate::R<PLL2CFGR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PLL2CFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PLL2CFGR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PLL2CFGR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PLL2CFGR` writer"]
pub struct W(crate::W<PLL2CFGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PLL2CFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PLL2CFGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PLL2CFGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PLL2SRC` reader - "]
pub type PLL2SRC_R = crate::BitReader<bool>;
#[doc = "Field `PLL2SRC` writer - "]
pub type PLL2SRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, PLL2CFGR_SPEC, bool, O>;
#[doc = "Field `PLL2XTPRE` reader - "]
pub type PLL2XTPRE_R = crate::BitReader<bool>;
#[doc = "Field `PLL2XTPRE` writer - "]
pub type PLL2XTPRE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PLL2CFGR_SPEC, bool, O>;
#[doc = "Field `PLL2_ICTRL` reader - "]
pub type PLL2_ICTRL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PLL2_ICTRL` writer - "]
pub type PLL2_ICTRL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PLL2CFGR_SPEC, u8, u8, 2, O>;
#[doc = "Field `PLL2_LDS` reader - "]
pub type PLL2_LDS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PLL2_LDS` writer - "]
pub type PLL2_LDS_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PLL2CFGR_SPEC, u8, u8, 3, O>;
#[doc = "Field `PLL2_DIV` reader - "]
pub type PLL2_DIV_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PLL2_DIV` writer - "]
pub type PLL2_DIV_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PLL2CFGR_SPEC, u8, u8, 3, O>;
#[doc = "Field `PLL2_MUL` reader - "]
pub type PLL2_MUL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PLL2_MUL` writer - "]
pub type PLL2_MUL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PLL2CFGR_SPEC, u8, u8, 8, O>;
#[doc = "Field `PLL2_PDIV` reader - "]
pub type PLL2_PDIV_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PLL2_PDIV` writer - "]
pub type PLL2_PDIV_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, PLL2CFGR_SPEC, u8, u8, 3, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pll2src(&self) -> PLL2SRC_R {
PLL2SRC_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn pll2xtpre(&self) -> PLL2XTPRE_R {
PLL2XTPRE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:3"]
#[inline(always)]
pub fn pll2_ictrl(&self) -> PLL2_ICTRL_R {
PLL2_ICTRL_R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn pll2_lds(&self) -> PLL2_LDS_R {
PLL2_LDS_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bits 8:10"]
#[inline(always)]
pub fn pll2_div(&self) -> PLL2_DIV_R {
PLL2_DIV_R::new(((self.bits >> 8) & 7) as u8)
}
#[doc = "Bits 16:23"]
#[inline(always)]
pub fn pll2_mul(&self) -> PLL2_MUL_R {
PLL2_MUL_R::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:26"]
#[inline(always)]
pub fn pll2_pdiv(&self) -> PLL2_PDIV_R {
PLL2_PDIV_R::new(((self.bits >> 24) & 7) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pll2src(&mut self) -> PLL2SRC_W<0> {
PLL2SRC_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn pll2xtpre(&mut self) -> PLL2XTPRE_W<1> {
PLL2XTPRE_W::new(self)
}
#[doc = "Bits 2:3"]
#[inline(always)]
#[must_use]
pub fn pll2_ictrl(&mut self) -> PLL2_ICTRL_W<2> {
PLL2_ICTRL_W::new(self)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn pll2_lds(&mut self) -> PLL2_LDS_W<4> {
PLL2_LDS_W::new(self)
}
#[doc = "Bits 8:10"]
#[inline(always)]
#[must_use]
pub fn pll2_div(&mut self) -> PLL2_DIV_W<8> {
PLL2_DIV_W::new(self)
}
#[doc = "Bits 16:23"]
#[inline(always)]
#[must_use]
pub fn pll2_mul(&mut self) -> PLL2_MUL_W<16> {
PLL2_MUL_W::new(self)
}
#[doc = "Bits 24:26"]
#[inline(always)]
#[must_use]
pub fn pll2_pdiv(&mut self) -> PLL2_PDIV_W<24> {
PLL2_PDIV_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "PLL2 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pll2cfgr](index.html) module"]
pub struct PLL2CFGR_SPEC;
impl crate::RegisterSpec for PLL2CFGR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [pll2cfgr::R](R) reader structure"]
impl crate::Readable for PLL2CFGR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pll2cfgr::W](W) writer structure"]
impl crate::Writable for PLL2CFGR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PLL2CFGR to value 0"]
impl crate::Resettable for PLL2CFGR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ADC1CFGR (rw) register accessor: an alias for `Reg<ADC1CFGR_SPEC>`"]
pub type ADC1CFGR = crate::Reg<adc1cfgr::ADC1CFGR_SPEC>;
#[doc = "ADC1 Configuration Register"]
pub mod adc1cfgr {
#[doc = "Register `ADC1CFGR` reader"]
pub struct R(crate::R<ADC1CFGR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ADC1CFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ADC1CFGR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ADC1CFGR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ADC1CFGR` writer"]
pub struct W(crate::W<ADC1CFGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ADC1CFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ADC1CFGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ADC1CFGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PRE` reader - "]
pub type PRE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PRE` writer - "]
pub type PRE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADC1CFGR_SPEC, u8, u8, 4, O>;
#[doc = "Field `PRE_CAL` reader - "]
pub type PRE_CAL_R = crate::FieldReader<u16, u16>;
#[doc = "Field `PRE_CAL` writer - "]
pub type PRE_CAL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, ADC1CFGR_SPEC, u16, u16, 9, O>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn pre(&self) -> PRE_R {
PRE_R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 8:16"]
#[inline(always)]
pub fn pre_cal(&self) -> PRE_CAL_R {
PRE_CAL_R::new(((self.bits >> 8) & 0x01ff) as u16)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn pre(&mut self) -> PRE_W<0> {
PRE_W::new(self)
}
#[doc = "Bits 8:16"]
#[inline(always)]
#[must_use]
pub fn pre_cal(&mut self) -> PRE_CAL_W<8> {
PRE_CAL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "ADC1 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adc1cfgr](index.html) module"]
pub struct ADC1CFGR_SPEC;
impl crate::RegisterSpec for ADC1CFGR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [adc1cfgr::R](R) reader structure"]
impl crate::Readable for ADC1CFGR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [adc1cfgr::W](W) writer structure"]
impl crate::Writable for ADC1CFGR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ADC1CFGR to value 0"]
impl crate::Resettable for ADC1CFGR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ADC2CFGR (rw) register accessor: an alias for `Reg<ADC2CFGR_SPEC>`"]
pub type ADC2CFGR = crate::Reg<adc2cfgr::ADC2CFGR_SPEC>;
#[doc = "ADC2 Configuration Register"]
pub mod adc2cfgr {
#[doc = "Register `ADC2CFGR` reader"]
pub struct R(crate::R<ADC2CFGR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ADC2CFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ADC2CFGR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ADC2CFGR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ADC2CFGR` writer"]
pub struct W(crate::W<ADC2CFGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ADC2CFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ADC2CFGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ADC2CFGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PRE` reader - "]
pub type PRE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PRE` writer - "]
pub type PRE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADC2CFGR_SPEC, u8, u8, 4, O>;
#[doc = "Field `PRE_CAL` reader - "]
pub type PRE_CAL_R = crate::FieldReader<u16, u16>;
#[doc = "Field `PRE_CAL` writer - "]
pub type PRE_CAL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, ADC2CFGR_SPEC, u16, u16, 9, O>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn pre(&self) -> PRE_R {
PRE_R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 8:16"]
#[inline(always)]
pub fn pre_cal(&self) -> PRE_CAL_R {
PRE_CAL_R::new(((self.bits >> 8) & 0x01ff) as u16)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn pre(&mut self) -> PRE_W<0> {
PRE_W::new(self)
}
#[doc = "Bits 8:16"]
#[inline(always)]
#[must_use]
pub fn pre_cal(&mut self) -> PRE_CAL_W<8> {
PRE_CAL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "ADC2 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adc2cfgr](index.html) module"]
pub struct ADC2CFGR_SPEC;
impl crate::RegisterSpec for ADC2CFGR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [adc2cfgr::R](R) reader structure"]
impl crate::Readable for ADC2CFGR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [adc2cfgr::W](W) writer structure"]
impl crate::Writable for ADC2CFGR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ADC2CFGR to value 0"]
impl crate::Resettable for ADC2CFGR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DACCFGR (rw) register accessor: an alias for `Reg<DACCFGR_SPEC>`"]
pub type DACCFGR = crate::Reg<daccfgr::DACCFGR_SPEC>;
#[doc = "DAC Configuration Register"]
pub mod daccfgr {
#[doc = "Register `DACCFGR` reader"]
pub struct R(crate::R<DACCFGR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DACCFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DACCFGR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DACCFGR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DACCFGR` writer"]
pub struct W(crate::W<DACCFGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DACCFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DACCFGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DACCFGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PRE` reader - "]
pub type PRE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PRE` writer - "]
pub type PRE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DACCFGR_SPEC, u8, u8, 7, O>;
impl R {
#[doc = "Bits 0:6"]
#[inline(always)]
pub fn pre(&self) -> PRE_R {
PRE_R::new((self.bits & 0x7f) as u8)
}
}
impl W {
#[doc = "Bits 0:6"]
#[inline(always)]
#[must_use]
pub fn pre(&mut self) -> PRE_W<0> {
PRE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DAC Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [daccfgr](index.html) module"]
pub struct DACCFGR_SPEC;
impl crate::RegisterSpec for DACCFGR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [daccfgr::R](R) reader structure"]
impl crate::Readable for DACCFGR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [daccfgr::W](W) writer structure"]
impl crate::Writable for DACCFGR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DACCFGR to value 0"]
impl crate::Resettable for DACCFGR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "FSMCCFGR (rw) register accessor: an alias for `Reg<FSMCCFGR_SPEC>`"]
pub type FSMCCFGR = crate::Reg<fsmccfgr::FSMCCFGR_SPEC>;
#[doc = "FSMC Configuration Register"]
pub mod fsmccfgr {
#[doc = "Register `FSMCCFGR` reader"]
pub struct R(crate::R<FSMCCFGR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSMCCFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSMCCFGR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSMCCFGR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSMCCFGR` writer"]
pub struct W(crate::W<FSMCCFGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSMCCFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSMCCFGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSMCCFGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `FSMC_PRE` reader - "]
pub type FSMC_PRE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `FSMC_PRE` writer - "]
pub type FSMC_PRE_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, FSMCCFGR_SPEC, u8, u8, 5, O>;
#[doc = "Field `FSMC_SYNCEN` reader - "]
pub type FSMC_SYNCEN_R = crate::BitReader<bool>;
#[doc = "Field `FSMC_SYNCEN` writer - "]
pub type FSMC_SYNCEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSMCCFGR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:4"]
#[inline(always)]
pub fn fsmc_pre(&self) -> FSMC_PRE_R {
FSMC_PRE_R::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn fsmc_syncen(&self) -> FSMC_SYNCEN_R {
FSMC_SYNCEN_R::new(((self.bits >> 8) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:4"]
#[inline(always)]
#[must_use]
pub fn fsmc_pre(&mut self) -> FSMC_PRE_W<0> {
FSMC_PRE_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn fsmc_syncen(&mut self) -> FSMC_SYNCEN_W<8> {
FSMC_SYNCEN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "FSMC Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsmccfgr](index.html) module"]
pub struct FSMCCFGR_SPEC;
impl crate::RegisterSpec for FSMCCFGR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fsmccfgr::R](R) reader structure"]
impl crate::Readable for FSMCCFGR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fsmccfgr::W](W) writer structure"]
impl crate::Writable for FSMCCFGR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSMCCFGR to value 0x1f"]
impl crate::Resettable for FSMCCFGR_SPEC {
const RESET_VALUE: Self::Ux = 0x1f;
}
}
#[doc = "TPIUCFGR (rw) register accessor: an alias for `Reg<TPIUCFGR_SPEC>`"]
pub type TPIUCFGR = crate::Reg<tpiucfgr::TPIUCFGR_SPEC>;
#[doc = "TPIU configuration register"]
pub mod tpiucfgr {
#[doc = "Register `TPIUCFGR` reader"]
pub struct R(crate::R<TPIUCFGR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<TPIUCFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<TPIUCFGR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<TPIUCFGR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `TPIUCFGR` writer"]
pub struct W(crate::W<TPIUCFGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<TPIUCFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<TPIUCFGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<TPIUCFGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PRE` reader - "]
pub type PRE_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PRE` writer - "]
pub type PRE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TPIUCFGR_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn pre(&self) -> PRE_R {
PRE_R::new((self.bits & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn pre(&mut self) -> PRE_W<0> {
PRE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "TPIU configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tpiucfgr](index.html) module"]
pub struct TPIUCFGR_SPEC;
impl crate::RegisterSpec for TPIUCFGR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [tpiucfgr::R](R) reader structure"]
impl crate::Readable for TPIUCFGR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [tpiucfgr::W](W) writer structure"]
impl crate::Writable for TPIUCFGR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets TPIUCFGR to value 0"]
impl crate::Resettable for TPIUCFGR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "RTC"]
pub struct RTC {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for RTC {}
impl RTC {
#[doc = r"Pointer to the register block"]
pub const PTR: *const rtc::RegisterBlock = 0x4000_2800 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const rtc::RegisterBlock {
Self::PTR
}
}
impl Deref for RTC {
type Target = rtc::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for RTC {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("RTC").finish()
}
}
#[doc = "RTC"]
pub mod rtc {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - RTC control register high bits"]
pub crh: CRH,
#[doc = "0x04 - RTC control register low bits"]
pub crl: CRL,
#[doc = "0x08 - RTC prescaler load register high bits"]
pub prlh: PRLH,
#[doc = "0x0c - RTC prescaler load register low bits"]
pub prll: PRLL,
#[doc = "0x10 - RTC prescaler division factor register high bits"]
pub divh: DIVH,
#[doc = "0x14 - RTC prescaler division factor register low bits"]
pub divl: DIVL,
#[doc = "0x18 - RTC counter register high bits"]
pub cnth: CNTH,
#[doc = "0x1c - RTC counter register low bits"]
pub cntl: CNTL,
#[doc = "0x20 - RTC alarm register high bit"]
pub alrh: ALRH,
#[doc = "0x24 - RTC alarm register low bits"]
pub alrl: ALRL,
#[doc = "0x28 - RTC millisecond register high bit"]
pub msrh: MSRH,
#[doc = "0x2c - RTC millisecond register low bit"]
pub msrl: MSRL,
_reserved12: [u8; 0x0c],
#[doc = "0x3c - RTC LSE Configuration Register"]
pub lse_cfg: LSE_CFG,
}
#[doc = "CRH (rw) register accessor: an alias for `Reg<CRH_SPEC>`"]
pub type CRH = crate::Reg<crh::CRH_SPEC>;
#[doc = "RTC control register high bits"]
pub mod crh {
#[doc = "Register `CRH` reader"]
pub struct R(crate::R<CRH_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CRH_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CRH_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CRH_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CRH` writer"]
pub struct W(crate::W<CRH_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CRH_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CRH_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CRH_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SECIE` reader - "]
pub type SECIE_R = crate::BitReader<bool>;
#[doc = "Field `SECIE` writer - "]
pub type SECIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CRH_SPEC, bool, O>;
#[doc = "Field `ALRIE` reader - "]
pub type ALRIE_R = crate::BitReader<bool>;
#[doc = "Field `ALRIE` writer - "]
pub type ALRIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CRH_SPEC, bool, O>;
#[doc = "Field `OWIE` reader - "]
pub type OWIE_R = crate::BitReader<bool>;
#[doc = "Field `OWIE` writer - "]
pub type OWIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CRH_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn secie(&self) -> SECIE_R {
SECIE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn alrie(&self) -> ALRIE_R {
ALRIE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn owie(&self) -> OWIE_R {
OWIE_R::new(((self.bits >> 2) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn secie(&mut self) -> SECIE_W<0> {
SECIE_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn alrie(&mut self) -> ALRIE_W<1> {
ALRIE_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn owie(&mut self) -> OWIE_W<2> {
OWIE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "RTC control register high bits\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crh](index.html) module"]
pub struct CRH_SPEC;
impl crate::RegisterSpec for CRH_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [crh::R](R) reader structure"]
impl crate::Readable for CRH_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [crh::W](W) writer structure"]
impl crate::Writable for CRH_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CRH to value 0"]
impl crate::Resettable for CRH_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CRL (rw) register accessor: an alias for `Reg<CRL_SPEC>`"]
pub type CRL = crate::Reg<crl::CRL_SPEC>;
#[doc = "RTC control register low bits"]
pub mod crl {
#[doc = "Register `CRL` reader"]
pub struct R(crate::R<CRL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CRL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CRL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CRL` writer"]
pub struct W(crate::W<CRL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CRL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CRL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SECF` reader - "]
pub type SECF_R = crate::BitReader<bool>;
#[doc = "Field `SECF` writer - "]
pub type SECF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CRL_SPEC, bool, O>;
#[doc = "Field `ALRF` reader - "]
pub type ALRF_R = crate::BitReader<bool>;
#[doc = "Field `ALRF` writer - "]
pub type ALRF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CRL_SPEC, bool, O>;
#[doc = "Field `OWF` reader - "]
pub type OWF_R = crate::BitReader<bool>;
#[doc = "Field `OWF` writer - "]
pub type OWF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CRL_SPEC, bool, O>;
#[doc = "Field `RSF` reader - "]
pub type RSF_R = crate::BitReader<bool>;
#[doc = "Field `RSF` writer - "]
pub type RSF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CRL_SPEC, bool, O>;
#[doc = "Field `CNF` reader - "]
pub type CNF_R = crate::BitReader<bool>;
#[doc = "Field `CNF` writer - "]
pub type CNF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CRL_SPEC, bool, O>;
#[doc = "Field `RTOFF` reader - "]
pub type RTOFF_R = crate::BitReader<bool>;
#[doc = "Field `ALPEN` reader - "]
pub type ALPEN_R = crate::BitReader<bool>;
#[doc = "Field `ALPEN` writer - "]
pub type ALPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CRL_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn secf(&self) -> SECF_R {
SECF_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn alrf(&self) -> ALRF_R {
ALRF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn owf(&self) -> OWF_R {
OWF_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rsf(&self) -> RSF_R {
RSF_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn cnf(&self) -> CNF_R {
CNF_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rtoff(&self) -> RTOFF_R {
RTOFF_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn alpen(&self) -> ALPEN_R {
ALPEN_R::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn secf(&mut self) -> SECF_W<0> {
SECF_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn alrf(&mut self) -> ALRF_W<1> {
ALRF_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn owf(&mut self) -> OWF_W<2> {
OWF_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rsf(&mut self) -> RSF_W<3> {
RSF_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn cnf(&mut self) -> CNF_W<4> {
CNF_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn alpen(&mut self) -> ALPEN_W<6> {
ALPEN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "RTC control register low bits\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crl](index.html) module"]
pub struct CRL_SPEC;
impl crate::RegisterSpec for CRL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [crl::R](R) reader structure"]
impl crate::Readable for CRL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [crl::W](W) writer structure"]
impl crate::Writable for CRL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CRL to value 0x20"]
impl crate::Resettable for CRL_SPEC {
const RESET_VALUE: Self::Ux = 0x20;
}
}
#[doc = "PRLH (w) register accessor: an alias for `Reg<PRLH_SPEC>`"]
pub type PRLH = crate::Reg<prlh::PRLH_SPEC>;
#[doc = "RTC prescaler load register high bits"]
pub mod prlh {
#[doc = "Register `PRLH` writer"]
pub struct W(crate::W<PRLH_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PRLH_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PRLH_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PRLH_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PRL` writer - "]
pub type PRL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PRLH_SPEC, u8, u8, 4, O>;
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn prl(&mut self) -> PRL_W<0> {
PRL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "RTC prescaler load register high bits\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prlh](index.html) module"]
pub struct PRLH_SPEC;
impl crate::RegisterSpec for PRLH_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [prlh::W](W) writer structure"]
impl crate::Writable for PRLH_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PRLH to value 0"]
impl crate::Resettable for PRLH_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PRLL (w) register accessor: an alias for `Reg<PRLL_SPEC>`"]
pub type PRLL = crate::Reg<prll::PRLL_SPEC>;
#[doc = "RTC prescaler load register low bits"]
pub mod prll {
#[doc = "Register `PRLL` writer"]
pub struct W(crate::W<PRLL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PRLL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PRLL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PRLL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PRL` writer - "]
pub type PRL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PRLL_SPEC, u16, u16, 16, O>;
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn prl(&mut self) -> PRL_W<0> {
PRL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "RTC prescaler load register low bits\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prll](index.html) module"]
pub struct PRLL_SPEC;
impl crate::RegisterSpec for PRLL_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [prll::W](W) writer structure"]
impl crate::Writable for PRLL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PRLL to value 0x8000"]
impl crate::Resettable for PRLL_SPEC {
const RESET_VALUE: Self::Ux = 0x8000;
}
}
#[doc = "DIVH (r) register accessor: an alias for `Reg<DIVH_SPEC>`"]
pub type DIVH = crate::Reg<divh::DIVH_SPEC>;
#[doc = "RTC prescaler division factor register high bits"]
pub mod divh {
#[doc = "Register `DIVH` reader"]
pub struct R(crate::R<DIVH_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DIVH_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DIVH_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DIVH_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `DIV` reader - "]
pub type DIV_R = crate::FieldReader<u8, u8>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn div(&self) -> DIV_R {
DIV_R::new((self.bits & 0x0f) as u8)
}
}
#[doc = "RTC prescaler division factor register high bits\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [divh](index.html) module"]
pub struct DIVH_SPEC;
impl crate::RegisterSpec for DIVH_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [divh::R](R) reader structure"]
impl crate::Readable for DIVH_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets DIVH to value 0"]
impl crate::Resettable for DIVH_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DIVL (r) register accessor: an alias for `Reg<DIVL_SPEC>`"]
pub type DIVL = crate::Reg<divl::DIVL_SPEC>;
#[doc = "RTC prescaler division factor register low bits"]
pub mod divl {
#[doc = "Register `DIVL` reader"]
pub struct R(crate::R<DIVL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DIVL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DIVL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DIVL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `DIV` reader - "]
pub type DIV_R = crate::FieldReader<u16, u16>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn div(&self) -> DIV_R {
DIV_R::new((self.bits & 0xffff) as u16)
}
}
#[doc = "RTC prescaler division factor register low bits\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [divl](index.html) module"]
pub struct DIVL_SPEC;
impl crate::RegisterSpec for DIVL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [divl::R](R) reader structure"]
impl crate::Readable for DIVL_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets DIVL to value 0"]
impl crate::Resettable for DIVL_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CNTH (rw) register accessor: an alias for `Reg<CNTH_SPEC>`"]
pub type CNTH = crate::Reg<cnth::CNTH_SPEC>;
#[doc = "RTC counter register high bits"]
pub mod cnth {
#[doc = "Register `CNTH` reader"]
pub struct R(crate::R<CNTH_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CNTH_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CNTH_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CNTH_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CNTH` writer"]
pub struct W(crate::W<CNTH_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CNTH_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CNTH_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CNTH_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CNT` reader - "]
pub type CNT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CNT` writer - "]
pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTH_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn cnt(&self) -> CNT_R {
CNT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CNT_W<0> {
CNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "RTC counter register high bits\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnth](index.html) module"]
pub struct CNTH_SPEC;
impl crate::RegisterSpec for CNTH_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cnth::R](R) reader structure"]
impl crate::Readable for CNTH_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cnth::W](W) writer structure"]
impl crate::Writable for CNTH_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CNTH to value 0"]
impl crate::Resettable for CNTH_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CNTL (rw) register accessor: an alias for `Reg<CNTL_SPEC>`"]
pub type CNTL = crate::Reg<cntl::CNTL_SPEC>;
#[doc = "RTC counter register low bits"]
pub mod cntl {
#[doc = "Register `CNTL` reader"]
pub struct R(crate::R<CNTL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CNTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CNTL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CNTL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CNTL` writer"]
pub struct W(crate::W<CNTL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CNTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CNTL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CNTL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CNT` reader - "]
pub type CNT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CNT` writer - "]
pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNTL_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn cnt(&self) -> CNT_R {
CNT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CNT_W<0> {
CNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "RTC counter register low bits\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntl](index.html) module"]
pub struct CNTL_SPEC;
impl crate::RegisterSpec for CNTL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cntl::R](R) reader structure"]
impl crate::Readable for CNTL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cntl::W](W) writer structure"]
impl crate::Writable for CNTL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CNTL to value 0"]
impl crate::Resettable for CNTL_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ALRH (rw) register accessor: an alias for `Reg<ALRH_SPEC>`"]
pub type ALRH = crate::Reg<alrh::ALRH_SPEC>;
#[doc = "RTC alarm register high bit"]
pub mod alrh {
#[doc = "Register `ALRH` reader"]
pub struct R(crate::R<ALRH_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ALRH_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ALRH_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ALRH_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ALRH` writer"]
pub struct W(crate::W<ALRH_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ALRH_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ALRH_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ALRH_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `ALR` reader - "]
pub type ALR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `ALR` writer - "]
pub type ALR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ALRH_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn alr(&self) -> ALR_R {
ALR_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn alr(&mut self) -> ALR_W<0> {
ALR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "RTC alarm register high bit\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alrh](index.html) module"]
pub struct ALRH_SPEC;
impl crate::RegisterSpec for ALRH_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [alrh::R](R) reader structure"]
impl crate::Readable for ALRH_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [alrh::W](W) writer structure"]
impl crate::Writable for ALRH_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ALRH to value 0xffff"]
impl crate::Resettable for ALRH_SPEC {
const RESET_VALUE: Self::Ux = 0xffff;
}
}
#[doc = "ALRL (rw) register accessor: an alias for `Reg<ALRL_SPEC>`"]
pub type ALRL = crate::Reg<alrl::ALRL_SPEC>;
#[doc = "RTC alarm register low bits"]
pub mod alrl {
#[doc = "Register `ALRL` reader"]
pub struct R(crate::R<ALRL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ALRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ALRL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ALRL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ALRL` writer"]
pub struct W(crate::W<ALRL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ALRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ALRL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ALRL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `ALR` reader - "]
pub type ALR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `ALR` writer - "]
pub type ALR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ALRL_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn alr(&self) -> ALR_R {
ALR_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn alr(&mut self) -> ALR_W<0> {
ALR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "RTC alarm register low bits\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alrl](index.html) module"]
pub struct ALRL_SPEC;
impl crate::RegisterSpec for ALRL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [alrl::R](R) reader structure"]
impl crate::Readable for ALRL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [alrl::W](W) writer structure"]
impl crate::Writable for ALRL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ALRL to value 0xffff"]
impl crate::Resettable for ALRL_SPEC {
const RESET_VALUE: Self::Ux = 0xffff;
}
}
#[doc = "MSRH (rw) register accessor: an alias for `Reg<MSRH_SPEC>`"]
pub type MSRH = crate::Reg<msrh::MSRH_SPEC>;
#[doc = "RTC millisecond register high bit"]
pub mod msrh {
#[doc = "Register `MSRH` reader"]
pub struct R(crate::R<MSRH_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MSRH_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MSRH_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MSRH_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MSRH` writer"]
pub struct W(crate::W<MSRH_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MSRH_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MSRH_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MSRH_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MSR` reader - "]
pub type MSR_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MSR` writer - "]
pub type MSR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MSRH_SPEC, u8, u8, 4, O>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn msr(&self) -> MSR_R {
MSR_R::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn msr(&mut self) -> MSR_W<0> {
MSR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "RTC millisecond register high bit\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msrh](index.html) module"]
pub struct MSRH_SPEC;
impl crate::RegisterSpec for MSRH_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [msrh::R](R) reader structure"]
impl crate::Readable for MSRH_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [msrh::W](W) writer structure"]
impl crate::Writable for MSRH_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MSRH to value 0"]
impl crate::Resettable for MSRH_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "MSRL (rw) register accessor: an alias for `Reg<MSRL_SPEC>`"]
pub type MSRL = crate::Reg<msrl::MSRL_SPEC>;
#[doc = "RTC millisecond register low bit"]
pub mod msrl {
#[doc = "Register `MSRL` reader"]
pub struct R(crate::R<MSRL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MSRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MSRL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MSRL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MSRL` writer"]
pub struct W(crate::W<MSRL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MSRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MSRL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MSRL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `MSR` reader - "]
pub type MSR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `MSR` writer - "]
pub type MSR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MSRL_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn msr(&self) -> MSR_R {
MSR_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn msr(&mut self) -> MSR_W<0> {
MSR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "RTC millisecond register low bit\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msrl](index.html) module"]
pub struct MSRL_SPEC;
impl crate::RegisterSpec for MSRL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [msrl::R](R) reader structure"]
impl crate::Readable for MSRL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [msrl::W](W) writer structure"]
impl crate::Writable for MSRL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets MSRL to value 0"]
impl crate::Resettable for MSRL_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "LSE_CFG (rw) register accessor: an alias for `Reg<LSE_CFG_SPEC>`"]
pub type LSE_CFG = crate::Reg<lse_cfg::LSE_CFG_SPEC>;
#[doc = "RTC LSE Configuration Register"]
pub mod lse_cfg {
#[doc = "Register `LSE_CFG` reader"]
pub struct R(crate::R<LSE_CFG_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<LSE_CFG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<LSE_CFG_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<LSE_CFG_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `LSE_CFG` writer"]
pub struct W(crate::W<LSE_CFG_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<LSE_CFG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<LSE_CFG_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<LSE_CFG_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `LSE_TC` reader - "]
pub type LSE_TC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `LSE_TC` writer - "]
pub type LSE_TC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, LSE_CFG_SPEC, u8, u8, 2, O>;
#[doc = "Field `LSE_OUTENH` reader - "]
pub type LSE_OUTENH_R = crate::BitReader<bool>;
#[doc = "Field `LSE_OUTENH` writer - "]
pub type LSE_OUTENH_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSE_CFG_SPEC, bool, O>;
#[doc = "Field `LSE_DR` reader - "]
pub type LSE_DR_R = crate::FieldReader<u8, u8>;
#[doc = "Field `LSE_DR` writer - "]
pub type LSE_DR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, LSE_CFG_SPEC, u8, u8, 2, O>;
#[doc = "Field `LSE_RFB_SEL` reader - "]
pub type LSE_RFB_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `LSE_RFB_SEL` writer - "]
pub type LSE_RFB_SEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, LSE_CFG_SPEC, u8, u8, 2, O>;
#[doc = "Field `LSE_IB` reader - "]
pub type LSE_IB_R = crate::FieldReader<u8, u8>;
#[doc = "Field `LSE_IB` writer - "]
pub type LSE_IB_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, LSE_CFG_SPEC, u8, u8, 2, O>;
#[doc = "Field `LSE_AAC` reader - "]
pub type LSE_AAC_R = crate::BitReader<bool>;
#[doc = "Field `LSE_AAC` writer - "]
pub type LSE_AAC_W<'a, const O: u8> = crate::BitWriter<'a, u32, LSE_CFG_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn lse_tc(&self) -> LSE_TC_R {
LSE_TC_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn lse_outenh(&self) -> LSE_OUTENH_R {
LSE_OUTENH_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 4:5"]
#[inline(always)]
pub fn lse_dr(&self) -> LSE_DR_R {
LSE_DR_R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn lse_rfb_sel(&self) -> LSE_RFB_SEL_R {
LSE_RFB_SEL_R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn lse_ib(&self) -> LSE_IB_R {
LSE_IB_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn lse_aac(&self) -> LSE_AAC_R {
LSE_AAC_R::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn lse_tc(&mut self) -> LSE_TC_W<0> {
LSE_TC_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn lse_outenh(&mut self) -> LSE_OUTENH_W<2> {
LSE_OUTENH_W::new(self)
}
#[doc = "Bits 4:5"]
#[inline(always)]
#[must_use]
pub fn lse_dr(&mut self) -> LSE_DR_W<4> {
LSE_DR_W::new(self)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn lse_rfb_sel(&mut self) -> LSE_RFB_SEL_W<6> {
LSE_RFB_SEL_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn lse_ib(&mut self) -> LSE_IB_W<8> {
LSE_IB_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn lse_aac(&mut self) -> LSE_AAC_W<10> {
LSE_AAC_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "RTC LSE Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lse_cfg](index.html) module"]
pub struct LSE_CFG_SPEC;
impl crate::RegisterSpec for LSE_CFG_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [lse_cfg::R](R) reader structure"]
impl crate::Readable for LSE_CFG_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [lse_cfg::W](W) writer structure"]
impl crate::Writable for LSE_CFG_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets LSE_CFG to value 0x0250"]
impl crate::Resettable for LSE_CFG_SPEC {
const RESET_VALUE: Self::Ux = 0x0250;
}
}
}
#[doc = "SPI1"]
pub struct SPI1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for SPI1 {}
impl SPI1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const spi1::RegisterBlock = 0x4001_3000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const spi1::RegisterBlock {
Self::PTR
}
}
impl Deref for SPI1 {
type Target = spi1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for SPI1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI1").finish()
}
}
#[doc = "SPI1"]
pub mod spi1 {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - transmit data register"]
pub i2s_txreg: I2S_TXREG,
#[doc = "0x04 - receive data register"]
pub i2s_rxreg: I2S_RXREG,
#[doc = "0x08 - current status register"]
pub i2s_cstat: I2S_CSTAT,
#[doc = "0x0c - Interrupt Status Register"]
pub i2s_intstat: I2S_INTSTAT,
#[doc = "0x10 - Interrupt Enable Register"]
pub i2s_inten: I2S_INTEN,
#[doc = "0x14 - interrupt clear register"]
pub i2s_intclr: I2S_INTCLR,
#[doc = "0x18 - global control register"]
pub i2s_gctl: I2S_GCTL,
#[doc = "0x1c - General Control Register"]
pub i2s_cctl: I2S_CCTL,
#[doc = "0x20 - baud rate generator"]
pub i2s_spbrg: I2S_SPBRG,
#[doc = "0x24 - Receive data count register"]
pub i2s_rxdnr: I2S_RXDNR,
#[doc = "0x28 - Slave Chip Select Register"]
pub i2s_nssr: I2S_NSSR,
#[doc = "0x2c - data control register"]
pub i2s_extctl: I2S_EXTCTL,
#[doc = "0x30 - I2S configuration register"]
pub i2s_i2scfgr: I2S_I2SCFGR,
}
#[doc = "I2S_TXREG (rw) register accessor: an alias for `Reg<I2S_TXREG_SPEC>`"]
pub type I2S_TXREG = crate::Reg<i2s_txreg::I2S_TXREG_SPEC>;
#[doc = "transmit data register"]
pub mod i2s_txreg {
#[doc = "Register `I2S_TXREG` reader"]
pub struct R(crate::R<I2S_TXREG_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<I2S_TXREG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<I2S_TXREG_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<I2S_TXREG_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `I2S_TXREG` writer"]
pub struct W(crate::W<I2S_TXREG_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<I2S_TXREG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<I2S_TXREG_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<I2S_TXREG_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TXREG` reader - "]
pub type TXREG_R = crate::FieldReader<u32, u32>;
#[doc = "Field `TXREG` writer - "]
pub type TXREG_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, I2S_TXREG_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn txreg(&self) -> TXREG_R {
TXREG_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31"]
#[inline(always)]
#[must_use]
pub fn txreg(&mut self) -> TXREG_W<0> {
TXREG_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "transmit data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_txreg](index.html) module"]
pub struct I2S_TXREG_SPEC;
impl crate::RegisterSpec for I2S_TXREG_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [i2s_txreg::R](R) reader structure"]
impl crate::Readable for I2S_TXREG_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [i2s_txreg::W](W) writer structure"]
impl crate::Writable for I2S_TXREG_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets I2S_TXREG to value 0"]
impl crate::Resettable for I2S_TXREG_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "I2S_RXREG (r) register accessor: an alias for `Reg<I2S_RXREG_SPEC>`"]
pub type I2S_RXREG = crate::Reg<i2s_rxreg::I2S_RXREG_SPEC>;
#[doc = "receive data register"]
pub mod i2s_rxreg {
#[doc = "Register `I2S_RXREG` reader"]
pub struct R(crate::R<I2S_RXREG_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<I2S_RXREG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<I2S_RXREG_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<I2S_RXREG_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `RXREG` reader - "]
pub type RXREG_R = crate::FieldReader<u32, u32>;
impl R {
#[doc = "Bits 0:31"]
#[inline(always)]
pub fn rxreg(&self) -> RXREG_R {
RXREG_R::new(self.bits)
}
}
#[doc = "receive data register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_rxreg](index.html) module"]
pub struct I2S_RXREG_SPEC;
impl crate::RegisterSpec for I2S_RXREG_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [i2s_rxreg::R](R) reader structure"]
impl crate::Readable for I2S_RXREG_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets I2S_RXREG to value 0"]
impl crate::Resettable for I2S_RXREG_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "I2S_CSTAT (r) register accessor: an alias for `Reg<I2S_CSTAT_SPEC>`"]
pub type I2S_CSTAT = crate::Reg<i2s_cstat::I2S_CSTAT_SPEC>;
#[doc = "current status register"]
pub mod i2s_cstat {
#[doc = "Register `I2S_CSTAT` reader"]
pub struct R(crate::R<I2S_CSTAT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<I2S_CSTAT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<I2S_CSTAT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<I2S_CSTAT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `TXEPT` reader - "]
pub type TXEPT_R = crate::BitReader<bool>;
#[doc = "Field `RXAVL` reader - "]
pub type RXAVL_R = crate::BitReader<bool>;
#[doc = "Field `TXFULL` reader - "]
pub type TXFULL_R = crate::BitReader<bool>;
#[doc = "Field `RXAVL_4BYTE` reader - "]
pub type RXAVL_4BYTE_R = crate::BitReader<bool>;
#[doc = "Field `TXFADDR` reader - "]
pub type TXFADDR_R = crate::FieldReader<u8, u8>;
#[doc = "Field `RXFADDR` reader - "]
pub type RXFADDR_R = crate::FieldReader<u8, u8>;
#[doc = "Field `BUSY` reader - "]
pub type BUSY_R = crate::BitReader<bool>;
#[doc = "Field `CHSIDE` reader - "]
pub type CHSIDE_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn txept(&self) -> TXEPT_R {
TXEPT_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rxavl(&self) -> RXAVL_R {
RXAVL_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn txfull(&self) -> TXFULL_R {
TXFULL_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rxavl_4byte(&self) -> RXAVL_4BYTE_R {
RXAVL_4BYTE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn txfaddr(&self) -> TXFADDR_R {
TXFADDR_R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:11"]
#[inline(always)]
pub fn rxfaddr(&self) -> RXFADDR_R {
RXFADDR_R::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn busy(&self) -> BUSY_R {
BUSY_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn chside(&self) -> CHSIDE_R {
CHSIDE_R::new(((self.bits >> 13) & 1) != 0)
}
}
#[doc = "current status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_cstat](index.html) module"]
pub struct I2S_CSTAT_SPEC;
impl crate::RegisterSpec for I2S_CSTAT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [i2s_cstat::R](R) reader structure"]
impl crate::Readable for I2S_CSTAT_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets I2S_CSTAT to value 0x2001"]
impl crate::Resettable for I2S_CSTAT_SPEC {
const RESET_VALUE: Self::Ux = 0x2001;
}
}
#[doc = "I2S_INTSTAT (r) register accessor: an alias for `Reg<I2S_INTSTAT_SPEC>`"]
pub type I2S_INTSTAT = crate::Reg<i2s_intstat::I2S_INTSTAT_SPEC>;
#[doc = "Interrupt Status Register"]
pub mod i2s_intstat {
#[doc = "Register `I2S_INTSTAT` reader"]
pub struct R(crate::R<I2S_INTSTAT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<I2S_INTSTAT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<I2S_INTSTAT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<I2S_INTSTAT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `TX_INTF` reader - "]
pub type TX_INTF_R = crate::BitReader<bool>;
#[doc = "Field `RX_INTF` reader - "]
pub type RX_INTF_R = crate::BitReader<bool>;
#[doc = "Field `UNDERRUN_INTF` reader - "]
pub type UNDERRUN_INTF_R = crate::BitReader<bool>;
#[doc = "Field `RXOERR_INTF` reader - "]
pub type RXOERR_INTF_R = crate::BitReader<bool>;
#[doc = "Field `RXMATCH_INTF` reader - "]
pub type RXMATCH_INTF_R = crate::BitReader<bool>;
#[doc = "Field `RXFULL_INTF` reader - "]
pub type RXFULL_INTF_R = crate::BitReader<bool>;
#[doc = "Field `TXEPT_INTF` reader - "]
pub type TXEPT_INTF_R = crate::BitReader<bool>;
#[doc = "Field `FRE_INTF` reader - "]
pub type FRE_INTF_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn tx_intf(&self) -> TX_INTF_R {
TX_INTF_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rx_intf(&self) -> RX_INTF_R {
RX_INTF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn underrun_intf(&self) -> UNDERRUN_INTF_R {
UNDERRUN_INTF_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rxoerr_intf(&self) -> RXOERR_INTF_R {
RXOERR_INTF_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn rxmatch_intf(&self) -> RXMATCH_INTF_R {
RXMATCH_INTF_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rxfull_intf(&self) -> RXFULL_INTF_R {
RXFULL_INTF_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn txept_intf(&self) -> TXEPT_INTF_R {
TXEPT_INTF_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn fre_intf(&self) -> FRE_INTF_R {
FRE_INTF_R::new(((self.bits >> 7) & 1) != 0)
}
}
#[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_intstat](index.html) module"]
pub struct I2S_INTSTAT_SPEC;
impl crate::RegisterSpec for I2S_INTSTAT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [i2s_intstat::R](R) reader structure"]
impl crate::Readable for I2S_INTSTAT_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets I2S_INTSTAT to value 0"]
impl crate::Resettable for I2S_INTSTAT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "I2S_INTEN (rw) register accessor: an alias for `Reg<I2S_INTEN_SPEC>`"]
pub type I2S_INTEN = crate::Reg<i2s_inten::I2S_INTEN_SPEC>;
#[doc = "Interrupt Enable Register"]
pub mod i2s_inten {
#[doc = "Register `I2S_INTEN` reader"]
pub struct R(crate::R<I2S_INTEN_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<I2S_INTEN_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<I2S_INTEN_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<I2S_INTEN_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `I2S_INTEN` writer"]
pub struct W(crate::W<I2S_INTEN_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<I2S_INTEN_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<I2S_INTEN_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<I2S_INTEN_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TX_IEN` reader - "]
pub type TX_IEN_R = crate::BitReader<bool>;
#[doc = "Field `TX_IEN` writer - "]
pub type TX_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_INTEN_SPEC, bool, O>;
#[doc = "Field `RX_IEN` reader - "]
pub type RX_IEN_R = crate::BitReader<bool>;
#[doc = "Field `RX_IEN` writer - "]
pub type RX_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_INTEN_SPEC, bool, O>;
#[doc = "Field `UNDERRUN_IEN` reader - "]
pub type UNDERRUN_IEN_R = crate::BitReader<bool>;
#[doc = "Field `UNDERRUN_IEN` writer - "]
pub type UNDERRUN_IEN_W<'a, const O: u8> =
crate::BitWriter<'a, u32, I2S_INTEN_SPEC, bool, O>;
#[doc = "Field `RXOERR_IEN` reader - "]
pub type RXOERR_IEN_R = crate::BitReader<bool>;
#[doc = "Field `RXOERR_IEN` writer - "]
pub type RXOERR_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_INTEN_SPEC, bool, O>;
#[doc = "Field `RXMATCH_IEN` reader - "]
pub type RXMATCH_IEN_R = crate::BitReader<bool>;
#[doc = "Field `RXMATCH_IEN` writer - "]
pub type RXMATCH_IEN_W<'a, const O: u8> =
crate::BitWriter<'a, u32, I2S_INTEN_SPEC, bool, O>;
#[doc = "Field `RXFULL_IEN` reader - "]
pub type RXFULL_IEN_R = crate::BitReader<bool>;
#[doc = "Field `RXFULL_IEN` writer - "]
pub type RXFULL_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_INTEN_SPEC, bool, O>;
#[doc = "Field `TXEPT_IEN` reader - "]
pub type TXEPT_IEN_R = crate::BitReader<bool>;
#[doc = "Field `TXEPT_IEN` writer - "]
pub type TXEPT_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_INTEN_SPEC, bool, O>;
#[doc = "Field `FRE_IEN` reader - "]
pub type FRE_IEN_R = crate::BitReader<bool>;
#[doc = "Field `FRE_IEN` writer - "]
pub type FRE_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_INTEN_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn tx_ien(&self) -> TX_IEN_R {
TX_IEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rx_ien(&self) -> RX_IEN_R {
RX_IEN_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn underrun_ien(&self) -> UNDERRUN_IEN_R {
UNDERRUN_IEN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rxoerr_ien(&self) -> RXOERR_IEN_R {
RXOERR_IEN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn rxmatch_ien(&self) -> RXMATCH_IEN_R {
RXMATCH_IEN_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rxfull_ien(&self) -> RXFULL_IEN_R {
RXFULL_IEN_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn txept_ien(&self) -> TXEPT_IEN_R {
TXEPT_IEN_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn fre_ien(&self) -> FRE_IEN_R {
FRE_IEN_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn tx_ien(&mut self) -> TX_IEN_W<0> {
TX_IEN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn rx_ien(&mut self) -> RX_IEN_W<1> {
RX_IEN_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn underrun_ien(&mut self) -> UNDERRUN_IEN_W<2> {
UNDERRUN_IEN_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rxoerr_ien(&mut self) -> RXOERR_IEN_W<3> {
RXOERR_IEN_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn rxmatch_ien(&mut self) -> RXMATCH_IEN_W<4> {
RXMATCH_IEN_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rxfull_ien(&mut self) -> RXFULL_IEN_W<5> {
RXFULL_IEN_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn txept_ien(&mut self) -> TXEPT_IEN_W<6> {
TXEPT_IEN_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn fre_ien(&mut self) -> FRE_IEN_W<7> {
FRE_IEN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_inten](index.html) module"]
pub struct I2S_INTEN_SPEC;
impl crate::RegisterSpec for I2S_INTEN_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [i2s_inten::R](R) reader structure"]
impl crate::Readable for I2S_INTEN_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [i2s_inten::W](W) writer structure"]
impl crate::Writable for I2S_INTEN_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets I2S_INTEN to value 0"]
impl crate::Resettable for I2S_INTEN_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "I2S_INTCLR (w) register accessor: an alias for `Reg<I2S_INTCLR_SPEC>`"]
pub type I2S_INTCLR = crate::Reg<i2s_intclr::I2S_INTCLR_SPEC>;
#[doc = "interrupt clear register"]
pub mod i2s_intclr {
#[doc = "Register `I2S_INTCLR` writer"]
pub struct W(crate::W<I2S_INTCLR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<I2S_INTCLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<I2S_INTCLR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<I2S_INTCLR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TX_ICLR` writer - "]
pub type TX_ICLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_INTCLR_SPEC, bool, O>;
#[doc = "Field `RX_ICLR` writer - "]
pub type RX_ICLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_INTCLR_SPEC, bool, O>;
#[doc = "Field `UNDERRUN_ICLR` writer - "]
pub type UNDERRUN_ICLR_W<'a, const O: u8> =
crate::BitWriter<'a, u32, I2S_INTCLR_SPEC, bool, O>;
#[doc = "Field `RXOERR_ICLR` writer - "]
pub type RXOERR_ICLR_W<'a, const O: u8> =
crate::BitWriter<'a, u32, I2S_INTCLR_SPEC, bool, O>;
#[doc = "Field `RXMATCH_ICLR` writer - "]
pub type RXMATCH_ICLR_W<'a, const O: u8> =
crate::BitWriter<'a, u32, I2S_INTCLR_SPEC, bool, O>;
#[doc = "Field `RXFULL_ICLR` writer - "]
pub type RXFULL_ICLR_W<'a, const O: u8> =
crate::BitWriter<'a, u32, I2S_INTCLR_SPEC, bool, O>;
#[doc = "Field `TXEPT_ICLR` writer - "]
pub type TXEPT_ICLR_W<'a, const O: u8> =
crate::BitWriter<'a, u32, I2S_INTCLR_SPEC, bool, O>;
#[doc = "Field `FRE_ICLR` writer - "]
pub type FRE_ICLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_INTCLR_SPEC, bool, O>;
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn tx_iclr(&mut self) -> TX_ICLR_W<0> {
TX_ICLR_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn rx_iclr(&mut self) -> RX_ICLR_W<1> {
RX_ICLR_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn underrun_iclr(&mut self) -> UNDERRUN_ICLR_W<2> {
UNDERRUN_ICLR_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rxoerr_iclr(&mut self) -> RXOERR_ICLR_W<3> {
RXOERR_ICLR_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn rxmatch_iclr(&mut self) -> RXMATCH_ICLR_W<4> {
RXMATCH_ICLR_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rxfull_iclr(&mut self) -> RXFULL_ICLR_W<5> {
RXFULL_ICLR_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn txept_iclr(&mut self) -> TXEPT_ICLR_W<6> {
TXEPT_ICLR_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn fre_iclr(&mut self) -> FRE_ICLR_W<7> {
FRE_ICLR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "interrupt clear register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_intclr](index.html) module"]
pub struct I2S_INTCLR_SPEC;
impl crate::RegisterSpec for I2S_INTCLR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [i2s_intclr::W](W) writer structure"]
impl crate::Writable for I2S_INTCLR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets I2S_INTCLR to value 0"]
impl crate::Resettable for I2S_INTCLR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "I2S_GCTL (rw) register accessor: an alias for `Reg<I2S_GCTL_SPEC>`"]
pub type I2S_GCTL = crate::Reg<i2s_gctl::I2S_GCTL_SPEC>;
#[doc = "global control register"]
pub mod i2s_gctl {
#[doc = "Register `I2S_GCTL` reader"]
pub struct R(crate::R<I2S_GCTL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<I2S_GCTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<I2S_GCTL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<I2S_GCTL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `I2S_GCTL` writer"]
pub struct W(crate::W<I2S_GCTL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<I2S_GCTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<I2S_GCTL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<I2S_GCTL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SPIEN` reader - "]
pub type SPIEN_R = crate::BitReader<bool>;
#[doc = "Field `SPIEN` writer - "]
pub type SPIEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_GCTL_SPEC, bool, O>;
#[doc = "Field `INTEN` reader - "]
pub type INTEN_R = crate::BitReader<bool>;
#[doc = "Field `INTEN` writer - "]
pub type INTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_GCTL_SPEC, bool, O>;
#[doc = "Field `MODE` reader - "]
pub type MODE_R = crate::BitReader<bool>;
#[doc = "Field `MODE` writer - "]
pub type MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_GCTL_SPEC, bool, O>;
#[doc = "Field `TXEN` reader - "]
pub type TXEN_R = crate::BitReader<bool>;
#[doc = "Field `TXEN` writer - "]
pub type TXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_GCTL_SPEC, bool, O>;
#[doc = "Field `RXEN` reader - "]
pub type RXEN_R = crate::BitReader<bool>;
#[doc = "Field `RXEN` writer - "]
pub type RXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_GCTL_SPEC, bool, O>;
#[doc = "Field `DMAMODE` reader - "]
pub type DMAMODE_R = crate::BitReader<bool>;
#[doc = "Field `DMAMODE` writer - "]
pub type DMAMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_GCTL_SPEC, bool, O>;
#[doc = "Field `NSS` reader - "]
pub type NSS_R = crate::BitReader<bool>;
#[doc = "Field `NSS` writer - "]
pub type NSS_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_GCTL_SPEC, bool, O>;
#[doc = "Field `DW8_32` reader - "]
pub type DW8_32_R = crate::BitReader<bool>;
#[doc = "Field `DW8_32` writer - "]
pub type DW8_32_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_GCTL_SPEC, bool, O>;
#[doc = "Field `PAD_SEL` reader - "]
pub type PAD_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PAD_SEL` writer - "]
pub type PAD_SEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, I2S_GCTL_SPEC, u8, u8, 5, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn spien(&self) -> SPIEN_R {
SPIEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn inten(&self) -> INTEN_R {
INTEN_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn mode(&self) -> MODE_R {
MODE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn txen(&self) -> TXEN_R {
TXEN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn rxen(&self) -> RXEN_R {
RXEN_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn dmamode(&self) -> DMAMODE_R {
DMAMODE_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn nss(&self) -> NSS_R {
NSS_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn dw8_32(&self) -> DW8_32_R {
DW8_32_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 13:17"]
#[inline(always)]
pub fn pad_sel(&self) -> PAD_SEL_R {
PAD_SEL_R::new(((self.bits >> 13) & 0x1f) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn spien(&mut self) -> SPIEN_W<0> {
SPIEN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn inten(&mut self) -> INTEN_W<1> {
INTEN_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> MODE_W<2> {
MODE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn txen(&mut self) -> TXEN_W<3> {
TXEN_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn rxen(&mut self) -> RXEN_W<4> {
RXEN_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn dmamode(&mut self) -> DMAMODE_W<9> {
DMAMODE_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn nss(&mut self) -> NSS_W<10> {
NSS_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn dw8_32(&mut self) -> DW8_32_W<11> {
DW8_32_W::new(self)
}
#[doc = "Bits 13:17"]
#[inline(always)]
#[must_use]
pub fn pad_sel(&mut self) -> PAD_SEL_W<13> {
PAD_SEL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "global control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_gctl](index.html) module"]
pub struct I2S_GCTL_SPEC;
impl crate::RegisterSpec for I2S_GCTL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [i2s_gctl::R](R) reader structure"]
impl crate::Readable for I2S_GCTL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [i2s_gctl::W](W) writer structure"]
impl crate::Writable for I2S_GCTL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets I2S_GCTL to value 0x04"]
impl crate::Resettable for I2S_GCTL_SPEC {
const RESET_VALUE: Self::Ux = 0x04;
}
}
#[doc = "I2S_CCTL (rw) register accessor: an alias for `Reg<I2S_CCTL_SPEC>`"]
pub type I2S_CCTL = crate::Reg<i2s_cctl::I2S_CCTL_SPEC>;
#[doc = "General Control Register"]
pub mod i2s_cctl {
#[doc = "Register `I2S_CCTL` reader"]
pub struct R(crate::R<I2S_CCTL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<I2S_CCTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<I2S_CCTL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<I2S_CCTL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `I2S_CCTL` writer"]
pub struct W(crate::W<I2S_CCTL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<I2S_CCTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<I2S_CCTL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<I2S_CCTL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CPHA` reader - "]
pub type CPHA_R = crate::BitReader<bool>;
#[doc = "Field `CPHA` writer - "]
pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_CCTL_SPEC, bool, O>;
#[doc = "Field `CPOL` reader - "]
pub type CPOL_R = crate::BitReader<bool>;
#[doc = "Field `CPOL` writer - "]
pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_CCTL_SPEC, bool, O>;
#[doc = "Field `LSBFE` reader - "]
pub type LSBFE_R = crate::BitReader<bool>;
#[doc = "Field `LSBFE` writer - "]
pub type LSBFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_CCTL_SPEC, bool, O>;
#[doc = "Field `SPILEN` reader - "]
pub type SPILEN_R = crate::BitReader<bool>;
#[doc = "Field `SPILEN` writer - "]
pub type SPILEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_CCTL_SPEC, bool, O>;
#[doc = "Field `RXEDGE` reader - "]
pub type RXEDGE_R = crate::BitReader<bool>;
#[doc = "Field `RXEDGE` writer - "]
pub type RXEDGE_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_CCTL_SPEC, bool, O>;
#[doc = "Field `TXEDGE` reader - "]
pub type TXEDGE_R = crate::BitReader<bool>;
#[doc = "Field `TXEDGE` writer - "]
pub type TXEDGE_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_CCTL_SPEC, bool, O>;
#[doc = "Field `CPHASEL` reader - "]
pub type CPHASEL_R = crate::BitReader<bool>;
#[doc = "Field `CPHASEL` writer - "]
pub type CPHASEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_CCTL_SPEC, bool, O>;
#[doc = "Field `TISEL` reader - "]
pub type TISEL_R = crate::BitReader<bool>;
#[doc = "Field `TISEL` writer - "]
pub type TISEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_CCTL_SPEC, bool, O>;
#[doc = "Field `MRDECHG` reader - "]
pub type MRDECHG_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MRDECHG` writer - "]
pub type MRDECHG_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, I2S_CCTL_SPEC, u8, u8, 3, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn cpha(&self) -> CPHA_R {
CPHA_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn cpol(&self) -> CPOL_R {
CPOL_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn lsbfe(&self) -> LSBFE_R {
LSBFE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn spilen(&self) -> SPILEN_R {
SPILEN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn rxedge(&self) -> RXEDGE_R {
RXEDGE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn txedge(&self) -> TXEDGE_R {
TXEDGE_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn cphasel(&self) -> CPHASEL_R {
CPHASEL_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn tisel(&self) -> TISEL_R {
TISEL_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:10"]
#[inline(always)]
pub fn mrdechg(&self) -> MRDECHG_R {
MRDECHG_R::new(((self.bits >> 8) & 7) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn cpha(&mut self) -> CPHA_W<0> {
CPHA_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn cpol(&mut self) -> CPOL_W<1> {
CPOL_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn lsbfe(&mut self) -> LSBFE_W<2> {
LSBFE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn spilen(&mut self) -> SPILEN_W<3> {
SPILEN_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn rxedge(&mut self) -> RXEDGE_W<4> {
RXEDGE_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn txedge(&mut self) -> TXEDGE_W<5> {
TXEDGE_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn cphasel(&mut self) -> CPHASEL_W<6> {
CPHASEL_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn tisel(&mut self) -> TISEL_W<7> {
TISEL_W::new(self)
}
#[doc = "Bits 8:10"]
#[inline(always)]
#[must_use]
pub fn mrdechg(&mut self) -> MRDECHG_W<8> {
MRDECHG_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "General Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_cctl](index.html) module"]
pub struct I2S_CCTL_SPEC;
impl crate::RegisterSpec for I2S_CCTL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [i2s_cctl::R](R) reader structure"]
impl crate::Readable for I2S_CCTL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [i2s_cctl::W](W) writer structure"]
impl crate::Writable for I2S_CCTL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets I2S_CCTL to value 0x08"]
impl crate::Resettable for I2S_CCTL_SPEC {
const RESET_VALUE: Self::Ux = 0x08;
}
}
#[doc = "I2S_SPBRG (rw) register accessor: an alias for `Reg<I2S_SPBRG_SPEC>`"]
pub type I2S_SPBRG = crate::Reg<i2s_spbrg::I2S_SPBRG_SPEC>;
#[doc = "baud rate generator"]
pub mod i2s_spbrg {
#[doc = "Register `I2S_SPBRG` reader"]
pub struct R(crate::R<I2S_SPBRG_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<I2S_SPBRG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<I2S_SPBRG_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<I2S_SPBRG_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `I2S_SPBRG` writer"]
pub struct W(crate::W<I2S_SPBRG_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<I2S_SPBRG_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<I2S_SPBRG_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<I2S_SPBRG_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SPBRG` reader - "]
pub type SPBRG_R = crate::FieldReader<u16, u16>;
#[doc = "Field `SPBRG` writer - "]
pub type SPBRG_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, I2S_SPBRG_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn spbrg(&self) -> SPBRG_R {
SPBRG_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn spbrg(&mut self) -> SPBRG_W<0> {
SPBRG_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "baud rate generator\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_spbrg](index.html) module"]
pub struct I2S_SPBRG_SPEC;
impl crate::RegisterSpec for I2S_SPBRG_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [i2s_spbrg::R](R) reader structure"]
impl crate::Readable for I2S_SPBRG_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [i2s_spbrg::W](W) writer structure"]
impl crate::Writable for I2S_SPBRG_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets I2S_SPBRG to value 0x02"]
impl crate::Resettable for I2S_SPBRG_SPEC {
const RESET_VALUE: Self::Ux = 0x02;
}
}
#[doc = "I2S_RXDNR (rw) register accessor: an alias for `Reg<I2S_RXDNR_SPEC>`"]
pub type I2S_RXDNR = crate::Reg<i2s_rxdnr::I2S_RXDNR_SPEC>;
#[doc = "Receive data count register"]
pub mod i2s_rxdnr {
#[doc = "Register `I2S_RXDNR` reader"]
pub struct R(crate::R<I2S_RXDNR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<I2S_RXDNR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<I2S_RXDNR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<I2S_RXDNR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `I2S_RXDNR` writer"]
pub struct W(crate::W<I2S_RXDNR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<I2S_RXDNR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<I2S_RXDNR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<I2S_RXDNR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RXDNR` reader - "]
pub type RXDNR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `RXDNR` writer - "]
pub type RXDNR_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, I2S_RXDNR_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn rxdnr(&self) -> RXDNR_R {
RXDNR_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn rxdnr(&mut self) -> RXDNR_W<0> {
RXDNR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Receive data count register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_rxdnr](index.html) module"]
pub struct I2S_RXDNR_SPEC;
impl crate::RegisterSpec for I2S_RXDNR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [i2s_rxdnr::R](R) reader structure"]
impl crate::Readable for I2S_RXDNR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [i2s_rxdnr::W](W) writer structure"]
impl crate::Writable for I2S_RXDNR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets I2S_RXDNR to value 0x01"]
impl crate::Resettable for I2S_RXDNR_SPEC {
const RESET_VALUE: Self::Ux = 0x01;
}
}
#[doc = "I2S_NSSR (rw) register accessor: an alias for `Reg<I2S_NSSR_SPEC>`"]
pub type I2S_NSSR = crate::Reg<i2s_nssr::I2S_NSSR_SPEC>;
#[doc = "Slave Chip Select Register"]
pub mod i2s_nssr {
#[doc = "Register `I2S_NSSR` reader"]
pub struct R(crate::R<I2S_NSSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<I2S_NSSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<I2S_NSSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<I2S_NSSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `I2S_NSSR` writer"]
pub struct W(crate::W<I2S_NSSR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<I2S_NSSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<I2S_NSSR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<I2S_NSSR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `NSS` reader - "]
pub type NSS_R = crate::BitReader<bool>;
#[doc = "Field `NSS` writer - "]
pub type NSS_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_NSSR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn nss(&self) -> NSS_R {
NSS_R::new((self.bits & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn nss(&mut self) -> NSS_W<0> {
NSS_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Slave Chip Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_nssr](index.html) module"]
pub struct I2S_NSSR_SPEC;
impl crate::RegisterSpec for I2S_NSSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [i2s_nssr::R](R) reader structure"]
impl crate::Readable for I2S_NSSR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [i2s_nssr::W](W) writer structure"]
impl crate::Writable for I2S_NSSR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets I2S_NSSR to value 0xff"]
impl crate::Resettable for I2S_NSSR_SPEC {
const RESET_VALUE: Self::Ux = 0xff;
}
}
#[doc = "I2S_EXTCTL (rw) register accessor: an alias for `Reg<I2S_EXTCTL_SPEC>`"]
pub type I2S_EXTCTL = crate::Reg<i2s_extctl::I2S_EXTCTL_SPEC>;
#[doc = "data control register"]
pub mod i2s_extctl {
#[doc = "Register `I2S_EXTCTL` reader"]
pub struct R(crate::R<I2S_EXTCTL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<I2S_EXTCTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<I2S_EXTCTL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<I2S_EXTCTL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `I2S_EXTCTL` writer"]
pub struct W(crate::W<I2S_EXTCTL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<I2S_EXTCTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<I2S_EXTCTL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<I2S_EXTCTL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EXTLEN` reader - "]
pub type EXTLEN_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EXTLEN` writer - "]
pub type EXTLEN_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, I2S_EXTCTL_SPEC, u8, u8, 5, O>;
impl R {
#[doc = "Bits 0:4"]
#[inline(always)]
pub fn extlen(&self) -> EXTLEN_R {
EXTLEN_R::new((self.bits & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:4"]
#[inline(always)]
#[must_use]
pub fn extlen(&mut self) -> EXTLEN_W<0> {
EXTLEN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "data control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_extctl](index.html) module"]
pub struct I2S_EXTCTL_SPEC;
impl crate::RegisterSpec for I2S_EXTCTL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [i2s_extctl::R](R) reader structure"]
impl crate::Readable for I2S_EXTCTL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [i2s_extctl::W](W) writer structure"]
impl crate::Writable for I2S_EXTCTL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets I2S_EXTCTL to value 0x08"]
impl crate::Resettable for I2S_EXTCTL_SPEC {
const RESET_VALUE: Self::Ux = 0x08;
}
}
#[doc = "I2S_I2SCFGR (rw) register accessor: an alias for `Reg<I2S_I2SCFGR_SPEC>`"]
pub type I2S_I2SCFGR = crate::Reg<i2s_i2scfgr::I2S_I2SCFGR_SPEC>;
#[doc = "I2S configuration register"]
pub mod i2s_i2scfgr {
#[doc = "Register `I2S_I2SCFGR` reader"]
pub struct R(crate::R<I2S_I2SCFGR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<I2S_I2SCFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<I2S_I2SCFGR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<I2S_I2SCFGR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `I2S_I2SCFGR` writer"]
pub struct W(crate::W<I2S_I2SCFGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<I2S_I2SCFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<I2S_I2SCFGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<I2S_I2SCFGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CHLEN` reader - "]
pub type CHLEN_R = crate::BitReader<bool>;
#[doc = "Field `CHLEN` writer - "]
pub type CHLEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_I2SCFGR_SPEC, bool, O>;
#[doc = "Field `DATLEN` reader - "]
pub type DATLEN_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DATLEN` writer - "]
pub type DATLEN_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, I2S_I2SCFGR_SPEC, u8, u8, 2, O>;
#[doc = "Field `I2SSTD` reader - "]
pub type I2SSTD_R = crate::FieldReader<u8, u8>;
#[doc = "Field `I2SSTD` writer - "]
pub type I2SSTD_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, I2S_I2SCFGR_SPEC, u8, u8, 2, O>;
#[doc = "Field `PCMSYNC` reader - "]
pub type PCMSYNC_R = crate::BitReader<bool>;
#[doc = "Field `PCMSYNC` writer - "]
pub type PCMSYNC_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_I2SCFGR_SPEC, bool, O>;
#[doc = "Field `SPI_I2S` reader - "]
pub type SPI_I2S_R = crate::BitReader<bool>;
#[doc = "Field `SPI_I2S` writer - "]
pub type SPI_I2S_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_I2SCFGR_SPEC, bool, O>;
#[doc = "Field `MCKOE` reader - "]
pub type MCKOE_R = crate::BitReader<bool>;
#[doc = "Field `MCKOE` writer - "]
pub type MCKOE_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_I2SCFGR_SPEC, bool, O>;
#[doc = "Field `MCKSEL` reader - "]
pub type MCKSEL_R = crate::BitReader<bool>;
#[doc = "Field `MCKSEL` writer - "]
pub type MCKSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_I2SCFGR_SPEC, bool, O>;
#[doc = "Field `HFDSEL` reader - "]
pub type HFDSEL_R = crate::BitReader<bool>;
#[doc = "Field `HFDSEL` writer - "]
pub type HFDSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, I2S_I2SCFGR_SPEC, bool, O>;
#[doc = "Field `I2SDIV` reader - "]
pub type I2SDIV_R = crate::FieldReader<u16, u16>;
#[doc = "Field `I2SDIV` writer - "]
pub type I2SDIV_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, I2S_I2SCFGR_SPEC, u16, u16, 9, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn chlen(&self) -> CHLEN_R {
CHLEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2"]
#[inline(always)]
pub fn datlen(&self) -> DATLEN_R {
DATLEN_R::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bits 4:5"]
#[inline(always)]
pub fn i2sstd(&self) -> I2SSTD_R {
I2SSTD_R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn pcmsync(&self) -> PCMSYNC_R {
PCMSYNC_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn spi_i2s(&self) -> SPI_I2S_R {
SPI_I2S_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn mckoe(&self) -> MCKOE_R {
MCKOE_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn mcksel(&self) -> MCKSEL_R {
MCKSEL_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn hfdsel(&self) -> HFDSEL_R {
HFDSEL_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bits 16:24"]
#[inline(always)]
pub fn i2sdiv(&self) -> I2SDIV_R {
I2SDIV_R::new(((self.bits >> 16) & 0x01ff) as u16)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn chlen(&mut self) -> CHLEN_W<0> {
CHLEN_W::new(self)
}
#[doc = "Bits 1:2"]
#[inline(always)]
#[must_use]
pub fn datlen(&mut self) -> DATLEN_W<1> {
DATLEN_W::new(self)
}
#[doc = "Bits 4:5"]
#[inline(always)]
#[must_use]
pub fn i2sstd(&mut self) -> I2SSTD_W<4> {
I2SSTD_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn pcmsync(&mut self) -> PCMSYNC_W<6> {
PCMSYNC_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn spi_i2s(&mut self) -> SPI_I2S_W<10> {
SPI_I2S_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn mckoe(&mut self) -> MCKOE_W<11> {
MCKOE_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn mcksel(&mut self) -> MCKSEL_W<12> {
MCKSEL_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn hfdsel(&mut self) -> HFDSEL_W<13> {
HFDSEL_W::new(self)
}
#[doc = "Bits 16:24"]
#[inline(always)]
#[must_use]
pub fn i2sdiv(&mut self) -> I2SDIV_W<16> {
I2SDIV_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "I2S configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_i2scfgr](index.html) module"]
pub struct I2S_I2SCFGR_SPEC;
impl crate::RegisterSpec for I2S_I2SCFGR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [i2s_i2scfgr::R](R) reader structure"]
impl crate::Readable for I2S_I2SCFGR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [i2s_i2scfgr::W](W) writer structure"]
impl crate::Writable for I2S_I2SCFGR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets I2S_I2SCFGR to value 0x0001_0000"]
impl crate::Resettable for I2S_I2SCFGR_SPEC {
const RESET_VALUE: Self::Ux = 0x0001_0000;
}
}
}
#[doc = "SPI2"]
pub struct SPI2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for SPI2 {}
impl SPI2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const spi1::RegisterBlock = 0x4000_3800 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const spi1::RegisterBlock {
Self::PTR
}
}
impl Deref for SPI2 {
type Target = spi1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for SPI2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI2").finish()
}
}
#[doc = "SPI2"]
pub use self::spi1 as spi2;
#[doc = "SPI3"]
pub struct SPI3 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for SPI3 {}
impl SPI3 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const spi1::RegisterBlock = 0x4000_3c00 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const spi1::RegisterBlock {
Self::PTR
}
}
impl Deref for SPI3 {
type Target = spi1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for SPI3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SPI3").finish()
}
}
#[doc = "SPI3"]
pub use self::spi1 as spi3;
#[doc = "SYSCFG"]
pub struct SYSCFG {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for SYSCFG {}
impl SYSCFG {
#[doc = r"Pointer to the register block"]
pub const PTR: *const syscfg::RegisterBlock = 0x4001_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const syscfg::RegisterBlock {
Self::PTR
}
}
impl Deref for SYSCFG {
type Target = syscfg::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for SYSCFG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SYSCFG").finish()
}
}
#[doc = "SYSCFG"]
pub mod syscfg {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - SYSCFG Configuration Register"]
pub cfgr1: CFGR1,
_reserved1: [u8; 0x04],
#[doc = "0x08 - External Interrupt Configuration Register 1"]
pub exticr1: EXTICR1,
#[doc = "0x0c - External Interrupt Configuration Register 2"]
pub exticr2: EXTICR2,
#[doc = "0x10 - External Interrupt Configuration Register 3"]
pub exticr3: EXTICR3,
#[doc = "0x14 - External Interrupt Configuration Register 4"]
pub exticr4: EXTICR4,
#[doc = "0x18 - SYSCFG Configuration Register 2"]
pub cfgr2: CFGR2,
#[doc = "0x1c - Power Detect Configuration Status Register"]
pub pdetcsr: PDETCSR,
#[doc = "0x20 - VOSDLY configuration register"]
pub vosdly: VOSDLY,
#[doc = "0x24 - DAM remap register"]
pub dmarmp: DMARMP,
#[doc = "0x28 - Bus Priority Configuration Register"]
pub bus_pri: BUS_PRI,
}
#[doc = "CFGR1 (rw) register accessor: an alias for `Reg<CFGR1_SPEC>`"]
pub type CFGR1 = crate::Reg<cfgr1::CFGR1_SPEC>;
#[doc = "SYSCFG Configuration Register"]
pub mod cfgr1 {
#[doc = "Register `CFGR1` reader"]
pub struct R(crate::R<CFGR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CFGR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CFGR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CFGR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CFGR1` writer"]
pub struct W(crate::W<CFGR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CFGR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CFGR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CFGR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `USBFSVBUSOWDIS` reader - "]
pub type USBFSVBUSOWDIS_R = crate::BitReader<bool>;
#[doc = "Field `USBFSVBUSOWDIS` writer - "]
pub type USBFSVBUSOWDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `USBFSIDOWDIS` reader - "]
pub type USBFSIDOWDIS_R = crate::BitReader<bool>;
#[doc = "Field `USBFSIDOWDIS` writer - "]
pub type USBFSIDOWDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `USBFSVBUSORV` reader - "]
pub type USBFSVBUSORV_R = crate::BitReader<bool>;
#[doc = "Field `USBFSVBUSORV` writer - "]
pub type USBFSVBUSORV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `USBFSIDORV` reader - "]
pub type USBFSIDORV_R = crate::BitReader<bool>;
#[doc = "Field `USBFSIDORV` writer - "]
pub type USBFSIDORV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `CAN1_SPV` reader - "]
pub type CAN1_SPV_R = crate::BitReader<bool>;
#[doc = "Field `CAN1_SPV` writer - "]
pub type CAN1_SPV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `CAN1_TEST` reader - "]
pub type CAN1_TEST_R = crate::BitReader<bool>;
#[doc = "Field `CAN1_TEST` writer - "]
pub type CAN1_TEST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `CAN1_STOP` reader - "]
pub type CAN1_STOP_R = crate::BitReader<bool>;
#[doc = "Field `CAN1_STOP` writer - "]
pub type CAN1_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `CAN2_SPV` reader - "]
pub type CAN2_SPV_R = crate::BitReader<bool>;
#[doc = "Field `CAN2_SPV` writer - "]
pub type CAN2_SPV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `FCAN2_TEST` reader - "]
pub type FCAN2_TEST_R = crate::BitReader<bool>;
#[doc = "Field `FCAN2_TEST` writer - "]
pub type FCAN2_TEST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `CAN2_STOP` reader - "]
pub type CAN2_STOP_R = crate::BitReader<bool>;
#[doc = "Field `CAN2_STOP` writer - "]
pub type CAN2_STOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `FC_ODATAEN` reader - "]
pub type FC_ODATAEN_R = crate::BitReader<bool>;
#[doc = "Field `FC_ODATAEN` writer - "]
pub type FC_ODATAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR1_SPEC, bool, O>;
#[doc = "Field `FCMODESEL` reader - "]
pub type FCMODESEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `FCMODESEL` writer - "]
pub type FCMODESEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CFGR1_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn usbfsvbusowdis(&self) -> USBFSVBUSOWDIS_R {
USBFSVBUSOWDIS_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn usbfsidowdis(&self) -> USBFSIDOWDIS_R {
USBFSIDOWDIS_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn usbfsvbusorv(&self) -> USBFSVBUSORV_R {
USBFSVBUSORV_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn usbfsidorv(&self) -> USBFSIDORV_R {
USBFSIDORV_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn can1_spv(&self) -> CAN1_SPV_R {
CAN1_SPV_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn can1_test(&self) -> CAN1_TEST_R {
CAN1_TEST_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18"]
#[inline(always)]
pub fn can1_stop(&self) -> CAN1_STOP_R {
CAN1_STOP_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19"]
#[inline(always)]
pub fn can2_spv(&self) -> CAN2_SPV_R {
CAN2_SPV_R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn fcan2_test(&self) -> FCAN2_TEST_R {
FCAN2_TEST_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn can2_stop(&self) -> CAN2_STOP_R {
CAN2_STOP_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn fc_odataen(&self) -> FC_ODATAEN_R {
FC_ODATAEN_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bits 29:30"]
#[inline(always)]
pub fn fcmodesel(&self) -> FCMODESEL_R {
FCMODESEL_R::new(((self.bits >> 29) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn usbfsvbusowdis(&mut self) -> USBFSVBUSOWDIS_W<0> {
USBFSVBUSOWDIS_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn usbfsidowdis(&mut self) -> USBFSIDOWDIS_W<1> {
USBFSIDOWDIS_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn usbfsvbusorv(&mut self) -> USBFSVBUSORV_W<2> {
USBFSVBUSORV_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn usbfsidorv(&mut self) -> USBFSIDORV_W<3> {
USBFSIDORV_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn can1_spv(&mut self) -> CAN1_SPV_W<16> {
CAN1_SPV_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn can1_test(&mut self) -> CAN1_TEST_W<17> {
CAN1_TEST_W::new(self)
}
#[doc = "Bit 18"]
#[inline(always)]
#[must_use]
pub fn can1_stop(&mut self) -> CAN1_STOP_W<18> {
CAN1_STOP_W::new(self)
}
#[doc = "Bit 19"]
#[inline(always)]
#[must_use]
pub fn can2_spv(&mut self) -> CAN2_SPV_W<19> {
CAN2_SPV_W::new(self)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn fcan2_test(&mut self) -> FCAN2_TEST_W<20> {
FCAN2_TEST_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn can2_stop(&mut self) -> CAN2_STOP_W<21> {
CAN2_STOP_W::new(self)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn fc_odataen(&mut self) -> FC_ODATAEN_W<28> {
FC_ODATAEN_W::new(self)
}
#[doc = "Bits 29:30"]
#[inline(always)]
#[must_use]
pub fn fcmodesel(&mut self) -> FCMODESEL_W<29> {
FCMODESEL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "SYSCFG Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr1](index.html) module"]
pub struct CFGR1_SPEC;
impl crate::RegisterSpec for CFGR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cfgr1::R](R) reader structure"]
impl crate::Readable for CFGR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfgr1::W](W) writer structure"]
impl crate::Writable for CFGR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CFGR1 to value 0x2009_000b"]
impl crate::Resettable for CFGR1_SPEC {
const RESET_VALUE: Self::Ux = 0x2009_000b;
}
}
#[doc = "EXTICR1 (rw) register accessor: an alias for `Reg<EXTICR1_SPEC>`"]
pub type EXTICR1 = crate::Reg<exticr1::EXTICR1_SPEC>;
#[doc = "External Interrupt Configuration Register 1"]
pub mod exticr1 {
#[doc = "Register `EXTICR1` reader"]
pub struct R(crate::R<EXTICR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<EXTICR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<EXTICR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<EXTICR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `EXTICR1` writer"]
pub struct W(crate::W<EXTICR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<EXTICR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<EXTICR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<EXTICR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EXTIx` reader - "]
pub type EXTIX_R = crate::FieldReader<u16, u16>;
#[doc = "Field `EXTIx` writer - "]
pub type EXTIX_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, EXTICR1_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn extix(&self) -> EXTIX_R {
EXTIX_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn extix(&mut self) -> EXTIX_W<0> {
EXTIX_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "External Interrupt Configuration Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exticr1](index.html) module"]
pub struct EXTICR1_SPEC;
impl crate::RegisterSpec for EXTICR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [exticr1::R](R) reader structure"]
impl crate::Readable for EXTICR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [exticr1::W](W) writer structure"]
impl crate::Writable for EXTICR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets EXTICR1 to value 0"]
impl crate::Resettable for EXTICR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "EXTICR2 (rw) register accessor: an alias for `Reg<EXTICR2_SPEC>`"]
pub type EXTICR2 = crate::Reg<exticr2::EXTICR2_SPEC>;
#[doc = "External Interrupt Configuration Register 2"]
pub mod exticr2 {
#[doc = "Register `EXTICR2` reader"]
pub struct R(crate::R<EXTICR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<EXTICR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<EXTICR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<EXTICR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `EXTICR2` writer"]
pub struct W(crate::W<EXTICR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<EXTICR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<EXTICR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<EXTICR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EXTIx` reader - "]
pub type EXTIX_R = crate::FieldReader<u16, u16>;
#[doc = "Field `EXTIx` writer - "]
pub type EXTIX_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, EXTICR2_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn extix(&self) -> EXTIX_R {
EXTIX_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn extix(&mut self) -> EXTIX_W<0> {
EXTIX_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "External Interrupt Configuration Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exticr2](index.html) module"]
pub struct EXTICR2_SPEC;
impl crate::RegisterSpec for EXTICR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [exticr2::R](R) reader structure"]
impl crate::Readable for EXTICR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [exticr2::W](W) writer structure"]
impl crate::Writable for EXTICR2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets EXTICR2 to value 0"]
impl crate::Resettable for EXTICR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "EXTICR3 (rw) register accessor: an alias for `Reg<EXTICR3_SPEC>`"]
pub type EXTICR3 = crate::Reg<exticr3::EXTICR3_SPEC>;
#[doc = "External Interrupt Configuration Register 3"]
pub mod exticr3 {
#[doc = "Register `EXTICR3` reader"]
pub struct R(crate::R<EXTICR3_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<EXTICR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<EXTICR3_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<EXTICR3_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `EXTICR3` writer"]
pub struct W(crate::W<EXTICR3_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<EXTICR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<EXTICR3_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<EXTICR3_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EXTIx` reader - "]
pub type EXTIX_R = crate::FieldReader<u16, u16>;
#[doc = "Field `EXTIx` writer - "]
pub type EXTIX_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, EXTICR3_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn extix(&self) -> EXTIX_R {
EXTIX_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn extix(&mut self) -> EXTIX_W<0> {
EXTIX_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "External Interrupt Configuration Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exticr3](index.html) module"]
pub struct EXTICR3_SPEC;
impl crate::RegisterSpec for EXTICR3_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [exticr3::R](R) reader structure"]
impl crate::Readable for EXTICR3_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [exticr3::W](W) writer structure"]
impl crate::Writable for EXTICR3_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets EXTICR3 to value 0"]
impl crate::Resettable for EXTICR3_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "EXTICR4 (rw) register accessor: an alias for `Reg<EXTICR4_SPEC>`"]
pub type EXTICR4 = crate::Reg<exticr4::EXTICR4_SPEC>;
#[doc = "External Interrupt Configuration Register 4"]
pub mod exticr4 {
#[doc = "Register `EXTICR4` reader"]
pub struct R(crate::R<EXTICR4_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<EXTICR4_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<EXTICR4_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<EXTICR4_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `EXTICR4` writer"]
pub struct W(crate::W<EXTICR4_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<EXTICR4_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<EXTICR4_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<EXTICR4_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EXTIx` reader - "]
pub type EXTIX_R = crate::FieldReader<u16, u16>;
#[doc = "Field `EXTIx` writer - "]
pub type EXTIX_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, EXTICR4_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn extix(&self) -> EXTIX_R {
EXTIX_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn extix(&mut self) -> EXTIX_W<0> {
EXTIX_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "External Interrupt Configuration Register 4\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exticr4](index.html) module"]
pub struct EXTICR4_SPEC;
impl crate::RegisterSpec for EXTICR4_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [exticr4::R](R) reader structure"]
impl crate::Readable for EXTICR4_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [exticr4::W](W) writer structure"]
impl crate::Writable for EXTICR4_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets EXTICR4 to value 0"]
impl crate::Resettable for EXTICR4_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CFGR2 (rw) register accessor: an alias for `Reg<CFGR2_SPEC>`"]
pub type CFGR2 = crate::Reg<cfgr2::CFGR2_SPEC>;
#[doc = "SYSCFG Configuration Register 2"]
pub mod cfgr2 {
#[doc = "Register `CFGR2` reader"]
pub struct R(crate::R<CFGR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CFGR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CFGR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CFGR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CFGR2` writer"]
pub struct W(crate::W<CFGR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CFGR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CFGR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CFGR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `I2C1_MODE_SEL` reader - "]
pub type I2C1_MODE_SEL_R = crate::BitReader<bool>;
#[doc = "Field `I2C1_MODE_SEL` writer - "]
pub type I2C1_MODE_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
#[doc = "Field `I2C2_MODE_SEL` reader - "]
pub type I2C2_MODE_SEL_R = crate::BitReader<bool>;
#[doc = "Field `I2C2_MODE_SEL` writer - "]
pub type I2C2_MODE_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
#[doc = "Field `ENETMIIRMIISE` reader - "]
pub type ENETMIIRMIISE_R = crate::BitReader<bool>;
#[doc = "Field `ENETMIIRMIISE` writer - "]
pub type ENETMIIRMIISE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
#[doc = "Field `ENETSPDSEL` reader - "]
pub type ENETSPDSEL_R = crate::BitReader<bool>;
#[doc = "Field `ENETSPDSEL` writer - "]
pub type ENETSPDSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
#[doc = "Field `QSPI_AUTOIDLE_EN` reader - "]
pub type QSPI_AUTOIDLE_EN_R = crate::BitReader<bool>;
#[doc = "Field `QSPI_AUTOIDLE_EN` writer - "]
pub type QSPI_AUTOIDLE_EN_W<'a, const O: u8> =
crate::BitWriter<'a, u32, CFGR2_SPEC, bool, O>;
impl R {
#[doc = "Bit 16"]
#[inline(always)]
pub fn i2c1_mode_sel(&self) -> I2C1_MODE_SEL_R {
I2C1_MODE_SEL_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn i2c2_mode_sel(&self) -> I2C2_MODE_SEL_R {
I2C2_MODE_SEL_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn enetmiirmiise(&self) -> ENETMIIRMIISE_R {
ENETMIIRMIISE_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn enetspdsel(&self) -> ENETSPDSEL_R {
ENETSPDSEL_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 25"]
#[inline(always)]
pub fn qspi_autoidle_en(&self) -> QSPI_AUTOIDLE_EN_R {
QSPI_AUTOIDLE_EN_R::new(((self.bits >> 25) & 1) != 0)
}
}
impl W {
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn i2c1_mode_sel(&mut self) -> I2C1_MODE_SEL_W<16> {
I2C1_MODE_SEL_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn i2c2_mode_sel(&mut self) -> I2C2_MODE_SEL_W<17> {
I2C2_MODE_SEL_W::new(self)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn enetmiirmiise(&mut self) -> ENETMIIRMIISE_W<20> {
ENETMIIRMIISE_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn enetspdsel(&mut self) -> ENETSPDSEL_W<21> {
ENETSPDSEL_W::new(self)
}
#[doc = "Bit 25"]
#[inline(always)]
#[must_use]
pub fn qspi_autoidle_en(&mut self) -> QSPI_AUTOIDLE_EN_W<25> {
QSPI_AUTOIDLE_EN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "SYSCFG Configuration Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr2](index.html) module"]
pub struct CFGR2_SPEC;
impl crate::RegisterSpec for CFGR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cfgr2::R](R) reader structure"]
impl crate::Readable for CFGR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfgr2::W](W) writer structure"]
impl crate::Writable for CFGR2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CFGR2 to value 0"]
impl crate::Resettable for CFGR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PDETCSR (rw) register accessor: an alias for `Reg<PDETCSR_SPEC>`"]
pub type PDETCSR = crate::Reg<pdetcsr::PDETCSR_SPEC>;
#[doc = "Power Detect Configuration Status Register"]
pub mod pdetcsr {
#[doc = "Register `PDETCSR` reader"]
pub struct R(crate::R<PDETCSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PDETCSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PDETCSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PDETCSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PDETCSR` writer"]
pub struct W(crate::W<PDETCSR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PDETCSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PDETCSR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PDETCSR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PVDE` reader - "]
pub type PVDE_R = crate::BitReader<bool>;
#[doc = "Field `PVDE` writer - "]
pub type PVDE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDETCSR_SPEC, bool, O>;
#[doc = "Field `PLS` reader - "]
pub type PLS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PLS` writer - "]
pub type PLS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PDETCSR_SPEC, u8, u8, 4, O>;
#[doc = "Field `PVDO` reader - "]
pub type PVDO_R = crate::BitReader<bool>;
#[doc = "Field `VDTO` reader - "]
pub type VDTO_R = crate::BitReader<bool>;
#[doc = "Field `VDTE` reader - "]
pub type VDTE_R = crate::BitReader<bool>;
#[doc = "Field `VDTE` writer - "]
pub type VDTE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDETCSR_SPEC, bool, O>;
#[doc = "Field `VDTLS` reader - "]
pub type VDTLS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `VDTLS` writer - "]
pub type VDTLS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PDETCSR_SPEC, u8, u8, 2, O>;
#[doc = "Field `VBAT_DIV3_EN` reader - "]
pub type VBAT_DIV3_EN_R = crate::BitReader<bool>;
#[doc = "Field `VBAT_DIV3_EN` writer - "]
pub type VBAT_DIV3_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDETCSR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pvde(&self) -> PVDE_R {
PVDE_R::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:4"]
#[inline(always)]
pub fn pls(&self) -> PLS_R {
PLS_R::new(((self.bits >> 1) & 0x0f) as u8)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn pvdo(&self) -> PVDO_R {
PVDO_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn vdto(&self) -> VDTO_R {
VDTO_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn vdte(&self) -> VDTE_R {
VDTE_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bits 9:10"]
#[inline(always)]
pub fn vdtls(&self) -> VDTLS_R {
VDTLS_R::new(((self.bits >> 9) & 3) as u8)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn vbat_div3_en(&self) -> VBAT_DIV3_EN_R {
VBAT_DIV3_EN_R::new(((self.bits >> 11) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pvde(&mut self) -> PVDE_W<0> {
PVDE_W::new(self)
}
#[doc = "Bits 1:4"]
#[inline(always)]
#[must_use]
pub fn pls(&mut self) -> PLS_W<1> {
PLS_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn vdte(&mut self) -> VDTE_W<8> {
VDTE_W::new(self)
}
#[doc = "Bits 9:10"]
#[inline(always)]
#[must_use]
pub fn vdtls(&mut self) -> VDTLS_W<9> {
VDTLS_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn vbat_div3_en(&mut self) -> VBAT_DIV3_EN_W<11> {
VBAT_DIV3_EN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Power Detect Configuration Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdetcsr](index.html) module"]
pub struct PDETCSR_SPEC;
impl crate::RegisterSpec for PDETCSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [pdetcsr::R](R) reader structure"]
impl crate::Readable for PDETCSR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pdetcsr::W](W) writer structure"]
impl crate::Writable for PDETCSR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PDETCSR to value 0x06"]
impl crate::Resettable for PDETCSR_SPEC {
const RESET_VALUE: Self::Ux = 0x06;
}
}
#[doc = "VOSDLY (rw) register accessor: an alias for `Reg<VOSDLY_SPEC>`"]
pub type VOSDLY = crate::Reg<vosdly::VOSDLY_SPEC>;
#[doc = "VOSDLY configuration register"]
pub mod vosdly {
#[doc = "Register `VOSDLY` reader"]
pub struct R(crate::R<VOSDLY_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<VOSDLY_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<VOSDLY_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<VOSDLY_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `VOSDLY` writer"]
pub struct W(crate::W<VOSDLY_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<VOSDLY_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<VOSDLY_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<VOSDLY_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `VOSDLY_CNT` reader - "]
pub type VOSDLY_CNT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `VOSDLY_CNT` writer - "]
pub type VOSDLY_CNT_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, VOSDLY_SPEC, u16, u16, 10, O>;
impl R {
#[doc = "Bits 0:9"]
#[inline(always)]
pub fn vosdly_cnt(&self) -> VOSDLY_CNT_R {
VOSDLY_CNT_R::new((self.bits & 0x03ff) as u16)
}
}
impl W {
#[doc = "Bits 0:9"]
#[inline(always)]
#[must_use]
pub fn vosdly_cnt(&mut self) -> VOSDLY_CNT_W<0> {
VOSDLY_CNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "VOSDLY configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vosdly](index.html) module"]
pub struct VOSDLY_SPEC;
impl crate::RegisterSpec for VOSDLY_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [vosdly::R](R) reader structure"]
impl crate::Readable for VOSDLY_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [vosdly::W](W) writer structure"]
impl crate::Writable for VOSDLY_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets VOSDLY to value 0x01f4"]
impl crate::Resettable for VOSDLY_SPEC {
const RESET_VALUE: Self::Ux = 0x01f4;
}
}
#[doc = "DMARMP (rw) register accessor: an alias for `Reg<DMARMP_SPEC>`"]
pub type DMARMP = crate::Reg<dmarmp::DMARMP_SPEC>;
#[doc = "DAM remap register"]
pub mod dmarmp {
#[doc = "Register `DMARMP` reader"]
pub struct R(crate::R<DMARMP_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DMARMP_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DMARMP_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DMARMP_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DMARMP` writer"]
pub struct W(crate::W<DMARMP_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DMARMP_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DMARMP_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DMARMP_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TIM1_TRIG_RMP` reader - "]
pub type TIM1_TRIG_RMP_R = crate::BitReader<bool>;
#[doc = "Field `TIM1_TRIG_RMP` writer - "]
pub type TIM1_TRIG_RMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
#[doc = "Field `TIM1_COM_RMP` reader - "]
pub type TIM1_COM_RMP_R = crate::BitReader<bool>;
#[doc = "Field `TIM1_COM_RMP` writer - "]
pub type TIM1_COM_RMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
#[doc = "Field `TIM2_UP_RMP` reader - "]
pub type TIM2_UP_RMP_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TIM2_UP_RMP` writer - "]
pub type TIM2_UP_RMP_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, DMARMP_SPEC, u8, u8, 2, O>;
#[doc = "Field `TIM2_CC3_RMP` reader - "]
pub type TIM2_CC3_RMP_R = crate::BitReader<bool>;
#[doc = "Field `TIM2_CC3_RMP` writer - "]
pub type TIM2_CC3_RMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
#[doc = "Field `TIM2_CC4_RMP` reader - "]
pub type TIM2_CC4_RMP_R = crate::BitReader<bool>;
#[doc = "Field `TIM2_CC4_RMP` writer - "]
pub type TIM2_CC4_RMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
#[doc = "Field `TIM5_UP_RMP` reader - "]
pub type TIM5_UP_RMP_R = crate::BitReader<bool>;
#[doc = "Field `TIM5_UP_RMP` writer - "]
pub type TIM5_UP_RMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
#[doc = "Field `TIM6_UP_RMP` reader - "]
pub type TIM6_UP_RMP_R = crate::BitReader<bool>;
#[doc = "Field `TIM6_UP_RMP` writer - "]
pub type TIM6_UP_RMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
#[doc = "Field `TIM7_UP_RMP` reader - "]
pub type TIM7_UP_RMP_R = crate::BitReader<bool>;
#[doc = "Field `TIM7_UP_RMP` writer - "]
pub type TIM7_UP_RMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
#[doc = "Field `TIM8_TRIG_RMP` reader - "]
pub type TIM8_TRIG_RMP_R = crate::BitReader<bool>;
#[doc = "Field `TIM8_TRIG_RMP` writer - "]
pub type TIM8_TRIG_RMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
#[doc = "Field `TIM8_UP_RMP` reader - "]
pub type TIM8_UP_RMP_R = crate::BitReader<bool>;
#[doc = "Field `TIM8_UP_RMP` writer - "]
pub type TIM8_UP_RMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
#[doc = "Field `TIM8_COM_RMP` reader - "]
pub type TIM8_COM_RMP_R = crate::BitReader<bool>;
#[doc = "Field `TIM8_COM_RMP` writer - "]
pub type TIM8_COM_RMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
#[doc = "Field `UART4_RX_RMP` reader - "]
pub type UART4_RX_RMP_R = crate::BitReader<bool>;
#[doc = "Field `UART4_RX_RMP` writer - "]
pub type UART4_RX_RMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
#[doc = "Field `UART4_TX_RMP` reader - "]
pub type UART4_TX_RMP_R = crate::BitReader<bool>;
#[doc = "Field `UART4_TX_RMP` writer - "]
pub type UART4_TX_RMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
#[doc = "Field `UART6_RX_RMP` reader - "]
pub type UART6_RX_RMP_R = crate::BitReader<bool>;
#[doc = "Field `UART6_RX_RMP` writer - "]
pub type UART6_RX_RMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
#[doc = "Field `UART6_TX_RMP` reader - "]
pub type UART6_TX_RMP_R = crate::BitReader<bool>;
#[doc = "Field `UART6_TX_RMP` writer - "]
pub type UART6_TX_RMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
#[doc = "Field `UART7_RX_TMP` reader - "]
pub type UART7_RX_TMP_R = crate::BitReader<bool>;
#[doc = "Field `UART7_RX_TMP` writer - "]
pub type UART7_RX_TMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
#[doc = "Field `UART7_TX_RMP` reader - "]
pub type UART7_TX_RMP_R = crate::BitReader<bool>;
#[doc = "Field `UART7_TX_RMP` writer - "]
pub type UART7_TX_RMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
#[doc = "Field `DAC_CH1_RMP` reader - "]
pub type DAC_CH1_RMP_R = crate::BitReader<bool>;
#[doc = "Field `DAC_CH1_RMP` writer - "]
pub type DAC_CH1_RMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
#[doc = "Field `DAC_CH2_RMP` reader - "]
pub type DAC_CH2_RMP_R = crate::BitReader<bool>;
#[doc = "Field `DAC_CH2_RMP` writer - "]
pub type DAC_CH2_RMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMARMP_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn tim1_trig_rmp(&self) -> TIM1_TRIG_RMP_R {
TIM1_TRIG_RMP_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn tim1_com_rmp(&self) -> TIM1_COM_RMP_R {
TIM1_COM_RMP_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:3"]
#[inline(always)]
pub fn tim2_up_rmp(&self) -> TIM2_UP_RMP_R {
TIM2_UP_RMP_R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn tim2_cc3_rmp(&self) -> TIM2_CC3_RMP_R {
TIM2_CC3_RMP_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn tim2_cc4_rmp(&self) -> TIM2_CC4_RMP_R {
TIM2_CC4_RMP_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn tim5_up_rmp(&self) -> TIM5_UP_RMP_R {
TIM5_UP_RMP_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn tim6_up_rmp(&self) -> TIM6_UP_RMP_R {
TIM6_UP_RMP_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn tim7_up_rmp(&self) -> TIM7_UP_RMP_R {
TIM7_UP_RMP_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn tim8_trig_rmp(&self) -> TIM8_TRIG_RMP_R {
TIM8_TRIG_RMP_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn tim8_up_rmp(&self) -> TIM8_UP_RMP_R {
TIM8_UP_RMP_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn tim8_com_rmp(&self) -> TIM8_COM_RMP_R {
TIM8_COM_RMP_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn uart4_rx_rmp(&self) -> UART4_RX_RMP_R {
UART4_RX_RMP_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn uart4_tx_rmp(&self) -> UART4_TX_RMP_R {
UART4_TX_RMP_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 20"]
#[inline(always)]
pub fn uart6_rx_rmp(&self) -> UART6_RX_RMP_R {
UART6_RX_RMP_R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21"]
#[inline(always)]
pub fn uart6_tx_rmp(&self) -> UART6_TX_RMP_R {
UART6_TX_RMP_R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22"]
#[inline(always)]
pub fn uart7_rx_tmp(&self) -> UART7_RX_TMP_R {
UART7_RX_TMP_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23"]
#[inline(always)]
pub fn uart7_tx_rmp(&self) -> UART7_TX_RMP_R {
UART7_TX_RMP_R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 28"]
#[inline(always)]
pub fn dac_ch1_rmp(&self) -> DAC_CH1_RMP_R {
DAC_CH1_RMP_R::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29"]
#[inline(always)]
pub fn dac_ch2_rmp(&self) -> DAC_CH2_RMP_R {
DAC_CH2_RMP_R::new(((self.bits >> 29) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn tim1_trig_rmp(&mut self) -> TIM1_TRIG_RMP_W<0> {
TIM1_TRIG_RMP_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn tim1_com_rmp(&mut self) -> TIM1_COM_RMP_W<1> {
TIM1_COM_RMP_W::new(self)
}
#[doc = "Bits 2:3"]
#[inline(always)]
#[must_use]
pub fn tim2_up_rmp(&mut self) -> TIM2_UP_RMP_W<2> {
TIM2_UP_RMP_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn tim2_cc3_rmp(&mut self) -> TIM2_CC3_RMP_W<4> {
TIM2_CC3_RMP_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn tim2_cc4_rmp(&mut self) -> TIM2_CC4_RMP_W<5> {
TIM2_CC4_RMP_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn tim5_up_rmp(&mut self) -> TIM5_UP_RMP_W<8> {
TIM5_UP_RMP_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn tim6_up_rmp(&mut self) -> TIM6_UP_RMP_W<10> {
TIM6_UP_RMP_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn tim7_up_rmp(&mut self) -> TIM7_UP_RMP_W<12> {
TIM7_UP_RMP_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn tim8_trig_rmp(&mut self) -> TIM8_TRIG_RMP_W<13> {
TIM8_TRIG_RMP_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn tim8_up_rmp(&mut self) -> TIM8_UP_RMP_W<14> {
TIM8_UP_RMP_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn tim8_com_rmp(&mut self) -> TIM8_COM_RMP_W<15> {
TIM8_COM_RMP_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn uart4_rx_rmp(&mut self) -> UART4_RX_RMP_W<16> {
UART4_RX_RMP_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn uart4_tx_rmp(&mut self) -> UART4_TX_RMP_W<17> {
UART4_TX_RMP_W::new(self)
}
#[doc = "Bit 20"]
#[inline(always)]
#[must_use]
pub fn uart6_rx_rmp(&mut self) -> UART6_RX_RMP_W<20> {
UART6_RX_RMP_W::new(self)
}
#[doc = "Bit 21"]
#[inline(always)]
#[must_use]
pub fn uart6_tx_rmp(&mut self) -> UART6_TX_RMP_W<21> {
UART6_TX_RMP_W::new(self)
}
#[doc = "Bit 22"]
#[inline(always)]
#[must_use]
pub fn uart7_rx_tmp(&mut self) -> UART7_RX_TMP_W<22> {
UART7_RX_TMP_W::new(self)
}
#[doc = "Bit 23"]
#[inline(always)]
#[must_use]
pub fn uart7_tx_rmp(&mut self) -> UART7_TX_RMP_W<23> {
UART7_TX_RMP_W::new(self)
}
#[doc = "Bit 28"]
#[inline(always)]
#[must_use]
pub fn dac_ch1_rmp(&mut self) -> DAC_CH1_RMP_W<28> {
DAC_CH1_RMP_W::new(self)
}
#[doc = "Bit 29"]
#[inline(always)]
#[must_use]
pub fn dac_ch2_rmp(&mut self) -> DAC_CH2_RMP_W<29> {
DAC_CH2_RMP_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DAM remap register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmarmp](index.html) module"]
pub struct DMARMP_SPEC;
impl crate::RegisterSpec for DMARMP_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dmarmp::R](R) reader structure"]
impl crate::Readable for DMARMP_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dmarmp::W](W) writer structure"]
impl crate::Writable for DMARMP_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DMARMP to value 0"]
impl crate::Resettable for DMARMP_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "BUS_PRI (rw) register accessor: an alias for `Reg<BUS_PRI_SPEC>`"]
pub type BUS_PRI = crate::Reg<bus_pri::BUS_PRI_SPEC>;
#[doc = "Bus Priority Configuration Register"]
pub mod bus_pri {
#[doc = "Register `BUS_PRI` reader"]
pub struct R(crate::R<BUS_PRI_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<BUS_PRI_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<BUS_PRI_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<BUS_PRI_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `BUS_PRI` writer"]
pub struct W(crate::W<BUS_PRI_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<BUS_PRI_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<BUS_PRI_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<BUS_PRI_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PRI_M1` reader - "]
pub type PRI_M1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PRI_M1` writer - "]
pub type PRI_M1_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, BUS_PRI_SPEC, u8, u8, 3, O>;
#[doc = "Field `PRI_M2` reader - "]
pub type PRI_M2_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PRI_M2` writer - "]
pub type PRI_M2_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, BUS_PRI_SPEC, u8, u8, 3, O>;
#[doc = "Field `PRI_M3` reader - "]
pub type PRI_M3_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PRI_M3` writer - "]
pub type PRI_M3_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, BUS_PRI_SPEC, u8, u8, 3, O>;
#[doc = "Field `PRI_M4` reader - "]
pub type PRI_M4_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PRI_M4` writer - "]
pub type PRI_M4_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, BUS_PRI_SPEC, u8, u8, 3, O>;
#[doc = "Field `PRI_M5` reader - "]
pub type PRI_M5_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PRI_M5` writer - "]
pub type PRI_M5_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, BUS_PRI_SPEC, u8, u8, 3, O>;
#[doc = "Field `PRI_M6` reader - "]
pub type PRI_M6_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PRI_M6` writer - "]
pub type PRI_M6_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, BUS_PRI_SPEC, u8, u8, 3, O>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn pri_m1(&self) -> PRI_M1_R {
PRI_M1_R::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:5"]
#[inline(always)]
pub fn pri_m2(&self) -> PRI_M2_R {
PRI_M2_R::new(((self.bits >> 3) & 7) as u8)
}
#[doc = "Bits 6:8"]
#[inline(always)]
pub fn pri_m3(&self) -> PRI_M3_R {
PRI_M3_R::new(((self.bits >> 6) & 7) as u8)
}
#[doc = "Bits 9:11"]
#[inline(always)]
pub fn pri_m4(&self) -> PRI_M4_R {
PRI_M4_R::new(((self.bits >> 9) & 7) as u8)
}
#[doc = "Bits 12:14"]
#[inline(always)]
pub fn pri_m5(&self) -> PRI_M5_R {
PRI_M5_R::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bits 15:17"]
#[inline(always)]
pub fn pri_m6(&self) -> PRI_M6_R {
PRI_M6_R::new(((self.bits >> 15) & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:2"]
#[inline(always)]
#[must_use]
pub fn pri_m1(&mut self) -> PRI_M1_W<0> {
PRI_M1_W::new(self)
}
#[doc = "Bits 3:5"]
#[inline(always)]
#[must_use]
pub fn pri_m2(&mut self) -> PRI_M2_W<3> {
PRI_M2_W::new(self)
}
#[doc = "Bits 6:8"]
#[inline(always)]
#[must_use]
pub fn pri_m3(&mut self) -> PRI_M3_W<6> {
PRI_M3_W::new(self)
}
#[doc = "Bits 9:11"]
#[inline(always)]
#[must_use]
pub fn pri_m4(&mut self) -> PRI_M4_W<9> {
PRI_M4_W::new(self)
}
#[doc = "Bits 12:14"]
#[inline(always)]
#[must_use]
pub fn pri_m5(&mut self) -> PRI_M5_W<12> {
PRI_M5_W::new(self)
}
#[doc = "Bits 15:17"]
#[inline(always)]
#[must_use]
pub fn pri_m6(&mut self) -> PRI_M6_W<15> {
PRI_M6_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Bus Priority Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bus_pri](index.html) module"]
pub struct BUS_PRI_SPEC;
impl crate::RegisterSpec for BUS_PRI_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [bus_pri::R](R) reader structure"]
impl crate::Readable for BUS_PRI_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [bus_pri::W](W) writer structure"]
impl crate::Writable for BUS_PRI_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets BUS_PRI to value 0x0002_8853"]
impl crate::Resettable for BUS_PRI_SPEC {
const RESET_VALUE: Self::Ux = 0x0002_8853;
}
}
}
#[doc = "TIM1"]
pub struct TIM1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIM1 {}
impl TIM1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const tim1::RegisterBlock = 0x4001_2c00 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const tim1::RegisterBlock {
Self::PTR
}
}
impl Deref for TIM1 {
type Target = tim1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for TIM1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM1").finish()
}
}
#[doc = "TIM1"]
pub mod tim1 {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Control Register 1"]
pub cr1: CR1,
#[doc = "0x04 - Control Register 2"]
pub cr2: CR2,
#[doc = "0x08 - Slave Mode Control Register"]
pub smcr: SMCR,
#[doc = "0x0c - DMA/Interrupt Enable Register"]
pub dier: DIER,
#[doc = "0x10 - status register"]
pub sr: SR,
#[doc = "0x14 - event generation register"]
pub egr: EGR,
_reserved_6_ccmr1: [u8; 0x04],
_reserved_7_ccmr2: [u8; 0x04],
#[doc = "0x20 - Capture/Compare Enable Register"]
pub ccer: CCER,
#[doc = "0x24 - counter"]
pub cnt: CNT,
#[doc = "0x28 - Prescaler"]
pub psc: PSC,
#[doc = "0x2c - autoload register"]
pub arr: ARR,
#[doc = "0x30 - Repeat count register"]
pub rcr: RCR,
#[doc = "0x34 - Capture/Compare Register 1"]
pub ccr1: CCR1,
#[doc = "0x38 - Capture/Compare Register 1"]
pub ccr2: CCR2,
#[doc = "0x3c - Capture/Compare Register 1"]
pub ccr3: CCR3,
#[doc = "0x40 - Capture/Compare Register 1"]
pub ccr4: CCR4,
#[doc = "0x44 - Brake and Deadband Registers"]
pub bdtr: BDTR,
#[doc = "0x48 - DMA Control Register"]
pub dcr: DCR,
#[doc = "0x4c - DMA address for continuous mode"]
pub dmar: DMAR,
_reserved20: [u8; 0x04],
#[doc = "0x54 - Capture/Compare Mode Register 3"]
pub ccmr3: CCMR3,
#[doc = "0x58 - Capture/Compare Register 5"]
pub ccr5: CCR5,
#[doc = "0x5c - PWM phase shift/DMA repeat update request enable register"]
pub pder: PDER,
#[doc = "0x60 - PWM Phase Shift Down Count Capture/Compare Register"]
pub ccr1fall: CCR1FALL,
#[doc = "0x64 - PWM Phase Shift Down Count Capture/Compare Register"]
pub ccr2fall: CCR2FALL,
#[doc = "0x68 - PWM Phase Shift Down Count Capture/Compare Register"]
pub ccr3fall: CCR3FALL,
#[doc = "0x6c - PWM Phase Shift Down Count Capture/Compare Register"]
pub ccr4fall: CCR4FALL,
#[doc = "0x70 - PWM Phase Shift Down Count Capture/Compare Register"]
pub ccr5fall: CCR5FALL,
#[doc = "0x74 - brake input filter register"]
pub bkinf: BKINF,
}
impl RegisterBlock {
#[doc = "0x18 - Capture/Compare Mode Register 2"]
#[inline(always)]
pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
unsafe { &*(self as *const Self).cast::<u8>().add(24usize).cast() }
}
#[doc = "0x18 - Capture/Compare Mode Register 1"]
#[inline(always)]
pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
unsafe { &*(self as *const Self).cast::<u8>().add(24usize).cast() }
}
#[doc = "0x1c - Capture/Compare Mode Register 2"]
#[inline(always)]
pub const fn ccmr2_input(&self) -> &CCMR2_INPUT {
unsafe { &*(self as *const Self).cast::<u8>().add(28usize).cast() }
}
#[doc = "0x1c - Capture/Compare Mode Register 1"]
#[inline(always)]
pub const fn ccmr2_output(&self) -> &CCMR2_OUTPUT {
unsafe { &*(self as *const Self).cast::<u8>().add(28usize).cast() }
}
}
#[doc = "CR1 (rw) register accessor: an alias for `Reg<CR1_SPEC>`"]
pub type CR1 = crate::Reg<cr1::CR1_SPEC>;
#[doc = "Control Register 1"]
pub mod cr1 {
#[doc = "Register `CR1` reader"]
pub struct R(crate::R<CR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR1` writer"]
pub struct W(crate::W<CR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CEN` reader - "]
pub type CEN_R = crate::BitReader<bool>;
#[doc = "Field `CEN` writer - "]
pub type CEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `UDIS` reader - "]
pub type UDIS_R = crate::BitReader<bool>;
#[doc = "Field `UDIS` writer - "]
pub type UDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `URS` reader - "]
pub type URS_R = crate::BitReader<bool>;
#[doc = "Field `URS` writer - "]
pub type URS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `OPM` reader - "]
pub type OPM_R = crate::BitReader<bool>;
#[doc = "Field `OPM` writer - "]
pub type OPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `DIR` reader - "]
pub type DIR_R = crate::BitReader<bool>;
#[doc = "Field `DIR` writer - "]
pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `CMS` reader - "]
pub type CMS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CMS` writer - "]
pub type CMS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR1_SPEC, u8, u8, 2, O>;
#[doc = "Field `ARPE` reader - "]
pub type ARPE_R = crate::BitReader<bool>;
#[doc = "Field `ARPE` writer - "]
pub type ARPE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `CKD` reader - "]
pub type CKD_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CKD` writer - "]
pub type CKD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR1_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn cen(&self) -> CEN_R {
CEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn udis(&self) -> UDIS_R {
UDIS_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn urs(&self) -> URS_R {
URS_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn opm(&self) -> OPM_R {
OPM_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn dir(&self) -> DIR_R {
DIR_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6"]
#[inline(always)]
pub fn cms(&self) -> CMS_R {
CMS_R::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn arpe(&self) -> ARPE_R {
ARPE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn ckd(&self) -> CKD_R {
CKD_R::new(((self.bits >> 8) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn cen(&mut self) -> CEN_W<0> {
CEN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn udis(&mut self) -> UDIS_W<1> {
UDIS_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn urs(&mut self) -> URS_W<2> {
URS_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn opm(&mut self) -> OPM_W<3> {
OPM_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DIR_W<4> {
DIR_W::new(self)
}
#[doc = "Bits 5:6"]
#[inline(always)]
#[must_use]
pub fn cms(&mut self) -> CMS_W<5> {
CMS_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn arpe(&mut self) -> ARPE_W<7> {
ARPE_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn ckd(&mut self) -> CKD_W<8> {
CKD_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr1](index.html) module"]
pub struct CR1_SPEC;
impl crate::RegisterSpec for CR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr1::R](R) reader structure"]
impl crate::Readable for CR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr1::W](W) writer structure"]
impl crate::Writable for CR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for CR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CR2 (rw) register accessor: an alias for `Reg<CR2_SPEC>`"]
pub type CR2 = crate::Reg<cr2::CR2_SPEC>;
#[doc = "Control Register 2"]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub struct R(crate::R<CR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR2` writer"]
pub struct W(crate::W<CR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CCPC` reader - "]
pub type CCPC_R = crate::BitReader<bool>;
#[doc = "Field `CCPC` writer - "]
pub type CCPC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
#[doc = "Field `CCUS` reader - "]
pub type CCUS_R = crate::BitReader<bool>;
#[doc = "Field `CCUS` writer - "]
pub type CCUS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
#[doc = "Field `CCDS` reader - "]
pub type CCDS_R = crate::BitReader<bool>;
#[doc = "Field `CCDS` writer - "]
pub type CCDS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
#[doc = "Field `MMS` reader - "]
pub type MMS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MMS` writer - "]
pub type MMS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR2_SPEC, u8, u8, 3, O>;
#[doc = "Field `TI1S` reader - "]
pub type TI1S_R = crate::BitReader<bool>;
#[doc = "Field `TI1S` writer - "]
pub type TI1S_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
#[doc = "Field `OIS1` reader - "]
pub type OIS1_R = crate::BitReader<bool>;
#[doc = "Field `OIS1` writer - "]
pub type OIS1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
#[doc = "Field `OIS1N` reader - "]
pub type OIS1N_R = crate::BitReader<bool>;
#[doc = "Field `OIS1N` writer - "]
pub type OIS1N_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
#[doc = "Field `OIS2` reader - "]
pub type OIS2_R = crate::BitReader<bool>;
#[doc = "Field `OIS2` writer - "]
pub type OIS2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
#[doc = "Field `OIS2N` reader - "]
pub type OIS2N_R = crate::BitReader<bool>;
#[doc = "Field `OIS2N` writer - "]
pub type OIS2N_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
#[doc = "Field `OIS3` reader - "]
pub type OIS3_R = crate::BitReader<bool>;
#[doc = "Field `OIS3` writer - "]
pub type OIS3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
#[doc = "Field `OIS3N` reader - "]
pub type OIS3N_R = crate::BitReader<bool>;
#[doc = "Field `OIS3N` writer - "]
pub type OIS3N_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
#[doc = "Field `OIS4` reader - "]
pub type OIS4_R = crate::BitReader<bool>;
#[doc = "Field `OIS4` writer - "]
pub type OIS4_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
#[doc = "Field `OIS4N` reader - "]
pub type OIS4N_R = crate::BitReader<bool>;
#[doc = "Field `OIS4N` writer - "]
pub type OIS4N_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn ccpc(&self) -> CCPC_R {
CCPC_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn ccus(&self) -> CCUS_R {
CCUS_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn ccds(&self) -> CCDS_R {
CCDS_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn mms(&self) -> MMS_R {
MMS_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn ti1s(&self) -> TI1S_R {
TI1S_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn ois1(&self) -> OIS1_R {
OIS1_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ois1n(&self) -> OIS1N_R {
OIS1N_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn ois2(&self) -> OIS2_R {
OIS2_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn ois2n(&self) -> OIS2N_R {
OIS2N_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn ois3(&self) -> OIS3_R {
OIS3_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn ois3n(&self) -> OIS3N_R {
OIS3N_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn ois4(&self) -> OIS4_R {
OIS4_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn ois4n(&self) -> OIS4N_R {
OIS4N_R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn ccpc(&mut self) -> CCPC_W<0> {
CCPC_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn ccus(&mut self) -> CCUS_W<2> {
CCUS_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn ccds(&mut self) -> CCDS_W<3> {
CCDS_W::new(self)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn mms(&mut self) -> MMS_W<4> {
MMS_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn ti1s(&mut self) -> TI1S_W<7> {
TI1S_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn ois1(&mut self) -> OIS1_W<8> {
OIS1_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ois1n(&mut self) -> OIS1N_W<9> {
OIS1N_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn ois2(&mut self) -> OIS2_W<10> {
OIS2_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn ois2n(&mut self) -> OIS2N_W<11> {
OIS2N_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn ois3(&mut self) -> OIS3_W<12> {
OIS3_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn ois3n(&mut self) -> OIS3N_W<13> {
OIS3N_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn ois4(&mut self) -> OIS4_W<14> {
OIS4_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn ois4n(&mut self) -> OIS4N_W<15> {
OIS4N_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Control Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr2](index.html) module"]
pub struct CR2_SPEC;
impl crate::RegisterSpec for CR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr2::R](R) reader structure"]
impl crate::Readable for CR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr2::W](W) writer structure"]
impl crate::Writable for CR2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for CR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SMCR (rw) register accessor: an alias for `Reg<SMCR_SPEC>`"]
pub type SMCR = crate::Reg<smcr::SMCR_SPEC>;
#[doc = "Slave Mode Control Register"]
pub mod smcr {
#[doc = "Register `SMCR` reader"]
pub struct R(crate::R<SMCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SMCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SMCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SMCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SMCR` writer"]
pub struct W(crate::W<SMCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SMCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SMCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SMCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SMS` reader - "]
pub type SMS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMS` writer - "]
pub type SMS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SMCR_SPEC, u8, u8, 3, O>;
#[doc = "Field `OCCS` reader - "]
pub type OCCS_R = crate::BitReader<bool>;
#[doc = "Field `OCCS` writer - "]
pub type OCCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMCR_SPEC, bool, O>;
#[doc = "Field `TS` reader - "]
pub type TS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TS` writer - "]
pub type TS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SMCR_SPEC, u8, u8, 3, O>;
#[doc = "Field `MSM` reader - "]
pub type MSM_R = crate::BitReader<bool>;
#[doc = "Field `MSM` writer - "]
pub type MSM_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMCR_SPEC, bool, O>;
#[doc = "Field `ETF` reader - "]
pub type ETF_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ETF` writer - "]
pub type ETF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SMCR_SPEC, u8, u8, 4, O>;
#[doc = "Field `ETPS` reader - "]
pub type ETPS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ETPS` writer - "]
pub type ETPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `ECE` reader - "]
pub type ECE_R = crate::BitReader<bool>;
#[doc = "Field `ECE` writer - "]
pub type ECE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMCR_SPEC, bool, O>;
#[doc = "Field `ETP` reader - "]
pub type ETP_R = crate::BitReader<bool>;
#[doc = "Field `ETP` writer - "]
pub type ETP_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMCR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn sms(&self) -> SMS_R {
SMS_R::new((self.bits & 7) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn occs(&self) -> OCCS_R {
OCCS_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn ts(&self) -> TS_R {
TS_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn msm(&self) -> MSM_R {
MSM_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11"]
#[inline(always)]
pub fn etf(&self) -> ETF_R {
ETF_R::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bits 12:13"]
#[inline(always)]
pub fn etps(&self) -> ETPS_R {
ETPS_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn ece(&self) -> ECE_R {
ECE_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn etp(&self) -> ETP_R {
ETP_R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2"]
#[inline(always)]
#[must_use]
pub fn sms(&mut self) -> SMS_W<0> {
SMS_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn occs(&mut self) -> OCCS_W<3> {
OCCS_W::new(self)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn ts(&mut self) -> TS_W<4> {
TS_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn msm(&mut self) -> MSM_W<7> {
MSM_W::new(self)
}
#[doc = "Bits 8:11"]
#[inline(always)]
#[must_use]
pub fn etf(&mut self) -> ETF_W<8> {
ETF_W::new(self)
}
#[doc = "Bits 12:13"]
#[inline(always)]
#[must_use]
pub fn etps(&mut self) -> ETPS_W<12> {
ETPS_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn ece(&mut self) -> ECE_W<14> {
ECE_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn etp(&mut self) -> ETP_W<15> {
ETP_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Slave Mode Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smcr](index.html) module"]
pub struct SMCR_SPEC;
impl crate::RegisterSpec for SMCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [smcr::R](R) reader structure"]
impl crate::Readable for SMCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [smcr::W](W) writer structure"]
impl crate::Writable for SMCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SMCR to value 0"]
impl crate::Resettable for SMCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DIER (rw) register accessor: an alias for `Reg<DIER_SPEC>`"]
pub type DIER = crate::Reg<dier::DIER_SPEC>;
#[doc = "DMA/Interrupt Enable Register"]
pub mod dier {
#[doc = "Register `DIER` reader"]
pub struct R(crate::R<DIER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DIER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DIER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DIER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DIER` writer"]
pub struct W(crate::W<DIER_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DIER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DIER_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DIER_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `UIE` reader - "]
pub type UIE_R = crate::BitReader<bool>;
#[doc = "Field `UIE` writer - "]
pub type UIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC1IE` reader - "]
pub type CC1IE_R = crate::BitReader<bool>;
#[doc = "Field `CC1IE` writer - "]
pub type CC1IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC2IE` reader - "]
pub type CC2IE_R = crate::BitReader<bool>;
#[doc = "Field `CC2IE` writer - "]
pub type CC2IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC3IE` reader - "]
pub type CC3IE_R = crate::BitReader<bool>;
#[doc = "Field `CC3IE` writer - "]
pub type CC3IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC4IE` reader - "]
pub type CC4IE_R = crate::BitReader<bool>;
#[doc = "Field `CC4IE` writer - "]
pub type CC4IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `COMIE` reader - "]
pub type COMIE_R = crate::BitReader<bool>;
#[doc = "Field `COMIE` writer - "]
pub type COMIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `TIE` reader - "]
pub type TIE_R = crate::BitReader<bool>;
#[doc = "Field `TIE` writer - "]
pub type TIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `BIE` reader - "]
pub type BIE_R = crate::BitReader<bool>;
#[doc = "Field `BIE` writer - "]
pub type BIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `UDE` reader - "]
pub type UDE_R = crate::BitReader<bool>;
#[doc = "Field `UDE` writer - "]
pub type UDE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC1DE` reader - "]
pub type CC1DE_R = crate::BitReader<bool>;
#[doc = "Field `CC1DE` writer - "]
pub type CC1DE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC2DE` reader - "]
pub type CC2DE_R = crate::BitReader<bool>;
#[doc = "Field `CC2DE` writer - "]
pub type CC2DE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC3DE` reader - "]
pub type CC3DE_R = crate::BitReader<bool>;
#[doc = "Field `CC3DE` writer - "]
pub type CC3DE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC4DE` reader - "]
pub type CC4DE_R = crate::BitReader<bool>;
#[doc = "Field `CC4DE` writer - "]
pub type CC4DE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `COMDE` reader - "]
pub type COMDE_R = crate::BitReader<bool>;
#[doc = "Field `COMDE` writer - "]
pub type COMDE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `TDE` reader - "]
pub type TDE_R = crate::BitReader<bool>;
#[doc = "Field `TDE` writer - "]
pub type TDE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC5IE` reader - "]
pub type CC5IE_R = crate::BitReader<bool>;
#[doc = "Field `CC5IE` writer - "]
pub type CC5IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC5DE` reader - "]
pub type CC5DE_R = crate::BitReader<bool>;
#[doc = "Field `CC5DE` writer - "]
pub type CC5DE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn uie(&self) -> UIE_R {
UIE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn cc1ie(&self) -> CC1IE_R {
CC1IE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn cc2ie(&self) -> CC2IE_R {
CC2IE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn cc3ie(&self) -> CC3IE_R {
CC3IE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn cc4ie(&self) -> CC4IE_R {
CC4IE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn comie(&self) -> COMIE_R {
COMIE_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tie(&self) -> TIE_R {
TIE_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn bie(&self) -> BIE_R {
BIE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn ude(&self) -> UDE_R {
UDE_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn cc1de(&self) -> CC1DE_R {
CC1DE_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn cc2de(&self) -> CC2DE_R {
CC2DE_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn cc3de(&self) -> CC3DE_R {
CC3DE_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn cc4de(&self) -> CC4DE_R {
CC4DE_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn comde(&self) -> COMDE_R {
COMDE_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn tde(&self) -> TDE_R {
TDE_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn cc5ie(&self) -> CC5IE_R {
CC5IE_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17"]
#[inline(always)]
pub fn cc5de(&self) -> CC5DE_R {
CC5DE_R::new(((self.bits >> 17) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn uie(&mut self) -> UIE_W<0> {
UIE_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn cc1ie(&mut self) -> CC1IE_W<1> {
CC1IE_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn cc2ie(&mut self) -> CC2IE_W<2> {
CC2IE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn cc3ie(&mut self) -> CC3IE_W<3> {
CC3IE_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn cc4ie(&mut self) -> CC4IE_W<4> {
CC4IE_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn comie(&mut self) -> COMIE_W<5> {
COMIE_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tie(&mut self) -> TIE_W<6> {
TIE_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn bie(&mut self) -> BIE_W<7> {
BIE_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn ude(&mut self) -> UDE_W<8> {
UDE_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn cc1de(&mut self) -> CC1DE_W<9> {
CC1DE_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn cc2de(&mut self) -> CC2DE_W<10> {
CC2DE_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn cc3de(&mut self) -> CC3DE_W<11> {
CC3DE_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn cc4de(&mut self) -> CC4DE_W<12> {
CC4DE_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn comde(&mut self) -> COMDE_W<13> {
COMDE_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn tde(&mut self) -> TDE_W<14> {
TDE_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn cc5ie(&mut self) -> CC5IE_W<16> {
CC5IE_W::new(self)
}
#[doc = "Bit 17"]
#[inline(always)]
#[must_use]
pub fn cc5de(&mut self) -> CC5DE_W<17> {
CC5DE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA/Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dier](index.html) module"]
pub struct DIER_SPEC;
impl crate::RegisterSpec for DIER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dier::R](R) reader structure"]
impl crate::Readable for DIER_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dier::W](W) writer structure"]
impl crate::Writable for DIER_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DIER to value 0"]
impl crate::Resettable for DIER_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SR (rw) register accessor: an alias for `Reg<SR_SPEC>`"]
pub type SR = crate::Reg<sr::SR_SPEC>;
#[doc = "status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub struct R(crate::R<SR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SR` writer"]
pub struct W(crate::W<SR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `UIF` reader - "]
pub type UIF_R = crate::BitReader<bool>;
#[doc = "Field `UIF` writer - "]
pub type UIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC1IF` reader - "]
pub type CC1IF_R = crate::BitReader<bool>;
#[doc = "Field `CC1IF` writer - "]
pub type CC1IF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC2IF` reader - "]
pub type CC2IF_R = crate::BitReader<bool>;
#[doc = "Field `CC2IF` writer - "]
pub type CC2IF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC3IF` reader - "]
pub type CC3IF_R = crate::BitReader<bool>;
#[doc = "Field `CC3IF` writer - "]
pub type CC3IF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC4IF` reader - "]
pub type CC4IF_R = crate::BitReader<bool>;
#[doc = "Field `CC4IF` writer - "]
pub type CC4IF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `COMIF` reader - "]
pub type COMIF_R = crate::BitReader<bool>;
#[doc = "Field `COMIF` writer - "]
pub type COMIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `TIF` reader - "]
pub type TIF_R = crate::BitReader<bool>;
#[doc = "Field `TIF` writer - "]
pub type TIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `BIF` reader - "]
pub type BIF_R = crate::BitReader<bool>;
#[doc = "Field `BIF` writer - "]
pub type BIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC1OF` reader - "]
pub type CC1OF_R = crate::BitReader<bool>;
#[doc = "Field `CC1OF` writer - "]
pub type CC1OF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC2OF` reader - "]
pub type CC2OF_R = crate::BitReader<bool>;
#[doc = "Field `CC2OF` writer - "]
pub type CC2OF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC3OF` reader - "]
pub type CC3OF_R = crate::BitReader<bool>;
#[doc = "Field `CC3OF` writer - "]
pub type CC3OF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC4OF` reader - "]
pub type CC4OF_R = crate::BitReader<bool>;
#[doc = "Field `CC4OF` writer - "]
pub type CC4OF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC5IF` reader - "]
pub type CC5IF_R = crate::BitReader<bool>;
#[doc = "Field `CC5IF` writer - "]
pub type CC5IF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn uif(&self) -> UIF_R {
UIF_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn cc1if(&self) -> CC1IF_R {
CC1IF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn cc2if(&self) -> CC2IF_R {
CC2IF_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn cc3if(&self) -> CC3IF_R {
CC3IF_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn cc4if(&self) -> CC4IF_R {
CC4IF_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn comif(&self) -> COMIF_R {
COMIF_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tif(&self) -> TIF_R {
TIF_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn bif(&self) -> BIF_R {
BIF_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn cc1of(&self) -> CC1OF_R {
CC1OF_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn cc2of(&self) -> CC2OF_R {
CC2OF_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn cc3of(&self) -> CC3OF_R {
CC3OF_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn cc4of(&self) -> CC4OF_R {
CC4OF_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn cc5if(&self) -> CC5IF_R {
CC5IF_R::new(((self.bits >> 16) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn uif(&mut self) -> UIF_W<0> {
UIF_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn cc1if(&mut self) -> CC1IF_W<1> {
CC1IF_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn cc2if(&mut self) -> CC2IF_W<2> {
CC2IF_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn cc3if(&mut self) -> CC3IF_W<3> {
CC3IF_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn cc4if(&mut self) -> CC4IF_W<4> {
CC4IF_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn comif(&mut self) -> COMIF_W<5> {
COMIF_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tif(&mut self) -> TIF_W<6> {
TIF_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn bif(&mut self) -> BIF_W<7> {
BIF_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn cc1of(&mut self) -> CC1OF_W<9> {
CC1OF_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn cc2of(&mut self) -> CC2OF_W<10> {
CC2OF_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn cc3of(&mut self) -> CC3OF_W<11> {
CC3OF_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn cc4of(&mut self) -> CC4OF_W<12> {
CC4OF_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn cc5if(&mut self) -> CC5IF_W<16> {
CC5IF_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"]
pub struct SR_SPEC;
impl crate::RegisterSpec for SR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [sr::R](R) reader structure"]
impl crate::Readable for SR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [sr::W](W) writer structure"]
impl crate::Writable for SR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "EGR (w) register accessor: an alias for `Reg<EGR_SPEC>`"]
pub type EGR = crate::Reg<egr::EGR_SPEC>;
#[doc = "event generation register"]
pub mod egr {
#[doc = "Register `EGR` writer"]
pub struct W(crate::W<EGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<EGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<EGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<EGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `UG` writer - "]
pub type UG_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `CC1G` writer - "]
pub type CC1G_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `CC2G` writer - "]
pub type CC2G_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `CC3G` writer - "]
pub type CC3G_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `CC4G` writer - "]
pub type CC4G_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `COMG` writer - "]
pub type COMG_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `TG` writer - "]
pub type TG_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `BG` writer - "]
pub type BG_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `CC5G` writer - "]
pub type CC5G_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn ug(&mut self) -> UG_W<0> {
UG_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn cc1g(&mut self) -> CC1G_W<1> {
CC1G_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn cc2g(&mut self) -> CC2G_W<2> {
CC2G_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn cc3g(&mut self) -> CC3G_W<3> {
CC3G_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn cc4g(&mut self) -> CC4G_W<4> {
CC4G_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn comg(&mut self) -> COMG_W<5> {
COMG_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tg(&mut self) -> TG_W<6> {
TG_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn bg(&mut self) -> BG_W<7> {
BG_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn cc5g(&mut self) -> CC5G_W<16> {
CC5G_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "event generation register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [egr](index.html) module"]
pub struct EGR_SPEC;
impl crate::RegisterSpec for EGR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [egr::W](W) writer structure"]
impl crate::Writable for EGR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets EGR to value 0"]
impl crate::Resettable for EGR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCMR1_Output (rw) register accessor: an alias for `Reg<CCMR1_OUTPUT_SPEC>`"]
pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUT_SPEC>;
#[doc = "Capture/Compare Mode Register 1"]
pub mod ccmr1_output {
#[doc = "Register `CCMR1_Output` reader"]
pub struct R(crate::R<CCMR1_OUTPUT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCMR1_OUTPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCMR1_OUTPUT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCMR1_OUTPUT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCMR1_Output` writer"]
pub struct W(crate::W<CCMR1_OUTPUT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCMR1_OUTPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCMR1_OUTPUT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCMR1_OUTPUT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CC1S` reader - "]
pub type CC1S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC1S` writer - "]
pub type CC1S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `OC1FE` reader - "]
pub type OC1FE_R = crate::BitReader<bool>;
#[doc = "Field `OC1FE` writer - "]
pub type OC1FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC1PE` reader - "]
pub type OC1PE_R = crate::BitReader<bool>;
#[doc = "Field `OC1PE` writer - "]
pub type OC1PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC1M` reader - "]
pub type OC1M_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OC1M` writer - "]
pub type OC1M_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, u8, 3, O>;
#[doc = "Field `OC1CE` reader - "]
pub type OC1CE_R = crate::BitReader<bool>;
#[doc = "Field `OC1CE` writer - "]
pub type OC1CE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `CC2S` reader - "]
pub type CC2S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC2S` writer - "]
pub type CC2S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `OC2FE` reader - "]
pub type OC2FE_R = crate::BitReader<bool>;
#[doc = "Field `OC2FE` writer - "]
pub type OC2FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC2PE` reader - "]
pub type OC2PE_R = crate::BitReader<bool>;
#[doc = "Field `OC2PE` writer - "]
pub type OC2PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC2M` reader - "]
pub type OC2M_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OC2M` writer - "]
pub type OC2M_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, u8, 3, O>;
#[doc = "Field `OC2CE` reader - "]
pub type OC2CE_R = crate::BitReader<bool>;
#[doc = "Field `OC2CE` writer - "]
pub type OC2CE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn cc1s(&self) -> CC1S_R {
CC1S_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn oc1fe(&self) -> OC1FE_R {
OC1FE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn oc1pe(&self) -> OC1PE_R {
OC1PE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn oc1m(&self) -> OC1M_R {
OC1M_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn oc1ce(&self) -> OC1CE_R {
OC1CE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn cc2s(&self) -> CC2S_R {
CC2S_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn oc2fe(&self) -> OC2FE_R {
OC2FE_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn oc2pe(&self) -> OC2PE_R {
OC2PE_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:14"]
#[inline(always)]
pub fn oc2m(&self) -> OC2M_R {
OC2M_R::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn oc2ce(&self) -> OC2CE_R {
OC2CE_R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn cc1s(&mut self) -> CC1S_W<0> {
CC1S_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn oc1fe(&mut self) -> OC1FE_W<2> {
OC1FE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn oc1pe(&mut self) -> OC1PE_W<3> {
OC1PE_W::new(self)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn oc1m(&mut self) -> OC1M_W<4> {
OC1M_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn oc1ce(&mut self) -> OC1CE_W<7> {
OC1CE_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn cc2s(&mut self) -> CC2S_W<8> {
CC2S_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn oc2fe(&mut self) -> OC2FE_W<10> {
OC2FE_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn oc2pe(&mut self) -> OC2PE_W<11> {
OC2PE_W::new(self)
}
#[doc = "Bits 12:14"]
#[inline(always)]
#[must_use]
pub fn oc2m(&mut self) -> OC2M_W<12> {
OC2M_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn oc2ce(&mut self) -> OC2CE_W<15> {
OC2CE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Mode Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr1_output](index.html) module"]
pub struct CCMR1_OUTPUT_SPEC;
impl crate::RegisterSpec for CCMR1_OUTPUT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccmr1_output::R](R) reader structure"]
impl crate::Readable for CCMR1_OUTPUT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccmr1_output::W](W) writer structure"]
impl crate::Writable for CCMR1_OUTPUT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCMR1_Output to value 0"]
impl crate::Resettable for CCMR1_OUTPUT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCMR1_Input (rw) register accessor: an alias for `Reg<CCMR1_INPUT_SPEC>`"]
pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUT_SPEC>;
#[doc = "Capture/Compare Mode Register 2"]
pub mod ccmr1_input {
#[doc = "Register `CCMR1_Input` reader"]
pub struct R(crate::R<CCMR1_INPUT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCMR1_INPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCMR1_INPUT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCMR1_INPUT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCMR1_Input` writer"]
pub struct W(crate::W<CCMR1_INPUT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCMR1_INPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCMR1_INPUT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCMR1_INPUT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CC1S` reader - "]
pub type CC1S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC1S` writer - "]
pub type CC1S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC1PSC` reader - "]
pub type IC1PSC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC1PSC` writer - "]
pub type IC1PSC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC1F` reader - "]
pub type IC1F_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC1F` writer - "]
pub type IC1F_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 4, O>;
#[doc = "Field `CC2S` reader - "]
pub type CC2S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC2S` writer - "]
pub type CC2S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC2PSC` reader - "]
pub type IC2PSC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC2PSC` writer - "]
pub type IC2PSC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC2F` reader - "]
pub type IC2F_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC2F` writer - "]
pub type IC2F_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 4, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn cc1s(&self) -> CC1S_R {
CC1S_R::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3"]
#[inline(always)]
pub fn ic1psc(&self) -> IC1PSC_R {
IC1PSC_R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn ic1f(&self) -> IC1F_R {
IC1F_R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn cc2s(&self) -> CC2S_R {
CC2S_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11"]
#[inline(always)]
pub fn ic2psc(&self) -> IC2PSC_R {
IC2PSC_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:15"]
#[inline(always)]
pub fn ic2f(&self) -> IC2F_R {
IC2F_R::new(((self.bits >> 12) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn cc1s(&mut self) -> CC1S_W<0> {
CC1S_W::new(self)
}
#[doc = "Bits 2:3"]
#[inline(always)]
#[must_use]
pub fn ic1psc(&mut self) -> IC1PSC_W<2> {
IC1PSC_W::new(self)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn ic1f(&mut self) -> IC1F_W<4> {
IC1F_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn cc2s(&mut self) -> CC2S_W<8> {
CC2S_W::new(self)
}
#[doc = "Bits 10:11"]
#[inline(always)]
#[must_use]
pub fn ic2psc(&mut self) -> IC2PSC_W<10> {
IC2PSC_W::new(self)
}
#[doc = "Bits 12:15"]
#[inline(always)]
#[must_use]
pub fn ic2f(&mut self) -> IC2F_W<12> {
IC2F_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Mode Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr1_input](index.html) module"]
pub struct CCMR1_INPUT_SPEC;
impl crate::RegisterSpec for CCMR1_INPUT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccmr1_input::R](R) reader structure"]
impl crate::Readable for CCMR1_INPUT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccmr1_input::W](W) writer structure"]
impl crate::Writable for CCMR1_INPUT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCMR1_Input to value 0"]
impl crate::Resettable for CCMR1_INPUT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCMR2_Output (rw) register accessor: an alias for `Reg<CCMR2_OUTPUT_SPEC>`"]
pub type CCMR2_OUTPUT = crate::Reg<ccmr2_output::CCMR2_OUTPUT_SPEC>;
#[doc = "Capture/Compare Mode Register 1"]
pub mod ccmr2_output {
#[doc = "Register `CCMR2_Output` reader"]
pub struct R(crate::R<CCMR2_OUTPUT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCMR2_OUTPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCMR2_OUTPUT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCMR2_OUTPUT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCMR2_Output` writer"]
pub struct W(crate::W<CCMR2_OUTPUT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCMR2_OUTPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCMR2_OUTPUT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCMR2_OUTPUT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CC3S` reader - "]
pub type CC3S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC3S` writer - "]
pub type CC3S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_OUTPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `OC3FE` reader - "]
pub type OC3FE_R = crate::BitReader<bool>;
#[doc = "Field `OC3FE` writer - "]
pub type OC3FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC3PE` reader - "]
pub type OC3PE_R = crate::BitReader<bool>;
#[doc = "Field `OC3PE` writer - "]
pub type OC3PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC3M` reader - "]
pub type OC3M_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OC3M` writer - "]
pub type OC3M_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_OUTPUT_SPEC, u8, u8, 3, O>;
#[doc = "Field `OC3CE` reader - "]
pub type OC3CE_R = crate::BitReader<bool>;
#[doc = "Field `OC3CE` writer - "]
pub type OC3CE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
#[doc = "Field `CC4S` reader - "]
pub type CC4S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC4S` writer - "]
pub type CC4S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_OUTPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `OC4FE` reader - "]
pub type OC4FE_R = crate::BitReader<bool>;
#[doc = "Field `OC4FE` writer - "]
pub type OC4FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC4PE` reader - "]
pub type OC4PE_R = crate::BitReader<bool>;
#[doc = "Field `OC4PE` writer - "]
pub type OC4PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC4M` reader - "]
pub type OC4M_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OC4M` writer - "]
pub type OC4M_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_OUTPUT_SPEC, u8, u8, 3, O>;
#[doc = "Field `OC4CE` reader - "]
pub type OC4CE_R = crate::BitReader<bool>;
#[doc = "Field `OC4CE` writer - "]
pub type OC4CE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn cc3s(&self) -> CC3S_R {
CC3S_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn oc3fe(&self) -> OC3FE_R {
OC3FE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn oc3pe(&self) -> OC3PE_R {
OC3PE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn oc3m(&self) -> OC3M_R {
OC3M_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn oc3ce(&self) -> OC3CE_R {
OC3CE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn cc4s(&self) -> CC4S_R {
CC4S_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn oc4fe(&self) -> OC4FE_R {
OC4FE_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn oc4pe(&self) -> OC4PE_R {
OC4PE_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:14"]
#[inline(always)]
pub fn oc4m(&self) -> OC4M_R {
OC4M_R::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn oc4ce(&self) -> OC4CE_R {
OC4CE_R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn cc3s(&mut self) -> CC3S_W<0> {
CC3S_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn oc3fe(&mut self) -> OC3FE_W<2> {
OC3FE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn oc3pe(&mut self) -> OC3PE_W<3> {
OC3PE_W::new(self)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn oc3m(&mut self) -> OC3M_W<4> {
OC3M_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn oc3ce(&mut self) -> OC3CE_W<7> {
OC3CE_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn cc4s(&mut self) -> CC4S_W<8> {
CC4S_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn oc4fe(&mut self) -> OC4FE_W<10> {
OC4FE_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn oc4pe(&mut self) -> OC4PE_W<11> {
OC4PE_W::new(self)
}
#[doc = "Bits 12:14"]
#[inline(always)]
#[must_use]
pub fn oc4m(&mut self) -> OC4M_W<12> {
OC4M_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn oc4ce(&mut self) -> OC4CE_W<15> {
OC4CE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Mode Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr2_output](index.html) module"]
pub struct CCMR2_OUTPUT_SPEC;
impl crate::RegisterSpec for CCMR2_OUTPUT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccmr2_output::R](R) reader structure"]
impl crate::Readable for CCMR2_OUTPUT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccmr2_output::W](W) writer structure"]
impl crate::Writable for CCMR2_OUTPUT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCMR2_Output to value 0"]
impl crate::Resettable for CCMR2_OUTPUT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCMR2_Input (rw) register accessor: an alias for `Reg<CCMR2_INPUT_SPEC>`"]
pub type CCMR2_INPUT = crate::Reg<ccmr2_input::CCMR2_INPUT_SPEC>;
#[doc = "Capture/Compare Mode Register 2"]
pub mod ccmr2_input {
#[doc = "Register `CCMR2_Input` reader"]
pub struct R(crate::R<CCMR2_INPUT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCMR2_INPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCMR2_INPUT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCMR2_INPUT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCMR2_Input` writer"]
pub struct W(crate::W<CCMR2_INPUT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCMR2_INPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCMR2_INPUT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCMR2_INPUT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CC3S` reader - "]
pub type CC3S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC3S` writer - "]
pub type CC3S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC3PSC` reader - "]
pub type IC3PSC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC3PSC` writer - "]
pub type IC3PSC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC3F` reader - "]
pub type IC3F_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC3F` writer - "]
pub type IC3F_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 4, O>;
#[doc = "Field `CC4S` reader - "]
pub type CC4S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC4S` writer - "]
pub type CC4S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC4PSC` reader - "]
pub type IC4PSC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC4PSC` writer - "]
pub type IC4PSC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC4F` reader - "]
pub type IC4F_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC4F` writer - "]
pub type IC4F_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 4, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn cc3s(&self) -> CC3S_R {
CC3S_R::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3"]
#[inline(always)]
pub fn ic3psc(&self) -> IC3PSC_R {
IC3PSC_R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn ic3f(&self) -> IC3F_R {
IC3F_R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn cc4s(&self) -> CC4S_R {
CC4S_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11"]
#[inline(always)]
pub fn ic4psc(&self) -> IC4PSC_R {
IC4PSC_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:15"]
#[inline(always)]
pub fn ic4f(&self) -> IC4F_R {
IC4F_R::new(((self.bits >> 12) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn cc3s(&mut self) -> CC3S_W<0> {
CC3S_W::new(self)
}
#[doc = "Bits 2:3"]
#[inline(always)]
#[must_use]
pub fn ic3psc(&mut self) -> IC3PSC_W<2> {
IC3PSC_W::new(self)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn ic3f(&mut self) -> IC3F_W<4> {
IC3F_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn cc4s(&mut self) -> CC4S_W<8> {
CC4S_W::new(self)
}
#[doc = "Bits 10:11"]
#[inline(always)]
#[must_use]
pub fn ic4psc(&mut self) -> IC4PSC_W<10> {
IC4PSC_W::new(self)
}
#[doc = "Bits 12:15"]
#[inline(always)]
#[must_use]
pub fn ic4f(&mut self) -> IC4F_W<12> {
IC4F_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Mode Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr2_input](index.html) module"]
pub struct CCMR2_INPUT_SPEC;
impl crate::RegisterSpec for CCMR2_INPUT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccmr2_input::R](R) reader structure"]
impl crate::Readable for CCMR2_INPUT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccmr2_input::W](W) writer structure"]
impl crate::Writable for CCMR2_INPUT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCMR2_Input to value 0"]
impl crate::Resettable for CCMR2_INPUT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCER (rw) register accessor: an alias for `Reg<CCER_SPEC>`"]
pub type CCER = crate::Reg<ccer::CCER_SPEC>;
#[doc = "Capture/Compare Enable Register"]
pub mod ccer {
#[doc = "Register `CCER` reader"]
pub struct R(crate::R<CCER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCER` writer"]
pub struct W(crate::W<CCER_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCER_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCER_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CC1E` reader - "]
pub type CC1E_R = crate::BitReader<bool>;
#[doc = "Field `CC1E` writer - "]
pub type CC1E_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC1P` reader - "]
pub type CC1P_R = crate::BitReader<bool>;
#[doc = "Field `CC1P` writer - "]
pub type CC1P_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC1NE` reader - "]
pub type CC1NE_R = crate::BitReader<bool>;
#[doc = "Field `CC1NE` writer - "]
pub type CC1NE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC1NP` reader - "]
pub type CC1NP_R = crate::BitReader<bool>;
#[doc = "Field `CC1NP` writer - "]
pub type CC1NP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC2E` reader - "]
pub type CC2E_R = crate::BitReader<bool>;
#[doc = "Field `CC2E` writer - "]
pub type CC2E_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC2P` reader - "]
pub type CC2P_R = crate::BitReader<bool>;
#[doc = "Field `CC2P` writer - "]
pub type CC2P_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC2NE` reader - "]
pub type CC2NE_R = crate::BitReader<bool>;
#[doc = "Field `CC2NE` writer - "]
pub type CC2NE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC2NP` reader - "]
pub type CC2NP_R = crate::BitReader<bool>;
#[doc = "Field `CC2NP` writer - "]
pub type CC2NP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC3E` reader - "]
pub type CC3E_R = crate::BitReader<bool>;
#[doc = "Field `CC3E` writer - "]
pub type CC3E_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC3P` reader - "]
pub type CC3P_R = crate::BitReader<bool>;
#[doc = "Field `CC3P` writer - "]
pub type CC3P_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC3NE` reader - "]
pub type CC3NE_R = crate::BitReader<bool>;
#[doc = "Field `CC3NE` writer - "]
pub type CC3NE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC3NP` reader - "]
pub type CC3NP_R = crate::BitReader<bool>;
#[doc = "Field `CC3NP` writer - "]
pub type CC3NP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC4E` reader - "]
pub type CC4E_R = crate::BitReader<bool>;
#[doc = "Field `CC4E` writer - "]
pub type CC4E_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC4P` reader - "]
pub type CC4P_R = crate::BitReader<bool>;
#[doc = "Field `CC4P` writer - "]
pub type CC4P_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC4NE` reader - "]
pub type CC4NE_R = crate::BitReader<bool>;
#[doc = "Field `CC4NE` writer - "]
pub type CC4NE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC4NP` reader - "]
pub type CC4NP_R = crate::BitReader<bool>;
#[doc = "Field `CC4NP` writer - "]
pub type CC4NP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn cc1e(&self) -> CC1E_R {
CC1E_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn cc1p(&self) -> CC1P_R {
CC1P_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn cc1ne(&self) -> CC1NE_R {
CC1NE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn cc1np(&self) -> CC1NP_R {
CC1NP_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn cc2e(&self) -> CC2E_R {
CC2E_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn cc2p(&self) -> CC2P_R {
CC2P_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn cc2ne(&self) -> CC2NE_R {
CC2NE_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn cc2np(&self) -> CC2NP_R {
CC2NP_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn cc3e(&self) -> CC3E_R {
CC3E_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn cc3p(&self) -> CC3P_R {
CC3P_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn cc3ne(&self) -> CC3NE_R {
CC3NE_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn cc3np(&self) -> CC3NP_R {
CC3NP_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn cc4e(&self) -> CC4E_R {
CC4E_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn cc4p(&self) -> CC4P_R {
CC4P_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn cc4ne(&self) -> CC4NE_R {
CC4NE_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn cc4np(&self) -> CC4NP_R {
CC4NP_R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn cc1e(&mut self) -> CC1E_W<0> {
CC1E_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn cc1p(&mut self) -> CC1P_W<1> {
CC1P_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn cc1ne(&mut self) -> CC1NE_W<2> {
CC1NE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn cc1np(&mut self) -> CC1NP_W<3> {
CC1NP_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn cc2e(&mut self) -> CC2E_W<4> {
CC2E_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn cc2p(&mut self) -> CC2P_W<5> {
CC2P_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn cc2ne(&mut self) -> CC2NE_W<6> {
CC2NE_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn cc2np(&mut self) -> CC2NP_W<7> {
CC2NP_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn cc3e(&mut self) -> CC3E_W<8> {
CC3E_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn cc3p(&mut self) -> CC3P_W<9> {
CC3P_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn cc3ne(&mut self) -> CC3NE_W<10> {
CC3NE_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn cc3np(&mut self) -> CC3NP_W<11> {
CC3NP_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn cc4e(&mut self) -> CC4E_W<12> {
CC4E_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn cc4p(&mut self) -> CC4P_W<13> {
CC4P_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn cc4ne(&mut self) -> CC4NE_W<14> {
CC4NE_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn cc4np(&mut self) -> CC4NP_W<15> {
CC4NP_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccer](index.html) module"]
pub struct CCER_SPEC;
impl crate::RegisterSpec for CCER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccer::R](R) reader structure"]
impl crate::Readable for CCER_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccer::W](W) writer structure"]
impl crate::Writable for CCER_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCER to value 0"]
impl crate::Resettable for CCER_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CNT (rw) register accessor: an alias for `Reg<CNT_SPEC>`"]
pub type CNT = crate::Reg<cnt::CNT_SPEC>;
#[doc = "counter"]
pub mod cnt {
#[doc = "Register `CNT` reader"]
pub struct R(crate::R<CNT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CNT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CNT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CNT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CNT` writer"]
pub struct W(crate::W<CNT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CNT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CNT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CNT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CNT` reader - "]
pub type CNT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CNT` writer - "]
pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNT_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn cnt(&self) -> CNT_R {
CNT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CNT_W<0> {
CNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnt](index.html) module"]
pub struct CNT_SPEC;
impl crate::RegisterSpec for CNT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cnt::R](R) reader structure"]
impl crate::Readable for CNT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cnt::W](W) writer structure"]
impl crate::Writable for CNT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CNT to value 0"]
impl crate::Resettable for CNT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PSC (rw) register accessor: an alias for `Reg<PSC_SPEC>`"]
pub type PSC = crate::Reg<psc::PSC_SPEC>;
#[doc = "Prescaler"]
pub mod psc {
#[doc = "Register `PSC` reader"]
pub struct R(crate::R<PSC_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PSC_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PSC_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PSC_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PSC` writer"]
pub struct W(crate::W<PSC_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PSC_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PSC_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PSC_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PSC` reader - "]
pub type PSC_R = crate::FieldReader<u16, u16>;
#[doc = "Field `PSC` writer - "]
pub type PSC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PSC_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn psc(&self) -> PSC_R {
PSC_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn psc(&mut self) -> PSC_W<0> {
PSC_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [psc](index.html) module"]
pub struct PSC_SPEC;
impl crate::RegisterSpec for PSC_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [psc::R](R) reader structure"]
impl crate::Readable for PSC_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [psc::W](W) writer structure"]
impl crate::Writable for PSC_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PSC to value 0"]
impl crate::Resettable for PSC_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ARR (rw) register accessor: an alias for `Reg<ARR_SPEC>`"]
pub type ARR = crate::Reg<arr::ARR_SPEC>;
#[doc = "autoload register"]
pub mod arr {
#[doc = "Register `ARR` reader"]
pub struct R(crate::R<ARR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ARR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ARR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ARR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ARR` writer"]
pub struct W(crate::W<ARR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ARR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ARR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ARR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `ARR` reader - "]
pub type ARR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `ARR` writer - "]
pub type ARR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ARR_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn arr(&self) -> ARR_R {
ARR_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn arr(&mut self) -> ARR_W<0> {
ARR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "autoload register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arr](index.html) module"]
pub struct ARR_SPEC;
impl crate::RegisterSpec for ARR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [arr::R](R) reader structure"]
impl crate::Readable for ARR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [arr::W](W) writer structure"]
impl crate::Writable for ARR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ARR to value 0"]
impl crate::Resettable for ARR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RCR (rw) register accessor: an alias for `Reg<RCR_SPEC>`"]
pub type RCR = crate::Reg<rcr::RCR_SPEC>;
#[doc = "Repeat count register"]
pub mod rcr {
#[doc = "Register `RCR` reader"]
pub struct R(crate::R<RCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `RCR` writer"]
pub struct W(crate::W<RCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<RCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<RCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<RCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `REP` reader - "]
pub type REP_R = crate::FieldReader<u8, u8>;
#[doc = "Field `REP` writer - "]
pub type REP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RCR_SPEC, u8, u8, 8, O>;
#[doc = "Field `REP_CNT` reader - "]
pub type REP_CNT_R = crate::FieldReader<u8, u8>;
#[doc = "Field `REP_CNT` writer - "]
pub type REP_CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RCR_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn rep(&self) -> REP_R {
REP_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15"]
#[inline(always)]
pub fn rep_cnt(&self) -> REP_CNT_R {
REP_CNT_R::new(((self.bits >> 8) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn rep(&mut self) -> REP_W<0> {
REP_W::new(self)
}
#[doc = "Bits 8:15"]
#[inline(always)]
#[must_use]
pub fn rep_cnt(&mut self) -> REP_CNT_W<8> {
REP_CNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Repeat count register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcr](index.html) module"]
pub struct RCR_SPEC;
impl crate::RegisterSpec for RCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rcr::R](R) reader structure"]
impl crate::Readable for RCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [rcr::W](W) writer structure"]
impl crate::Writable for RCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets RCR to value 0"]
impl crate::Resettable for RCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCR1 (rw) register accessor: an alias for `Reg<CCR1_SPEC>`"]
pub type CCR1 = crate::Reg<ccr1::CCR1_SPEC>;
#[doc = "Capture/Compare Register 1"]
pub mod ccr1 {
#[doc = "Register `CCR1` reader"]
pub struct R(crate::R<CCR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCR1` writer"]
pub struct W(crate::W<CCR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CCR` reader - "]
pub type CCR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CCR` writer - "]
pub type CCR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCR1_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn ccr(&self) -> CCR_R {
CCR_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn ccr(&mut self) -> CCR_W<0> {
CCR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr1](index.html) module"]
pub struct CCR1_SPEC;
impl crate::RegisterSpec for CCR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccr1::R](R) reader structure"]
impl crate::Readable for CCR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccr1::W](W) writer structure"]
impl crate::Writable for CCR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCR1 to value 0"]
impl crate::Resettable for CCR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
pub use ccr1 as ccr2;
pub use ccr1 as ccr3;
pub use ccr1 as ccr4;
pub use CCR1 as CCR2;
pub use CCR1 as CCR3;
pub use CCR1 as CCR4;
#[doc = "BDTR (rw) register accessor: an alias for `Reg<BDTR_SPEC>`"]
pub type BDTR = crate::Reg<bdtr::BDTR_SPEC>;
#[doc = "Brake and Deadband Registers"]
pub mod bdtr {
#[doc = "Register `BDTR` reader"]
pub struct R(crate::R<BDTR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<BDTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<BDTR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<BDTR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `BDTR` writer"]
pub struct W(crate::W<BDTR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<BDTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<BDTR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<BDTR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DTG` reader - "]
pub type DTG_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DTG` writer - "]
pub type DTG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BDTR_SPEC, u8, u8, 8, O>;
#[doc = "Field `LOCK` reader - "]
pub type LOCK_R = crate::FieldReader<u8, u8>;
#[doc = "Field `LOCK` writer - "]
pub type LOCK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BDTR_SPEC, u8, u8, 2, O>;
#[doc = "Field `OSSI` reader - "]
pub type OSSI_R = crate::BitReader<bool>;
#[doc = "Field `OSSI` writer - "]
pub type OSSI_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDTR_SPEC, bool, O>;
#[doc = "Field `OSSR` reader - "]
pub type OSSR_R = crate::BitReader<bool>;
#[doc = "Field `OSSR` writer - "]
pub type OSSR_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDTR_SPEC, bool, O>;
#[doc = "Field `BKE` reader - "]
pub type BKE_R = crate::BitReader<bool>;
#[doc = "Field `BKE` writer - "]
pub type BKE_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDTR_SPEC, bool, O>;
#[doc = "Field `BKP` reader - "]
pub type BKP_R = crate::BitReader<bool>;
#[doc = "Field `BKP` writer - "]
pub type BKP_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDTR_SPEC, bool, O>;
#[doc = "Field `AOE` reader - "]
pub type AOE_R = crate::BitReader<bool>;
#[doc = "Field `AOE` writer - "]
pub type AOE_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDTR_SPEC, bool, O>;
#[doc = "Field `MOE` reader - "]
pub type MOE_R = crate::BitReader<bool>;
#[doc = "Field `MOE` writer - "]
pub type MOE_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDTR_SPEC, bool, O>;
#[doc = "Field `DOE` reader - "]
pub type DOE_R = crate::BitReader<bool>;
#[doc = "Field `DOE` writer - "]
pub type DOE_W<'a, const O: u8> = crate::BitWriter<'a, u32, BDTR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn dtg(&self) -> DTG_R {
DTG_R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn lock(&self) -> LOCK_R {
LOCK_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn ossi(&self) -> OSSI_R {
OSSI_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn ossr(&self) -> OSSR_R {
OSSR_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn bke(&self) -> BKE_R {
BKE_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn bkp(&self) -> BKP_R {
BKP_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn aoe(&self) -> AOE_R {
AOE_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn moe(&self) -> MOE_R {
MOE_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16"]
#[inline(always)]
pub fn doe(&self) -> DOE_R {
DOE_R::new(((self.bits >> 16) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn dtg(&mut self) -> DTG_W<0> {
DTG_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn lock(&mut self) -> LOCK_W<8> {
LOCK_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn ossi(&mut self) -> OSSI_W<10> {
OSSI_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn ossr(&mut self) -> OSSR_W<11> {
OSSR_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn bke(&mut self) -> BKE_W<12> {
BKE_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn bkp(&mut self) -> BKP_W<13> {
BKP_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn aoe(&mut self) -> AOE_W<14> {
AOE_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn moe(&mut self) -> MOE_W<15> {
MOE_W::new(self)
}
#[doc = "Bit 16"]
#[inline(always)]
#[must_use]
pub fn doe(&mut self) -> DOE_W<16> {
DOE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Brake and Deadband Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bdtr](index.html) module"]
pub struct BDTR_SPEC;
impl crate::RegisterSpec for BDTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [bdtr::R](R) reader structure"]
impl crate::Readable for BDTR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [bdtr::W](W) writer structure"]
impl crate::Writable for BDTR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets BDTR to value 0"]
impl crate::Resettable for BDTR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DCR (rw) register accessor: an alias for `Reg<DCR_SPEC>`"]
pub type DCR = crate::Reg<dcr::DCR_SPEC>;
#[doc = "DMA Control Register"]
pub mod dcr {
#[doc = "Register `DCR` reader"]
pub struct R(crate::R<DCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DCR` writer"]
pub struct W(crate::W<DCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DBA` reader - "]
pub type DBA_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DBA` writer - "]
pub type DBA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCR_SPEC, u8, u8, 5, O>;
#[doc = "Field `DBL` reader - "]
pub type DBL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DBL` writer - "]
pub type DBL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCR_SPEC, u8, u8, 5, O>;
impl R {
#[doc = "Bits 0:4"]
#[inline(always)]
pub fn dba(&self) -> DBA_R {
DBA_R::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 8:12"]
#[inline(always)]
pub fn dbl(&self) -> DBL_R {
DBL_R::new(((self.bits >> 8) & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:4"]
#[inline(always)]
#[must_use]
pub fn dba(&mut self) -> DBA_W<0> {
DBA_W::new(self)
}
#[doc = "Bits 8:12"]
#[inline(always)]
#[must_use]
pub fn dbl(&mut self) -> DBL_W<8> {
DBL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcr](index.html) module"]
pub struct DCR_SPEC;
impl crate::RegisterSpec for DCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dcr::R](R) reader structure"]
impl crate::Readable for DCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dcr::W](W) writer structure"]
impl crate::Writable for DCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DCR to value 0"]
impl crate::Resettable for DCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMAR (w) register accessor: an alias for `Reg<DMAR_SPEC>`"]
pub type DMAR = crate::Reg<dmar::DMAR_SPEC>;
#[doc = "DMA address for continuous mode"]
pub mod dmar {
#[doc = "Register `DMAR` writer"]
pub struct W(crate::W<DMAR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DMAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DMAR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DMAR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DMAB` writer - "]
pub type DMAB_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMAR_SPEC, u16, u16, 16, O>;
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn dmab(&mut self) -> DMAB_W<0> {
DMAB_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA address for continuous mode\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmar](index.html) module"]
pub struct DMAR_SPEC;
impl crate::RegisterSpec for DMAR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [dmar::W](W) writer structure"]
impl crate::Writable for DMAR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DMAR to value 0"]
impl crate::Resettable for DMAR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCMR3 (rw) register accessor: an alias for `Reg<CCMR3_SPEC>`"]
pub type CCMR3 = crate::Reg<ccmr3::CCMR3_SPEC>;
#[doc = "Capture/Compare Mode Register 3"]
pub mod ccmr3 {
#[doc = "Register `CCMR3` reader"]
pub struct R(crate::R<CCMR3_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCMR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCMR3_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCMR3_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCMR3` writer"]
pub struct W(crate::W<CCMR3_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCMR3_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCMR3_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCMR3_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `OC5FE` reader - "]
pub type OC5FE_R = crate::BitReader<bool>;
#[doc = "Field `OC5FE` writer - "]
pub type OC5FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR3_SPEC, bool, O>;
#[doc = "Field `OC5PE` reader - "]
pub type OC5PE_R = crate::BitReader<bool>;
#[doc = "Field `OC5PE` writer - "]
pub type OC5PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR3_SPEC, bool, O>;
#[doc = "Field `OC5M` reader - "]
pub type OC5M_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OC5M` writer - "]
pub type OC5M_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCMR3_SPEC, u8, u8, 3, O>;
impl R {
#[doc = "Bit 2"]
#[inline(always)]
pub fn oc5fe(&self) -> OC5FE_R {
OC5FE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn oc5pe(&self) -> OC5PE_R {
OC5PE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn oc5m(&self) -> OC5M_R {
OC5M_R::new(((self.bits >> 4) & 7) as u8)
}
}
impl W {
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn oc5fe(&mut self) -> OC5FE_W<2> {
OC5FE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn oc5pe(&mut self) -> OC5PE_W<3> {
OC5PE_W::new(self)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn oc5m(&mut self) -> OC5M_W<4> {
OC5M_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Mode Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr3](index.html) module"]
pub struct CCMR3_SPEC;
impl crate::RegisterSpec for CCMR3_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccmr3::R](R) reader structure"]
impl crate::Readable for CCMR3_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccmr3::W](W) writer structure"]
impl crate::Writable for CCMR3_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCMR3 to value 0"]
impl crate::Resettable for CCMR3_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCR5 (rw) register accessor: an alias for `Reg<CCR5_SPEC>`"]
pub type CCR5 = crate::Reg<ccr5::CCR5_SPEC>;
#[doc = "Capture/Compare Register 5"]
pub mod ccr5 {
#[doc = "Register `CCR5` reader"]
pub struct R(crate::R<CCR5_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCR5_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCR5_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCR5_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCR5` writer"]
pub struct W(crate::W<CCR5_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCR5_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCR5_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCR5_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CCR5` reader - "]
pub type CCR5_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CCR5` writer - "]
pub type CCR5_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCR5_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn ccr5(&self) -> CCR5_R {
CCR5_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn ccr5(&mut self) -> CCR5_W<0> {
CCR5_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Register 5\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr5](index.html) module"]
pub struct CCR5_SPEC;
impl crate::RegisterSpec for CCR5_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccr5::R](R) reader structure"]
impl crate::Readable for CCR5_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccr5::W](W) writer structure"]
impl crate::Writable for CCR5_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCR5 to value 0"]
impl crate::Resettable for CCR5_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PDER (rw) register accessor: an alias for `Reg<PDER_SPEC>`"]
pub type PDER = crate::Reg<pder::PDER_SPEC>;
#[doc = "PWM phase shift/DMA repeat update request enable register"]
pub mod pder {
#[doc = "Register `PDER` reader"]
pub struct R(crate::R<PDER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PDER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PDER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PDER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PDER` writer"]
pub struct W(crate::W<PDER_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PDER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PDER_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PDER_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CCDREPE` reader - "]
pub type CCDREPE_R = crate::BitReader<bool>;
#[doc = "Field `CCDREPE` writer - "]
pub type CCDREPE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDER_SPEC, bool, O>;
#[doc = "Field `CCR1SHIFTEN` reader - "]
pub type CCR1SHIFTEN_R = crate::BitReader<bool>;
#[doc = "Field `CCR1SHIFTEN` writer - "]
pub type CCR1SHIFTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDER_SPEC, bool, O>;
#[doc = "Field `CCR2SHIFTEN` reader - "]
pub type CCR2SHIFTEN_R = crate::BitReader<bool>;
#[doc = "Field `CCR2SHIFTEN` writer - "]
pub type CCR2SHIFTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDER_SPEC, bool, O>;
#[doc = "Field `CCR3SHIFTEN` reader - "]
pub type CCR3SHIFTEN_R = crate::BitReader<bool>;
#[doc = "Field `CCR3SHIFTEN` writer - "]
pub type CCR3SHIFTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDER_SPEC, bool, O>;
#[doc = "Field `CCR4SHIFTEN` reader - "]
pub type CCR4SHIFTEN_R = crate::BitReader<bool>;
#[doc = "Field `CCR4SHIFTEN` writer - "]
pub type CCR4SHIFTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDER_SPEC, bool, O>;
#[doc = "Field `CCR5SHIFTEN` reader - "]
pub type CCR5SHIFTEN_R = crate::BitReader<bool>;
#[doc = "Field `CCR5SHIFTEN` writer - "]
pub type CCR5SHIFTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDER_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn ccdrepe(&self) -> CCDREPE_R {
CCDREPE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn ccr1shiften(&self) -> CCR1SHIFTEN_R {
CCR1SHIFTEN_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn ccr2shiften(&self) -> CCR2SHIFTEN_R {
CCR2SHIFTEN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn ccr3shiften(&self) -> CCR3SHIFTEN_R {
CCR3SHIFTEN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn ccr4shiften(&self) -> CCR4SHIFTEN_R {
CCR4SHIFTEN_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn ccr5shiften(&self) -> CCR5SHIFTEN_R {
CCR5SHIFTEN_R::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn ccdrepe(&mut self) -> CCDREPE_W<0> {
CCDREPE_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn ccr1shiften(&mut self) -> CCR1SHIFTEN_W<1> {
CCR1SHIFTEN_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn ccr2shiften(&mut self) -> CCR2SHIFTEN_W<2> {
CCR2SHIFTEN_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn ccr3shiften(&mut self) -> CCR3SHIFTEN_W<3> {
CCR3SHIFTEN_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn ccr4shiften(&mut self) -> CCR4SHIFTEN_W<4> {
CCR4SHIFTEN_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn ccr5shiften(&mut self) -> CCR5SHIFTEN_W<5> {
CCR5SHIFTEN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "PWM phase shift/DMA repeat update request enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pder](index.html) module"]
pub struct PDER_SPEC;
impl crate::RegisterSpec for PDER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [pder::R](R) reader structure"]
impl crate::Readable for PDER_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pder::W](W) writer structure"]
impl crate::Writable for PDER_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PDER to value 0"]
impl crate::Resettable for PDER_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCR1FALL (r) register accessor: an alias for `Reg<CCR1FALL_SPEC>`"]
pub type CCR1FALL = crate::Reg<ccr1fall::CCR1FALL_SPEC>;
#[doc = "PWM Phase Shift Down Count Capture/Compare Register"]
pub mod ccr1fall {
#[doc = "Register `CCR1FALL` reader"]
pub struct R(crate::R<CCR1FALL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCR1FALL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCR1FALL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCR1FALL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `CCRxFALL` reader - "]
pub type CCRX_FALL_R = crate::FieldReader<u16, u16>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn ccrx_fall(&self) -> CCRX_FALL_R {
CCRX_FALL_R::new((self.bits & 0xffff) as u16)
}
}
#[doc = "PWM Phase Shift Down Count Capture/Compare Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr1fall](index.html) module"]
pub struct CCR1FALL_SPEC;
impl crate::RegisterSpec for CCR1FALL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccr1fall::R](R) reader structure"]
impl crate::Readable for CCR1FALL_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets CCR1FALL to value 0"]
impl crate::Resettable for CCR1FALL_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
pub use ccr1fall as ccr2fall;
pub use ccr1fall as ccr3fall;
pub use ccr1fall as ccr4fall;
pub use ccr1fall as ccr5fall;
pub use CCR1FALL as CCR2FALL;
pub use CCR1FALL as CCR3FALL;
pub use CCR1FALL as CCR4FALL;
pub use CCR1FALL as CCR5FALL;
#[doc = "BKINF (rw) register accessor: an alias for `Reg<BKINF_SPEC>`"]
pub type BKINF = crate::Reg<bkinf::BKINF_SPEC>;
#[doc = "brake input filter register"]
pub mod bkinf {
#[doc = "Register `BKINF` reader"]
pub struct R(crate::R<BKINF_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<BKINF_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<BKINF_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<BKINF_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `BKINF` writer"]
pub struct W(crate::W<BKINF_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<BKINF_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<BKINF_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<BKINF_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `BKINFE` reader - "]
pub type BKINFE_R = crate::BitReader<bool>;
#[doc = "Field `BKINFE` writer - "]
pub type BKINFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, BKINF_SPEC, bool, O>;
#[doc = "Field `BKINF` reader - "]
pub type BKINF_R = crate::FieldReader<u8, u8>;
#[doc = "Field `BKINF` writer - "]
pub type BKINF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BKINF_SPEC, u8, u8, 4, O>;
#[doc = "Field `CSSBKINSEL` reader - "]
pub type CSSBKINSEL_R = crate::BitReader<bool>;
#[doc = "Field `CSSBKINSEL` writer - "]
pub type CSSBKINSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, BKINF_SPEC, bool, O>;
#[doc = "Field `IOBKINSEL` reader - "]
pub type IOBKINSEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IOBKINSEL` writer - "]
pub type IOBKINSEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, BKINF_SPEC, u8, u8, 4, O>;
#[doc = "Field `COMPBKINSEL` reader - "]
pub type COMPBKINSEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `COMPBKINSEL` writer - "]
pub type COMPBKINSEL_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, BKINF_SPEC, u8, u8, 3, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn bkinfe(&self) -> BKINFE_R {
BKINFE_R::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:4"]
#[inline(always)]
pub fn bkinf(&self) -> BKINF_R {
BKINF_R::new(((self.bits >> 1) & 0x0f) as u8)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn cssbkinsel(&self) -> CSSBKINSEL_R {
CSSBKINSEL_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:9"]
#[inline(always)]
pub fn iobkinsel(&self) -> IOBKINSEL_R {
IOBKINSEL_R::new(((self.bits >> 6) & 0x0f) as u8)
}
#[doc = "Bits 13:15"]
#[inline(always)]
pub fn compbkinsel(&self) -> COMPBKINSEL_R {
COMPBKINSEL_R::new(((self.bits >> 13) & 7) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn bkinfe(&mut self) -> BKINFE_W<0> {
BKINFE_W::new(self)
}
#[doc = "Bits 1:4"]
#[inline(always)]
#[must_use]
pub fn bkinf(&mut self) -> BKINF_W<1> {
BKINF_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn cssbkinsel(&mut self) -> CSSBKINSEL_W<5> {
CSSBKINSEL_W::new(self)
}
#[doc = "Bits 6:9"]
#[inline(always)]
#[must_use]
pub fn iobkinsel(&mut self) -> IOBKINSEL_W<6> {
IOBKINSEL_W::new(self)
}
#[doc = "Bits 13:15"]
#[inline(always)]
#[must_use]
pub fn compbkinsel(&mut self) -> COMPBKINSEL_W<13> {
COMPBKINSEL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "brake input filter register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bkinf](index.html) module"]
pub struct BKINF_SPEC;
impl crate::RegisterSpec for BKINF_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [bkinf::R](R) reader structure"]
impl crate::Readable for BKINF_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [bkinf::W](W) writer structure"]
impl crate::Writable for BKINF_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets BKINF to value 0"]
impl crate::Resettable for BKINF_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "TIM8"]
pub struct TIM8 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIM8 {}
impl TIM8 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const tim1::RegisterBlock = 0x4001_3400 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const tim1::RegisterBlock {
Self::PTR
}
}
impl Deref for TIM8 {
type Target = tim1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for TIM8 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM8").finish()
}
}
#[doc = "TIM8"]
pub use self::tim1 as tim8;
#[doc = "TIM2"]
pub struct TIM2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIM2 {}
impl TIM2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const tim2::RegisterBlock = 0x4000_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const tim2::RegisterBlock {
Self::PTR
}
}
impl Deref for TIM2 {
type Target = tim2::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for TIM2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM2").finish()
}
}
#[doc = "TIM2"]
pub mod tim2 {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Control Register 1"]
pub cr1: CR1,
#[doc = "0x04 - Control Register 2"]
pub cr2: CR2,
#[doc = "0x08 - Slave Mode Control Register"]
pub smcr: SMCR,
#[doc = "0x0c - DMA/Interrupt Enable Register"]
pub dier: DIER,
#[doc = "0x10 - status register"]
pub sr: SR,
#[doc = "0x14 - event generation register"]
pub egr: EGR,
_reserved_6_ccmr1: [u8; 0x04],
_reserved_7_ccmr2: [u8; 0x04],
#[doc = "0x20 - Capture/Compare Enable Register"]
pub ccer: CCER,
#[doc = "0x24 - counter"]
pub cnt: CNT,
#[doc = "0x28 - Prescaler"]
pub psc: PSC,
#[doc = "0x2c - autoload register"]
pub arr: ARR,
_reserved12: [u8; 0x04],
#[doc = "0x34 - Capture/Compare Register 1"]
pub ccr1: CCR1,
#[doc = "0x38 - Capture/Compare Register 1"]
pub ccr2: CCR2,
#[doc = "0x3c - Capture/Compare Register 1"]
pub ccr3: CCR3,
#[doc = "0x40 - Capture/Compare Register 1"]
pub ccr4: CCR4,
_reserved16: [u8; 0x04],
#[doc = "0x48 - DMA Control Register"]
pub dcr: DCR,
#[doc = "0x4c - DMA address for continuous mode"]
pub dmar: DMAR,
#[doc = "0x50 - TIMERx option register"]
pub or: OR,
}
impl RegisterBlock {
#[doc = "0x18 - Capture/Compare Mode Register 1"]
#[inline(always)]
pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
unsafe { &*(self as *const Self).cast::<u8>().add(24usize).cast() }
}
#[doc = "0x18 - Capture/Compare Mode Register 1"]
#[inline(always)]
pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
unsafe { &*(self as *const Self).cast::<u8>().add(24usize).cast() }
}
#[doc = "0x1c - Capture/Compare Mode Register 2"]
#[inline(always)]
pub const fn ccmr2_input(&self) -> &CCMR2_INPUT {
unsafe { &*(self as *const Self).cast::<u8>().add(28usize).cast() }
}
#[doc = "0x1c - Capture/Compare Mode Register 2"]
#[inline(always)]
pub const fn ccmr2_output(&self) -> &CCMR2_OUTPUT {
unsafe { &*(self as *const Self).cast::<u8>().add(28usize).cast() }
}
}
#[doc = "CR1 (rw) register accessor: an alias for `Reg<CR1_SPEC>`"]
pub type CR1 = crate::Reg<cr1::CR1_SPEC>;
#[doc = "Control Register 1"]
pub mod cr1 {
#[doc = "Register `CR1` reader"]
pub struct R(crate::R<CR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR1` writer"]
pub struct W(crate::W<CR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CEN` reader - "]
pub type CEN_R = crate::BitReader<bool>;
#[doc = "Field `CEN` writer - "]
pub type CEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `UDIS` reader - "]
pub type UDIS_R = crate::BitReader<bool>;
#[doc = "Field `UDIS` writer - "]
pub type UDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `URS` reader - "]
pub type URS_R = crate::BitReader<bool>;
#[doc = "Field `URS` writer - "]
pub type URS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `OPM` reader - "]
pub type OPM_R = crate::BitReader<bool>;
#[doc = "Field `OPM` writer - "]
pub type OPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `DIR` reader - "]
pub type DIR_R = crate::BitReader<bool>;
#[doc = "Field `DIR` writer - "]
pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `CMS` reader - "]
pub type CMS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CMS` writer - "]
pub type CMS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR1_SPEC, u8, u8, 2, O>;
#[doc = "Field `ARPE` reader - "]
pub type ARPE_R = crate::BitReader<bool>;
#[doc = "Field `ARPE` writer - "]
pub type ARPE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `CKD` reader - "]
pub type CKD_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CKD` writer - "]
pub type CKD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR1_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn cen(&self) -> CEN_R {
CEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn udis(&self) -> UDIS_R {
UDIS_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn urs(&self) -> URS_R {
URS_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn opm(&self) -> OPM_R {
OPM_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn dir(&self) -> DIR_R {
DIR_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6"]
#[inline(always)]
pub fn cms(&self) -> CMS_R {
CMS_R::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn arpe(&self) -> ARPE_R {
ARPE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn ckd(&self) -> CKD_R {
CKD_R::new(((self.bits >> 8) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn cen(&mut self) -> CEN_W<0> {
CEN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn udis(&mut self) -> UDIS_W<1> {
UDIS_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn urs(&mut self) -> URS_W<2> {
URS_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn opm(&mut self) -> OPM_W<3> {
OPM_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DIR_W<4> {
DIR_W::new(self)
}
#[doc = "Bits 5:6"]
#[inline(always)]
#[must_use]
pub fn cms(&mut self) -> CMS_W<5> {
CMS_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn arpe(&mut self) -> ARPE_W<7> {
ARPE_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn ckd(&mut self) -> CKD_W<8> {
CKD_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr1](index.html) module"]
pub struct CR1_SPEC;
impl crate::RegisterSpec for CR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr1::R](R) reader structure"]
impl crate::Readable for CR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr1::W](W) writer structure"]
impl crate::Writable for CR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for CR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CR2 (rw) register accessor: an alias for `Reg<CR2_SPEC>`"]
pub type CR2 = crate::Reg<cr2::CR2_SPEC>;
#[doc = "Control Register 2"]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub struct R(crate::R<CR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR2` writer"]
pub struct W(crate::W<CR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CCDS` reader - "]
pub type CCDS_R = crate::BitReader<bool>;
#[doc = "Field `CCDS` writer - "]
pub type CCDS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
#[doc = "Field `MMS` reader - "]
pub type MMS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MMS` writer - "]
pub type MMS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR2_SPEC, u8, u8, 3, O>;
#[doc = "Field `TI1S` reader - "]
pub type TI1S_R = crate::BitReader<bool>;
#[doc = "Field `TI1S` writer - "]
pub type TI1S_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
impl R {
#[doc = "Bit 3"]
#[inline(always)]
pub fn ccds(&self) -> CCDS_R {
CCDS_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn mms(&self) -> MMS_R {
MMS_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn ti1s(&self) -> TI1S_R {
TI1S_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn ccds(&mut self) -> CCDS_W<3> {
CCDS_W::new(self)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn mms(&mut self) -> MMS_W<4> {
MMS_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn ti1s(&mut self) -> TI1S_W<7> {
TI1S_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Control Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr2](index.html) module"]
pub struct CR2_SPEC;
impl crate::RegisterSpec for CR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr2::R](R) reader structure"]
impl crate::Readable for CR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr2::W](W) writer structure"]
impl crate::Writable for CR2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for CR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SMCR (rw) register accessor: an alias for `Reg<SMCR_SPEC>`"]
pub type SMCR = crate::Reg<smcr::SMCR_SPEC>;
#[doc = "Slave Mode Control Register"]
pub mod smcr {
#[doc = "Register `SMCR` reader"]
pub struct R(crate::R<SMCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SMCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SMCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SMCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SMCR` writer"]
pub struct W(crate::W<SMCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SMCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SMCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SMCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SMS` reader - "]
pub type SMS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMS` writer - "]
pub type SMS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SMCR_SPEC, u8, u8, 3, O>;
#[doc = "Field `OCCS` reader - "]
pub type OCCS_R = crate::BitReader<bool>;
#[doc = "Field `OCCS` writer - "]
pub type OCCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMCR_SPEC, bool, O>;
#[doc = "Field `TS` reader - "]
pub type TS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TS` writer - "]
pub type TS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SMCR_SPEC, u8, u8, 3, O>;
#[doc = "Field `MSM` reader - "]
pub type MSM_R = crate::BitReader<bool>;
#[doc = "Field `MSM` writer - "]
pub type MSM_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMCR_SPEC, bool, O>;
#[doc = "Field `ETF` reader - "]
pub type ETF_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ETF` writer - "]
pub type ETF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SMCR_SPEC, u8, u8, 4, O>;
#[doc = "Field `ETPS` reader - "]
pub type ETPS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ETPS` writer - "]
pub type ETPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `ECE` reader - "]
pub type ECE_R = crate::BitReader<bool>;
#[doc = "Field `ECE` writer - "]
pub type ECE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMCR_SPEC, bool, O>;
#[doc = "Field `ETP` reader - "]
pub type ETP_R = crate::BitReader<bool>;
#[doc = "Field `ETP` writer - "]
pub type ETP_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMCR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn sms(&self) -> SMS_R {
SMS_R::new((self.bits & 7) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn occs(&self) -> OCCS_R {
OCCS_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn ts(&self) -> TS_R {
TS_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn msm(&self) -> MSM_R {
MSM_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11"]
#[inline(always)]
pub fn etf(&self) -> ETF_R {
ETF_R::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bits 12:13"]
#[inline(always)]
pub fn etps(&self) -> ETPS_R {
ETPS_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn ece(&self) -> ECE_R {
ECE_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn etp(&self) -> ETP_R {
ETP_R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2"]
#[inline(always)]
#[must_use]
pub fn sms(&mut self) -> SMS_W<0> {
SMS_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn occs(&mut self) -> OCCS_W<3> {
OCCS_W::new(self)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn ts(&mut self) -> TS_W<4> {
TS_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn msm(&mut self) -> MSM_W<7> {
MSM_W::new(self)
}
#[doc = "Bits 8:11"]
#[inline(always)]
#[must_use]
pub fn etf(&mut self) -> ETF_W<8> {
ETF_W::new(self)
}
#[doc = "Bits 12:13"]
#[inline(always)]
#[must_use]
pub fn etps(&mut self) -> ETPS_W<12> {
ETPS_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn ece(&mut self) -> ECE_W<14> {
ECE_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn etp(&mut self) -> ETP_W<15> {
ETP_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Slave Mode Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smcr](index.html) module"]
pub struct SMCR_SPEC;
impl crate::RegisterSpec for SMCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [smcr::R](R) reader structure"]
impl crate::Readable for SMCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [smcr::W](W) writer structure"]
impl crate::Writable for SMCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SMCR to value 0"]
impl crate::Resettable for SMCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DIER (rw) register accessor: an alias for `Reg<DIER_SPEC>`"]
pub type DIER = crate::Reg<dier::DIER_SPEC>;
#[doc = "DMA/Interrupt Enable Register"]
pub mod dier {
#[doc = "Register `DIER` reader"]
pub struct R(crate::R<DIER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DIER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DIER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DIER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DIER` writer"]
pub struct W(crate::W<DIER_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DIER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DIER_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DIER_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `UIE` reader - "]
pub type UIE_R = crate::BitReader<bool>;
#[doc = "Field `UIE` writer - "]
pub type UIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC1IE` reader - "]
pub type CC1IE_R = crate::BitReader<bool>;
#[doc = "Field `CC1IE` writer - "]
pub type CC1IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC2IE` reader - "]
pub type CC2IE_R = crate::BitReader<bool>;
#[doc = "Field `CC2IE` writer - "]
pub type CC2IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC3IE` reader - "]
pub type CC3IE_R = crate::BitReader<bool>;
#[doc = "Field `CC3IE` writer - "]
pub type CC3IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC4IE` reader - "]
pub type CC4IE_R = crate::BitReader<bool>;
#[doc = "Field `CC4IE` writer - "]
pub type CC4IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `TIE` reader - "]
pub type TIE_R = crate::BitReader<bool>;
#[doc = "Field `TIE` writer - "]
pub type TIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `UDE` reader - "]
pub type UDE_R = crate::BitReader<bool>;
#[doc = "Field `UDE` writer - "]
pub type UDE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC1DE` reader - "]
pub type CC1DE_R = crate::BitReader<bool>;
#[doc = "Field `CC1DE` writer - "]
pub type CC1DE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC2DE` reader - "]
pub type CC2DE_R = crate::BitReader<bool>;
#[doc = "Field `CC2DE` writer - "]
pub type CC2DE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC3DE` reader - "]
pub type CC3DE_R = crate::BitReader<bool>;
#[doc = "Field `CC3DE` writer - "]
pub type CC3DE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC4DE` reader - "]
pub type CC4DE_R = crate::BitReader<bool>;
#[doc = "Field `CC4DE` writer - "]
pub type CC4DE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `TDE` reader - "]
pub type TDE_R = crate::BitReader<bool>;
#[doc = "Field `TDE` writer - "]
pub type TDE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn uie(&self) -> UIE_R {
UIE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn cc1ie(&self) -> CC1IE_R {
CC1IE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn cc2ie(&self) -> CC2IE_R {
CC2IE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn cc3ie(&self) -> CC3IE_R {
CC3IE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn cc4ie(&self) -> CC4IE_R {
CC4IE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tie(&self) -> TIE_R {
TIE_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn ude(&self) -> UDE_R {
UDE_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn cc1de(&self) -> CC1DE_R {
CC1DE_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn cc2de(&self) -> CC2DE_R {
CC2DE_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn cc3de(&self) -> CC3DE_R {
CC3DE_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn cc4de(&self) -> CC4DE_R {
CC4DE_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn tde(&self) -> TDE_R {
TDE_R::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn uie(&mut self) -> UIE_W<0> {
UIE_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn cc1ie(&mut self) -> CC1IE_W<1> {
CC1IE_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn cc2ie(&mut self) -> CC2IE_W<2> {
CC2IE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn cc3ie(&mut self) -> CC3IE_W<3> {
CC3IE_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn cc4ie(&mut self) -> CC4IE_W<4> {
CC4IE_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tie(&mut self) -> TIE_W<6> {
TIE_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn ude(&mut self) -> UDE_W<8> {
UDE_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn cc1de(&mut self) -> CC1DE_W<9> {
CC1DE_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn cc2de(&mut self) -> CC2DE_W<10> {
CC2DE_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn cc3de(&mut self) -> CC3DE_W<11> {
CC3DE_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn cc4de(&mut self) -> CC4DE_W<12> {
CC4DE_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn tde(&mut self) -> TDE_W<14> {
TDE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA/Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dier](index.html) module"]
pub struct DIER_SPEC;
impl crate::RegisterSpec for DIER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dier::R](R) reader structure"]
impl crate::Readable for DIER_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dier::W](W) writer structure"]
impl crate::Writable for DIER_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DIER to value 0"]
impl crate::Resettable for DIER_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SR (rw) register accessor: an alias for `Reg<SR_SPEC>`"]
pub type SR = crate::Reg<sr::SR_SPEC>;
#[doc = "status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub struct R(crate::R<SR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SR` writer"]
pub struct W(crate::W<SR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `UIF` reader - "]
pub type UIF_R = crate::BitReader<bool>;
#[doc = "Field `UIF` writer - "]
pub type UIF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC1IF` reader - "]
pub type CC1IF_R = crate::BitReader<bool>;
#[doc = "Field `CC1IF` writer - "]
pub type CC1IF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC2IF` reader - "]
pub type CC2IF_R = crate::BitReader<bool>;
#[doc = "Field `CC2IF` writer - "]
pub type CC2IF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC3IF` reader - "]
pub type CC3IF_R = crate::BitReader<bool>;
#[doc = "Field `CC3IF` writer - "]
pub type CC3IF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC4IF` reader - "]
pub type CC4IF_R = crate::BitReader<bool>;
#[doc = "Field `CC4IF` writer - "]
pub type CC4IF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `TIF` reader - "]
pub type TIF_R = crate::BitReader<bool>;
#[doc = "Field `TIF` writer - "]
pub type TIF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC1OF` reader - "]
pub type CC1OF_R = crate::BitReader<bool>;
#[doc = "Field `CC1OF` writer - "]
pub type CC1OF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC2OF` reader - "]
pub type CC2OF_R = crate::BitReader<bool>;
#[doc = "Field `CC2OF` writer - "]
pub type CC2OF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC3OF` reader - "]
pub type CC3OF_R = crate::BitReader<bool>;
#[doc = "Field `CC3OF` writer - "]
pub type CC3OF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC4OF` reader - "]
pub type CC4OF_R = crate::BitReader<bool>;
#[doc = "Field `CC4OF` writer - "]
pub type CC4OF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn uif(&self) -> UIF_R {
UIF_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn cc1if(&self) -> CC1IF_R {
CC1IF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn cc2if(&self) -> CC2IF_R {
CC2IF_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn cc3if(&self) -> CC3IF_R {
CC3IF_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn cc4if(&self) -> CC4IF_R {
CC4IF_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tif(&self) -> TIF_R {
TIF_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn cc1of(&self) -> CC1OF_R {
CC1OF_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn cc2of(&self) -> CC2OF_R {
CC2OF_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn cc3of(&self) -> CC3OF_R {
CC3OF_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn cc4of(&self) -> CC4OF_R {
CC4OF_R::new(((self.bits >> 12) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn uif(&mut self) -> UIF_W<0> {
UIF_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn cc1if(&mut self) -> CC1IF_W<1> {
CC1IF_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn cc2if(&mut self) -> CC2IF_W<2> {
CC2IF_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn cc3if(&mut self) -> CC3IF_W<3> {
CC3IF_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn cc4if(&mut self) -> CC4IF_W<4> {
CC4IF_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tif(&mut self) -> TIF_W<6> {
TIF_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn cc1of(&mut self) -> CC1OF_W<9> {
CC1OF_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn cc2of(&mut self) -> CC2OF_W<10> {
CC2OF_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn cc3of(&mut self) -> CC3OF_W<11> {
CC3OF_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn cc4of(&mut self) -> CC4OF_W<12> {
CC4OF_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"]
pub struct SR_SPEC;
impl crate::RegisterSpec for SR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [sr::R](R) reader structure"]
impl crate::Readable for SR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [sr::W](W) writer structure"]
impl crate::Writable for SR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x1e5f;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "EGR (w) register accessor: an alias for `Reg<EGR_SPEC>`"]
pub type EGR = crate::Reg<egr::EGR_SPEC>;
#[doc = "event generation register"]
pub mod egr {
#[doc = "Register `EGR` writer"]
pub struct W(crate::W<EGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<EGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<EGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<EGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `UG` writer - "]
pub type UG_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `CC1G` writer - "]
pub type CC1G_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `CC2G` writer - "]
pub type CC2G_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `CC3G` writer - "]
pub type CC3G_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `CC4G` writer - "]
pub type CC4G_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `COMG` writer - "]
pub type COMG_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `TG` writer - "]
pub type TG_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn ug(&mut self) -> UG_W<0> {
UG_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn cc1g(&mut self) -> CC1G_W<1> {
CC1G_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn cc2g(&mut self) -> CC2G_W<2> {
CC2G_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn cc3g(&mut self) -> CC3G_W<3> {
CC3G_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn cc4g(&mut self) -> CC4G_W<4> {
CC4G_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn comg(&mut self) -> COMG_W<5> {
COMG_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tg(&mut self) -> TG_W<6> {
TG_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "event generation register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [egr](index.html) module"]
pub struct EGR_SPEC;
impl crate::RegisterSpec for EGR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [egr::W](W) writer structure"]
impl crate::Writable for EGR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets EGR to value 0"]
impl crate::Resettable for EGR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCMR1_Output (rw) register accessor: an alias for `Reg<CCMR1_OUTPUT_SPEC>`"]
pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUT_SPEC>;
#[doc = "Capture/Compare Mode Register 1"]
pub mod ccmr1_output {
#[doc = "Register `CCMR1_Output` reader"]
pub struct R(crate::R<CCMR1_OUTPUT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCMR1_OUTPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCMR1_OUTPUT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCMR1_OUTPUT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCMR1_Output` writer"]
pub struct W(crate::W<CCMR1_OUTPUT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCMR1_OUTPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCMR1_OUTPUT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCMR1_OUTPUT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CC1S` reader - "]
pub type CC1S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC1S` writer - "]
pub type CC1S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `OC1FE` reader - "]
pub type OC1FE_R = crate::BitReader<bool>;
#[doc = "Field `OC1FE` writer - "]
pub type OC1FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC1PE` reader - "]
pub type OC1PE_R = crate::BitReader<bool>;
#[doc = "Field `OC1PE` writer - "]
pub type OC1PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC1M` reader - "]
pub type OC1M_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OC1M` writer - "]
pub type OC1M_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, u8, 3, O>;
#[doc = "Field `OC1CE` reader - "]
pub type OC1CE_R = crate::BitReader<bool>;
#[doc = "Field `OC1CE` writer - "]
pub type OC1CE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `CC2S` reader - "]
pub type CC2S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC2S` writer - "]
pub type CC2S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `OC2FE` reader - "]
pub type OC2FE_R = crate::BitReader<bool>;
#[doc = "Field `OC2FE` writer - "]
pub type OC2FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC2PE` reader - "]
pub type OC2PE_R = crate::BitReader<bool>;
#[doc = "Field `OC2PE` writer - "]
pub type OC2PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC2M` reader - "]
pub type OC2M_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OC2M` writer - "]
pub type OC2M_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, u8, 3, O>;
#[doc = "Field `OC2CE` reader - "]
pub type OC2CE_R = crate::BitReader<bool>;
#[doc = "Field `OC2CE` writer - "]
pub type OC2CE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn cc1s(&self) -> CC1S_R {
CC1S_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn oc1fe(&self) -> OC1FE_R {
OC1FE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn oc1pe(&self) -> OC1PE_R {
OC1PE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn oc1m(&self) -> OC1M_R {
OC1M_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn oc1ce(&self) -> OC1CE_R {
OC1CE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn cc2s(&self) -> CC2S_R {
CC2S_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn oc2fe(&self) -> OC2FE_R {
OC2FE_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn oc2pe(&self) -> OC2PE_R {
OC2PE_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:14"]
#[inline(always)]
pub fn oc2m(&self) -> OC2M_R {
OC2M_R::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn oc2ce(&self) -> OC2CE_R {
OC2CE_R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn cc1s(&mut self) -> CC1S_W<0> {
CC1S_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn oc1fe(&mut self) -> OC1FE_W<2> {
OC1FE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn oc1pe(&mut self) -> OC1PE_W<3> {
OC1PE_W::new(self)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn oc1m(&mut self) -> OC1M_W<4> {
OC1M_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn oc1ce(&mut self) -> OC1CE_W<7> {
OC1CE_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn cc2s(&mut self) -> CC2S_W<8> {
CC2S_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn oc2fe(&mut self) -> OC2FE_W<10> {
OC2FE_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn oc2pe(&mut self) -> OC2PE_W<11> {
OC2PE_W::new(self)
}
#[doc = "Bits 12:14"]
#[inline(always)]
#[must_use]
pub fn oc2m(&mut self) -> OC2M_W<12> {
OC2M_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn oc2ce(&mut self) -> OC2CE_W<15> {
OC2CE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Mode Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr1_output](index.html) module"]
pub struct CCMR1_OUTPUT_SPEC;
impl crate::RegisterSpec for CCMR1_OUTPUT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccmr1_output::R](R) reader structure"]
impl crate::Readable for CCMR1_OUTPUT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccmr1_output::W](W) writer structure"]
impl crate::Writable for CCMR1_OUTPUT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCMR1_Output to value 0"]
impl crate::Resettable for CCMR1_OUTPUT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCMR1_Input (rw) register accessor: an alias for `Reg<CCMR1_INPUT_SPEC>`"]
pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUT_SPEC>;
#[doc = "Capture/Compare Mode Register 1"]
pub mod ccmr1_input {
#[doc = "Register `CCMR1_Input` reader"]
pub struct R(crate::R<CCMR1_INPUT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCMR1_INPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCMR1_INPUT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCMR1_INPUT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCMR1_Input` writer"]
pub struct W(crate::W<CCMR1_INPUT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCMR1_INPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCMR1_INPUT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCMR1_INPUT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CC1S` reader - "]
pub type CC1S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC1S` writer - "]
pub type CC1S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC1PSC` reader - "]
pub type IC1PSC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC1PSC` writer - "]
pub type IC1PSC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC1F` reader - "]
pub type IC1F_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC1F` writer - "]
pub type IC1F_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 4, O>;
#[doc = "Field `CC2S` reader - "]
pub type CC2S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC2S` writer - "]
pub type CC2S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC2PSC` reader - "]
pub type IC2PSC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC2PSC` writer - "]
pub type IC2PSC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC2F` reader - "]
pub type IC2F_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC2F` writer - "]
pub type IC2F_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 4, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn cc1s(&self) -> CC1S_R {
CC1S_R::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3"]
#[inline(always)]
pub fn ic1psc(&self) -> IC1PSC_R {
IC1PSC_R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn ic1f(&self) -> IC1F_R {
IC1F_R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn cc2s(&self) -> CC2S_R {
CC2S_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11"]
#[inline(always)]
pub fn ic2psc(&self) -> IC2PSC_R {
IC2PSC_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:15"]
#[inline(always)]
pub fn ic2f(&self) -> IC2F_R {
IC2F_R::new(((self.bits >> 12) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn cc1s(&mut self) -> CC1S_W<0> {
CC1S_W::new(self)
}
#[doc = "Bits 2:3"]
#[inline(always)]
#[must_use]
pub fn ic1psc(&mut self) -> IC1PSC_W<2> {
IC1PSC_W::new(self)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn ic1f(&mut self) -> IC1F_W<4> {
IC1F_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn cc2s(&mut self) -> CC2S_W<8> {
CC2S_W::new(self)
}
#[doc = "Bits 10:11"]
#[inline(always)]
#[must_use]
pub fn ic2psc(&mut self) -> IC2PSC_W<10> {
IC2PSC_W::new(self)
}
#[doc = "Bits 12:15"]
#[inline(always)]
#[must_use]
pub fn ic2f(&mut self) -> IC2F_W<12> {
IC2F_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Mode Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr1_input](index.html) module"]
pub struct CCMR1_INPUT_SPEC;
impl crate::RegisterSpec for CCMR1_INPUT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccmr1_input::R](R) reader structure"]
impl crate::Readable for CCMR1_INPUT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccmr1_input::W](W) writer structure"]
impl crate::Writable for CCMR1_INPUT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCMR1_Input to value 0"]
impl crate::Resettable for CCMR1_INPUT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCMR2_Output (rw) register accessor: an alias for `Reg<CCMR2_OUTPUT_SPEC>`"]
pub type CCMR2_OUTPUT = crate::Reg<ccmr2_output::CCMR2_OUTPUT_SPEC>;
#[doc = "Capture/Compare Mode Register 2"]
pub mod ccmr2_output {
#[doc = "Register `CCMR2_Output` reader"]
pub struct R(crate::R<CCMR2_OUTPUT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCMR2_OUTPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCMR2_OUTPUT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCMR2_OUTPUT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCMR2_Output` writer"]
pub struct W(crate::W<CCMR2_OUTPUT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCMR2_OUTPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCMR2_OUTPUT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCMR2_OUTPUT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CC3S` reader - "]
pub type CC3S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC3S` writer - "]
pub type CC3S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_OUTPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `OC3FE` reader - "]
pub type OC3FE_R = crate::BitReader<bool>;
#[doc = "Field `OC3FE` writer - "]
pub type OC3FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC3PE` reader - "]
pub type OC3PE_R = crate::BitReader<bool>;
#[doc = "Field `OC3PE` writer - "]
pub type OC3PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC3M` reader - "]
pub type OC3M_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OC3M` writer - "]
pub type OC3M_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_OUTPUT_SPEC, u8, u8, 3, O>;
#[doc = "Field `OC3CE` reader - "]
pub type OC3CE_R = crate::BitReader<bool>;
#[doc = "Field `OC3CE` writer - "]
pub type OC3CE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
#[doc = "Field `CC4S` reader - "]
pub type CC4S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC4S` writer - "]
pub type CC4S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_OUTPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `OC4FE` reader - "]
pub type OC4FE_R = crate::BitReader<bool>;
#[doc = "Field `OC4FE` writer - "]
pub type OC4FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC4PE` reader - "]
pub type OC4PE_R = crate::BitReader<bool>;
#[doc = "Field `OC4PE` writer - "]
pub type OC4PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC4M` reader - "]
pub type OC4M_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OC4M` writer - "]
pub type OC4M_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_OUTPUT_SPEC, u8, u8, 3, O>;
#[doc = "Field `OC4CE` reader - "]
pub type OC4CE_R = crate::BitReader<bool>;
#[doc = "Field `OC4CE` writer - "]
pub type OC4CE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn cc3s(&self) -> CC3S_R {
CC3S_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn oc3fe(&self) -> OC3FE_R {
OC3FE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn oc3pe(&self) -> OC3PE_R {
OC3PE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn oc3m(&self) -> OC3M_R {
OC3M_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn oc3ce(&self) -> OC3CE_R {
OC3CE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn cc4s(&self) -> CC4S_R {
CC4S_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn oc4fe(&self) -> OC4FE_R {
OC4FE_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn oc4pe(&self) -> OC4PE_R {
OC4PE_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:14"]
#[inline(always)]
pub fn oc4m(&self) -> OC4M_R {
OC4M_R::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn oc4ce(&self) -> OC4CE_R {
OC4CE_R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn cc3s(&mut self) -> CC3S_W<0> {
CC3S_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn oc3fe(&mut self) -> OC3FE_W<2> {
OC3FE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn oc3pe(&mut self) -> OC3PE_W<3> {
OC3PE_W::new(self)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn oc3m(&mut self) -> OC3M_W<4> {
OC3M_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn oc3ce(&mut self) -> OC3CE_W<7> {
OC3CE_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn cc4s(&mut self) -> CC4S_W<8> {
CC4S_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn oc4fe(&mut self) -> OC4FE_W<10> {
OC4FE_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn oc4pe(&mut self) -> OC4PE_W<11> {
OC4PE_W::new(self)
}
#[doc = "Bits 12:14"]
#[inline(always)]
#[must_use]
pub fn oc4m(&mut self) -> OC4M_W<12> {
OC4M_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn oc4ce(&mut self) -> OC4CE_W<15> {
OC4CE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Mode Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr2_output](index.html) module"]
pub struct CCMR2_OUTPUT_SPEC;
impl crate::RegisterSpec for CCMR2_OUTPUT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccmr2_output::R](R) reader structure"]
impl crate::Readable for CCMR2_OUTPUT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccmr2_output::W](W) writer structure"]
impl crate::Writable for CCMR2_OUTPUT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCMR2_Output to value 0"]
impl crate::Resettable for CCMR2_OUTPUT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCMR2_Input (rw) register accessor: an alias for `Reg<CCMR2_INPUT_SPEC>`"]
pub type CCMR2_INPUT = crate::Reg<ccmr2_input::CCMR2_INPUT_SPEC>;
#[doc = "Capture/Compare Mode Register 2"]
pub mod ccmr2_input {
#[doc = "Register `CCMR2_Input` reader"]
pub struct R(crate::R<CCMR2_INPUT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCMR2_INPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCMR2_INPUT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCMR2_INPUT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCMR2_Input` writer"]
pub struct W(crate::W<CCMR2_INPUT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCMR2_INPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCMR2_INPUT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCMR2_INPUT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CC3S` reader - "]
pub type CC3S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC3S` writer - "]
pub type CC3S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC3PSC` reader - "]
pub type IC3PSC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC3PSC` writer - "]
pub type IC3PSC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC3F` reader - "]
pub type IC3F_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC3F` writer - "]
pub type IC3F_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 4, O>;
#[doc = "Field `CC4S` reader - "]
pub type CC4S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC4S` writer - "]
pub type CC4S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC4PSC` reader - "]
pub type IC4PSC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC4PSC` writer - "]
pub type IC4PSC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC4F` reader - "]
pub type IC4F_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC4F` writer - "]
pub type IC4F_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 4, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn cc3s(&self) -> CC3S_R {
CC3S_R::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3"]
#[inline(always)]
pub fn ic3psc(&self) -> IC3PSC_R {
IC3PSC_R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn ic3f(&self) -> IC3F_R {
IC3F_R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn cc4s(&self) -> CC4S_R {
CC4S_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11"]
#[inline(always)]
pub fn ic4psc(&self) -> IC4PSC_R {
IC4PSC_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:15"]
#[inline(always)]
pub fn ic4f(&self) -> IC4F_R {
IC4F_R::new(((self.bits >> 12) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn cc3s(&mut self) -> CC3S_W<0> {
CC3S_W::new(self)
}
#[doc = "Bits 2:3"]
#[inline(always)]
#[must_use]
pub fn ic3psc(&mut self) -> IC3PSC_W<2> {
IC3PSC_W::new(self)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn ic3f(&mut self) -> IC3F_W<4> {
IC3F_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn cc4s(&mut self) -> CC4S_W<8> {
CC4S_W::new(self)
}
#[doc = "Bits 10:11"]
#[inline(always)]
#[must_use]
pub fn ic4psc(&mut self) -> IC4PSC_W<10> {
IC4PSC_W::new(self)
}
#[doc = "Bits 12:15"]
#[inline(always)]
#[must_use]
pub fn ic4f(&mut self) -> IC4F_W<12> {
IC4F_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Mode Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr2_input](index.html) module"]
pub struct CCMR2_INPUT_SPEC;
impl crate::RegisterSpec for CCMR2_INPUT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccmr2_input::R](R) reader structure"]
impl crate::Readable for CCMR2_INPUT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccmr2_input::W](W) writer structure"]
impl crate::Writable for CCMR2_INPUT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCMR2_Input to value 0"]
impl crate::Resettable for CCMR2_INPUT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCER (rw) register accessor: an alias for `Reg<CCER_SPEC>`"]
pub type CCER = crate::Reg<ccer::CCER_SPEC>;
#[doc = "Capture/Compare Enable Register"]
pub mod ccer {
#[doc = "Register `CCER` reader"]
pub struct R(crate::R<CCER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCER` writer"]
pub struct W(crate::W<CCER_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCER_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCER_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CC1E` reader - "]
pub type CC1E_R = crate::BitReader<bool>;
#[doc = "Field `CC1E` writer - "]
pub type CC1E_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC1P` reader - "]
pub type CC1P_R = crate::BitReader<bool>;
#[doc = "Field `CC1P` writer - "]
pub type CC1P_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC1NP` reader - "]
pub type CC1NP_R = crate::BitReader<bool>;
#[doc = "Field `CC1NP` writer - "]
pub type CC1NP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC2E` reader - "]
pub type CC2E_R = crate::BitReader<bool>;
#[doc = "Field `CC2E` writer - "]
pub type CC2E_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC2P` reader - "]
pub type CC2P_R = crate::BitReader<bool>;
#[doc = "Field `CC2P` writer - "]
pub type CC2P_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC2NP` reader - "]
pub type CC2NP_R = crate::BitReader<bool>;
#[doc = "Field `CC2NP` writer - "]
pub type CC2NP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC3E` reader - "]
pub type CC3E_R = crate::BitReader<bool>;
#[doc = "Field `CC3E` writer - "]
pub type CC3E_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC3P` reader - "]
pub type CC3P_R = crate::BitReader<bool>;
#[doc = "Field `CC3P` writer - "]
pub type CC3P_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC3NP` reader - "]
pub type CC3NP_R = crate::BitReader<bool>;
#[doc = "Field `CC3NP` writer - "]
pub type CC3NP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC4E` reader - "]
pub type CC4E_R = crate::BitReader<bool>;
#[doc = "Field `CC4E` writer - "]
pub type CC4E_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC4P` reader - "]
pub type CC4P_R = crate::BitReader<bool>;
#[doc = "Field `CC4P` writer - "]
pub type CC4P_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC4NP` reader - "]
pub type CC4NP_R = crate::BitReader<bool>;
#[doc = "Field `CC4NP` writer - "]
pub type CC4NP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn cc1e(&self) -> CC1E_R {
CC1E_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn cc1p(&self) -> CC1P_R {
CC1P_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn cc1np(&self) -> CC1NP_R {
CC1NP_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn cc2e(&self) -> CC2E_R {
CC2E_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn cc2p(&self) -> CC2P_R {
CC2P_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn cc2np(&self) -> CC2NP_R {
CC2NP_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn cc3e(&self) -> CC3E_R {
CC3E_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn cc3p(&self) -> CC3P_R {
CC3P_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn cc3np(&self) -> CC3NP_R {
CC3NP_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn cc4e(&self) -> CC4E_R {
CC4E_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn cc4p(&self) -> CC4P_R {
CC4P_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn cc4np(&self) -> CC4NP_R {
CC4NP_R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn cc1e(&mut self) -> CC1E_W<0> {
CC1E_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn cc1p(&mut self) -> CC1P_W<1> {
CC1P_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn cc1np(&mut self) -> CC1NP_W<3> {
CC1NP_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn cc2e(&mut self) -> CC2E_W<4> {
CC2E_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn cc2p(&mut self) -> CC2P_W<5> {
CC2P_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn cc2np(&mut self) -> CC2NP_W<7> {
CC2NP_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn cc3e(&mut self) -> CC3E_W<8> {
CC3E_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn cc3p(&mut self) -> CC3P_W<9> {
CC3P_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn cc3np(&mut self) -> CC3NP_W<11> {
CC3NP_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn cc4e(&mut self) -> CC4E_W<12> {
CC4E_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn cc4p(&mut self) -> CC4P_W<13> {
CC4P_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn cc4np(&mut self) -> CC4NP_W<15> {
CC4NP_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccer](index.html) module"]
pub struct CCER_SPEC;
impl crate::RegisterSpec for CCER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccer::R](R) reader structure"]
impl crate::Readable for CCER_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccer::W](W) writer structure"]
impl crate::Writable for CCER_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCER to value 0"]
impl crate::Resettable for CCER_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CNT (rw) register accessor: an alias for `Reg<CNT_SPEC>`"]
pub type CNT = crate::Reg<cnt::CNT_SPEC>;
#[doc = "counter"]
pub mod cnt {
#[doc = "Register `CNT` reader"]
pub struct R(crate::R<CNT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CNT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CNT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CNT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CNT` writer"]
pub struct W(crate::W<CNT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CNT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CNT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CNT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CNT` reader - "]
pub type CNT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CNT` writer - "]
pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNT_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn cnt(&self) -> CNT_R {
CNT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CNT_W<0> {
CNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnt](index.html) module"]
pub struct CNT_SPEC;
impl crate::RegisterSpec for CNT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cnt::R](R) reader structure"]
impl crate::Readable for CNT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cnt::W](W) writer structure"]
impl crate::Writable for CNT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CNT to value 0"]
impl crate::Resettable for CNT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PSC (rw) register accessor: an alias for `Reg<PSC_SPEC>`"]
pub type PSC = crate::Reg<psc::PSC_SPEC>;
#[doc = "Prescaler"]
pub mod psc {
#[doc = "Register `PSC` reader"]
pub struct R(crate::R<PSC_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PSC_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PSC_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PSC_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PSC` writer"]
pub struct W(crate::W<PSC_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PSC_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PSC_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PSC_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PSC` reader - "]
pub type PSC_R = crate::FieldReader<u16, u16>;
#[doc = "Field `PSC` writer - "]
pub type PSC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PSC_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn psc(&self) -> PSC_R {
PSC_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn psc(&mut self) -> PSC_W<0> {
PSC_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [psc](index.html) module"]
pub struct PSC_SPEC;
impl crate::RegisterSpec for PSC_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [psc::R](R) reader structure"]
impl crate::Readable for PSC_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [psc::W](W) writer structure"]
impl crate::Writable for PSC_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PSC to value 0"]
impl crate::Resettable for PSC_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ARR (rw) register accessor: an alias for `Reg<ARR_SPEC>`"]
pub type ARR = crate::Reg<arr::ARR_SPEC>;
#[doc = "autoload register"]
pub mod arr {
#[doc = "Register `ARR` reader"]
pub struct R(crate::R<ARR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ARR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ARR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ARR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ARR` writer"]
pub struct W(crate::W<ARR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ARR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ARR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ARR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `ARR` reader - "]
pub type ARR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `ARR` writer - "]
pub type ARR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ARR_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn arr(&self) -> ARR_R {
ARR_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn arr(&mut self) -> ARR_W<0> {
ARR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "autoload register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arr](index.html) module"]
pub struct ARR_SPEC;
impl crate::RegisterSpec for ARR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [arr::R](R) reader structure"]
impl crate::Readable for ARR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [arr::W](W) writer structure"]
impl crate::Writable for ARR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ARR to value 0"]
impl crate::Resettable for ARR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCR1 (rw) register accessor: an alias for `Reg<CCR1_SPEC>`"]
pub type CCR1 = crate::Reg<ccr1::CCR1_SPEC>;
#[doc = "Capture/Compare Register 1"]
pub mod ccr1 {
#[doc = "Register `CCR1` reader"]
pub struct R(crate::R<CCR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCR1` writer"]
pub struct W(crate::W<CCR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CCR` reader - "]
pub type CCR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CCR` writer - "]
pub type CCR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCR1_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn ccr(&self) -> CCR_R {
CCR_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn ccr(&mut self) -> CCR_W<0> {
CCR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr1](index.html) module"]
pub struct CCR1_SPEC;
impl crate::RegisterSpec for CCR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccr1::R](R) reader structure"]
impl crate::Readable for CCR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccr1::W](W) writer structure"]
impl crate::Writable for CCR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCR1 to value 0"]
impl crate::Resettable for CCR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
pub use ccr1 as ccr2;
pub use ccr1 as ccr3;
pub use ccr1 as ccr4;
pub use CCR1 as CCR2;
pub use CCR1 as CCR3;
pub use CCR1 as CCR4;
#[doc = "DCR (rw) register accessor: an alias for `Reg<DCR_SPEC>`"]
pub type DCR = crate::Reg<dcr::DCR_SPEC>;
#[doc = "DMA Control Register"]
pub mod dcr {
#[doc = "Register `DCR` reader"]
pub struct R(crate::R<DCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DCR` writer"]
pub struct W(crate::W<DCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DBA` reader - "]
pub type DBA_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DBA` writer - "]
pub type DBA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCR_SPEC, u8, u8, 5, O>;
#[doc = "Field `DBL` reader - "]
pub type DBL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DBL` writer - "]
pub type DBL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCR_SPEC, u8, u8, 5, O>;
impl R {
#[doc = "Bits 0:4"]
#[inline(always)]
pub fn dba(&self) -> DBA_R {
DBA_R::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 8:12"]
#[inline(always)]
pub fn dbl(&self) -> DBL_R {
DBL_R::new(((self.bits >> 8) & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:4"]
#[inline(always)]
#[must_use]
pub fn dba(&mut self) -> DBA_W<0> {
DBA_W::new(self)
}
#[doc = "Bits 8:12"]
#[inline(always)]
#[must_use]
pub fn dbl(&mut self) -> DBL_W<8> {
DBL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcr](index.html) module"]
pub struct DCR_SPEC;
impl crate::RegisterSpec for DCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dcr::R](R) reader structure"]
impl crate::Readable for DCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dcr::W](W) writer structure"]
impl crate::Writable for DCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DCR to value 0"]
impl crate::Resettable for DCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMAR (w) register accessor: an alias for `Reg<DMAR_SPEC>`"]
pub type DMAR = crate::Reg<dmar::DMAR_SPEC>;
#[doc = "DMA address for continuous mode"]
pub mod dmar {
#[doc = "Register `DMAR` writer"]
pub struct W(crate::W<DMAR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DMAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DMAR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DMAR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DMAB` writer - "]
pub type DMAB_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMAR_SPEC, u16, u16, 16, O>;
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn dmab(&mut self) -> DMAB_W<0> {
DMAB_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA address for continuous mode\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmar](index.html) module"]
pub struct DMAR_SPEC;
impl crate::RegisterSpec for DMAR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [dmar::W](W) writer structure"]
impl crate::Writable for DMAR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DMAR to value 0"]
impl crate::Resettable for DMAR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "OR (rw) register accessor: an alias for `Reg<OR_SPEC>`"]
pub type OR = crate::Reg<or::OR_SPEC>;
#[doc = "TIMERx option register"]
pub mod or {
#[doc = "Register `OR` reader"]
pub struct R(crate::R<OR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<OR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<OR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<OR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `OR` writer"]
pub struct W(crate::W<OR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<OR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<OR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<OR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `ETR_RMP` reader - "]
pub type ETR_RMP_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ETR_RMP` writer - "]
pub type ETR_RMP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OR_SPEC, u8, u8, 3, O>;
#[doc = "Field `TI4_RMP` reader - "]
pub type TI4_RMP_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TI4_RMP` writer - "]
pub type TI4_RMP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OR_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn etr_rmp(&self) -> ETR_RMP_R {
ETR_RMP_R::new((self.bits & 7) as u8)
}
#[doc = "Bits 6:7"]
#[inline(always)]
pub fn ti4_rmp(&self) -> TI4_RMP_R {
TI4_RMP_R::new(((self.bits >> 6) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:2"]
#[inline(always)]
#[must_use]
pub fn etr_rmp(&mut self) -> ETR_RMP_W<0> {
ETR_RMP_W::new(self)
}
#[doc = "Bits 6:7"]
#[inline(always)]
#[must_use]
pub fn ti4_rmp(&mut self) -> TI4_RMP_W<6> {
TI4_RMP_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "TIMERx option register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [or](index.html) module"]
pub struct OR_SPEC;
impl crate::RegisterSpec for OR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [or::R](R) reader structure"]
impl crate::Readable for OR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [or::W](W) writer structure"]
impl crate::Writable for OR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets OR to value 0"]
impl crate::Resettable for OR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "TIM5"]
pub struct TIM5 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIM5 {}
impl TIM5 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const tim2::RegisterBlock = 0x4000_0c00 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const tim2::RegisterBlock {
Self::PTR
}
}
impl Deref for TIM5 {
type Target = tim2::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for TIM5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM5").finish()
}
}
#[doc = "TIM5"]
pub use self::tim2 as tim5;
#[doc = "TIM3"]
pub struct TIM3 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIM3 {}
impl TIM3 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const tim3::RegisterBlock = 0x4000_0400 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const tim3::RegisterBlock {
Self::PTR
}
}
impl Deref for TIM3 {
type Target = tim3::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for TIM3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM3").finish()
}
}
#[doc = "TIM3"]
pub mod tim3 {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Control Register 1"]
pub cr1: CR1,
#[doc = "0x04 - Control Register 2"]
pub cr2: CR2,
#[doc = "0x08 - Slave Mode Control Register"]
pub smcr: SMCR,
#[doc = "0x0c - DMA/Interrupt Enable Register"]
pub dier: DIER,
#[doc = "0x10 - status register"]
pub sr: SR,
#[doc = "0x14 - event generation register"]
pub egr: EGR,
_reserved_6_ccmr1: [u8; 0x04],
_reserved_7_ccmr2: [u8; 0x04],
#[doc = "0x20 - Capture/Compare Enable Register"]
pub ccer: CCER,
#[doc = "0x24 - counter"]
pub cnt: CNT,
#[doc = "0x28 - Prescaler"]
pub psc: PSC,
#[doc = "0x2c - autoload register"]
pub arr: ARR,
_reserved12: [u8; 0x04],
#[doc = "0x34 - Capture/Compare Register 1"]
pub ccr1: CCR1,
#[doc = "0x38 - Capture/Compare Register 1"]
pub ccr2: CCR2,
#[doc = "0x3c - Capture/Compare Register 1"]
pub ccr3: CCR3,
#[doc = "0x40 - Capture/Compare Register 1"]
pub ccr4: CCR4,
_reserved16: [u8; 0x04],
#[doc = "0x48 - DMA Control Register"]
pub dcr: DCR,
#[doc = "0x4c - DMA address for continuous mode"]
pub dmar: DMAR,
}
impl RegisterBlock {
#[doc = "0x18 - Capture/Compare Mode Register 1"]
#[inline(always)]
pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
unsafe { &*(self as *const Self).cast::<u8>().add(24usize).cast() }
}
#[doc = "0x18 - Capture/Compare Mode Register 1"]
#[inline(always)]
pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
unsafe { &*(self as *const Self).cast::<u8>().add(24usize).cast() }
}
#[doc = "0x1c - Capture/Compare Mode Register 2"]
#[inline(always)]
pub const fn ccmr2_input(&self) -> &CCMR2_INPUT {
unsafe { &*(self as *const Self).cast::<u8>().add(28usize).cast() }
}
#[doc = "0x1c - Capture/Compare Mode Register 2"]
#[inline(always)]
pub const fn ccmr2_output(&self) -> &CCMR2_OUTPUT {
unsafe { &*(self as *const Self).cast::<u8>().add(28usize).cast() }
}
}
#[doc = "CR1 (rw) register accessor: an alias for `Reg<CR1_SPEC>`"]
pub type CR1 = crate::Reg<cr1::CR1_SPEC>;
#[doc = "Control Register 1"]
pub mod cr1 {
#[doc = "Register `CR1` reader"]
pub struct R(crate::R<CR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR1` writer"]
pub struct W(crate::W<CR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CEN` reader - "]
pub type CEN_R = crate::BitReader<bool>;
#[doc = "Field `CEN` writer - "]
pub type CEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `UDIS` reader - "]
pub type UDIS_R = crate::BitReader<bool>;
#[doc = "Field `UDIS` writer - "]
pub type UDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `URS` reader - "]
pub type URS_R = crate::BitReader<bool>;
#[doc = "Field `URS` writer - "]
pub type URS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `OPM` reader - "]
pub type OPM_R = crate::BitReader<bool>;
#[doc = "Field `OPM` writer - "]
pub type OPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `DIR` reader - "]
pub type DIR_R = crate::BitReader<bool>;
#[doc = "Field `DIR` writer - "]
pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `CMS` reader - "]
pub type CMS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CMS` writer - "]
pub type CMS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR1_SPEC, u8, u8, 2, O>;
#[doc = "Field `ARPE` reader - "]
pub type ARPE_R = crate::BitReader<bool>;
#[doc = "Field `ARPE` writer - "]
pub type ARPE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `CKD` reader - "]
pub type CKD_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CKD` writer - "]
pub type CKD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR1_SPEC, u8, u8, 2, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn cen(&self) -> CEN_R {
CEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn udis(&self) -> UDIS_R {
UDIS_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn urs(&self) -> URS_R {
URS_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn opm(&self) -> OPM_R {
OPM_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn dir(&self) -> DIR_R {
DIR_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6"]
#[inline(always)]
pub fn cms(&self) -> CMS_R {
CMS_R::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn arpe(&self) -> ARPE_R {
ARPE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn ckd(&self) -> CKD_R {
CKD_R::new(((self.bits >> 8) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn cen(&mut self) -> CEN_W<0> {
CEN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn udis(&mut self) -> UDIS_W<1> {
UDIS_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn urs(&mut self) -> URS_W<2> {
URS_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn opm(&mut self) -> OPM_W<3> {
OPM_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn dir(&mut self) -> DIR_W<4> {
DIR_W::new(self)
}
#[doc = "Bits 5:6"]
#[inline(always)]
#[must_use]
pub fn cms(&mut self) -> CMS_W<5> {
CMS_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn arpe(&mut self) -> ARPE_W<7> {
ARPE_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn ckd(&mut self) -> CKD_W<8> {
CKD_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr1](index.html) module"]
pub struct CR1_SPEC;
impl crate::RegisterSpec for CR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr1::R](R) reader structure"]
impl crate::Readable for CR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr1::W](W) writer structure"]
impl crate::Writable for CR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for CR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CR2 (rw) register accessor: an alias for `Reg<CR2_SPEC>`"]
pub type CR2 = crate::Reg<cr2::CR2_SPEC>;
#[doc = "Control Register 2"]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub struct R(crate::R<CR2_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR2_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR2_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR2` writer"]
pub struct W(crate::W<CR2_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR2_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR2_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR2_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CCDS` reader - "]
pub type CCDS_R = crate::BitReader<bool>;
#[doc = "Field `CCDS` writer - "]
pub type CCDS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
#[doc = "Field `MMS` reader - "]
pub type MMS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `MMS` writer - "]
pub type MMS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR2_SPEC, u8, u8, 3, O>;
#[doc = "Field `TI1S` reader - "]
pub type TI1S_R = crate::BitReader<bool>;
#[doc = "Field `TI1S` writer - "]
pub type TI1S_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
impl R {
#[doc = "Bit 3"]
#[inline(always)]
pub fn ccds(&self) -> CCDS_R {
CCDS_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn mms(&self) -> MMS_R {
MMS_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn ti1s(&self) -> TI1S_R {
TI1S_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn ccds(&mut self) -> CCDS_W<3> {
CCDS_W::new(self)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn mms(&mut self) -> MMS_W<4> {
MMS_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn ti1s(&mut self) -> TI1S_W<7> {
TI1S_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Control Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr2](index.html) module"]
pub struct CR2_SPEC;
impl crate::RegisterSpec for CR2_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr2::R](R) reader structure"]
impl crate::Readable for CR2_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr2::W](W) writer structure"]
impl crate::Writable for CR2_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for CR2_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SMCR (rw) register accessor: an alias for `Reg<SMCR_SPEC>`"]
pub type SMCR = crate::Reg<smcr::SMCR_SPEC>;
#[doc = "Slave Mode Control Register"]
pub mod smcr {
#[doc = "Register `SMCR` reader"]
pub struct R(crate::R<SMCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SMCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SMCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SMCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SMCR` writer"]
pub struct W(crate::W<SMCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SMCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SMCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SMCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SMS` reader - "]
pub type SMS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SMS` writer - "]
pub type SMS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SMCR_SPEC, u8, u8, 3, O>;
#[doc = "Field `OCCS` reader - "]
pub type OCCS_R = crate::BitReader<bool>;
#[doc = "Field `OCCS` writer - "]
pub type OCCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMCR_SPEC, bool, O>;
#[doc = "Field `TS` reader - "]
pub type TS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TS` writer - "]
pub type TS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SMCR_SPEC, u8, u8, 3, O>;
#[doc = "Field `MSM` reader - "]
pub type MSM_R = crate::BitReader<bool>;
#[doc = "Field `MSM` writer - "]
pub type MSM_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMCR_SPEC, bool, O>;
#[doc = "Field `ETF` reader - "]
pub type ETF_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ETF` writer - "]
pub type ETF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SMCR_SPEC, u8, u8, 4, O>;
#[doc = "Field `ETPS` reader - "]
pub type ETPS_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ETPS` writer - "]
pub type ETPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SMCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `ECE` reader - "]
pub type ECE_R = crate::BitReader<bool>;
#[doc = "Field `ECE` writer - "]
pub type ECE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMCR_SPEC, bool, O>;
#[doc = "Field `ETP` reader - "]
pub type ETP_R = crate::BitReader<bool>;
#[doc = "Field `ETP` writer - "]
pub type ETP_W<'a, const O: u8> = crate::BitWriter<'a, u32, SMCR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn sms(&self) -> SMS_R {
SMS_R::new((self.bits & 7) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn occs(&self) -> OCCS_R {
OCCS_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn ts(&self) -> TS_R {
TS_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn msm(&self) -> MSM_R {
MSM_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11"]
#[inline(always)]
pub fn etf(&self) -> ETF_R {
ETF_R::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bits 12:13"]
#[inline(always)]
pub fn etps(&self) -> ETPS_R {
ETPS_R::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn ece(&self) -> ECE_R {
ECE_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn etp(&self) -> ETP_R {
ETP_R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2"]
#[inline(always)]
#[must_use]
pub fn sms(&mut self) -> SMS_W<0> {
SMS_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn occs(&mut self) -> OCCS_W<3> {
OCCS_W::new(self)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn ts(&mut self) -> TS_W<4> {
TS_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn msm(&mut self) -> MSM_W<7> {
MSM_W::new(self)
}
#[doc = "Bits 8:11"]
#[inline(always)]
#[must_use]
pub fn etf(&mut self) -> ETF_W<8> {
ETF_W::new(self)
}
#[doc = "Bits 12:13"]
#[inline(always)]
#[must_use]
pub fn etps(&mut self) -> ETPS_W<12> {
ETPS_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn ece(&mut self) -> ECE_W<14> {
ECE_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn etp(&mut self) -> ETP_W<15> {
ETP_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Slave Mode Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smcr](index.html) module"]
pub struct SMCR_SPEC;
impl crate::RegisterSpec for SMCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [smcr::R](R) reader structure"]
impl crate::Readable for SMCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [smcr::W](W) writer structure"]
impl crate::Writable for SMCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SMCR to value 0"]
impl crate::Resettable for SMCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DIER (rw) register accessor: an alias for `Reg<DIER_SPEC>`"]
pub type DIER = crate::Reg<dier::DIER_SPEC>;
#[doc = "DMA/Interrupt Enable Register"]
pub mod dier {
#[doc = "Register `DIER` reader"]
pub struct R(crate::R<DIER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DIER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DIER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DIER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DIER` writer"]
pub struct W(crate::W<DIER_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DIER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DIER_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DIER_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `UIE` reader - "]
pub type UIE_R = crate::BitReader<bool>;
#[doc = "Field `UIE` writer - "]
pub type UIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC1IE` reader - "]
pub type CC1IE_R = crate::BitReader<bool>;
#[doc = "Field `CC1IE` writer - "]
pub type CC1IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC2IE` reader - "]
pub type CC2IE_R = crate::BitReader<bool>;
#[doc = "Field `CC2IE` writer - "]
pub type CC2IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC3IE` reader - "]
pub type CC3IE_R = crate::BitReader<bool>;
#[doc = "Field `CC3IE` writer - "]
pub type CC3IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC4IE` reader - "]
pub type CC4IE_R = crate::BitReader<bool>;
#[doc = "Field `CC4IE` writer - "]
pub type CC4IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `TIE` reader - "]
pub type TIE_R = crate::BitReader<bool>;
#[doc = "Field `TIE` writer - "]
pub type TIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `UDE` reader - "]
pub type UDE_R = crate::BitReader<bool>;
#[doc = "Field `UDE` writer - "]
pub type UDE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC1DE` reader - "]
pub type CC1DE_R = crate::BitReader<bool>;
#[doc = "Field `CC1DE` writer - "]
pub type CC1DE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC2DE` reader - "]
pub type CC2DE_R = crate::BitReader<bool>;
#[doc = "Field `CC2DE` writer - "]
pub type CC2DE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC3DE` reader - "]
pub type CC3DE_R = crate::BitReader<bool>;
#[doc = "Field `CC3DE` writer - "]
pub type CC3DE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `CC4DE` reader - "]
pub type CC4DE_R = crate::BitReader<bool>;
#[doc = "Field `CC4DE` writer - "]
pub type CC4DE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `TDE` reader - "]
pub type TDE_R = crate::BitReader<bool>;
#[doc = "Field `TDE` writer - "]
pub type TDE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn uie(&self) -> UIE_R {
UIE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn cc1ie(&self) -> CC1IE_R {
CC1IE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn cc2ie(&self) -> CC2IE_R {
CC2IE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn cc3ie(&self) -> CC3IE_R {
CC3IE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn cc4ie(&self) -> CC4IE_R {
CC4IE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tie(&self) -> TIE_R {
TIE_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn ude(&self) -> UDE_R {
UDE_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn cc1de(&self) -> CC1DE_R {
CC1DE_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn cc2de(&self) -> CC2DE_R {
CC2DE_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn cc3de(&self) -> CC3DE_R {
CC3DE_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn cc4de(&self) -> CC4DE_R {
CC4DE_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn tde(&self) -> TDE_R {
TDE_R::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn uie(&mut self) -> UIE_W<0> {
UIE_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn cc1ie(&mut self) -> CC1IE_W<1> {
CC1IE_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn cc2ie(&mut self) -> CC2IE_W<2> {
CC2IE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn cc3ie(&mut self) -> CC3IE_W<3> {
CC3IE_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn cc4ie(&mut self) -> CC4IE_W<4> {
CC4IE_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tie(&mut self) -> TIE_W<6> {
TIE_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn ude(&mut self) -> UDE_W<8> {
UDE_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn cc1de(&mut self) -> CC1DE_W<9> {
CC1DE_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn cc2de(&mut self) -> CC2DE_W<10> {
CC2DE_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn cc3de(&mut self) -> CC3DE_W<11> {
CC3DE_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn cc4de(&mut self) -> CC4DE_W<12> {
CC4DE_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn tde(&mut self) -> TDE_W<14> {
TDE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA/Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dier](index.html) module"]
pub struct DIER_SPEC;
impl crate::RegisterSpec for DIER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dier::R](R) reader structure"]
impl crate::Readable for DIER_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dier::W](W) writer structure"]
impl crate::Writable for DIER_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DIER to value 0"]
impl crate::Resettable for DIER_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SR (rw) register accessor: an alias for `Reg<SR_SPEC>`"]
pub type SR = crate::Reg<sr::SR_SPEC>;
#[doc = "status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub struct R(crate::R<SR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SR` writer"]
pub struct W(crate::W<SR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `UIF` reader - "]
pub type UIF_R = crate::BitReader<bool>;
#[doc = "Field `UIF` writer - "]
pub type UIF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC1IF` reader - "]
pub type CC1IF_R = crate::BitReader<bool>;
#[doc = "Field `CC1IF` writer - "]
pub type CC1IF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC2IF` reader - "]
pub type CC2IF_R = crate::BitReader<bool>;
#[doc = "Field `CC2IF` writer - "]
pub type CC2IF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC3IF` reader - "]
pub type CC3IF_R = crate::BitReader<bool>;
#[doc = "Field `CC3IF` writer - "]
pub type CC3IF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC4IF` reader - "]
pub type CC4IF_R = crate::BitReader<bool>;
#[doc = "Field `CC4IF` writer - "]
pub type CC4IF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `TIF` reader - "]
pub type TIF_R = crate::BitReader<bool>;
#[doc = "Field `TIF` writer - "]
pub type TIF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC1OF` reader - "]
pub type CC1OF_R = crate::BitReader<bool>;
#[doc = "Field `CC1OF` writer - "]
pub type CC1OF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC2OF` reader - "]
pub type CC2OF_R = crate::BitReader<bool>;
#[doc = "Field `CC2OF` writer - "]
pub type CC2OF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC3OF` reader - "]
pub type CC3OF_R = crate::BitReader<bool>;
#[doc = "Field `CC3OF` writer - "]
pub type CC3OF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
#[doc = "Field `CC4OF` reader - "]
pub type CC4OF_R = crate::BitReader<bool>;
#[doc = "Field `CC4OF` writer - "]
pub type CC4OF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn uif(&self) -> UIF_R {
UIF_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn cc1if(&self) -> CC1IF_R {
CC1IF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn cc2if(&self) -> CC2IF_R {
CC2IF_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn cc3if(&self) -> CC3IF_R {
CC3IF_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn cc4if(&self) -> CC4IF_R {
CC4IF_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn tif(&self) -> TIF_R {
TIF_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn cc1of(&self) -> CC1OF_R {
CC1OF_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn cc2of(&self) -> CC2OF_R {
CC2OF_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn cc3of(&self) -> CC3OF_R {
CC3OF_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn cc4of(&self) -> CC4OF_R {
CC4OF_R::new(((self.bits >> 12) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn uif(&mut self) -> UIF_W<0> {
UIF_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn cc1if(&mut self) -> CC1IF_W<1> {
CC1IF_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn cc2if(&mut self) -> CC2IF_W<2> {
CC2IF_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn cc3if(&mut self) -> CC3IF_W<3> {
CC3IF_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn cc4if(&mut self) -> CC4IF_W<4> {
CC4IF_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tif(&mut self) -> TIF_W<6> {
TIF_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn cc1of(&mut self) -> CC1OF_W<9> {
CC1OF_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn cc2of(&mut self) -> CC2OF_W<10> {
CC2OF_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn cc3of(&mut self) -> CC3OF_W<11> {
CC3OF_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn cc4of(&mut self) -> CC4OF_W<12> {
CC4OF_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"]
pub struct SR_SPEC;
impl crate::RegisterSpec for SR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [sr::R](R) reader structure"]
impl crate::Readable for SR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [sr::W](W) writer structure"]
impl crate::Writable for SR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x1e5f;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "EGR (w) register accessor: an alias for `Reg<EGR_SPEC>`"]
pub type EGR = crate::Reg<egr::EGR_SPEC>;
#[doc = "event generation register"]
pub mod egr {
#[doc = "Register `EGR` writer"]
pub struct W(crate::W<EGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<EGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<EGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<EGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `UG` writer - "]
pub type UG_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `CC1G` writer - "]
pub type CC1G_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `CC2G` writer - "]
pub type CC2G_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `CC3G` writer - "]
pub type CC3G_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `CC4G` writer - "]
pub type CC4G_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `COMG` writer - "]
pub type COMG_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
#[doc = "Field `TG` writer - "]
pub type TG_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn ug(&mut self) -> UG_W<0> {
UG_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn cc1g(&mut self) -> CC1G_W<1> {
CC1G_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn cc2g(&mut self) -> CC2G_W<2> {
CC2G_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn cc3g(&mut self) -> CC3G_W<3> {
CC3G_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn cc4g(&mut self) -> CC4G_W<4> {
CC4G_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn comg(&mut self) -> COMG_W<5> {
COMG_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn tg(&mut self) -> TG_W<6> {
TG_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "event generation register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [egr](index.html) module"]
pub struct EGR_SPEC;
impl crate::RegisterSpec for EGR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [egr::W](W) writer structure"]
impl crate::Writable for EGR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets EGR to value 0"]
impl crate::Resettable for EGR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCMR1_Output (rw) register accessor: an alias for `Reg<CCMR1_OUTPUT_SPEC>`"]
pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUT_SPEC>;
#[doc = "Capture/Compare Mode Register 1"]
pub mod ccmr1_output {
#[doc = "Register `CCMR1_Output` reader"]
pub struct R(crate::R<CCMR1_OUTPUT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCMR1_OUTPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCMR1_OUTPUT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCMR1_OUTPUT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCMR1_Output` writer"]
pub struct W(crate::W<CCMR1_OUTPUT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCMR1_OUTPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCMR1_OUTPUT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCMR1_OUTPUT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CC1S` reader - "]
pub type CC1S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC1S` writer - "]
pub type CC1S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `OC1FE` reader - "]
pub type OC1FE_R = crate::BitReader<bool>;
#[doc = "Field `OC1FE` writer - "]
pub type OC1FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC1PE` reader - "]
pub type OC1PE_R = crate::BitReader<bool>;
#[doc = "Field `OC1PE` writer - "]
pub type OC1PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC1M` reader - "]
pub type OC1M_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OC1M` writer - "]
pub type OC1M_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, u8, 3, O>;
#[doc = "Field `OC1CE` reader - "]
pub type OC1CE_R = crate::BitReader<bool>;
#[doc = "Field `OC1CE` writer - "]
pub type OC1CE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `CC2S` reader - "]
pub type CC2S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC2S` writer - "]
pub type CC2S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `OC2FE` reader - "]
pub type OC2FE_R = crate::BitReader<bool>;
#[doc = "Field `OC2FE` writer - "]
pub type OC2FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC2PE` reader - "]
pub type OC2PE_R = crate::BitReader<bool>;
#[doc = "Field `OC2PE` writer - "]
pub type OC2PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC2M` reader - "]
pub type OC2M_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OC2M` writer - "]
pub type OC2M_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, u8, 3, O>;
#[doc = "Field `OC2CE` reader - "]
pub type OC2CE_R = crate::BitReader<bool>;
#[doc = "Field `OC2CE` writer - "]
pub type OC2CE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn cc1s(&self) -> CC1S_R {
CC1S_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn oc1fe(&self) -> OC1FE_R {
OC1FE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn oc1pe(&self) -> OC1PE_R {
OC1PE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn oc1m(&self) -> OC1M_R {
OC1M_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn oc1ce(&self) -> OC1CE_R {
OC1CE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn cc2s(&self) -> CC2S_R {
CC2S_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn oc2fe(&self) -> OC2FE_R {
OC2FE_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn oc2pe(&self) -> OC2PE_R {
OC2PE_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:14"]
#[inline(always)]
pub fn oc2m(&self) -> OC2M_R {
OC2M_R::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn oc2ce(&self) -> OC2CE_R {
OC2CE_R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn cc1s(&mut self) -> CC1S_W<0> {
CC1S_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn oc1fe(&mut self) -> OC1FE_W<2> {
OC1FE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn oc1pe(&mut self) -> OC1PE_W<3> {
OC1PE_W::new(self)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn oc1m(&mut self) -> OC1M_W<4> {
OC1M_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn oc1ce(&mut self) -> OC1CE_W<7> {
OC1CE_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn cc2s(&mut self) -> CC2S_W<8> {
CC2S_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn oc2fe(&mut self) -> OC2FE_W<10> {
OC2FE_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn oc2pe(&mut self) -> OC2PE_W<11> {
OC2PE_W::new(self)
}
#[doc = "Bits 12:14"]
#[inline(always)]
#[must_use]
pub fn oc2m(&mut self) -> OC2M_W<12> {
OC2M_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn oc2ce(&mut self) -> OC2CE_W<15> {
OC2CE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Mode Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr1_output](index.html) module"]
pub struct CCMR1_OUTPUT_SPEC;
impl crate::RegisterSpec for CCMR1_OUTPUT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccmr1_output::R](R) reader structure"]
impl crate::Readable for CCMR1_OUTPUT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccmr1_output::W](W) writer structure"]
impl crate::Writable for CCMR1_OUTPUT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCMR1_Output to value 0"]
impl crate::Resettable for CCMR1_OUTPUT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCMR1_Input (rw) register accessor: an alias for `Reg<CCMR1_INPUT_SPEC>`"]
pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUT_SPEC>;
#[doc = "Capture/Compare Mode Register 1"]
pub mod ccmr1_input {
#[doc = "Register `CCMR1_Input` reader"]
pub struct R(crate::R<CCMR1_INPUT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCMR1_INPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCMR1_INPUT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCMR1_INPUT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCMR1_Input` writer"]
pub struct W(crate::W<CCMR1_INPUT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCMR1_INPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCMR1_INPUT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCMR1_INPUT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CC1S` reader - "]
pub type CC1S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC1S` writer - "]
pub type CC1S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC1PSC` reader - "]
pub type IC1PSC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC1PSC` writer - "]
pub type IC1PSC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC1F` reader - "]
pub type IC1F_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC1F` writer - "]
pub type IC1F_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 4, O>;
#[doc = "Field `CC2S` reader - "]
pub type CC2S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC2S` writer - "]
pub type CC2S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC2PSC` reader - "]
pub type IC2PSC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC2PSC` writer - "]
pub type IC2PSC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC2F` reader - "]
pub type IC2F_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC2F` writer - "]
pub type IC2F_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 4, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn cc1s(&self) -> CC1S_R {
CC1S_R::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3"]
#[inline(always)]
pub fn ic1psc(&self) -> IC1PSC_R {
IC1PSC_R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn ic1f(&self) -> IC1F_R {
IC1F_R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn cc2s(&self) -> CC2S_R {
CC2S_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11"]
#[inline(always)]
pub fn ic2psc(&self) -> IC2PSC_R {
IC2PSC_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:15"]
#[inline(always)]
pub fn ic2f(&self) -> IC2F_R {
IC2F_R::new(((self.bits >> 12) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn cc1s(&mut self) -> CC1S_W<0> {
CC1S_W::new(self)
}
#[doc = "Bits 2:3"]
#[inline(always)]
#[must_use]
pub fn ic1psc(&mut self) -> IC1PSC_W<2> {
IC1PSC_W::new(self)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn ic1f(&mut self) -> IC1F_W<4> {
IC1F_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn cc2s(&mut self) -> CC2S_W<8> {
CC2S_W::new(self)
}
#[doc = "Bits 10:11"]
#[inline(always)]
#[must_use]
pub fn ic2psc(&mut self) -> IC2PSC_W<10> {
IC2PSC_W::new(self)
}
#[doc = "Bits 12:15"]
#[inline(always)]
#[must_use]
pub fn ic2f(&mut self) -> IC2F_W<12> {
IC2F_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Mode Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr1_input](index.html) module"]
pub struct CCMR1_INPUT_SPEC;
impl crate::RegisterSpec for CCMR1_INPUT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccmr1_input::R](R) reader structure"]
impl crate::Readable for CCMR1_INPUT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccmr1_input::W](W) writer structure"]
impl crate::Writable for CCMR1_INPUT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCMR1_Input to value 0"]
impl crate::Resettable for CCMR1_INPUT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCMR2_Output (rw) register accessor: an alias for `Reg<CCMR2_OUTPUT_SPEC>`"]
pub type CCMR2_OUTPUT = crate::Reg<ccmr2_output::CCMR2_OUTPUT_SPEC>;
#[doc = "Capture/Compare Mode Register 2"]
pub mod ccmr2_output {
#[doc = "Register `CCMR2_Output` reader"]
pub struct R(crate::R<CCMR2_OUTPUT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCMR2_OUTPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCMR2_OUTPUT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCMR2_OUTPUT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCMR2_Output` writer"]
pub struct W(crate::W<CCMR2_OUTPUT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCMR2_OUTPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCMR2_OUTPUT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCMR2_OUTPUT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CC3S` reader - "]
pub type CC3S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC3S` writer - "]
pub type CC3S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_OUTPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `OC3FE` reader - "]
pub type OC3FE_R = crate::BitReader<bool>;
#[doc = "Field `OC3FE` writer - "]
pub type OC3FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC3PE` reader - "]
pub type OC3PE_R = crate::BitReader<bool>;
#[doc = "Field `OC3PE` writer - "]
pub type OC3PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC3M` reader - "]
pub type OC3M_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OC3M` writer - "]
pub type OC3M_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_OUTPUT_SPEC, u8, u8, 3, O>;
#[doc = "Field `OC3CE` reader - "]
pub type OC3CE_R = crate::BitReader<bool>;
#[doc = "Field `OC3CE` writer - "]
pub type OC3CE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
#[doc = "Field `CC4S` reader - "]
pub type CC4S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC4S` writer - "]
pub type CC4S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_OUTPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `OC4FE` reader - "]
pub type OC4FE_R = crate::BitReader<bool>;
#[doc = "Field `OC4FE` writer - "]
pub type OC4FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC4PE` reader - "]
pub type OC4PE_R = crate::BitReader<bool>;
#[doc = "Field `OC4PE` writer - "]
pub type OC4PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC4M` reader - "]
pub type OC4M_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OC4M` writer - "]
pub type OC4M_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_OUTPUT_SPEC, u8, u8, 3, O>;
#[doc = "Field `OC4CE` reader - "]
pub type OC4CE_R = crate::BitReader<bool>;
#[doc = "Field `OC4CE` writer - "]
pub type OC4CE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn cc3s(&self) -> CC3S_R {
CC3S_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn oc3fe(&self) -> OC3FE_R {
OC3FE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn oc3pe(&self) -> OC3PE_R {
OC3PE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6"]
#[inline(always)]
pub fn oc3m(&self) -> OC3M_R {
OC3M_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn oc3ce(&self) -> OC3CE_R {
OC3CE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn cc4s(&self) -> CC4S_R {
CC4S_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn oc4fe(&self) -> OC4FE_R {
OC4FE_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn oc4pe(&self) -> OC4PE_R {
OC4PE_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:14"]
#[inline(always)]
pub fn oc4m(&self) -> OC4M_R {
OC4M_R::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn oc4ce(&self) -> OC4CE_R {
OC4CE_R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn cc3s(&mut self) -> CC3S_W<0> {
CC3S_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn oc3fe(&mut self) -> OC3FE_W<2> {
OC3FE_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn oc3pe(&mut self) -> OC3PE_W<3> {
OC3PE_W::new(self)
}
#[doc = "Bits 4:6"]
#[inline(always)]
#[must_use]
pub fn oc3m(&mut self) -> OC3M_W<4> {
OC3M_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn oc3ce(&mut self) -> OC3CE_W<7> {
OC3CE_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn cc4s(&mut self) -> CC4S_W<8> {
CC4S_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn oc4fe(&mut self) -> OC4FE_W<10> {
OC4FE_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn oc4pe(&mut self) -> OC4PE_W<11> {
OC4PE_W::new(self)
}
#[doc = "Bits 12:14"]
#[inline(always)]
#[must_use]
pub fn oc4m(&mut self) -> OC4M_W<12> {
OC4M_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn oc4ce(&mut self) -> OC4CE_W<15> {
OC4CE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Mode Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr2_output](index.html) module"]
pub struct CCMR2_OUTPUT_SPEC;
impl crate::RegisterSpec for CCMR2_OUTPUT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccmr2_output::R](R) reader structure"]
impl crate::Readable for CCMR2_OUTPUT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccmr2_output::W](W) writer structure"]
impl crate::Writable for CCMR2_OUTPUT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCMR2_Output to value 0"]
impl crate::Resettable for CCMR2_OUTPUT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCMR2_Input (rw) register accessor: an alias for `Reg<CCMR2_INPUT_SPEC>`"]
pub type CCMR2_INPUT = crate::Reg<ccmr2_input::CCMR2_INPUT_SPEC>;
#[doc = "Capture/Compare Mode Register 2"]
pub mod ccmr2_input {
#[doc = "Register `CCMR2_Input` reader"]
pub struct R(crate::R<CCMR2_INPUT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCMR2_INPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCMR2_INPUT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCMR2_INPUT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCMR2_Input` writer"]
pub struct W(crate::W<CCMR2_INPUT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCMR2_INPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCMR2_INPUT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCMR2_INPUT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CC3S` reader - "]
pub type CC3S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC3S` writer - "]
pub type CC3S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC3PSC` reader - "]
pub type IC3PSC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC3PSC` writer - "]
pub type IC3PSC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC3F` reader - "]
pub type IC3F_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC3F` writer - "]
pub type IC3F_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 4, O>;
#[doc = "Field `CC4S` reader - "]
pub type CC4S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC4S` writer - "]
pub type CC4S_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC4PSC` reader - "]
pub type IC4PSC_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC4PSC` writer - "]
pub type IC4PSC_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `IC4F` reader - "]
pub type IC4F_R = crate::FieldReader<u8, u8>;
#[doc = "Field `IC4F` writer - "]
pub type IC4F_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 4, O>;
impl R {
#[doc = "Bits 0:1"]
#[inline(always)]
pub fn cc3s(&self) -> CC3S_R {
CC3S_R::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3"]
#[inline(always)]
pub fn ic3psc(&self) -> IC3PSC_R {
IC3PSC_R::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn ic3f(&self) -> IC3F_R {
IC3F_R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:9"]
#[inline(always)]
pub fn cc4s(&self) -> CC4S_R {
CC4S_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11"]
#[inline(always)]
pub fn ic4psc(&self) -> IC4PSC_R {
IC4PSC_R::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:15"]
#[inline(always)]
pub fn ic4f(&self) -> IC4F_R {
IC4F_R::new(((self.bits >> 12) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:1"]
#[inline(always)]
#[must_use]
pub fn cc3s(&mut self) -> CC3S_W<0> {
CC3S_W::new(self)
}
#[doc = "Bits 2:3"]
#[inline(always)]
#[must_use]
pub fn ic3psc(&mut self) -> IC3PSC_W<2> {
IC3PSC_W::new(self)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn ic3f(&mut self) -> IC3F_W<4> {
IC3F_W::new(self)
}
#[doc = "Bits 8:9"]
#[inline(always)]
#[must_use]
pub fn cc4s(&mut self) -> CC4S_W<8> {
CC4S_W::new(self)
}
#[doc = "Bits 10:11"]
#[inline(always)]
#[must_use]
pub fn ic4psc(&mut self) -> IC4PSC_W<10> {
IC4PSC_W::new(self)
}
#[doc = "Bits 12:15"]
#[inline(always)]
#[must_use]
pub fn ic4f(&mut self) -> IC4F_W<12> {
IC4F_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Mode Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr2_input](index.html) module"]
pub struct CCMR2_INPUT_SPEC;
impl crate::RegisterSpec for CCMR2_INPUT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccmr2_input::R](R) reader structure"]
impl crate::Readable for CCMR2_INPUT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccmr2_input::W](W) writer structure"]
impl crate::Writable for CCMR2_INPUT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCMR2_Input to value 0"]
impl crate::Resettable for CCMR2_INPUT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCER (rw) register accessor: an alias for `Reg<CCER_SPEC>`"]
pub type CCER = crate::Reg<ccer::CCER_SPEC>;
#[doc = "Capture/Compare Enable Register"]
pub mod ccer {
#[doc = "Register `CCER` reader"]
pub struct R(crate::R<CCER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCER` writer"]
pub struct W(crate::W<CCER_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCER_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCER_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CC1E` reader - "]
pub type CC1E_R = crate::BitReader<bool>;
#[doc = "Field `CC1E` writer - "]
pub type CC1E_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC1P` reader - "]
pub type CC1P_R = crate::BitReader<bool>;
#[doc = "Field `CC1P` writer - "]
pub type CC1P_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC1NP` reader - "]
pub type CC1NP_R = crate::BitReader<bool>;
#[doc = "Field `CC1NP` writer - "]
pub type CC1NP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC2E` reader - "]
pub type CC2E_R = crate::BitReader<bool>;
#[doc = "Field `CC2E` writer - "]
pub type CC2E_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC2P` reader - "]
pub type CC2P_R = crate::BitReader<bool>;
#[doc = "Field `CC2P` writer - "]
pub type CC2P_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC2NP` reader - "]
pub type CC2NP_R = crate::BitReader<bool>;
#[doc = "Field `CC2NP` writer - "]
pub type CC2NP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC3E` reader - "]
pub type CC3E_R = crate::BitReader<bool>;
#[doc = "Field `CC3E` writer - "]
pub type CC3E_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC3P` reader - "]
pub type CC3P_R = crate::BitReader<bool>;
#[doc = "Field `CC3P` writer - "]
pub type CC3P_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC3NP` reader - "]
pub type CC3NP_R = crate::BitReader<bool>;
#[doc = "Field `CC3NP` writer - "]
pub type CC3NP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC4E` reader - "]
pub type CC4E_R = crate::BitReader<bool>;
#[doc = "Field `CC4E` writer - "]
pub type CC4E_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC4P` reader - "]
pub type CC4P_R = crate::BitReader<bool>;
#[doc = "Field `CC4P` writer - "]
pub type CC4P_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
#[doc = "Field `CC4NP` reader - "]
pub type CC4NP_R = crate::BitReader<bool>;
#[doc = "Field `CC4NP` writer - "]
pub type CC4NP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCER_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn cc1e(&self) -> CC1E_R {
CC1E_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn cc1p(&self) -> CC1P_R {
CC1P_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn cc1np(&self) -> CC1NP_R {
CC1NP_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn cc2e(&self) -> CC2E_R {
CC2E_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn cc2p(&self) -> CC2P_R {
CC2P_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn cc2np(&self) -> CC2NP_R {
CC2NP_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn cc3e(&self) -> CC3E_R {
CC3E_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn cc3p(&self) -> CC3P_R {
CC3P_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn cc3np(&self) -> CC3NP_R {
CC3NP_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn cc4e(&self) -> CC4E_R {
CC4E_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn cc4p(&self) -> CC4P_R {
CC4P_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 15"]
#[inline(always)]
pub fn cc4np(&self) -> CC4NP_R {
CC4NP_R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn cc1e(&mut self) -> CC1E_W<0> {
CC1E_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn cc1p(&mut self) -> CC1P_W<1> {
CC1P_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn cc1np(&mut self) -> CC1NP_W<3> {
CC1NP_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn cc2e(&mut self) -> CC2E_W<4> {
CC2E_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn cc2p(&mut self) -> CC2P_W<5> {
CC2P_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn cc2np(&mut self) -> CC2NP_W<7> {
CC2NP_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn cc3e(&mut self) -> CC3E_W<8> {
CC3E_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn cc3p(&mut self) -> CC3P_W<9> {
CC3P_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn cc3np(&mut self) -> CC3NP_W<11> {
CC3NP_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn cc4e(&mut self) -> CC4E_W<12> {
CC4E_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn cc4p(&mut self) -> CC4P_W<13> {
CC4P_W::new(self)
}
#[doc = "Bit 15"]
#[inline(always)]
#[must_use]
pub fn cc4np(&mut self) -> CC4NP_W<15> {
CC4NP_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccer](index.html) module"]
pub struct CCER_SPEC;
impl crate::RegisterSpec for CCER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccer::R](R) reader structure"]
impl crate::Readable for CCER_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccer::W](W) writer structure"]
impl crate::Writable for CCER_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCER to value 0"]
impl crate::Resettable for CCER_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CNT (rw) register accessor: an alias for `Reg<CNT_SPEC>`"]
pub type CNT = crate::Reg<cnt::CNT_SPEC>;
#[doc = "counter"]
pub mod cnt {
#[doc = "Register `CNT` reader"]
pub struct R(crate::R<CNT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CNT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CNT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CNT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CNT` writer"]
pub struct W(crate::W<CNT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CNT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CNT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CNT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CNT` reader - "]
pub type CNT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CNT` writer - "]
pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNT_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn cnt(&self) -> CNT_R {
CNT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CNT_W<0> {
CNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnt](index.html) module"]
pub struct CNT_SPEC;
impl crate::RegisterSpec for CNT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cnt::R](R) reader structure"]
impl crate::Readable for CNT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cnt::W](W) writer structure"]
impl crate::Writable for CNT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CNT to value 0"]
impl crate::Resettable for CNT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PSC (rw) register accessor: an alias for `Reg<PSC_SPEC>`"]
pub type PSC = crate::Reg<psc::PSC_SPEC>;
#[doc = "Prescaler"]
pub mod psc {
#[doc = "Register `PSC` reader"]
pub struct R(crate::R<PSC_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PSC_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PSC_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PSC_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PSC` writer"]
pub struct W(crate::W<PSC_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PSC_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PSC_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PSC_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PSC` reader - "]
pub type PSC_R = crate::FieldReader<u16, u16>;
#[doc = "Field `PSC` writer - "]
pub type PSC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PSC_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn psc(&self) -> PSC_R {
PSC_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn psc(&mut self) -> PSC_W<0> {
PSC_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [psc](index.html) module"]
pub struct PSC_SPEC;
impl crate::RegisterSpec for PSC_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [psc::R](R) reader structure"]
impl crate::Readable for PSC_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [psc::W](W) writer structure"]
impl crate::Writable for PSC_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PSC to value 0"]
impl crate::Resettable for PSC_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ARR (rw) register accessor: an alias for `Reg<ARR_SPEC>`"]
pub type ARR = crate::Reg<arr::ARR_SPEC>;
#[doc = "autoload register"]
pub mod arr {
#[doc = "Register `ARR` reader"]
pub struct R(crate::R<ARR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ARR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ARR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ARR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ARR` writer"]
pub struct W(crate::W<ARR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ARR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ARR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ARR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `ARR` reader - "]
pub type ARR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `ARR` writer - "]
pub type ARR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ARR_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn arr(&self) -> ARR_R {
ARR_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn arr(&mut self) -> ARR_W<0> {
ARR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "autoload register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arr](index.html) module"]
pub struct ARR_SPEC;
impl crate::RegisterSpec for ARR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [arr::R](R) reader structure"]
impl crate::Readable for ARR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [arr::W](W) writer structure"]
impl crate::Writable for ARR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ARR to value 0"]
impl crate::Resettable for ARR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCR1 (rw) register accessor: an alias for `Reg<CCR1_SPEC>`"]
pub type CCR1 = crate::Reg<ccr1::CCR1_SPEC>;
#[doc = "Capture/Compare Register 1"]
pub mod ccr1 {
#[doc = "Register `CCR1` reader"]
pub struct R(crate::R<CCR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCR1` writer"]
pub struct W(crate::W<CCR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CCR` reader - "]
pub type CCR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CCR` writer - "]
pub type CCR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCR1_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn ccr(&self) -> CCR_R {
CCR_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn ccr(&mut self) -> CCR_W<0> {
CCR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Capture/Compare Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr1](index.html) module"]
pub struct CCR1_SPEC;
impl crate::RegisterSpec for CCR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccr1::R](R) reader structure"]
impl crate::Readable for CCR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccr1::W](W) writer structure"]
impl crate::Writable for CCR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCR1 to value 0"]
impl crate::Resettable for CCR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
pub use ccr1 as ccr2;
pub use ccr1 as ccr3;
pub use ccr1 as ccr4;
pub use CCR1 as CCR2;
pub use CCR1 as CCR3;
pub use CCR1 as CCR4;
#[doc = "DCR (rw) register accessor: an alias for `Reg<DCR_SPEC>`"]
pub type DCR = crate::Reg<dcr::DCR_SPEC>;
#[doc = "DMA Control Register"]
pub mod dcr {
#[doc = "Register `DCR` reader"]
pub struct R(crate::R<DCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DCR` writer"]
pub struct W(crate::W<DCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DBA` reader - "]
pub type DBA_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DBA` writer - "]
pub type DBA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCR_SPEC, u8, u8, 5, O>;
#[doc = "Field `DBL` reader - "]
pub type DBL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DBL` writer - "]
pub type DBL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCR_SPEC, u8, u8, 5, O>;
impl R {
#[doc = "Bits 0:4"]
#[inline(always)]
pub fn dba(&self) -> DBA_R {
DBA_R::new((self.bits & 0x1f) as u8)
}
#[doc = "Bits 8:12"]
#[inline(always)]
pub fn dbl(&self) -> DBL_R {
DBL_R::new(((self.bits >> 8) & 0x1f) as u8)
}
}
impl W {
#[doc = "Bits 0:4"]
#[inline(always)]
#[must_use]
pub fn dba(&mut self) -> DBA_W<0> {
DBA_W::new(self)
}
#[doc = "Bits 8:12"]
#[inline(always)]
#[must_use]
pub fn dbl(&mut self) -> DBL_W<8> {
DBL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcr](index.html) module"]
pub struct DCR_SPEC;
impl crate::RegisterSpec for DCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dcr::R](R) reader structure"]
impl crate::Readable for DCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dcr::W](W) writer structure"]
impl crate::Writable for DCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DCR to value 0"]
impl crate::Resettable for DCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DMAR (w) register accessor: an alias for `Reg<DMAR_SPEC>`"]
pub type DMAR = crate::Reg<dmar::DMAR_SPEC>;
#[doc = "DMA address for continuous mode"]
pub mod dmar {
#[doc = "Register `DMAR` writer"]
pub struct W(crate::W<DMAR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DMAR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DMAR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DMAR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DMAB` writer - "]
pub type DMAB_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMAR_SPEC, u16, u16, 16, O>;
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn dmab(&mut self) -> DMAB_W<0> {
DMAB_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA address for continuous mode\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmar](index.html) module"]
pub struct DMAR_SPEC;
impl crate::RegisterSpec for DMAR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [dmar::W](W) writer structure"]
impl crate::Writable for DMAR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DMAR to value 0"]
impl crate::Resettable for DMAR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "TIM4"]
pub struct TIM4 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIM4 {}
impl TIM4 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const tim3::RegisterBlock = 0x4000_0800 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const tim3::RegisterBlock {
Self::PTR
}
}
impl Deref for TIM4 {
type Target = tim3::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for TIM4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM4").finish()
}
}
#[doc = "TIM4"]
pub use self::tim3 as tim4;
#[doc = "TIM6"]
pub struct TIM6 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIM6 {}
impl TIM6 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const tim6::RegisterBlock = 0x4000_1000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const tim6::RegisterBlock {
Self::PTR
}
}
impl Deref for TIM6 {
type Target = tim6::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for TIM6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM6").finish()
}
}
#[doc = "TIM6"]
pub mod tim6 {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Control Register 1"]
pub cr1: CR1,
_reserved1: [u8; 0x08],
#[doc = "0x0c - DMA/Interrupt Enable Register"]
pub dier: DIER,
#[doc = "0x10 - status register"]
pub sr: SR,
#[doc = "0x14 - event generation register"]
pub egr: EGR,
_reserved4: [u8; 0x0c],
#[doc = "0x24 - counter"]
pub cnt: CNT,
#[doc = "0x28 - Prescaler"]
pub psc: PSC,
#[doc = "0x2c - autoload register"]
pub arr: ARR,
}
#[doc = "CR1 (rw) register accessor: an alias for `Reg<CR1_SPEC>`"]
pub type CR1 = crate::Reg<cr1::CR1_SPEC>;
#[doc = "Control Register 1"]
pub mod cr1 {
#[doc = "Register `CR1` reader"]
pub struct R(crate::R<CR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR1` writer"]
pub struct W(crate::W<CR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CEN` reader - "]
pub type CEN_R = crate::BitReader<bool>;
#[doc = "Field `CEN` writer - "]
pub type CEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `UDIS` reader - "]
pub type UDIS_R = crate::BitReader<bool>;
#[doc = "Field `UDIS` writer - "]
pub type UDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `URS` reader - "]
pub type URS_R = crate::BitReader<bool>;
#[doc = "Field `URS` writer - "]
pub type URS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `OPM` reader - "]
pub type OPM_R = crate::BitReader<bool>;
#[doc = "Field `OPM` writer - "]
pub type OPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `ARPE` reader - "]
pub type ARPE_R = crate::BitReader<bool>;
#[doc = "Field `ARPE` writer - "]
pub type ARPE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn cen(&self) -> CEN_R {
CEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn udis(&self) -> UDIS_R {
UDIS_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn urs(&self) -> URS_R {
URS_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn opm(&self) -> OPM_R {
OPM_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn arpe(&self) -> ARPE_R {
ARPE_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn cen(&mut self) -> CEN_W<0> {
CEN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn udis(&mut self) -> UDIS_W<1> {
UDIS_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn urs(&mut self) -> URS_W<2> {
URS_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn opm(&mut self) -> OPM_W<3> {
OPM_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn arpe(&mut self) -> ARPE_W<7> {
ARPE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr1](index.html) module"]
pub struct CR1_SPEC;
impl crate::RegisterSpec for CR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr1::R](R) reader structure"]
impl crate::Readable for CR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr1::W](W) writer structure"]
impl crate::Writable for CR1_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for CR1_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "DIER (rw) register accessor: an alias for `Reg<DIER_SPEC>`"]
pub type DIER = crate::Reg<dier::DIER_SPEC>;
#[doc = "DMA/Interrupt Enable Register"]
pub mod dier {
#[doc = "Register `DIER` reader"]
pub struct R(crate::R<DIER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<DIER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<DIER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<DIER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `DIER` writer"]
pub struct W(crate::W<DIER_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<DIER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<DIER_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<DIER_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `UIE` reader - "]
pub type UIE_R = crate::BitReader<bool>;
#[doc = "Field `UIE` writer - "]
pub type UIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
#[doc = "Field `UDE` reader - "]
pub type UDE_R = crate::BitReader<bool>;
#[doc = "Field `UDE` writer - "]
pub type UDE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIER_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn uie(&self) -> UIE_R {
UIE_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn ude(&self) -> UDE_R {
UDE_R::new(((self.bits >> 8) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn uie(&mut self) -> UIE_W<0> {
UIE_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn ude(&mut self) -> UDE_W<8> {
UDE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "DMA/Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dier](index.html) module"]
pub struct DIER_SPEC;
impl crate::RegisterSpec for DIER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [dier::R](R) reader structure"]
impl crate::Readable for DIER_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dier::W](W) writer structure"]
impl crate::Writable for DIER_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets DIER to value 0"]
impl crate::Resettable for DIER_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "SR (rw) register accessor: an alias for `Reg<SR_SPEC>`"]
pub type SR = crate::Reg<sr::SR_SPEC>;
#[doc = "status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub struct R(crate::R<SR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SR` writer"]
pub struct W(crate::W<SR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `UIF` reader - "]
pub type UIF_R = crate::BitReader<bool>;
#[doc = "Field `UIF` writer - "]
pub type UIF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn uif(&self) -> UIF_R {
UIF_R::new((self.bits & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn uif(&mut self) -> UIF_W<0> {
UIF_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"]
pub struct SR_SPEC;
impl crate::RegisterSpec for SR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [sr::R](R) reader structure"]
impl crate::Readable for SR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [sr::W](W) writer structure"]
impl crate::Writable for SR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x01;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "EGR (w) register accessor: an alias for `Reg<EGR_SPEC>`"]
pub type EGR = crate::Reg<egr::EGR_SPEC>;
#[doc = "event generation register"]
pub mod egr {
#[doc = "Register `EGR` writer"]
pub struct W(crate::W<EGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<EGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<EGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<EGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `UG` writer - "]
pub type UG_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, bool, O>;
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn ug(&mut self) -> UG_W<0> {
UG_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "event generation register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [egr](index.html) module"]
pub struct EGR_SPEC;
impl crate::RegisterSpec for EGR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [egr::W](W) writer structure"]
impl crate::Writable for EGR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets EGR to value 0"]
impl crate::Resettable for EGR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CNT (rw) register accessor: an alias for `Reg<CNT_SPEC>`"]
pub type CNT = crate::Reg<cnt::CNT_SPEC>;
#[doc = "counter"]
pub mod cnt {
#[doc = "Register `CNT` reader"]
pub struct R(crate::R<CNT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CNT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CNT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CNT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CNT` writer"]
pub struct W(crate::W<CNT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CNT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CNT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CNT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CNT` reader - "]
pub type CNT_R = crate::FieldReader<u16, u16>;
#[doc = "Field `CNT` writer - "]
pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNT_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn cnt(&self) -> CNT_R {
CNT_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CNT_W<0> {
CNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnt](index.html) module"]
pub struct CNT_SPEC;
impl crate::RegisterSpec for CNT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cnt::R](R) reader structure"]
impl crate::Readable for CNT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cnt::W](W) writer structure"]
impl crate::Writable for CNT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CNT to value 0"]
impl crate::Resettable for CNT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "PSC (rw) register accessor: an alias for `Reg<PSC_SPEC>`"]
pub type PSC = crate::Reg<psc::PSC_SPEC>;
#[doc = "Prescaler"]
pub mod psc {
#[doc = "Register `PSC` reader"]
pub struct R(crate::R<PSC_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PSC_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PSC_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PSC_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PSC` writer"]
pub struct W(crate::W<PSC_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PSC_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PSC_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PSC_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PSC` reader - "]
pub type PSC_R = crate::FieldReader<u16, u16>;
#[doc = "Field `PSC` writer - "]
pub type PSC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PSC_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn psc(&self) -> PSC_R {
PSC_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn psc(&mut self) -> PSC_W<0> {
PSC_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [psc](index.html) module"]
pub struct PSC_SPEC;
impl crate::RegisterSpec for PSC_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [psc::R](R) reader structure"]
impl crate::Readable for PSC_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [psc::W](W) writer structure"]
impl crate::Writable for PSC_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PSC to value 0"]
impl crate::Resettable for PSC_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ARR (rw) register accessor: an alias for `Reg<ARR_SPEC>`"]
pub type ARR = crate::Reg<arr::ARR_SPEC>;
#[doc = "autoload register"]
pub mod arr {
#[doc = "Register `ARR` reader"]
pub struct R(crate::R<ARR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ARR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ARR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ARR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ARR` writer"]
pub struct W(crate::W<ARR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ARR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ARR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ARR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `ARR` reader - "]
pub type ARR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `ARR` writer - "]
pub type ARR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ARR_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn arr(&self) -> ARR_R {
ARR_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn arr(&mut self) -> ARR_W<0> {
ARR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "autoload register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [arr](index.html) module"]
pub struct ARR_SPEC;
impl crate::RegisterSpec for ARR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [arr::R](R) reader structure"]
impl crate::Readable for ARR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [arr::W](W) writer structure"]
impl crate::Writable for ARR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ARR to value 0"]
impl crate::Resettable for ARR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "TIM7"]
pub struct TIM7 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for TIM7 {}
impl TIM7 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const tim6::RegisterBlock = 0x4000_1400 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const tim6::RegisterBlock {
Self::PTR
}
}
impl Deref for TIM7 {
type Target = tim6::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for TIM7 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("TIM7").finish()
}
}
#[doc = "TIM7"]
pub use self::tim6 as tim7;
#[doc = "UART1"]
pub struct UART1 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for UART1 {}
impl UART1 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const uart1::RegisterBlock = 0x4001_3800 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const uart1::RegisterBlock {
Self::PTR
}
}
impl Deref for UART1 {
type Target = uart1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for UART1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UART1").finish()
}
}
#[doc = "UART1"]
pub mod uart1 {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - UART transmit data register"]
pub tdr: TDR,
#[doc = "0x04 - UART receive data register"]
pub rdr: RDR,
#[doc = "0x08 - UART current status register"]
pub csr: CSR,
#[doc = "0x0c - UART Interrupt Status Register"]
pub isr: ISR,
#[doc = "0x10 - UART Interrupt Enable Register"]
pub ier: IER,
#[doc = "0x14 - UART Interrupt Clear Register"]
pub icr: ICR,
#[doc = "0x18 - UART Global Control Register"]
pub gcr: GCR,
#[doc = "0x1c - UART General Control Register"]
pub ccr: CCR,
#[doc = "0x20 - UART Baud Rate Register"]
pub brr: BRR,
#[doc = "0x24 - UART Fractional Baud Rate Register"]
pub fra: FRA,
#[doc = "0x28 - UART receive address register"]
pub rxaddr: RXADDR,
#[doc = "0x2c - UART Receive Mask Register"]
pub rxmask: RXMASK,
#[doc = "0x30 - UART SCR register"]
pub scr: SCR,
#[doc = "0x34 - UART IDLE Data Length Register"]
pub idlr: IDLR,
#[doc = "0x38 - UART ABRCR Auto-Baud Rate Control Register"]
pub abrcr: ABRCR,
#[doc = "0x3c - UART IRDA infrared function control register"]
pub irda: IRDA,
}
#[doc = "TDR (rw) register accessor: an alias for `Reg<TDR_SPEC>`"]
pub type TDR = crate::Reg<tdr::TDR_SPEC>;
#[doc = "UART transmit data register"]
pub mod tdr {
#[doc = "Register `TDR` reader"]
pub struct R(crate::R<TDR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<TDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<TDR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<TDR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `TDR` writer"]
pub struct W(crate::W<TDR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<TDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<TDR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<TDR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TXREG` reader - "]
pub type TXREG_R = crate::FieldReader<u16, u16>;
#[doc = "Field `TXREG` writer - "]
pub type TXREG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TDR_SPEC, u16, u16, 9, O>;
impl R {
#[doc = "Bits 0:8"]
#[inline(always)]
pub fn txreg(&self) -> TXREG_R {
TXREG_R::new((self.bits & 0x01ff) as u16)
}
}
impl W {
#[doc = "Bits 0:8"]
#[inline(always)]
#[must_use]
pub fn txreg(&mut self) -> TXREG_W<0> {
TXREG_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "UART transmit data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tdr](index.html) module"]
pub struct TDR_SPEC;
impl crate::RegisterSpec for TDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [tdr::R](R) reader structure"]
impl crate::Readable for TDR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [tdr::W](W) writer structure"]
impl crate::Writable for TDR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets TDR to value 0"]
impl crate::Resettable for TDR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RDR (rw) register accessor: an alias for `Reg<RDR_SPEC>`"]
pub type RDR = crate::Reg<rdr::RDR_SPEC>;
#[doc = "UART receive data register"]
pub mod rdr {
#[doc = "Register `RDR` reader"]
pub struct R(crate::R<RDR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RDR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RDR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `RDR` writer"]
pub struct W(crate::W<RDR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<RDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<RDR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<RDR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RXREG` reader - "]
pub type RXREG_R = crate::FieldReader<u16, u16>;
#[doc = "Field `RXREG` writer - "]
pub type RXREG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RDR_SPEC, u16, u16, 9, O>;
impl R {
#[doc = "Bits 0:8"]
#[inline(always)]
pub fn rxreg(&self) -> RXREG_R {
RXREG_R::new((self.bits & 0x01ff) as u16)
}
}
impl W {
#[doc = "Bits 0:8"]
#[inline(always)]
#[must_use]
pub fn rxreg(&mut self) -> RXREG_W<0> {
RXREG_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "UART receive data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rdr](index.html) module"]
pub struct RDR_SPEC;
impl crate::RegisterSpec for RDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rdr::R](R) reader structure"]
impl crate::Readable for RDR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [rdr::W](W) writer structure"]
impl crate::Writable for RDR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets RDR to value 0"]
impl crate::Resettable for RDR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CSR (r) register accessor: an alias for `Reg<CSR_SPEC>`"]
pub type CSR = crate::Reg<csr::CSR_SPEC>;
#[doc = "UART current status register"]
pub mod csr {
#[doc = "Register `CSR` reader"]
pub struct R(crate::R<CSR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CSR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CSR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CSR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `TXC` reader - "]
pub type TXC_R = crate::BitReader<bool>;
#[doc = "Field `RXAVL` reader - "]
pub type RXAVL_R = crate::BitReader<bool>;
#[doc = "Field `TXFULL` reader - "]
pub type TXFULL_R = crate::BitReader<bool>;
#[doc = "Field `TXEPT` reader - "]
pub type TXEPT_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn txc(&self) -> TXC_R {
TXC_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rxavl(&self) -> RXAVL_R {
RXAVL_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn txfull(&self) -> TXFULL_R {
TXFULL_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn txept(&self) -> TXEPT_R {
TXEPT_R::new(((self.bits >> 3) & 1) != 0)
}
}
#[doc = "UART current status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"]
pub struct CSR_SPEC;
impl crate::RegisterSpec for CSR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [csr::R](R) reader structure"]
impl crate::Readable for CSR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets CSR to value 0x09"]
impl crate::Resettable for CSR_SPEC {
const RESET_VALUE: Self::Ux = 0x09;
}
}
#[doc = "ISR (r) register accessor: an alias for `Reg<ISR_SPEC>`"]
pub type ISR = crate::Reg<isr::ISR_SPEC>;
#[doc = "UART Interrupt Status Register"]
pub mod isr {
#[doc = "Register `ISR` reader"]
pub struct R(crate::R<ISR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ISR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ISR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ISR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `TX_INTF` reader - "]
pub type TX_INTF_R = crate::BitReader<bool>;
#[doc = "Field `RX_INTF` reader - "]
pub type RX_INTF_R = crate::BitReader<bool>;
#[doc = "Field `TXC_INTF` reader - "]
pub type TXC_INTF_R = crate::BitReader<bool>;
#[doc = "Field `RXOERR_INTF` reader - "]
pub type RXOERR_INTF_R = crate::BitReader<bool>;
#[doc = "Field `RXPERR_INTF` reader - "]
pub type RXPERR_INTF_R = crate::BitReader<bool>;
#[doc = "Field `RXFERR_INTF` reader - "]
pub type RXFERR_INTF_R = crate::BitReader<bool>;
#[doc = "Field `RXBRK_INTF` reader - "]
pub type RXBRK_INTF_R = crate::BitReader<bool>;
#[doc = "Field `TXBRK_INTF` reader - "]
pub type TXBRK_INTF_R = crate::BitReader<bool>;
#[doc = "Field `RXB8_INTF` reader - "]
pub type RXB8_INTF_R = crate::BitReader<bool>;
#[doc = "Field `RXIDLE_INTF` reader - "]
pub type RXIDLE_INTF_R = crate::BitReader<bool>;
#[doc = "Field `ABREND_INTF` reader - "]
pub type ABREND_INTF_R = crate::BitReader<bool>;
#[doc = "Field `ABRERR_INTF` reader - "]
pub type ABRERR_INTF_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn tx_intf(&self) -> TX_INTF_R {
TX_INTF_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rx_intf(&self) -> RX_INTF_R {
RX_INTF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn txc_intf(&self) -> TXC_INTF_R {
TXC_INTF_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rxoerr_intf(&self) -> RXOERR_INTF_R {
RXOERR_INTF_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn rxperr_intf(&self) -> RXPERR_INTF_R {
RXPERR_INTF_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rxferr_intf(&self) -> RXFERR_INTF_R {
RXFERR_INTF_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn rxbrk_intf(&self) -> RXBRK_INTF_R {
RXBRK_INTF_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn txbrk_intf(&self) -> TXBRK_INTF_R {
TXBRK_INTF_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rxb8_intf(&self) -> RXB8_INTF_R {
RXB8_INTF_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn rxidle_intf(&self) -> RXIDLE_INTF_R {
RXIDLE_INTF_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn abrend_intf(&self) -> ABREND_INTF_R {
ABREND_INTF_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn abrerr_intf(&self) -> ABRERR_INTF_R {
ABRERR_INTF_R::new(((self.bits >> 11) & 1) != 0)
}
}
#[doc = "UART Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](index.html) module"]
pub struct ISR_SPEC;
impl crate::RegisterSpec for ISR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [isr::R](R) reader structure"]
impl crate::Readable for ISR_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets ISR to value 0"]
impl crate::Resettable for ISR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "IER (rw) register accessor: an alias for `Reg<IER_SPEC>`"]
pub type IER = crate::Reg<ier::IER_SPEC>;
#[doc = "UART Interrupt Enable Register"]
pub mod ier {
#[doc = "Register `IER` reader"]
pub struct R(crate::R<IER_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IER_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IER_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IER` writer"]
pub struct W(crate::W<IER_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IER_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IER_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TX_IEN` reader - "]
pub type TX_IEN_R = crate::BitReader<bool>;
#[doc = "Field `TX_IEN` writer - "]
pub type TX_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
#[doc = "Field `RX_IEN` reader - "]
pub type RX_IEN_R = crate::BitReader<bool>;
#[doc = "Field `RX_IEN` writer - "]
pub type RX_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
#[doc = "Field `TXC_IEN` reader - "]
pub type TXC_IEN_R = crate::BitReader<bool>;
#[doc = "Field `TXC_IEN` writer - "]
pub type TXC_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
#[doc = "Field `RXOERR_IEN` reader - "]
pub type RXOERR_IEN_R = crate::BitReader<bool>;
#[doc = "Field `RXOERR_IEN` writer - "]
pub type RXOERR_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
#[doc = "Field `RXPERR_IEN` reader - "]
pub type RXPERR_IEN_R = crate::BitReader<bool>;
#[doc = "Field `RXPERR_IEN` writer - "]
pub type RXPERR_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
#[doc = "Field `RXFERR_IEN` reader - "]
pub type RXFERR_IEN_R = crate::BitReader<bool>;
#[doc = "Field `RXFERR_IEN` writer - "]
pub type RXFERR_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
#[doc = "Field `RXBRK_IEN` reader - "]
pub type RXBRK_IEN_R = crate::BitReader<bool>;
#[doc = "Field `RXBRK_IEN` writer - "]
pub type RXBRK_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
#[doc = "Field `TXBRK_IEN` reader - "]
pub type TXBRK_IEN_R = crate::BitReader<bool>;
#[doc = "Field `TXBRK_IEN` writer - "]
pub type TXBRK_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
#[doc = "Field `RXB8_IEN` reader - "]
pub type RXB8_IEN_R = crate::BitReader<bool>;
#[doc = "Field `RXB8_IEN` writer - "]
pub type RXB8_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
#[doc = "Field `RXIDLE_IEN` reader - "]
pub type RXIDLE_IEN_R = crate::BitReader<bool>;
#[doc = "Field `RXIDLE_IEN` writer - "]
pub type RXIDLE_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
#[doc = "Field `ABREND_IEN` reader - "]
pub type ABREND_IEN_R = crate::BitReader<bool>;
#[doc = "Field `ABREND_IEN` writer - "]
pub type ABREND_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
#[doc = "Field `ABRERR_IEN` reader - "]
pub type ABRERR_IEN_R = crate::BitReader<bool>;
#[doc = "Field `ABRERR_IEN` writer - "]
pub type ABRERR_IEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn tx_ien(&self) -> TX_IEN_R {
TX_IEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn rx_ien(&self) -> RX_IEN_R {
RX_IEN_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn txc_ien(&self) -> TXC_IEN_R {
TXC_IEN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rxoerr_ien(&self) -> RXOERR_IEN_R {
RXOERR_IEN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn rxperr_ien(&self) -> RXPERR_IEN_R {
RXPERR_IEN_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn rxferr_ien(&self) -> RXFERR_IEN_R {
RXFERR_IEN_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn rxbrk_ien(&self) -> RXBRK_IEN_R {
RXBRK_IEN_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn txbrk_ien(&self) -> TXBRK_IEN_R {
TXBRK_IEN_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn rxb8_ien(&self) -> RXB8_IEN_R {
RXB8_IEN_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn rxidle_ien(&self) -> RXIDLE_IEN_R {
RXIDLE_IEN_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn abrend_ien(&self) -> ABREND_IEN_R {
ABREND_IEN_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn abrerr_ien(&self) -> ABRERR_IEN_R {
ABRERR_IEN_R::new(((self.bits >> 11) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn tx_ien(&mut self) -> TX_IEN_W<0> {
TX_IEN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn rx_ien(&mut self) -> RX_IEN_W<1> {
RX_IEN_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn txc_ien(&mut self) -> TXC_IEN_W<2> {
TXC_IEN_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rxoerr_ien(&mut self) -> RXOERR_IEN_W<3> {
RXOERR_IEN_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn rxperr_ien(&mut self) -> RXPERR_IEN_W<4> {
RXPERR_IEN_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rxferr_ien(&mut self) -> RXFERR_IEN_W<5> {
RXFERR_IEN_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn rxbrk_ien(&mut self) -> RXBRK_IEN_W<6> {
RXBRK_IEN_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn txbrk_ien(&mut self) -> TXBRK_IEN_W<7> {
TXBRK_IEN_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rxb8_ien(&mut self) -> RXB8_IEN_W<8> {
RXB8_IEN_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn rxidle_ien(&mut self) -> RXIDLE_IEN_W<9> {
RXIDLE_IEN_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn abrend_ien(&mut self) -> ABREND_IEN_W<10> {
ABREND_IEN_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn abrerr_ien(&mut self) -> ABRERR_IEN_W<11> {
ABRERR_IEN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "UART Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"]
pub struct IER_SPEC;
impl crate::RegisterSpec for IER_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ier::R](R) reader structure"]
impl crate::Readable for IER_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"]
impl crate::Writable for IER_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IER to value 0"]
impl crate::Resettable for IER_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "ICR (w) register accessor: an alias for `Reg<ICR_SPEC>`"]
pub type ICR = crate::Reg<icr::ICR_SPEC>;
#[doc = "UART Interrupt Clear Register"]
pub mod icr {
#[doc = "Register `ICR` writer"]
pub struct W(crate::W<ICR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ICR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ICR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ICR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TX_ICLR` writer - "]
pub type TX_ICLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
#[doc = "Field `RX_ICLR` writer - "]
pub type RX_ICLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
#[doc = "Field `TXC_ICLR` writer - "]
pub type TXC_ICLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
#[doc = "Field `RXOERR_ICLR` writer - "]
pub type RXOERR_ICLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
#[doc = "Field `RXPERR_ICLR` writer - "]
pub type RXPERR_ICLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
#[doc = "Field `RXFERR_ICLR` writer - "]
pub type RXFERR_ICLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
#[doc = "Field `RXBRK_ICLR` writer - "]
pub type RXBRK_ICLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
#[doc = "Field `TXBRK_ICLR` writer - "]
pub type TXBRK_ICLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
#[doc = "Field `RXB8_ICLR` writer - "]
pub type RXB8_ICLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
#[doc = "Field `RXIDLE_ICLR` writer - "]
pub type RXIDLE_ICLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
#[doc = "Field `ABREND_ICLR` writer - "]
pub type ABREND_ICLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
#[doc = "Field `ABRERR_ICLR` writer - "]
pub type ABRERR_ICLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICR_SPEC, bool, O>;
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn tx_iclr(&mut self) -> TX_ICLR_W<0> {
TX_ICLR_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn rx_iclr(&mut self) -> RX_ICLR_W<1> {
RX_ICLR_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn txc_iclr(&mut self) -> TXC_ICLR_W<2> {
TXC_ICLR_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rxoerr_iclr(&mut self) -> RXOERR_ICLR_W<3> {
RXOERR_ICLR_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn rxperr_iclr(&mut self) -> RXPERR_ICLR_W<4> {
RXPERR_ICLR_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn rxferr_iclr(&mut self) -> RXFERR_ICLR_W<5> {
RXFERR_ICLR_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn rxbrk_iclr(&mut self) -> RXBRK_ICLR_W<6> {
RXBRK_ICLR_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn txbrk_iclr(&mut self) -> TXBRK_ICLR_W<7> {
TXBRK_ICLR_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn rxb8_iclr(&mut self) -> RXB8_ICLR_W<8> {
RXB8_ICLR_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn rxidle_iclr(&mut self) -> RXIDLE_ICLR_W<9> {
RXIDLE_ICLR_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn abrend_iclr(&mut self) -> ABREND_ICLR_W<10> {
ABREND_ICLR_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn abrerr_iclr(&mut self) -> ABRERR_ICLR_W<11> {
ABRERR_ICLR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "UART Interrupt Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](index.html) module"]
pub struct ICR_SPEC;
impl crate::RegisterSpec for ICR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [icr::W](W) writer structure"]
impl crate::Writable for ICR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ICR to value 0"]
impl crate::Resettable for ICR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "GCR (rw) register accessor: an alias for `Reg<GCR_SPEC>`"]
pub type GCR = crate::Reg<gcr::GCR_SPEC>;
#[doc = "UART Global Control Register"]
pub mod gcr {
#[doc = "Register `GCR` reader"]
pub struct R(crate::R<GCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<GCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<GCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<GCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `GCR` writer"]
pub struct W(crate::W<GCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<GCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<GCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<GCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `UARTEN` reader - "]
pub type UARTEN_R = crate::BitReader<bool>;
#[doc = "Field `UARTEN` writer - "]
pub type UARTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCR_SPEC, bool, O>;
#[doc = "Field `DMAMODE` reader - "]
pub type DMAMODE_R = crate::BitReader<bool>;
#[doc = "Field `DMAMODE` writer - "]
pub type DMAMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCR_SPEC, bool, O>;
#[doc = "Field `AUTOFLOWEN` reader - "]
pub type AUTOFLOWEN_R = crate::BitReader<bool>;
#[doc = "Field `AUTOFLOWEN` writer - "]
pub type AUTOFLOWEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCR_SPEC, bool, O>;
#[doc = "Field `RXEN` reader - "]
pub type RXEN_R = crate::BitReader<bool>;
#[doc = "Field `RXEN` writer - "]
pub type RXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCR_SPEC, bool, O>;
#[doc = "Field `TXEN` reader - "]
pub type TXEN_R = crate::BitReader<bool>;
#[doc = "Field `TXEN` writer - "]
pub type TXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCR_SPEC, bool, O>;
#[doc = "Field `SELB8` reader - "]
pub type SELB8_R = crate::BitReader<bool>;
#[doc = "Field `SELB8` writer - "]
pub type SELB8_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCR_SPEC, bool, O>;
#[doc = "Field `SWAP` reader - "]
pub type SWAP_R = crate::BitReader<bool>;
#[doc = "Field `SWAP` writer - "]
pub type SWAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCR_SPEC, bool, O>;
#[doc = "Field `RXTOG` reader - "]
pub type RXTOG_R = crate::BitReader<bool>;
#[doc = "Field `RXTOG` writer - "]
pub type RXTOG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCR_SPEC, bool, O>;
#[doc = "Field `TXTOG` reader - "]
pub type TXTOG_R = crate::BitReader<bool>;
#[doc = "Field `TXTOG` writer - "]
pub type TXTOG_W<'a, const O: u8> = crate::BitWriter<'a, u32, GCR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn uarten(&self) -> UARTEN_R {
UARTEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn dmamode(&self) -> DMAMODE_R {
DMAMODE_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn autoflowen(&self) -> AUTOFLOWEN_R {
AUTOFLOWEN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn rxen(&self) -> RXEN_R {
RXEN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn txen(&self) -> TXEN_R {
TXEN_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn selb8(&self) -> SELB8_R {
SELB8_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn swap(&self) -> SWAP_R {
SWAP_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn rxtog(&self) -> RXTOG_R {
RXTOG_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn txtog(&self) -> TXTOG_R {
TXTOG_R::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn uarten(&mut self) -> UARTEN_W<0> {
UARTEN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn dmamode(&mut self) -> DMAMODE_W<1> {
DMAMODE_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn autoflowen(&mut self) -> AUTOFLOWEN_W<2> {
AUTOFLOWEN_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn rxen(&mut self) -> RXEN_W<3> {
RXEN_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn txen(&mut self) -> TXEN_W<4> {
TXEN_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn selb8(&mut self) -> SELB8_W<7> {
SELB8_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn swap(&mut self) -> SWAP_W<8> {
SWAP_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn rxtog(&mut self) -> RXTOG_W<9> {
RXTOG_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn txtog(&mut self) -> TXTOG_W<10> {
TXTOG_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "UART Global Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gcr](index.html) module"]
pub struct GCR_SPEC;
impl crate::RegisterSpec for GCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [gcr::R](R) reader structure"]
impl crate::Readable for GCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [gcr::W](W) writer structure"]
impl crate::Writable for GCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets GCR to value 0"]
impl crate::Resettable for GCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "CCR (rw) register accessor: an alias for `Reg<CCR_SPEC>`"]
pub type CCR = crate::Reg<ccr::CCR_SPEC>;
#[doc = "UART General Control Register"]
pub mod ccr {
#[doc = "Register `CCR` reader"]
pub struct R(crate::R<CCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCR` writer"]
pub struct W(crate::W<CCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PEN` reader - "]
pub type PEN_R = crate::BitReader<bool>;
#[doc = "Field `PEN` writer - "]
pub type PEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
#[doc = "Field `PSEL` reader - "]
pub type PSEL_R = crate::BitReader<bool>;
#[doc = "Field `PSEL` writer - "]
pub type PSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
#[doc = "Field `SPB0` reader - "]
pub type SPB0_R = crate::BitReader<bool>;
#[doc = "Field `SPB0` writer - "]
pub type SPB0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
#[doc = "Field `BRK` reader - "]
pub type BRK_R = crate::BitReader<bool>;
#[doc = "Field `BRK` writer - "]
pub type BRK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
#[doc = "Field `CHAR` reader - "]
pub type CHAR_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CHAR` writer - "]
pub type CHAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `SPB1` reader - "]
pub type SPB1_R = crate::BitReader<bool>;
#[doc = "Field `SPB1` writer - "]
pub type SPB1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
#[doc = "Field `B8RXD` reader - "]
pub type B8RXD_R = crate::BitReader<bool>;
#[doc = "Field `B8RXD` writer - "]
pub type B8RXD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
#[doc = "Field `B8TXD` reader - "]
pub type B8TXD_R = crate::BitReader<bool>;
#[doc = "Field `B8TXD` writer - "]
pub type B8TXD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
#[doc = "Field `B8POL` reader - "]
pub type B8POL_R = crate::BitReader<bool>;
#[doc = "Field `B8POL` writer - "]
pub type B8POL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
#[doc = "Field `B8TOG` reader - "]
pub type B8TOG_R = crate::BitReader<bool>;
#[doc = "Field `B8TOG` writer - "]
pub type B8TOG_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
#[doc = "Field `B8EN` reader - "]
pub type B8EN_R = crate::BitReader<bool>;
#[doc = "Field `B8EN` writer - "]
pub type B8EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
#[doc = "Field `RWU` reader - "]
pub type RWU_R = crate::BitReader<bool>;
#[doc = "Field `RWU` writer - "]
pub type RWU_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
#[doc = "Field `WAKE` reader - "]
pub type WAKE_R = crate::BitReader<bool>;
#[doc = "Field `WAKE` writer - "]
pub type WAKE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
#[doc = "Field `LIN` reader - "]
pub type LIN_R = crate::BitReader<bool>;
#[doc = "Field `LIN` writer - "]
pub type LIN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pen(&self) -> PEN_R {
PEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn psel(&self) -> PSEL_R {
PSEL_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn spb0(&self) -> SPB0_R {
SPB0_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn brk(&self) -> BRK_R {
BRK_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:5"]
#[inline(always)]
pub fn char(&self) -> CHAR_R {
CHAR_R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn spb1(&self) -> SPB1_R {
SPB1_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn b8rxd(&self) -> B8RXD_R {
B8RXD_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8"]
#[inline(always)]
pub fn b8txd(&self) -> B8TXD_R {
B8TXD_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn b8pol(&self) -> B8POL_R {
B8POL_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10"]
#[inline(always)]
pub fn b8tog(&self) -> B8TOG_R {
B8TOG_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11"]
#[inline(always)]
pub fn b8en(&self) -> B8EN_R {
B8EN_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn rwu(&self) -> RWU_R {
RWU_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13"]
#[inline(always)]
pub fn wake(&self) -> WAKE_R {
WAKE_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14"]
#[inline(always)]
pub fn lin(&self) -> LIN_R {
LIN_R::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pen(&mut self) -> PEN_W<0> {
PEN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn psel(&mut self) -> PSEL_W<1> {
PSEL_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn spb0(&mut self) -> SPB0_W<2> {
SPB0_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn brk(&mut self) -> BRK_W<3> {
BRK_W::new(self)
}
#[doc = "Bits 4:5"]
#[inline(always)]
#[must_use]
pub fn char(&mut self) -> CHAR_W<4> {
CHAR_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn spb1(&mut self) -> SPB1_W<6> {
SPB1_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn b8rxd(&mut self) -> B8RXD_W<7> {
B8RXD_W::new(self)
}
#[doc = "Bit 8"]
#[inline(always)]
#[must_use]
pub fn b8txd(&mut self) -> B8TXD_W<8> {
B8TXD_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn b8pol(&mut self) -> B8POL_W<9> {
B8POL_W::new(self)
}
#[doc = "Bit 10"]
#[inline(always)]
#[must_use]
pub fn b8tog(&mut self) -> B8TOG_W<10> {
B8TOG_W::new(self)
}
#[doc = "Bit 11"]
#[inline(always)]
#[must_use]
pub fn b8en(&mut self) -> B8EN_W<11> {
B8EN_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn rwu(&mut self) -> RWU_W<12> {
RWU_W::new(self)
}
#[doc = "Bit 13"]
#[inline(always)]
#[must_use]
pub fn wake(&mut self) -> WAKE_W<13> {
WAKE_W::new(self)
}
#[doc = "Bit 14"]
#[inline(always)]
#[must_use]
pub fn lin(&mut self) -> LIN_W<14> {
LIN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "UART General Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"]
pub struct CCR_SPEC;
impl crate::RegisterSpec for CCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccr::R](R) reader structure"]
impl crate::Readable for CCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccr::W](W) writer structure"]
impl crate::Writable for CCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CCR to value 0"]
impl crate::Resettable for CCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "BRR (rw) register accessor: an alias for `Reg<BRR_SPEC>`"]
pub type BRR = crate::Reg<brr::BRR_SPEC>;
#[doc = "UART Baud Rate Register"]
pub mod brr {
#[doc = "Register `BRR` reader"]
pub struct R(crate::R<BRR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<BRR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<BRR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<BRR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `BRR` writer"]
pub struct W(crate::W<BRR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<BRR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<BRR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<BRR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DIV_Mantissa` reader - "]
pub type DIV_MANTISSA_R = crate::FieldReader<u16, u16>;
#[doc = "Field `DIV_Mantissa` writer - "]
pub type DIV_MANTISSA_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, BRR_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn div_mantissa(&self) -> DIV_MANTISSA_R {
DIV_MANTISSA_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<0> {
DIV_MANTISSA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "UART Baud Rate Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [brr](index.html) module"]
pub struct BRR_SPEC;
impl crate::RegisterSpec for BRR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [brr::R](R) reader structure"]
impl crate::Readable for BRR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [brr::W](W) writer structure"]
impl crate::Writable for BRR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets BRR to value 0x01"]
impl crate::Resettable for BRR_SPEC {
const RESET_VALUE: Self::Ux = 0x01;
}
}
#[doc = "FRA (rw) register accessor: an alias for `Reg<FRA_SPEC>`"]
pub type FRA = crate::Reg<fra::FRA_SPEC>;
#[doc = "UART Fractional Baud Rate Register"]
pub mod fra {
#[doc = "Register `FRA` reader"]
pub struct R(crate::R<FRA_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FRA_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FRA_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FRA_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FRA` writer"]
pub struct W(crate::W<FRA_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FRA_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FRA_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FRA_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DIV_Fraction` reader - "]
pub type DIV_FRACTION_R = crate::FieldReader<u8, u8>;
#[doc = "Field `DIV_Fraction` writer - "]
pub type DIV_FRACTION_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, FRA_SPEC, u8, u8, 4, O>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn div_fraction(&self) -> DIV_FRACTION_R {
DIV_FRACTION_R::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn div_fraction(&mut self) -> DIV_FRACTION_W<0> {
DIV_FRACTION_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "UART Fractional Baud Rate Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fra](index.html) module"]
pub struct FRA_SPEC;
impl crate::RegisterSpec for FRA_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fra::R](R) reader structure"]
impl crate::Readable for FRA_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fra::W](W) writer structure"]
impl crate::Writable for FRA_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FRA to value 0"]
impl crate::Resettable for FRA_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RXADDR (rw) register accessor: an alias for `Reg<RXADDR_SPEC>`"]
pub type RXADDR = crate::Reg<rxaddr::RXADDR_SPEC>;
#[doc = "UART receive address register"]
pub mod rxaddr {
#[doc = "Register `RXADDR` reader"]
pub struct R(crate::R<RXADDR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RXADDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RXADDR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RXADDR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `RXADDR` writer"]
pub struct W(crate::W<RXADDR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<RXADDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<RXADDR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<RXADDR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RXADDR` reader - "]
pub type RXADDR_R = crate::FieldReader<u8, u8>;
#[doc = "Field `RXADDR` writer - "]
pub type RXADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RXADDR_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn rxaddr(&self) -> RXADDR_R {
RXADDR_R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn rxaddr(&mut self) -> RXADDR_W<0> {
RXADDR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "UART receive address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxaddr](index.html) module"]
pub struct RXADDR_SPEC;
impl crate::RegisterSpec for RXADDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rxaddr::R](R) reader structure"]
impl crate::Readable for RXADDR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [rxaddr::W](W) writer structure"]
impl crate::Writable for RXADDR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets RXADDR to value 0"]
impl crate::Resettable for RXADDR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "RXMASK (rw) register accessor: an alias for `Reg<RXMASK_SPEC>`"]
pub type RXMASK = crate::Reg<rxmask::RXMASK_SPEC>;
#[doc = "UART Receive Mask Register"]
pub mod rxmask {
#[doc = "Register `RXMASK` reader"]
pub struct R(crate::R<RXMASK_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<RXMASK_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<RXMASK_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<RXMASK_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `RXMASK` writer"]
pub struct W(crate::W<RXMASK_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<RXMASK_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<RXMASK_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<RXMASK_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RXMASK` reader - "]
pub type RXMASK_R = crate::FieldReader<u8, u8>;
#[doc = "Field `RXMASK` writer - "]
pub type RXMASK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RXMASK_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn rxmask(&self) -> RXMASK_R {
RXMASK_R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn rxmask(&mut self) -> RXMASK_W<0> {
RXMASK_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "UART Receive Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxmask](index.html) module"]
pub struct RXMASK_SPEC;
impl crate::RegisterSpec for RXMASK_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [rxmask::R](R) reader structure"]
impl crate::Readable for RXMASK_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [rxmask::W](W) writer structure"]
impl crate::Writable for RXMASK_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets RXMASK to value 0xff"]
impl crate::Resettable for RXMASK_SPEC {
const RESET_VALUE: Self::Ux = 0xff;
}
}
#[doc = "SCR (rw) register accessor: an alias for `Reg<SCR_SPEC>`"]
pub type SCR = crate::Reg<scr::SCR_SPEC>;
#[doc = "UART SCR register"]
pub mod scr {
#[doc = "Register `SCR` reader"]
pub struct R(crate::R<SCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SCR` writer"]
pub struct W(crate::W<SCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SCEN` reader - "]
pub type SCEN_R = crate::BitReader<bool>;
#[doc = "Field `SCEN` writer - "]
pub type SCEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCR_SPEC, bool, O>;
#[doc = "Field `SCAEN` reader - "]
pub type SCAEN_R = crate::BitReader<bool>;
#[doc = "Field `SCAEN` writer - "]
pub type SCAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCR_SPEC, bool, O>;
#[doc = "Field `NACK` reader - "]
pub type NACK_R = crate::BitReader<bool>;
#[doc = "Field `SCFCNT` reader - "]
pub type SCFCNT_R = crate::FieldReader<u8, u8>;
#[doc = "Field `SCFCNT` writer - "]
pub type SCFCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SCR_SPEC, u8, u8, 8, O>;
#[doc = "Field `HDSEL` reader - "]
pub type HDSEL_R = crate::BitReader<bool>;
#[doc = "Field `HDSEL` writer - "]
pub type HDSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn scen(&self) -> SCEN_R {
SCEN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn scaen(&self) -> SCAEN_R {
SCAEN_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn nack(&self) -> NACK_R {
NACK_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 4:11"]
#[inline(always)]
pub fn scfcnt(&self) -> SCFCNT_R {
SCFCNT_R::new(((self.bits >> 4) & 0xff) as u8)
}
#[doc = "Bit 12"]
#[inline(always)]
pub fn hdsel(&self) -> HDSEL_R {
HDSEL_R::new(((self.bits >> 12) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn scen(&mut self) -> SCEN_W<0> {
SCEN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn scaen(&mut self) -> SCAEN_W<1> {
SCAEN_W::new(self)
}
#[doc = "Bits 4:11"]
#[inline(always)]
#[must_use]
pub fn scfcnt(&mut self) -> SCFCNT_W<4> {
SCFCNT_W::new(self)
}
#[doc = "Bit 12"]
#[inline(always)]
#[must_use]
pub fn hdsel(&mut self) -> HDSEL_W<12> {
HDSEL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "UART SCR register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"]
pub struct SCR_SPEC;
impl crate::RegisterSpec for SCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [scr::R](R) reader structure"]
impl crate::Readable for SCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"]
impl crate::Writable for SCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SCR to value 0"]
impl crate::Resettable for SCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "IDLR (rw) register accessor: an alias for `Reg<IDLR_SPEC>`"]
pub type IDLR = crate::Reg<idlr::IDLR_SPEC>;
#[doc = "UART IDLE Data Length Register"]
pub mod idlr {
#[doc = "Register `IDLR` reader"]
pub struct R(crate::R<IDLR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IDLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IDLR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IDLR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IDLR` writer"]
pub struct W(crate::W<IDLR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IDLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IDLR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IDLR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `IDLR` reader - "]
pub type IDLR_R = crate::FieldReader<u16, u16>;
#[doc = "Field `IDLR` writer - "]
pub type IDLR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IDLR_SPEC, u16, u16, 16, O>;
impl R {
#[doc = "Bits 0:15"]
#[inline(always)]
pub fn idlr(&self) -> IDLR_R {
IDLR_R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15"]
#[inline(always)]
#[must_use]
pub fn idlr(&mut self) -> IDLR_W<0> {
IDLR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "UART IDLE Data Length Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idlr](index.html) module"]
pub struct IDLR_SPEC;
impl crate::RegisterSpec for IDLR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [idlr::R](R) reader structure"]
impl crate::Readable for IDLR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [idlr::W](W) writer structure"]
impl crate::Writable for IDLR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IDLR to value 0x0c"]
impl crate::Resettable for IDLR_SPEC {
const RESET_VALUE: Self::Ux = 0x0c;
}
}
#[doc = "ABRCR (rw) register accessor: an alias for `Reg<ABRCR_SPEC>`"]
pub type ABRCR = crate::Reg<abrcr::ABRCR_SPEC>;
#[doc = "UART ABRCR Auto-Baud Rate Control Register"]
pub mod abrcr {
#[doc = "Register `ABRCR` reader"]
pub struct R(crate::R<ABRCR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<ABRCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<ABRCR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<ABRCR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `ABRCR` writer"]
pub struct W(crate::W<ABRCR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<ABRCR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<ABRCR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<ABRCR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `Abren` reader - "]
pub type ABREN_R = crate::BitReader<bool>;
#[doc = "Field `Abren` writer - "]
pub type ABREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ABRCR_SPEC, bool, O>;
#[doc = "Field `Abr_bitcnt` reader - "]
pub type ABR_BITCNT_R = crate::FieldReader<u8, u8>;
#[doc = "Field `Abr_bitcnt` writer - "]
pub type ABR_BITCNT_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, ABRCR_SPEC, u8, u8, 2, O>;
#[doc = "Field `Former_edge` reader - "]
pub type FORMER_EDGE_R = crate::BitReader<bool>;
#[doc = "Field `Former_edge` writer - "]
pub type FORMER_EDGE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ABRCR_SPEC, bool, O>;
#[doc = "Field `Latter_edge` reader - "]
pub type LATTER_EDGE_R = crate::BitReader<bool>;
#[doc = "Field `Latter_edge` writer - "]
pub type LATTER_EDGE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ABRCR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn abren(&self) -> ABREN_R {
ABREN_R::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:2"]
#[inline(always)]
pub fn abr_bitcnt(&self) -> ABR_BITCNT_R {
ABR_BITCNT_R::new(((self.bits >> 1) & 3) as u8)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn former_edge(&self) -> FORMER_EDGE_R {
FORMER_EDGE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn latter_edge(&self) -> LATTER_EDGE_R {
LATTER_EDGE_R::new(((self.bits >> 4) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn abren(&mut self) -> ABREN_W<0> {
ABREN_W::new(self)
}
#[doc = "Bits 1:2"]
#[inline(always)]
#[must_use]
pub fn abr_bitcnt(&mut self) -> ABR_BITCNT_W<1> {
ABR_BITCNT_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn former_edge(&mut self) -> FORMER_EDGE_W<3> {
FORMER_EDGE_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn latter_edge(&mut self) -> LATTER_EDGE_W<4> {
LATTER_EDGE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "UART ABRCR Auto-Baud Rate Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [abrcr](index.html) module"]
pub struct ABRCR_SPEC;
impl crate::RegisterSpec for ABRCR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [abrcr::R](R) reader structure"]
impl crate::Readable for ABRCR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [abrcr::W](W) writer structure"]
impl crate::Writable for ABRCR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets ABRCR to value 0"]
impl crate::Resettable for ABRCR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "IRDA (rw) register accessor: an alias for `Reg<IRDA_SPEC>`"]
pub type IRDA = crate::Reg<irda::IRDA_SPEC>;
#[doc = "UART IRDA infrared function control register"]
pub mod irda {
#[doc = "Register `IRDA` reader"]
pub struct R(crate::R<IRDA_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IRDA_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IRDA_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IRDA_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IRDA` writer"]
pub struct W(crate::W<IRDA_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IRDA_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IRDA_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IRDA_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `Siren` reader - "]
pub type SIREN_R = crate::BitReader<bool>;
#[doc = "Field `Siren` writer - "]
pub type SIREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRDA_SPEC, bool, O>;
#[doc = "Field `Sirlp` reader - "]
pub type SIRLP_R = crate::BitReader<bool>;
#[doc = "Field `Sirlp` writer - "]
pub type SIRLP_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRDA_SPEC, bool, O>;
#[doc = "Field `PSC_REG` reader - "]
pub type PSC_REG_R = crate::FieldReader<u8, u8>;
#[doc = "Field `PSC_REG` writer - "]
pub type PSC_REG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IRDA_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn siren(&self) -> SIREN_R {
SIREN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn sirlp(&self) -> SIRLP_R {
SIRLP_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 8:15"]
#[inline(always)]
pub fn psc_reg(&self) -> PSC_REG_R {
PSC_REG_R::new(((self.bits >> 8) & 0xff) as u8)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn siren(&mut self) -> SIREN_W<0> {
SIREN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn sirlp(&mut self) -> SIRLP_W<1> {
SIRLP_W::new(self)
}
#[doc = "Bits 8:15"]
#[inline(always)]
#[must_use]
pub fn psc_reg(&mut self) -> PSC_REG_W<8> {
PSC_REG_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "UART IRDA infrared function control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irda](index.html) module"]
pub struct IRDA_SPEC;
impl crate::RegisterSpec for IRDA_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [irda::R](R) reader structure"]
impl crate::Readable for IRDA_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [irda::W](W) writer structure"]
impl crate::Writable for IRDA_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets IRDA to value 0x0100"]
impl crate::Resettable for IRDA_SPEC {
const RESET_VALUE: Self::Ux = 0x0100;
}
}
}
#[doc = "UART2"]
pub struct UART2 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for UART2 {}
impl UART2 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const uart1::RegisterBlock = 0x4000_4400 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const uart1::RegisterBlock {
Self::PTR
}
}
impl Deref for UART2 {
type Target = uart1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for UART2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UART2").finish()
}
}
#[doc = "UART2"]
pub use self::uart1 as uart2;
#[doc = "UART3"]
pub struct UART3 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for UART3 {}
impl UART3 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const uart1::RegisterBlock = 0x4000_4800 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const uart1::RegisterBlock {
Self::PTR
}
}
impl Deref for UART3 {
type Target = uart1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for UART3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UART3").finish()
}
}
#[doc = "UART3"]
pub use self::uart1 as uart3;
#[doc = "UART4"]
pub struct UART4 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for UART4 {}
impl UART4 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const uart1::RegisterBlock = 0x4000_4c00 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const uart1::RegisterBlock {
Self::PTR
}
}
impl Deref for UART4 {
type Target = uart1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for UART4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UART4").finish()
}
}
#[doc = "UART4"]
pub use self::uart1 as uart4;
#[doc = "UART5"]
pub struct UART5 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for UART5 {}
impl UART5 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const uart1::RegisterBlock = 0x4000_5000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const uart1::RegisterBlock {
Self::PTR
}
}
impl Deref for UART5 {
type Target = uart1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for UART5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UART5").finish()
}
}
#[doc = "UART5"]
pub use self::uart1 as uart5;
#[doc = "UART6"]
pub struct UART6 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for UART6 {}
impl UART6 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const uart1::RegisterBlock = 0x4001_3c00 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const uart1::RegisterBlock {
Self::PTR
}
}
impl Deref for UART6 {
type Target = uart1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for UART6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UART6").finish()
}
}
#[doc = "UART6"]
pub use self::uart1 as uart6;
#[doc = "UART7"]
pub struct UART7 {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for UART7 {}
impl UART7 {
#[doc = r"Pointer to the register block"]
pub const PTR: *const uart1::RegisterBlock = 0x4000_7800 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const uart1::RegisterBlock {
Self::PTR
}
}
impl Deref for UART7 {
type Target = uart1::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for UART7 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("UART7").finish()
}
}
#[doc = "UART7"]
pub use self::uart1 as uart7;
#[doc = "USB"]
pub struct USB {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for USB {}
impl USB {
#[doc = r"Pointer to the register block"]
pub const PTR: *const usb::RegisterBlock = 0x5000_0000 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const usb::RegisterBlock {
Self::PTR
}
}
impl Deref for USB {
type Target = usb::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for USB {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("USB").finish()
}
}
#[doc = "USB"]
pub mod usb {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
_reserved0: [u8; 0x10],
#[doc = "0x10 - OTG Interrupt Status Register"]
pub fsotg_istat: FSOTG_ISTAT,
#[doc = "0x14 - OTG Interrupt Control Register"]
pub fsotg_ictrl: FSOTG_ICTRL,
#[doc = "0x18 - OTG Status Register"]
pub fsotg_stat: FSOTG_STAT,
#[doc = "0x1c - OTG Control register"]
pub fsotg_ctrl: FSOTG_CTRL,
_reserved4: [u8; 0x60],
#[doc = "0x80 - Interrupt status register"]
pub fsint_stat: FSINT_STAT,
#[doc = "0x84 - Interrupt enable register"]
pub fsint_enb: FSINT_ENB,
#[doc = "0x88 - Error interrupt status register"]
pub fserr_stat: FSERR_STAT,
#[doc = "0x8c - Error interrupt enable register"]
pub fserr_enb: FSERR_ENB,
#[doc = "0x90 - Status register"]
pub fsstat: FSSTAT,
#[doc = "0x94 - Control register"]
pub fsctl: FSCTL,
#[doc = "0x98 - Address register"]
pub fsaddr: FSADDR,
#[doc = "0x9c - BDT page register 1"]
pub fsbdt_page_01: FSBDT_PAGE_01,
#[doc = "0xa0 - Frame number register"]
pub fsfrm_numl: FSFRM_NUML,
#[doc = "0xa4 - Frame number register"]
pub fsfrm_numh: FSFRM_NUMH,
#[doc = "0xa8 - Token register"]
pub fstoken: FSTOKEN,
#[doc = "0xac - SOF threshold register"]
pub fssof_thld: FSSOF_THLD,
#[doc = "0xb0 - BDT page register 2"]
pub fsbdt_page_02: FSBDT_PAGE_02,
#[doc = "0xb4 - BDT page register 3"]
pub fsbdt_page_03: FSBDT_PAGE_03,
_reserved18: [u8; 0x08],
#[doc = "0xc0 - Endpoint control register 0"]
pub fsep0_ctl: FSEP0_CTL,
#[doc = "0xc4 - Endpoint control register 0"]
pub fsep1_ctl: FSEP1_CTL,
#[doc = "0xc8 - Endpoint control register 0"]
pub fsep2_ctl: FSEP2_CTL,
#[doc = "0xcc - Endpoint control register 0"]
pub fsep3_ctl: FSEP3_CTL,
#[doc = "0xd0 - Endpoint control register 0"]
pub fsep4_ctl: FSEP4_CTL,
#[doc = "0xd4 - Endpoint control register 0"]
pub fsep5_ctl: FSEP5_CTL,
#[doc = "0xd8 - Endpoint control register 0"]
pub fsep6_ctl: FSEP6_CTL,
#[doc = "0xdc - Endpoint control register 0"]
pub fsep7_ctl: FSEP7_CTL,
#[doc = "0xe0 - Endpoint control register 0"]
pub fsep8_ctl: FSEP8_CTL,
#[doc = "0xe4 - Endpoint control register 0"]
pub fsep9_ctl: FSEP9_CTL,
#[doc = "0xe8 - Endpoint control register 0"]
pub fsep10_ctl: FSEP10_CTL,
#[doc = "0xec - Endpoint control register 0"]
pub fsep11_ctl: FSEP11_CTL,
#[doc = "0xf0 - Endpoint control register 0"]
pub fsep12_ctl: FSEP12_CTL,
#[doc = "0xf4 - Endpoint control register 0"]
pub fsep13_ctl: FSEP13_CTL,
#[doc = "0xf8 - Endpoint control register 0"]
pub fsep14_ctl: FSEP14_CTL,
#[doc = "0xfc - Endpoint control register 0"]
pub fsep15_ctl: FSEP15_CTL,
#[doc = "0x100 - USB Control register"]
pub fsusbctrl: FSUSBCTRL,
}
#[doc = "FSOTG_ISTAT (rw) register accessor: an alias for `Reg<FSOTG_ISTAT_SPEC>`"]
pub type FSOTG_ISTAT = crate::Reg<fsotg_istat::FSOTG_ISTAT_SPEC>;
#[doc = "OTG Interrupt Status Register"]
pub mod fsotg_istat {
#[doc = "Register `FSOTG_ISTAT` reader"]
pub struct R(crate::R<FSOTG_ISTAT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSOTG_ISTAT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSOTG_ISTAT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSOTG_ISTAT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSOTG_ISTAT` writer"]
pub struct W(crate::W<FSOTG_ISTAT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSOTG_ISTAT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSOTG_ISTAT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSOTG_ISTAT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `A_VBUS_VLD_CHG` reader - "]
pub type A_VBUS_VLD_CHG_R = crate::BitReader<bool>;
#[doc = "Field `A_VBUS_VLD_CHG` writer - "]
pub type A_VBUS_VLD_CHG_W<'a, const O: u8> =
crate::BitWriter1C<'a, u32, FSOTG_ISTAT_SPEC, bool, O>;
#[doc = "Field `B_SESS_END_CHG` reader - "]
pub type B_SESS_END_CHG_R = crate::BitReader<bool>;
#[doc = "Field `B_SESS_END_CHG` writer - "]
pub type B_SESS_END_CHG_W<'a, const O: u8> =
crate::BitWriter1C<'a, u32, FSOTG_ISTAT_SPEC, bool, O>;
#[doc = "Field `SESS_VLD_CHG` reader - "]
pub type SESS_VLD_CHG_R = crate::BitReader<bool>;
#[doc = "Field `SESS_VLD_CHG` writer - "]
pub type SESS_VLD_CHG_W<'a, const O: u8> =
crate::BitWriter1C<'a, u32, FSOTG_ISTAT_SPEC, bool, O>;
#[doc = "Field `LINE_STATE_CHG` reader - "]
pub type LINE_STATE_CHG_R = crate::BitReader<bool>;
#[doc = "Field `LINE_STATE_CHG` writer - "]
pub type LINE_STATE_CHG_W<'a, const O: u8> =
crate::BitWriter1C<'a, u32, FSOTG_ISTAT_SPEC, bool, O>;
#[doc = "Field `1_MSEC` reader - "]
pub type _1_MSEC_R = crate::BitReader<bool>;
#[doc = "Field `1_MSEC` writer - "]
pub type _1_MSEC_W<'a, const O: u8> =
crate::BitWriter1C<'a, u32, FSOTG_ISTAT_SPEC, bool, O>;
#[doc = "Field `ID_CHG` reader - "]
pub type ID_CHG_R = crate::BitReader<bool>;
#[doc = "Field `ID_CHG` writer - "]
pub type ID_CHG_W<'a, const O: u8> = crate::BitWriter1C<'a, u32, FSOTG_ISTAT_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn a_vbus_vld_chg(&self) -> A_VBUS_VLD_CHG_R {
A_VBUS_VLD_CHG_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn b_sess_end_chg(&self) -> B_SESS_END_CHG_R {
B_SESS_END_CHG_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn sess_vld_chg(&self) -> SESS_VLD_CHG_R {
SESS_VLD_CHG_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn line_state_chg(&self) -> LINE_STATE_CHG_R {
LINE_STATE_CHG_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn _1_msec(&self) -> _1_MSEC_R {
_1_MSEC_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn id_chg(&self) -> ID_CHG_R {
ID_CHG_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn a_vbus_vld_chg(&mut self) -> A_VBUS_VLD_CHG_W<0> {
A_VBUS_VLD_CHG_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn b_sess_end_chg(&mut self) -> B_SESS_END_CHG_W<2> {
B_SESS_END_CHG_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn sess_vld_chg(&mut self) -> SESS_VLD_CHG_W<3> {
SESS_VLD_CHG_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn line_state_chg(&mut self) -> LINE_STATE_CHG_W<5> {
LINE_STATE_CHG_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn _1_msec(&mut self) -> _1_MSEC_W<6> {
_1_MSEC_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn id_chg(&mut self) -> ID_CHG_W<7> {
ID_CHG_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "OTG Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsotg_istat](index.html) module"]
pub struct FSOTG_ISTAT_SPEC;
impl crate::RegisterSpec for FSOTG_ISTAT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fsotg_istat::R](R) reader structure"]
impl crate::Readable for FSOTG_ISTAT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fsotg_istat::W](W) writer structure"]
impl crate::Writable for FSOTG_ISTAT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0xed;
}
#[doc = "`reset()` method sets FSOTG_ISTAT to value 0xe8"]
impl crate::Resettable for FSOTG_ISTAT_SPEC {
const RESET_VALUE: Self::Ux = 0xe8;
}
}
#[doc = "FSOTG_ICTRL (rw) register accessor: an alias for `Reg<FSOTG_ICTRL_SPEC>`"]
pub type FSOTG_ICTRL = crate::Reg<fsotg_ictrl::FSOTG_ICTRL_SPEC>;
#[doc = "OTG Interrupt Control Register"]
pub mod fsotg_ictrl {
#[doc = "Register `FSOTG_ICTRL` reader"]
pub struct R(crate::R<FSOTG_ICTRL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSOTG_ICTRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSOTG_ICTRL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSOTG_ICTRL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSOTG_ICTRL` writer"]
pub struct W(crate::W<FSOTG_ICTRL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSOTG_ICTRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSOTG_ICTRL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSOTG_ICTRL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `A_VBUS_VLD_EN` reader - "]
pub type A_VBUS_VLD_EN_R = crate::BitReader<bool>;
#[doc = "Field `A_VBUS_VLD_EN` writer - "]
pub type A_VBUS_VLD_EN_W<'a, const O: u8> =
crate::BitWriter<'a, u32, FSOTG_ICTRL_SPEC, bool, O>;
#[doc = "Field `B_SESS_END_EN` reader - "]
pub type B_SESS_END_EN_R = crate::BitReader<bool>;
#[doc = "Field `B_SESS_END_EN` writer - "]
pub type B_SESS_END_EN_W<'a, const O: u8> =
crate::BitWriter<'a, u32, FSOTG_ICTRL_SPEC, bool, O>;
#[doc = "Field `SESS_VLD_EN` reader - "]
pub type SESS_VLD_EN_R = crate::BitReader<bool>;
#[doc = "Field `SESS_VLD_EN` writer - "]
pub type SESS_VLD_EN_W<'a, const O: u8> =
crate::BitWriter<'a, u32, FSOTG_ICTRL_SPEC, bool, O>;
#[doc = "Field `LINESTATE_EN` reader - "]
pub type LINESTATE_EN_R = crate::BitReader<bool>;
#[doc = "Field `LINESTATE_EN` writer - "]
pub type LINESTATE_EN_W<'a, const O: u8> =
crate::BitWriter<'a, u32, FSOTG_ICTRL_SPEC, bool, O>;
#[doc = "Field `1_MSEC_EN` reader - "]
pub type _1_MSEC_EN_R = crate::BitReader<bool>;
#[doc = "Field `1_MSEC_EN` writer - "]
pub type _1_MSEC_EN_W<'a, const O: u8> =
crate::BitWriter<'a, u32, FSOTG_ICTRL_SPEC, bool, O>;
#[doc = "Field `ID_EN` reader - "]
pub type ID_EN_R = crate::BitReader<bool>;
#[doc = "Field `ID_EN` writer - "]
pub type ID_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSOTG_ICTRL_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn a_vbus_vld_en(&self) -> A_VBUS_VLD_EN_R {
A_VBUS_VLD_EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn b_sess_end_en(&self) -> B_SESS_END_EN_R {
B_SESS_END_EN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn sess_vld_en(&self) -> SESS_VLD_EN_R {
SESS_VLD_EN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn linestate_en(&self) -> LINESTATE_EN_R {
LINESTATE_EN_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn _1_msec_en(&self) -> _1_MSEC_EN_R {
_1_MSEC_EN_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn id_en(&self) -> ID_EN_R {
ID_EN_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn a_vbus_vld_en(&mut self) -> A_VBUS_VLD_EN_W<0> {
A_VBUS_VLD_EN_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn b_sess_end_en(&mut self) -> B_SESS_END_EN_W<2> {
B_SESS_END_EN_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn sess_vld_en(&mut self) -> SESS_VLD_EN_W<3> {
SESS_VLD_EN_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn linestate_en(&mut self) -> LINESTATE_EN_W<5> {
LINESTATE_EN_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn _1_msec_en(&mut self) -> _1_MSEC_EN_W<6> {
_1_MSEC_EN_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn id_en(&mut self) -> ID_EN_W<7> {
ID_EN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "OTG Interrupt Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsotg_ictrl](index.html) module"]
pub struct FSOTG_ICTRL_SPEC;
impl crate::RegisterSpec for FSOTG_ICTRL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fsotg_ictrl::R](R) reader structure"]
impl crate::Readable for FSOTG_ICTRL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fsotg_ictrl::W](W) writer structure"]
impl crate::Writable for FSOTG_ICTRL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSOTG_ICTRL to value 0"]
impl crate::Resettable for FSOTG_ICTRL_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "FSOTG_STAT (rw) register accessor: an alias for `Reg<FSOTG_STAT_SPEC>`"]
pub type FSOTG_STAT = crate::Reg<fsotg_stat::FSOTG_STAT_SPEC>;
#[doc = "OTG Status Register"]
pub mod fsotg_stat {
#[doc = "Register `FSOTG_STAT` reader"]
pub struct R(crate::R<FSOTG_STAT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSOTG_STAT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSOTG_STAT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSOTG_STAT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSOTG_STAT` writer"]
pub struct W(crate::W<FSOTG_STAT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSOTG_STAT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSOTG_STAT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSOTG_STAT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `A_VBUS_VLD` reader - "]
pub type A_VBUS_VLD_R = crate::BitReader<bool>;
#[doc = "Field `A_VBUS_VLD` writer - "]
pub type A_VBUS_VLD_W<'a, const O: u8> =
crate::BitWriter<'a, u32, FSOTG_STAT_SPEC, bool, O>;
#[doc = "Field `B_SESS_END` reader - "]
pub type B_SESS_END_R = crate::BitReader<bool>;
#[doc = "Field `B_SESS_END` writer - "]
pub type B_SESS_END_W<'a, const O: u8> =
crate::BitWriter<'a, u32, FSOTG_STAT_SPEC, bool, O>;
#[doc = "Field `SESS_VLD` reader - "]
pub type SESS_VLD_R = crate::BitReader<bool>;
#[doc = "Field `SESS_VLD` writer - "]
pub type SESS_VLD_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSOTG_STAT_SPEC, bool, O>;
#[doc = "Field `LINESTATE_STABLE` reader - "]
pub type LINESTATE_STABLE_R = crate::BitReader<bool>;
#[doc = "Field `LINESTATE_STABLE` writer - "]
pub type LINESTATE_STABLE_W<'a, const O: u8> =
crate::BitWriter<'a, u32, FSOTG_STAT_SPEC, bool, O>;
#[doc = "Field `ID` reader - "]
pub type ID_R = crate::BitReader<bool>;
#[doc = "Field `ID` writer - "]
pub type ID_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSOTG_STAT_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn a_vbus_vld(&self) -> A_VBUS_VLD_R {
A_VBUS_VLD_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn b_sess_end(&self) -> B_SESS_END_R {
B_SESS_END_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn sess_vld(&self) -> SESS_VLD_R {
SESS_VLD_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn linestate_stable(&self) -> LINESTATE_STABLE_R {
LINESTATE_STABLE_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn id(&self) -> ID_R {
ID_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn a_vbus_vld(&mut self) -> A_VBUS_VLD_W<0> {
A_VBUS_VLD_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn b_sess_end(&mut self) -> B_SESS_END_W<2> {
B_SESS_END_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn sess_vld(&mut self) -> SESS_VLD_W<3> {
SESS_VLD_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn linestate_stable(&mut self) -> LINESTATE_STABLE_W<5> {
LINESTATE_STABLE_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn id(&mut self) -> ID_W<7> {
ID_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "OTG Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsotg_stat](index.html) module"]
pub struct FSOTG_STAT_SPEC;
impl crate::RegisterSpec for FSOTG_STAT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fsotg_stat::R](R) reader structure"]
impl crate::Readable for FSOTG_STAT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fsotg_stat::W](W) writer structure"]
impl crate::Writable for FSOTG_STAT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSOTG_STAT to value 0xa8"]
impl crate::Resettable for FSOTG_STAT_SPEC {
const RESET_VALUE: Self::Ux = 0xa8;
}
}
#[doc = "FSOTG_CTRL (rw) register accessor: an alias for `Reg<FSOTG_CTRL_SPEC>`"]
pub type FSOTG_CTRL = crate::Reg<fsotg_ctrl::FSOTG_CTRL_SPEC>;
#[doc = "OTG Control register"]
pub mod fsotg_ctrl {
#[doc = "Register `FSOTG_CTRL` reader"]
pub struct R(crate::R<FSOTG_CTRL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSOTG_CTRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSOTG_CTRL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSOTG_CTRL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSOTG_CTRL` writer"]
pub struct W(crate::W<FSOTG_CTRL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSOTG_CTRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSOTG_CTRL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSOTG_CTRL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `VBUS_DSCHG` reader - "]
pub type VBUS_DSCHG_R = crate::BitReader<bool>;
#[doc = "Field `VBUS_DSCHG` writer - "]
pub type VBUS_DSCHG_W<'a, const O: u8> =
crate::BitWriter<'a, u32, FSOTG_CTRL_SPEC, bool, O>;
#[doc = "Field `VBUS_CHG` reader - "]
pub type VBUS_CHG_R = crate::BitReader<bool>;
#[doc = "Field `VBUS_CHG` writer - "]
pub type VBUS_CHG_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSOTG_CTRL_SPEC, bool, O>;
#[doc = "Field `OTG_EN` reader - "]
pub type OTG_EN_R = crate::BitReader<bool>;
#[doc = "Field `OTG_EN` writer - "]
pub type OTG_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSOTG_CTRL_SPEC, bool, O>;
#[doc = "Field `VBUS_ON` reader - "]
pub type VBUS_ON_R = crate::BitReader<bool>;
#[doc = "Field `VBUS_ON` writer - "]
pub type VBUS_ON_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSOTG_CTRL_SPEC, bool, O>;
#[doc = "Field `DM_LOW` reader - "]
pub type DM_LOW_R = crate::BitReader<bool>;
#[doc = "Field `DM_LOW` writer - "]
pub type DM_LOW_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSOTG_CTRL_SPEC, bool, O>;
#[doc = "Field `DP_LOW` reader - "]
pub type DP_LOW_R = crate::BitReader<bool>;
#[doc = "Field `DP_LOW` writer - "]
pub type DP_LOW_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSOTG_CTRL_SPEC, bool, O>;
#[doc = "Field `DM_HIGH` reader - "]
pub type DM_HIGH_R = crate::BitReader<bool>;
#[doc = "Field `DM_HIGH` writer - "]
pub type DM_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSOTG_CTRL_SPEC, bool, O>;
#[doc = "Field `DP_HIGH` reader - "]
pub type DP_HIGH_R = crate::BitReader<bool>;
#[doc = "Field `DP_HIGH` writer - "]
pub type DP_HIGH_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSOTG_CTRL_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn vbus_dschg(&self) -> VBUS_DSCHG_R {
VBUS_DSCHG_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn vbus_chg(&self) -> VBUS_CHG_R {
VBUS_CHG_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn otg_en(&self) -> OTG_EN_R {
OTG_EN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn vbus_on(&self) -> VBUS_ON_R {
VBUS_ON_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn dm_low(&self) -> DM_LOW_R {
DM_LOW_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn dp_low(&self) -> DP_LOW_R {
DP_LOW_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn dm_high(&self) -> DM_HIGH_R {
DM_HIGH_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn dp_high(&self) -> DP_HIGH_R {
DP_HIGH_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn vbus_dschg(&mut self) -> VBUS_DSCHG_W<0> {
VBUS_DSCHG_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn vbus_chg(&mut self) -> VBUS_CHG_W<1> {
VBUS_CHG_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn otg_en(&mut self) -> OTG_EN_W<2> {
OTG_EN_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn vbus_on(&mut self) -> VBUS_ON_W<3> {
VBUS_ON_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn dm_low(&mut self) -> DM_LOW_W<4> {
DM_LOW_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn dp_low(&mut self) -> DP_LOW_W<5> {
DP_LOW_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn dm_high(&mut self) -> DM_HIGH_W<6> {
DM_HIGH_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn dp_high(&mut self) -> DP_HIGH_W<7> {
DP_HIGH_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "OTG Control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsotg_ctrl](index.html) module"]
pub struct FSOTG_CTRL_SPEC;
impl crate::RegisterSpec for FSOTG_CTRL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fsotg_ctrl::R](R) reader structure"]
impl crate::Readable for FSOTG_CTRL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fsotg_ctrl::W](W) writer structure"]
impl crate::Writable for FSOTG_CTRL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSOTG_CTRL to value 0"]
impl crate::Resettable for FSOTG_CTRL_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "FSINT_STAT (rw) register accessor: an alias for `Reg<FSINT_STAT_SPEC>`"]
pub type FSINT_STAT = crate::Reg<fsint_stat::FSINT_STAT_SPEC>;
#[doc = "Interrupt status register"]
pub mod fsint_stat {
#[doc = "Register `FSINT_STAT` reader"]
pub struct R(crate::R<FSINT_STAT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSINT_STAT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSINT_STAT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSINT_STAT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSINT_STAT` writer"]
pub struct W(crate::W<FSINT_STAT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSINT_STAT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSINT_STAT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSINT_STAT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `USB_RST` reader - "]
pub type USB_RST_R = crate::BitReader<bool>;
#[doc = "Field `USB_RST` writer - "]
pub type USB_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSINT_STAT_SPEC, bool, O>;
#[doc = "Field `ERROR` reader - "]
pub type ERROR_R = crate::BitReader<bool>;
#[doc = "Field `ERROR` writer - "]
pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSINT_STAT_SPEC, bool, O>;
#[doc = "Field `SOF_TOK` reader - "]
pub type SOF_TOK_R = crate::BitReader<bool>;
#[doc = "Field `SOF_TOK` writer - "]
pub type SOF_TOK_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSINT_STAT_SPEC, bool, O>;
#[doc = "Field `TOK_DNE` reader - "]
pub type TOK_DNE_R = crate::BitReader<bool>;
#[doc = "Field `TOK_DNE` writer - "]
pub type TOK_DNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSINT_STAT_SPEC, bool, O>;
#[doc = "Field `SLEEP` reader - "]
pub type SLEEP_R = crate::BitReader<bool>;
#[doc = "Field `SLEEP` writer - "]
pub type SLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSINT_STAT_SPEC, bool, O>;
#[doc = "Field `RESUME` reader - "]
pub type RESUME_R = crate::BitReader<bool>;
#[doc = "Field `RESUME` writer - "]
pub type RESUME_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSINT_STAT_SPEC, bool, O>;
#[doc = "Field `ATTACH` reader - "]
pub type ATTACH_R = crate::BitReader<bool>;
#[doc = "Field `ATTACH` writer - "]
pub type ATTACH_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSINT_STAT_SPEC, bool, O>;
#[doc = "Field `STALL` reader - "]
pub type STALL_R = crate::BitReader<bool>;
#[doc = "Field `STALL` writer - "]
pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSINT_STAT_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn usb_rst(&self) -> USB_RST_R {
USB_RST_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn error(&self) -> ERROR_R {
ERROR_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn sof_tok(&self) -> SOF_TOK_R {
SOF_TOK_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn tok_dne(&self) -> TOK_DNE_R {
TOK_DNE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn sleep(&self) -> SLEEP_R {
SLEEP_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn resume(&self) -> RESUME_R {
RESUME_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn attach(&self) -> ATTACH_R {
ATTACH_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn stall(&self) -> STALL_R {
STALL_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn usb_rst(&mut self) -> USB_RST_W<0> {
USB_RST_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn error(&mut self) -> ERROR_W<1> {
ERROR_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn sof_tok(&mut self) -> SOF_TOK_W<2> {
SOF_TOK_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn tok_dne(&mut self) -> TOK_DNE_W<3> {
TOK_DNE_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn sleep(&mut self) -> SLEEP_W<4> {
SLEEP_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn resume(&mut self) -> RESUME_W<5> {
RESUME_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn attach(&mut self) -> ATTACH_W<6> {
ATTACH_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn stall(&mut self) -> STALL_W<7> {
STALL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Interrupt status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsint_stat](index.html) module"]
pub struct FSINT_STAT_SPEC;
impl crate::RegisterSpec for FSINT_STAT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fsint_stat::R](R) reader structure"]
impl crate::Readable for FSINT_STAT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fsint_stat::W](W) writer structure"]
impl crate::Writable for FSINT_STAT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSINT_STAT to value 0x01"]
impl crate::Resettable for FSINT_STAT_SPEC {
const RESET_VALUE: Self::Ux = 0x01;
}
}
#[doc = "FSINT_ENB (rw) register accessor: an alias for `Reg<FSINT_ENB_SPEC>`"]
pub type FSINT_ENB = crate::Reg<fsint_enb::FSINT_ENB_SPEC>;
#[doc = "Interrupt enable register"]
pub mod fsint_enb {
#[doc = "Register `FSINT_ENB` reader"]
pub struct R(crate::R<FSINT_ENB_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSINT_ENB_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSINT_ENB_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSINT_ENB_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSINT_ENB` writer"]
pub struct W(crate::W<FSINT_ENB_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSINT_ENB_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSINT_ENB_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSINT_ENB_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `USB_RST` reader - "]
pub type USB_RST_R = crate::BitReader<bool>;
#[doc = "Field `USB_RST` writer - "]
pub type USB_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSINT_ENB_SPEC, bool, O>;
#[doc = "Field `ERROR` reader - "]
pub type ERROR_R = crate::BitReader<bool>;
#[doc = "Field `ERROR` writer - "]
pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSINT_ENB_SPEC, bool, O>;
#[doc = "Field `SOF_TOK` reader - "]
pub type SOF_TOK_R = crate::BitReader<bool>;
#[doc = "Field `SOF_TOK` writer - "]
pub type SOF_TOK_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSINT_ENB_SPEC, bool, O>;
#[doc = "Field `TOK_DNE` reader - "]
pub type TOK_DNE_R = crate::BitReader<bool>;
#[doc = "Field `TOK_DNE` writer - "]
pub type TOK_DNE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSINT_ENB_SPEC, bool, O>;
#[doc = "Field `SLEEP` reader - "]
pub type SLEEP_R = crate::BitReader<bool>;
#[doc = "Field `SLEEP` writer - "]
pub type SLEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSINT_ENB_SPEC, bool, O>;
#[doc = "Field `RESUME` reader - "]
pub type RESUME_R = crate::BitReader<bool>;
#[doc = "Field `RESUME` writer - "]
pub type RESUME_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSINT_ENB_SPEC, bool, O>;
#[doc = "Field `ATTACH` reader - "]
pub type ATTACH_R = crate::BitReader<bool>;
#[doc = "Field `ATTACH` writer - "]
pub type ATTACH_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSINT_ENB_SPEC, bool, O>;
#[doc = "Field `STALL` reader - "]
pub type STALL_R = crate::BitReader<bool>;
#[doc = "Field `STALL` writer - "]
pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSINT_ENB_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn usb_rst(&self) -> USB_RST_R {
USB_RST_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn error(&self) -> ERROR_R {
ERROR_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn sof_tok(&self) -> SOF_TOK_R {
SOF_TOK_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn tok_dne(&self) -> TOK_DNE_R {
TOK_DNE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn sleep(&self) -> SLEEP_R {
SLEEP_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn resume(&self) -> RESUME_R {
RESUME_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn attach(&self) -> ATTACH_R {
ATTACH_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn stall(&self) -> STALL_R {
STALL_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn usb_rst(&mut self) -> USB_RST_W<0> {
USB_RST_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn error(&mut self) -> ERROR_W<1> {
ERROR_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn sof_tok(&mut self) -> SOF_TOK_W<2> {
SOF_TOK_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn tok_dne(&mut self) -> TOK_DNE_W<3> {
TOK_DNE_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn sleep(&mut self) -> SLEEP_W<4> {
SLEEP_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn resume(&mut self) -> RESUME_W<5> {
RESUME_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn attach(&mut self) -> ATTACH_W<6> {
ATTACH_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn stall(&mut self) -> STALL_W<7> {
STALL_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Interrupt enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsint_enb](index.html) module"]
pub struct FSINT_ENB_SPEC;
impl crate::RegisterSpec for FSINT_ENB_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fsint_enb::R](R) reader structure"]
impl crate::Readable for FSINT_ENB_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fsint_enb::W](W) writer structure"]
impl crate::Writable for FSINT_ENB_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSINT_ENB to value 0"]
impl crate::Resettable for FSINT_ENB_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "FSERR_STAT (rw) register accessor: an alias for `Reg<FSERR_STAT_SPEC>`"]
pub type FSERR_STAT = crate::Reg<fserr_stat::FSERR_STAT_SPEC>;
#[doc = "Error interrupt status register"]
pub mod fserr_stat {
#[doc = "Register `FSERR_STAT` reader"]
pub struct R(crate::R<FSERR_STAT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSERR_STAT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSERR_STAT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSERR_STAT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSERR_STAT` writer"]
pub struct W(crate::W<FSERR_STAT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSERR_STAT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSERR_STAT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSERR_STAT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PID_ERR` reader - "]
pub type PID_ERR_R = crate::BitReader<bool>;
#[doc = "Field `PID_ERR` writer - "]
pub type PID_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSERR_STAT_SPEC, bool, O>;
#[doc = "Field `CRC5EOF` reader - "]
pub type CRC5EOF_R = crate::BitReader<bool>;
#[doc = "Field `CRC5EOF` writer - "]
pub type CRC5EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSERR_STAT_SPEC, bool, O>;
#[doc = "Field `CRC16` reader - "]
pub type CRC16_R = crate::BitReader<bool>;
#[doc = "Field `CRC16` writer - "]
pub type CRC16_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSERR_STAT_SPEC, bool, O>;
#[doc = "Field `DFN8` reader - "]
pub type DFN8_R = crate::BitReader<bool>;
#[doc = "Field `DFN8` writer - "]
pub type DFN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSERR_STAT_SPEC, bool, O>;
#[doc = "Field `BTO_ERR` reader - "]
pub type BTO_ERR_R = crate::BitReader<bool>;
#[doc = "Field `BTO_ERR` writer - "]
pub type BTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSERR_STAT_SPEC, bool, O>;
#[doc = "Field `DMA_ERR` reader - "]
pub type DMA_ERR_R = crate::BitReader<bool>;
#[doc = "Field `DMA_ERR` writer - "]
pub type DMA_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSERR_STAT_SPEC, bool, O>;
#[doc = "Field `BTS_ERR` reader - "]
pub type BTS_ERR_R = crate::BitReader<bool>;
#[doc = "Field `BTS_ERR` writer - "]
pub type BTS_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSERR_STAT_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pid_err(&self) -> PID_ERR_R {
PID_ERR_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn crc5eof(&self) -> CRC5EOF_R {
CRC5EOF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn crc16(&self) -> CRC16_R {
CRC16_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn dfn8(&self) -> DFN8_R {
DFN8_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn bto_err(&self) -> BTO_ERR_R {
BTO_ERR_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn dma_err(&self) -> DMA_ERR_R {
DMA_ERR_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn bts_err(&self) -> BTS_ERR_R {
BTS_ERR_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pid_err(&mut self) -> PID_ERR_W<0> {
PID_ERR_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn crc5eof(&mut self) -> CRC5EOF_W<1> {
CRC5EOF_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn crc16(&mut self) -> CRC16_W<2> {
CRC16_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn dfn8(&mut self) -> DFN8_W<3> {
DFN8_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn bto_err(&mut self) -> BTO_ERR_W<4> {
BTO_ERR_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn dma_err(&mut self) -> DMA_ERR_W<5> {
DMA_ERR_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn bts_err(&mut self) -> BTS_ERR_W<7> {
BTS_ERR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Error interrupt status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fserr_stat](index.html) module"]
pub struct FSERR_STAT_SPEC;
impl crate::RegisterSpec for FSERR_STAT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fserr_stat::R](R) reader structure"]
impl crate::Readable for FSERR_STAT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fserr_stat::W](W) writer structure"]
impl crate::Writable for FSERR_STAT_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSERR_STAT to value 0"]
impl crate::Resettable for FSERR_STAT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "FSERR_ENB (rw) register accessor: an alias for `Reg<FSERR_ENB_SPEC>`"]
pub type FSERR_ENB = crate::Reg<fserr_enb::FSERR_ENB_SPEC>;
#[doc = "Error interrupt enable register"]
pub mod fserr_enb {
#[doc = "Register `FSERR_ENB` reader"]
pub struct R(crate::R<FSERR_ENB_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSERR_ENB_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSERR_ENB_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSERR_ENB_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSERR_ENB` writer"]
pub struct W(crate::W<FSERR_ENB_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSERR_ENB_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSERR_ENB_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSERR_ENB_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `PID_ERR` reader - "]
pub type PID_ERR_R = crate::BitReader<bool>;
#[doc = "Field `PID_ERR` writer - "]
pub type PID_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSERR_ENB_SPEC, bool, O>;
#[doc = "Field `CRC5EOF` reader - "]
pub type CRC5EOF_R = crate::BitReader<bool>;
#[doc = "Field `CRC5EOF` writer - "]
pub type CRC5EOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSERR_ENB_SPEC, bool, O>;
#[doc = "Field `CRC16` reader - "]
pub type CRC16_R = crate::BitReader<bool>;
#[doc = "Field `CRC16` writer - "]
pub type CRC16_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSERR_ENB_SPEC, bool, O>;
#[doc = "Field `DFN8` reader - "]
pub type DFN8_R = crate::BitReader<bool>;
#[doc = "Field `DFN8` writer - "]
pub type DFN8_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSERR_ENB_SPEC, bool, O>;
#[doc = "Field `BTO_ERR` reader - "]
pub type BTO_ERR_R = crate::BitReader<bool>;
#[doc = "Field `BTO_ERR` writer - "]
pub type BTO_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSERR_ENB_SPEC, bool, O>;
#[doc = "Field `DMA_ERR` reader - "]
pub type DMA_ERR_R = crate::BitReader<bool>;
#[doc = "Field `DMA_ERR` writer - "]
pub type DMA_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSERR_ENB_SPEC, bool, O>;
#[doc = "Field `BTS_ERR` reader - "]
pub type BTS_ERR_R = crate::BitReader<bool>;
#[doc = "Field `BTS_ERR` writer - "]
pub type BTS_ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSERR_ENB_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn pid_err(&self) -> PID_ERR_R {
PID_ERR_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn crc5eof(&self) -> CRC5EOF_R {
CRC5EOF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn crc16(&self) -> CRC16_R {
CRC16_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn dfn8(&self) -> DFN8_R {
DFN8_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn bto_err(&self) -> BTO_ERR_R {
BTO_ERR_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn dma_err(&self) -> DMA_ERR_R {
DMA_ERR_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn bts_err(&self) -> BTS_ERR_R {
BTS_ERR_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn pid_err(&mut self) -> PID_ERR_W<0> {
PID_ERR_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn crc5eof(&mut self) -> CRC5EOF_W<1> {
CRC5EOF_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn crc16(&mut self) -> CRC16_W<2> {
CRC16_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn dfn8(&mut self) -> DFN8_W<3> {
DFN8_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn bto_err(&mut self) -> BTO_ERR_W<4> {
BTO_ERR_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn dma_err(&mut self) -> DMA_ERR_W<5> {
DMA_ERR_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn bts_err(&mut self) -> BTS_ERR_W<7> {
BTS_ERR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Error interrupt enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fserr_enb](index.html) module"]
pub struct FSERR_ENB_SPEC;
impl crate::RegisterSpec for FSERR_ENB_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fserr_enb::R](R) reader structure"]
impl crate::Readable for FSERR_ENB_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fserr_enb::W](W) writer structure"]
impl crate::Writable for FSERR_ENB_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSERR_ENB to value 0"]
impl crate::Resettable for FSERR_ENB_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "FSSTAT (r) register accessor: an alias for `Reg<FSSTAT_SPEC>`"]
pub type FSSTAT = crate::Reg<fsstat::FSSTAT_SPEC>;
#[doc = "Status register"]
pub mod fsstat {
#[doc = "Register `FSSTAT` reader"]
pub struct R(crate::R<FSSTAT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSSTAT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSSTAT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSSTAT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Field `ODD` reader - "]
pub type ODD_R = crate::BitReader<bool>;
#[doc = "Field `TX` reader - "]
pub type TX_R = crate::BitReader<bool>;
#[doc = "Field `ENDP` reader - "]
pub type ENDP_R = crate::FieldReader<u8, u8>;
impl R {
#[doc = "Bit 2"]
#[inline(always)]
pub fn odd(&self) -> ODD_R {
ODD_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn tx(&self) -> TX_R {
TX_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn endp(&self) -> ENDP_R {
ENDP_R::new(((self.bits >> 4) & 0x0f) as u8)
}
}
#[doc = "Status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsstat](index.html) module"]
pub struct FSSTAT_SPEC;
impl crate::RegisterSpec for FSSTAT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fsstat::R](R) reader structure"]
impl crate::Readable for FSSTAT_SPEC {
type Reader = R;
}
#[doc = "`reset()` method sets FSSTAT to value 0"]
impl crate::Resettable for FSSTAT_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "FSCTL (rw) register accessor: an alias for `Reg<FSCTL_SPEC>`"]
pub type FSCTL = crate::Reg<fsctl::FSCTL_SPEC>;
#[doc = "Control register"]
pub mod fsctl {
#[doc = "Register `FSCTL` reader"]
pub struct R(crate::R<FSCTL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSCTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSCTL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSCTL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSCTL` writer"]
pub struct W(crate::W<FSCTL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSCTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSCTL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSCTL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `USB_EN` reader - "]
pub type USB_EN_R = crate::BitReader<bool>;
#[doc = "Field `USB_EN` writer - "]
pub type USB_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSCTL_SPEC, bool, O>;
#[doc = "Field `ODD_RST` reader - "]
pub type ODD_RST_R = crate::BitReader<bool>;
#[doc = "Field `ODD_RST` writer - "]
pub type ODD_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSCTL_SPEC, bool, O>;
#[doc = "Field `RESUME` reader - "]
pub type RESUME_R = crate::BitReader<bool>;
#[doc = "Field `RESUME` writer - "]
pub type RESUME_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSCTL_SPEC, bool, O>;
#[doc = "Field `HOST_MODE_EN` reader - "]
pub type HOST_MODE_EN_R = crate::BitReader<bool>;
#[doc = "Field `HOST_MODE_EN` writer - "]
pub type HOST_MODE_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSCTL_SPEC, bool, O>;
#[doc = "Field `RESET` reader - "]
pub type RESET_R = crate::BitReader<bool>;
#[doc = "Field `RESET` writer - "]
pub type RESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSCTL_SPEC, bool, O>;
#[doc = "Field `TxdSuspendTokenBusy` reader - "]
pub type TXD_SUSPEND_TOKEN_BUSY_R = crate::BitReader<bool>;
#[doc = "Field `TxdSuspendTokenBusy` writer - "]
pub type TXD_SUSPEND_TOKEN_BUSY_W<'a, const O: u8> =
crate::BitWriter<'a, u32, FSCTL_SPEC, bool, O>;
#[doc = "Field `SE0` reader - "]
pub type SE0_R = crate::BitReader<bool>;
#[doc = "Field `JSTATE` reader - "]
pub type JSTATE_R = crate::BitReader<bool>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn usb_en(&self) -> USB_EN_R {
USB_EN_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn odd_rst(&self) -> ODD_RST_R {
ODD_RST_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2"]
#[inline(always)]
pub fn resume(&self) -> RESUME_R {
RESUME_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3"]
#[inline(always)]
pub fn host_mode_en(&self) -> HOST_MODE_EN_R {
HOST_MODE_EN_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4"]
#[inline(always)]
pub fn reset(&self) -> RESET_R {
RESET_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5"]
#[inline(always)]
pub fn txd_suspend_token_busy(&self) -> TXD_SUSPEND_TOKEN_BUSY_R {
TXD_SUSPEND_TOKEN_BUSY_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn se0(&self) -> SE0_R {
SE0_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn jstate(&self) -> JSTATE_R {
JSTATE_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn usb_en(&mut self) -> USB_EN_W<0> {
USB_EN_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn odd_rst(&mut self) -> ODD_RST_W<1> {
ODD_RST_W::new(self)
}
#[doc = "Bit 2"]
#[inline(always)]
#[must_use]
pub fn resume(&mut self) -> RESUME_W<2> {
RESUME_W::new(self)
}
#[doc = "Bit 3"]
#[inline(always)]
#[must_use]
pub fn host_mode_en(&mut self) -> HOST_MODE_EN_W<3> {
HOST_MODE_EN_W::new(self)
}
#[doc = "Bit 4"]
#[inline(always)]
#[must_use]
pub fn reset(&mut self) -> RESET_W<4> {
RESET_W::new(self)
}
#[doc = "Bit 5"]
#[inline(always)]
#[must_use]
pub fn txd_suspend_token_busy(&mut self) -> TXD_SUSPEND_TOKEN_BUSY_W<5> {
TXD_SUSPEND_TOKEN_BUSY_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsctl](index.html) module"]
pub struct FSCTL_SPEC;
impl crate::RegisterSpec for FSCTL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fsctl::R](R) reader structure"]
impl crate::Readable for FSCTL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fsctl::W](W) writer structure"]
impl crate::Writable for FSCTL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSCTL to value 0x40"]
impl crate::Resettable for FSCTL_SPEC {
const RESET_VALUE: Self::Ux = 0x40;
}
}
#[doc = "FSADDR (rw) register accessor: an alias for `Reg<FSADDR_SPEC>`"]
pub type FSADDR = crate::Reg<fsaddr::FSADDR_SPEC>;
#[doc = "Address register"]
pub mod fsaddr {
#[doc = "Register `FSADDR` reader"]
pub struct R(crate::R<FSADDR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSADDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSADDR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSADDR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSADDR` writer"]
pub struct W(crate::W<FSADDR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSADDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSADDR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSADDR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `ADDR` reader - "]
pub type ADDR_R = crate::FieldReader<u8, u8>;
#[doc = "Field `ADDR` writer - "]
pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FSADDR_SPEC, u8, u8, 7, O>;
#[doc = "Field `LS_EN` reader - "]
pub type LS_EN_R = crate::BitReader<bool>;
#[doc = "Field `LS_EN` writer - "]
pub type LS_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSADDR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:6"]
#[inline(always)]
pub fn addr(&self) -> ADDR_R {
ADDR_R::new((self.bits & 0x7f) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn ls_en(&self) -> LS_EN_R {
LS_EN_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:6"]
#[inline(always)]
#[must_use]
pub fn addr(&mut self) -> ADDR_W<0> {
ADDR_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn ls_en(&mut self) -> LS_EN_W<7> {
LS_EN_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Address register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsaddr](index.html) module"]
pub struct FSADDR_SPEC;
impl crate::RegisterSpec for FSADDR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fsaddr::R](R) reader structure"]
impl crate::Readable for FSADDR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fsaddr::W](W) writer structure"]
impl crate::Writable for FSADDR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSADDR to value 0"]
impl crate::Resettable for FSADDR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "FSBDT_PAGE_01 (rw) register accessor: an alias for `Reg<FSBDT_PAGE_01_SPEC>`"]
pub type FSBDT_PAGE_01 = crate::Reg<fsbdt_page_01::FSBDT_PAGE_01_SPEC>;
#[doc = "BDT page register 1"]
pub mod fsbdt_page_01 {
#[doc = "Register `FSBDT_PAGE_01` reader"]
pub struct R(crate::R<FSBDT_PAGE_01_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSBDT_PAGE_01_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSBDT_PAGE_01_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSBDT_PAGE_01_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSBDT_PAGE_01` writer"]
pub struct W(crate::W<FSBDT_PAGE_01_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSBDT_PAGE_01_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSBDT_PAGE_01_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSBDT_PAGE_01_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `BDT_BA` reader - "]
pub type BDT_BA_R = crate::FieldReader<u8, u8>;
#[doc = "Field `BDT_BA` writer - "]
pub type BDT_BA_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, FSBDT_PAGE_01_SPEC, u8, u8, 7, O>;
impl R {
#[doc = "Bits 1:7"]
#[inline(always)]
pub fn bdt_ba(&self) -> BDT_BA_R {
BDT_BA_R::new(((self.bits >> 1) & 0x7f) as u8)
}
}
impl W {
#[doc = "Bits 1:7"]
#[inline(always)]
#[must_use]
pub fn bdt_ba(&mut self) -> BDT_BA_W<1> {
BDT_BA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "BDT page register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsbdt_page_01](index.html) module"]
pub struct FSBDT_PAGE_01_SPEC;
impl crate::RegisterSpec for FSBDT_PAGE_01_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fsbdt_page_01::R](R) reader structure"]
impl crate::Readable for FSBDT_PAGE_01_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fsbdt_page_01::W](W) writer structure"]
impl crate::Writable for FSBDT_PAGE_01_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSBDT_PAGE_01 to value 0"]
impl crate::Resettable for FSBDT_PAGE_01_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "FSFRM_NUML (rw) register accessor: an alias for `Reg<FSFRM_NUML_SPEC>`"]
pub type FSFRM_NUML = crate::Reg<fsfrm_numl::FSFRM_NUML_SPEC>;
#[doc = "Frame number register"]
pub mod fsfrm_numl {
#[doc = "Register `FSFRM_NUML` reader"]
pub struct R(crate::R<FSFRM_NUML_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSFRM_NUML_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSFRM_NUML_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSFRM_NUML_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSFRM_NUML` writer"]
pub struct W(crate::W<FSFRM_NUML_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSFRM_NUML_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSFRM_NUML_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSFRM_NUML_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `FRM` reader - "]
pub type FRM_R = crate::FieldReader<u8, u8>;
#[doc = "Field `FRM` writer - "]
pub type FRM_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, FSFRM_NUML_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn frm(&self) -> FRM_R {
FRM_R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn frm(&mut self) -> FRM_W<0> {
FRM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Frame number register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsfrm_numl](index.html) module"]
pub struct FSFRM_NUML_SPEC;
impl crate::RegisterSpec for FSFRM_NUML_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fsfrm_numl::R](R) reader structure"]
impl crate::Readable for FSFRM_NUML_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fsfrm_numl::W](W) writer structure"]
impl crate::Writable for FSFRM_NUML_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSFRM_NUML to value 0"]
impl crate::Resettable for FSFRM_NUML_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "FSFRM_NUMH (rw) register accessor: an alias for `Reg<FSFRM_NUMH_SPEC>`"]
pub type FSFRM_NUMH = crate::Reg<fsfrm_numh::FSFRM_NUMH_SPEC>;
#[doc = "Frame number register"]
pub mod fsfrm_numh {
#[doc = "Register `FSFRM_NUMH` reader"]
pub struct R(crate::R<FSFRM_NUMH_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSFRM_NUMH_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSFRM_NUMH_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSFRM_NUMH_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSFRM_NUMH` writer"]
pub struct W(crate::W<FSFRM_NUMH_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSFRM_NUMH_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSFRM_NUMH_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSFRM_NUMH_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `FRM` reader - "]
pub type FRM_R = crate::FieldReader<u8, u8>;
#[doc = "Field `FRM` writer - "]
pub type FRM_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, FSFRM_NUMH_SPEC, u8, u8, 3, O>;
impl R {
#[doc = "Bits 0:2"]
#[inline(always)]
pub fn frm(&self) -> FRM_R {
FRM_R::new((self.bits & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:2"]
#[inline(always)]
#[must_use]
pub fn frm(&mut self) -> FRM_W<0> {
FRM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Frame number register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsfrm_numh](index.html) module"]
pub struct FSFRM_NUMH_SPEC;
impl crate::RegisterSpec for FSFRM_NUMH_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fsfrm_numh::R](R) reader structure"]
impl crate::Readable for FSFRM_NUMH_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fsfrm_numh::W](W) writer structure"]
impl crate::Writable for FSFRM_NUMH_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSFRM_NUMH to value 0"]
impl crate::Resettable for FSFRM_NUMH_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "FSTOKEN (rw) register accessor: an alias for `Reg<FSTOKEN_SPEC>`"]
pub type FSTOKEN = crate::Reg<fstoken::FSTOKEN_SPEC>;
#[doc = "Token register"]
pub mod fstoken {
#[doc = "Register `FSTOKEN` reader"]
pub struct R(crate::R<FSTOKEN_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSTOKEN_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSTOKEN_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSTOKEN_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSTOKEN` writer"]
pub struct W(crate::W<FSTOKEN_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSTOKEN_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSTOKEN_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSTOKEN_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TOKEN_ENDPT` reader - "]
pub type TOKEN_ENDPT_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TOKEN_ENDPT` writer - "]
pub type TOKEN_ENDPT_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, FSTOKEN_SPEC, u8, u8, 4, O>;
#[doc = "Field `TOKEN_PID` reader - "]
pub type TOKEN_PID_R = crate::FieldReader<u8, u8>;
#[doc = "Field `TOKEN_PID` writer - "]
pub type TOKEN_PID_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, FSTOKEN_SPEC, u8, u8, 4, O>;
impl R {
#[doc = "Bits 0:3"]
#[inline(always)]
pub fn token_endpt(&self) -> TOKEN_ENDPT_R {
TOKEN_ENDPT_R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn token_pid(&self) -> TOKEN_PID_R {
TOKEN_PID_R::new(((self.bits >> 4) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3"]
#[inline(always)]
#[must_use]
pub fn token_endpt(&mut self) -> TOKEN_ENDPT_W<0> {
TOKEN_ENDPT_W::new(self)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn token_pid(&mut self) -> TOKEN_PID_W<4> {
TOKEN_PID_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Token register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fstoken](index.html) module"]
pub struct FSTOKEN_SPEC;
impl crate::RegisterSpec for FSTOKEN_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fstoken::R](R) reader structure"]
impl crate::Readable for FSTOKEN_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fstoken::W](W) writer structure"]
impl crate::Writable for FSTOKEN_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSTOKEN to value 0"]
impl crate::Resettable for FSTOKEN_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "FSSOF_THLD (rw) register accessor: an alias for `Reg<FSSOF_THLD_SPEC>`"]
pub type FSSOF_THLD = crate::Reg<fssof_thld::FSSOF_THLD_SPEC>;
#[doc = "SOF threshold register"]
pub mod fssof_thld {
#[doc = "Register `FSSOF_THLD` reader"]
pub struct R(crate::R<FSSOF_THLD_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSSOF_THLD_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSSOF_THLD_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSSOF_THLD_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSSOF_THLD` writer"]
pub struct W(crate::W<FSSOF_THLD_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSSOF_THLD_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSSOF_THLD_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSSOF_THLD_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CNT` reader - "]
pub type CNT_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CNT` writer - "]
pub type CNT_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, FSSOF_THLD_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn cnt(&self) -> CNT_R {
CNT_R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn cnt(&mut self) -> CNT_W<0> {
CNT_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "SOF threshold register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fssof_thld](index.html) module"]
pub struct FSSOF_THLD_SPEC;
impl crate::RegisterSpec for FSSOF_THLD_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fssof_thld::R](R) reader structure"]
impl crate::Readable for FSSOF_THLD_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fssof_thld::W](W) writer structure"]
impl crate::Writable for FSSOF_THLD_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSSOF_THLD to value 0"]
impl crate::Resettable for FSSOF_THLD_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "FSBDT_PAGE_02 (rw) register accessor: an alias for `Reg<FSBDT_PAGE_02_SPEC>`"]
pub type FSBDT_PAGE_02 = crate::Reg<fsbdt_page_02::FSBDT_PAGE_02_SPEC>;
#[doc = "BDT page register 2"]
pub mod fsbdt_page_02 {
#[doc = "Register `FSBDT_PAGE_02` reader"]
pub struct R(crate::R<FSBDT_PAGE_02_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSBDT_PAGE_02_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSBDT_PAGE_02_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSBDT_PAGE_02_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSBDT_PAGE_02` writer"]
pub struct W(crate::W<FSBDT_PAGE_02_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSBDT_PAGE_02_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSBDT_PAGE_02_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSBDT_PAGE_02_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `BDT_BA` reader - "]
pub type BDT_BA_R = crate::FieldReader<u8, u8>;
#[doc = "Field `BDT_BA` writer - "]
pub type BDT_BA_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, FSBDT_PAGE_02_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn bdt_ba(&self) -> BDT_BA_R {
BDT_BA_R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn bdt_ba(&mut self) -> BDT_BA_W<0> {
BDT_BA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "BDT page register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsbdt_page_02](index.html) module"]
pub struct FSBDT_PAGE_02_SPEC;
impl crate::RegisterSpec for FSBDT_PAGE_02_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fsbdt_page_02::R](R) reader structure"]
impl crate::Readable for FSBDT_PAGE_02_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fsbdt_page_02::W](W) writer structure"]
impl crate::Writable for FSBDT_PAGE_02_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSBDT_PAGE_02 to value 0"]
impl crate::Resettable for FSBDT_PAGE_02_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "FSBDT_PAGE_03 (rw) register accessor: an alias for `Reg<FSBDT_PAGE_03_SPEC>`"]
pub type FSBDT_PAGE_03 = crate::Reg<fsbdt_page_03::FSBDT_PAGE_03_SPEC>;
#[doc = "BDT page register 3"]
pub mod fsbdt_page_03 {
#[doc = "Register `FSBDT_PAGE_03` reader"]
pub struct R(crate::R<FSBDT_PAGE_03_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSBDT_PAGE_03_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSBDT_PAGE_03_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSBDT_PAGE_03_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSBDT_PAGE_03` writer"]
pub struct W(crate::W<FSBDT_PAGE_03_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSBDT_PAGE_03_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSBDT_PAGE_03_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSBDT_PAGE_03_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `BDT_BA` reader - "]
pub type BDT_BA_R = crate::FieldReader<u8, u8>;
#[doc = "Field `BDT_BA` writer - "]
pub type BDT_BA_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, FSBDT_PAGE_03_SPEC, u8, u8, 8, O>;
impl R {
#[doc = "Bits 0:7"]
#[inline(always)]
pub fn bdt_ba(&self) -> BDT_BA_R {
BDT_BA_R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7"]
#[inline(always)]
#[must_use]
pub fn bdt_ba(&mut self) -> BDT_BA_W<0> {
BDT_BA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "BDT page register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsbdt_page_03](index.html) module"]
pub struct FSBDT_PAGE_03_SPEC;
impl crate::RegisterSpec for FSBDT_PAGE_03_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fsbdt_page_03::R](R) reader structure"]
impl crate::Readable for FSBDT_PAGE_03_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fsbdt_page_03::W](W) writer structure"]
impl crate::Writable for FSBDT_PAGE_03_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSBDT_PAGE_03 to value 0"]
impl crate::Resettable for FSBDT_PAGE_03_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
#[doc = "FSEP0_CTL (rw) register accessor: an alias for `Reg<FSEP0_CTL_SPEC>`"]
pub type FSEP0_CTL = crate::Reg<fsep0_ctl::FSEP0_CTL_SPEC>;
#[doc = "Endpoint control register 0"]
pub mod fsep0_ctl {
#[doc = "Register `FSEP0_CTL` reader"]
pub struct R(crate::R<FSEP0_CTL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSEP0_CTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSEP0_CTL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSEP0_CTL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSEP0_CTL` writer"]
pub struct W(crate::W<FSEP0_CTL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSEP0_CTL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSEP0_CTL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSEP0_CTL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EP_HSHK` reader - "]
pub type EP_HSHK_R = crate::BitReader<bool>;
#[doc = "Field `EP_HSHK` writer - "]
pub type EP_HSHK_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSEP0_CTL_SPEC, bool, O>;
#[doc = "Field `EP_STALL` reader - "]
pub type EP_STALL_R = crate::BitReader<bool>;
#[doc = "Field `EP_STALL` writer - "]
pub type EP_STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSEP0_CTL_SPEC, bool, O>;
#[doc = "Field `EP_CTL_DISEP_RX_ENEP_TX_EN` reader - "]
pub type EP_CTL_DISEP_RX_ENEP_TX_EN_R = crate::FieldReader<u8, u8>;
#[doc = "Field `EP_CTL_DISEP_RX_ENEP_TX_EN` writer - "]
pub type EP_CTL_DISEP_RX_ENEP_TX_EN_W<'a, const O: u8> =
crate::FieldWriter<'a, u32, FSEP0_CTL_SPEC, u8, u8, 3, O>;
#[doc = "Field `RETRY_DIS` reader - "]
pub type RETRY_DIS_R = crate::BitReader<bool>;
#[doc = "Field `RETRY_DIS` writer - "]
pub type RETRY_DIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSEP0_CTL_SPEC, bool, O>;
#[doc = "Field `HOST_WO_HUB` reader - "]
pub type HOST_WO_HUB_R = crate::BitReader<bool>;
#[doc = "Field `HOST_WO_HUB` writer - "]
pub type HOST_WO_HUB_W<'a, const O: u8> =
crate::BitWriter<'a, u32, FSEP0_CTL_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn ep_hshk(&self) -> EP_HSHK_R {
EP_HSHK_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1"]
#[inline(always)]
pub fn ep_stall(&self) -> EP_STALL_R {
EP_STALL_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:4"]
#[inline(always)]
pub fn ep_ctl_disep_rx_enep_tx_en(&self) -> EP_CTL_DISEP_RX_ENEP_TX_EN_R {
EP_CTL_DISEP_RX_ENEP_TX_EN_R::new(((self.bits >> 2) & 7) as u8)
}
#[doc = "Bit 6"]
#[inline(always)]
pub fn retry_dis(&self) -> RETRY_DIS_R {
RETRY_DIS_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn host_wo_hub(&self) -> HOST_WO_HUB_R {
HOST_WO_HUB_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn ep_hshk(&mut self) -> EP_HSHK_W<0> {
EP_HSHK_W::new(self)
}
#[doc = "Bit 1"]
#[inline(always)]
#[must_use]
pub fn ep_stall(&mut self) -> EP_STALL_W<1> {
EP_STALL_W::new(self)
}
#[doc = "Bits 2:4"]
#[inline(always)]
#[must_use]
pub fn ep_ctl_disep_rx_enep_tx_en(&mut self) -> EP_CTL_DISEP_RX_ENEP_TX_EN_W<2> {
EP_CTL_DISEP_RX_ENEP_TX_EN_W::new(self)
}
#[doc = "Bit 6"]
#[inline(always)]
#[must_use]
pub fn retry_dis(&mut self) -> RETRY_DIS_W<6> {
RETRY_DIS_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn host_wo_hub(&mut self) -> HOST_WO_HUB_W<7> {
HOST_WO_HUB_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Endpoint control register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsep0_ctl](index.html) module"]
pub struct FSEP0_CTL_SPEC;
impl crate::RegisterSpec for FSEP0_CTL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fsep0_ctl::R](R) reader structure"]
impl crate::Readable for FSEP0_CTL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fsep0_ctl::W](W) writer structure"]
impl crate::Writable for FSEP0_CTL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSEP0_CTL to value 0"]
impl crate::Resettable for FSEP0_CTL_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
pub use fsep0_ctl as fsep1_ctl;
pub use fsep0_ctl as fsep2_ctl;
pub use fsep0_ctl as fsep3_ctl;
pub use fsep0_ctl as fsep4_ctl;
pub use fsep0_ctl as fsep5_ctl;
pub use fsep0_ctl as fsep6_ctl;
pub use fsep0_ctl as fsep7_ctl;
pub use fsep0_ctl as fsep8_ctl;
pub use fsep0_ctl as fsep9_ctl;
pub use fsep0_ctl as fsep10_ctl;
pub use fsep0_ctl as fsep11_ctl;
pub use fsep0_ctl as fsep12_ctl;
pub use fsep0_ctl as fsep13_ctl;
pub use fsep0_ctl as fsep14_ctl;
pub use fsep0_ctl as fsep15_ctl;
pub use FSEP0_CTL as FSEP1_CTL;
pub use FSEP0_CTL as FSEP2_CTL;
pub use FSEP0_CTL as FSEP3_CTL;
pub use FSEP0_CTL as FSEP4_CTL;
pub use FSEP0_CTL as FSEP5_CTL;
pub use FSEP0_CTL as FSEP6_CTL;
pub use FSEP0_CTL as FSEP7_CTL;
pub use FSEP0_CTL as FSEP8_CTL;
pub use FSEP0_CTL as FSEP9_CTL;
pub use FSEP0_CTL as FSEP10_CTL;
pub use FSEP0_CTL as FSEP11_CTL;
pub use FSEP0_CTL as FSEP12_CTL;
pub use FSEP0_CTL as FSEP13_CTL;
pub use FSEP0_CTL as FSEP14_CTL;
pub use FSEP0_CTL as FSEP15_CTL;
#[doc = "FSUSBCTRL (rw) register accessor: an alias for `Reg<FSUSBCTRL_SPEC>`"]
pub type FSUSBCTRL = crate::Reg<fsusbctrl::FSUSBCTRL_SPEC>;
#[doc = "USB Control register"]
pub mod fsusbctrl {
#[doc = "Register `FSUSBCTRL` reader"]
pub struct R(crate::R<FSUSBCTRL_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<FSUSBCTRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<FSUSBCTRL_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<FSUSBCTRL_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `FSUSBCTRL` writer"]
pub struct W(crate::W<FSUSBCTRL_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<FSUSBCTRL_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<FSUSBCTRL_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<FSUSBCTRL_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SUSPE` reader - "]
pub type SUSPE_R = crate::BitReader<bool>;
#[doc = "Field `SUSPE` writer - "]
pub type SUSPE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FSUSBCTRL_SPEC, bool, O>;
impl R {
#[doc = "Bit 7"]
#[inline(always)]
pub fn suspe(&self) -> SUSPE_R {
SUSPE_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn suspe(&mut self) -> SUSPE_W<7> {
SUSPE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "USB Control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsusbctrl](index.html) module"]
pub struct FSUSBCTRL_SPEC;
impl crate::RegisterSpec for FSUSBCTRL_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [fsusbctrl::R](R) reader structure"]
impl crate::Readable for FSUSBCTRL_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [fsusbctrl::W](W) writer structure"]
impl crate::Writable for FSUSBCTRL_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets FSUSBCTRL to value 0"]
impl crate::Resettable for FSUSBCTRL_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[doc = "WWDG"]
pub struct WWDG {
_marker: PhantomData<*const ()>,
}
unsafe impl Send for WWDG {}
impl WWDG {
#[doc = r"Pointer to the register block"]
pub const PTR: *const wwdg::RegisterBlock = 0x4000_2c00 as *const _;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const wwdg::RegisterBlock {
Self::PTR
}
}
impl Deref for WWDG {
type Target = wwdg::RegisterBlock;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
impl core::fmt::Debug for WWDG {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("WWDG").finish()
}
}
#[doc = "WWDG"]
pub mod wwdg {
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - control register"]
pub cr: CR,
#[doc = "0x04 - configuration register"]
pub cfgr: CFGR,
#[doc = "0x08 - status register"]
pub sr: SR,
}
#[doc = "CR (rw) register accessor: an alias for `Reg<CR_SPEC>`"]
pub type CR = crate::Reg<cr::CR_SPEC>;
#[doc = "control register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub struct R(crate::R<CR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR` writer"]
pub struct W(crate::W<CR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `T` reader - "]
pub type T_R = crate::FieldReader<u8, u8>;
#[doc = "Field `T` writer - "]
pub type T_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, u8, 7, O>;
#[doc = "Field `WDGA` reader - "]
pub type WDGA_R = crate::BitReader<bool>;
#[doc = "Field `WDGA` writer - "]
pub type WDGA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:6"]
#[inline(always)]
pub fn t(&self) -> T_R {
T_R::new((self.bits & 0x7f) as u8)
}
#[doc = "Bit 7"]
#[inline(always)]
pub fn wdga(&self) -> WDGA_R {
WDGA_R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:6"]
#[inline(always)]
#[must_use]
pub fn t(&mut self) -> T_W<0> {
T_W::new(self)
}
#[doc = "Bit 7"]
#[inline(always)]
#[must_use]
pub fn wdga(&mut self) -> WDGA_W<7> {
WDGA_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"]
pub struct CR_SPEC;
impl crate::RegisterSpec for CR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr::R](R) reader structure"]
impl crate::Readable for CR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"]
impl crate::Writable for CR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CR to value 0x7f"]
impl crate::Resettable for CR_SPEC {
const RESET_VALUE: Self::Ux = 0x7f;
}
}
#[doc = "CFGR (rw) register accessor: an alias for `Reg<CFGR_SPEC>`"]
pub type CFGR = crate::Reg<cfgr::CFGR_SPEC>;
#[doc = "configuration register"]
pub mod cfgr {
#[doc = "Register `CFGR` reader"]
pub struct R(crate::R<CFGR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CFGR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CFGR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CFGR` writer"]
pub struct W(crate::W<CFGR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CFGR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CFGR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CFGR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `W` reader - "]
pub type W_R = crate::FieldReader<u8, u8>;
#[doc = "Field `W` writer - "]
pub type W_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR_SPEC, u8, u8, 7, O>;
#[doc = "Field `WDGTB` reader - "]
pub type WDGTB_R = crate::FieldReader<u8, u8>;
#[doc = "Field `WDGTB` writer - "]
pub type WDGTB_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR_SPEC, u8, u8, 2, O>;
#[doc = "Field `EWI` reader - "]
pub type EWI_R = crate::BitReader<bool>;
#[doc = "Field `EWI` writer - "]
pub type EWI_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR_SPEC, bool, O>;
impl R {
#[doc = "Bits 0:6"]
#[inline(always)]
pub fn w(&self) -> W_R {
W_R::new((self.bits & 0x7f) as u8)
}
#[doc = "Bits 7:8"]
#[inline(always)]
pub fn wdgtb(&self) -> WDGTB_R {
WDGTB_R::new(((self.bits >> 7) & 3) as u8)
}
#[doc = "Bit 9"]
#[inline(always)]
pub fn ewi(&self) -> EWI_R {
EWI_R::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:6"]
#[inline(always)]
#[must_use]
pub fn w(&mut self) -> W_W<0> {
W_W::new(self)
}
#[doc = "Bits 7:8"]
#[inline(always)]
#[must_use]
pub fn wdgtb(&mut self) -> WDGTB_W<7> {
WDGTB_W::new(self)
}
#[doc = "Bit 9"]
#[inline(always)]
#[must_use]
pub fn ewi(&mut self) -> EWI_W<9> {
EWI_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr](index.html) module"]
pub struct CFGR_SPEC;
impl crate::RegisterSpec for CFGR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cfgr::R](R) reader structure"]
impl crate::Readable for CFGR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cfgr::W](W) writer structure"]
impl crate::Writable for CFGR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets CFGR to value 0x7f"]
impl crate::Resettable for CFGR_SPEC {
const RESET_VALUE: Self::Ux = 0x7f;
}
}
#[doc = "SR (rw) register accessor: an alias for `Reg<SR_SPEC>`"]
pub type SR = crate::Reg<sr::SR_SPEC>;
#[doc = "status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub struct R(crate::R<SR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<SR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<SR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `SR` writer"]
pub struct W(crate::W<SR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<SR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<SR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<SR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `EWIF` reader - "]
pub type EWIF_R = crate::BitReader<bool>;
#[doc = "Field `EWIF` writer - "]
pub type EWIF_W<'a, const O: u8> = crate::BitWriter0C<'a, u32, SR_SPEC, bool, O>;
impl R {
#[doc = "Bit 0"]
#[inline(always)]
pub fn ewif(&self) -> EWIF_R {
EWIF_R::new((self.bits & 1) != 0)
}
}
impl W {
#[doc = "Bit 0"]
#[inline(always)]
#[must_use]
pub fn ewif(&mut self) -> EWIF_W<0> {
EWIF_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"]
pub struct SR_SPEC;
impl crate::RegisterSpec for SR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [sr::R](R) reader structure"]
impl crate::Readable for SR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [sr::W](W) writer structure"]
impl crate::Writable for SR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x01;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}
}
}
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
#[doc = r" All the peripherals."]
#[allow(non_snake_case)]
pub struct Peripherals {
#[doc = "ADC1"]
pub ADC1: ADC1,
#[doc = "ADC2"]
pub ADC2: ADC2,
#[doc = "BKP"]
pub BKP: BKP,
#[doc = "COMP"]
pub COMP: COMP,
#[doc = "CORDIC"]
pub CORDIC: CORDIC,
#[doc = "CRC"]
pub CRC: CRC,
#[doc = "CRS"]
pub CRS: CRS,
#[doc = "DAC"]
pub DAC: DAC,
#[doc = "DBGMCU"]
pub DBGMCU: DBGMCU,
#[doc = "DMA1"]
pub DMA1: DMA1,
#[doc = "DMA2"]
pub DMA2: DMA2,
#[doc = "ENET"]
pub ENET: ENET,
#[doc = "EXTI"]
pub EXTI: EXTI,
#[doc = "FLASH"]
pub FLASH: FLASH,
#[doc = "FLEXCAN1"]
pub FLEXCAN1: FLEXCAN1,
#[doc = "FLEXCAN2"]
pub FLEXCAN2: FLEXCAN2,
#[doc = "FSMC"]
pub FSMC: FSMC,
#[doc = "GPIOA"]
pub GPIOA: GPIOA,
#[doc = "GPIOB"]
pub GPIOB: GPIOB,
#[doc = "GPIOC"]
pub GPIOC: GPIOC,
#[doc = "GPIOD"]
pub GPIOD: GPIOD,
#[doc = "GPIOE"]
pub GPIOE: GPIOE,
#[doc = "GPIOF"]
pub GPIOF: GPIOF,
#[doc = "GPIOG"]
pub GPIOG: GPIOG,
#[doc = "GPIOH"]
pub GPIOH: GPIOH,
#[doc = "GPIOI"]
pub GPIOI: GPIOI,
#[doc = "I2C1"]
pub I2C1: I2C1,
#[doc = "I2C2"]
pub I2C2: I2C2,
#[doc = "IWDG"]
pub IWDG: IWDG,
#[doc = "LPT"]
pub LPT: LPT,
#[doc = "LPU"]
pub LPU: LPU,
#[doc = "MDS"]
pub MDS: MDS,
#[doc = "PWR"]
pub PWR: PWR,
#[doc = "QSPI"]
pub QSPI: QSPI,
#[doc = "RCC"]
pub RCC: RCC,
#[doc = "RTC"]
pub RTC: RTC,
#[doc = "SPI1"]
pub SPI1: SPI1,
#[doc = "SPI2"]
pub SPI2: SPI2,
#[doc = "SPI3"]
pub SPI3: SPI3,
#[doc = "SYSCFG"]
pub SYSCFG: SYSCFG,
#[doc = "TIM1"]
pub TIM1: TIM1,
#[doc = "TIM8"]
pub TIM8: TIM8,
#[doc = "TIM2"]
pub TIM2: TIM2,
#[doc = "TIM5"]
pub TIM5: TIM5,
#[doc = "TIM3"]
pub TIM3: TIM3,
#[doc = "TIM4"]
pub TIM4: TIM4,
#[doc = "TIM6"]
pub TIM6: TIM6,
#[doc = "TIM7"]
pub TIM7: TIM7,
#[doc = "UART1"]
pub UART1: UART1,
#[doc = "UART2"]
pub UART2: UART2,
#[doc = "UART3"]
pub UART3: UART3,
#[doc = "UART4"]
pub UART4: UART4,
#[doc = "UART5"]
pub UART5: UART5,
#[doc = "UART6"]
pub UART6: UART6,
#[doc = "UART7"]
pub UART7: UART7,
#[doc = "USB"]
pub USB: USB,
#[doc = "WWDG"]
pub WWDG: WWDG,
}
impl Peripherals {
#[doc = r" Returns all the peripherals *once*."]
#[cfg(feature = "critical-section")]
#[inline]
pub fn take() -> Option<Self> {
critical_section::with(|_| {
if unsafe { DEVICE_PERIPHERALS } {
return None;
}
Some(unsafe { Peripherals::steal() })
})
}
#[doc = r" Unchecked version of `Peripherals::take`."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Each of the returned peripherals must be used at most once."]
#[inline]
pub unsafe fn steal() -> Self {
DEVICE_PERIPHERALS = true;
Peripherals {
ADC1: ADC1 {
_marker: PhantomData,
},
ADC2: ADC2 {
_marker: PhantomData,
},
BKP: BKP {
_marker: PhantomData,
},
COMP: COMP {
_marker: PhantomData,
},
CORDIC: CORDIC {
_marker: PhantomData,
},
CRC: CRC {
_marker: PhantomData,
},
CRS: CRS {
_marker: PhantomData,
},
DAC: DAC {
_marker: PhantomData,
},
DBGMCU: DBGMCU {
_marker: PhantomData,
},
DMA1: DMA1 {
_marker: PhantomData,
},
DMA2: DMA2 {
_marker: PhantomData,
},
ENET: ENET {
_marker: PhantomData,
},
EXTI: EXTI {
_marker: PhantomData,
},
FLASH: FLASH {
_marker: PhantomData,
},
FLEXCAN1: FLEXCAN1 {
_marker: PhantomData,
},
FLEXCAN2: FLEXCAN2 {
_marker: PhantomData,
},
FSMC: FSMC {
_marker: PhantomData,
},
GPIOA: GPIOA {
_marker: PhantomData,
},
GPIOB: GPIOB {
_marker: PhantomData,
},
GPIOC: GPIOC {
_marker: PhantomData,
},
GPIOD: GPIOD {
_marker: PhantomData,
},
GPIOE: GPIOE {
_marker: PhantomData,
},
GPIOF: GPIOF {
_marker: PhantomData,
},
GPIOG: GPIOG {
_marker: PhantomData,
},
GPIOH: GPIOH {
_marker: PhantomData,
},
GPIOI: GPIOI {
_marker: PhantomData,
},
I2C1: I2C1 {
_marker: PhantomData,
},
I2C2: I2C2 {
_marker: PhantomData,
},
IWDG: IWDG {
_marker: PhantomData,
},
LPT: LPT {
_marker: PhantomData,
},
LPU: LPU {
_marker: PhantomData,
},
MDS: MDS {
_marker: PhantomData,
},
PWR: PWR {
_marker: PhantomData,
},
QSPI: QSPI {
_marker: PhantomData,
},
RCC: RCC {
_marker: PhantomData,
},
RTC: RTC {
_marker: PhantomData,
},
SPI1: SPI1 {
_marker: PhantomData,
},
SPI2: SPI2 {
_marker: PhantomData,
},
SPI3: SPI3 {
_marker: PhantomData,
},
SYSCFG: SYSCFG {
_marker: PhantomData,
},
TIM1: TIM1 {
_marker: PhantomData,
},
TIM8: TIM8 {
_marker: PhantomData,
},
TIM2: TIM2 {
_marker: PhantomData,
},
TIM5: TIM5 {
_marker: PhantomData,
},
TIM3: TIM3 {
_marker: PhantomData,
},
TIM4: TIM4 {
_marker: PhantomData,
},
TIM6: TIM6 {
_marker: PhantomData,
},
TIM7: TIM7 {
_marker: PhantomData,
},
UART1: UART1 {
_marker: PhantomData,
},
UART2: UART2 {
_marker: PhantomData,
},
UART3: UART3 {
_marker: PhantomData,
},
UART4: UART4 {
_marker: PhantomData,
},
UART5: UART5 {
_marker: PhantomData,
},
UART6: UART6 {
_marker: PhantomData,
},
UART7: UART7 {
_marker: PhantomData,
},
USB: USB {
_marker: PhantomData,
},
WWDG: WWDG {
_marker: PhantomData,
},
}
}
}