1#[doc = "Reader of register C1"]
2pub type R = crate::R<u8, super::C1>;
3#[doc = "Writer for register C1"]
4pub type W = crate::W<u8, super::C1>;
5#[doc = "Register C1 `reset()`'s with value 0"]
6impl crate::ResetValue for super::C1 {
7 type Type = u8;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "DMA Enable\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15pub enum DMAEN_A {
16 #[doc = "0: All DMA signalling disabled."]
17 _0 = 0,
18 #[doc = "1: DMA transfer is enabled and the following conditions trigger the DMA request: While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted."]
19 _1 = 1,
20}
21impl From<DMAEN_A> for bool {
22 #[inline(always)]
23 fn from(variant: DMAEN_A) -> Self {
24 variant as u8 != 0
25 }
26}
27#[doc = "Reader of field `DMAEN`"]
28pub type DMAEN_R = crate::R<bool, DMAEN_A>;
29impl DMAEN_R {
30 #[doc = r"Get enumerated values variant"]
31 #[inline(always)]
32 pub fn variant(&self) -> DMAEN_A {
33 match self.bits {
34 false => DMAEN_A::_0,
35 true => DMAEN_A::_1,
36 }
37 }
38 #[doc = "Checks if the value of the field is `_0`"]
39 #[inline(always)]
40 pub fn is_0(&self) -> bool {
41 *self == DMAEN_A::_0
42 }
43 #[doc = "Checks if the value of the field is `_1`"]
44 #[inline(always)]
45 pub fn is_1(&self) -> bool {
46 *self == DMAEN_A::_1
47 }
48}
49#[doc = "Write proxy for field `DMAEN`"]
50pub struct DMAEN_W<'a> {
51 w: &'a mut W,
52}
53impl<'a> DMAEN_W<'a> {
54 #[doc = r"Writes `variant` to the field"]
55 #[inline(always)]
56 pub fn variant(self, variant: DMAEN_A) -> &'a mut W {
57 {
58 self.bit(variant.into())
59 }
60 }
61 #[doc = "All DMA signalling disabled."]
62 #[inline(always)]
63 pub fn _0(self) -> &'a mut W {
64 self.variant(DMAEN_A::_0)
65 }
66 #[doc = "DMA transfer is enabled and the following conditions trigger the DMA request: While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted."]
67 #[inline(always)]
68 pub fn _1(self) -> &'a mut W {
69 self.variant(DMAEN_A::_1)
70 }
71 #[doc = r"Sets the field bit"]
72 #[inline(always)]
73 pub fn set_bit(self) -> &'a mut W {
74 self.bit(true)
75 }
76 #[doc = r"Clears the field bit"]
77 #[inline(always)]
78 pub fn clear_bit(self) -> &'a mut W {
79 self.bit(false)
80 }
81 #[doc = r"Writes raw bits to the field"]
82 #[inline(always)]
83 pub fn bit(self, value: bool) -> &'a mut W {
84 self.w.bits = (self.w.bits & !0x01) | ((value as u8) & 0x01);
85 self.w
86 }
87}
88#[doc = "Wakeup Enable\n\nValue on reset: 0"]
89#[derive(Clone, Copy, Debug, PartialEq)]
90pub enum WUEN_A {
91 #[doc = "0: Normal operation. No interrupt generated when address matching in low power mode."]
92 _0 = 0,
93 #[doc = "1: Enables the wakeup function in low power mode."]
94 _1 = 1,
95}
96impl From<WUEN_A> for bool {
97 #[inline(always)]
98 fn from(variant: WUEN_A) -> Self {
99 variant as u8 != 0
100 }
101}
102#[doc = "Reader of field `WUEN`"]
103pub type WUEN_R = crate::R<bool, WUEN_A>;
104impl WUEN_R {
105 #[doc = r"Get enumerated values variant"]
106 #[inline(always)]
107 pub fn variant(&self) -> WUEN_A {
108 match self.bits {
109 false => WUEN_A::_0,
110 true => WUEN_A::_1,
111 }
112 }
113 #[doc = "Checks if the value of the field is `_0`"]
114 #[inline(always)]
115 pub fn is_0(&self) -> bool {
116 *self == WUEN_A::_0
117 }
118 #[doc = "Checks if the value of the field is `_1`"]
119 #[inline(always)]
120 pub fn is_1(&self) -> bool {
121 *self == WUEN_A::_1
122 }
123}
124#[doc = "Write proxy for field `WUEN`"]
125pub struct WUEN_W<'a> {
126 w: &'a mut W,
127}
128impl<'a> WUEN_W<'a> {
129 #[doc = r"Writes `variant` to the field"]
130 #[inline(always)]
131 pub fn variant(self, variant: WUEN_A) -> &'a mut W {
132 {
133 self.bit(variant.into())
134 }
135 }
136 #[doc = "Normal operation. No interrupt generated when address matching in low power mode."]
137 #[inline(always)]
138 pub fn _0(self) -> &'a mut W {
139 self.variant(WUEN_A::_0)
140 }
141 #[doc = "Enables the wakeup function in low power mode."]
142 #[inline(always)]
143 pub fn _1(self) -> &'a mut W {
144 self.variant(WUEN_A::_1)
145 }
146 #[doc = r"Sets the field bit"]
147 #[inline(always)]
148 pub fn set_bit(self) -> &'a mut W {
149 self.bit(true)
150 }
151 #[doc = r"Clears the field bit"]
152 #[inline(always)]
153 pub fn clear_bit(self) -> &'a mut W {
154 self.bit(false)
155 }
156 #[doc = r"Writes raw bits to the field"]
157 #[inline(always)]
158 pub fn bit(self, value: bool) -> &'a mut W {
159 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u8) & 0x01) << 1);
160 self.w
161 }
162}
163#[doc = "Write proxy for field `RSTA`"]
164pub struct RSTA_W<'a> {
165 w: &'a mut W,
166}
167impl<'a> RSTA_W<'a> {
168 #[doc = r"Sets the field bit"]
169 #[inline(always)]
170 pub fn set_bit(self) -> &'a mut W {
171 self.bit(true)
172 }
173 #[doc = r"Clears the field bit"]
174 #[inline(always)]
175 pub fn clear_bit(self) -> &'a mut W {
176 self.bit(false)
177 }
178 #[doc = r"Writes raw bits to the field"]
179 #[inline(always)]
180 pub fn bit(self, value: bool) -> &'a mut W {
181 self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u8) & 0x01) << 2);
182 self.w
183 }
184}
185#[doc = "Transmit Acknowledge Enable\n\nValue on reset: 0"]
186#[derive(Clone, Copy, Debug, PartialEq)]
187pub enum TXAK_A {
188 #[doc = "0: An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set)."]
189 _0 = 0,
190 #[doc = "1: No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set)."]
191 _1 = 1,
192}
193impl From<TXAK_A> for bool {
194 #[inline(always)]
195 fn from(variant: TXAK_A) -> Self {
196 variant as u8 != 0
197 }
198}
199#[doc = "Reader of field `TXAK`"]
200pub type TXAK_R = crate::R<bool, TXAK_A>;
201impl TXAK_R {
202 #[doc = r"Get enumerated values variant"]
203 #[inline(always)]
204 pub fn variant(&self) -> TXAK_A {
205 match self.bits {
206 false => TXAK_A::_0,
207 true => TXAK_A::_1,
208 }
209 }
210 #[doc = "Checks if the value of the field is `_0`"]
211 #[inline(always)]
212 pub fn is_0(&self) -> bool {
213 *self == TXAK_A::_0
214 }
215 #[doc = "Checks if the value of the field is `_1`"]
216 #[inline(always)]
217 pub fn is_1(&self) -> bool {
218 *self == TXAK_A::_1
219 }
220}
221#[doc = "Write proxy for field `TXAK`"]
222pub struct TXAK_W<'a> {
223 w: &'a mut W,
224}
225impl<'a> TXAK_W<'a> {
226 #[doc = r"Writes `variant` to the field"]
227 #[inline(always)]
228 pub fn variant(self, variant: TXAK_A) -> &'a mut W {
229 {
230 self.bit(variant.into())
231 }
232 }
233 #[doc = "An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set)."]
234 #[inline(always)]
235 pub fn _0(self) -> &'a mut W {
236 self.variant(TXAK_A::_0)
237 }
238 #[doc = "No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set)."]
239 #[inline(always)]
240 pub fn _1(self) -> &'a mut W {
241 self.variant(TXAK_A::_1)
242 }
243 #[doc = r"Sets the field bit"]
244 #[inline(always)]
245 pub fn set_bit(self) -> &'a mut W {
246 self.bit(true)
247 }
248 #[doc = r"Clears the field bit"]
249 #[inline(always)]
250 pub fn clear_bit(self) -> &'a mut W {
251 self.bit(false)
252 }
253 #[doc = r"Writes raw bits to the field"]
254 #[inline(always)]
255 pub fn bit(self, value: bool) -> &'a mut W {
256 self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u8) & 0x01) << 3);
257 self.w
258 }
259}
260#[doc = "Transmit Mode Select\n\nValue on reset: 0"]
261#[derive(Clone, Copy, Debug, PartialEq)]
262pub enum TX_A {
263 #[doc = "0: Receive"]
264 _0 = 0,
265 #[doc = "1: Transmit"]
266 _1 = 1,
267}
268impl From<TX_A> for bool {
269 #[inline(always)]
270 fn from(variant: TX_A) -> Self {
271 variant as u8 != 0
272 }
273}
274#[doc = "Reader of field `TX`"]
275pub type TX_R = crate::R<bool, TX_A>;
276impl TX_R {
277 #[doc = r"Get enumerated values variant"]
278 #[inline(always)]
279 pub fn variant(&self) -> TX_A {
280 match self.bits {
281 false => TX_A::_0,
282 true => TX_A::_1,
283 }
284 }
285 #[doc = "Checks if the value of the field is `_0`"]
286 #[inline(always)]
287 pub fn is_0(&self) -> bool {
288 *self == TX_A::_0
289 }
290 #[doc = "Checks if the value of the field is `_1`"]
291 #[inline(always)]
292 pub fn is_1(&self) -> bool {
293 *self == TX_A::_1
294 }
295}
296#[doc = "Write proxy for field `TX`"]
297pub struct TX_W<'a> {
298 w: &'a mut W,
299}
300impl<'a> TX_W<'a> {
301 #[doc = r"Writes `variant` to the field"]
302 #[inline(always)]
303 pub fn variant(self, variant: TX_A) -> &'a mut W {
304 {
305 self.bit(variant.into())
306 }
307 }
308 #[doc = "Receive"]
309 #[inline(always)]
310 pub fn _0(self) -> &'a mut W {
311 self.variant(TX_A::_0)
312 }
313 #[doc = "Transmit"]
314 #[inline(always)]
315 pub fn _1(self) -> &'a mut W {
316 self.variant(TX_A::_1)
317 }
318 #[doc = r"Sets the field bit"]
319 #[inline(always)]
320 pub fn set_bit(self) -> &'a mut W {
321 self.bit(true)
322 }
323 #[doc = r"Clears the field bit"]
324 #[inline(always)]
325 pub fn clear_bit(self) -> &'a mut W {
326 self.bit(false)
327 }
328 #[doc = r"Writes raw bits to the field"]
329 #[inline(always)]
330 pub fn bit(self, value: bool) -> &'a mut W {
331 self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u8) & 0x01) << 4);
332 self.w
333 }
334}
335#[doc = "Master Mode Select\n\nValue on reset: 0"]
336#[derive(Clone, Copy, Debug, PartialEq)]
337pub enum MST_A {
338 #[doc = "0: Slave mode"]
339 _0 = 0,
340 #[doc = "1: Master mode"]
341 _1 = 1,
342}
343impl From<MST_A> for bool {
344 #[inline(always)]
345 fn from(variant: MST_A) -> Self {
346 variant as u8 != 0
347 }
348}
349#[doc = "Reader of field `MST`"]
350pub type MST_R = crate::R<bool, MST_A>;
351impl MST_R {
352 #[doc = r"Get enumerated values variant"]
353 #[inline(always)]
354 pub fn variant(&self) -> MST_A {
355 match self.bits {
356 false => MST_A::_0,
357 true => MST_A::_1,
358 }
359 }
360 #[doc = "Checks if the value of the field is `_0`"]
361 #[inline(always)]
362 pub fn is_0(&self) -> bool {
363 *self == MST_A::_0
364 }
365 #[doc = "Checks if the value of the field is `_1`"]
366 #[inline(always)]
367 pub fn is_1(&self) -> bool {
368 *self == MST_A::_1
369 }
370}
371#[doc = "Write proxy for field `MST`"]
372pub struct MST_W<'a> {
373 w: &'a mut W,
374}
375impl<'a> MST_W<'a> {
376 #[doc = r"Writes `variant` to the field"]
377 #[inline(always)]
378 pub fn variant(self, variant: MST_A) -> &'a mut W {
379 {
380 self.bit(variant.into())
381 }
382 }
383 #[doc = "Slave mode"]
384 #[inline(always)]
385 pub fn _0(self) -> &'a mut W {
386 self.variant(MST_A::_0)
387 }
388 #[doc = "Master mode"]
389 #[inline(always)]
390 pub fn _1(self) -> &'a mut W {
391 self.variant(MST_A::_1)
392 }
393 #[doc = r"Sets the field bit"]
394 #[inline(always)]
395 pub fn set_bit(self) -> &'a mut W {
396 self.bit(true)
397 }
398 #[doc = r"Clears the field bit"]
399 #[inline(always)]
400 pub fn clear_bit(self) -> &'a mut W {
401 self.bit(false)
402 }
403 #[doc = r"Writes raw bits to the field"]
404 #[inline(always)]
405 pub fn bit(self, value: bool) -> &'a mut W {
406 self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u8) & 0x01) << 5);
407 self.w
408 }
409}
410#[doc = "I2C Interrupt Enable\n\nValue on reset: 0"]
411#[derive(Clone, Copy, Debug, PartialEq)]
412pub enum IICIE_A {
413 #[doc = "0: Disabled"]
414 _0 = 0,
415 #[doc = "1: Enabled"]
416 _1 = 1,
417}
418impl From<IICIE_A> for bool {
419 #[inline(always)]
420 fn from(variant: IICIE_A) -> Self {
421 variant as u8 != 0
422 }
423}
424#[doc = "Reader of field `IICIE`"]
425pub type IICIE_R = crate::R<bool, IICIE_A>;
426impl IICIE_R {
427 #[doc = r"Get enumerated values variant"]
428 #[inline(always)]
429 pub fn variant(&self) -> IICIE_A {
430 match self.bits {
431 false => IICIE_A::_0,
432 true => IICIE_A::_1,
433 }
434 }
435 #[doc = "Checks if the value of the field is `_0`"]
436 #[inline(always)]
437 pub fn is_0(&self) -> bool {
438 *self == IICIE_A::_0
439 }
440 #[doc = "Checks if the value of the field is `_1`"]
441 #[inline(always)]
442 pub fn is_1(&self) -> bool {
443 *self == IICIE_A::_1
444 }
445}
446#[doc = "Write proxy for field `IICIE`"]
447pub struct IICIE_W<'a> {
448 w: &'a mut W,
449}
450impl<'a> IICIE_W<'a> {
451 #[doc = r"Writes `variant` to the field"]
452 #[inline(always)]
453 pub fn variant(self, variant: IICIE_A) -> &'a mut W {
454 {
455 self.bit(variant.into())
456 }
457 }
458 #[doc = "Disabled"]
459 #[inline(always)]
460 pub fn _0(self) -> &'a mut W {
461 self.variant(IICIE_A::_0)
462 }
463 #[doc = "Enabled"]
464 #[inline(always)]
465 pub fn _1(self) -> &'a mut W {
466 self.variant(IICIE_A::_1)
467 }
468 #[doc = r"Sets the field bit"]
469 #[inline(always)]
470 pub fn set_bit(self) -> &'a mut W {
471 self.bit(true)
472 }
473 #[doc = r"Clears the field bit"]
474 #[inline(always)]
475 pub fn clear_bit(self) -> &'a mut W {
476 self.bit(false)
477 }
478 #[doc = r"Writes raw bits to the field"]
479 #[inline(always)]
480 pub fn bit(self, value: bool) -> &'a mut W {
481 self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u8) & 0x01) << 6);
482 self.w
483 }
484}
485#[doc = "I2C Enable\n\nValue on reset: 0"]
486#[derive(Clone, Copy, Debug, PartialEq)]
487pub enum IICEN_A {
488 #[doc = "0: Disabled"]
489 _0 = 0,
490 #[doc = "1: Enabled"]
491 _1 = 1,
492}
493impl From<IICEN_A> for bool {
494 #[inline(always)]
495 fn from(variant: IICEN_A) -> Self {
496 variant as u8 != 0
497 }
498}
499#[doc = "Reader of field `IICEN`"]
500pub type IICEN_R = crate::R<bool, IICEN_A>;
501impl IICEN_R {
502 #[doc = r"Get enumerated values variant"]
503 #[inline(always)]
504 pub fn variant(&self) -> IICEN_A {
505 match self.bits {
506 false => IICEN_A::_0,
507 true => IICEN_A::_1,
508 }
509 }
510 #[doc = "Checks if the value of the field is `_0`"]
511 #[inline(always)]
512 pub fn is_0(&self) -> bool {
513 *self == IICEN_A::_0
514 }
515 #[doc = "Checks if the value of the field is `_1`"]
516 #[inline(always)]
517 pub fn is_1(&self) -> bool {
518 *self == IICEN_A::_1
519 }
520}
521#[doc = "Write proxy for field `IICEN`"]
522pub struct IICEN_W<'a> {
523 w: &'a mut W,
524}
525impl<'a> IICEN_W<'a> {
526 #[doc = r"Writes `variant` to the field"]
527 #[inline(always)]
528 pub fn variant(self, variant: IICEN_A) -> &'a mut W {
529 {
530 self.bit(variant.into())
531 }
532 }
533 #[doc = "Disabled"]
534 #[inline(always)]
535 pub fn _0(self) -> &'a mut W {
536 self.variant(IICEN_A::_0)
537 }
538 #[doc = "Enabled"]
539 #[inline(always)]
540 pub fn _1(self) -> &'a mut W {
541 self.variant(IICEN_A::_1)
542 }
543 #[doc = r"Sets the field bit"]
544 #[inline(always)]
545 pub fn set_bit(self) -> &'a mut W {
546 self.bit(true)
547 }
548 #[doc = r"Clears the field bit"]
549 #[inline(always)]
550 pub fn clear_bit(self) -> &'a mut W {
551 self.bit(false)
552 }
553 #[doc = r"Writes raw bits to the field"]
554 #[inline(always)]
555 pub fn bit(self, value: bool) -> &'a mut W {
556 self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u8) & 0x01) << 7);
557 self.w
558 }
559}
560impl R {
561 #[doc = "Bit 0 - DMA Enable"]
562 #[inline(always)]
563 pub fn dmaen(&self) -> DMAEN_R {
564 DMAEN_R::new((self.bits & 0x01) != 0)
565 }
566 #[doc = "Bit 1 - Wakeup Enable"]
567 #[inline(always)]
568 pub fn wuen(&self) -> WUEN_R {
569 WUEN_R::new(((self.bits >> 1) & 0x01) != 0)
570 }
571 #[doc = "Bit 3 - Transmit Acknowledge Enable"]
572 #[inline(always)]
573 pub fn txak(&self) -> TXAK_R {
574 TXAK_R::new(((self.bits >> 3) & 0x01) != 0)
575 }
576 #[doc = "Bit 4 - Transmit Mode Select"]
577 #[inline(always)]
578 pub fn tx(&self) -> TX_R {
579 TX_R::new(((self.bits >> 4) & 0x01) != 0)
580 }
581 #[doc = "Bit 5 - Master Mode Select"]
582 #[inline(always)]
583 pub fn mst(&self) -> MST_R {
584 MST_R::new(((self.bits >> 5) & 0x01) != 0)
585 }
586 #[doc = "Bit 6 - I2C Interrupt Enable"]
587 #[inline(always)]
588 pub fn iicie(&self) -> IICIE_R {
589 IICIE_R::new(((self.bits >> 6) & 0x01) != 0)
590 }
591 #[doc = "Bit 7 - I2C Enable"]
592 #[inline(always)]
593 pub fn iicen(&self) -> IICEN_R {
594 IICEN_R::new(((self.bits >> 7) & 0x01) != 0)
595 }
596}
597impl W {
598 #[doc = "Bit 0 - DMA Enable"]
599 #[inline(always)]
600 pub fn dmaen(&mut self) -> DMAEN_W {
601 DMAEN_W { w: self }
602 }
603 #[doc = "Bit 1 - Wakeup Enable"]
604 #[inline(always)]
605 pub fn wuen(&mut self) -> WUEN_W {
606 WUEN_W { w: self }
607 }
608 #[doc = "Bit 2 - Repeat START"]
609 #[inline(always)]
610 pub fn rsta(&mut self) -> RSTA_W {
611 RSTA_W { w: self }
612 }
613 #[doc = "Bit 3 - Transmit Acknowledge Enable"]
614 #[inline(always)]
615 pub fn txak(&mut self) -> TXAK_W {
616 TXAK_W { w: self }
617 }
618 #[doc = "Bit 4 - Transmit Mode Select"]
619 #[inline(always)]
620 pub fn tx(&mut self) -> TX_W {
621 TX_W { w: self }
622 }
623 #[doc = "Bit 5 - Master Mode Select"]
624 #[inline(always)]
625 pub fn mst(&mut self) -> MST_W {
626 MST_W { w: self }
627 }
628 #[doc = "Bit 6 - I2C Interrupt Enable"]
629 #[inline(always)]
630 pub fn iicie(&mut self) -> IICIE_W {
631 IICIE_W { w: self }
632 }
633 #[doc = "Bit 7 - I2C Enable"]
634 #[inline(always)]
635 pub fn iicen(&mut self) -> IICEN_W {
636 IICEN_W { w: self }
637 }
638}