#[doc = "Reader of register SCGC6"]
pub type R = crate::R<u32, super::SCGC6>;
#[doc = "Writer for register SCGC6"]
pub type W = crate::W<u32, super::SCGC6>;
#[doc = "Register SCGC6 `reset()`'s with value 0x01"]
impl crate::ResetValue for super::SCGC6 {
type Type = u32;
#[inline(always)]
fn reset_value() -> Self::Type {
0x01
}
}
#[doc = "Flash Memory Clock Gate Control\n\nValue on reset: 1"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTF_A {
#[doc = "0: Clock disabled"]
_0 = 0,
#[doc = "1: Clock enabled"]
_1 = 1,
}
impl From<FTF_A> for bool {
#[inline(always)]
fn from(variant: FTF_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `FTF`"]
pub type FTF_R = crate::R<bool, FTF_A>;
impl FTF_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> FTF_A {
match self.bits {
false => FTF_A::_0,
true => FTF_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == FTF_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == FTF_A::_1
}
}
#[doc = "Write proxy for field `FTF`"]
pub struct FTF_W<'a> {
w: &'a mut W,
}
impl<'a> FTF_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: FTF_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Clock disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(FTF_A::_0)
}
#[doc = "Clock enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(FTF_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
self.w
}
}
#[doc = "DMA Mux Clock Gate Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAMUX_A {
#[doc = "0: Clock disabled"]
_0 = 0,
#[doc = "1: Clock enabled"]
_1 = 1,
}
impl From<DMAMUX_A> for bool {
#[inline(always)]
fn from(variant: DMAMUX_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `DMAMUX`"]
pub type DMAMUX_R = crate::R<bool, DMAMUX_A>;
impl DMAMUX_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> DMAMUX_A {
match self.bits {
false => DMAMUX_A::_0,
true => DMAMUX_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == DMAMUX_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == DMAMUX_A::_1
}
}
#[doc = "Write proxy for field `DMAMUX`"]
pub struct DMAMUX_W<'a> {
w: &'a mut W,
}
impl<'a> DMAMUX_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DMAMUX_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Clock disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(DMAMUX_A::_0)
}
#[doc = "Clock enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(DMAMUX_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
self.w
}
}
#[doc = "PIT Clock Gate Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PIT_A {
#[doc = "0: Clock disabled"]
_0 = 0,
#[doc = "1: Clock enabled"]
_1 = 1,
}
impl From<PIT_A> for bool {
#[inline(always)]
fn from(variant: PIT_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `PIT`"]
pub type PIT_R = crate::R<bool, PIT_A>;
impl PIT_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> PIT_A {
match self.bits {
false => PIT_A::_0,
true => PIT_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == PIT_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == PIT_A::_1
}
}
#[doc = "Write proxy for field `PIT`"]
pub struct PIT_W<'a> {
w: &'a mut W,
}
impl<'a> PIT_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: PIT_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Clock disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(PIT_A::_0)
}
#[doc = "Clock enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(PIT_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
self.w
}
}
#[doc = "TPM0 Clock Gate Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TPM0_A {
#[doc = "0: Clock disabled"]
_0 = 0,
#[doc = "1: Clock enabled"]
_1 = 1,
}
impl From<TPM0_A> for bool {
#[inline(always)]
fn from(variant: TPM0_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `TPM0`"]
pub type TPM0_R = crate::R<bool, TPM0_A>;
impl TPM0_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> TPM0_A {
match self.bits {
false => TPM0_A::_0,
true => TPM0_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == TPM0_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == TPM0_A::_1
}
}
#[doc = "Write proxy for field `TPM0`"]
pub struct TPM0_W<'a> {
w: &'a mut W,
}
impl<'a> TPM0_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TPM0_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Clock disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(TPM0_A::_0)
}
#[doc = "Clock enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(TPM0_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
self.w
}
}
#[doc = "TPM1 Clock Gate Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TPM1_A {
#[doc = "0: Clock disabled"]
_0 = 0,
#[doc = "1: Clock enabled"]
_1 = 1,
}
impl From<TPM1_A> for bool {
#[inline(always)]
fn from(variant: TPM1_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `TPM1`"]
pub type TPM1_R = crate::R<bool, TPM1_A>;
impl TPM1_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> TPM1_A {
match self.bits {
false => TPM1_A::_0,
true => TPM1_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == TPM1_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == TPM1_A::_1
}
}
#[doc = "Write proxy for field `TPM1`"]
pub struct TPM1_W<'a> {
w: &'a mut W,
}
impl<'a> TPM1_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TPM1_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Clock disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(TPM1_A::_0)
}
#[doc = "Clock enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(TPM1_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
self.w
}
}
#[doc = "TPM2 Clock Gate Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TPM2_A {
#[doc = "0: Clock disabled"]
_0 = 0,
#[doc = "1: Clock enabled"]
_1 = 1,
}
impl From<TPM2_A> for bool {
#[inline(always)]
fn from(variant: TPM2_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `TPM2`"]
pub type TPM2_R = crate::R<bool, TPM2_A>;
impl TPM2_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> TPM2_A {
match self.bits {
false => TPM2_A::_0,
true => TPM2_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == TPM2_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == TPM2_A::_1
}
}
#[doc = "Write proxy for field `TPM2`"]
pub struct TPM2_W<'a> {
w: &'a mut W,
}
impl<'a> TPM2_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TPM2_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Clock disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(TPM2_A::_0)
}
#[doc = "Clock enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(TPM2_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
self.w
}
}
#[doc = "ADC0 Clock Gate Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC0_A {
#[doc = "0: Clock disabled"]
_0 = 0,
#[doc = "1: Clock enabled"]
_1 = 1,
}
impl From<ADC0_A> for bool {
#[inline(always)]
fn from(variant: ADC0_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `ADC0`"]
pub type ADC0_R = crate::R<bool, ADC0_A>;
impl ADC0_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> ADC0_A {
match self.bits {
false => ADC0_A::_0,
true => ADC0_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == ADC0_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == ADC0_A::_1
}
}
#[doc = "Write proxy for field `ADC0`"]
pub struct ADC0_W<'a> {
w: &'a mut W,
}
impl<'a> ADC0_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: ADC0_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Clock disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(ADC0_A::_0)
}
#[doc = "Clock enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(ADC0_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
self.w
}
}
#[doc = "RTC Access Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RTC_A {
#[doc = "0: Access and interrupts disabled"]
_0 = 0,
#[doc = "1: Access and interrupts enabled"]
_1 = 1,
}
impl From<RTC_A> for bool {
#[inline(always)]
fn from(variant: RTC_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `RTC`"]
pub type RTC_R = crate::R<bool, RTC_A>;
impl RTC_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> RTC_A {
match self.bits {
false => RTC_A::_0,
true => RTC_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == RTC_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == RTC_A::_1
}
}
#[doc = "Write proxy for field `RTC`"]
pub struct RTC_W<'a> {
w: &'a mut W,
}
impl<'a> RTC_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: RTC_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Access and interrupts disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(RTC_A::_0)
}
#[doc = "Access and interrupts enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(RTC_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
self.w
}
}
#[doc = "DAC0 Clock Gate Control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DAC0_A {
#[doc = "0: Clock disabled"]
_0 = 0,
#[doc = "1: Clock enabled"]
_1 = 1,
}
impl From<DAC0_A> for bool {
#[inline(always)]
fn from(variant: DAC0_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `DAC0`"]
pub type DAC0_R = crate::R<bool, DAC0_A>;
impl DAC0_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> DAC0_A {
match self.bits {
false => DAC0_A::_0,
true => DAC0_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == DAC0_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == DAC0_A::_1
}
}
#[doc = "Write proxy for field `DAC0`"]
pub struct DAC0_W<'a> {
w: &'a mut W,
}
impl<'a> DAC0_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DAC0_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Clock disabled"]
#[inline(always)]
pub fn _0(self) -> &'a mut W {
self.variant(DAC0_A::_0)
}
#[doc = "Clock enabled"]
#[inline(always)]
pub fn _1(self) -> &'a mut W {
self.variant(DAC0_A::_1)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
self.w
}
}
impl R {
#[doc = "Bit 0 - Flash Memory Clock Gate Control"]
#[inline(always)]
pub fn ftf(&self) -> FTF_R {
FTF_R::new((self.bits & 0x01) != 0)
}
#[doc = "Bit 1 - DMA Mux Clock Gate Control"]
#[inline(always)]
pub fn dmamux(&self) -> DMAMUX_R {
DMAMUX_R::new(((self.bits >> 1) & 0x01) != 0)
}
#[doc = "Bit 23 - PIT Clock Gate Control"]
#[inline(always)]
pub fn pit(&self) -> PIT_R {
PIT_R::new(((self.bits >> 23) & 0x01) != 0)
}
#[doc = "Bit 24 - TPM0 Clock Gate Control"]
#[inline(always)]
pub fn tpm0(&self) -> TPM0_R {
TPM0_R::new(((self.bits >> 24) & 0x01) != 0)
}
#[doc = "Bit 25 - TPM1 Clock Gate Control"]
#[inline(always)]
pub fn tpm1(&self) -> TPM1_R {
TPM1_R::new(((self.bits >> 25) & 0x01) != 0)
}
#[doc = "Bit 26 - TPM2 Clock Gate Control"]
#[inline(always)]
pub fn tpm2(&self) -> TPM2_R {
TPM2_R::new(((self.bits >> 26) & 0x01) != 0)
}
#[doc = "Bit 27 - ADC0 Clock Gate Control"]
#[inline(always)]
pub fn adc0(&self) -> ADC0_R {
ADC0_R::new(((self.bits >> 27) & 0x01) != 0)
}
#[doc = "Bit 29 - RTC Access Control"]
#[inline(always)]
pub fn rtc(&self) -> RTC_R {
RTC_R::new(((self.bits >> 29) & 0x01) != 0)
}
#[doc = "Bit 31 - DAC0 Clock Gate Control"]
#[inline(always)]
pub fn dac0(&self) -> DAC0_R {
DAC0_R::new(((self.bits >> 31) & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 0 - Flash Memory Clock Gate Control"]
#[inline(always)]
pub fn ftf(&mut self) -> FTF_W {
FTF_W { w: self }
}
#[doc = "Bit 1 - DMA Mux Clock Gate Control"]
#[inline(always)]
pub fn dmamux(&mut self) -> DMAMUX_W {
DMAMUX_W { w: self }
}
#[doc = "Bit 23 - PIT Clock Gate Control"]
#[inline(always)]
pub fn pit(&mut self) -> PIT_W {
PIT_W { w: self }
}
#[doc = "Bit 24 - TPM0 Clock Gate Control"]
#[inline(always)]
pub fn tpm0(&mut self) -> TPM0_W {
TPM0_W { w: self }
}
#[doc = "Bit 25 - TPM1 Clock Gate Control"]
#[inline(always)]
pub fn tpm1(&mut self) -> TPM1_W {
TPM1_W { w: self }
}
#[doc = "Bit 26 - TPM2 Clock Gate Control"]
#[inline(always)]
pub fn tpm2(&mut self) -> TPM2_W {
TPM2_W { w: self }
}
#[doc = "Bit 27 - ADC0 Clock Gate Control"]
#[inline(always)]
pub fn adc0(&mut self) -> ADC0_W {
ADC0_W { w: self }
}
#[doc = "Bit 29 - RTC Access Control"]
#[inline(always)]
pub fn rtc(&mut self) -> RTC_W {
RTC_W { w: self }
}
#[doc = "Bit 31 - DAC0 Clock Gate Control"]
#[inline(always)]
pub fn dac0(&mut self) -> DAC0_W {
DAC0_W { w: self }
}
}