#[doc = r" Value read from the register"]
pub struct R {
bits: u8,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u8,
}
impl super::C1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `LSBFE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LSBFER {
#[doc = "SPI serial data transfers start with most significant bit"]
_0,
#[doc = "SPI serial data transfers start with least significant bit"]
_1,
}
impl LSBFER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
LSBFER::_0 => false,
LSBFER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> LSBFER {
match value {
false => LSBFER::_0,
true => LSBFER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == LSBFER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == LSBFER::_1
}
}
#[doc = "Possible values of the field `SSOE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SSOER {
#[doc = "When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input."]
_0,
#[doc = "When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input."]
_1,
}
impl SSOER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SSOER::_0 => false,
SSOER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SSOER {
match value {
false => SSOER::_0,
true => SSOER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SSOER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SSOER::_1
}
}
#[doc = "Possible values of the field `CPHA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CPHAR {
#[doc = "First edge on SPSCK occurs at the middle of the first cycle of a data transfer"]
_0,
#[doc = "First edge on SPSCK occurs at the start of the first cycle of a data transfer"]
_1,
}
impl CPHAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CPHAR::_0 => false,
CPHAR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CPHAR {
match value {
false => CPHAR::_0,
true => CPHAR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == CPHAR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == CPHAR::_1
}
}
#[doc = "Possible values of the field `CPOL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CPOLR {
#[doc = "Active-high SPI clock (idles low)"]
_0,
#[doc = "Active-low SPI clock (idles high)"]
_1,
}
impl CPOLR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
CPOLR::_0 => false,
CPOLR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> CPOLR {
match value {
false => CPOLR::_0,
true => CPOLR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == CPOLR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == CPOLR::_1
}
}
#[doc = "Possible values of the field `MSTR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MSTRR {
#[doc = "SPI module configured as a slave SPI device"]
_0,
#[doc = "SPI module configured as a master SPI device"]
_1,
}
impl MSTRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MSTRR::_0 => false,
MSTRR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MSTRR {
match value {
false => MSTRR::_0,
true => MSTRR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == MSTRR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == MSTRR::_1
}
}
#[doc = "Possible values of the field `SPTIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPTIER {
#[doc = "Interrupts from SPTEF inhibited (use polling)"]
_0,
#[doc = "When SPTEF is 1, hardware interrupt requested"]
_1,
}
impl SPTIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SPTIER::_0 => false,
SPTIER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SPTIER {
match value {
false => SPTIER::_0,
true => SPTIER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SPTIER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SPTIER::_1
}
}
#[doc = "Possible values of the field `SPE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPER {
#[doc = "SPI system inactive"]
_0,
#[doc = "SPI system enabled"]
_1,
}
impl SPER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SPER::_0 => false,
SPER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SPER {
match value {
false => SPER::_0,
true => SPER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SPER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SPER::_1
}
}
#[doc = "Possible values of the field `SPIE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPIER {
#[doc = "Interrupts from SPRF and MODF are inhibited-use polling"]
_0,
#[doc = "Request a hardware interrupt when SPRF or MODF is 1"]
_1,
}
impl SPIER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SPIER::_0 => false,
SPIER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SPIER {
match value {
false => SPIER::_0,
true => SPIER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SPIER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SPIER::_1
}
}
#[doc = "Values that can be written to the field `LSBFE`"]
pub enum LSBFEW {
#[doc = "SPI serial data transfers start with most significant bit"]
_0,
#[doc = "SPI serial data transfers start with least significant bit"]
_1,
}
impl LSBFEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
LSBFEW::_0 => false,
LSBFEW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _LSBFEW<'a> {
w: &'a mut W,
}
impl<'a> _LSBFEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: LSBFEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "SPI serial data transfers start with most significant bit"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(LSBFEW::_0)
}
#[doc = "SPI serial data transfers start with least significant bit"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(LSBFEW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u8) << OFFSET);
self.w.bits |= ((value & MASK) as u8) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SSOE`"]
pub enum SSOEW {
#[doc = "When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input."]
_0,
#[doc = "When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input."]
_1,
}
impl SSOEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SSOEW::_0 => false,
SSOEW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SSOEW<'a> {
w: &'a mut W,
}
impl<'a> _SSOEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SSOEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SSOEW::_0)
}
#[doc = "When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SSOEW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u8) << OFFSET);
self.w.bits |= ((value & MASK) as u8) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CPHA`"]
pub enum CPHAW {
#[doc = "First edge on SPSCK occurs at the middle of the first cycle of a data transfer"]
_0,
#[doc = "First edge on SPSCK occurs at the start of the first cycle of a data transfer"]
_1,
}
impl CPHAW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CPHAW::_0 => false,
CPHAW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CPHAW<'a> {
w: &'a mut W,
}
impl<'a> _CPHAW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CPHAW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "First edge on SPSCK occurs at the middle of the first cycle of a data transfer"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(CPHAW::_0)
}
#[doc = "First edge on SPSCK occurs at the start of the first cycle of a data transfer"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(CPHAW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u8) << OFFSET);
self.w.bits |= ((value & MASK) as u8) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `CPOL`"]
pub enum CPOLW {
#[doc = "Active-high SPI clock (idles low)"]
_0,
#[doc = "Active-low SPI clock (idles high)"]
_1,
}
impl CPOLW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
CPOLW::_0 => false,
CPOLW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _CPOLW<'a> {
w: &'a mut W,
}
impl<'a> _CPOLW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CPOLW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Active-high SPI clock (idles low)"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(CPOLW::_0)
}
#[doc = "Active-low SPI clock (idles high)"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(CPOLW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u8) << OFFSET);
self.w.bits |= ((value & MASK) as u8) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MSTR`"]
pub enum MSTRW {
#[doc = "SPI module configured as a slave SPI device"]
_0,
#[doc = "SPI module configured as a master SPI device"]
_1,
}
impl MSTRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MSTRW::_0 => false,
MSTRW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _MSTRW<'a> {
w: &'a mut W,
}
impl<'a> _MSTRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MSTRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "SPI module configured as a slave SPI device"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(MSTRW::_0)
}
#[doc = "SPI module configured as a master SPI device"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(MSTRW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u8) << OFFSET);
self.w.bits |= ((value & MASK) as u8) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SPTIE`"]
pub enum SPTIEW {
#[doc = "Interrupts from SPTEF inhibited (use polling)"]
_0,
#[doc = "When SPTEF is 1, hardware interrupt requested"]
_1,
}
impl SPTIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SPTIEW::_0 => false,
SPTIEW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SPTIEW<'a> {
w: &'a mut W,
}
impl<'a> _SPTIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SPTIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupts from SPTEF inhibited (use polling)"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SPTIEW::_0)
}
#[doc = "When SPTEF is 1, hardware interrupt requested"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SPTIEW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u8) << OFFSET);
self.w.bits |= ((value & MASK) as u8) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SPE`"]
pub enum SPEW {
#[doc = "SPI system inactive"]
_0,
#[doc = "SPI system enabled"]
_1,
}
impl SPEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SPEW::_0 => false,
SPEW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SPEW<'a> {
w: &'a mut W,
}
impl<'a> _SPEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SPEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "SPI system inactive"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SPEW::_0)
}
#[doc = "SPI system enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SPEW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u8) << OFFSET);
self.w.bits |= ((value & MASK) as u8) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SPIE`"]
pub enum SPIEW {
#[doc = "Interrupts from SPRF and MODF are inhibited-use polling"]
_0,
#[doc = "Request a hardware interrupt when SPRF or MODF is 1"]
_1,
}
impl SPIEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SPIEW::_0 => false,
SPIEW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SPIEW<'a> {
w: &'a mut W,
}
impl<'a> _SPIEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SPIEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Interrupts from SPRF and MODF are inhibited-use polling"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SPIEW::_0)
}
#[doc = "Request a hardware interrupt when SPRF or MODF is 1"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SPIEW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u8) << OFFSET);
self.w.bits |= ((value & MASK) as u8) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
#[doc = "Bit 0 - LSB first (shifter direction)"]
#[inline]
pub fn lsbfe(&self) -> LSBFER {
LSBFER::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u8) != 0
})
}
#[doc = "Bit 1 - Slave select output enable"]
#[inline]
pub fn ssoe(&self) -> SSOER {
SSOER::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u8) != 0
})
}
#[doc = "Bit 2 - Clock phase"]
#[inline]
pub fn cpha(&self) -> CPHAR {
CPHAR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u8) != 0
})
}
#[doc = "Bit 3 - Clock polarity"]
#[inline]
pub fn cpol(&self) -> CPOLR {
CPOLR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u8) != 0
})
}
#[doc = "Bit 4 - Master/slave mode select"]
#[inline]
pub fn mstr(&self) -> MSTRR {
MSTRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u8) != 0
})
}
#[doc = "Bit 5 - SPI transmit interrupt enable"]
#[inline]
pub fn sptie(&self) -> SPTIER {
SPTIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u8) != 0
})
}
#[doc = "Bit 6 - SPI system enable"]
#[inline]
pub fn spe(&self) -> SPER {
SPER::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u8) != 0
})
}
#[doc = "Bit 7 - SPI interrupt enable: for SPRF and MODF"]
#[inline]
pub fn spie(&self) -> SPIER {
SPIER::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u8) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 4 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - LSB first (shifter direction)"]
#[inline]
pub fn lsbfe(&mut self) -> _LSBFEW {
_LSBFEW { w: self }
}
#[doc = "Bit 1 - Slave select output enable"]
#[inline]
pub fn ssoe(&mut self) -> _SSOEW {
_SSOEW { w: self }
}
#[doc = "Bit 2 - Clock phase"]
#[inline]
pub fn cpha(&mut self) -> _CPHAW {
_CPHAW { w: self }
}
#[doc = "Bit 3 - Clock polarity"]
#[inline]
pub fn cpol(&mut self) -> _CPOLW {
_CPOLW { w: self }
}
#[doc = "Bit 4 - Master/slave mode select"]
#[inline]
pub fn mstr(&mut self) -> _MSTRW {
_MSTRW { w: self }
}
#[doc = "Bit 5 - SPI transmit interrupt enable"]
#[inline]
pub fn sptie(&mut self) -> _SPTIEW {
_SPTIEW { w: self }
}
#[doc = "Bit 6 - SPI system enable"]
#[inline]
pub fn spe(&mut self) -> _SPEW {
_SPEW { w: self }
}
#[doc = "Bit 7 - SPI interrupt enable: for SPRF and MODF"]
#[inline]
pub fn spie(&mut self) -> _SPIEW {
_SPIEW { w: self }
}
}