#![feature(used)]
#![feature(const_fn)]
#![feature(asm)]
#![no_main]
#![no_std]
extern crate mk66f18;
extern crate cortex_m;
extern crate panic_semihosting;
extern crate cortex_m_rt as rt;
use rt::{entry, pre_init};
#[entry]
fn main() -> ! {
let sim = mk66f18::SIM::ptr();
let porta = mk66f18::PORTA::ptr();
let pta = mk66f18::PTA::ptr();
let portc = mk66f18::PORTC::ptr();
let ptc = mk66f18::PTC::ptr();
let porte = mk66f18::PORTE::ptr();
let pte = mk66f18::PTE::ptr();
unsafe {
(*sim).scgc5.modify(|_, w| w.porta().set_bit());
(*sim).scgc5.modify(|_, w| w.portc().set_bit());
(*sim).scgc5.modify(|_, w| w.porte().set_bit());
(*porta).pcr[11].modify(|_, w| w.mux()._001());
(*pta).pddr.modify(|r, w| w.bits(r.bits() | 0b1 << 11));
(*pta).pcor.write(|w| w.bits(0b1 << 11));
(*portc).pcr[9].modify(|_, w| w.mux()._001());
(*ptc).pddr.modify(|r, w| w.bits(r.bits() | 0b1 << 9));
(*ptc).pcor.write(|w| w.bits(0b1 << 9));
(*porte).pcr[6].modify(|_, w| w.mux()._001());
(*pte).pddr.modify(|r, w| w.bits(r.bits() | 0b1 << 6));
(*pte).pcor.write(|w| w.bits(0b1 << 6));
}
loop {
unsafe {
(*pta).pcor.write(|w| w.bits(0b1 << 11));
(*ptc).psor.write(|w| w.bits(0b1 << 9));
(*pte).psor.write(|w| w.bits(0b1 << 6));
}
for _ in 0..100_000 {
cortex_m::asm::nop();
}
unsafe {
(*pta).psor.write(|w| w.bits(0b1 << 11));
(*ptc).pcor.write(|w| w.bits(0b1 << 9));
(*pte).psor.write(|w| w.bits(0b1 << 6));
}
for _ in 0..100_000 {
cortex_m::asm::nop();
}
unsafe {
(*pta).psor.write(|w| w.bits(0b1 << 11));
(*ptc).psor.write(|w| w.bits(0b1 << 9));
(*pte).pcor.write(|w| w.bits(0b1 << 6));
}
for _ in 0..100_000 {
cortex_m::asm::nop();
}
}
}
#[pre_init]
unsafe fn pre_init() {
asm!("
movw r0, #0x2000
movt r0, #0x4005
movw r1, #0xc520
strh r1, [r0, #14]
movw r1, #0xd928
strh r1, [r0, #14]
movw r1, #0x01d2
strh r1, [r0, #0]
"
:
:
:
: "volatile");
}