mk66f18/dma/
ssrt.rs

1#[doc = "Writer for register SSRT"]
2pub type W = crate::W<u8, super::SSRT>;
3#[doc = "Register SSRT `reset()`'s with value 0"]
4impl crate::ResetValue for super::SSRT {
5    type Type = u8;
6    #[inline(always)]
7    fn reset_value() -> Self::Type {
8        0
9    }
10}
11#[doc = "Write proxy for field `SSRT`"]
12pub struct SSRT_W<'a> {
13    w: &'a mut W,
14}
15impl<'a> SSRT_W<'a> {
16    #[doc = r"Writes raw bits to the field"]
17    #[inline(always)]
18    pub unsafe fn bits(self, value: u8) -> &'a mut W {
19        self.w.bits = (self.w.bits & !0x1f) | ((value as u8) & 0x1f);
20        self.w
21    }
22}
23#[doc = "Set All START Bits (activates all channels)\n\nValue on reset: 0"]
24#[derive(Clone, Copy, Debug, PartialEq)]
25pub enum SAST_AW {
26    #[doc = "0: Set only the TCDn_CSR\\[START\\] bit specified in the SSRT field"]
27    _0,
28    #[doc = "1: Set all bits in TCDn_CSR\\[START\\]"]
29    _1,
30}
31impl From<SAST_AW> for bool {
32    #[inline(always)]
33    fn from(variant: SAST_AW) -> Self {
34        match variant {
35            SAST_AW::_0 => false,
36            SAST_AW::_1 => true,
37        }
38    }
39}
40#[doc = "Write proxy for field `SAST`"]
41pub struct SAST_W<'a> {
42    w: &'a mut W,
43}
44impl<'a> SAST_W<'a> {
45    #[doc = r"Writes `variant` to the field"]
46    #[inline(always)]
47    pub fn variant(self, variant: SAST_AW) -> &'a mut W {
48        {
49            self.bit(variant.into())
50        }
51    }
52    #[doc = "Set only the TCDn_CSR\\[START\\] bit specified in the SSRT field"]
53    #[inline(always)]
54    pub fn _0(self) -> &'a mut W {
55        self.variant(SAST_AW::_0)
56    }
57    #[doc = "Set all bits in TCDn_CSR\\[START\\]"]
58    #[inline(always)]
59    pub fn _1(self) -> &'a mut W {
60        self.variant(SAST_AW::_1)
61    }
62    #[doc = r"Sets the field bit"]
63    #[inline(always)]
64    pub fn set_bit(self) -> &'a mut W {
65        self.bit(true)
66    }
67    #[doc = r"Clears the field bit"]
68    #[inline(always)]
69    pub fn clear_bit(self) -> &'a mut W {
70        self.bit(false)
71    }
72    #[doc = r"Writes raw bits to the field"]
73    #[inline(always)]
74    pub fn bit(self, value: bool) -> &'a mut W {
75        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u8) & 0x01) << 6);
76        self.w
77    }
78}
79#[doc = "No Op enable\n\nValue on reset: 0"]
80#[derive(Clone, Copy, Debug, PartialEq)]
81pub enum NOP_AW {
82    #[doc = "0: Normal operation"]
83    _0,
84    #[doc = "1: No operation, ignore the other bits in this register"]
85    _1,
86}
87impl From<NOP_AW> for bool {
88    #[inline(always)]
89    fn from(variant: NOP_AW) -> Self {
90        match variant {
91            NOP_AW::_0 => false,
92            NOP_AW::_1 => true,
93        }
94    }
95}
96#[doc = "Write proxy for field `NOP`"]
97pub struct NOP_W<'a> {
98    w: &'a mut W,
99}
100impl<'a> NOP_W<'a> {
101    #[doc = r"Writes `variant` to the field"]
102    #[inline(always)]
103    pub fn variant(self, variant: NOP_AW) -> &'a mut W {
104        {
105            self.bit(variant.into())
106        }
107    }
108    #[doc = "Normal operation"]
109    #[inline(always)]
110    pub fn _0(self) -> &'a mut W {
111        self.variant(NOP_AW::_0)
112    }
113    #[doc = "No operation, ignore the other bits in this register"]
114    #[inline(always)]
115    pub fn _1(self) -> &'a mut W {
116        self.variant(NOP_AW::_1)
117    }
118    #[doc = r"Sets the field bit"]
119    #[inline(always)]
120    pub fn set_bit(self) -> &'a mut W {
121        self.bit(true)
122    }
123    #[doc = r"Clears the field bit"]
124    #[inline(always)]
125    pub fn clear_bit(self) -> &'a mut W {
126        self.bit(false)
127    }
128    #[doc = r"Writes raw bits to the field"]
129    #[inline(always)]
130    pub fn bit(self, value: bool) -> &'a mut W {
131        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u8) & 0x01) << 7);
132        self.w
133    }
134}
135impl W {
136    #[doc = "Bits 0:4 - Set START Bit"]
137    #[inline(always)]
138    pub fn ssrt(&mut self) -> SSRT_W {
139        SSRT_W { w: self }
140    }
141    #[doc = "Bit 6 - Set All START Bits (activates all channels)"]
142    #[inline(always)]
143    pub fn sast(&mut self) -> SAST_W {
144        SAST_W { w: self }
145    }
146    #[doc = "Bit 7 - No Op enable"]
147    #[inline(always)]
148    pub fn nop(&mut self) -> NOP_W {
149        NOP_W { w: self }
150    }
151}
mk66f18/dma/ssrt.rs

mk66f18/dma/
ssrt.rs
