1#[doc = "Reader of register COMBINE"]
2pub type R = crate::R<u32, super::COMBINE>;
3#[doc = "Writer for register COMBINE"]
4pub type W = crate::W<u32, super::COMBINE>;
5#[doc = "Register COMBINE `reset()`'s with value 0"]
6impl crate::ResetValue for super::COMBINE {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Combine Channels For n = 0\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15pub enum COMBINE0_A {
16 #[doc = "0: Channels (n) and (n+1) are independent."]
17 _0,
18 #[doc = "1: Channels (n) and (n+1) are combined."]
19 _1,
20}
21impl From<COMBINE0_A> for bool {
22 #[inline(always)]
23 fn from(variant: COMBINE0_A) -> Self {
24 match variant {
25 COMBINE0_A::_0 => false,
26 COMBINE0_A::_1 => true,
27 }
28 }
29}
30#[doc = "Reader of field `COMBINE0`"]
31pub type COMBINE0_R = crate::R<bool, COMBINE0_A>;
32impl COMBINE0_R {
33 #[doc = r"Get enumerated values variant"]
34 #[inline(always)]
35 pub fn variant(&self) -> COMBINE0_A {
36 match self.bits {
37 false => COMBINE0_A::_0,
38 true => COMBINE0_A::_1,
39 }
40 }
41 #[doc = "Checks if the value of the field is `_0`"]
42 #[inline(always)]
43 pub fn is_0(&self) -> bool {
44 *self == COMBINE0_A::_0
45 }
46 #[doc = "Checks if the value of the field is `_1`"]
47 #[inline(always)]
48 pub fn is_1(&self) -> bool {
49 *self == COMBINE0_A::_1
50 }
51}
52#[doc = "Write proxy for field `COMBINE0`"]
53pub struct COMBINE0_W<'a> {
54 w: &'a mut W,
55}
56impl<'a> COMBINE0_W<'a> {
57 #[doc = r"Writes `variant` to the field"]
58 #[inline(always)]
59 pub fn variant(self, variant: COMBINE0_A) -> &'a mut W {
60 {
61 self.bit(variant.into())
62 }
63 }
64 #[doc = "Channels (n) and (n+1) are independent."]
65 #[inline(always)]
66 pub fn _0(self) -> &'a mut W {
67 self.variant(COMBINE0_A::_0)
68 }
69 #[doc = "Channels (n) and (n+1) are combined."]
70 #[inline(always)]
71 pub fn _1(self) -> &'a mut W {
72 self.variant(COMBINE0_A::_1)
73 }
74 #[doc = r"Sets the field bit"]
75 #[inline(always)]
76 pub fn set_bit(self) -> &'a mut W {
77 self.bit(true)
78 }
79 #[doc = r"Clears the field bit"]
80 #[inline(always)]
81 pub fn clear_bit(self) -> &'a mut W {
82 self.bit(false)
83 }
84 #[doc = r"Writes raw bits to the field"]
85 #[inline(always)]
86 pub fn bit(self, value: bool) -> &'a mut W {
87 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
88 self.w
89 }
90}
91#[doc = "Complement Of Channel (n) For n = 0\n\nValue on reset: 0"]
92#[derive(Clone, Copy, Debug, PartialEq)]
93pub enum COMP0_A {
94 #[doc = "0: The channel (n+1) output is the same as the channel (n) output."]
95 _0,
96 #[doc = "1: The channel (n+1) output is the complement of the channel (n) output."]
97 _1,
98}
99impl From<COMP0_A> for bool {
100 #[inline(always)]
101 fn from(variant: COMP0_A) -> Self {
102 match variant {
103 COMP0_A::_0 => false,
104 COMP0_A::_1 => true,
105 }
106 }
107}
108#[doc = "Reader of field `COMP0`"]
109pub type COMP0_R = crate::R<bool, COMP0_A>;
110impl COMP0_R {
111 #[doc = r"Get enumerated values variant"]
112 #[inline(always)]
113 pub fn variant(&self) -> COMP0_A {
114 match self.bits {
115 false => COMP0_A::_0,
116 true => COMP0_A::_1,
117 }
118 }
119 #[doc = "Checks if the value of the field is `_0`"]
120 #[inline(always)]
121 pub fn is_0(&self) -> bool {
122 *self == COMP0_A::_0
123 }
124 #[doc = "Checks if the value of the field is `_1`"]
125 #[inline(always)]
126 pub fn is_1(&self) -> bool {
127 *self == COMP0_A::_1
128 }
129}
130#[doc = "Write proxy for field `COMP0`"]
131pub struct COMP0_W<'a> {
132 w: &'a mut W,
133}
134impl<'a> COMP0_W<'a> {
135 #[doc = r"Writes `variant` to the field"]
136 #[inline(always)]
137 pub fn variant(self, variant: COMP0_A) -> &'a mut W {
138 {
139 self.bit(variant.into())
140 }
141 }
142 #[doc = "The channel (n+1) output is the same as the channel (n) output."]
143 #[inline(always)]
144 pub fn _0(self) -> &'a mut W {
145 self.variant(COMP0_A::_0)
146 }
147 #[doc = "The channel (n+1) output is the complement of the channel (n) output."]
148 #[inline(always)]
149 pub fn _1(self) -> &'a mut W {
150 self.variant(COMP0_A::_1)
151 }
152 #[doc = r"Sets the field bit"]
153 #[inline(always)]
154 pub fn set_bit(self) -> &'a mut W {
155 self.bit(true)
156 }
157 #[doc = r"Clears the field bit"]
158 #[inline(always)]
159 pub fn clear_bit(self) -> &'a mut W {
160 self.bit(false)
161 }
162 #[doc = r"Writes raw bits to the field"]
163 #[inline(always)]
164 pub fn bit(self, value: bool) -> &'a mut W {
165 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
166 self.w
167 }
168}
169#[doc = "Dual Edge Capture Mode Enable For n = 0\n\nValue on reset: 0"]
170#[derive(Clone, Copy, Debug, PartialEq)]
171pub enum DECAPEN0_A {
172 #[doc = "0: The Dual Edge Capture mode in this pair of channels is disabled."]
173 _0,
174 #[doc = "1: The Dual Edge Capture mode in this pair of channels is enabled."]
175 _1,
176}
177impl From<DECAPEN0_A> for bool {
178 #[inline(always)]
179 fn from(variant: DECAPEN0_A) -> Self {
180 match variant {
181 DECAPEN0_A::_0 => false,
182 DECAPEN0_A::_1 => true,
183 }
184 }
185}
186#[doc = "Reader of field `DECAPEN0`"]
187pub type DECAPEN0_R = crate::R<bool, DECAPEN0_A>;
188impl DECAPEN0_R {
189 #[doc = r"Get enumerated values variant"]
190 #[inline(always)]
191 pub fn variant(&self) -> DECAPEN0_A {
192 match self.bits {
193 false => DECAPEN0_A::_0,
194 true => DECAPEN0_A::_1,
195 }
196 }
197 #[doc = "Checks if the value of the field is `_0`"]
198 #[inline(always)]
199 pub fn is_0(&self) -> bool {
200 *self == DECAPEN0_A::_0
201 }
202 #[doc = "Checks if the value of the field is `_1`"]
203 #[inline(always)]
204 pub fn is_1(&self) -> bool {
205 *self == DECAPEN0_A::_1
206 }
207}
208#[doc = "Write proxy for field `DECAPEN0`"]
209pub struct DECAPEN0_W<'a> {
210 w: &'a mut W,
211}
212impl<'a> DECAPEN0_W<'a> {
213 #[doc = r"Writes `variant` to the field"]
214 #[inline(always)]
215 pub fn variant(self, variant: DECAPEN0_A) -> &'a mut W {
216 {
217 self.bit(variant.into())
218 }
219 }
220 #[doc = "The Dual Edge Capture mode in this pair of channels is disabled."]
221 #[inline(always)]
222 pub fn _0(self) -> &'a mut W {
223 self.variant(DECAPEN0_A::_0)
224 }
225 #[doc = "The Dual Edge Capture mode in this pair of channels is enabled."]
226 #[inline(always)]
227 pub fn _1(self) -> &'a mut W {
228 self.variant(DECAPEN0_A::_1)
229 }
230 #[doc = r"Sets the field bit"]
231 #[inline(always)]
232 pub fn set_bit(self) -> &'a mut W {
233 self.bit(true)
234 }
235 #[doc = r"Clears the field bit"]
236 #[inline(always)]
237 pub fn clear_bit(self) -> &'a mut W {
238 self.bit(false)
239 }
240 #[doc = r"Writes raw bits to the field"]
241 #[inline(always)]
242 pub fn bit(self, value: bool) -> &'a mut W {
243 self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
244 self.w
245 }
246}
247#[doc = "Dual Edge Capture Mode Captures For n = 0\n\nValue on reset: 0"]
248#[derive(Clone, Copy, Debug, PartialEq)]
249pub enum DECAP0_A {
250 #[doc = "0: The dual edge captures are inactive."]
251 _0,
252 #[doc = "1: The dual edge captures are active."]
253 _1,
254}
255impl From<DECAP0_A> for bool {
256 #[inline(always)]
257 fn from(variant: DECAP0_A) -> Self {
258 match variant {
259 DECAP0_A::_0 => false,
260 DECAP0_A::_1 => true,
261 }
262 }
263}
264#[doc = "Reader of field `DECAP0`"]
265pub type DECAP0_R = crate::R<bool, DECAP0_A>;
266impl DECAP0_R {
267 #[doc = r"Get enumerated values variant"]
268 #[inline(always)]
269 pub fn variant(&self) -> DECAP0_A {
270 match self.bits {
271 false => DECAP0_A::_0,
272 true => DECAP0_A::_1,
273 }
274 }
275 #[doc = "Checks if the value of the field is `_0`"]
276 #[inline(always)]
277 pub fn is_0(&self) -> bool {
278 *self == DECAP0_A::_0
279 }
280 #[doc = "Checks if the value of the field is `_1`"]
281 #[inline(always)]
282 pub fn is_1(&self) -> bool {
283 *self == DECAP0_A::_1
284 }
285}
286#[doc = "Write proxy for field `DECAP0`"]
287pub struct DECAP0_W<'a> {
288 w: &'a mut W,
289}
290impl<'a> DECAP0_W<'a> {
291 #[doc = r"Writes `variant` to the field"]
292 #[inline(always)]
293 pub fn variant(self, variant: DECAP0_A) -> &'a mut W {
294 {
295 self.bit(variant.into())
296 }
297 }
298 #[doc = "The dual edge captures are inactive."]
299 #[inline(always)]
300 pub fn _0(self) -> &'a mut W {
301 self.variant(DECAP0_A::_0)
302 }
303 #[doc = "The dual edge captures are active."]
304 #[inline(always)]
305 pub fn _1(self) -> &'a mut W {
306 self.variant(DECAP0_A::_1)
307 }
308 #[doc = r"Sets the field bit"]
309 #[inline(always)]
310 pub fn set_bit(self) -> &'a mut W {
311 self.bit(true)
312 }
313 #[doc = r"Clears the field bit"]
314 #[inline(always)]
315 pub fn clear_bit(self) -> &'a mut W {
316 self.bit(false)
317 }
318 #[doc = r"Writes raw bits to the field"]
319 #[inline(always)]
320 pub fn bit(self, value: bool) -> &'a mut W {
321 self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
322 self.w
323 }
324}
325#[doc = "Deadtime Enable For n = 0\n\nValue on reset: 0"]
326#[derive(Clone, Copy, Debug, PartialEq)]
327pub enum DTEN0_A {
328 #[doc = "0: The deadtime insertion in this pair of channels is disabled."]
329 _0,
330 #[doc = "1: The deadtime insertion in this pair of channels is enabled."]
331 _1,
332}
333impl From<DTEN0_A> for bool {
334 #[inline(always)]
335 fn from(variant: DTEN0_A) -> Self {
336 match variant {
337 DTEN0_A::_0 => false,
338 DTEN0_A::_1 => true,
339 }
340 }
341}
342#[doc = "Reader of field `DTEN0`"]
343pub type DTEN0_R = crate::R<bool, DTEN0_A>;
344impl DTEN0_R {
345 #[doc = r"Get enumerated values variant"]
346 #[inline(always)]
347 pub fn variant(&self) -> DTEN0_A {
348 match self.bits {
349 false => DTEN0_A::_0,
350 true => DTEN0_A::_1,
351 }
352 }
353 #[doc = "Checks if the value of the field is `_0`"]
354 #[inline(always)]
355 pub fn is_0(&self) -> bool {
356 *self == DTEN0_A::_0
357 }
358 #[doc = "Checks if the value of the field is `_1`"]
359 #[inline(always)]
360 pub fn is_1(&self) -> bool {
361 *self == DTEN0_A::_1
362 }
363}
364#[doc = "Write proxy for field `DTEN0`"]
365pub struct DTEN0_W<'a> {
366 w: &'a mut W,
367}
368impl<'a> DTEN0_W<'a> {
369 #[doc = r"Writes `variant` to the field"]
370 #[inline(always)]
371 pub fn variant(self, variant: DTEN0_A) -> &'a mut W {
372 {
373 self.bit(variant.into())
374 }
375 }
376 #[doc = "The deadtime insertion in this pair of channels is disabled."]
377 #[inline(always)]
378 pub fn _0(self) -> &'a mut W {
379 self.variant(DTEN0_A::_0)
380 }
381 #[doc = "The deadtime insertion in this pair of channels is enabled."]
382 #[inline(always)]
383 pub fn _1(self) -> &'a mut W {
384 self.variant(DTEN0_A::_1)
385 }
386 #[doc = r"Sets the field bit"]
387 #[inline(always)]
388 pub fn set_bit(self) -> &'a mut W {
389 self.bit(true)
390 }
391 #[doc = r"Clears the field bit"]
392 #[inline(always)]
393 pub fn clear_bit(self) -> &'a mut W {
394 self.bit(false)
395 }
396 #[doc = r"Writes raw bits to the field"]
397 #[inline(always)]
398 pub fn bit(self, value: bool) -> &'a mut W {
399 self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
400 self.w
401 }
402}
403#[doc = "Synchronization Enable For n = 0\n\nValue on reset: 0"]
404#[derive(Clone, Copy, Debug, PartialEq)]
405pub enum SYNCEN0_A {
406 #[doc = "0: The PWM synchronization in this pair of channels is disabled."]
407 _0,
408 #[doc = "1: The PWM synchronization in this pair of channels is enabled."]
409 _1,
410}
411impl From<SYNCEN0_A> for bool {
412 #[inline(always)]
413 fn from(variant: SYNCEN0_A) -> Self {
414 match variant {
415 SYNCEN0_A::_0 => false,
416 SYNCEN0_A::_1 => true,
417 }
418 }
419}
420#[doc = "Reader of field `SYNCEN0`"]
421pub type SYNCEN0_R = crate::R<bool, SYNCEN0_A>;
422impl SYNCEN0_R {
423 #[doc = r"Get enumerated values variant"]
424 #[inline(always)]
425 pub fn variant(&self) -> SYNCEN0_A {
426 match self.bits {
427 false => SYNCEN0_A::_0,
428 true => SYNCEN0_A::_1,
429 }
430 }
431 #[doc = "Checks if the value of the field is `_0`"]
432 #[inline(always)]
433 pub fn is_0(&self) -> bool {
434 *self == SYNCEN0_A::_0
435 }
436 #[doc = "Checks if the value of the field is `_1`"]
437 #[inline(always)]
438 pub fn is_1(&self) -> bool {
439 *self == SYNCEN0_A::_1
440 }
441}
442#[doc = "Write proxy for field `SYNCEN0`"]
443pub struct SYNCEN0_W<'a> {
444 w: &'a mut W,
445}
446impl<'a> SYNCEN0_W<'a> {
447 #[doc = r"Writes `variant` to the field"]
448 #[inline(always)]
449 pub fn variant(self, variant: SYNCEN0_A) -> &'a mut W {
450 {
451 self.bit(variant.into())
452 }
453 }
454 #[doc = "The PWM synchronization in this pair of channels is disabled."]
455 #[inline(always)]
456 pub fn _0(self) -> &'a mut W {
457 self.variant(SYNCEN0_A::_0)
458 }
459 #[doc = "The PWM synchronization in this pair of channels is enabled."]
460 #[inline(always)]
461 pub fn _1(self) -> &'a mut W {
462 self.variant(SYNCEN0_A::_1)
463 }
464 #[doc = r"Sets the field bit"]
465 #[inline(always)]
466 pub fn set_bit(self) -> &'a mut W {
467 self.bit(true)
468 }
469 #[doc = r"Clears the field bit"]
470 #[inline(always)]
471 pub fn clear_bit(self) -> &'a mut W {
472 self.bit(false)
473 }
474 #[doc = r"Writes raw bits to the field"]
475 #[inline(always)]
476 pub fn bit(self, value: bool) -> &'a mut W {
477 self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
478 self.w
479 }
480}
481#[doc = "Fault Control Enable For n = 0\n\nValue on reset: 0"]
482#[derive(Clone, Copy, Debug, PartialEq)]
483pub enum FAULTEN0_A {
484 #[doc = "0: The fault control in this pair of channels is disabled."]
485 _0,
486 #[doc = "1: The fault control in this pair of channels is enabled."]
487 _1,
488}
489impl From<FAULTEN0_A> for bool {
490 #[inline(always)]
491 fn from(variant: FAULTEN0_A) -> Self {
492 match variant {
493 FAULTEN0_A::_0 => false,
494 FAULTEN0_A::_1 => true,
495 }
496 }
497}
498#[doc = "Reader of field `FAULTEN0`"]
499pub type FAULTEN0_R = crate::R<bool, FAULTEN0_A>;
500impl FAULTEN0_R {
501 #[doc = r"Get enumerated values variant"]
502 #[inline(always)]
503 pub fn variant(&self) -> FAULTEN0_A {
504 match self.bits {
505 false => FAULTEN0_A::_0,
506 true => FAULTEN0_A::_1,
507 }
508 }
509 #[doc = "Checks if the value of the field is `_0`"]
510 #[inline(always)]
511 pub fn is_0(&self) -> bool {
512 *self == FAULTEN0_A::_0
513 }
514 #[doc = "Checks if the value of the field is `_1`"]
515 #[inline(always)]
516 pub fn is_1(&self) -> bool {
517 *self == FAULTEN0_A::_1
518 }
519}
520#[doc = "Write proxy for field `FAULTEN0`"]
521pub struct FAULTEN0_W<'a> {
522 w: &'a mut W,
523}
524impl<'a> FAULTEN0_W<'a> {
525 #[doc = r"Writes `variant` to the field"]
526 #[inline(always)]
527 pub fn variant(self, variant: FAULTEN0_A) -> &'a mut W {
528 {
529 self.bit(variant.into())
530 }
531 }
532 #[doc = "The fault control in this pair of channels is disabled."]
533 #[inline(always)]
534 pub fn _0(self) -> &'a mut W {
535 self.variant(FAULTEN0_A::_0)
536 }
537 #[doc = "The fault control in this pair of channels is enabled."]
538 #[inline(always)]
539 pub fn _1(self) -> &'a mut W {
540 self.variant(FAULTEN0_A::_1)
541 }
542 #[doc = r"Sets the field bit"]
543 #[inline(always)]
544 pub fn set_bit(self) -> &'a mut W {
545 self.bit(true)
546 }
547 #[doc = r"Clears the field bit"]
548 #[inline(always)]
549 pub fn clear_bit(self) -> &'a mut W {
550 self.bit(false)
551 }
552 #[doc = r"Writes raw bits to the field"]
553 #[inline(always)]
554 pub fn bit(self, value: bool) -> &'a mut W {
555 self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
556 self.w
557 }
558}
559#[doc = "Combine Channels For n = 2\n\nValue on reset: 0"]
560#[derive(Clone, Copy, Debug, PartialEq)]
561pub enum COMBINE1_A {
562 #[doc = "0: Channels (n) and (n+1) are independent."]
563 _0,
564 #[doc = "1: Channels (n) and (n+1) are combined."]
565 _1,
566}
567impl From<COMBINE1_A> for bool {
568 #[inline(always)]
569 fn from(variant: COMBINE1_A) -> Self {
570 match variant {
571 COMBINE1_A::_0 => false,
572 COMBINE1_A::_1 => true,
573 }
574 }
575}
576#[doc = "Reader of field `COMBINE1`"]
577pub type COMBINE1_R = crate::R<bool, COMBINE1_A>;
578impl COMBINE1_R {
579 #[doc = r"Get enumerated values variant"]
580 #[inline(always)]
581 pub fn variant(&self) -> COMBINE1_A {
582 match self.bits {
583 false => COMBINE1_A::_0,
584 true => COMBINE1_A::_1,
585 }
586 }
587 #[doc = "Checks if the value of the field is `_0`"]
588 #[inline(always)]
589 pub fn is_0(&self) -> bool {
590 *self == COMBINE1_A::_0
591 }
592 #[doc = "Checks if the value of the field is `_1`"]
593 #[inline(always)]
594 pub fn is_1(&self) -> bool {
595 *self == COMBINE1_A::_1
596 }
597}
598#[doc = "Write proxy for field `COMBINE1`"]
599pub struct COMBINE1_W<'a> {
600 w: &'a mut W,
601}
602impl<'a> COMBINE1_W<'a> {
603 #[doc = r"Writes `variant` to the field"]
604 #[inline(always)]
605 pub fn variant(self, variant: COMBINE1_A) -> &'a mut W {
606 {
607 self.bit(variant.into())
608 }
609 }
610 #[doc = "Channels (n) and (n+1) are independent."]
611 #[inline(always)]
612 pub fn _0(self) -> &'a mut W {
613 self.variant(COMBINE1_A::_0)
614 }
615 #[doc = "Channels (n) and (n+1) are combined."]
616 #[inline(always)]
617 pub fn _1(self) -> &'a mut W {
618 self.variant(COMBINE1_A::_1)
619 }
620 #[doc = r"Sets the field bit"]
621 #[inline(always)]
622 pub fn set_bit(self) -> &'a mut W {
623 self.bit(true)
624 }
625 #[doc = r"Clears the field bit"]
626 #[inline(always)]
627 pub fn clear_bit(self) -> &'a mut W {
628 self.bit(false)
629 }
630 #[doc = r"Writes raw bits to the field"]
631 #[inline(always)]
632 pub fn bit(self, value: bool) -> &'a mut W {
633 self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
634 self.w
635 }
636}
637#[doc = "Complement Of Channel (n) For n = 2\n\nValue on reset: 0"]
638#[derive(Clone, Copy, Debug, PartialEq)]
639pub enum COMP1_A {
640 #[doc = "0: The channel (n+1) output is the same as the channel (n) output."]
641 _0,
642 #[doc = "1: The channel (n+1) output is the complement of the channel (n) output."]
643 _1,
644}
645impl From<COMP1_A> for bool {
646 #[inline(always)]
647 fn from(variant: COMP1_A) -> Self {
648 match variant {
649 COMP1_A::_0 => false,
650 COMP1_A::_1 => true,
651 }
652 }
653}
654#[doc = "Reader of field `COMP1`"]
655pub type COMP1_R = crate::R<bool, COMP1_A>;
656impl COMP1_R {
657 #[doc = r"Get enumerated values variant"]
658 #[inline(always)]
659 pub fn variant(&self) -> COMP1_A {
660 match self.bits {
661 false => COMP1_A::_0,
662 true => COMP1_A::_1,
663 }
664 }
665 #[doc = "Checks if the value of the field is `_0`"]
666 #[inline(always)]
667 pub fn is_0(&self) -> bool {
668 *self == COMP1_A::_0
669 }
670 #[doc = "Checks if the value of the field is `_1`"]
671 #[inline(always)]
672 pub fn is_1(&self) -> bool {
673 *self == COMP1_A::_1
674 }
675}
676#[doc = "Write proxy for field `COMP1`"]
677pub struct COMP1_W<'a> {
678 w: &'a mut W,
679}
680impl<'a> COMP1_W<'a> {
681 #[doc = r"Writes `variant` to the field"]
682 #[inline(always)]
683 pub fn variant(self, variant: COMP1_A) -> &'a mut W {
684 {
685 self.bit(variant.into())
686 }
687 }
688 #[doc = "The channel (n+1) output is the same as the channel (n) output."]
689 #[inline(always)]
690 pub fn _0(self) -> &'a mut W {
691 self.variant(COMP1_A::_0)
692 }
693 #[doc = "The channel (n+1) output is the complement of the channel (n) output."]
694 #[inline(always)]
695 pub fn _1(self) -> &'a mut W {
696 self.variant(COMP1_A::_1)
697 }
698 #[doc = r"Sets the field bit"]
699 #[inline(always)]
700 pub fn set_bit(self) -> &'a mut W {
701 self.bit(true)
702 }
703 #[doc = r"Clears the field bit"]
704 #[inline(always)]
705 pub fn clear_bit(self) -> &'a mut W {
706 self.bit(false)
707 }
708 #[doc = r"Writes raw bits to the field"]
709 #[inline(always)]
710 pub fn bit(self, value: bool) -> &'a mut W {
711 self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
712 self.w
713 }
714}
715#[doc = "Dual Edge Capture Mode Enable For n = 2\n\nValue on reset: 0"]
716#[derive(Clone, Copy, Debug, PartialEq)]
717pub enum DECAPEN1_A {
718 #[doc = "0: The Dual Edge Capture mode in this pair of channels is disabled."]
719 _0,
720 #[doc = "1: The Dual Edge Capture mode in this pair of channels is enabled."]
721 _1,
722}
723impl From<DECAPEN1_A> for bool {
724 #[inline(always)]
725 fn from(variant: DECAPEN1_A) -> Self {
726 match variant {
727 DECAPEN1_A::_0 => false,
728 DECAPEN1_A::_1 => true,
729 }
730 }
731}
732#[doc = "Reader of field `DECAPEN1`"]
733pub type DECAPEN1_R = crate::R<bool, DECAPEN1_A>;
734impl DECAPEN1_R {
735 #[doc = r"Get enumerated values variant"]
736 #[inline(always)]
737 pub fn variant(&self) -> DECAPEN1_A {
738 match self.bits {
739 false => DECAPEN1_A::_0,
740 true => DECAPEN1_A::_1,
741 }
742 }
743 #[doc = "Checks if the value of the field is `_0`"]
744 #[inline(always)]
745 pub fn is_0(&self) -> bool {
746 *self == DECAPEN1_A::_0
747 }
748 #[doc = "Checks if the value of the field is `_1`"]
749 #[inline(always)]
750 pub fn is_1(&self) -> bool {
751 *self == DECAPEN1_A::_1
752 }
753}
754#[doc = "Write proxy for field `DECAPEN1`"]
755pub struct DECAPEN1_W<'a> {
756 w: &'a mut W,
757}
758impl<'a> DECAPEN1_W<'a> {
759 #[doc = r"Writes `variant` to the field"]
760 #[inline(always)]
761 pub fn variant(self, variant: DECAPEN1_A) -> &'a mut W {
762 {
763 self.bit(variant.into())
764 }
765 }
766 #[doc = "The Dual Edge Capture mode in this pair of channels is disabled."]
767 #[inline(always)]
768 pub fn _0(self) -> &'a mut W {
769 self.variant(DECAPEN1_A::_0)
770 }
771 #[doc = "The Dual Edge Capture mode in this pair of channels is enabled."]
772 #[inline(always)]
773 pub fn _1(self) -> &'a mut W {
774 self.variant(DECAPEN1_A::_1)
775 }
776 #[doc = r"Sets the field bit"]
777 #[inline(always)]
778 pub fn set_bit(self) -> &'a mut W {
779 self.bit(true)
780 }
781 #[doc = r"Clears the field bit"]
782 #[inline(always)]
783 pub fn clear_bit(self) -> &'a mut W {
784 self.bit(false)
785 }
786 #[doc = r"Writes raw bits to the field"]
787 #[inline(always)]
788 pub fn bit(self, value: bool) -> &'a mut W {
789 self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
790 self.w
791 }
792}
793#[doc = "Dual Edge Capture Mode Captures For n = 2\n\nValue on reset: 0"]
794#[derive(Clone, Copy, Debug, PartialEq)]
795pub enum DECAP1_A {
796 #[doc = "0: The dual edge captures are inactive."]
797 _0,
798 #[doc = "1: The dual edge captures are active."]
799 _1,
800}
801impl From<DECAP1_A> for bool {
802 #[inline(always)]
803 fn from(variant: DECAP1_A) -> Self {
804 match variant {
805 DECAP1_A::_0 => false,
806 DECAP1_A::_1 => true,
807 }
808 }
809}
810#[doc = "Reader of field `DECAP1`"]
811pub type DECAP1_R = crate::R<bool, DECAP1_A>;
812impl DECAP1_R {
813 #[doc = r"Get enumerated values variant"]
814 #[inline(always)]
815 pub fn variant(&self) -> DECAP1_A {
816 match self.bits {
817 false => DECAP1_A::_0,
818 true => DECAP1_A::_1,
819 }
820 }
821 #[doc = "Checks if the value of the field is `_0`"]
822 #[inline(always)]
823 pub fn is_0(&self) -> bool {
824 *self == DECAP1_A::_0
825 }
826 #[doc = "Checks if the value of the field is `_1`"]
827 #[inline(always)]
828 pub fn is_1(&self) -> bool {
829 *self == DECAP1_A::_1
830 }
831}
832#[doc = "Write proxy for field `DECAP1`"]
833pub struct DECAP1_W<'a> {
834 w: &'a mut W,
835}
836impl<'a> DECAP1_W<'a> {
837 #[doc = r"Writes `variant` to the field"]
838 #[inline(always)]
839 pub fn variant(self, variant: DECAP1_A) -> &'a mut W {
840 {
841 self.bit(variant.into())
842 }
843 }
844 #[doc = "The dual edge captures are inactive."]
845 #[inline(always)]
846 pub fn _0(self) -> &'a mut W {
847 self.variant(DECAP1_A::_0)
848 }
849 #[doc = "The dual edge captures are active."]
850 #[inline(always)]
851 pub fn _1(self) -> &'a mut W {
852 self.variant(DECAP1_A::_1)
853 }
854 #[doc = r"Sets the field bit"]
855 #[inline(always)]
856 pub fn set_bit(self) -> &'a mut W {
857 self.bit(true)
858 }
859 #[doc = r"Clears the field bit"]
860 #[inline(always)]
861 pub fn clear_bit(self) -> &'a mut W {
862 self.bit(false)
863 }
864 #[doc = r"Writes raw bits to the field"]
865 #[inline(always)]
866 pub fn bit(self, value: bool) -> &'a mut W {
867 self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
868 self.w
869 }
870}
871#[doc = "Deadtime Enable For n = 2\n\nValue on reset: 0"]
872#[derive(Clone, Copy, Debug, PartialEq)]
873pub enum DTEN1_A {
874 #[doc = "0: The deadtime insertion in this pair of channels is disabled."]
875 _0,
876 #[doc = "1: The deadtime insertion in this pair of channels is enabled."]
877 _1,
878}
879impl From<DTEN1_A> for bool {
880 #[inline(always)]
881 fn from(variant: DTEN1_A) -> Self {
882 match variant {
883 DTEN1_A::_0 => false,
884 DTEN1_A::_1 => true,
885 }
886 }
887}
888#[doc = "Reader of field `DTEN1`"]
889pub type DTEN1_R = crate::R<bool, DTEN1_A>;
890impl DTEN1_R {
891 #[doc = r"Get enumerated values variant"]
892 #[inline(always)]
893 pub fn variant(&self) -> DTEN1_A {
894 match self.bits {
895 false => DTEN1_A::_0,
896 true => DTEN1_A::_1,
897 }
898 }
899 #[doc = "Checks if the value of the field is `_0`"]
900 #[inline(always)]
901 pub fn is_0(&self) -> bool {
902 *self == DTEN1_A::_0
903 }
904 #[doc = "Checks if the value of the field is `_1`"]
905 #[inline(always)]
906 pub fn is_1(&self) -> bool {
907 *self == DTEN1_A::_1
908 }
909}
910#[doc = "Write proxy for field `DTEN1`"]
911pub struct DTEN1_W<'a> {
912 w: &'a mut W,
913}
914impl<'a> DTEN1_W<'a> {
915 #[doc = r"Writes `variant` to the field"]
916 #[inline(always)]
917 pub fn variant(self, variant: DTEN1_A) -> &'a mut W {
918 {
919 self.bit(variant.into())
920 }
921 }
922 #[doc = "The deadtime insertion in this pair of channels is disabled."]
923 #[inline(always)]
924 pub fn _0(self) -> &'a mut W {
925 self.variant(DTEN1_A::_0)
926 }
927 #[doc = "The deadtime insertion in this pair of channels is enabled."]
928 #[inline(always)]
929 pub fn _1(self) -> &'a mut W {
930 self.variant(DTEN1_A::_1)
931 }
932 #[doc = r"Sets the field bit"]
933 #[inline(always)]
934 pub fn set_bit(self) -> &'a mut W {
935 self.bit(true)
936 }
937 #[doc = r"Clears the field bit"]
938 #[inline(always)]
939 pub fn clear_bit(self) -> &'a mut W {
940 self.bit(false)
941 }
942 #[doc = r"Writes raw bits to the field"]
943 #[inline(always)]
944 pub fn bit(self, value: bool) -> &'a mut W {
945 self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
946 self.w
947 }
948}
949#[doc = "Synchronization Enable For n = 2\n\nValue on reset: 0"]
950#[derive(Clone, Copy, Debug, PartialEq)]
951pub enum SYNCEN1_A {
952 #[doc = "0: The PWM synchronization in this pair of channels is disabled."]
953 _0,
954 #[doc = "1: The PWM synchronization in this pair of channels is enabled."]
955 _1,
956}
957impl From<SYNCEN1_A> for bool {
958 #[inline(always)]
959 fn from(variant: SYNCEN1_A) -> Self {
960 match variant {
961 SYNCEN1_A::_0 => false,
962 SYNCEN1_A::_1 => true,
963 }
964 }
965}
966#[doc = "Reader of field `SYNCEN1`"]
967pub type SYNCEN1_R = crate::R<bool, SYNCEN1_A>;
968impl SYNCEN1_R {
969 #[doc = r"Get enumerated values variant"]
970 #[inline(always)]
971 pub fn variant(&self) -> SYNCEN1_A {
972 match self.bits {
973 false => SYNCEN1_A::_0,
974 true => SYNCEN1_A::_1,
975 }
976 }
977 #[doc = "Checks if the value of the field is `_0`"]
978 #[inline(always)]
979 pub fn is_0(&self) -> bool {
980 *self == SYNCEN1_A::_0
981 }
982 #[doc = "Checks if the value of the field is `_1`"]
983 #[inline(always)]
984 pub fn is_1(&self) -> bool {
985 *self == SYNCEN1_A::_1
986 }
987}
988#[doc = "Write proxy for field `SYNCEN1`"]
989pub struct SYNCEN1_W<'a> {
990 w: &'a mut W,
991}
992impl<'a> SYNCEN1_W<'a> {
993 #[doc = r"Writes `variant` to the field"]
994 #[inline(always)]
995 pub fn variant(self, variant: SYNCEN1_A) -> &'a mut W {
996 {
997 self.bit(variant.into())
998 }
999 }
1000 #[doc = "The PWM synchronization in this pair of channels is disabled."]
1001 #[inline(always)]
1002 pub fn _0(self) -> &'a mut W {
1003 self.variant(SYNCEN1_A::_0)
1004 }
1005 #[doc = "The PWM synchronization in this pair of channels is enabled."]
1006 #[inline(always)]
1007 pub fn _1(self) -> &'a mut W {
1008 self.variant(SYNCEN1_A::_1)
1009 }
1010 #[doc = r"Sets the field bit"]
1011 #[inline(always)]
1012 pub fn set_bit(self) -> &'a mut W {
1013 self.bit(true)
1014 }
1015 #[doc = r"Clears the field bit"]
1016 #[inline(always)]
1017 pub fn clear_bit(self) -> &'a mut W {
1018 self.bit(false)
1019 }
1020 #[doc = r"Writes raw bits to the field"]
1021 #[inline(always)]
1022 pub fn bit(self, value: bool) -> &'a mut W {
1023 self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
1024 self.w
1025 }
1026}
1027#[doc = "Fault Control Enable For n = 2\n\nValue on reset: 0"]
1028#[derive(Clone, Copy, Debug, PartialEq)]
1029pub enum FAULTEN1_A {
1030 #[doc = "0: The fault control in this pair of channels is disabled."]
1031 _0,
1032 #[doc = "1: The fault control in this pair of channels is enabled."]
1033 _1,
1034}
1035impl From<FAULTEN1_A> for bool {
1036 #[inline(always)]
1037 fn from(variant: FAULTEN1_A) -> Self {
1038 match variant {
1039 FAULTEN1_A::_0 => false,
1040 FAULTEN1_A::_1 => true,
1041 }
1042 }
1043}
1044#[doc = "Reader of field `FAULTEN1`"]
1045pub type FAULTEN1_R = crate::R<bool, FAULTEN1_A>;
1046impl FAULTEN1_R {
1047 #[doc = r"Get enumerated values variant"]
1048 #[inline(always)]
1049 pub fn variant(&self) -> FAULTEN1_A {
1050 match self.bits {
1051 false => FAULTEN1_A::_0,
1052 true => FAULTEN1_A::_1,
1053 }
1054 }
1055 #[doc = "Checks if the value of the field is `_0`"]
1056 #[inline(always)]
1057 pub fn is_0(&self) -> bool {
1058 *self == FAULTEN1_A::_0
1059 }
1060 #[doc = "Checks if the value of the field is `_1`"]
1061 #[inline(always)]
1062 pub fn is_1(&self) -> bool {
1063 *self == FAULTEN1_A::_1
1064 }
1065}
1066#[doc = "Write proxy for field `FAULTEN1`"]
1067pub struct FAULTEN1_W<'a> {
1068 w: &'a mut W,
1069}
1070impl<'a> FAULTEN1_W<'a> {
1071 #[doc = r"Writes `variant` to the field"]
1072 #[inline(always)]
1073 pub fn variant(self, variant: FAULTEN1_A) -> &'a mut W {
1074 {
1075 self.bit(variant.into())
1076 }
1077 }
1078 #[doc = "The fault control in this pair of channels is disabled."]
1079 #[inline(always)]
1080 pub fn _0(self) -> &'a mut W {
1081 self.variant(FAULTEN1_A::_0)
1082 }
1083 #[doc = "The fault control in this pair of channels is enabled."]
1084 #[inline(always)]
1085 pub fn _1(self) -> &'a mut W {
1086 self.variant(FAULTEN1_A::_1)
1087 }
1088 #[doc = r"Sets the field bit"]
1089 #[inline(always)]
1090 pub fn set_bit(self) -> &'a mut W {
1091 self.bit(true)
1092 }
1093 #[doc = r"Clears the field bit"]
1094 #[inline(always)]
1095 pub fn clear_bit(self) -> &'a mut W {
1096 self.bit(false)
1097 }
1098 #[doc = r"Writes raw bits to the field"]
1099 #[inline(always)]
1100 pub fn bit(self, value: bool) -> &'a mut W {
1101 self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
1102 self.w
1103 }
1104}
1105#[doc = "Combine Channels For n = 4\n\nValue on reset: 0"]
1106#[derive(Clone, Copy, Debug, PartialEq)]
1107pub enum COMBINE2_A {
1108 #[doc = "0: Channels (n) and (n+1) are independent."]
1109 _0,
1110 #[doc = "1: Channels (n) and (n+1) are combined."]
1111 _1,
1112}
1113impl From<COMBINE2_A> for bool {
1114 #[inline(always)]
1115 fn from(variant: COMBINE2_A) -> Self {
1116 match variant {
1117 COMBINE2_A::_0 => false,
1118 COMBINE2_A::_1 => true,
1119 }
1120 }
1121}
1122#[doc = "Reader of field `COMBINE2`"]
1123pub type COMBINE2_R = crate::R<bool, COMBINE2_A>;
1124impl COMBINE2_R {
1125 #[doc = r"Get enumerated values variant"]
1126 #[inline(always)]
1127 pub fn variant(&self) -> COMBINE2_A {
1128 match self.bits {
1129 false => COMBINE2_A::_0,
1130 true => COMBINE2_A::_1,
1131 }
1132 }
1133 #[doc = "Checks if the value of the field is `_0`"]
1134 #[inline(always)]
1135 pub fn is_0(&self) -> bool {
1136 *self == COMBINE2_A::_0
1137 }
1138 #[doc = "Checks if the value of the field is `_1`"]
1139 #[inline(always)]
1140 pub fn is_1(&self) -> bool {
1141 *self == COMBINE2_A::_1
1142 }
1143}
1144#[doc = "Write proxy for field `COMBINE2`"]
1145pub struct COMBINE2_W<'a> {
1146 w: &'a mut W,
1147}
1148impl<'a> COMBINE2_W<'a> {
1149 #[doc = r"Writes `variant` to the field"]
1150 #[inline(always)]
1151 pub fn variant(self, variant: COMBINE2_A) -> &'a mut W {
1152 {
1153 self.bit(variant.into())
1154 }
1155 }
1156 #[doc = "Channels (n) and (n+1) are independent."]
1157 #[inline(always)]
1158 pub fn _0(self) -> &'a mut W {
1159 self.variant(COMBINE2_A::_0)
1160 }
1161 #[doc = "Channels (n) and (n+1) are combined."]
1162 #[inline(always)]
1163 pub fn _1(self) -> &'a mut W {
1164 self.variant(COMBINE2_A::_1)
1165 }
1166 #[doc = r"Sets the field bit"]
1167 #[inline(always)]
1168 pub fn set_bit(self) -> &'a mut W {
1169 self.bit(true)
1170 }
1171 #[doc = r"Clears the field bit"]
1172 #[inline(always)]
1173 pub fn clear_bit(self) -> &'a mut W {
1174 self.bit(false)
1175 }
1176 #[doc = r"Writes raw bits to the field"]
1177 #[inline(always)]
1178 pub fn bit(self, value: bool) -> &'a mut W {
1179 self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
1180 self.w
1181 }
1182}
1183#[doc = "Complement Of Channel (n) For n = 4\n\nValue on reset: 0"]
1184#[derive(Clone, Copy, Debug, PartialEq)]
1185pub enum COMP2_A {
1186 #[doc = "0: The channel (n+1) output is the same as the channel (n) output."]
1187 _0,
1188 #[doc = "1: The channel (n+1) output is the complement of the channel (n) output."]
1189 _1,
1190}
1191impl From<COMP2_A> for bool {
1192 #[inline(always)]
1193 fn from(variant: COMP2_A) -> Self {
1194 match variant {
1195 COMP2_A::_0 => false,
1196 COMP2_A::_1 => true,
1197 }
1198 }
1199}
1200#[doc = "Reader of field `COMP2`"]
1201pub type COMP2_R = crate::R<bool, COMP2_A>;
1202impl COMP2_R {
1203 #[doc = r"Get enumerated values variant"]
1204 #[inline(always)]
1205 pub fn variant(&self) -> COMP2_A {
1206 match self.bits {
1207 false => COMP2_A::_0,
1208 true => COMP2_A::_1,
1209 }
1210 }
1211 #[doc = "Checks if the value of the field is `_0`"]
1212 #[inline(always)]
1213 pub fn is_0(&self) -> bool {
1214 *self == COMP2_A::_0
1215 }
1216 #[doc = "Checks if the value of the field is `_1`"]
1217 #[inline(always)]
1218 pub fn is_1(&self) -> bool {
1219 *self == COMP2_A::_1
1220 }
1221}
1222#[doc = "Write proxy for field `COMP2`"]
1223pub struct COMP2_W<'a> {
1224 w: &'a mut W,
1225}
1226impl<'a> COMP2_W<'a> {
1227 #[doc = r"Writes `variant` to the field"]
1228 #[inline(always)]
1229 pub fn variant(self, variant: COMP2_A) -> &'a mut W {
1230 {
1231 self.bit(variant.into())
1232 }
1233 }
1234 #[doc = "The channel (n+1) output is the same as the channel (n) output."]
1235 #[inline(always)]
1236 pub fn _0(self) -> &'a mut W {
1237 self.variant(COMP2_A::_0)
1238 }
1239 #[doc = "The channel (n+1) output is the complement of the channel (n) output."]
1240 #[inline(always)]
1241 pub fn _1(self) -> &'a mut W {
1242 self.variant(COMP2_A::_1)
1243 }
1244 #[doc = r"Sets the field bit"]
1245 #[inline(always)]
1246 pub fn set_bit(self) -> &'a mut W {
1247 self.bit(true)
1248 }
1249 #[doc = r"Clears the field bit"]
1250 #[inline(always)]
1251 pub fn clear_bit(self) -> &'a mut W {
1252 self.bit(false)
1253 }
1254 #[doc = r"Writes raw bits to the field"]
1255 #[inline(always)]
1256 pub fn bit(self, value: bool) -> &'a mut W {
1257 self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
1258 self.w
1259 }
1260}
1261#[doc = "Dual Edge Capture Mode Enable For n = 4\n\nValue on reset: 0"]
1262#[derive(Clone, Copy, Debug, PartialEq)]
1263pub enum DECAPEN2_A {
1264 #[doc = "0: The Dual Edge Capture mode in this pair of channels is disabled."]
1265 _0,
1266 #[doc = "1: The Dual Edge Capture mode in this pair of channels is enabled."]
1267 _1,
1268}
1269impl From<DECAPEN2_A> for bool {
1270 #[inline(always)]
1271 fn from(variant: DECAPEN2_A) -> Self {
1272 match variant {
1273 DECAPEN2_A::_0 => false,
1274 DECAPEN2_A::_1 => true,
1275 }
1276 }
1277}
1278#[doc = "Reader of field `DECAPEN2`"]
1279pub type DECAPEN2_R = crate::R<bool, DECAPEN2_A>;
1280impl DECAPEN2_R {
1281 #[doc = r"Get enumerated values variant"]
1282 #[inline(always)]
1283 pub fn variant(&self) -> DECAPEN2_A {
1284 match self.bits {
1285 false => DECAPEN2_A::_0,
1286 true => DECAPEN2_A::_1,
1287 }
1288 }
1289 #[doc = "Checks if the value of the field is `_0`"]
1290 #[inline(always)]
1291 pub fn is_0(&self) -> bool {
1292 *self == DECAPEN2_A::_0
1293 }
1294 #[doc = "Checks if the value of the field is `_1`"]
1295 #[inline(always)]
1296 pub fn is_1(&self) -> bool {
1297 *self == DECAPEN2_A::_1
1298 }
1299}
1300#[doc = "Write proxy for field `DECAPEN2`"]
1301pub struct DECAPEN2_W<'a> {
1302 w: &'a mut W,
1303}
1304impl<'a> DECAPEN2_W<'a> {
1305 #[doc = r"Writes `variant` to the field"]
1306 #[inline(always)]
1307 pub fn variant(self, variant: DECAPEN2_A) -> &'a mut W {
1308 {
1309 self.bit(variant.into())
1310 }
1311 }
1312 #[doc = "The Dual Edge Capture mode in this pair of channels is disabled."]
1313 #[inline(always)]
1314 pub fn _0(self) -> &'a mut W {
1315 self.variant(DECAPEN2_A::_0)
1316 }
1317 #[doc = "The Dual Edge Capture mode in this pair of channels is enabled."]
1318 #[inline(always)]
1319 pub fn _1(self) -> &'a mut W {
1320 self.variant(DECAPEN2_A::_1)
1321 }
1322 #[doc = r"Sets the field bit"]
1323 #[inline(always)]
1324 pub fn set_bit(self) -> &'a mut W {
1325 self.bit(true)
1326 }
1327 #[doc = r"Clears the field bit"]
1328 #[inline(always)]
1329 pub fn clear_bit(self) -> &'a mut W {
1330 self.bit(false)
1331 }
1332 #[doc = r"Writes raw bits to the field"]
1333 #[inline(always)]
1334 pub fn bit(self, value: bool) -> &'a mut W {
1335 self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
1336 self.w
1337 }
1338}
1339#[doc = "Dual Edge Capture Mode Captures For n = 4\n\nValue on reset: 0"]
1340#[derive(Clone, Copy, Debug, PartialEq)]
1341pub enum DECAP2_A {
1342 #[doc = "0: The dual edge captures are inactive."]
1343 _0,
1344 #[doc = "1: The dual edge captures are active."]
1345 _1,
1346}
1347impl From<DECAP2_A> for bool {
1348 #[inline(always)]
1349 fn from(variant: DECAP2_A) -> Self {
1350 match variant {
1351 DECAP2_A::_0 => false,
1352 DECAP2_A::_1 => true,
1353 }
1354 }
1355}
1356#[doc = "Reader of field `DECAP2`"]
1357pub type DECAP2_R = crate::R<bool, DECAP2_A>;
1358impl DECAP2_R {
1359 #[doc = r"Get enumerated values variant"]
1360 #[inline(always)]
1361 pub fn variant(&self) -> DECAP2_A {
1362 match self.bits {
1363 false => DECAP2_A::_0,
1364 true => DECAP2_A::_1,
1365 }
1366 }
1367 #[doc = "Checks if the value of the field is `_0`"]
1368 #[inline(always)]
1369 pub fn is_0(&self) -> bool {
1370 *self == DECAP2_A::_0
1371 }
1372 #[doc = "Checks if the value of the field is `_1`"]
1373 #[inline(always)]
1374 pub fn is_1(&self) -> bool {
1375 *self == DECAP2_A::_1
1376 }
1377}
1378#[doc = "Write proxy for field `DECAP2`"]
1379pub struct DECAP2_W<'a> {
1380 w: &'a mut W,
1381}
1382impl<'a> DECAP2_W<'a> {
1383 #[doc = r"Writes `variant` to the field"]
1384 #[inline(always)]
1385 pub fn variant(self, variant: DECAP2_A) -> &'a mut W {
1386 {
1387 self.bit(variant.into())
1388 }
1389 }
1390 #[doc = "The dual edge captures are inactive."]
1391 #[inline(always)]
1392 pub fn _0(self) -> &'a mut W {
1393 self.variant(DECAP2_A::_0)
1394 }
1395 #[doc = "The dual edge captures are active."]
1396 #[inline(always)]
1397 pub fn _1(self) -> &'a mut W {
1398 self.variant(DECAP2_A::_1)
1399 }
1400 #[doc = r"Sets the field bit"]
1401 #[inline(always)]
1402 pub fn set_bit(self) -> &'a mut W {
1403 self.bit(true)
1404 }
1405 #[doc = r"Clears the field bit"]
1406 #[inline(always)]
1407 pub fn clear_bit(self) -> &'a mut W {
1408 self.bit(false)
1409 }
1410 #[doc = r"Writes raw bits to the field"]
1411 #[inline(always)]
1412 pub fn bit(self, value: bool) -> &'a mut W {
1413 self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
1414 self.w
1415 }
1416}
1417#[doc = "Deadtime Enable For n = 4\n\nValue on reset: 0"]
1418#[derive(Clone, Copy, Debug, PartialEq)]
1419pub enum DTEN2_A {
1420 #[doc = "0: The deadtime insertion in this pair of channels is disabled."]
1421 _0,
1422 #[doc = "1: The deadtime insertion in this pair of channels is enabled."]
1423 _1,
1424}
1425impl From<DTEN2_A> for bool {
1426 #[inline(always)]
1427 fn from(variant: DTEN2_A) -> Self {
1428 match variant {
1429 DTEN2_A::_0 => false,
1430 DTEN2_A::_1 => true,
1431 }
1432 }
1433}
1434#[doc = "Reader of field `DTEN2`"]
1435pub type DTEN2_R = crate::R<bool, DTEN2_A>;
1436impl DTEN2_R {
1437 #[doc = r"Get enumerated values variant"]
1438 #[inline(always)]
1439 pub fn variant(&self) -> DTEN2_A {
1440 match self.bits {
1441 false => DTEN2_A::_0,
1442 true => DTEN2_A::_1,
1443 }
1444 }
1445 #[doc = "Checks if the value of the field is `_0`"]
1446 #[inline(always)]
1447 pub fn is_0(&self) -> bool {
1448 *self == DTEN2_A::_0
1449 }
1450 #[doc = "Checks if the value of the field is `_1`"]
1451 #[inline(always)]
1452 pub fn is_1(&self) -> bool {
1453 *self == DTEN2_A::_1
1454 }
1455}
1456#[doc = "Write proxy for field `DTEN2`"]
1457pub struct DTEN2_W<'a> {
1458 w: &'a mut W,
1459}
1460impl<'a> DTEN2_W<'a> {
1461 #[doc = r"Writes `variant` to the field"]
1462 #[inline(always)]
1463 pub fn variant(self, variant: DTEN2_A) -> &'a mut W {
1464 {
1465 self.bit(variant.into())
1466 }
1467 }
1468 #[doc = "The deadtime insertion in this pair of channels is disabled."]
1469 #[inline(always)]
1470 pub fn _0(self) -> &'a mut W {
1471 self.variant(DTEN2_A::_0)
1472 }
1473 #[doc = "The deadtime insertion in this pair of channels is enabled."]
1474 #[inline(always)]
1475 pub fn _1(self) -> &'a mut W {
1476 self.variant(DTEN2_A::_1)
1477 }
1478 #[doc = r"Sets the field bit"]
1479 #[inline(always)]
1480 pub fn set_bit(self) -> &'a mut W {
1481 self.bit(true)
1482 }
1483 #[doc = r"Clears the field bit"]
1484 #[inline(always)]
1485 pub fn clear_bit(self) -> &'a mut W {
1486 self.bit(false)
1487 }
1488 #[doc = r"Writes raw bits to the field"]
1489 #[inline(always)]
1490 pub fn bit(self, value: bool) -> &'a mut W {
1491 self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
1492 self.w
1493 }
1494}
1495#[doc = "Synchronization Enable For n = 4\n\nValue on reset: 0"]
1496#[derive(Clone, Copy, Debug, PartialEq)]
1497pub enum SYNCEN2_A {
1498 #[doc = "0: The PWM synchronization in this pair of channels is disabled."]
1499 _0,
1500 #[doc = "1: The PWM synchronization in this pair of channels is enabled."]
1501 _1,
1502}
1503impl From<SYNCEN2_A> for bool {
1504 #[inline(always)]
1505 fn from(variant: SYNCEN2_A) -> Self {
1506 match variant {
1507 SYNCEN2_A::_0 => false,
1508 SYNCEN2_A::_1 => true,
1509 }
1510 }
1511}
1512#[doc = "Reader of field `SYNCEN2`"]
1513pub type SYNCEN2_R = crate::R<bool, SYNCEN2_A>;
1514impl SYNCEN2_R {
1515 #[doc = r"Get enumerated values variant"]
1516 #[inline(always)]
1517 pub fn variant(&self) -> SYNCEN2_A {
1518 match self.bits {
1519 false => SYNCEN2_A::_0,
1520 true => SYNCEN2_A::_1,
1521 }
1522 }
1523 #[doc = "Checks if the value of the field is `_0`"]
1524 #[inline(always)]
1525 pub fn is_0(&self) -> bool {
1526 *self == SYNCEN2_A::_0
1527 }
1528 #[doc = "Checks if the value of the field is `_1`"]
1529 #[inline(always)]
1530 pub fn is_1(&self) -> bool {
1531 *self == SYNCEN2_A::_1
1532 }
1533}
1534#[doc = "Write proxy for field `SYNCEN2`"]
1535pub struct SYNCEN2_W<'a> {
1536 w: &'a mut W,
1537}
1538impl<'a> SYNCEN2_W<'a> {
1539 #[doc = r"Writes `variant` to the field"]
1540 #[inline(always)]
1541 pub fn variant(self, variant: SYNCEN2_A) -> &'a mut W {
1542 {
1543 self.bit(variant.into())
1544 }
1545 }
1546 #[doc = "The PWM synchronization in this pair of channels is disabled."]
1547 #[inline(always)]
1548 pub fn _0(self) -> &'a mut W {
1549 self.variant(SYNCEN2_A::_0)
1550 }
1551 #[doc = "The PWM synchronization in this pair of channels is enabled."]
1552 #[inline(always)]
1553 pub fn _1(self) -> &'a mut W {
1554 self.variant(SYNCEN2_A::_1)
1555 }
1556 #[doc = r"Sets the field bit"]
1557 #[inline(always)]
1558 pub fn set_bit(self) -> &'a mut W {
1559 self.bit(true)
1560 }
1561 #[doc = r"Clears the field bit"]
1562 #[inline(always)]
1563 pub fn clear_bit(self) -> &'a mut W {
1564 self.bit(false)
1565 }
1566 #[doc = r"Writes raw bits to the field"]
1567 #[inline(always)]
1568 pub fn bit(self, value: bool) -> &'a mut W {
1569 self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
1570 self.w
1571 }
1572}
1573#[doc = "Fault Control Enable For n = 4\n\nValue on reset: 0"]
1574#[derive(Clone, Copy, Debug, PartialEq)]
1575pub enum FAULTEN2_A {
1576 #[doc = "0: The fault control in this pair of channels is disabled."]
1577 _0,
1578 #[doc = "1: The fault control in this pair of channels is enabled."]
1579 _1,
1580}
1581impl From<FAULTEN2_A> for bool {
1582 #[inline(always)]
1583 fn from(variant: FAULTEN2_A) -> Self {
1584 match variant {
1585 FAULTEN2_A::_0 => false,
1586 FAULTEN2_A::_1 => true,
1587 }
1588 }
1589}
1590#[doc = "Reader of field `FAULTEN2`"]
1591pub type FAULTEN2_R = crate::R<bool, FAULTEN2_A>;
1592impl FAULTEN2_R {
1593 #[doc = r"Get enumerated values variant"]
1594 #[inline(always)]
1595 pub fn variant(&self) -> FAULTEN2_A {
1596 match self.bits {
1597 false => FAULTEN2_A::_0,
1598 true => FAULTEN2_A::_1,
1599 }
1600 }
1601 #[doc = "Checks if the value of the field is `_0`"]
1602 #[inline(always)]
1603 pub fn is_0(&self) -> bool {
1604 *self == FAULTEN2_A::_0
1605 }
1606 #[doc = "Checks if the value of the field is `_1`"]
1607 #[inline(always)]
1608 pub fn is_1(&self) -> bool {
1609 *self == FAULTEN2_A::_1
1610 }
1611}
1612#[doc = "Write proxy for field `FAULTEN2`"]
1613pub struct FAULTEN2_W<'a> {
1614 w: &'a mut W,
1615}
1616impl<'a> FAULTEN2_W<'a> {
1617 #[doc = r"Writes `variant` to the field"]
1618 #[inline(always)]
1619 pub fn variant(self, variant: FAULTEN2_A) -> &'a mut W {
1620 {
1621 self.bit(variant.into())
1622 }
1623 }
1624 #[doc = "The fault control in this pair of channels is disabled."]
1625 #[inline(always)]
1626 pub fn _0(self) -> &'a mut W {
1627 self.variant(FAULTEN2_A::_0)
1628 }
1629 #[doc = "The fault control in this pair of channels is enabled."]
1630 #[inline(always)]
1631 pub fn _1(self) -> &'a mut W {
1632 self.variant(FAULTEN2_A::_1)
1633 }
1634 #[doc = r"Sets the field bit"]
1635 #[inline(always)]
1636 pub fn set_bit(self) -> &'a mut W {
1637 self.bit(true)
1638 }
1639 #[doc = r"Clears the field bit"]
1640 #[inline(always)]
1641 pub fn clear_bit(self) -> &'a mut W {
1642 self.bit(false)
1643 }
1644 #[doc = r"Writes raw bits to the field"]
1645 #[inline(always)]
1646 pub fn bit(self, value: bool) -> &'a mut W {
1647 self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
1648 self.w
1649 }
1650}
1651#[doc = "Combine Channels For n = 6\n\nValue on reset: 0"]
1652#[derive(Clone, Copy, Debug, PartialEq)]
1653pub enum COMBINE3_A {
1654 #[doc = "0: Channels (n) and (n+1) are independent."]
1655 _0,
1656 #[doc = "1: Channels (n) and (n+1) are combined."]
1657 _1,
1658}
1659impl From<COMBINE3_A> for bool {
1660 #[inline(always)]
1661 fn from(variant: COMBINE3_A) -> Self {
1662 match variant {
1663 COMBINE3_A::_0 => false,
1664 COMBINE3_A::_1 => true,
1665 }
1666 }
1667}
1668#[doc = "Reader of field `COMBINE3`"]
1669pub type COMBINE3_R = crate::R<bool, COMBINE3_A>;
1670impl COMBINE3_R {
1671 #[doc = r"Get enumerated values variant"]
1672 #[inline(always)]
1673 pub fn variant(&self) -> COMBINE3_A {
1674 match self.bits {
1675 false => COMBINE3_A::_0,
1676 true => COMBINE3_A::_1,
1677 }
1678 }
1679 #[doc = "Checks if the value of the field is `_0`"]
1680 #[inline(always)]
1681 pub fn is_0(&self) -> bool {
1682 *self == COMBINE3_A::_0
1683 }
1684 #[doc = "Checks if the value of the field is `_1`"]
1685 #[inline(always)]
1686 pub fn is_1(&self) -> bool {
1687 *self == COMBINE3_A::_1
1688 }
1689}
1690#[doc = "Write proxy for field `COMBINE3`"]
1691pub struct COMBINE3_W<'a> {
1692 w: &'a mut W,
1693}
1694impl<'a> COMBINE3_W<'a> {
1695 #[doc = r"Writes `variant` to the field"]
1696 #[inline(always)]
1697 pub fn variant(self, variant: COMBINE3_A) -> &'a mut W {
1698 {
1699 self.bit(variant.into())
1700 }
1701 }
1702 #[doc = "Channels (n) and (n+1) are independent."]
1703 #[inline(always)]
1704 pub fn _0(self) -> &'a mut W {
1705 self.variant(COMBINE3_A::_0)
1706 }
1707 #[doc = "Channels (n) and (n+1) are combined."]
1708 #[inline(always)]
1709 pub fn _1(self) -> &'a mut W {
1710 self.variant(COMBINE3_A::_1)
1711 }
1712 #[doc = r"Sets the field bit"]
1713 #[inline(always)]
1714 pub fn set_bit(self) -> &'a mut W {
1715 self.bit(true)
1716 }
1717 #[doc = r"Clears the field bit"]
1718 #[inline(always)]
1719 pub fn clear_bit(self) -> &'a mut W {
1720 self.bit(false)
1721 }
1722 #[doc = r"Writes raw bits to the field"]
1723 #[inline(always)]
1724 pub fn bit(self, value: bool) -> &'a mut W {
1725 self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
1726 self.w
1727 }
1728}
1729#[doc = "Complement Of Channel (n) for n = 6\n\nValue on reset: 0"]
1730#[derive(Clone, Copy, Debug, PartialEq)]
1731pub enum COMP3_A {
1732 #[doc = "0: The channel (n+1) output is the same as the channel (n) output."]
1733 _0,
1734 #[doc = "1: The channel (n+1) output is the complement of the channel (n) output."]
1735 _1,
1736}
1737impl From<COMP3_A> for bool {
1738 #[inline(always)]
1739 fn from(variant: COMP3_A) -> Self {
1740 match variant {
1741 COMP3_A::_0 => false,
1742 COMP3_A::_1 => true,
1743 }
1744 }
1745}
1746#[doc = "Reader of field `COMP3`"]
1747pub type COMP3_R = crate::R<bool, COMP3_A>;
1748impl COMP3_R {
1749 #[doc = r"Get enumerated values variant"]
1750 #[inline(always)]
1751 pub fn variant(&self) -> COMP3_A {
1752 match self.bits {
1753 false => COMP3_A::_0,
1754 true => COMP3_A::_1,
1755 }
1756 }
1757 #[doc = "Checks if the value of the field is `_0`"]
1758 #[inline(always)]
1759 pub fn is_0(&self) -> bool {
1760 *self == COMP3_A::_0
1761 }
1762 #[doc = "Checks if the value of the field is `_1`"]
1763 #[inline(always)]
1764 pub fn is_1(&self) -> bool {
1765 *self == COMP3_A::_1
1766 }
1767}
1768#[doc = "Write proxy for field `COMP3`"]
1769pub struct COMP3_W<'a> {
1770 w: &'a mut W,
1771}
1772impl<'a> COMP3_W<'a> {
1773 #[doc = r"Writes `variant` to the field"]
1774 #[inline(always)]
1775 pub fn variant(self, variant: COMP3_A) -> &'a mut W {
1776 {
1777 self.bit(variant.into())
1778 }
1779 }
1780 #[doc = "The channel (n+1) output is the same as the channel (n) output."]
1781 #[inline(always)]
1782 pub fn _0(self) -> &'a mut W {
1783 self.variant(COMP3_A::_0)
1784 }
1785 #[doc = "The channel (n+1) output is the complement of the channel (n) output."]
1786 #[inline(always)]
1787 pub fn _1(self) -> &'a mut W {
1788 self.variant(COMP3_A::_1)
1789 }
1790 #[doc = r"Sets the field bit"]
1791 #[inline(always)]
1792 pub fn set_bit(self) -> &'a mut W {
1793 self.bit(true)
1794 }
1795 #[doc = r"Clears the field bit"]
1796 #[inline(always)]
1797 pub fn clear_bit(self) -> &'a mut W {
1798 self.bit(false)
1799 }
1800 #[doc = r"Writes raw bits to the field"]
1801 #[inline(always)]
1802 pub fn bit(self, value: bool) -> &'a mut W {
1803 self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
1804 self.w
1805 }
1806}
1807#[doc = "Dual Edge Capture Mode Enable For n = 6\n\nValue on reset: 0"]
1808#[derive(Clone, Copy, Debug, PartialEq)]
1809pub enum DECAPEN3_A {
1810 #[doc = "0: The Dual Edge Capture mode in this pair of channels is disabled."]
1811 _0,
1812 #[doc = "1: The Dual Edge Capture mode in this pair of channels is enabled."]
1813 _1,
1814}
1815impl From<DECAPEN3_A> for bool {
1816 #[inline(always)]
1817 fn from(variant: DECAPEN3_A) -> Self {
1818 match variant {
1819 DECAPEN3_A::_0 => false,
1820 DECAPEN3_A::_1 => true,
1821 }
1822 }
1823}
1824#[doc = "Reader of field `DECAPEN3`"]
1825pub type DECAPEN3_R = crate::R<bool, DECAPEN3_A>;
1826impl DECAPEN3_R {
1827 #[doc = r"Get enumerated values variant"]
1828 #[inline(always)]
1829 pub fn variant(&self) -> DECAPEN3_A {
1830 match self.bits {
1831 false => DECAPEN3_A::_0,
1832 true => DECAPEN3_A::_1,
1833 }
1834 }
1835 #[doc = "Checks if the value of the field is `_0`"]
1836 #[inline(always)]
1837 pub fn is_0(&self) -> bool {
1838 *self == DECAPEN3_A::_0
1839 }
1840 #[doc = "Checks if the value of the field is `_1`"]
1841 #[inline(always)]
1842 pub fn is_1(&self) -> bool {
1843 *self == DECAPEN3_A::_1
1844 }
1845}
1846#[doc = "Write proxy for field `DECAPEN3`"]
1847pub struct DECAPEN3_W<'a> {
1848 w: &'a mut W,
1849}
1850impl<'a> DECAPEN3_W<'a> {
1851 #[doc = r"Writes `variant` to the field"]
1852 #[inline(always)]
1853 pub fn variant(self, variant: DECAPEN3_A) -> &'a mut W {
1854 {
1855 self.bit(variant.into())
1856 }
1857 }
1858 #[doc = "The Dual Edge Capture mode in this pair of channels is disabled."]
1859 #[inline(always)]
1860 pub fn _0(self) -> &'a mut W {
1861 self.variant(DECAPEN3_A::_0)
1862 }
1863 #[doc = "The Dual Edge Capture mode in this pair of channels is enabled."]
1864 #[inline(always)]
1865 pub fn _1(self) -> &'a mut W {
1866 self.variant(DECAPEN3_A::_1)
1867 }
1868 #[doc = r"Sets the field bit"]
1869 #[inline(always)]
1870 pub fn set_bit(self) -> &'a mut W {
1871 self.bit(true)
1872 }
1873 #[doc = r"Clears the field bit"]
1874 #[inline(always)]
1875 pub fn clear_bit(self) -> &'a mut W {
1876 self.bit(false)
1877 }
1878 #[doc = r"Writes raw bits to the field"]
1879 #[inline(always)]
1880 pub fn bit(self, value: bool) -> &'a mut W {
1881 self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
1882 self.w
1883 }
1884}
1885#[doc = "Dual Edge Capture Mode Captures For n = 6\n\nValue on reset: 0"]
1886#[derive(Clone, Copy, Debug, PartialEq)]
1887pub enum DECAP3_A {
1888 #[doc = "0: The dual edge captures are inactive."]
1889 _0,
1890 #[doc = "1: The dual edge captures are active."]
1891 _1,
1892}
1893impl From<DECAP3_A> for bool {
1894 #[inline(always)]
1895 fn from(variant: DECAP3_A) -> Self {
1896 match variant {
1897 DECAP3_A::_0 => false,
1898 DECAP3_A::_1 => true,
1899 }
1900 }
1901}
1902#[doc = "Reader of field `DECAP3`"]
1903pub type DECAP3_R = crate::R<bool, DECAP3_A>;
1904impl DECAP3_R {
1905 #[doc = r"Get enumerated values variant"]
1906 #[inline(always)]
1907 pub fn variant(&self) -> DECAP3_A {
1908 match self.bits {
1909 false => DECAP3_A::_0,
1910 true => DECAP3_A::_1,
1911 }
1912 }
1913 #[doc = "Checks if the value of the field is `_0`"]
1914 #[inline(always)]
1915 pub fn is_0(&self) -> bool {
1916 *self == DECAP3_A::_0
1917 }
1918 #[doc = "Checks if the value of the field is `_1`"]
1919 #[inline(always)]
1920 pub fn is_1(&self) -> bool {
1921 *self == DECAP3_A::_1
1922 }
1923}
1924#[doc = "Write proxy for field `DECAP3`"]
1925pub struct DECAP3_W<'a> {
1926 w: &'a mut W,
1927}
1928impl<'a> DECAP3_W<'a> {
1929 #[doc = r"Writes `variant` to the field"]
1930 #[inline(always)]
1931 pub fn variant(self, variant: DECAP3_A) -> &'a mut W {
1932 {
1933 self.bit(variant.into())
1934 }
1935 }
1936 #[doc = "The dual edge captures are inactive."]
1937 #[inline(always)]
1938 pub fn _0(self) -> &'a mut W {
1939 self.variant(DECAP3_A::_0)
1940 }
1941 #[doc = "The dual edge captures are active."]
1942 #[inline(always)]
1943 pub fn _1(self) -> &'a mut W {
1944 self.variant(DECAP3_A::_1)
1945 }
1946 #[doc = r"Sets the field bit"]
1947 #[inline(always)]
1948 pub fn set_bit(self) -> &'a mut W {
1949 self.bit(true)
1950 }
1951 #[doc = r"Clears the field bit"]
1952 #[inline(always)]
1953 pub fn clear_bit(self) -> &'a mut W {
1954 self.bit(false)
1955 }
1956 #[doc = r"Writes raw bits to the field"]
1957 #[inline(always)]
1958 pub fn bit(self, value: bool) -> &'a mut W {
1959 self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
1960 self.w
1961 }
1962}
1963#[doc = "Deadtime Enable For n = 6\n\nValue on reset: 0"]
1964#[derive(Clone, Copy, Debug, PartialEq)]
1965pub enum DTEN3_A {
1966 #[doc = "0: The deadtime insertion in this pair of channels is disabled."]
1967 _0,
1968 #[doc = "1: The deadtime insertion in this pair of channels is enabled."]
1969 _1,
1970}
1971impl From<DTEN3_A> for bool {
1972 #[inline(always)]
1973 fn from(variant: DTEN3_A) -> Self {
1974 match variant {
1975 DTEN3_A::_0 => false,
1976 DTEN3_A::_1 => true,
1977 }
1978 }
1979}
1980#[doc = "Reader of field `DTEN3`"]
1981pub type DTEN3_R = crate::R<bool, DTEN3_A>;
1982impl DTEN3_R {
1983 #[doc = r"Get enumerated values variant"]
1984 #[inline(always)]
1985 pub fn variant(&self) -> DTEN3_A {
1986 match self.bits {
1987 false => DTEN3_A::_0,
1988 true => DTEN3_A::_1,
1989 }
1990 }
1991 #[doc = "Checks if the value of the field is `_0`"]
1992 #[inline(always)]
1993 pub fn is_0(&self) -> bool {
1994 *self == DTEN3_A::_0
1995 }
1996 #[doc = "Checks if the value of the field is `_1`"]
1997 #[inline(always)]
1998 pub fn is_1(&self) -> bool {
1999 *self == DTEN3_A::_1
2000 }
2001}
2002#[doc = "Write proxy for field `DTEN3`"]
2003pub struct DTEN3_W<'a> {
2004 w: &'a mut W,
2005}
2006impl<'a> DTEN3_W<'a> {
2007 #[doc = r"Writes `variant` to the field"]
2008 #[inline(always)]
2009 pub fn variant(self, variant: DTEN3_A) -> &'a mut W {
2010 {
2011 self.bit(variant.into())
2012 }
2013 }
2014 #[doc = "The deadtime insertion in this pair of channels is disabled."]
2015 #[inline(always)]
2016 pub fn _0(self) -> &'a mut W {
2017 self.variant(DTEN3_A::_0)
2018 }
2019 #[doc = "The deadtime insertion in this pair of channels is enabled."]
2020 #[inline(always)]
2021 pub fn _1(self) -> &'a mut W {
2022 self.variant(DTEN3_A::_1)
2023 }
2024 #[doc = r"Sets the field bit"]
2025 #[inline(always)]
2026 pub fn set_bit(self) -> &'a mut W {
2027 self.bit(true)
2028 }
2029 #[doc = r"Clears the field bit"]
2030 #[inline(always)]
2031 pub fn clear_bit(self) -> &'a mut W {
2032 self.bit(false)
2033 }
2034 #[doc = r"Writes raw bits to the field"]
2035 #[inline(always)]
2036 pub fn bit(self, value: bool) -> &'a mut W {
2037 self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
2038 self.w
2039 }
2040}
2041#[doc = "Synchronization Enable For n = 6\n\nValue on reset: 0"]
2042#[derive(Clone, Copy, Debug, PartialEq)]
2043pub enum SYNCEN3_A {
2044 #[doc = "0: The PWM synchronization in this pair of channels is disabled."]
2045 _0,
2046 #[doc = "1: The PWM synchronization in this pair of channels is enabled."]
2047 _1,
2048}
2049impl From<SYNCEN3_A> for bool {
2050 #[inline(always)]
2051 fn from(variant: SYNCEN3_A) -> Self {
2052 match variant {
2053 SYNCEN3_A::_0 => false,
2054 SYNCEN3_A::_1 => true,
2055 }
2056 }
2057}
2058#[doc = "Reader of field `SYNCEN3`"]
2059pub type SYNCEN3_R = crate::R<bool, SYNCEN3_A>;
2060impl SYNCEN3_R {
2061 #[doc = r"Get enumerated values variant"]
2062 #[inline(always)]
2063 pub fn variant(&self) -> SYNCEN3_A {
2064 match self.bits {
2065 false => SYNCEN3_A::_0,
2066 true => SYNCEN3_A::_1,
2067 }
2068 }
2069 #[doc = "Checks if the value of the field is `_0`"]
2070 #[inline(always)]
2071 pub fn is_0(&self) -> bool {
2072 *self == SYNCEN3_A::_0
2073 }
2074 #[doc = "Checks if the value of the field is `_1`"]
2075 #[inline(always)]
2076 pub fn is_1(&self) -> bool {
2077 *self == SYNCEN3_A::_1
2078 }
2079}
2080#[doc = "Write proxy for field `SYNCEN3`"]
2081pub struct SYNCEN3_W<'a> {
2082 w: &'a mut W,
2083}
2084impl<'a> SYNCEN3_W<'a> {
2085 #[doc = r"Writes `variant` to the field"]
2086 #[inline(always)]
2087 pub fn variant(self, variant: SYNCEN3_A) -> &'a mut W {
2088 {
2089 self.bit(variant.into())
2090 }
2091 }
2092 #[doc = "The PWM synchronization in this pair of channels is disabled."]
2093 #[inline(always)]
2094 pub fn _0(self) -> &'a mut W {
2095 self.variant(SYNCEN3_A::_0)
2096 }
2097 #[doc = "The PWM synchronization in this pair of channels is enabled."]
2098 #[inline(always)]
2099 pub fn _1(self) -> &'a mut W {
2100 self.variant(SYNCEN3_A::_1)
2101 }
2102 #[doc = r"Sets the field bit"]
2103 #[inline(always)]
2104 pub fn set_bit(self) -> &'a mut W {
2105 self.bit(true)
2106 }
2107 #[doc = r"Clears the field bit"]
2108 #[inline(always)]
2109 pub fn clear_bit(self) -> &'a mut W {
2110 self.bit(false)
2111 }
2112 #[doc = r"Writes raw bits to the field"]
2113 #[inline(always)]
2114 pub fn bit(self, value: bool) -> &'a mut W {
2115 self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
2116 self.w
2117 }
2118}
2119#[doc = "Fault Control Enable For n = 6\n\nValue on reset: 0"]
2120#[derive(Clone, Copy, Debug, PartialEq)]
2121pub enum FAULTEN3_A {
2122 #[doc = "0: The fault control in this pair of channels is disabled."]
2123 _0,
2124 #[doc = "1: The fault control in this pair of channels is enabled."]
2125 _1,
2126}
2127impl From<FAULTEN3_A> for bool {
2128 #[inline(always)]
2129 fn from(variant: FAULTEN3_A) -> Self {
2130 match variant {
2131 FAULTEN3_A::_0 => false,
2132 FAULTEN3_A::_1 => true,
2133 }
2134 }
2135}
2136#[doc = "Reader of field `FAULTEN3`"]
2137pub type FAULTEN3_R = crate::R<bool, FAULTEN3_A>;
2138impl FAULTEN3_R {
2139 #[doc = r"Get enumerated values variant"]
2140 #[inline(always)]
2141 pub fn variant(&self) -> FAULTEN3_A {
2142 match self.bits {
2143 false => FAULTEN3_A::_0,
2144 true => FAULTEN3_A::_1,
2145 }
2146 }
2147 #[doc = "Checks if the value of the field is `_0`"]
2148 #[inline(always)]
2149 pub fn is_0(&self) -> bool {
2150 *self == FAULTEN3_A::_0
2151 }
2152 #[doc = "Checks if the value of the field is `_1`"]
2153 #[inline(always)]
2154 pub fn is_1(&self) -> bool {
2155 *self == FAULTEN3_A::_1
2156 }
2157}
2158#[doc = "Write proxy for field `FAULTEN3`"]
2159pub struct FAULTEN3_W<'a> {
2160 w: &'a mut W,
2161}
2162impl<'a> FAULTEN3_W<'a> {
2163 #[doc = r"Writes `variant` to the field"]
2164 #[inline(always)]
2165 pub fn variant(self, variant: FAULTEN3_A) -> &'a mut W {
2166 {
2167 self.bit(variant.into())
2168 }
2169 }
2170 #[doc = "The fault control in this pair of channels is disabled."]
2171 #[inline(always)]
2172 pub fn _0(self) -> &'a mut W {
2173 self.variant(FAULTEN3_A::_0)
2174 }
2175 #[doc = "The fault control in this pair of channels is enabled."]
2176 #[inline(always)]
2177 pub fn _1(self) -> &'a mut W {
2178 self.variant(FAULTEN3_A::_1)
2179 }
2180 #[doc = r"Sets the field bit"]
2181 #[inline(always)]
2182 pub fn set_bit(self) -> &'a mut W {
2183 self.bit(true)
2184 }
2185 #[doc = r"Clears the field bit"]
2186 #[inline(always)]
2187 pub fn clear_bit(self) -> &'a mut W {
2188 self.bit(false)
2189 }
2190 #[doc = r"Writes raw bits to the field"]
2191 #[inline(always)]
2192 pub fn bit(self, value: bool) -> &'a mut W {
2193 self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
2194 self.w
2195 }
2196}
2197impl R {
2198 #[doc = "Bit 0 - Combine Channels For n = 0"]
2199 #[inline(always)]
2200 pub fn combine0(&self) -> COMBINE0_R {
2201 COMBINE0_R::new((self.bits & 0x01) != 0)
2202 }
2203 #[doc = "Bit 1 - Complement Of Channel (n) For n = 0"]
2204 #[inline(always)]
2205 pub fn comp0(&self) -> COMP0_R {
2206 COMP0_R::new(((self.bits >> 1) & 0x01) != 0)
2207 }
2208 #[doc = "Bit 2 - Dual Edge Capture Mode Enable For n = 0"]
2209 #[inline(always)]
2210 pub fn decapen0(&self) -> DECAPEN0_R {
2211 DECAPEN0_R::new(((self.bits >> 2) & 0x01) != 0)
2212 }
2213 #[doc = "Bit 3 - Dual Edge Capture Mode Captures For n = 0"]
2214 #[inline(always)]
2215 pub fn decap0(&self) -> DECAP0_R {
2216 DECAP0_R::new(((self.bits >> 3) & 0x01) != 0)
2217 }
2218 #[doc = "Bit 4 - Deadtime Enable For n = 0"]
2219 #[inline(always)]
2220 pub fn dten0(&self) -> DTEN0_R {
2221 DTEN0_R::new(((self.bits >> 4) & 0x01) != 0)
2222 }
2223 #[doc = "Bit 5 - Synchronization Enable For n = 0"]
2224 #[inline(always)]
2225 pub fn syncen0(&self) -> SYNCEN0_R {
2226 SYNCEN0_R::new(((self.bits >> 5) & 0x01) != 0)
2227 }
2228 #[doc = "Bit 6 - Fault Control Enable For n = 0"]
2229 #[inline(always)]
2230 pub fn faulten0(&self) -> FAULTEN0_R {
2231 FAULTEN0_R::new(((self.bits >> 6) & 0x01) != 0)
2232 }
2233 #[doc = "Bit 8 - Combine Channels For n = 2"]
2234 #[inline(always)]
2235 pub fn combine1(&self) -> COMBINE1_R {
2236 COMBINE1_R::new(((self.bits >> 8) & 0x01) != 0)
2237 }
2238 #[doc = "Bit 9 - Complement Of Channel (n) For n = 2"]
2239 #[inline(always)]
2240 pub fn comp1(&self) -> COMP1_R {
2241 COMP1_R::new(((self.bits >> 9) & 0x01) != 0)
2242 }
2243 #[doc = "Bit 10 - Dual Edge Capture Mode Enable For n = 2"]
2244 #[inline(always)]
2245 pub fn decapen1(&self) -> DECAPEN1_R {
2246 DECAPEN1_R::new(((self.bits >> 10) & 0x01) != 0)
2247 }
2248 #[doc = "Bit 11 - Dual Edge Capture Mode Captures For n = 2"]
2249 #[inline(always)]
2250 pub fn decap1(&self) -> DECAP1_R {
2251 DECAP1_R::new(((self.bits >> 11) & 0x01) != 0)
2252 }
2253 #[doc = "Bit 12 - Deadtime Enable For n = 2"]
2254 #[inline(always)]
2255 pub fn dten1(&self) -> DTEN1_R {
2256 DTEN1_R::new(((self.bits >> 12) & 0x01) != 0)
2257 }
2258 #[doc = "Bit 13 - Synchronization Enable For n = 2"]
2259 #[inline(always)]
2260 pub fn syncen1(&self) -> SYNCEN1_R {
2261 SYNCEN1_R::new(((self.bits >> 13) & 0x01) != 0)
2262 }
2263 #[doc = "Bit 14 - Fault Control Enable For n = 2"]
2264 #[inline(always)]
2265 pub fn faulten1(&self) -> FAULTEN1_R {
2266 FAULTEN1_R::new(((self.bits >> 14) & 0x01) != 0)
2267 }
2268 #[doc = "Bit 16 - Combine Channels For n = 4"]
2269 #[inline(always)]
2270 pub fn combine2(&self) -> COMBINE2_R {
2271 COMBINE2_R::new(((self.bits >> 16) & 0x01) != 0)
2272 }
2273 #[doc = "Bit 17 - Complement Of Channel (n) For n = 4"]
2274 #[inline(always)]
2275 pub fn comp2(&self) -> COMP2_R {
2276 COMP2_R::new(((self.bits >> 17) & 0x01) != 0)
2277 }
2278 #[doc = "Bit 18 - Dual Edge Capture Mode Enable For n = 4"]
2279 #[inline(always)]
2280 pub fn decapen2(&self) -> DECAPEN2_R {
2281 DECAPEN2_R::new(((self.bits >> 18) & 0x01) != 0)
2282 }
2283 #[doc = "Bit 19 - Dual Edge Capture Mode Captures For n = 4"]
2284 #[inline(always)]
2285 pub fn decap2(&self) -> DECAP2_R {
2286 DECAP2_R::new(((self.bits >> 19) & 0x01) != 0)
2287 }
2288 #[doc = "Bit 20 - Deadtime Enable For n = 4"]
2289 #[inline(always)]
2290 pub fn dten2(&self) -> DTEN2_R {
2291 DTEN2_R::new(((self.bits >> 20) & 0x01) != 0)
2292 }
2293 #[doc = "Bit 21 - Synchronization Enable For n = 4"]
2294 #[inline(always)]
2295 pub fn syncen2(&self) -> SYNCEN2_R {
2296 SYNCEN2_R::new(((self.bits >> 21) & 0x01) != 0)
2297 }
2298 #[doc = "Bit 22 - Fault Control Enable For n = 4"]
2299 #[inline(always)]
2300 pub fn faulten2(&self) -> FAULTEN2_R {
2301 FAULTEN2_R::new(((self.bits >> 22) & 0x01) != 0)
2302 }
2303 #[doc = "Bit 24 - Combine Channels For n = 6"]
2304 #[inline(always)]
2305 pub fn combine3(&self) -> COMBINE3_R {
2306 COMBINE3_R::new(((self.bits >> 24) & 0x01) != 0)
2307 }
2308 #[doc = "Bit 25 - Complement Of Channel (n) for n = 6"]
2309 #[inline(always)]
2310 pub fn comp3(&self) -> COMP3_R {
2311 COMP3_R::new(((self.bits >> 25) & 0x01) != 0)
2312 }
2313 #[doc = "Bit 26 - Dual Edge Capture Mode Enable For n = 6"]
2314 #[inline(always)]
2315 pub fn decapen3(&self) -> DECAPEN3_R {
2316 DECAPEN3_R::new(((self.bits >> 26) & 0x01) != 0)
2317 }
2318 #[doc = "Bit 27 - Dual Edge Capture Mode Captures For n = 6"]
2319 #[inline(always)]
2320 pub fn decap3(&self) -> DECAP3_R {
2321 DECAP3_R::new(((self.bits >> 27) & 0x01) != 0)
2322 }
2323 #[doc = "Bit 28 - Deadtime Enable For n = 6"]
2324 #[inline(always)]
2325 pub fn dten3(&self) -> DTEN3_R {
2326 DTEN3_R::new(((self.bits >> 28) & 0x01) != 0)
2327 }
2328 #[doc = "Bit 29 - Synchronization Enable For n = 6"]
2329 #[inline(always)]
2330 pub fn syncen3(&self) -> SYNCEN3_R {
2331 SYNCEN3_R::new(((self.bits >> 29) & 0x01) != 0)
2332 }
2333 #[doc = "Bit 30 - Fault Control Enable For n = 6"]
2334 #[inline(always)]
2335 pub fn faulten3(&self) -> FAULTEN3_R {
2336 FAULTEN3_R::new(((self.bits >> 30) & 0x01) != 0)
2337 }
2338}
2339impl W {
2340 #[doc = "Bit 0 - Combine Channels For n = 0"]
2341 #[inline(always)]
2342 pub fn combine0(&mut self) -> COMBINE0_W {
2343 COMBINE0_W { w: self }
2344 }
2345 #[doc = "Bit 1 - Complement Of Channel (n) For n = 0"]
2346 #[inline(always)]
2347 pub fn comp0(&mut self) -> COMP0_W {
2348 COMP0_W { w: self }
2349 }
2350 #[doc = "Bit 2 - Dual Edge Capture Mode Enable For n = 0"]
2351 #[inline(always)]
2352 pub fn decapen0(&mut self) -> DECAPEN0_W {
2353 DECAPEN0_W { w: self }
2354 }
2355 #[doc = "Bit 3 - Dual Edge Capture Mode Captures For n = 0"]
2356 #[inline(always)]
2357 pub fn decap0(&mut self) -> DECAP0_W {
2358 DECAP0_W { w: self }
2359 }
2360 #[doc = "Bit 4 - Deadtime Enable For n = 0"]
2361 #[inline(always)]
2362 pub fn dten0(&mut self) -> DTEN0_W {
2363 DTEN0_W { w: self }
2364 }
2365 #[doc = "Bit 5 - Synchronization Enable For n = 0"]
2366 #[inline(always)]
2367 pub fn syncen0(&mut self) -> SYNCEN0_W {
2368 SYNCEN0_W { w: self }
2369 }
2370 #[doc = "Bit 6 - Fault Control Enable For n = 0"]
2371 #[inline(always)]
2372 pub fn faulten0(&mut self) -> FAULTEN0_W {
2373 FAULTEN0_W { w: self }
2374 }
2375 #[doc = "Bit 8 - Combine Channels For n = 2"]
2376 #[inline(always)]
2377 pub fn combine1(&mut self) -> COMBINE1_W {
2378 COMBINE1_W { w: self }
2379 }
2380 #[doc = "Bit 9 - Complement Of Channel (n) For n = 2"]
2381 #[inline(always)]
2382 pub fn comp1(&mut self) -> COMP1_W {
2383 COMP1_W { w: self }
2384 }
2385 #[doc = "Bit 10 - Dual Edge Capture Mode Enable For n = 2"]
2386 #[inline(always)]
2387 pub fn decapen1(&mut self) -> DECAPEN1_W {
2388 DECAPEN1_W { w: self }
2389 }
2390 #[doc = "Bit 11 - Dual Edge Capture Mode Captures For n = 2"]
2391 #[inline(always)]
2392 pub fn decap1(&mut self) -> DECAP1_W {
2393 DECAP1_W { w: self }
2394 }
2395 #[doc = "Bit 12 - Deadtime Enable For n = 2"]
2396 #[inline(always)]
2397 pub fn dten1(&mut self) -> DTEN1_W {
2398 DTEN1_W { w: self }
2399 }
2400 #[doc = "Bit 13 - Synchronization Enable For n = 2"]
2401 #[inline(always)]
2402 pub fn syncen1(&mut self) -> SYNCEN1_W {
2403 SYNCEN1_W { w: self }
2404 }
2405 #[doc = "Bit 14 - Fault Control Enable For n = 2"]
2406 #[inline(always)]
2407 pub fn faulten1(&mut self) -> FAULTEN1_W {
2408 FAULTEN1_W { w: self }
2409 }
2410 #[doc = "Bit 16 - Combine Channels For n = 4"]
2411 #[inline(always)]
2412 pub fn combine2(&mut self) -> COMBINE2_W {
2413 COMBINE2_W { w: self }
2414 }
2415 #[doc = "Bit 17 - Complement Of Channel (n) For n = 4"]
2416 #[inline(always)]
2417 pub fn comp2(&mut self) -> COMP2_W {
2418 COMP2_W { w: self }
2419 }
2420 #[doc = "Bit 18 - Dual Edge Capture Mode Enable For n = 4"]
2421 #[inline(always)]
2422 pub fn decapen2(&mut self) -> DECAPEN2_W {
2423 DECAPEN2_W { w: self }
2424 }
2425 #[doc = "Bit 19 - Dual Edge Capture Mode Captures For n = 4"]
2426 #[inline(always)]
2427 pub fn decap2(&mut self) -> DECAP2_W {
2428 DECAP2_W { w: self }
2429 }
2430 #[doc = "Bit 20 - Deadtime Enable For n = 4"]
2431 #[inline(always)]
2432 pub fn dten2(&mut self) -> DTEN2_W {
2433 DTEN2_W { w: self }
2434 }
2435 #[doc = "Bit 21 - Synchronization Enable For n = 4"]
2436 #[inline(always)]
2437 pub fn syncen2(&mut self) -> SYNCEN2_W {
2438 SYNCEN2_W { w: self }
2439 }
2440 #[doc = "Bit 22 - Fault Control Enable For n = 4"]
2441 #[inline(always)]
2442 pub fn faulten2(&mut self) -> FAULTEN2_W {
2443 FAULTEN2_W { w: self }
2444 }
2445 #[doc = "Bit 24 - Combine Channels For n = 6"]
2446 #[inline(always)]
2447 pub fn combine3(&mut self) -> COMBINE3_W {
2448 COMBINE3_W { w: self }
2449 }
2450 #[doc = "Bit 25 - Complement Of Channel (n) for n = 6"]
2451 #[inline(always)]
2452 pub fn comp3(&mut self) -> COMP3_W {
2453 COMP3_W { w: self }
2454 }
2455 #[doc = "Bit 26 - Dual Edge Capture Mode Enable For n = 6"]
2456 #[inline(always)]
2457 pub fn decapen3(&mut self) -> DECAPEN3_W {
2458 DECAPEN3_W { w: self }
2459 }
2460 #[doc = "Bit 27 - Dual Edge Capture Mode Captures For n = 6"]
2461 #[inline(always)]
2462 pub fn decap3(&mut self) -> DECAP3_W {
2463 DECAP3_W { w: self }
2464 }
2465 #[doc = "Bit 28 - Deadtime Enable For n = 6"]
2466 #[inline(always)]
2467 pub fn dten3(&mut self) -> DTEN3_W {
2468 DTEN3_W { w: self }
2469 }
2470 #[doc = "Bit 29 - Synchronization Enable For n = 6"]
2471 #[inline(always)]
2472 pub fn syncen3(&mut self) -> SYNCEN3_W {
2473 SYNCEN3_W { w: self }
2474 }
2475 #[doc = "Bit 30 - Fault Control Enable For n = 6"]
2476 #[inline(always)]
2477 pub fn faulten3(&mut self) -> FAULTEN3_W {
2478 FAULTEN3_W { w: self }
2479 }
2480}