1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u8,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u8,
8}
9impl super::C4 {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = r" Value of the field"]
46pub struct BRFAR {
47 bits: u8,
48}
49impl BRFAR {
50 #[doc = r" Value of the field as raw bits"]
51 #[inline]
52 pub fn bits(&self) -> u8 {
53 self.bits
54 }
55}
56#[doc = "Possible values of the field `M10`"]
57#[derive(Clone, Copy, Debug, PartialEq)]
58pub enum M10R {
59 #[doc = "The parity bit is the ninth bit in the serial transmission."]
60 _0,
61 #[doc = "The parity bit is the tenth bit in the serial transmission."]
62 _1,
63}
64impl M10R {
65 #[doc = r" Returns `true` if the bit is clear (0)"]
66 #[inline]
67 pub fn bit_is_clear(&self) -> bool {
68 !self.bit()
69 }
70 #[doc = r" Returns `true` if the bit is set (1)"]
71 #[inline]
72 pub fn bit_is_set(&self) -> bool {
73 self.bit()
74 }
75 #[doc = r" Value of the field as raw bits"]
76 #[inline]
77 pub fn bit(&self) -> bool {
78 match *self {
79 M10R::_0 => false,
80 M10R::_1 => true,
81 }
82 }
83 #[allow(missing_docs)]
84 #[doc(hidden)]
85 #[inline]
86 pub fn _from(value: bool) -> M10R {
87 match value {
88 false => M10R::_0,
89 true => M10R::_1,
90 }
91 }
92 #[doc = "Checks if the value of the field is `_0`"]
93 #[inline]
94 pub fn is_0(&self) -> bool {
95 *self == M10R::_0
96 }
97 #[doc = "Checks if the value of the field is `_1`"]
98 #[inline]
99 pub fn is_1(&self) -> bool {
100 *self == M10R::_1
101 }
102}
103#[doc = "Possible values of the field `MAEN2`"]
104#[derive(Clone, Copy, Debug, PartialEq)]
105pub enum MAEN2R {
106 #[doc = "All data received is transferred to the data buffer if MAEN1 is cleared."]
107 _0,
108 #[doc = "All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled."]
109 _1,
110}
111impl MAEN2R {
112 #[doc = r" Returns `true` if the bit is clear (0)"]
113 #[inline]
114 pub fn bit_is_clear(&self) -> bool {
115 !self.bit()
116 }
117 #[doc = r" Returns `true` if the bit is set (1)"]
118 #[inline]
119 pub fn bit_is_set(&self) -> bool {
120 self.bit()
121 }
122 #[doc = r" Value of the field as raw bits"]
123 #[inline]
124 pub fn bit(&self) -> bool {
125 match *self {
126 MAEN2R::_0 => false,
127 MAEN2R::_1 => true,
128 }
129 }
130 #[allow(missing_docs)]
131 #[doc(hidden)]
132 #[inline]
133 pub fn _from(value: bool) -> MAEN2R {
134 match value {
135 false => MAEN2R::_0,
136 true => MAEN2R::_1,
137 }
138 }
139 #[doc = "Checks if the value of the field is `_0`"]
140 #[inline]
141 pub fn is_0(&self) -> bool {
142 *self == MAEN2R::_0
143 }
144 #[doc = "Checks if the value of the field is `_1`"]
145 #[inline]
146 pub fn is_1(&self) -> bool {
147 *self == MAEN2R::_1
148 }
149}
150#[doc = "Possible values of the field `MAEN1`"]
151#[derive(Clone, Copy, Debug, PartialEq)]
152pub enum MAEN1R {
153 #[doc = "All data received is transferred to the data buffer if MAEN2 is cleared."]
154 _0,
155 #[doc = "All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled."]
156 _1,
157}
158impl MAEN1R {
159 #[doc = r" Returns `true` if the bit is clear (0)"]
160 #[inline]
161 pub fn bit_is_clear(&self) -> bool {
162 !self.bit()
163 }
164 #[doc = r" Returns `true` if the bit is set (1)"]
165 #[inline]
166 pub fn bit_is_set(&self) -> bool {
167 self.bit()
168 }
169 #[doc = r" Value of the field as raw bits"]
170 #[inline]
171 pub fn bit(&self) -> bool {
172 match *self {
173 MAEN1R::_0 => false,
174 MAEN1R::_1 => true,
175 }
176 }
177 #[allow(missing_docs)]
178 #[doc(hidden)]
179 #[inline]
180 pub fn _from(value: bool) -> MAEN1R {
181 match value {
182 false => MAEN1R::_0,
183 true => MAEN1R::_1,
184 }
185 }
186 #[doc = "Checks if the value of the field is `_0`"]
187 #[inline]
188 pub fn is_0(&self) -> bool {
189 *self == MAEN1R::_0
190 }
191 #[doc = "Checks if the value of the field is `_1`"]
192 #[inline]
193 pub fn is_1(&self) -> bool {
194 *self == MAEN1R::_1
195 }
196}
197#[doc = r" Proxy"]
198pub struct _BRFAW<'a> {
199 w: &'a mut W,
200}
201impl<'a> _BRFAW<'a> {
202 #[doc = r" Writes raw bits to the field"]
203 #[inline]
204 pub unsafe fn bits(self, value: u8) -> &'a mut W {
205 const MASK: u8 = 31;
206 const OFFSET: u8 = 0;
207 self.w.bits &= !((MASK as u8) << OFFSET);
208 self.w.bits |= ((value & MASK) as u8) << OFFSET;
209 self.w
210 }
211}
212#[doc = "Values that can be written to the field `M10`"]
213pub enum M10W {
214 #[doc = "The parity bit is the ninth bit in the serial transmission."]
215 _0,
216 #[doc = "The parity bit is the tenth bit in the serial transmission."]
217 _1,
218}
219impl M10W {
220 #[allow(missing_docs)]
221 #[doc(hidden)]
222 #[inline]
223 pub fn _bits(&self) -> bool {
224 match *self {
225 M10W::_0 => false,
226 M10W::_1 => true,
227 }
228 }
229}
230#[doc = r" Proxy"]
231pub struct _M10W<'a> {
232 w: &'a mut W,
233}
234impl<'a> _M10W<'a> {
235 #[doc = r" Writes `variant` to the field"]
236 #[inline]
237 pub fn variant(self, variant: M10W) -> &'a mut W {
238 {
239 self.bit(variant._bits())
240 }
241 }
242 #[doc = "The parity bit is the ninth bit in the serial transmission."]
243 #[inline]
244 pub fn _0(self) -> &'a mut W {
245 self.variant(M10W::_0)
246 }
247 #[doc = "The parity bit is the tenth bit in the serial transmission."]
248 #[inline]
249 pub fn _1(self) -> &'a mut W {
250 self.variant(M10W::_1)
251 }
252 #[doc = r" Sets the field bit"]
253 pub fn set_bit(self) -> &'a mut W {
254 self.bit(true)
255 }
256 #[doc = r" Clears the field bit"]
257 pub fn clear_bit(self) -> &'a mut W {
258 self.bit(false)
259 }
260 #[doc = r" Writes raw bits to the field"]
261 #[inline]
262 pub fn bit(self, value: bool) -> &'a mut W {
263 const MASK: bool = true;
264 const OFFSET: u8 = 5;
265 self.w.bits &= !((MASK as u8) << OFFSET);
266 self.w.bits |= ((value & MASK) as u8) << OFFSET;
267 self.w
268 }
269}
270#[doc = "Values that can be written to the field `MAEN2`"]
271pub enum MAEN2W {
272 #[doc = "All data received is transferred to the data buffer if MAEN1 is cleared."]
273 _0,
274 #[doc = "All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled."]
275 _1,
276}
277impl MAEN2W {
278 #[allow(missing_docs)]
279 #[doc(hidden)]
280 #[inline]
281 pub fn _bits(&self) -> bool {
282 match *self {
283 MAEN2W::_0 => false,
284 MAEN2W::_1 => true,
285 }
286 }
287}
288#[doc = r" Proxy"]
289pub struct _MAEN2W<'a> {
290 w: &'a mut W,
291}
292impl<'a> _MAEN2W<'a> {
293 #[doc = r" Writes `variant` to the field"]
294 #[inline]
295 pub fn variant(self, variant: MAEN2W) -> &'a mut W {
296 {
297 self.bit(variant._bits())
298 }
299 }
300 #[doc = "All data received is transferred to the data buffer if MAEN1 is cleared."]
301 #[inline]
302 pub fn _0(self) -> &'a mut W {
303 self.variant(MAEN2W::_0)
304 }
305 #[doc = "All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled."]
306 #[inline]
307 pub fn _1(self) -> &'a mut W {
308 self.variant(MAEN2W::_1)
309 }
310 #[doc = r" Sets the field bit"]
311 pub fn set_bit(self) -> &'a mut W {
312 self.bit(true)
313 }
314 #[doc = r" Clears the field bit"]
315 pub fn clear_bit(self) -> &'a mut W {
316 self.bit(false)
317 }
318 #[doc = r" Writes raw bits to the field"]
319 #[inline]
320 pub fn bit(self, value: bool) -> &'a mut W {
321 const MASK: bool = true;
322 const OFFSET: u8 = 6;
323 self.w.bits &= !((MASK as u8) << OFFSET);
324 self.w.bits |= ((value & MASK) as u8) << OFFSET;
325 self.w
326 }
327}
328#[doc = "Values that can be written to the field `MAEN1`"]
329pub enum MAEN1W {
330 #[doc = "All data received is transferred to the data buffer if MAEN2 is cleared."]
331 _0,
332 #[doc = "All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled."]
333 _1,
334}
335impl MAEN1W {
336 #[allow(missing_docs)]
337 #[doc(hidden)]
338 #[inline]
339 pub fn _bits(&self) -> bool {
340 match *self {
341 MAEN1W::_0 => false,
342 MAEN1W::_1 => true,
343 }
344 }
345}
346#[doc = r" Proxy"]
347pub struct _MAEN1W<'a> {
348 w: &'a mut W,
349}
350impl<'a> _MAEN1W<'a> {
351 #[doc = r" Writes `variant` to the field"]
352 #[inline]
353 pub fn variant(self, variant: MAEN1W) -> &'a mut W {
354 {
355 self.bit(variant._bits())
356 }
357 }
358 #[doc = "All data received is transferred to the data buffer if MAEN2 is cleared."]
359 #[inline]
360 pub fn _0(self) -> &'a mut W {
361 self.variant(MAEN1W::_0)
362 }
363 #[doc = "All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when C7816[ISO7816E] is set/enabled."]
364 #[inline]
365 pub fn _1(self) -> &'a mut W {
366 self.variant(MAEN1W::_1)
367 }
368 #[doc = r" Sets the field bit"]
369 pub fn set_bit(self) -> &'a mut W {
370 self.bit(true)
371 }
372 #[doc = r" Clears the field bit"]
373 pub fn clear_bit(self) -> &'a mut W {
374 self.bit(false)
375 }
376 #[doc = r" Writes raw bits to the field"]
377 #[inline]
378 pub fn bit(self, value: bool) -> &'a mut W {
379 const MASK: bool = true;
380 const OFFSET: u8 = 7;
381 self.w.bits &= !((MASK as u8) << OFFSET);
382 self.w.bits |= ((value & MASK) as u8) << OFFSET;
383 self.w
384 }
385}
386impl R {
387 #[doc = r" Value of the register as raw bits"]
388 #[inline]
389 pub fn bits(&self) -> u8 {
390 self.bits
391 }
392 #[doc = "Bits 0:4 - Baud Rate Fine Adjust"]
393 #[inline]
394 pub fn brfa(&self) -> BRFAR {
395 let bits = {
396 const MASK: u8 = 31;
397 const OFFSET: u8 = 0;
398 ((self.bits >> OFFSET) & MASK as u8) as u8
399 };
400 BRFAR { bits }
401 }
402 #[doc = "Bit 5 - 10-bit Mode select"]
403 #[inline]
404 pub fn m10(&self) -> M10R {
405 M10R::_from({
406 const MASK: bool = true;
407 const OFFSET: u8 = 5;
408 ((self.bits >> OFFSET) & MASK as u8) != 0
409 })
410 }
411 #[doc = "Bit 6 - Match Address Mode Enable 2"]
412 #[inline]
413 pub fn maen2(&self) -> MAEN2R {
414 MAEN2R::_from({
415 const MASK: bool = true;
416 const OFFSET: u8 = 6;
417 ((self.bits >> OFFSET) & MASK as u8) != 0
418 })
419 }
420 #[doc = "Bit 7 - Match Address Mode Enable 1"]
421 #[inline]
422 pub fn maen1(&self) -> MAEN1R {
423 MAEN1R::_from({
424 const MASK: bool = true;
425 const OFFSET: u8 = 7;
426 ((self.bits >> OFFSET) & MASK as u8) != 0
427 })
428 }
429}
430impl W {
431 #[doc = r" Reset value of the register"]
432 #[inline]
433 pub fn reset_value() -> W {
434 W { bits: 0 }
435 }
436 #[doc = r" Writes raw bits to the register"]
437 #[inline]
438 pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
439 self.bits = bits;
440 self
441 }
442 #[doc = "Bits 0:4 - Baud Rate Fine Adjust"]
443 #[inline]
444 pub fn brfa(&mut self) -> _BRFAW {
445 _BRFAW { w: self }
446 }
447 #[doc = "Bit 5 - 10-bit Mode select"]
448 #[inline]
449 pub fn m10(&mut self) -> _M10W {
450 _M10W { w: self }
451 }
452 #[doc = "Bit 6 - Match Address Mode Enable 2"]
453 #[inline]
454 pub fn maen2(&mut self) -> _MAEN2W {
455 _MAEN2W { w: self }
456 }
457 #[doc = "Bit 7 - Match Address Mode Enable 1"]
458 #[inline]
459 pub fn maen1(&mut self) -> _MAEN1W {
460 _MAEN1W { w: self }
461 }
462}